1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_macvlan.h> 31 #include <linux/if_bridge.h> 32 #include <linux/clocksource.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_mirred.h> 38 #include <net/udp_tunnel.h> 39 #include <net/xdp_sock.h> 40 #include "i40e_type.h" 41 #include "i40e_prototype.h" 42 #include <linux/net/intel/i40e_client.h> 43 #include <linux/avf/virtchnl.h> 44 #include "i40e_virtchnl_pf.h" 45 #include "i40e_txrx.h" 46 #include "i40e_dcb.h" 47 48 /* Useful i40e defaults */ 49 #define I40E_MAX_VEB 16 50 51 #define I40E_MAX_NUM_DESCRIPTORS 4096 52 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 53 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 54 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 55 #define I40E_MIN_NUM_DESCRIPTORS 64 56 #define I40E_MIN_MSIX 2 57 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 58 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 59 /* max 16 qps */ 60 #define i40e_default_queues_per_vmdq(pf) \ 61 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 62 #define I40E_DEFAULT_QUEUES_PER_VF 4 63 #define I40E_MAX_VF_QUEUES 16 64 #define i40e_pf_get_max_q_per_tc(pf) \ 65 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 66 #define I40E_FDIR_RING_COUNT 32 67 #define I40E_MAX_AQ_BUF_SIZE 4096 68 #define I40E_AQ_LEN 256 69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 70 #define I40E_MAX_USER_PRIORITY 8 71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 72 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 73 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 74 75 #define I40E_NVM_VERSION_LO_SHIFT 0 76 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 77 #define I40E_NVM_VERSION_HI_SHIFT 12 78 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 79 #define I40E_OEM_VER_BUILD_MASK 0xffff 80 #define I40E_OEM_VER_PATCH_MASK 0xff 81 #define I40E_OEM_VER_BUILD_SHIFT 8 82 #define I40E_OEM_VER_SHIFT 24 83 #define I40E_PHY_DEBUG_ALL \ 84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 86 87 #define I40E_OEM_EETRACK_ID 0xffffffff 88 #define I40E_OEM_GEN_SHIFT 24 89 #define I40E_OEM_SNAP_MASK 0x00ff0000 90 #define I40E_OEM_SNAP_SHIFT 16 91 #define I40E_OEM_RELEASE_MASK 0x0000ffff 92 93 #define I40E_RX_DESC(R, i) \ 94 (&(((union i40e_rx_desc *)((R)->desc))[i])) 95 #define I40E_TX_DESC(R, i) \ 96 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 97 #define I40E_TX_CTXTDESC(R, i) \ 98 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 99 #define I40E_TX_FDIRDESC(R, i) \ 100 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 101 102 /* BW rate limiting */ 103 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 104 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 105 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 106 107 /* driver state flags */ 108 enum i40e_state_t { 109 __I40E_TESTING, 110 __I40E_CONFIG_BUSY, 111 __I40E_CONFIG_DONE, 112 __I40E_DOWN, 113 __I40E_SERVICE_SCHED, 114 __I40E_ADMINQ_EVENT_PENDING, 115 __I40E_MDD_EVENT_PENDING, 116 __I40E_VFLR_EVENT_PENDING, 117 __I40E_RESET_RECOVERY_PENDING, 118 __I40E_TIMEOUT_RECOVERY_PENDING, 119 __I40E_MISC_IRQ_REQUESTED, 120 __I40E_RESET_INTR_RECEIVED, 121 __I40E_REINIT_REQUESTED, 122 __I40E_PF_RESET_REQUESTED, 123 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 124 __I40E_CORE_RESET_REQUESTED, 125 __I40E_GLOBAL_RESET_REQUESTED, 126 __I40E_EMP_RESET_INTR_RECEIVED, 127 __I40E_SUSPENDED, 128 __I40E_PTP_TX_IN_PROGRESS, 129 __I40E_BAD_EEPROM, 130 __I40E_DOWN_REQUESTED, 131 __I40E_FD_FLUSH_REQUESTED, 132 __I40E_FD_ATR_AUTO_DISABLED, 133 __I40E_FD_SB_AUTO_DISABLED, 134 __I40E_RESET_FAILED, 135 __I40E_PORT_SUSPENDED, 136 __I40E_VF_DISABLE, 137 __I40E_MACVLAN_SYNC_PENDING, 138 __I40E_TEMP_LINK_POLLING, 139 __I40E_CLIENT_SERVICE_REQUESTED, 140 __I40E_CLIENT_L2_CHANGE, 141 __I40E_CLIENT_RESET, 142 __I40E_VIRTCHNL_OP_PENDING, 143 __I40E_RECOVERY_MODE, 144 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 145 /* This must be last as it determines the size of the BITMAP */ 146 __I40E_STATE_SIZE__, 147 }; 148 149 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 150 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 151 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 152 153 /* VSI state flags */ 154 enum i40e_vsi_state_t { 155 __I40E_VSI_DOWN, 156 __I40E_VSI_NEEDS_RESTART, 157 __I40E_VSI_SYNCING_FILTERS, 158 __I40E_VSI_OVERFLOW_PROMISC, 159 __I40E_VSI_REINIT_REQUESTED, 160 __I40E_VSI_DOWN_REQUESTED, 161 /* This must be last as it determines the size of the BITMAP */ 162 __I40E_VSI_STATE_SIZE__, 163 }; 164 165 enum i40e_interrupt_policy { 166 I40E_INTERRUPT_BEST_CASE, 167 I40E_INTERRUPT_MEDIUM, 168 I40E_INTERRUPT_LOWEST 169 }; 170 171 struct i40e_lump_tracking { 172 u16 num_entries; 173 u16 search_hint; 174 u16 list[0]; 175 #define I40E_PILE_VALID_BIT 0x8000 176 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 177 }; 178 179 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 180 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 181 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 182 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 183 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 184 185 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 186 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 187 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 188 189 enum i40e_fd_stat_idx { 190 I40E_FD_STAT_ATR, 191 I40E_FD_STAT_SB, 192 I40E_FD_STAT_ATR_TUNNEL, 193 I40E_FD_STAT_PF_COUNT 194 }; 195 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 196 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 197 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 198 #define I40E_FD_SB_STAT_IDX(pf_id) \ 199 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 200 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 202 203 /* The following structure contains the data parsed from the user-defined 204 * field of the ethtool_rx_flow_spec structure. 205 */ 206 struct i40e_rx_flow_userdef { 207 bool flex_filter; 208 u16 flex_word; 209 u16 flex_offset; 210 }; 211 212 struct i40e_fdir_filter { 213 struct hlist_node fdir_node; 214 /* filter ipnut set */ 215 u8 flow_type; 216 u8 ip4_proto; 217 /* TX packet view of src and dst */ 218 __be32 dst_ip; 219 __be32 src_ip; 220 __be16 src_port; 221 __be16 dst_port; 222 __be32 sctp_v_tag; 223 224 /* Flexible data to match within the packet payload */ 225 __be16 flex_word; 226 u16 flex_offset; 227 bool flex_filter; 228 229 /* filter control */ 230 u16 q_index; 231 u8 flex_off; 232 u8 pctype; 233 u16 dest_vsi; 234 u8 dest_ctl; 235 u8 fd_status; 236 u16 cnt_index; 237 u32 fd_id; 238 }; 239 240 #define I40E_CLOUD_FIELD_OMAC BIT(0) 241 #define I40E_CLOUD_FIELD_IMAC BIT(1) 242 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 243 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 244 #define I40E_CLOUD_FIELD_IIP BIT(4) 245 246 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 247 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 248 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 249 I40E_CLOUD_FIELD_IVLAN) 250 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 251 I40E_CLOUD_FIELD_TEN_ID) 252 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 253 I40E_CLOUD_FIELD_IMAC | \ 254 I40E_CLOUD_FIELD_TEN_ID) 255 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_IVLAN | \ 257 I40E_CLOUD_FIELD_TEN_ID) 258 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 259 260 struct i40e_cloud_filter { 261 struct hlist_node cloud_node; 262 unsigned long cookie; 263 /* cloud filter input set follows */ 264 u8 dst_mac[ETH_ALEN]; 265 u8 src_mac[ETH_ALEN]; 266 __be16 vlan_id; 267 u16 seid; /* filter control */ 268 __be16 dst_port; 269 __be16 src_port; 270 u32 tenant_id; 271 union { 272 struct { 273 struct in_addr dst_ip; 274 struct in_addr src_ip; 275 } v4; 276 struct { 277 struct in6_addr dst_ip6; 278 struct in6_addr src_ip6; 279 } v6; 280 } ip; 281 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 282 #define src_ipv6 ip.v6.src_ip6.s6_addr32 283 #define dst_ipv4 ip.v4.dst_ip.s_addr 284 #define src_ipv4 ip.v4.src_ip.s_addr 285 u16 n_proto; /* Ethernet Protocol */ 286 u8 ip_proto; /* IPPROTO value */ 287 u8 flags; 288 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 289 u8 tunnel_type; 290 }; 291 292 /* DCB per TC information data structure */ 293 struct i40e_tc_info { 294 u16 qoffset; /* Queue offset from base queue */ 295 u16 qcount; /* Total Queues */ 296 u8 netdev_tc; /* Netdev TC index if netdev associated */ 297 }; 298 299 /* TC configuration data structure */ 300 struct i40e_tc_configuration { 301 u8 numtc; /* Total number of enabled TCs */ 302 u8 enabled_tc; /* TC map */ 303 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 304 }; 305 306 #define I40E_UDP_PORT_INDEX_UNUSED 255 307 struct i40e_udp_port_config { 308 /* AdminQ command interface expects port number in Host byte order */ 309 u16 port; 310 u8 type; 311 u8 filter_index; 312 }; 313 314 #define I40_DDP_FLASH_REGION 100 315 #define I40E_PROFILE_INFO_SIZE 48 316 #define I40E_MAX_PROFILE_NUM 16 317 #define I40E_PROFILE_LIST_SIZE \ 318 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 319 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 320 #define I40E_DDP_PROFILE_NAME_MAX 64 321 322 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 323 bool is_add); 324 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 325 326 struct i40e_ddp_profile_list { 327 u32 p_count; 328 struct i40e_profile_info p_info[]; 329 }; 330 331 struct i40e_ddp_old_profile_list { 332 struct list_head list; 333 size_t old_ddp_size; 334 u8 old_ddp_buf[]; 335 }; 336 337 /* macros related to FLX_PIT */ 338 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 339 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 340 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 341 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 342 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 343 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 344 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 345 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 346 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 347 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 348 I40E_FLEX_SET_FSIZE(fsize) | \ 349 I40E_FLEX_SET_SRC_WORD(src)) 350 351 352 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 353 354 /* macros related to GLQF_ORT */ 355 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 356 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 357 I40E_GLQF_ORT_PIT_INDX_MASK) 358 359 #define I40E_ORT_SET_COUNT(count) (((count) << \ 360 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 361 I40E_GLQF_ORT_FIELD_CNT_MASK) 362 363 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 364 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 365 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 366 367 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 368 I40E_ORT_SET_COUNT(count) | \ 369 I40E_ORT_SET_PAYLOAD(payload)) 370 371 #define I40E_L3_GLQF_ORT_IDX 34 372 #define I40E_L4_GLQF_ORT_IDX 35 373 374 /* Flex PIT register index */ 375 #define I40E_FLEX_PIT_IDX_START_L3 3 376 #define I40E_FLEX_PIT_IDX_START_L4 6 377 378 #define I40E_FLEX_PIT_TABLE_SIZE 3 379 380 #define I40E_FLEX_DEST_UNUSED 63 381 382 #define I40E_FLEX_INDEX_ENTRIES 8 383 384 /* Flex MASK to disable all flexible entries */ 385 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 386 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 387 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 388 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 389 390 struct i40e_flex_pit { 391 struct list_head list; 392 u16 src_offset; 393 u8 pit_index; 394 }; 395 396 struct i40e_fwd_adapter { 397 struct net_device *netdev; 398 int bit_no; 399 }; 400 401 struct i40e_channel { 402 struct list_head list; 403 bool initialized; 404 u8 type; 405 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 406 u16 stat_counter_idx; 407 u16 base_queue; 408 u16 num_queue_pairs; /* Requested by user */ 409 u16 seid; 410 411 u8 enabled_tc; 412 struct i40e_aqc_vsi_properties_data info; 413 414 u64 max_tx_rate; 415 struct i40e_fwd_adapter *fwd; 416 417 /* track this channel belongs to which VSI */ 418 struct i40e_vsi *parent_vsi; 419 }; 420 421 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 422 { 423 return !!ch->fwd; 424 } 425 426 static inline u8 *i40e_channel_mac(struct i40e_channel *ch) 427 { 428 if (i40e_is_channel_macvlan(ch)) 429 return ch->fwd->netdev->dev_addr; 430 else 431 return NULL; 432 } 433 434 /* struct that defines the Ethernet device */ 435 struct i40e_pf { 436 struct pci_dev *pdev; 437 struct i40e_hw hw; 438 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 439 struct msix_entry *msix_entries; 440 bool fc_autoneg_status; 441 442 u16 eeprom_version; 443 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 444 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 445 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 446 u16 num_req_vfs; /* num VFs requested for this PF */ 447 u16 num_vf_qps; /* num queue pairs per VF */ 448 u16 num_lan_qps; /* num lan queues this PF has set up */ 449 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 450 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 451 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 452 int iwarp_base_vector; 453 int queues_left; /* queues left unclaimed */ 454 u16 alloc_rss_size; /* allocated RSS queues */ 455 u16 rss_size_max; /* HW defined max RSS queues */ 456 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 457 u16 num_alloc_vsi; /* num VSIs this driver supports */ 458 u8 atr_sample_rate; 459 bool wol_en; 460 461 struct hlist_head fdir_filter_list; 462 u16 fdir_pf_active_filters; 463 unsigned long fd_flush_timestamp; 464 u32 fd_flush_cnt; 465 u32 fd_add_err; 466 u32 fd_atr_cnt; 467 468 /* Book-keeping of side-band filter count per flow-type. 469 * This is used to detect and handle input set changes for 470 * respective flow-type. 471 */ 472 u16 fd_tcp4_filter_cnt; 473 u16 fd_udp4_filter_cnt; 474 u16 fd_sctp4_filter_cnt; 475 u16 fd_ip4_filter_cnt; 476 477 /* Flexible filter table values that need to be programmed into 478 * hardware, which expects L3 and L4 to be programmed separately. We 479 * need to ensure that the values are in ascended order and don't have 480 * duplicates, so we track each L3 and L4 values in separate lists. 481 */ 482 struct list_head l3_flex_pit_list; 483 struct list_head l4_flex_pit_list; 484 485 struct udp_tunnel_nic_shared udp_tunnel_shared; 486 struct udp_tunnel_nic_info udp_tunnel_nic; 487 488 struct hlist_head cloud_filter_list; 489 u16 num_cloud_filters; 490 491 enum i40e_interrupt_policy int_policy; 492 u16 rx_itr_default; 493 u16 tx_itr_default; 494 u32 msg_enable; 495 char int_name[I40E_INT_NAME_STR_LEN]; 496 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 497 unsigned long service_timer_period; 498 unsigned long service_timer_previous; 499 struct timer_list service_timer; 500 struct work_struct service_task; 501 502 u32 hw_features; 503 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 504 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 505 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 506 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 507 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 508 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 509 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 510 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 511 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 512 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 513 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 514 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 515 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 516 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 517 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 518 #define I40E_HW_STOP_FW_LLDP BIT(16) 519 #define I40E_HW_PORT_ID_VALID BIT(17) 520 #define I40E_HW_RESTART_AUTONEG BIT(18) 521 522 u32 flags; 523 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 524 #define I40E_FLAG_MSI_ENABLED BIT(1) 525 #define I40E_FLAG_MSIX_ENABLED BIT(2) 526 #define I40E_FLAG_RSS_ENABLED BIT(3) 527 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 528 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 529 #define I40E_FLAG_DCB_CAPABLE BIT(6) 530 #define I40E_FLAG_DCB_ENABLED BIT(7) 531 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 532 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 533 #define I40E_FLAG_MFP_ENABLED BIT(10) 534 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 535 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 536 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 537 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 538 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 539 #define I40E_FLAG_LEGACY_RX BIT(16) 540 #define I40E_FLAG_PTP BIT(17) 541 #define I40E_FLAG_IWARP_ENABLED BIT(18) 542 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 543 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 544 #define I40E_FLAG_TC_MQPRIO BIT(21) 545 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 546 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 547 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 548 #define I40E_FLAG_RS_FEC BIT(25) 549 #define I40E_FLAG_BASE_R_FEC BIT(26) 550 /* TOTAL_PORT_SHUTDOWN 551 * Allows to physically disable the link on the NIC's port. 552 * If enabled, (after link down request from the OS) 553 * no link, traffic or led activity is possible on that port. 554 * 555 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 556 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 557 * and cannot be disabled by system admin at that time. 558 * The functionalities are exclusive in terms of configuration, but they also 559 * have similar behavior (allowing to disable physical link of the port), 560 * with following differences: 561 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 562 * supported by whole family of 7xx Intel Ethernet Controllers 563 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 564 * only if motherboard's BIOS and NIC's FW has support of it 565 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 566 * by sending phy_type=0 to NIC's FW 567 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 568 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 569 * in abilities field of i40e_aq_set_phy_config structure 570 */ 571 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 572 573 struct i40e_client_instance *cinst; 574 bool stat_offsets_loaded; 575 struct i40e_hw_port_stats stats; 576 struct i40e_hw_port_stats stats_offsets; 577 u32 tx_timeout_count; 578 u32 tx_timeout_recovery_level; 579 unsigned long tx_timeout_last_recovery; 580 u32 tx_sluggish_count; 581 u32 hw_csum_rx_error; 582 u32 led_status; 583 u16 corer_count; /* Core reset count */ 584 u16 globr_count; /* Global reset count */ 585 u16 empr_count; /* EMP reset count */ 586 u16 pfr_count; /* PF reset count */ 587 u16 sw_int_count; /* SW interrupt count */ 588 589 struct mutex switch_mutex; 590 u16 lan_vsi; /* our default LAN VSI */ 591 u16 lan_veb; /* initial relay, if exists */ 592 #define I40E_NO_VEB 0xffff 593 #define I40E_NO_VSI 0xffff 594 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 595 struct i40e_vsi **vsi; 596 struct i40e_veb *veb[I40E_MAX_VEB]; 597 598 struct i40e_lump_tracking *qp_pile; 599 struct i40e_lump_tracking *irq_pile; 600 601 /* switch config info */ 602 u16 pf_seid; 603 u16 main_vsi_seid; 604 u16 mac_seid; 605 struct kobject *switch_kobj; 606 #ifdef CONFIG_DEBUG_FS 607 struct dentry *i40e_dbg_pf; 608 #endif /* CONFIG_DEBUG_FS */ 609 bool cur_promisc; 610 611 u16 instance; /* A unique number per i40e_pf instance in the system */ 612 613 /* sr-iov config info */ 614 struct i40e_vf *vf; 615 int num_alloc_vfs; /* actual number of VFs allocated */ 616 u32 vf_aq_requests; 617 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 618 619 /* DCBx/DCBNL capability for PF that indicates 620 * whether DCBx is managed by firmware or host 621 * based agent (LLDPAD). Also, indicates what 622 * flavor of DCBx protocol (IEEE/CEE) is supported 623 * by the device. For now we're supporting IEEE 624 * mode only. 625 */ 626 u16 dcbx_cap; 627 628 struct i40e_filter_control_settings filter_settings; 629 630 struct ptp_clock *ptp_clock; 631 struct ptp_clock_info ptp_caps; 632 struct sk_buff *ptp_tx_skb; 633 unsigned long ptp_tx_start; 634 struct hwtstamp_config tstamp_config; 635 struct timespec64 ptp_prev_hw_time; 636 ktime_t ptp_reset_start; 637 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 638 u32 ptp_adj_mult; 639 u32 tx_hwtstamp_timeouts; 640 u32 tx_hwtstamp_skipped; 641 u32 rx_hwtstamp_cleared; 642 u32 latch_event_flags; 643 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 644 unsigned long latch_events[4]; 645 bool ptp_tx; 646 bool ptp_rx; 647 u16 rss_table_size; /* HW RSS table size */ 648 u32 max_bw; 649 u32 min_bw; 650 651 u32 ioremap_len; 652 u32 fd_inv; 653 u16 phy_led_val; 654 655 u16 override_q_count; 656 u16 last_sw_conf_flags; 657 u16 last_sw_conf_valid_flags; 658 /* List to keep previous DDP profiles to be rolled back in the future */ 659 struct list_head ddp_old_prof; 660 }; 661 662 /** 663 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 664 * @macaddr: the MAC Address as the base key 665 * 666 * Simply copies the address and returns it as a u64 for hashing 667 **/ 668 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 669 { 670 u64 key = 0; 671 672 ether_addr_copy((u8 *)&key, macaddr); 673 return key; 674 } 675 676 enum i40e_filter_state { 677 I40E_FILTER_INVALID = 0, /* Invalid state */ 678 I40E_FILTER_NEW, /* New, not sent to FW yet */ 679 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 680 I40E_FILTER_FAILED, /* Rejected by FW */ 681 I40E_FILTER_REMOVE, /* To be removed */ 682 /* There is no 'removed' state; the filter struct is freed */ 683 }; 684 struct i40e_mac_filter { 685 struct hlist_node hlist; 686 u8 macaddr[ETH_ALEN]; 687 #define I40E_VLAN_ANY -1 688 s16 vlan; 689 enum i40e_filter_state state; 690 }; 691 692 /* Wrapper structure to keep track of filters while we are preparing to send 693 * firmware commands. We cannot send firmware commands while holding a 694 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 695 * a separate structure, which will track the state change and update the real 696 * filter while under lock. We can't simply hold the filters in a separate 697 * list, as this opens a window for a race condition when adding new MAC 698 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 699 */ 700 struct i40e_new_mac_filter { 701 struct hlist_node hlist; 702 struct i40e_mac_filter *f; 703 704 /* Track future changes to state separately */ 705 enum i40e_filter_state state; 706 }; 707 708 struct i40e_veb { 709 struct i40e_pf *pf; 710 u16 idx; 711 u16 veb_idx; /* index of VEB parent */ 712 u16 seid; 713 u16 uplink_seid; 714 u16 stats_idx; /* index of VEB parent */ 715 u8 enabled_tc; 716 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 717 u16 flags; 718 u16 bw_limit; 719 u8 bw_max_quanta; 720 bool is_abs_credits; 721 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 722 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 723 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 724 struct kobject *kobj; 725 bool stat_offsets_loaded; 726 struct i40e_eth_stats stats; 727 struct i40e_eth_stats stats_offsets; 728 struct i40e_veb_tc_stats tc_stats; 729 struct i40e_veb_tc_stats tc_stats_offsets; 730 }; 731 732 /* struct that defines a VSI, associated with a dev */ 733 struct i40e_vsi { 734 struct net_device *netdev; 735 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 736 bool netdev_registered; 737 bool stat_offsets_loaded; 738 739 u32 current_netdev_flags; 740 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 741 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 742 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 743 unsigned long flags; 744 745 /* Per VSI lock to protect elements/hash (MAC filter) */ 746 spinlock_t mac_filter_hash_lock; 747 /* Fixed size hash table with 2^8 buckets for MAC filters */ 748 DECLARE_HASHTABLE(mac_filter_hash, 8); 749 bool has_vlan_filter; 750 751 /* VSI stats */ 752 struct rtnl_link_stats64 net_stats; 753 struct rtnl_link_stats64 net_stats_offsets; 754 struct i40e_eth_stats eth_stats; 755 struct i40e_eth_stats eth_stats_offsets; 756 u32 tx_restart; 757 u32 tx_busy; 758 u64 tx_linearize; 759 u64 tx_force_wb; 760 u32 rx_buf_failed; 761 u32 rx_page_failed; 762 763 /* These are containers of ring pointers, allocated at run-time */ 764 struct i40e_ring **rx_rings; 765 struct i40e_ring **tx_rings; 766 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 767 768 u32 active_filters; 769 u32 promisc_threshold; 770 771 u16 work_limit; 772 u16 int_rate_limit; /* value in usecs */ 773 774 u16 rss_table_size; /* HW RSS table size */ 775 u16 rss_size; /* Allocated RSS queues */ 776 u8 *rss_hkey_user; /* User configured hash keys */ 777 u8 *rss_lut_user; /* User configured lookup table entries */ 778 779 780 u16 max_frame; 781 u16 rx_buf_len; 782 783 struct bpf_prog *xdp_prog; 784 785 /* List of q_vectors allocated to this VSI */ 786 struct i40e_q_vector **q_vectors; 787 int num_q_vectors; 788 int base_vector; 789 bool irqs_ready; 790 791 u16 seid; /* HW index of this VSI (absolute index) */ 792 u16 id; /* VSI number */ 793 u16 uplink_seid; 794 795 u16 base_queue; /* vsi's first queue in hw array */ 796 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 797 u16 req_queue_pairs; /* User requested queue pairs */ 798 u16 num_queue_pairs; /* Used tx and rx pairs */ 799 u16 num_tx_desc; 800 u16 num_rx_desc; 801 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 802 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 803 804 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 805 struct i40e_tc_configuration tc_config; 806 struct i40e_aqc_vsi_properties_data info; 807 808 /* VSI BW limit (absolute across all TCs) */ 809 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 810 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 811 812 /* Relative TC credits across VSIs */ 813 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 814 /* TC BW limit credits within VSI */ 815 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 816 /* TC BW limit max quanta within VSI */ 817 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 818 819 struct i40e_pf *back; /* Backreference to associated PF */ 820 u16 idx; /* index in pf->vsi[] */ 821 u16 veb_idx; /* index of VEB parent */ 822 struct kobject *kobj; /* sysfs object */ 823 bool current_isup; /* Sync 'link up' logging */ 824 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 825 826 /* channel specific fields */ 827 u16 cnt_q_avail; /* num of queues available for channel usage */ 828 u16 orig_rss_size; 829 u16 current_rss_size; 830 bool reconfig_rss; 831 832 u16 next_base_queue; /* next queue to be used for channel setup */ 833 834 struct list_head ch_list; 835 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 836 837 /* macvlan fields */ 838 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 839 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 840 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 841 struct list_head macvlan_list; 842 int macvlan_cnt; 843 844 void *priv; /* client driver data reference. */ 845 846 /* VSI specific handlers */ 847 irqreturn_t (*irq_handler)(int irq, void *data); 848 849 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 850 } ____cacheline_internodealigned_in_smp; 851 852 struct i40e_netdev_priv { 853 struct i40e_vsi *vsi; 854 }; 855 856 /* struct that defines an interrupt vector */ 857 struct i40e_q_vector { 858 struct i40e_vsi *vsi; 859 860 u16 v_idx; /* index in the vsi->q_vector array. */ 861 u16 reg_idx; /* register index of the interrupt */ 862 863 struct napi_struct napi; 864 865 struct i40e_ring_container rx; 866 struct i40e_ring_container tx; 867 868 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 869 u8 num_ringpairs; /* total number of ring pairs in vector */ 870 871 cpumask_t affinity_mask; 872 struct irq_affinity_notify affinity_notify; 873 874 struct rcu_head rcu; /* to avoid race with update stats on free */ 875 char name[I40E_INT_NAME_STR_LEN]; 876 bool arm_wb_state; 877 } ____cacheline_internodealigned_in_smp; 878 879 /* lan device */ 880 struct i40e_device { 881 struct list_head list; 882 struct i40e_pf *pf; 883 }; 884 885 /** 886 * i40e_nvm_version_str - format the NVM version strings 887 * @hw: ptr to the hardware info 888 **/ 889 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 890 { 891 static char buf[32]; 892 u32 full_ver; 893 894 full_ver = hw->nvm.oem_ver; 895 896 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 897 u8 gen, snap; 898 u16 release; 899 900 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 901 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 902 I40E_OEM_SNAP_SHIFT); 903 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 904 905 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 906 } else { 907 u8 ver, patch; 908 u16 build; 909 910 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 911 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 912 I40E_OEM_VER_BUILD_MASK); 913 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 914 915 snprintf(buf, sizeof(buf), 916 "%x.%02x 0x%x %d.%d.%d", 917 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 918 I40E_NVM_VERSION_HI_SHIFT, 919 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 920 I40E_NVM_VERSION_LO_SHIFT, 921 hw->nvm.eetrack, ver, build, patch); 922 } 923 924 return buf; 925 } 926 927 /** 928 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 929 * @netdev: the corresponding netdev 930 * 931 * Return the PF struct for the given netdev 932 **/ 933 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 934 { 935 struct i40e_netdev_priv *np = netdev_priv(netdev); 936 struct i40e_vsi *vsi = np->vsi; 937 938 return vsi->back; 939 } 940 941 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 942 irqreturn_t (*irq_handler)(int, void *)) 943 { 944 vsi->irq_handler = irq_handler; 945 } 946 947 /** 948 * i40e_get_fd_cnt_all - get the total FD filter space available 949 * @pf: pointer to the PF struct 950 **/ 951 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 952 { 953 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 954 } 955 956 /** 957 * i40e_read_fd_input_set - reads value of flow director input set register 958 * @pf: pointer to the PF struct 959 * @addr: register addr 960 * 961 * This function reads value of flow director input set register 962 * specified by 'addr' (which is specific to flow-type) 963 **/ 964 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 965 { 966 u64 val; 967 968 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 969 val <<= 32; 970 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 971 972 return val; 973 } 974 975 /** 976 * i40e_write_fd_input_set - writes value into flow director input set register 977 * @pf: pointer to the PF struct 978 * @addr: register addr 979 * @val: value to be written 980 * 981 * This function writes specified value to the register specified by 'addr'. 982 * This register is input set register based on flow-type. 983 **/ 984 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 985 u16 addr, u64 val) 986 { 987 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 988 (u32)(val >> 32)); 989 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 990 (u32)(val & 0xFFFFFFFFULL)); 991 } 992 993 /* needed by i40e_ethtool.c */ 994 int i40e_up(struct i40e_vsi *vsi); 995 void i40e_down(struct i40e_vsi *vsi); 996 extern const char i40e_driver_name[]; 997 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 998 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 999 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1000 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1001 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1002 u16 rss_table_size, u16 rss_size); 1003 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1004 /** 1005 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1006 * @pf: PF to search for VSI 1007 * @type: Value indicating type of VSI we are looking for 1008 **/ 1009 static inline struct i40e_vsi * 1010 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1011 { 1012 int i; 1013 1014 for (i = 0; i < pf->num_alloc_vsi; i++) { 1015 struct i40e_vsi *vsi = pf->vsi[i]; 1016 1017 if (vsi && vsi->type == type) 1018 return vsi; 1019 } 1020 1021 return NULL; 1022 } 1023 void i40e_update_stats(struct i40e_vsi *vsi); 1024 void i40e_update_veb_stats(struct i40e_veb *veb); 1025 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1026 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1027 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1028 bool printconfig); 1029 1030 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1031 struct i40e_fdir_filter *input, bool add); 1032 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1033 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1034 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1035 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1036 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1037 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1038 void i40e_set_ethtool_ops(struct net_device *netdev); 1039 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1040 const u8 *macaddr, s16 vlan); 1041 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1042 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1043 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1044 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1045 u16 uplink, u32 param1); 1046 int i40e_vsi_release(struct i40e_vsi *vsi); 1047 void i40e_service_event_schedule(struct i40e_pf *pf); 1048 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1049 u8 *msg, u16 len); 1050 1051 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1052 bool enable); 1053 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1054 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1055 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1056 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1057 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1058 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1059 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1060 u16 downlink_seid, u8 enabled_tc); 1061 void i40e_veb_release(struct i40e_veb *veb); 1062 1063 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1064 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1065 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1066 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1067 void i40e_pf_reset_stats(struct i40e_pf *pf); 1068 #ifdef CONFIG_DEBUG_FS 1069 void i40e_dbg_pf_init(struct i40e_pf *pf); 1070 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1071 void i40e_dbg_init(void); 1072 void i40e_dbg_exit(void); 1073 #else 1074 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1075 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1076 static inline void i40e_dbg_init(void) {} 1077 static inline void i40e_dbg_exit(void) {} 1078 #endif /* CONFIG_DEBUG_FS*/ 1079 /* needed by client drivers */ 1080 int i40e_lan_add_device(struct i40e_pf *pf); 1081 int i40e_lan_del_device(struct i40e_pf *pf); 1082 void i40e_client_subtask(struct i40e_pf *pf); 1083 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1084 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1085 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1086 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1087 void i40e_client_update_msix_info(struct i40e_pf *pf); 1088 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1089 /** 1090 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1091 * @vsi: pointer to a vsi 1092 * @vector: enable a particular Hw Interrupt vector, without base_vector 1093 **/ 1094 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1095 { 1096 struct i40e_pf *pf = vsi->back; 1097 struct i40e_hw *hw = &pf->hw; 1098 u32 val; 1099 1100 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1101 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1102 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1103 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1104 /* skip the flush */ 1105 } 1106 1107 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1108 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1109 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1110 int i40e_open(struct net_device *netdev); 1111 int i40e_close(struct net_device *netdev); 1112 int i40e_vsi_open(struct i40e_vsi *vsi); 1113 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1114 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1115 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1116 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1117 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1118 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1119 const u8 *macaddr); 1120 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1121 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1122 int i40e_count_filters(struct i40e_vsi *vsi); 1123 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1124 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1125 #ifdef CONFIG_I40E_DCB 1126 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1127 struct i40e_dcbx_config *old_cfg, 1128 struct i40e_dcbx_config *new_cfg); 1129 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1130 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1131 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1132 struct i40e_dcbx_config *old_cfg, 1133 struct i40e_dcbx_config *new_cfg); 1134 #endif /* CONFIG_I40E_DCB */ 1135 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1136 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1137 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1138 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1139 void i40e_ptp_set_increment(struct i40e_pf *pf); 1140 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1141 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1142 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1143 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1144 void i40e_ptp_init(struct i40e_pf *pf); 1145 void i40e_ptp_stop(struct i40e_pf *pf); 1146 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1147 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1148 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1149 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1150 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1151 1152 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1153 1154 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1155 { 1156 return !!READ_ONCE(vsi->xdp_prog); 1157 } 1158 1159 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1160 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1161 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1162 struct i40e_cloud_filter *filter, 1163 bool add); 1164 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1165 struct i40e_cloud_filter *filter, 1166 bool add); 1167 #endif /* _I40E_H_ */ 1168