1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_H_ 28 #define _I40E_H_ 29 30 #include <net/tcp.h> 31 #include <net/udp.h> 32 #include <linux/types.h> 33 #include <linux/errno.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/aer.h> 37 #include <linux/netdevice.h> 38 #include <linux/ioport.h> 39 #include <linux/iommu.h> 40 #include <linux/slab.h> 41 #include <linux/list.h> 42 #include <linux/hashtable.h> 43 #include <linux/string.h> 44 #include <linux/in.h> 45 #include <linux/ip.h> 46 #include <linux/sctp.h> 47 #include <linux/pkt_sched.h> 48 #include <linux/ipv6.h> 49 #include <net/checksum.h> 50 #include <net/ip6_checksum.h> 51 #include <linux/ethtool.h> 52 #include <linux/if_vlan.h> 53 #include <linux/if_bridge.h> 54 #include <linux/clocksource.h> 55 #include <linux/net_tstamp.h> 56 #include <linux/ptp_clock_kernel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include "i40e_type.h" 61 #include "i40e_prototype.h" 62 #include "i40e_client.h" 63 #include <linux/avf/virtchnl.h> 64 #include "i40e_virtchnl_pf.h" 65 #include "i40e_txrx.h" 66 #include "i40e_dcb.h" 67 68 /* Useful i40e defaults */ 69 #define I40E_MAX_VEB 16 70 71 #define I40E_MAX_NUM_DESCRIPTORS 4096 72 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 73 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 74 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 75 #define I40E_MIN_NUM_DESCRIPTORS 64 76 #define I40E_MIN_MSIX 2 77 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 78 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 79 /* max 16 qps */ 80 #define i40e_default_queues_per_vmdq(pf) \ 81 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 82 #define I40E_DEFAULT_QUEUES_PER_VF 4 83 #define I40E_MAX_VF_QUEUES 16 84 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 85 #define i40e_pf_get_max_q_per_tc(pf) \ 86 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 87 #define I40E_FDIR_RING 0 88 #define I40E_FDIR_RING_COUNT 32 89 #define I40E_MAX_AQ_BUF_SIZE 4096 90 #define I40E_AQ_LEN 256 91 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 92 #define I40E_MAX_USER_PRIORITY 8 93 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 94 #define I40E_DEFAULT_MSG_ENABLE 4 95 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 96 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 97 98 #define I40E_NVM_VERSION_LO_SHIFT 0 99 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 100 #define I40E_NVM_VERSION_HI_SHIFT 12 101 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 102 #define I40E_OEM_VER_BUILD_MASK 0xffff 103 #define I40E_OEM_VER_PATCH_MASK 0xff 104 #define I40E_OEM_VER_BUILD_SHIFT 8 105 #define I40E_OEM_VER_SHIFT 24 106 #define I40E_PHY_DEBUG_ALL \ 107 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 108 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 109 110 #define I40E_OEM_EETRACK_ID 0xffffffff 111 #define I40E_OEM_GEN_SHIFT 24 112 #define I40E_OEM_SNAP_MASK 0x00ff0000 113 #define I40E_OEM_SNAP_SHIFT 16 114 #define I40E_OEM_RELEASE_MASK 0x0000ffff 115 116 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 117 #define I40E_CURRENT_NVM_VERSION_HI 0x2 118 #define I40E_CURRENT_NVM_VERSION_LO 0x40 119 120 #define I40E_RX_DESC(R, i) \ 121 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 122 #define I40E_TX_DESC(R, i) \ 123 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 124 #define I40E_TX_CTXTDESC(R, i) \ 125 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 126 #define I40E_TX_FDIRDESC(R, i) \ 127 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 128 129 /* default to trying for four seconds */ 130 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 131 132 /* BW rate limiting */ 133 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 134 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 135 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 136 137 /* driver state flags */ 138 enum i40e_state_t { 139 __I40E_TESTING, 140 __I40E_CONFIG_BUSY, 141 __I40E_CONFIG_DONE, 142 __I40E_DOWN, 143 __I40E_SERVICE_SCHED, 144 __I40E_ADMINQ_EVENT_PENDING, 145 __I40E_MDD_EVENT_PENDING, 146 __I40E_VFLR_EVENT_PENDING, 147 __I40E_RESET_RECOVERY_PENDING, 148 __I40E_MISC_IRQ_REQUESTED, 149 __I40E_RESET_INTR_RECEIVED, 150 __I40E_REINIT_REQUESTED, 151 __I40E_PF_RESET_REQUESTED, 152 __I40E_CORE_RESET_REQUESTED, 153 __I40E_GLOBAL_RESET_REQUESTED, 154 __I40E_EMP_RESET_REQUESTED, 155 __I40E_EMP_RESET_INTR_RECEIVED, 156 __I40E_SUSPENDED, 157 __I40E_PTP_TX_IN_PROGRESS, 158 __I40E_BAD_EEPROM, 159 __I40E_DOWN_REQUESTED, 160 __I40E_FD_FLUSH_REQUESTED, 161 __I40E_RESET_FAILED, 162 __I40E_PORT_SUSPENDED, 163 __I40E_VF_DISABLE, 164 /* This must be last as it determines the size of the BITMAP */ 165 __I40E_STATE_SIZE__, 166 }; 167 168 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 169 170 /* VSI state flags */ 171 enum i40e_vsi_state_t { 172 __I40E_VSI_DOWN, 173 __I40E_VSI_NEEDS_RESTART, 174 __I40E_VSI_SYNCING_FILTERS, 175 __I40E_VSI_OVERFLOW_PROMISC, 176 __I40E_VSI_REINIT_REQUESTED, 177 __I40E_VSI_DOWN_REQUESTED, 178 /* This must be last as it determines the size of the BITMAP */ 179 __I40E_VSI_STATE_SIZE__, 180 }; 181 182 enum i40e_interrupt_policy { 183 I40E_INTERRUPT_BEST_CASE, 184 I40E_INTERRUPT_MEDIUM, 185 I40E_INTERRUPT_LOWEST 186 }; 187 188 struct i40e_lump_tracking { 189 u16 num_entries; 190 u16 search_hint; 191 u16 list[0]; 192 #define I40E_PILE_VALID_BIT 0x8000 193 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 194 }; 195 196 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 197 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 198 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 199 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 200 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 201 202 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 203 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 204 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 205 206 enum i40e_fd_stat_idx { 207 I40E_FD_STAT_ATR, 208 I40E_FD_STAT_SB, 209 I40E_FD_STAT_ATR_TUNNEL, 210 I40E_FD_STAT_PF_COUNT 211 }; 212 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 213 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 214 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 215 #define I40E_FD_SB_STAT_IDX(pf_id) \ 216 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 217 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 218 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 219 220 /* The following structure contains the data parsed from the user-defined 221 * field of the ethtool_rx_flow_spec structure. 222 */ 223 struct i40e_rx_flow_userdef { 224 bool flex_filter; 225 u16 flex_word; 226 u16 flex_offset; 227 }; 228 229 struct i40e_fdir_filter { 230 struct hlist_node fdir_node; 231 /* filter ipnut set */ 232 u8 flow_type; 233 u8 ip4_proto; 234 /* TX packet view of src and dst */ 235 __be32 dst_ip; 236 __be32 src_ip; 237 __be16 src_port; 238 __be16 dst_port; 239 __be32 sctp_v_tag; 240 241 /* Flexible data to match within the packet payload */ 242 __be16 flex_word; 243 u16 flex_offset; 244 bool flex_filter; 245 246 /* filter control */ 247 u16 q_index; 248 u8 flex_off; 249 u8 pctype; 250 u16 dest_vsi; 251 u8 dest_ctl; 252 u8 fd_status; 253 u16 cnt_index; 254 u32 fd_id; 255 }; 256 257 #define I40E_CLOUD_FIELD_OMAC 0x01 258 #define I40E_CLOUD_FIELD_IMAC 0x02 259 #define I40E_CLOUD_FIELD_IVLAN 0x04 260 #define I40E_CLOUD_FIELD_TEN_ID 0x08 261 #define I40E_CLOUD_FIELD_IIP 0x10 262 263 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 264 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 265 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 266 I40E_CLOUD_FIELD_IVLAN) 267 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 268 I40E_CLOUD_FIELD_TEN_ID) 269 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 270 I40E_CLOUD_FIELD_IMAC | \ 271 I40E_CLOUD_FIELD_TEN_ID) 272 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 273 I40E_CLOUD_FIELD_IVLAN | \ 274 I40E_CLOUD_FIELD_TEN_ID) 275 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 276 277 struct i40e_cloud_filter { 278 struct hlist_node cloud_node; 279 unsigned long cookie; 280 /* cloud filter input set follows */ 281 u8 dst_mac[ETH_ALEN]; 282 u8 src_mac[ETH_ALEN]; 283 __be16 vlan_id; 284 u16 seid; /* filter control */ 285 __be16 dst_port; 286 __be16 src_port; 287 u32 tenant_id; 288 union { 289 struct { 290 struct in_addr dst_ip; 291 struct in_addr src_ip; 292 } v4; 293 struct { 294 struct in6_addr dst_ip6; 295 struct in6_addr src_ip6; 296 } v6; 297 } ip; 298 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 299 #define src_ipv6 ip.v6.src_ip6.s6_addr32 300 #define dst_ipv4 ip.v4.dst_ip.s_addr 301 #define src_ipv4 ip.v4.src_ip.s_addr 302 u16 n_proto; /* Ethernet Protocol */ 303 u8 ip_proto; /* IPPROTO value */ 304 u8 flags; 305 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 306 u8 tunnel_type; 307 }; 308 309 #define I40E_ETH_P_LLDP 0x88cc 310 311 #define I40E_DCB_PRIO_TYPE_STRICT 0 312 #define I40E_DCB_PRIO_TYPE_ETS 1 313 #define I40E_DCB_STRICT_PRIO_CREDITS 127 314 /* DCB per TC information data structure */ 315 struct i40e_tc_info { 316 u16 qoffset; /* Queue offset from base queue */ 317 u16 qcount; /* Total Queues */ 318 u8 netdev_tc; /* Netdev TC index if netdev associated */ 319 }; 320 321 /* TC configuration data structure */ 322 struct i40e_tc_configuration { 323 u8 numtc; /* Total number of enabled TCs */ 324 u8 enabled_tc; /* TC map */ 325 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 326 }; 327 328 struct i40e_udp_port_config { 329 /* AdminQ command interface expects port number in Host byte order */ 330 u16 port; 331 u8 type; 332 }; 333 334 /* macros related to FLX_PIT */ 335 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 336 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 337 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 338 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 339 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 340 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 341 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 342 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 343 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 344 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 345 I40E_FLEX_SET_FSIZE(fsize) | \ 346 I40E_FLEX_SET_SRC_WORD(src)) 347 348 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 349 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 350 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 351 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 352 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 353 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 354 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 355 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 356 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 357 358 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 359 360 /* macros related to GLQF_ORT */ 361 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 362 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 363 I40E_GLQF_ORT_PIT_INDX_MASK) 364 365 #define I40E_ORT_SET_COUNT(count) (((count) << \ 366 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 367 I40E_GLQF_ORT_FIELD_CNT_MASK) 368 369 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 370 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 371 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 372 373 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 374 I40E_ORT_SET_COUNT(count) | \ 375 I40E_ORT_SET_PAYLOAD(payload)) 376 377 #define I40E_L3_GLQF_ORT_IDX 34 378 #define I40E_L4_GLQF_ORT_IDX 35 379 380 /* Flex PIT register index */ 381 #define I40E_FLEX_PIT_IDX_START_L2 0 382 #define I40E_FLEX_PIT_IDX_START_L3 3 383 #define I40E_FLEX_PIT_IDX_START_L4 6 384 385 #define I40E_FLEX_PIT_TABLE_SIZE 3 386 387 #define I40E_FLEX_DEST_UNUSED 63 388 389 #define I40E_FLEX_INDEX_ENTRIES 8 390 391 /* Flex MASK to disable all flexible entries */ 392 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 393 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 394 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 395 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 396 397 struct i40e_flex_pit { 398 struct list_head list; 399 u16 src_offset; 400 u8 pit_index; 401 }; 402 403 struct i40e_channel { 404 struct list_head list; 405 bool initialized; 406 u8 type; 407 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 408 u16 stat_counter_idx; 409 u16 base_queue; 410 u16 num_queue_pairs; /* Requested by user */ 411 u16 seid; 412 413 u8 enabled_tc; 414 struct i40e_aqc_vsi_properties_data info; 415 416 u64 max_tx_rate; 417 418 /* track this channel belongs to which VSI */ 419 struct i40e_vsi *parent_vsi; 420 }; 421 422 /* struct that defines the Ethernet device */ 423 struct i40e_pf { 424 struct pci_dev *pdev; 425 struct i40e_hw hw; 426 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 427 struct msix_entry *msix_entries; 428 bool fc_autoneg_status; 429 430 u16 eeprom_version; 431 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 432 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 433 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 434 u16 num_req_vfs; /* num VFs requested for this PF */ 435 u16 num_vf_qps; /* num queue pairs per VF */ 436 u16 num_lan_qps; /* num lan queues this PF has set up */ 437 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 438 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 439 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 440 int iwarp_base_vector; 441 int queues_left; /* queues left unclaimed */ 442 u16 alloc_rss_size; /* allocated RSS queues */ 443 u16 rss_size_max; /* HW defined max RSS queues */ 444 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 445 u16 num_alloc_vsi; /* num VSIs this driver supports */ 446 u8 atr_sample_rate; 447 bool wol_en; 448 449 struct hlist_head fdir_filter_list; 450 u16 fdir_pf_active_filters; 451 unsigned long fd_flush_timestamp; 452 u32 fd_flush_cnt; 453 u32 fd_add_err; 454 u32 fd_atr_cnt; 455 456 /* Book-keeping of side-band filter count per flow-type. 457 * This is used to detect and handle input set changes for 458 * respective flow-type. 459 */ 460 u16 fd_tcp4_filter_cnt; 461 u16 fd_udp4_filter_cnt; 462 u16 fd_sctp4_filter_cnt; 463 u16 fd_ip4_filter_cnt; 464 465 /* Flexible filter table values that need to be programmed into 466 * hardware, which expects L3 and L4 to be programmed separately. We 467 * need to ensure that the values are in ascended order and don't have 468 * duplicates, so we track each L3 and L4 values in separate lists. 469 */ 470 struct list_head l3_flex_pit_list; 471 struct list_head l4_flex_pit_list; 472 473 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 474 u16 pending_udp_bitmap; 475 476 struct hlist_head cloud_filter_list; 477 u16 num_cloud_filters; 478 479 enum i40e_interrupt_policy int_policy; 480 u16 rx_itr_default; 481 u16 tx_itr_default; 482 u32 msg_enable; 483 char int_name[I40E_INT_NAME_STR_LEN]; 484 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 485 unsigned long service_timer_period; 486 unsigned long service_timer_previous; 487 struct timer_list service_timer; 488 struct work_struct service_task; 489 490 u32 hw_features; 491 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 492 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 493 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 494 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 495 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 496 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 497 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 498 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 499 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 500 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 501 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 502 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 503 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 504 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 505 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 506 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 507 #define I40E_HW_STOP_FW_LLDP BIT(16) 508 #define I40E_HW_PORT_ID_VALID BIT(17) 509 #define I40E_HW_RESTART_AUTONEG BIT(18) 510 511 u32 flags; 512 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 513 #define I40E_FLAG_MSI_ENABLED BIT(1) 514 #define I40E_FLAG_MSIX_ENABLED BIT(2) 515 #define I40E_FLAG_RSS_ENABLED BIT(3) 516 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 517 #define I40E_FLAG_FILTER_SYNC BIT(5) 518 #define I40E_FLAG_SRIOV_ENABLED BIT(6) 519 #define I40E_FLAG_DCB_CAPABLE BIT(7) 520 #define I40E_FLAG_DCB_ENABLED BIT(8) 521 #define I40E_FLAG_FD_SB_ENABLED BIT(9) 522 #define I40E_FLAG_FD_ATR_ENABLED BIT(10) 523 #define I40E_FLAG_FD_SB_AUTO_DISABLED BIT(11) 524 #define I40E_FLAG_FD_ATR_AUTO_DISABLED BIT(12) 525 #define I40E_FLAG_MFP_ENABLED BIT(13) 526 #define I40E_FLAG_UDP_FILTER_SYNC BIT(14) 527 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(15) 528 #define I40E_FLAG_VEB_MODE_ENABLED BIT(16) 529 #define I40E_FLAG_VEB_STATS_ENABLED BIT(17) 530 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(18) 531 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(19) 532 #define I40E_FLAG_TEMP_LINK_POLLING BIT(20) 533 #define I40E_FLAG_LEGACY_RX BIT(21) 534 #define I40E_FLAG_PTP BIT(22) 535 #define I40E_FLAG_IWARP_ENABLED BIT(23) 536 #define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT(24) 537 #define I40E_FLAG_CLIENT_L2_CHANGE BIT(25) 538 #define I40E_FLAG_CLIENT_RESET BIT(26) 539 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(27) 540 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(28) 541 #define I40E_FLAG_TC_MQPRIO BIT(29) 542 #define I40E_FLAG_FD_SB_INACTIVE BIT(30) 543 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(31) 544 545 struct i40e_client_instance *cinst; 546 bool stat_offsets_loaded; 547 struct i40e_hw_port_stats stats; 548 struct i40e_hw_port_stats stats_offsets; 549 u32 tx_timeout_count; 550 u32 tx_timeout_recovery_level; 551 unsigned long tx_timeout_last_recovery; 552 u32 tx_sluggish_count; 553 u32 hw_csum_rx_error; 554 u32 led_status; 555 u16 corer_count; /* Core reset count */ 556 u16 globr_count; /* Global reset count */ 557 u16 empr_count; /* EMP reset count */ 558 u16 pfr_count; /* PF reset count */ 559 u16 sw_int_count; /* SW interrupt count */ 560 561 struct mutex switch_mutex; 562 u16 lan_vsi; /* our default LAN VSI */ 563 u16 lan_veb; /* initial relay, if exists */ 564 #define I40E_NO_VEB 0xffff 565 #define I40E_NO_VSI 0xffff 566 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 567 struct i40e_vsi **vsi; 568 struct i40e_veb *veb[I40E_MAX_VEB]; 569 570 struct i40e_lump_tracking *qp_pile; 571 struct i40e_lump_tracking *irq_pile; 572 573 /* switch config info */ 574 u16 pf_seid; 575 u16 main_vsi_seid; 576 u16 mac_seid; 577 struct kobject *switch_kobj; 578 #ifdef CONFIG_DEBUG_FS 579 struct dentry *i40e_dbg_pf; 580 #endif /* CONFIG_DEBUG_FS */ 581 bool cur_promisc; 582 583 u16 instance; /* A unique number per i40e_pf instance in the system */ 584 585 /* sr-iov config info */ 586 struct i40e_vf *vf; 587 int num_alloc_vfs; /* actual number of VFs allocated */ 588 u32 vf_aq_requests; 589 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 590 591 /* DCBx/DCBNL capability for PF that indicates 592 * whether DCBx is managed by firmware or host 593 * based agent (LLDPAD). Also, indicates what 594 * flavor of DCBx protocol (IEEE/CEE) is supported 595 * by the device. For now we're supporting IEEE 596 * mode only. 597 */ 598 u16 dcbx_cap; 599 600 struct i40e_filter_control_settings filter_settings; 601 602 struct ptp_clock *ptp_clock; 603 struct ptp_clock_info ptp_caps; 604 struct sk_buff *ptp_tx_skb; 605 unsigned long ptp_tx_start; 606 struct hwtstamp_config tstamp_config; 607 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 608 u64 ptp_base_adj; 609 u32 tx_hwtstamp_timeouts; 610 u32 tx_hwtstamp_skipped; 611 u32 rx_hwtstamp_cleared; 612 u32 latch_event_flags; 613 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 614 unsigned long latch_events[4]; 615 bool ptp_tx; 616 bool ptp_rx; 617 u16 rss_table_size; /* HW RSS table size */ 618 u32 max_bw; 619 u32 min_bw; 620 621 u32 ioremap_len; 622 u32 fd_inv; 623 u16 phy_led_val; 624 625 u16 override_q_count; 626 u16 last_sw_conf_flags; 627 u16 last_sw_conf_valid_flags; 628 }; 629 630 /** 631 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 632 * @macaddr: the MAC Address as the base key 633 * 634 * Simply copies the address and returns it as a u64 for hashing 635 **/ 636 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 637 { 638 u64 key = 0; 639 640 ether_addr_copy((u8 *)&key, macaddr); 641 return key; 642 } 643 644 enum i40e_filter_state { 645 I40E_FILTER_INVALID = 0, /* Invalid state */ 646 I40E_FILTER_NEW, /* New, not sent to FW yet */ 647 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 648 I40E_FILTER_FAILED, /* Rejected by FW */ 649 I40E_FILTER_REMOVE, /* To be removed */ 650 /* There is no 'removed' state; the filter struct is freed */ 651 }; 652 struct i40e_mac_filter { 653 struct hlist_node hlist; 654 u8 macaddr[ETH_ALEN]; 655 #define I40E_VLAN_ANY -1 656 s16 vlan; 657 enum i40e_filter_state state; 658 }; 659 660 /* Wrapper structure to keep track of filters while we are preparing to send 661 * firmware commands. We cannot send firmware commands while holding a 662 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 663 * a separate structure, which will track the state change and update the real 664 * filter while under lock. We can't simply hold the filters in a separate 665 * list, as this opens a window for a race condition when adding new MAC 666 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 667 */ 668 struct i40e_new_mac_filter { 669 struct hlist_node hlist; 670 struct i40e_mac_filter *f; 671 672 /* Track future changes to state separately */ 673 enum i40e_filter_state state; 674 }; 675 676 struct i40e_veb { 677 struct i40e_pf *pf; 678 u16 idx; 679 u16 veb_idx; /* index of VEB parent */ 680 u16 seid; 681 u16 uplink_seid; 682 u16 stats_idx; /* index of VEB parent */ 683 u8 enabled_tc; 684 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 685 u16 flags; 686 u16 bw_limit; 687 u8 bw_max_quanta; 688 bool is_abs_credits; 689 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 690 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 691 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 692 struct kobject *kobj; 693 bool stat_offsets_loaded; 694 struct i40e_eth_stats stats; 695 struct i40e_eth_stats stats_offsets; 696 struct i40e_veb_tc_stats tc_stats; 697 struct i40e_veb_tc_stats tc_stats_offsets; 698 }; 699 700 /* struct that defines a VSI, associated with a dev */ 701 struct i40e_vsi { 702 struct net_device *netdev; 703 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 704 bool netdev_registered; 705 bool stat_offsets_loaded; 706 707 u32 current_netdev_flags; 708 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 709 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 710 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 711 unsigned long flags; 712 713 /* Per VSI lock to protect elements/hash (MAC filter) */ 714 spinlock_t mac_filter_hash_lock; 715 /* Fixed size hash table with 2^8 buckets for MAC filters */ 716 DECLARE_HASHTABLE(mac_filter_hash, 8); 717 bool has_vlan_filter; 718 719 /* VSI stats */ 720 struct rtnl_link_stats64 net_stats; 721 struct rtnl_link_stats64 net_stats_offsets; 722 struct i40e_eth_stats eth_stats; 723 struct i40e_eth_stats eth_stats_offsets; 724 u32 tx_restart; 725 u32 tx_busy; 726 u64 tx_linearize; 727 u64 tx_force_wb; 728 u32 rx_buf_failed; 729 u32 rx_page_failed; 730 731 /* These are containers of ring pointers, allocated at run-time */ 732 struct i40e_ring **rx_rings; 733 struct i40e_ring **tx_rings; 734 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 735 736 u32 active_filters; 737 u32 promisc_threshold; 738 739 u16 work_limit; 740 u16 int_rate_limit; /* value in usecs */ 741 742 u16 rss_table_size; /* HW RSS table size */ 743 u16 rss_size; /* Allocated RSS queues */ 744 u8 *rss_hkey_user; /* User configured hash keys */ 745 u8 *rss_lut_user; /* User configured lookup table entries */ 746 747 748 u16 max_frame; 749 u16 rx_buf_len; 750 751 struct bpf_prog *xdp_prog; 752 753 /* List of q_vectors allocated to this VSI */ 754 struct i40e_q_vector **q_vectors; 755 int num_q_vectors; 756 int base_vector; 757 bool irqs_ready; 758 759 u16 seid; /* HW index of this VSI (absolute index) */ 760 u16 id; /* VSI number */ 761 u16 uplink_seid; 762 763 u16 base_queue; /* vsi's first queue in hw array */ 764 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 765 u16 req_queue_pairs; /* User requested queue pairs */ 766 u16 num_queue_pairs; /* Used tx and rx pairs */ 767 u16 num_desc; 768 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 769 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 770 771 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 772 struct i40e_tc_configuration tc_config; 773 struct i40e_aqc_vsi_properties_data info; 774 775 /* VSI BW limit (absolute across all TCs) */ 776 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 777 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 778 779 /* Relative TC credits across VSIs */ 780 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 781 /* TC BW limit credits within VSI */ 782 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 783 /* TC BW limit max quanta within VSI */ 784 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 785 786 struct i40e_pf *back; /* Backreference to associated PF */ 787 u16 idx; /* index in pf->vsi[] */ 788 u16 veb_idx; /* index of VEB parent */ 789 struct kobject *kobj; /* sysfs object */ 790 bool current_isup; /* Sync 'link up' logging */ 791 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 792 793 /* channel specific fields */ 794 u16 cnt_q_avail; /* num of queues available for channel usage */ 795 u16 orig_rss_size; 796 u16 current_rss_size; 797 bool reconfig_rss; 798 799 u16 next_base_queue; /* next queue to be used for channel setup */ 800 801 struct list_head ch_list; 802 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 803 804 void *priv; /* client driver data reference. */ 805 806 /* VSI specific handlers */ 807 irqreturn_t (*irq_handler)(int irq, void *data); 808 } ____cacheline_internodealigned_in_smp; 809 810 struct i40e_netdev_priv { 811 struct i40e_vsi *vsi; 812 }; 813 814 /* struct that defines an interrupt vector */ 815 struct i40e_q_vector { 816 struct i40e_vsi *vsi; 817 818 u16 v_idx; /* index in the vsi->q_vector array. */ 819 u16 reg_idx; /* register index of the interrupt */ 820 821 struct napi_struct napi; 822 823 struct i40e_ring_container rx; 824 struct i40e_ring_container tx; 825 826 u8 num_ringpairs; /* total number of ring pairs in vector */ 827 828 cpumask_t affinity_mask; 829 struct irq_affinity_notify affinity_notify; 830 831 struct rcu_head rcu; /* to avoid race with update stats on free */ 832 char name[I40E_INT_NAME_STR_LEN]; 833 bool arm_wb_state; 834 #define ITR_COUNTDOWN_START 100 835 u8 itr_countdown; /* when 0 should adjust ITR */ 836 } ____cacheline_internodealigned_in_smp; 837 838 /* lan device */ 839 struct i40e_device { 840 struct list_head list; 841 struct i40e_pf *pf; 842 }; 843 844 /** 845 * i40e_nvm_version_str - format the NVM version strings 846 * @hw: ptr to the hardware info 847 **/ 848 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 849 { 850 static char buf[32]; 851 u32 full_ver; 852 853 full_ver = hw->nvm.oem_ver; 854 855 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 856 u8 gen, snap; 857 u16 release; 858 859 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 860 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 861 I40E_OEM_SNAP_SHIFT); 862 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 863 864 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 865 } else { 866 u8 ver, patch; 867 u16 build; 868 869 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 870 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 871 I40E_OEM_VER_BUILD_MASK); 872 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 873 874 snprintf(buf, sizeof(buf), 875 "%x.%02x 0x%x %d.%d.%d", 876 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 877 I40E_NVM_VERSION_HI_SHIFT, 878 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 879 I40E_NVM_VERSION_LO_SHIFT, 880 hw->nvm.eetrack, ver, build, patch); 881 } 882 883 return buf; 884 } 885 886 /** 887 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 888 * @netdev: the corresponding netdev 889 * 890 * Return the PF struct for the given netdev 891 **/ 892 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 893 { 894 struct i40e_netdev_priv *np = netdev_priv(netdev); 895 struct i40e_vsi *vsi = np->vsi; 896 897 return vsi->back; 898 } 899 900 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 901 irqreturn_t (*irq_handler)(int, void *)) 902 { 903 vsi->irq_handler = irq_handler; 904 } 905 906 /** 907 * i40e_get_fd_cnt_all - get the total FD filter space available 908 * @pf: pointer to the PF struct 909 **/ 910 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 911 { 912 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 913 } 914 915 /** 916 * i40e_read_fd_input_set - reads value of flow director input set register 917 * @pf: pointer to the PF struct 918 * @addr: register addr 919 * 920 * This function reads value of flow director input set register 921 * specified by 'addr' (which is specific to flow-type) 922 **/ 923 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 924 { 925 u64 val; 926 927 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 928 val <<= 32; 929 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 930 931 return val; 932 } 933 934 /** 935 * i40e_write_fd_input_set - writes value into flow director input set register 936 * @pf: pointer to the PF struct 937 * @addr: register addr 938 * @val: value to be written 939 * 940 * This function writes specified value to the register specified by 'addr'. 941 * This register is input set register based on flow-type. 942 **/ 943 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 944 u16 addr, u64 val) 945 { 946 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 947 (u32)(val >> 32)); 948 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 949 (u32)(val & 0xFFFFFFFFULL)); 950 } 951 952 /* needed by i40e_ethtool.c */ 953 int i40e_up(struct i40e_vsi *vsi); 954 void i40e_down(struct i40e_vsi *vsi); 955 extern const char i40e_driver_name[]; 956 extern const char i40e_driver_version_str[]; 957 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 958 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 959 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 960 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 961 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 962 u16 rss_table_size, u16 rss_size); 963 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 964 /** 965 * i40e_find_vsi_by_type - Find and return Flow Director VSI 966 * @pf: PF to search for VSI 967 * @type: Value indicating type of VSI we are looking for 968 **/ 969 static inline struct i40e_vsi * 970 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 971 { 972 int i; 973 974 for (i = 0; i < pf->num_alloc_vsi; i++) { 975 struct i40e_vsi *vsi = pf->vsi[i]; 976 977 if (vsi && vsi->type == type) 978 return vsi; 979 } 980 981 return NULL; 982 } 983 void i40e_update_stats(struct i40e_vsi *vsi); 984 void i40e_update_eth_stats(struct i40e_vsi *vsi); 985 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 986 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 987 bool printconfig); 988 989 int i40e_add_del_fdir(struct i40e_vsi *vsi, 990 struct i40e_fdir_filter *input, bool add); 991 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 992 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 993 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 994 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 995 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 996 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 997 void i40e_set_ethtool_ops(struct net_device *netdev); 998 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 999 const u8 *macaddr, s16 vlan); 1000 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1001 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1002 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1003 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1004 u16 uplink, u32 param1); 1005 int i40e_vsi_release(struct i40e_vsi *vsi); 1006 void i40e_service_event_schedule(struct i40e_pf *pf); 1007 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1008 u8 *msg, u16 len); 1009 1010 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1011 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1012 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1013 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1014 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1015 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1016 u16 downlink_seid, u8 enabled_tc); 1017 void i40e_veb_release(struct i40e_veb *veb); 1018 1019 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1020 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1021 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1022 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1023 void i40e_pf_reset_stats(struct i40e_pf *pf); 1024 #ifdef CONFIG_DEBUG_FS 1025 void i40e_dbg_pf_init(struct i40e_pf *pf); 1026 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1027 void i40e_dbg_init(void); 1028 void i40e_dbg_exit(void); 1029 #else 1030 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1031 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1032 static inline void i40e_dbg_init(void) {} 1033 static inline void i40e_dbg_exit(void) {} 1034 #endif /* CONFIG_DEBUG_FS*/ 1035 /* needed by client drivers */ 1036 int i40e_lan_add_device(struct i40e_pf *pf); 1037 int i40e_lan_del_device(struct i40e_pf *pf); 1038 void i40e_client_subtask(struct i40e_pf *pf); 1039 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1040 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1041 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1042 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1043 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1044 /** 1045 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1046 * @vsi: pointer to a vsi 1047 * @vector: enable a particular Hw Interrupt vector, without base_vector 1048 **/ 1049 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1050 { 1051 struct i40e_pf *pf = vsi->back; 1052 struct i40e_hw *hw = &pf->hw; 1053 u32 val; 1054 1055 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1056 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1057 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1058 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1059 /* skip the flush */ 1060 } 1061 1062 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1063 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1064 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1065 int i40e_open(struct net_device *netdev); 1066 int i40e_close(struct net_device *netdev); 1067 int i40e_vsi_open(struct i40e_vsi *vsi); 1068 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1069 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1070 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1071 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1072 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1073 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1074 const u8 *macaddr); 1075 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1076 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1077 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1078 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1079 #ifdef CONFIG_I40E_DCB 1080 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1081 struct i40e_dcbx_config *old_cfg, 1082 struct i40e_dcbx_config *new_cfg); 1083 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1084 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1085 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1086 struct i40e_dcbx_config *old_cfg, 1087 struct i40e_dcbx_config *new_cfg); 1088 #endif /* CONFIG_I40E_DCB */ 1089 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1090 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1091 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1092 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1093 void i40e_ptp_set_increment(struct i40e_pf *pf); 1094 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1095 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1096 void i40e_ptp_init(struct i40e_pf *pf); 1097 void i40e_ptp_stop(struct i40e_pf *pf); 1098 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1099 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1100 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1101 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1102 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1103 1104 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1105 { 1106 return !!vsi->xdp_prog; 1107 } 1108 1109 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1110 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1111 #endif /* _I40E_H_ */ 1112