1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #ifndef _I40E_H_
5 #define _I40E_H_
6 
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/xdp_sock.h>
39 #include "i40e_type.h"
40 #include "i40e_prototype.h"
41 #include "i40e_client.h"
42 #include <linux/avf/virtchnl.h>
43 #include "i40e_virtchnl_pf.h"
44 #include "i40e_txrx.h"
45 #include "i40e_dcb.h"
46 
47 /* Useful i40e defaults */
48 #define I40E_MAX_VEB			16
49 
50 #define I40E_MAX_NUM_DESCRIPTORS	4096
51 #define I40E_MAX_CSR_SPACE		(4 * 1024 * 1024 - 64 * 1024)
52 #define I40E_DEFAULT_NUM_DESCRIPTORS	512
53 #define I40E_REQ_DESCRIPTOR_MULTIPLE	32
54 #define I40E_MIN_NUM_DESCRIPTORS	64
55 #define I40E_MIN_MSIX			2
56 #define I40E_DEFAULT_NUM_VMDQ_VSI	8 /* max 256 VSIs */
57 #define I40E_MIN_VSI_ALLOC		83 /* LAN, ATR, FCOE, 64 VF */
58 /* max 16 qps */
59 #define i40e_default_queues_per_vmdq(pf) \
60 		(((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
61 #define I40E_DEFAULT_QUEUES_PER_VF	4
62 #define I40E_MAX_VF_QUEUES		16
63 #define I40E_DEFAULT_QUEUES_PER_TC	1 /* should be a power of 2 */
64 #define i40e_pf_get_max_q_per_tc(pf) \
65 		(((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
66 #define I40E_FDIR_RING			0
67 #define I40E_FDIR_RING_COUNT		32
68 #define I40E_MAX_AQ_BUF_SIZE		4096
69 #define I40E_AQ_LEN			256
70 #define I40E_AQ_WORK_LIMIT		66 /* max number of VFs + a little */
71 #define I40E_MAX_USER_PRIORITY		8
72 #define I40E_DEFAULT_TRAFFIC_CLASS	BIT(0)
73 #define I40E_DEFAULT_MSG_ENABLE		4
74 #define I40E_QUEUE_WAIT_RETRY_LIMIT	10
75 #define I40E_INT_NAME_STR_LEN		(IFNAMSIZ + 16)
76 
77 #define I40E_NVM_VERSION_LO_SHIFT	0
78 #define I40E_NVM_VERSION_LO_MASK	(0xff << I40E_NVM_VERSION_LO_SHIFT)
79 #define I40E_NVM_VERSION_HI_SHIFT	12
80 #define I40E_NVM_VERSION_HI_MASK	(0xf << I40E_NVM_VERSION_HI_SHIFT)
81 #define I40E_OEM_VER_BUILD_MASK		0xffff
82 #define I40E_OEM_VER_PATCH_MASK		0xff
83 #define I40E_OEM_VER_BUILD_SHIFT	8
84 #define I40E_OEM_VER_SHIFT		24
85 #define I40E_PHY_DEBUG_ALL \
86 	(I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
87 	I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
88 
89 #define I40E_OEM_EETRACK_ID		0xffffffff
90 #define I40E_OEM_GEN_SHIFT		24
91 #define I40E_OEM_SNAP_MASK		0x00ff0000
92 #define I40E_OEM_SNAP_SHIFT		16
93 #define I40E_OEM_RELEASE_MASK		0x0000ffff
94 
95 /* The values in here are decimal coded as hex as is the case in the NVM map*/
96 #define I40E_CURRENT_NVM_VERSION_HI	0x2
97 #define I40E_CURRENT_NVM_VERSION_LO	0x40
98 
99 #define I40E_RX_DESC(R, i)	\
100 	(&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
101 #define I40E_TX_DESC(R, i)	\
102 	(&(((struct i40e_tx_desc *)((R)->desc))[i]))
103 #define I40E_TX_CTXTDESC(R, i)	\
104 	(&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
105 #define I40E_TX_FDIRDESC(R, i)	\
106 	(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
107 
108 /* default to trying for four seconds */
109 #define I40E_TRY_LINK_TIMEOUT	(4 * HZ)
110 
111 /* BW rate limiting */
112 #define I40E_BW_CREDIT_DIVISOR		50 /* 50Mbps per BW credit */
113 #define I40E_BW_MBPS_DIVISOR		125000 /* rate / (1000000 / 8) Mbps */
114 #define I40E_MAX_BW_INACTIVE_ACCUM	4 /* accumulate 4 credits max */
115 
116 /* driver state flags */
117 enum i40e_state_t {
118 	__I40E_TESTING,
119 	__I40E_CONFIG_BUSY,
120 	__I40E_CONFIG_DONE,
121 	__I40E_DOWN,
122 	__I40E_SERVICE_SCHED,
123 	__I40E_ADMINQ_EVENT_PENDING,
124 	__I40E_MDD_EVENT_PENDING,
125 	__I40E_VFLR_EVENT_PENDING,
126 	__I40E_RESET_RECOVERY_PENDING,
127 	__I40E_TIMEOUT_RECOVERY_PENDING,
128 	__I40E_MISC_IRQ_REQUESTED,
129 	__I40E_RESET_INTR_RECEIVED,
130 	__I40E_REINIT_REQUESTED,
131 	__I40E_PF_RESET_REQUESTED,
132 	__I40E_CORE_RESET_REQUESTED,
133 	__I40E_GLOBAL_RESET_REQUESTED,
134 	__I40E_EMP_RESET_INTR_RECEIVED,
135 	__I40E_SUSPENDED,
136 	__I40E_PTP_TX_IN_PROGRESS,
137 	__I40E_BAD_EEPROM,
138 	__I40E_DOWN_REQUESTED,
139 	__I40E_FD_FLUSH_REQUESTED,
140 	__I40E_FD_ATR_AUTO_DISABLED,
141 	__I40E_FD_SB_AUTO_DISABLED,
142 	__I40E_RESET_FAILED,
143 	__I40E_PORT_SUSPENDED,
144 	__I40E_VF_DISABLE,
145 	__I40E_MACVLAN_SYNC_PENDING,
146 	__I40E_UDP_FILTER_SYNC_PENDING,
147 	__I40E_TEMP_LINK_POLLING,
148 	__I40E_CLIENT_SERVICE_REQUESTED,
149 	__I40E_CLIENT_L2_CHANGE,
150 	__I40E_CLIENT_RESET,
151 	__I40E_VIRTCHNL_OP_PENDING,
152 	__I40E_RECOVERY_MODE,
153 	/* This must be last as it determines the size of the BITMAP */
154 	__I40E_STATE_SIZE__,
155 };
156 
157 #define I40E_PF_RESET_FLAG	BIT_ULL(__I40E_PF_RESET_REQUESTED)
158 
159 /* VSI state flags */
160 enum i40e_vsi_state_t {
161 	__I40E_VSI_DOWN,
162 	__I40E_VSI_NEEDS_RESTART,
163 	__I40E_VSI_SYNCING_FILTERS,
164 	__I40E_VSI_OVERFLOW_PROMISC,
165 	__I40E_VSI_REINIT_REQUESTED,
166 	__I40E_VSI_DOWN_REQUESTED,
167 	/* This must be last as it determines the size of the BITMAP */
168 	__I40E_VSI_STATE_SIZE__,
169 };
170 
171 enum i40e_interrupt_policy {
172 	I40E_INTERRUPT_BEST_CASE,
173 	I40E_INTERRUPT_MEDIUM,
174 	I40E_INTERRUPT_LOWEST
175 };
176 
177 struct i40e_lump_tracking {
178 	u16 num_entries;
179 	u16 search_hint;
180 	u16 list[0];
181 #define I40E_PILE_VALID_BIT  0x8000
182 #define I40E_IWARP_IRQ_PILE_ID  (I40E_PILE_VALID_BIT - 2)
183 };
184 
185 #define I40E_DEFAULT_ATR_SAMPLE_RATE	20
186 #define I40E_FDIR_MAX_RAW_PACKET_SIZE	512
187 #define I40E_FDIR_BUFFER_FULL_MARGIN	10
188 #define I40E_FDIR_BUFFER_HEAD_ROOM	32
189 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
190 
191 #define I40E_HKEY_ARRAY_SIZE	((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
192 #define I40E_HLUT_ARRAY_SIZE	((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
193 #define I40E_VF_HLUT_ARRAY_SIZE	((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
194 
195 enum i40e_fd_stat_idx {
196 	I40E_FD_STAT_ATR,
197 	I40E_FD_STAT_SB,
198 	I40E_FD_STAT_ATR_TUNNEL,
199 	I40E_FD_STAT_PF_COUNT
200 };
201 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
202 #define I40E_FD_ATR_STAT_IDX(pf_id) \
203 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
204 #define I40E_FD_SB_STAT_IDX(pf_id)  \
205 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
206 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
207 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
208 
209 /* The following structure contains the data parsed from the user-defined
210  * field of the ethtool_rx_flow_spec structure.
211  */
212 struct i40e_rx_flow_userdef {
213 	bool flex_filter;
214 	u16 flex_word;
215 	u16 flex_offset;
216 };
217 
218 struct i40e_fdir_filter {
219 	struct hlist_node fdir_node;
220 	/* filter ipnut set */
221 	u8 flow_type;
222 	u8 ip4_proto;
223 	/* TX packet view of src and dst */
224 	__be32 dst_ip;
225 	__be32 src_ip;
226 	__be16 src_port;
227 	__be16 dst_port;
228 	__be32 sctp_v_tag;
229 
230 	/* Flexible data to match within the packet payload */
231 	__be16 flex_word;
232 	u16 flex_offset;
233 	bool flex_filter;
234 
235 	/* filter control */
236 	u16 q_index;
237 	u8  flex_off;
238 	u8  pctype;
239 	u16 dest_vsi;
240 	u8  dest_ctl;
241 	u8  fd_status;
242 	u16 cnt_index;
243 	u32 fd_id;
244 };
245 
246 #define I40E_CLOUD_FIELD_OMAC		BIT(0)
247 #define I40E_CLOUD_FIELD_IMAC		BIT(1)
248 #define I40E_CLOUD_FIELD_IVLAN		BIT(2)
249 #define I40E_CLOUD_FIELD_TEN_ID		BIT(3)
250 #define I40E_CLOUD_FIELD_IIP		BIT(4)
251 
252 #define I40E_CLOUD_FILTER_FLAGS_OMAC	I40E_CLOUD_FIELD_OMAC
253 #define I40E_CLOUD_FILTER_FLAGS_IMAC	I40E_CLOUD_FIELD_IMAC
254 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN	(I40E_CLOUD_FIELD_IMAC | \
255 						 I40E_CLOUD_FIELD_IVLAN)
256 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID	(I40E_CLOUD_FIELD_IMAC | \
257 						 I40E_CLOUD_FIELD_TEN_ID)
258 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
259 						  I40E_CLOUD_FIELD_IMAC | \
260 						  I40E_CLOUD_FIELD_TEN_ID)
261 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
262 						   I40E_CLOUD_FIELD_IVLAN | \
263 						   I40E_CLOUD_FIELD_TEN_ID)
264 #define I40E_CLOUD_FILTER_FLAGS_IIP	I40E_CLOUD_FIELD_IIP
265 
266 struct i40e_cloud_filter {
267 	struct hlist_node cloud_node;
268 	unsigned long cookie;
269 	/* cloud filter input set follows */
270 	u8 dst_mac[ETH_ALEN];
271 	u8 src_mac[ETH_ALEN];
272 	__be16 vlan_id;
273 	u16 seid;       /* filter control */
274 	__be16 dst_port;
275 	__be16 src_port;
276 	u32 tenant_id;
277 	union {
278 		struct {
279 			struct in_addr dst_ip;
280 			struct in_addr src_ip;
281 		} v4;
282 		struct {
283 			struct in6_addr dst_ip6;
284 			struct in6_addr src_ip6;
285 		} v6;
286 	} ip;
287 #define dst_ipv6	ip.v6.dst_ip6.s6_addr32
288 #define src_ipv6	ip.v6.src_ip6.s6_addr32
289 #define dst_ipv4	ip.v4.dst_ip.s_addr
290 #define src_ipv4	ip.v4.src_ip.s_addr
291 	u16 n_proto;    /* Ethernet Protocol */
292 	u8 ip_proto;    /* IPPROTO value */
293 	u8 flags;
294 #define I40E_CLOUD_TNL_TYPE_NONE        0xff
295 	u8 tunnel_type;
296 };
297 
298 #define I40E_DCB_PRIO_TYPE_STRICT	0
299 #define I40E_DCB_PRIO_TYPE_ETS		1
300 #define I40E_DCB_STRICT_PRIO_CREDITS	127
301 /* DCB per TC information data structure */
302 struct i40e_tc_info {
303 	u16	qoffset;	/* Queue offset from base queue */
304 	u16	qcount;		/* Total Queues */
305 	u8	netdev_tc;	/* Netdev TC index if netdev associated */
306 };
307 
308 /* TC configuration data structure */
309 struct i40e_tc_configuration {
310 	u8	numtc;		/* Total number of enabled TCs */
311 	u8	enabled_tc;	/* TC map */
312 	struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
313 };
314 
315 #define I40E_UDP_PORT_INDEX_UNUSED	255
316 struct i40e_udp_port_config {
317 	/* AdminQ command interface expects port number in Host byte order */
318 	u16 port;
319 	u8 type;
320 	u8 filter_index;
321 };
322 
323 #define I40_DDP_FLASH_REGION 100
324 #define I40E_PROFILE_INFO_SIZE 48
325 #define I40E_MAX_PROFILE_NUM 16
326 #define I40E_PROFILE_LIST_SIZE \
327 	(I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
328 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
329 #define I40E_DDP_PROFILE_NAME_MAX 64
330 
331 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
332 		  bool is_add);
333 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
334 
335 struct i40e_ddp_profile_list {
336 	u32 p_count;
337 	struct i40e_profile_info p_info[0];
338 };
339 
340 struct i40e_ddp_old_profile_list {
341 	struct list_head list;
342 	size_t old_ddp_size;
343 	u8 old_ddp_buf[0];
344 };
345 
346 /* macros related to FLX_PIT */
347 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
348 				    I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
349 				    I40E_PRTQF_FLX_PIT_FSIZE_MASK)
350 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
351 				     I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
352 				     I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
353 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
354 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
355 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
356 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
357 					     I40E_FLEX_SET_FSIZE(fsize) | \
358 					     I40E_FLEX_SET_SRC_WORD(src))
359 
360 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
361 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
362 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
363 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
364 				     I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
365 				     I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
366 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
367 				       I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
368 				       I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
369 
370 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
371 
372 /* macros related to GLQF_ORT */
373 #define I40E_ORT_SET_IDX(idx)		(((idx) << \
374 					  I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
375 					 I40E_GLQF_ORT_PIT_INDX_MASK)
376 
377 #define I40E_ORT_SET_COUNT(count)	(((count) << \
378 					  I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
379 					 I40E_GLQF_ORT_FIELD_CNT_MASK)
380 
381 #define I40E_ORT_SET_PAYLOAD(payload)	(((payload) << \
382 					  I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
383 					 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
384 
385 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
386 						I40E_ORT_SET_COUNT(count) | \
387 						I40E_ORT_SET_PAYLOAD(payload))
388 
389 #define I40E_L3_GLQF_ORT_IDX		34
390 #define I40E_L4_GLQF_ORT_IDX		35
391 
392 /* Flex PIT register index */
393 #define I40E_FLEX_PIT_IDX_START_L2	0
394 #define I40E_FLEX_PIT_IDX_START_L3	3
395 #define I40E_FLEX_PIT_IDX_START_L4	6
396 
397 #define I40E_FLEX_PIT_TABLE_SIZE	3
398 
399 #define I40E_FLEX_DEST_UNUSED		63
400 
401 #define I40E_FLEX_INDEX_ENTRIES		8
402 
403 /* Flex MASK to disable all flexible entries */
404 #define I40E_FLEX_INPUT_MASK	(I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
405 				 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
406 				 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
407 				 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
408 
409 struct i40e_flex_pit {
410 	struct list_head list;
411 	u16 src_offset;
412 	u8 pit_index;
413 };
414 
415 struct i40e_fwd_adapter {
416 	struct net_device *netdev;
417 	int bit_no;
418 };
419 
420 struct i40e_channel {
421 	struct list_head list;
422 	bool initialized;
423 	u8 type;
424 	u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
425 	u16 stat_counter_idx;
426 	u16 base_queue;
427 	u16 num_queue_pairs; /* Requested by user */
428 	u16 seid;
429 
430 	u8 enabled_tc;
431 	struct i40e_aqc_vsi_properties_data info;
432 
433 	u64 max_tx_rate;
434 	struct i40e_fwd_adapter *fwd;
435 
436 	/* track this channel belongs to which VSI */
437 	struct i40e_vsi *parent_vsi;
438 };
439 
440 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
441 {
442 	return !!ch->fwd;
443 }
444 
445 static inline u8 *i40e_channel_mac(struct i40e_channel *ch)
446 {
447 	if (i40e_is_channel_macvlan(ch))
448 		return ch->fwd->netdev->dev_addr;
449 	else
450 		return NULL;
451 }
452 
453 /* struct that defines the Ethernet device */
454 struct i40e_pf {
455 	struct pci_dev *pdev;
456 	struct i40e_hw hw;
457 	DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
458 	struct msix_entry *msix_entries;
459 	bool fc_autoneg_status;
460 
461 	u16 eeprom_version;
462 	u16 num_vmdq_vsis;         /* num vmdq vsis this PF has set up */
463 	u16 num_vmdq_qps;          /* num queue pairs per vmdq pool */
464 	u16 num_vmdq_msix;         /* num queue vectors per vmdq pool */
465 	u16 num_req_vfs;           /* num VFs requested for this PF */
466 	u16 num_vf_qps;            /* num queue pairs per VF */
467 	u16 num_lan_qps;           /* num lan queues this PF has set up */
468 	u16 num_lan_msix;          /* num queue vectors for the base PF vsi */
469 	u16 num_fdsb_msix;         /* num queue vectors for sideband Fdir */
470 	u16 num_iwarp_msix;        /* num of iwarp vectors for this PF */
471 	int iwarp_base_vector;
472 	int queues_left;           /* queues left unclaimed */
473 	u16 alloc_rss_size;        /* allocated RSS queues */
474 	u16 rss_size_max;          /* HW defined max RSS queues */
475 	u16 fdir_pf_filter_count;  /* num of guaranteed filters for this PF */
476 	u16 num_alloc_vsi;         /* num VSIs this driver supports */
477 	u8 atr_sample_rate;
478 	bool wol_en;
479 
480 	struct hlist_head fdir_filter_list;
481 	u16 fdir_pf_active_filters;
482 	unsigned long fd_flush_timestamp;
483 	u32 fd_flush_cnt;
484 	u32 fd_add_err;
485 	u32 fd_atr_cnt;
486 
487 	/* Book-keeping of side-band filter count per flow-type.
488 	 * This is used to detect and handle input set changes for
489 	 * respective flow-type.
490 	 */
491 	u16 fd_tcp4_filter_cnt;
492 	u16 fd_udp4_filter_cnt;
493 	u16 fd_sctp4_filter_cnt;
494 	u16 fd_ip4_filter_cnt;
495 
496 	/* Flexible filter table values that need to be programmed into
497 	 * hardware, which expects L3 and L4 to be programmed separately. We
498 	 * need to ensure that the values are in ascended order and don't have
499 	 * duplicates, so we track each L3 and L4 values in separate lists.
500 	 */
501 	struct list_head l3_flex_pit_list;
502 	struct list_head l4_flex_pit_list;
503 
504 	struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
505 	u16 pending_udp_bitmap;
506 
507 	struct hlist_head cloud_filter_list;
508 	u16 num_cloud_filters;
509 
510 	enum i40e_interrupt_policy int_policy;
511 	u16 rx_itr_default;
512 	u16 tx_itr_default;
513 	u32 msg_enable;
514 	char int_name[I40E_INT_NAME_STR_LEN];
515 	u16 adminq_work_limit; /* num of admin receive queue desc to process */
516 	unsigned long service_timer_period;
517 	unsigned long service_timer_previous;
518 	struct timer_list service_timer;
519 	struct work_struct service_task;
520 
521 	u32 hw_features;
522 #define I40E_HW_RSS_AQ_CAPABLE			BIT(0)
523 #define I40E_HW_128_QP_RSS_CAPABLE		BIT(1)
524 #define I40E_HW_ATR_EVICT_CAPABLE		BIT(2)
525 #define I40E_HW_WB_ON_ITR_CAPABLE		BIT(3)
526 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE	BIT(4)
527 #define I40E_HW_NO_PCI_LINK_CHECK		BIT(5)
528 #define I40E_HW_100M_SGMII_CAPABLE		BIT(6)
529 #define I40E_HW_NO_DCB_SUPPORT			BIT(7)
530 #define I40E_HW_USE_SET_LLDP_MIB		BIT(8)
531 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE		BIT(9)
532 #define I40E_HW_PTP_L4_CAPABLE			BIT(10)
533 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE		BIT(11)
534 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE	BIT(12)
535 #define I40E_HW_HAVE_CRT_RETIMER		BIT(13)
536 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE		BIT(14)
537 #define I40E_HW_PHY_CONTROLS_LEDS		BIT(15)
538 #define I40E_HW_STOP_FW_LLDP			BIT(16)
539 #define I40E_HW_PORT_ID_VALID			BIT(17)
540 #define I40E_HW_RESTART_AUTONEG			BIT(18)
541 
542 	u32 flags;
543 #define I40E_FLAG_RX_CSUM_ENABLED		BIT(0)
544 #define I40E_FLAG_MSI_ENABLED			BIT(1)
545 #define I40E_FLAG_MSIX_ENABLED			BIT(2)
546 #define I40E_FLAG_RSS_ENABLED			BIT(3)
547 #define I40E_FLAG_VMDQ_ENABLED			BIT(4)
548 #define I40E_FLAG_SRIOV_ENABLED			BIT(5)
549 #define I40E_FLAG_DCB_CAPABLE			BIT(6)
550 #define I40E_FLAG_DCB_ENABLED			BIT(7)
551 #define I40E_FLAG_FD_SB_ENABLED			BIT(8)
552 #define I40E_FLAG_FD_ATR_ENABLED		BIT(9)
553 #define I40E_FLAG_MFP_ENABLED			BIT(10)
554 #define I40E_FLAG_HW_ATR_EVICT_ENABLED		BIT(11)
555 #define I40E_FLAG_VEB_MODE_ENABLED		BIT(12)
556 #define I40E_FLAG_VEB_STATS_ENABLED		BIT(13)
557 #define I40E_FLAG_LINK_POLLING_ENABLED		BIT(14)
558 #define I40E_FLAG_TRUE_PROMISC_SUPPORT		BIT(15)
559 #define I40E_FLAG_LEGACY_RX			BIT(16)
560 #define I40E_FLAG_PTP				BIT(17)
561 #define I40E_FLAG_IWARP_ENABLED			BIT(18)
562 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(19)
563 #define I40E_FLAG_SOURCE_PRUNING_DISABLED       BIT(20)
564 #define I40E_FLAG_TC_MQPRIO			BIT(21)
565 #define I40E_FLAG_FD_SB_INACTIVE		BIT(22)
566 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER		BIT(23)
567 #define I40E_FLAG_DISABLE_FW_LLDP		BIT(24)
568 #define I40E_FLAG_RS_FEC			BIT(25)
569 #define I40E_FLAG_BASE_R_FEC			BIT(26)
570 
571 	struct i40e_client_instance *cinst;
572 	bool stat_offsets_loaded;
573 	struct i40e_hw_port_stats stats;
574 	struct i40e_hw_port_stats stats_offsets;
575 	u32 tx_timeout_count;
576 	u32 tx_timeout_recovery_level;
577 	unsigned long tx_timeout_last_recovery;
578 	u32 tx_sluggish_count;
579 	u32 hw_csum_rx_error;
580 	u32 led_status;
581 	u16 corer_count; /* Core reset count */
582 	u16 globr_count; /* Global reset count */
583 	u16 empr_count; /* EMP reset count */
584 	u16 pfr_count; /* PF reset count */
585 	u16 sw_int_count; /* SW interrupt count */
586 
587 	struct mutex switch_mutex;
588 	u16 lan_vsi;       /* our default LAN VSI */
589 	u16 lan_veb;       /* initial relay, if exists */
590 #define I40E_NO_VEB	0xffff
591 #define I40E_NO_VSI	0xffff
592 	u16 next_vsi;      /* Next unallocated VSI - 0-based! */
593 	struct i40e_vsi **vsi;
594 	struct i40e_veb *veb[I40E_MAX_VEB];
595 
596 	struct i40e_lump_tracking *qp_pile;
597 	struct i40e_lump_tracking *irq_pile;
598 
599 	/* switch config info */
600 	u16 pf_seid;
601 	u16 main_vsi_seid;
602 	u16 mac_seid;
603 	struct kobject *switch_kobj;
604 #ifdef CONFIG_DEBUG_FS
605 	struct dentry *i40e_dbg_pf;
606 #endif /* CONFIG_DEBUG_FS */
607 	bool cur_promisc;
608 
609 	u16 instance; /* A unique number per i40e_pf instance in the system */
610 
611 	/* sr-iov config info */
612 	struct i40e_vf *vf;
613 	int num_alloc_vfs;	/* actual number of VFs allocated */
614 	u32 vf_aq_requests;
615 	u32 arq_overflows;	/* Not fatal, possibly indicative of problems */
616 
617 	/* DCBx/DCBNL capability for PF that indicates
618 	 * whether DCBx is managed by firmware or host
619 	 * based agent (LLDPAD). Also, indicates what
620 	 * flavor of DCBx protocol (IEEE/CEE) is supported
621 	 * by the device. For now we're supporting IEEE
622 	 * mode only.
623 	 */
624 	u16 dcbx_cap;
625 
626 	struct i40e_filter_control_settings filter_settings;
627 
628 	struct ptp_clock *ptp_clock;
629 	struct ptp_clock_info ptp_caps;
630 	struct sk_buff *ptp_tx_skb;
631 	unsigned long ptp_tx_start;
632 	struct hwtstamp_config tstamp_config;
633 	struct timespec64 ptp_prev_hw_time;
634 	ktime_t ptp_reset_start;
635 	struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
636 	u32 ptp_adj_mult;
637 	u32 tx_hwtstamp_timeouts;
638 	u32 tx_hwtstamp_skipped;
639 	u32 rx_hwtstamp_cleared;
640 	u32 latch_event_flags;
641 	spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
642 	unsigned long latch_events[4];
643 	bool ptp_tx;
644 	bool ptp_rx;
645 	u16 rss_table_size; /* HW RSS table size */
646 	u32 max_bw;
647 	u32 min_bw;
648 
649 	u32 ioremap_len;
650 	u32 fd_inv;
651 	u16 phy_led_val;
652 
653 	u16 override_q_count;
654 	u16 last_sw_conf_flags;
655 	u16 last_sw_conf_valid_flags;
656 	/* List to keep previous DDP profiles to be rolled back in the future */
657 	struct list_head ddp_old_prof;
658 };
659 
660 /**
661  * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
662  * @macaddr: the MAC Address as the base key
663  *
664  * Simply copies the address and returns it as a u64 for hashing
665  **/
666 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
667 {
668 	u64 key = 0;
669 
670 	ether_addr_copy((u8 *)&key, macaddr);
671 	return key;
672 }
673 
674 enum i40e_filter_state {
675 	I40E_FILTER_INVALID = 0,	/* Invalid state */
676 	I40E_FILTER_NEW,		/* New, not sent to FW yet */
677 	I40E_FILTER_ACTIVE,		/* Added to switch by FW */
678 	I40E_FILTER_FAILED,		/* Rejected by FW */
679 	I40E_FILTER_REMOVE,		/* To be removed */
680 /* There is no 'removed' state; the filter struct is freed */
681 };
682 struct i40e_mac_filter {
683 	struct hlist_node hlist;
684 	u8 macaddr[ETH_ALEN];
685 #define I40E_VLAN_ANY -1
686 	s16 vlan;
687 	enum i40e_filter_state state;
688 };
689 
690 /* Wrapper structure to keep track of filters while we are preparing to send
691  * firmware commands. We cannot send firmware commands while holding a
692  * spinlock, since it might sleep. To avoid this, we wrap the added filters in
693  * a separate structure, which will track the state change and update the real
694  * filter while under lock. We can't simply hold the filters in a separate
695  * list, as this opens a window for a race condition when adding new MAC
696  * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
697  */
698 struct i40e_new_mac_filter {
699 	struct hlist_node hlist;
700 	struct i40e_mac_filter *f;
701 
702 	/* Track future changes to state separately */
703 	enum i40e_filter_state state;
704 };
705 
706 struct i40e_veb {
707 	struct i40e_pf *pf;
708 	u16 idx;
709 	u16 veb_idx;		/* index of VEB parent */
710 	u16 seid;
711 	u16 uplink_seid;
712 	u16 stats_idx;		/* index of VEB parent */
713 	u8  enabled_tc;
714 	u16 bridge_mode;	/* Bridge Mode (VEB/VEPA) */
715 	u16 flags;
716 	u16 bw_limit;
717 	u8  bw_max_quanta;
718 	bool is_abs_credits;
719 	u8  bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
720 	u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
721 	u8  bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
722 	struct kobject *kobj;
723 	bool stat_offsets_loaded;
724 	struct i40e_eth_stats stats;
725 	struct i40e_eth_stats stats_offsets;
726 	struct i40e_veb_tc_stats tc_stats;
727 	struct i40e_veb_tc_stats tc_stats_offsets;
728 };
729 
730 /* struct that defines a VSI, associated with a dev */
731 struct i40e_vsi {
732 	struct net_device *netdev;
733 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
734 	bool netdev_registered;
735 	bool stat_offsets_loaded;
736 
737 	u32 current_netdev_flags;
738 	DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
739 #define I40E_VSI_FLAG_FILTER_CHANGED	BIT(0)
740 #define I40E_VSI_FLAG_VEB_OWNER		BIT(1)
741 	unsigned long flags;
742 
743 	/* Per VSI lock to protect elements/hash (MAC filter) */
744 	spinlock_t mac_filter_hash_lock;
745 	/* Fixed size hash table with 2^8 buckets for MAC filters */
746 	DECLARE_HASHTABLE(mac_filter_hash, 8);
747 	bool has_vlan_filter;
748 
749 	/* VSI stats */
750 	struct rtnl_link_stats64 net_stats;
751 	struct rtnl_link_stats64 net_stats_offsets;
752 	struct i40e_eth_stats eth_stats;
753 	struct i40e_eth_stats eth_stats_offsets;
754 	u32 tx_restart;
755 	u32 tx_busy;
756 	u64 tx_linearize;
757 	u64 tx_force_wb;
758 	u32 rx_buf_failed;
759 	u32 rx_page_failed;
760 
761 	/* These are containers of ring pointers, allocated at run-time */
762 	struct i40e_ring **rx_rings;
763 	struct i40e_ring **tx_rings;
764 	struct i40e_ring **xdp_rings; /* XDP Tx rings */
765 
766 	u32  active_filters;
767 	u32  promisc_threshold;
768 
769 	u16 work_limit;
770 	u16 int_rate_limit;	/* value in usecs */
771 
772 	u16 rss_table_size;	/* HW RSS table size */
773 	u16 rss_size;		/* Allocated RSS queues */
774 	u8  *rss_hkey_user;	/* User configured hash keys */
775 	u8  *rss_lut_user;	/* User configured lookup table entries */
776 
777 
778 	u16 max_frame;
779 	u16 rx_buf_len;
780 
781 	struct bpf_prog *xdp_prog;
782 
783 	/* List of q_vectors allocated to this VSI */
784 	struct i40e_q_vector **q_vectors;
785 	int num_q_vectors;
786 	int base_vector;
787 	bool irqs_ready;
788 
789 	u16 seid;		/* HW index of this VSI (absolute index) */
790 	u16 id;			/* VSI number */
791 	u16 uplink_seid;
792 
793 	u16 base_queue;		/* vsi's first queue in hw array */
794 	u16 alloc_queue_pairs;	/* Allocated Tx/Rx queues */
795 	u16 req_queue_pairs;	/* User requested queue pairs */
796 	u16 num_queue_pairs;	/* Used tx and rx pairs */
797 	u16 num_tx_desc;
798 	u16 num_rx_desc;
799 	enum i40e_vsi_type type;  /* VSI type, e.g., LAN, FCoE, etc */
800 	s16 vf_id;		/* Virtual function ID for SRIOV VSIs */
801 
802 	struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
803 	struct i40e_tc_configuration tc_config;
804 	struct i40e_aqc_vsi_properties_data info;
805 
806 	/* VSI BW limit (absolute across all TCs) */
807 	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */
808 	u8  bw_max_quanta;	/* Max Quanta when BW limit is enabled */
809 
810 	/* Relative TC credits across VSIs */
811 	u8  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
812 	/* TC BW limit credits within VSI */
813 	u16  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
814 	/* TC BW limit max quanta within VSI */
815 	u8  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
816 
817 	struct i40e_pf *back;	/* Backreference to associated PF */
818 	u16 idx;		/* index in pf->vsi[] */
819 	u16 veb_idx;		/* index of VEB parent */
820 	struct kobject *kobj;	/* sysfs object */
821 	bool current_isup;	/* Sync 'link up' logging */
822 	enum i40e_aq_link_speed current_speed;	/* Sync link speed logging */
823 
824 	/* channel specific fields */
825 	u16 cnt_q_avail;	/* num of queues available for channel usage */
826 	u16 orig_rss_size;
827 	u16 current_rss_size;
828 	bool reconfig_rss;
829 
830 	u16 next_base_queue;	/* next queue to be used for channel setup */
831 
832 	struct list_head ch_list;
833 	u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
834 
835 	/* macvlan fields */
836 #define I40E_MAX_MACVLANS		128 /* Max HW vectors - 1 on FVL */
837 #define I40E_MIN_MACVLAN_VECTORS	2   /* Min vectors to enable macvlans */
838 	DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
839 	struct list_head macvlan_list;
840 	int macvlan_cnt;
841 
842 	void *priv;	/* client driver data reference. */
843 
844 	/* VSI specific handlers */
845 	irqreturn_t (*irq_handler)(int irq, void *data);
846 
847 	unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
848 } ____cacheline_internodealigned_in_smp;
849 
850 struct i40e_netdev_priv {
851 	struct i40e_vsi *vsi;
852 };
853 
854 /* struct that defines an interrupt vector */
855 struct i40e_q_vector {
856 	struct i40e_vsi *vsi;
857 
858 	u16 v_idx;		/* index in the vsi->q_vector array. */
859 	u16 reg_idx;		/* register index of the interrupt */
860 
861 	struct napi_struct napi;
862 
863 	struct i40e_ring_container rx;
864 	struct i40e_ring_container tx;
865 
866 	u8 itr_countdown;	/* when 0 should adjust adaptive ITR */
867 	u8 num_ringpairs;	/* total number of ring pairs in vector */
868 
869 	cpumask_t affinity_mask;
870 	struct irq_affinity_notify affinity_notify;
871 
872 	struct rcu_head rcu;	/* to avoid race with update stats on free */
873 	char name[I40E_INT_NAME_STR_LEN];
874 	bool arm_wb_state;
875 } ____cacheline_internodealigned_in_smp;
876 
877 /* lan device */
878 struct i40e_device {
879 	struct list_head list;
880 	struct i40e_pf *pf;
881 };
882 
883 /**
884  * i40e_nvm_version_str - format the NVM version strings
885  * @hw: ptr to the hardware info
886  **/
887 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
888 {
889 	static char buf[32];
890 	u32 full_ver;
891 
892 	full_ver = hw->nvm.oem_ver;
893 
894 	if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
895 		u8 gen, snap;
896 		u16 release;
897 
898 		gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
899 		snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
900 			I40E_OEM_SNAP_SHIFT);
901 		release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
902 
903 		snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
904 	} else {
905 		u8 ver, patch;
906 		u16 build;
907 
908 		ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
909 		build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
910 			 I40E_OEM_VER_BUILD_MASK);
911 		patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
912 
913 		snprintf(buf, sizeof(buf),
914 			 "%x.%02x 0x%x %d.%d.%d",
915 			 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
916 				I40E_NVM_VERSION_HI_SHIFT,
917 			 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
918 				I40E_NVM_VERSION_LO_SHIFT,
919 			 hw->nvm.eetrack, ver, build, patch);
920 	}
921 
922 	return buf;
923 }
924 
925 /**
926  * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
927  * @netdev: the corresponding netdev
928  *
929  * Return the PF struct for the given netdev
930  **/
931 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
932 {
933 	struct i40e_netdev_priv *np = netdev_priv(netdev);
934 	struct i40e_vsi *vsi = np->vsi;
935 
936 	return vsi->back;
937 }
938 
939 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
940 				irqreturn_t (*irq_handler)(int, void *))
941 {
942 	vsi->irq_handler = irq_handler;
943 }
944 
945 /**
946  * i40e_get_fd_cnt_all - get the total FD filter space available
947  * @pf: pointer to the PF struct
948  **/
949 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
950 {
951 	return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
952 }
953 
954 /**
955  * i40e_read_fd_input_set - reads value of flow director input set register
956  * @pf: pointer to the PF struct
957  * @addr: register addr
958  *
959  * This function reads value of flow director input set register
960  * specified by 'addr' (which is specific to flow-type)
961  **/
962 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
963 {
964 	u64 val;
965 
966 	val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
967 	val <<= 32;
968 	val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
969 
970 	return val;
971 }
972 
973 /**
974  * i40e_write_fd_input_set - writes value into flow director input set register
975  * @pf: pointer to the PF struct
976  * @addr: register addr
977  * @val: value to be written
978  *
979  * This function writes specified value to the register specified by 'addr'.
980  * This register is input set register based on flow-type.
981  **/
982 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
983 					   u16 addr, u64 val)
984 {
985 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
986 			  (u32)(val >> 32));
987 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
988 			  (u32)(val & 0xFFFFFFFFULL));
989 }
990 
991 /* needed by i40e_ethtool.c */
992 int i40e_up(struct i40e_vsi *vsi);
993 void i40e_down(struct i40e_vsi *vsi);
994 extern const char i40e_driver_name[];
995 extern const char i40e_driver_version_str[];
996 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
997 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
998 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
999 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1000 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1001 		       u16 rss_table_size, u16 rss_size);
1002 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1003 /**
1004  * i40e_find_vsi_by_type - Find and return Flow Director VSI
1005  * @pf: PF to search for VSI
1006  * @type: Value indicating type of VSI we are looking for
1007  **/
1008 static inline struct i40e_vsi *
1009 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1010 {
1011 	int i;
1012 
1013 	for (i = 0; i < pf->num_alloc_vsi; i++) {
1014 		struct i40e_vsi *vsi = pf->vsi[i];
1015 
1016 		if (vsi && vsi->type == type)
1017 			return vsi;
1018 	}
1019 
1020 	return NULL;
1021 }
1022 void i40e_update_stats(struct i40e_vsi *vsi);
1023 void i40e_update_veb_stats(struct i40e_veb *veb);
1024 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1025 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1026 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1027 				    bool printconfig);
1028 
1029 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1030 		      struct i40e_fdir_filter *input, bool add);
1031 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1032 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1033 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1034 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1035 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1036 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1037 void i40e_set_ethtool_ops(struct net_device *netdev);
1038 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1039 					const u8 *macaddr, s16 vlan);
1040 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1041 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1042 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1043 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1044 				u16 uplink, u32 param1);
1045 int i40e_vsi_release(struct i40e_vsi *vsi);
1046 void i40e_service_event_schedule(struct i40e_pf *pf);
1047 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1048 				  u8 *msg, u16 len);
1049 
1050 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1051 			   bool enable);
1052 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1053 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1054 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1055 void i40e_vsi_stop_rings_no_wait(struct  i40e_vsi *vsi);
1056 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1057 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1058 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1059 				u16 downlink_seid, u8 enabled_tc);
1060 void i40e_veb_release(struct i40e_veb *veb);
1061 
1062 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1063 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1064 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1065 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1066 void i40e_pf_reset_stats(struct i40e_pf *pf);
1067 #ifdef CONFIG_DEBUG_FS
1068 void i40e_dbg_pf_init(struct i40e_pf *pf);
1069 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1070 void i40e_dbg_init(void);
1071 void i40e_dbg_exit(void);
1072 #else
1073 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1074 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1075 static inline void i40e_dbg_init(void) {}
1076 static inline void i40e_dbg_exit(void) {}
1077 #endif /* CONFIG_DEBUG_FS*/
1078 /* needed by client drivers */
1079 int i40e_lan_add_device(struct i40e_pf *pf);
1080 int i40e_lan_del_device(struct i40e_pf *pf);
1081 void i40e_client_subtask(struct i40e_pf *pf);
1082 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1083 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1084 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1085 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1086 void i40e_client_update_msix_info(struct i40e_pf *pf);
1087 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1088 /**
1089  * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1090  * @vsi: pointer to a vsi
1091  * @vector: enable a particular Hw Interrupt vector, without base_vector
1092  **/
1093 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1094 {
1095 	struct i40e_pf *pf = vsi->back;
1096 	struct i40e_hw *hw = &pf->hw;
1097 	u32 val;
1098 
1099 	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1100 	      I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1101 	      (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1102 	wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1103 	/* skip the flush */
1104 }
1105 
1106 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1107 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1108 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1109 int i40e_open(struct net_device *netdev);
1110 int i40e_close(struct net_device *netdev);
1111 int i40e_vsi_open(struct i40e_vsi *vsi);
1112 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1113 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1114 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1115 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1116 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1117 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1118 					    const u8 *macaddr);
1119 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1120 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1121 int i40e_count_filters(struct i40e_vsi *vsi);
1122 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1123 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1124 #ifdef CONFIG_I40E_DCB
1125 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1126 			   struct i40e_dcbx_config *old_cfg,
1127 			   struct i40e_dcbx_config *new_cfg);
1128 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1129 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1130 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1131 			    struct i40e_dcbx_config *old_cfg,
1132 			    struct i40e_dcbx_config *new_cfg);
1133 #endif /* CONFIG_I40E_DCB */
1134 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1135 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1136 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1137 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1138 void i40e_ptp_set_increment(struct i40e_pf *pf);
1139 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1140 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1141 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1142 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1143 void i40e_ptp_init(struct i40e_pf *pf);
1144 void i40e_ptp_stop(struct i40e_pf *pf);
1145 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1146 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1147 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1148 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1149 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1150 
1151 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1152 
1153 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1154 {
1155 	return !!READ_ONCE(vsi->xdp_prog);
1156 }
1157 
1158 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1159 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1160 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1161 			      struct i40e_cloud_filter *filter,
1162 			      bool add);
1163 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1164 				      struct i40e_cloud_filter *filter,
1165 				      bool add);
1166 #endif /* _I40E_H_ */
1167