1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_bridge.h> 31 #include <linux/clocksource.h> 32 #include <linux/net_tstamp.h> 33 #include <linux/ptp_clock_kernel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/xdp_sock.h> 38 #include "i40e_type.h" 39 #include "i40e_prototype.h" 40 #include "i40e_client.h" 41 #include <linux/avf/virtchnl.h> 42 #include "i40e_virtchnl_pf.h" 43 #include "i40e_txrx.h" 44 #include "i40e_dcb.h" 45 46 /* Useful i40e defaults */ 47 #define I40E_MAX_VEB 16 48 49 #define I40E_MAX_NUM_DESCRIPTORS 4096 50 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 51 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 52 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 53 #define I40E_MIN_NUM_DESCRIPTORS 64 54 #define I40E_MIN_MSIX 2 55 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 56 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 57 /* max 16 qps */ 58 #define i40e_default_queues_per_vmdq(pf) \ 59 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 60 #define I40E_DEFAULT_QUEUES_PER_VF 4 61 #define I40E_MAX_VF_QUEUES 16 62 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 63 #define i40e_pf_get_max_q_per_tc(pf) \ 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 65 #define I40E_FDIR_RING 0 66 #define I40E_FDIR_RING_COUNT 32 67 #define I40E_MAX_AQ_BUF_SIZE 4096 68 #define I40E_AQ_LEN 256 69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 70 #define I40E_MAX_USER_PRIORITY 8 71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 72 #define I40E_DEFAULT_MSG_ENABLE 4 73 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 74 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 75 76 #define I40E_NVM_VERSION_LO_SHIFT 0 77 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 78 #define I40E_NVM_VERSION_HI_SHIFT 12 79 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 80 #define I40E_OEM_VER_BUILD_MASK 0xffff 81 #define I40E_OEM_VER_PATCH_MASK 0xff 82 #define I40E_OEM_VER_BUILD_SHIFT 8 83 #define I40E_OEM_VER_SHIFT 24 84 #define I40E_PHY_DEBUG_ALL \ 85 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 86 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 87 88 #define I40E_OEM_EETRACK_ID 0xffffffff 89 #define I40E_OEM_GEN_SHIFT 24 90 #define I40E_OEM_SNAP_MASK 0x00ff0000 91 #define I40E_OEM_SNAP_SHIFT 16 92 #define I40E_OEM_RELEASE_MASK 0x0000ffff 93 94 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 95 #define I40E_CURRENT_NVM_VERSION_HI 0x2 96 #define I40E_CURRENT_NVM_VERSION_LO 0x40 97 98 #define I40E_RX_DESC(R, i) \ 99 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 100 #define I40E_TX_DESC(R, i) \ 101 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 102 #define I40E_TX_CTXTDESC(R, i) \ 103 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 104 #define I40E_TX_FDIRDESC(R, i) \ 105 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 106 107 /* default to trying for four seconds */ 108 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 109 110 /* BW rate limiting */ 111 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 112 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 113 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 114 115 /* driver state flags */ 116 enum i40e_state_t { 117 __I40E_TESTING, 118 __I40E_CONFIG_BUSY, 119 __I40E_CONFIG_DONE, 120 __I40E_DOWN, 121 __I40E_SERVICE_SCHED, 122 __I40E_ADMINQ_EVENT_PENDING, 123 __I40E_MDD_EVENT_PENDING, 124 __I40E_VFLR_EVENT_PENDING, 125 __I40E_RESET_RECOVERY_PENDING, 126 __I40E_TIMEOUT_RECOVERY_PENDING, 127 __I40E_MISC_IRQ_REQUESTED, 128 __I40E_RESET_INTR_RECEIVED, 129 __I40E_REINIT_REQUESTED, 130 __I40E_PF_RESET_REQUESTED, 131 __I40E_CORE_RESET_REQUESTED, 132 __I40E_GLOBAL_RESET_REQUESTED, 133 __I40E_EMP_RESET_REQUESTED, 134 __I40E_EMP_RESET_INTR_RECEIVED, 135 __I40E_SUSPENDED, 136 __I40E_PTP_TX_IN_PROGRESS, 137 __I40E_BAD_EEPROM, 138 __I40E_DOWN_REQUESTED, 139 __I40E_FD_FLUSH_REQUESTED, 140 __I40E_FD_ATR_AUTO_DISABLED, 141 __I40E_FD_SB_AUTO_DISABLED, 142 __I40E_RESET_FAILED, 143 __I40E_PORT_SUSPENDED, 144 __I40E_VF_DISABLE, 145 __I40E_MACVLAN_SYNC_PENDING, 146 __I40E_UDP_FILTER_SYNC_PENDING, 147 __I40E_TEMP_LINK_POLLING, 148 __I40E_CLIENT_SERVICE_REQUESTED, 149 __I40E_CLIENT_L2_CHANGE, 150 __I40E_CLIENT_RESET, 151 __I40E_VIRTCHNL_OP_PENDING, 152 /* This must be last as it determines the size of the BITMAP */ 153 __I40E_STATE_SIZE__, 154 }; 155 156 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 157 158 /* VSI state flags */ 159 enum i40e_vsi_state_t { 160 __I40E_VSI_DOWN, 161 __I40E_VSI_NEEDS_RESTART, 162 __I40E_VSI_SYNCING_FILTERS, 163 __I40E_VSI_OVERFLOW_PROMISC, 164 __I40E_VSI_REINIT_REQUESTED, 165 __I40E_VSI_DOWN_REQUESTED, 166 /* This must be last as it determines the size of the BITMAP */ 167 __I40E_VSI_STATE_SIZE__, 168 }; 169 170 enum i40e_interrupt_policy { 171 I40E_INTERRUPT_BEST_CASE, 172 I40E_INTERRUPT_MEDIUM, 173 I40E_INTERRUPT_LOWEST 174 }; 175 176 struct i40e_lump_tracking { 177 u16 num_entries; 178 u16 search_hint; 179 u16 list[0]; 180 #define I40E_PILE_VALID_BIT 0x8000 181 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 182 }; 183 184 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 186 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 187 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 189 190 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 191 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 193 194 enum i40e_fd_stat_idx { 195 I40E_FD_STAT_ATR, 196 I40E_FD_STAT_SB, 197 I40E_FD_STAT_ATR_TUNNEL, 198 I40E_FD_STAT_PF_COUNT 199 }; 200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 201 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 203 #define I40E_FD_SB_STAT_IDX(pf_id) \ 204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 207 208 /* The following structure contains the data parsed from the user-defined 209 * field of the ethtool_rx_flow_spec structure. 210 */ 211 struct i40e_rx_flow_userdef { 212 bool flex_filter; 213 u16 flex_word; 214 u16 flex_offset; 215 }; 216 217 struct i40e_fdir_filter { 218 struct hlist_node fdir_node; 219 /* filter ipnut set */ 220 u8 flow_type; 221 u8 ip4_proto; 222 /* TX packet view of src and dst */ 223 __be32 dst_ip; 224 __be32 src_ip; 225 __be16 src_port; 226 __be16 dst_port; 227 __be32 sctp_v_tag; 228 229 /* Flexible data to match within the packet payload */ 230 __be16 flex_word; 231 u16 flex_offset; 232 bool flex_filter; 233 234 /* filter control */ 235 u16 q_index; 236 u8 flex_off; 237 u8 pctype; 238 u16 dest_vsi; 239 u8 dest_ctl; 240 u8 fd_status; 241 u16 cnt_index; 242 u32 fd_id; 243 }; 244 245 #define I40E_CLOUD_FIELD_OMAC 0x01 246 #define I40E_CLOUD_FIELD_IMAC 0x02 247 #define I40E_CLOUD_FIELD_IVLAN 0x04 248 #define I40E_CLOUD_FIELD_TEN_ID 0x08 249 #define I40E_CLOUD_FIELD_IIP 0x10 250 251 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 252 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 253 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 254 I40E_CLOUD_FIELD_IVLAN) 255 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_TEN_ID) 257 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 258 I40E_CLOUD_FIELD_IMAC | \ 259 I40E_CLOUD_FIELD_TEN_ID) 260 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 261 I40E_CLOUD_FIELD_IVLAN | \ 262 I40E_CLOUD_FIELD_TEN_ID) 263 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 264 265 struct i40e_cloud_filter { 266 struct hlist_node cloud_node; 267 unsigned long cookie; 268 /* cloud filter input set follows */ 269 u8 dst_mac[ETH_ALEN]; 270 u8 src_mac[ETH_ALEN]; 271 __be16 vlan_id; 272 u16 seid; /* filter control */ 273 __be16 dst_port; 274 __be16 src_port; 275 u32 tenant_id; 276 union { 277 struct { 278 struct in_addr dst_ip; 279 struct in_addr src_ip; 280 } v4; 281 struct { 282 struct in6_addr dst_ip6; 283 struct in6_addr src_ip6; 284 } v6; 285 } ip; 286 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 287 #define src_ipv6 ip.v6.src_ip6.s6_addr32 288 #define dst_ipv4 ip.v4.dst_ip.s_addr 289 #define src_ipv4 ip.v4.src_ip.s_addr 290 u16 n_proto; /* Ethernet Protocol */ 291 u8 ip_proto; /* IPPROTO value */ 292 u8 flags; 293 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 294 u8 tunnel_type; 295 }; 296 297 #define I40E_ETH_P_LLDP 0x88cc 298 299 #define I40E_DCB_PRIO_TYPE_STRICT 0 300 #define I40E_DCB_PRIO_TYPE_ETS 1 301 #define I40E_DCB_STRICT_PRIO_CREDITS 127 302 /* DCB per TC information data structure */ 303 struct i40e_tc_info { 304 u16 qoffset; /* Queue offset from base queue */ 305 u16 qcount; /* Total Queues */ 306 u8 netdev_tc; /* Netdev TC index if netdev associated */ 307 }; 308 309 /* TC configuration data structure */ 310 struct i40e_tc_configuration { 311 u8 numtc; /* Total number of enabled TCs */ 312 u8 enabled_tc; /* TC map */ 313 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 314 }; 315 316 #define I40E_UDP_PORT_INDEX_UNUSED 255 317 struct i40e_udp_port_config { 318 /* AdminQ command interface expects port number in Host byte order */ 319 u16 port; 320 u8 type; 321 u8 filter_index; 322 }; 323 324 #define I40_DDP_FLASH_REGION 100 325 #define I40E_PROFILE_INFO_SIZE 48 326 #define I40E_MAX_PROFILE_NUM 16 327 #define I40E_PROFILE_LIST_SIZE \ 328 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 329 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 330 #define I40E_DDP_PROFILE_NAME_MAX 64 331 332 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 333 bool is_add); 334 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 335 336 struct i40e_ddp_profile_list { 337 u32 p_count; 338 struct i40e_profile_info p_info[0]; 339 }; 340 341 struct i40e_ddp_old_profile_list { 342 struct list_head list; 343 size_t old_ddp_size; 344 u8 old_ddp_buf[0]; 345 }; 346 347 /* macros related to FLX_PIT */ 348 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 349 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 350 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 351 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 352 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 353 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 354 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 355 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 356 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 357 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 358 I40E_FLEX_SET_FSIZE(fsize) | \ 359 I40E_FLEX_SET_SRC_WORD(src)) 360 361 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 362 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 363 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 364 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 365 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 366 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 367 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 368 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 369 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 370 371 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 372 373 /* macros related to GLQF_ORT */ 374 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 375 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 376 I40E_GLQF_ORT_PIT_INDX_MASK) 377 378 #define I40E_ORT_SET_COUNT(count) (((count) << \ 379 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 380 I40E_GLQF_ORT_FIELD_CNT_MASK) 381 382 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 383 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 384 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 385 386 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 387 I40E_ORT_SET_COUNT(count) | \ 388 I40E_ORT_SET_PAYLOAD(payload)) 389 390 #define I40E_L3_GLQF_ORT_IDX 34 391 #define I40E_L4_GLQF_ORT_IDX 35 392 393 /* Flex PIT register index */ 394 #define I40E_FLEX_PIT_IDX_START_L2 0 395 #define I40E_FLEX_PIT_IDX_START_L3 3 396 #define I40E_FLEX_PIT_IDX_START_L4 6 397 398 #define I40E_FLEX_PIT_TABLE_SIZE 3 399 400 #define I40E_FLEX_DEST_UNUSED 63 401 402 #define I40E_FLEX_INDEX_ENTRIES 8 403 404 /* Flex MASK to disable all flexible entries */ 405 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 406 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 407 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 408 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 409 410 struct i40e_flex_pit { 411 struct list_head list; 412 u16 src_offset; 413 u8 pit_index; 414 }; 415 416 struct i40e_channel { 417 struct list_head list; 418 bool initialized; 419 u8 type; 420 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 421 u16 stat_counter_idx; 422 u16 base_queue; 423 u16 num_queue_pairs; /* Requested by user */ 424 u16 seid; 425 426 u8 enabled_tc; 427 struct i40e_aqc_vsi_properties_data info; 428 429 u64 max_tx_rate; 430 431 /* track this channel belongs to which VSI */ 432 struct i40e_vsi *parent_vsi; 433 }; 434 435 /* struct that defines the Ethernet device */ 436 struct i40e_pf { 437 struct pci_dev *pdev; 438 struct i40e_hw hw; 439 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 440 struct msix_entry *msix_entries; 441 bool fc_autoneg_status; 442 443 u16 eeprom_version; 444 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 445 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 446 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 447 u16 num_req_vfs; /* num VFs requested for this PF */ 448 u16 num_vf_qps; /* num queue pairs per VF */ 449 u16 num_lan_qps; /* num lan queues this PF has set up */ 450 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 451 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 452 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 453 int iwarp_base_vector; 454 int queues_left; /* queues left unclaimed */ 455 u16 alloc_rss_size; /* allocated RSS queues */ 456 u16 rss_size_max; /* HW defined max RSS queues */ 457 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 458 u16 num_alloc_vsi; /* num VSIs this driver supports */ 459 u8 atr_sample_rate; 460 bool wol_en; 461 462 struct hlist_head fdir_filter_list; 463 u16 fdir_pf_active_filters; 464 unsigned long fd_flush_timestamp; 465 u32 fd_flush_cnt; 466 u32 fd_add_err; 467 u32 fd_atr_cnt; 468 469 /* Book-keeping of side-band filter count per flow-type. 470 * This is used to detect and handle input set changes for 471 * respective flow-type. 472 */ 473 u16 fd_tcp4_filter_cnt; 474 u16 fd_udp4_filter_cnt; 475 u16 fd_sctp4_filter_cnt; 476 u16 fd_ip4_filter_cnt; 477 478 /* Flexible filter table values that need to be programmed into 479 * hardware, which expects L3 and L4 to be programmed separately. We 480 * need to ensure that the values are in ascended order and don't have 481 * duplicates, so we track each L3 and L4 values in separate lists. 482 */ 483 struct list_head l3_flex_pit_list; 484 struct list_head l4_flex_pit_list; 485 486 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 487 u16 pending_udp_bitmap; 488 489 struct hlist_head cloud_filter_list; 490 u16 num_cloud_filters; 491 492 enum i40e_interrupt_policy int_policy; 493 u16 rx_itr_default; 494 u16 tx_itr_default; 495 u32 msg_enable; 496 char int_name[I40E_INT_NAME_STR_LEN]; 497 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 498 unsigned long service_timer_period; 499 unsigned long service_timer_previous; 500 struct timer_list service_timer; 501 struct work_struct service_task; 502 503 u32 hw_features; 504 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 505 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 506 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 507 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 508 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 509 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 510 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 511 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 512 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 513 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 514 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 515 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 516 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 517 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 518 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 519 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 520 #define I40E_HW_STOP_FW_LLDP BIT(16) 521 #define I40E_HW_PORT_ID_VALID BIT(17) 522 #define I40E_HW_RESTART_AUTONEG BIT(18) 523 524 u32 flags; 525 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 526 #define I40E_FLAG_MSI_ENABLED BIT(1) 527 #define I40E_FLAG_MSIX_ENABLED BIT(2) 528 #define I40E_FLAG_RSS_ENABLED BIT(3) 529 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 530 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 531 #define I40E_FLAG_DCB_CAPABLE BIT(6) 532 #define I40E_FLAG_DCB_ENABLED BIT(7) 533 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 534 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 535 #define I40E_FLAG_MFP_ENABLED BIT(10) 536 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 537 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 538 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 539 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 540 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 541 #define I40E_FLAG_LEGACY_RX BIT(16) 542 #define I40E_FLAG_PTP BIT(17) 543 #define I40E_FLAG_IWARP_ENABLED BIT(18) 544 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 545 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 546 #define I40E_FLAG_TC_MQPRIO BIT(21) 547 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 548 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 549 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 550 #define I40E_FLAG_RS_FEC BIT(25) 551 #define I40E_FLAG_BASE_R_FEC BIT(26) 552 553 struct i40e_client_instance *cinst; 554 bool stat_offsets_loaded; 555 struct i40e_hw_port_stats stats; 556 struct i40e_hw_port_stats stats_offsets; 557 u32 tx_timeout_count; 558 u32 tx_timeout_recovery_level; 559 unsigned long tx_timeout_last_recovery; 560 u32 tx_sluggish_count; 561 u32 hw_csum_rx_error; 562 u32 led_status; 563 u16 corer_count; /* Core reset count */ 564 u16 globr_count; /* Global reset count */ 565 u16 empr_count; /* EMP reset count */ 566 u16 pfr_count; /* PF reset count */ 567 u16 sw_int_count; /* SW interrupt count */ 568 569 struct mutex switch_mutex; 570 u16 lan_vsi; /* our default LAN VSI */ 571 u16 lan_veb; /* initial relay, if exists */ 572 #define I40E_NO_VEB 0xffff 573 #define I40E_NO_VSI 0xffff 574 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 575 struct i40e_vsi **vsi; 576 struct i40e_veb *veb[I40E_MAX_VEB]; 577 578 struct i40e_lump_tracking *qp_pile; 579 struct i40e_lump_tracking *irq_pile; 580 581 /* switch config info */ 582 u16 pf_seid; 583 u16 main_vsi_seid; 584 u16 mac_seid; 585 struct kobject *switch_kobj; 586 #ifdef CONFIG_DEBUG_FS 587 struct dentry *i40e_dbg_pf; 588 #endif /* CONFIG_DEBUG_FS */ 589 bool cur_promisc; 590 591 u16 instance; /* A unique number per i40e_pf instance in the system */ 592 593 /* sr-iov config info */ 594 struct i40e_vf *vf; 595 int num_alloc_vfs; /* actual number of VFs allocated */ 596 u32 vf_aq_requests; 597 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 598 599 /* DCBx/DCBNL capability for PF that indicates 600 * whether DCBx is managed by firmware or host 601 * based agent (LLDPAD). Also, indicates what 602 * flavor of DCBx protocol (IEEE/CEE) is supported 603 * by the device. For now we're supporting IEEE 604 * mode only. 605 */ 606 u16 dcbx_cap; 607 608 struct i40e_filter_control_settings filter_settings; 609 610 struct ptp_clock *ptp_clock; 611 struct ptp_clock_info ptp_caps; 612 struct sk_buff *ptp_tx_skb; 613 unsigned long ptp_tx_start; 614 struct hwtstamp_config tstamp_config; 615 struct timespec64 ptp_prev_hw_time; 616 ktime_t ptp_reset_start; 617 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 618 u32 ptp_adj_mult; 619 u32 tx_hwtstamp_timeouts; 620 u32 tx_hwtstamp_skipped; 621 u32 rx_hwtstamp_cleared; 622 u32 latch_event_flags; 623 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 624 unsigned long latch_events[4]; 625 bool ptp_tx; 626 bool ptp_rx; 627 u16 rss_table_size; /* HW RSS table size */ 628 u32 max_bw; 629 u32 min_bw; 630 631 u32 ioremap_len; 632 u32 fd_inv; 633 u16 phy_led_val; 634 635 u16 override_q_count; 636 u16 last_sw_conf_flags; 637 u16 last_sw_conf_valid_flags; 638 /* List to keep previous DDP profiles to be rolled back in the future */ 639 struct list_head ddp_old_prof; 640 }; 641 642 /** 643 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 644 * @macaddr: the MAC Address as the base key 645 * 646 * Simply copies the address and returns it as a u64 for hashing 647 **/ 648 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 649 { 650 u64 key = 0; 651 652 ether_addr_copy((u8 *)&key, macaddr); 653 return key; 654 } 655 656 enum i40e_filter_state { 657 I40E_FILTER_INVALID = 0, /* Invalid state */ 658 I40E_FILTER_NEW, /* New, not sent to FW yet */ 659 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 660 I40E_FILTER_FAILED, /* Rejected by FW */ 661 I40E_FILTER_REMOVE, /* To be removed */ 662 /* There is no 'removed' state; the filter struct is freed */ 663 }; 664 struct i40e_mac_filter { 665 struct hlist_node hlist; 666 u8 macaddr[ETH_ALEN]; 667 #define I40E_VLAN_ANY -1 668 s16 vlan; 669 enum i40e_filter_state state; 670 }; 671 672 /* Wrapper structure to keep track of filters while we are preparing to send 673 * firmware commands. We cannot send firmware commands while holding a 674 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 675 * a separate structure, which will track the state change and update the real 676 * filter while under lock. We can't simply hold the filters in a separate 677 * list, as this opens a window for a race condition when adding new MAC 678 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 679 */ 680 struct i40e_new_mac_filter { 681 struct hlist_node hlist; 682 struct i40e_mac_filter *f; 683 684 /* Track future changes to state separately */ 685 enum i40e_filter_state state; 686 }; 687 688 struct i40e_veb { 689 struct i40e_pf *pf; 690 u16 idx; 691 u16 veb_idx; /* index of VEB parent */ 692 u16 seid; 693 u16 uplink_seid; 694 u16 stats_idx; /* index of VEB parent */ 695 u8 enabled_tc; 696 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 697 u16 flags; 698 u16 bw_limit; 699 u8 bw_max_quanta; 700 bool is_abs_credits; 701 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 702 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 703 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 704 struct kobject *kobj; 705 bool stat_offsets_loaded; 706 struct i40e_eth_stats stats; 707 struct i40e_eth_stats stats_offsets; 708 struct i40e_veb_tc_stats tc_stats; 709 struct i40e_veb_tc_stats tc_stats_offsets; 710 }; 711 712 /* struct that defines a VSI, associated with a dev */ 713 struct i40e_vsi { 714 struct net_device *netdev; 715 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 716 bool netdev_registered; 717 bool stat_offsets_loaded; 718 719 u32 current_netdev_flags; 720 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 721 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 722 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 723 unsigned long flags; 724 725 /* Per VSI lock to protect elements/hash (MAC filter) */ 726 spinlock_t mac_filter_hash_lock; 727 /* Fixed size hash table with 2^8 buckets for MAC filters */ 728 DECLARE_HASHTABLE(mac_filter_hash, 8); 729 bool has_vlan_filter; 730 731 /* VSI stats */ 732 struct rtnl_link_stats64 net_stats; 733 struct rtnl_link_stats64 net_stats_offsets; 734 struct i40e_eth_stats eth_stats; 735 struct i40e_eth_stats eth_stats_offsets; 736 u32 tx_restart; 737 u32 tx_busy; 738 u64 tx_linearize; 739 u64 tx_force_wb; 740 u32 rx_buf_failed; 741 u32 rx_page_failed; 742 743 /* These are containers of ring pointers, allocated at run-time */ 744 struct i40e_ring **rx_rings; 745 struct i40e_ring **tx_rings; 746 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 747 748 u32 active_filters; 749 u32 promisc_threshold; 750 751 u16 work_limit; 752 u16 int_rate_limit; /* value in usecs */ 753 754 u16 rss_table_size; /* HW RSS table size */ 755 u16 rss_size; /* Allocated RSS queues */ 756 u8 *rss_hkey_user; /* User configured hash keys */ 757 u8 *rss_lut_user; /* User configured lookup table entries */ 758 759 760 u16 max_frame; 761 u16 rx_buf_len; 762 763 struct bpf_prog *xdp_prog; 764 765 /* List of q_vectors allocated to this VSI */ 766 struct i40e_q_vector **q_vectors; 767 int num_q_vectors; 768 int base_vector; 769 bool irqs_ready; 770 771 u16 seid; /* HW index of this VSI (absolute index) */ 772 u16 id; /* VSI number */ 773 u16 uplink_seid; 774 775 u16 base_queue; /* vsi's first queue in hw array */ 776 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 777 u16 req_queue_pairs; /* User requested queue pairs */ 778 u16 num_queue_pairs; /* Used tx and rx pairs */ 779 u16 num_desc; 780 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 781 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 782 783 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 784 struct i40e_tc_configuration tc_config; 785 struct i40e_aqc_vsi_properties_data info; 786 787 /* VSI BW limit (absolute across all TCs) */ 788 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 789 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 790 791 /* Relative TC credits across VSIs */ 792 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 793 /* TC BW limit credits within VSI */ 794 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 795 /* TC BW limit max quanta within VSI */ 796 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 797 798 struct i40e_pf *back; /* Backreference to associated PF */ 799 u16 idx; /* index in pf->vsi[] */ 800 u16 veb_idx; /* index of VEB parent */ 801 struct kobject *kobj; /* sysfs object */ 802 bool current_isup; /* Sync 'link up' logging */ 803 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 804 805 /* channel specific fields */ 806 u16 cnt_q_avail; /* num of queues available for channel usage */ 807 u16 orig_rss_size; 808 u16 current_rss_size; 809 bool reconfig_rss; 810 811 u16 next_base_queue; /* next queue to be used for channel setup */ 812 813 struct list_head ch_list; 814 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 815 816 void *priv; /* client driver data reference. */ 817 818 /* VSI specific handlers */ 819 irqreturn_t (*irq_handler)(int irq, void *data); 820 821 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 822 } ____cacheline_internodealigned_in_smp; 823 824 struct i40e_netdev_priv { 825 struct i40e_vsi *vsi; 826 }; 827 828 /* struct that defines an interrupt vector */ 829 struct i40e_q_vector { 830 struct i40e_vsi *vsi; 831 832 u16 v_idx; /* index in the vsi->q_vector array. */ 833 u16 reg_idx; /* register index of the interrupt */ 834 835 struct napi_struct napi; 836 837 struct i40e_ring_container rx; 838 struct i40e_ring_container tx; 839 840 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 841 u8 num_ringpairs; /* total number of ring pairs in vector */ 842 843 cpumask_t affinity_mask; 844 struct irq_affinity_notify affinity_notify; 845 846 struct rcu_head rcu; /* to avoid race with update stats on free */ 847 char name[I40E_INT_NAME_STR_LEN]; 848 bool arm_wb_state; 849 } ____cacheline_internodealigned_in_smp; 850 851 /* lan device */ 852 struct i40e_device { 853 struct list_head list; 854 struct i40e_pf *pf; 855 }; 856 857 /** 858 * i40e_nvm_version_str - format the NVM version strings 859 * @hw: ptr to the hardware info 860 **/ 861 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 862 { 863 static char buf[32]; 864 u32 full_ver; 865 866 full_ver = hw->nvm.oem_ver; 867 868 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 869 u8 gen, snap; 870 u16 release; 871 872 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 873 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 874 I40E_OEM_SNAP_SHIFT); 875 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 876 877 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 878 } else { 879 u8 ver, patch; 880 u16 build; 881 882 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 883 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 884 I40E_OEM_VER_BUILD_MASK); 885 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 886 887 snprintf(buf, sizeof(buf), 888 "%x.%02x 0x%x %d.%d.%d", 889 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 890 I40E_NVM_VERSION_HI_SHIFT, 891 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 892 I40E_NVM_VERSION_LO_SHIFT, 893 hw->nvm.eetrack, ver, build, patch); 894 } 895 896 return buf; 897 } 898 899 /** 900 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 901 * @netdev: the corresponding netdev 902 * 903 * Return the PF struct for the given netdev 904 **/ 905 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 906 { 907 struct i40e_netdev_priv *np = netdev_priv(netdev); 908 struct i40e_vsi *vsi = np->vsi; 909 910 return vsi->back; 911 } 912 913 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 914 irqreturn_t (*irq_handler)(int, void *)) 915 { 916 vsi->irq_handler = irq_handler; 917 } 918 919 /** 920 * i40e_get_fd_cnt_all - get the total FD filter space available 921 * @pf: pointer to the PF struct 922 **/ 923 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 924 { 925 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 926 } 927 928 /** 929 * i40e_read_fd_input_set - reads value of flow director input set register 930 * @pf: pointer to the PF struct 931 * @addr: register addr 932 * 933 * This function reads value of flow director input set register 934 * specified by 'addr' (which is specific to flow-type) 935 **/ 936 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 937 { 938 u64 val; 939 940 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 941 val <<= 32; 942 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 943 944 return val; 945 } 946 947 /** 948 * i40e_write_fd_input_set - writes value into flow director input set register 949 * @pf: pointer to the PF struct 950 * @addr: register addr 951 * @val: value to be written 952 * 953 * This function writes specified value to the register specified by 'addr'. 954 * This register is input set register based on flow-type. 955 **/ 956 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 957 u16 addr, u64 val) 958 { 959 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 960 (u32)(val >> 32)); 961 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 962 (u32)(val & 0xFFFFFFFFULL)); 963 } 964 965 /* needed by i40e_ethtool.c */ 966 int i40e_up(struct i40e_vsi *vsi); 967 void i40e_down(struct i40e_vsi *vsi); 968 extern const char i40e_driver_name[]; 969 extern const char i40e_driver_version_str[]; 970 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 971 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 972 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 973 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 974 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 975 u16 rss_table_size, u16 rss_size); 976 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 977 /** 978 * i40e_find_vsi_by_type - Find and return Flow Director VSI 979 * @pf: PF to search for VSI 980 * @type: Value indicating type of VSI we are looking for 981 **/ 982 static inline struct i40e_vsi * 983 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 984 { 985 int i; 986 987 for (i = 0; i < pf->num_alloc_vsi; i++) { 988 struct i40e_vsi *vsi = pf->vsi[i]; 989 990 if (vsi && vsi->type == type) 991 return vsi; 992 } 993 994 return NULL; 995 } 996 void i40e_update_stats(struct i40e_vsi *vsi); 997 void i40e_update_eth_stats(struct i40e_vsi *vsi); 998 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 999 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1000 bool printconfig); 1001 1002 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1003 struct i40e_fdir_filter *input, bool add); 1004 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1005 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1006 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1007 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1008 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1009 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1010 void i40e_set_ethtool_ops(struct net_device *netdev); 1011 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1012 const u8 *macaddr, s16 vlan); 1013 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1014 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1015 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1016 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1017 u16 uplink, u32 param1); 1018 int i40e_vsi_release(struct i40e_vsi *vsi); 1019 void i40e_service_event_schedule(struct i40e_pf *pf); 1020 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1021 u8 *msg, u16 len); 1022 1023 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1024 bool enable); 1025 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1026 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1027 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1028 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1029 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1030 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1031 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1032 u16 downlink_seid, u8 enabled_tc); 1033 void i40e_veb_release(struct i40e_veb *veb); 1034 1035 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1036 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1037 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1038 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1039 void i40e_pf_reset_stats(struct i40e_pf *pf); 1040 #ifdef CONFIG_DEBUG_FS 1041 void i40e_dbg_pf_init(struct i40e_pf *pf); 1042 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1043 void i40e_dbg_init(void); 1044 void i40e_dbg_exit(void); 1045 #else 1046 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1047 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1048 static inline void i40e_dbg_init(void) {} 1049 static inline void i40e_dbg_exit(void) {} 1050 #endif /* CONFIG_DEBUG_FS*/ 1051 /* needed by client drivers */ 1052 int i40e_lan_add_device(struct i40e_pf *pf); 1053 int i40e_lan_del_device(struct i40e_pf *pf); 1054 void i40e_client_subtask(struct i40e_pf *pf); 1055 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1056 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1057 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1058 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1059 void i40e_client_update_msix_info(struct i40e_pf *pf); 1060 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1061 /** 1062 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1063 * @vsi: pointer to a vsi 1064 * @vector: enable a particular Hw Interrupt vector, without base_vector 1065 **/ 1066 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1067 { 1068 struct i40e_pf *pf = vsi->back; 1069 struct i40e_hw *hw = &pf->hw; 1070 u32 val; 1071 1072 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1073 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1074 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1075 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1076 /* skip the flush */ 1077 } 1078 1079 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1080 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1081 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1082 int i40e_open(struct net_device *netdev); 1083 int i40e_close(struct net_device *netdev); 1084 int i40e_vsi_open(struct i40e_vsi *vsi); 1085 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1086 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1087 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1088 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1089 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1090 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1091 const u8 *macaddr); 1092 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1093 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1094 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1095 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1096 #ifdef CONFIG_I40E_DCB 1097 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1098 struct i40e_dcbx_config *old_cfg, 1099 struct i40e_dcbx_config *new_cfg); 1100 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1101 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1102 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1103 struct i40e_dcbx_config *old_cfg, 1104 struct i40e_dcbx_config *new_cfg); 1105 #endif /* CONFIG_I40E_DCB */ 1106 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1107 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1108 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1109 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1110 void i40e_ptp_set_increment(struct i40e_pf *pf); 1111 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1112 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1113 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1114 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1115 void i40e_ptp_init(struct i40e_pf *pf); 1116 void i40e_ptp_stop(struct i40e_pf *pf); 1117 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1118 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1119 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1120 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1121 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1122 1123 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1124 1125 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1126 { 1127 return !!vsi->xdp_prog; 1128 } 1129 1130 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1131 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1132 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1133 struct i40e_cloud_filter *filter, 1134 bool add); 1135 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1136 struct i40e_cloud_filter *filter, 1137 bool add); 1138 #endif /* _I40E_H_ */ 1139