1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_bridge.h> 31 #include <linux/clocksource.h> 32 #include <linux/net_tstamp.h> 33 #include <linux/ptp_clock_kernel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/xdp_sock.h> 38 #include "i40e_type.h" 39 #include "i40e_prototype.h" 40 #include "i40e_client.h" 41 #include <linux/avf/virtchnl.h> 42 #include "i40e_virtchnl_pf.h" 43 #include "i40e_txrx.h" 44 #include "i40e_dcb.h" 45 46 /* Useful i40e defaults */ 47 #define I40E_MAX_VEB 16 48 49 #define I40E_MAX_NUM_DESCRIPTORS 4096 50 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 51 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 52 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 53 #define I40E_MIN_NUM_DESCRIPTORS 64 54 #define I40E_MIN_MSIX 2 55 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 56 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 57 /* max 16 qps */ 58 #define i40e_default_queues_per_vmdq(pf) \ 59 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 60 #define I40E_DEFAULT_QUEUES_PER_VF 4 61 #define I40E_MAX_VF_QUEUES 16 62 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 63 #define i40e_pf_get_max_q_per_tc(pf) \ 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 65 #define I40E_FDIR_RING 0 66 #define I40E_FDIR_RING_COUNT 32 67 #define I40E_MAX_AQ_BUF_SIZE 4096 68 #define I40E_AQ_LEN 256 69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 70 #define I40E_MAX_USER_PRIORITY 8 71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 72 #define I40E_DEFAULT_MSG_ENABLE 4 73 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 74 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 75 76 #define I40E_NVM_VERSION_LO_SHIFT 0 77 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 78 #define I40E_NVM_VERSION_HI_SHIFT 12 79 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 80 #define I40E_OEM_VER_BUILD_MASK 0xffff 81 #define I40E_OEM_VER_PATCH_MASK 0xff 82 #define I40E_OEM_VER_BUILD_SHIFT 8 83 #define I40E_OEM_VER_SHIFT 24 84 #define I40E_PHY_DEBUG_ALL \ 85 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 86 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 87 88 #define I40E_OEM_EETRACK_ID 0xffffffff 89 #define I40E_OEM_GEN_SHIFT 24 90 #define I40E_OEM_SNAP_MASK 0x00ff0000 91 #define I40E_OEM_SNAP_SHIFT 16 92 #define I40E_OEM_RELEASE_MASK 0x0000ffff 93 94 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 95 #define I40E_CURRENT_NVM_VERSION_HI 0x2 96 #define I40E_CURRENT_NVM_VERSION_LO 0x40 97 98 #define I40E_RX_DESC(R, i) \ 99 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 100 #define I40E_TX_DESC(R, i) \ 101 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 102 #define I40E_TX_CTXTDESC(R, i) \ 103 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 104 #define I40E_TX_FDIRDESC(R, i) \ 105 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 106 107 /* default to trying for four seconds */ 108 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 109 110 /* BW rate limiting */ 111 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 112 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 113 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 114 115 /* driver state flags */ 116 enum i40e_state_t { 117 __I40E_TESTING, 118 __I40E_CONFIG_BUSY, 119 __I40E_CONFIG_DONE, 120 __I40E_DOWN, 121 __I40E_SERVICE_SCHED, 122 __I40E_ADMINQ_EVENT_PENDING, 123 __I40E_MDD_EVENT_PENDING, 124 __I40E_VFLR_EVENT_PENDING, 125 __I40E_RESET_RECOVERY_PENDING, 126 __I40E_TIMEOUT_RECOVERY_PENDING, 127 __I40E_MISC_IRQ_REQUESTED, 128 __I40E_RESET_INTR_RECEIVED, 129 __I40E_REINIT_REQUESTED, 130 __I40E_PF_RESET_REQUESTED, 131 __I40E_CORE_RESET_REQUESTED, 132 __I40E_GLOBAL_RESET_REQUESTED, 133 __I40E_EMP_RESET_REQUESTED, 134 __I40E_EMP_RESET_INTR_RECEIVED, 135 __I40E_SUSPENDED, 136 __I40E_PTP_TX_IN_PROGRESS, 137 __I40E_BAD_EEPROM, 138 __I40E_DOWN_REQUESTED, 139 __I40E_FD_FLUSH_REQUESTED, 140 __I40E_FD_ATR_AUTO_DISABLED, 141 __I40E_FD_SB_AUTO_DISABLED, 142 __I40E_RESET_FAILED, 143 __I40E_PORT_SUSPENDED, 144 __I40E_VF_DISABLE, 145 __I40E_MACVLAN_SYNC_PENDING, 146 __I40E_UDP_FILTER_SYNC_PENDING, 147 __I40E_TEMP_LINK_POLLING, 148 __I40E_CLIENT_SERVICE_REQUESTED, 149 __I40E_CLIENT_L2_CHANGE, 150 __I40E_CLIENT_RESET, 151 __I40E_VIRTCHNL_OP_PENDING, 152 /* This must be last as it determines the size of the BITMAP */ 153 __I40E_STATE_SIZE__, 154 }; 155 156 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 157 158 /* VSI state flags */ 159 enum i40e_vsi_state_t { 160 __I40E_VSI_DOWN, 161 __I40E_VSI_NEEDS_RESTART, 162 __I40E_VSI_SYNCING_FILTERS, 163 __I40E_VSI_OVERFLOW_PROMISC, 164 __I40E_VSI_REINIT_REQUESTED, 165 __I40E_VSI_DOWN_REQUESTED, 166 /* This must be last as it determines the size of the BITMAP */ 167 __I40E_VSI_STATE_SIZE__, 168 }; 169 170 enum i40e_interrupt_policy { 171 I40E_INTERRUPT_BEST_CASE, 172 I40E_INTERRUPT_MEDIUM, 173 I40E_INTERRUPT_LOWEST 174 }; 175 176 struct i40e_lump_tracking { 177 u16 num_entries; 178 u16 search_hint; 179 u16 list[0]; 180 #define I40E_PILE_VALID_BIT 0x8000 181 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 182 }; 183 184 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 186 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 187 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 189 190 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 191 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 193 194 enum i40e_fd_stat_idx { 195 I40E_FD_STAT_ATR, 196 I40E_FD_STAT_SB, 197 I40E_FD_STAT_ATR_TUNNEL, 198 I40E_FD_STAT_PF_COUNT 199 }; 200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 201 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 203 #define I40E_FD_SB_STAT_IDX(pf_id) \ 204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 207 208 /* The following structure contains the data parsed from the user-defined 209 * field of the ethtool_rx_flow_spec structure. 210 */ 211 struct i40e_rx_flow_userdef { 212 bool flex_filter; 213 u16 flex_word; 214 u16 flex_offset; 215 }; 216 217 struct i40e_fdir_filter { 218 struct hlist_node fdir_node; 219 /* filter ipnut set */ 220 u8 flow_type; 221 u8 ip4_proto; 222 /* TX packet view of src and dst */ 223 __be32 dst_ip; 224 __be32 src_ip; 225 __be16 src_port; 226 __be16 dst_port; 227 __be32 sctp_v_tag; 228 229 /* Flexible data to match within the packet payload */ 230 __be16 flex_word; 231 u16 flex_offset; 232 bool flex_filter; 233 234 /* filter control */ 235 u16 q_index; 236 u8 flex_off; 237 u8 pctype; 238 u16 dest_vsi; 239 u8 dest_ctl; 240 u8 fd_status; 241 u16 cnt_index; 242 u32 fd_id; 243 }; 244 245 #define I40E_CLOUD_FIELD_OMAC 0x01 246 #define I40E_CLOUD_FIELD_IMAC 0x02 247 #define I40E_CLOUD_FIELD_IVLAN 0x04 248 #define I40E_CLOUD_FIELD_TEN_ID 0x08 249 #define I40E_CLOUD_FIELD_IIP 0x10 250 251 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 252 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 253 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 254 I40E_CLOUD_FIELD_IVLAN) 255 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_TEN_ID) 257 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 258 I40E_CLOUD_FIELD_IMAC | \ 259 I40E_CLOUD_FIELD_TEN_ID) 260 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 261 I40E_CLOUD_FIELD_IVLAN | \ 262 I40E_CLOUD_FIELD_TEN_ID) 263 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 264 265 struct i40e_cloud_filter { 266 struct hlist_node cloud_node; 267 unsigned long cookie; 268 /* cloud filter input set follows */ 269 u8 dst_mac[ETH_ALEN]; 270 u8 src_mac[ETH_ALEN]; 271 __be16 vlan_id; 272 u16 seid; /* filter control */ 273 __be16 dst_port; 274 __be16 src_port; 275 u32 tenant_id; 276 union { 277 struct { 278 struct in_addr dst_ip; 279 struct in_addr src_ip; 280 } v4; 281 struct { 282 struct in6_addr dst_ip6; 283 struct in6_addr src_ip6; 284 } v6; 285 } ip; 286 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 287 #define src_ipv6 ip.v6.src_ip6.s6_addr32 288 #define dst_ipv4 ip.v4.dst_ip.s_addr 289 #define src_ipv4 ip.v4.src_ip.s_addr 290 u16 n_proto; /* Ethernet Protocol */ 291 u8 ip_proto; /* IPPROTO value */ 292 u8 flags; 293 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 294 u8 tunnel_type; 295 }; 296 297 #define I40E_ETH_P_LLDP 0x88cc 298 299 #define I40E_DCB_PRIO_TYPE_STRICT 0 300 #define I40E_DCB_PRIO_TYPE_ETS 1 301 #define I40E_DCB_STRICT_PRIO_CREDITS 127 302 /* DCB per TC information data structure */ 303 struct i40e_tc_info { 304 u16 qoffset; /* Queue offset from base queue */ 305 u16 qcount; /* Total Queues */ 306 u8 netdev_tc; /* Netdev TC index if netdev associated */ 307 }; 308 309 /* TC configuration data structure */ 310 struct i40e_tc_configuration { 311 u8 numtc; /* Total number of enabled TCs */ 312 u8 enabled_tc; /* TC map */ 313 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 314 }; 315 316 #define I40E_UDP_PORT_INDEX_UNUSED 255 317 struct i40e_udp_port_config { 318 /* AdminQ command interface expects port number in Host byte order */ 319 u16 port; 320 u8 type; 321 u8 filter_index; 322 }; 323 324 /* macros related to FLX_PIT */ 325 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 326 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 327 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 328 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 329 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 330 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 331 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 332 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 333 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 334 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 335 I40E_FLEX_SET_FSIZE(fsize) | \ 336 I40E_FLEX_SET_SRC_WORD(src)) 337 338 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 339 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 340 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 341 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 342 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 343 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 344 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 345 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 346 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 347 348 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 349 350 /* macros related to GLQF_ORT */ 351 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 352 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 353 I40E_GLQF_ORT_PIT_INDX_MASK) 354 355 #define I40E_ORT_SET_COUNT(count) (((count) << \ 356 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 357 I40E_GLQF_ORT_FIELD_CNT_MASK) 358 359 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 360 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 361 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 362 363 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 364 I40E_ORT_SET_COUNT(count) | \ 365 I40E_ORT_SET_PAYLOAD(payload)) 366 367 #define I40E_L3_GLQF_ORT_IDX 34 368 #define I40E_L4_GLQF_ORT_IDX 35 369 370 /* Flex PIT register index */ 371 #define I40E_FLEX_PIT_IDX_START_L2 0 372 #define I40E_FLEX_PIT_IDX_START_L3 3 373 #define I40E_FLEX_PIT_IDX_START_L4 6 374 375 #define I40E_FLEX_PIT_TABLE_SIZE 3 376 377 #define I40E_FLEX_DEST_UNUSED 63 378 379 #define I40E_FLEX_INDEX_ENTRIES 8 380 381 /* Flex MASK to disable all flexible entries */ 382 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 383 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 384 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 385 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 386 387 struct i40e_flex_pit { 388 struct list_head list; 389 u16 src_offset; 390 u8 pit_index; 391 }; 392 393 struct i40e_channel { 394 struct list_head list; 395 bool initialized; 396 u8 type; 397 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 398 u16 stat_counter_idx; 399 u16 base_queue; 400 u16 num_queue_pairs; /* Requested by user */ 401 u16 seid; 402 403 u8 enabled_tc; 404 struct i40e_aqc_vsi_properties_data info; 405 406 u64 max_tx_rate; 407 408 /* track this channel belongs to which VSI */ 409 struct i40e_vsi *parent_vsi; 410 }; 411 412 /* struct that defines the Ethernet device */ 413 struct i40e_pf { 414 struct pci_dev *pdev; 415 struct i40e_hw hw; 416 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 417 struct msix_entry *msix_entries; 418 bool fc_autoneg_status; 419 420 u16 eeprom_version; 421 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 422 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 423 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 424 u16 num_req_vfs; /* num VFs requested for this PF */ 425 u16 num_vf_qps; /* num queue pairs per VF */ 426 u16 num_lan_qps; /* num lan queues this PF has set up */ 427 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 428 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 429 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 430 int iwarp_base_vector; 431 int queues_left; /* queues left unclaimed */ 432 u16 alloc_rss_size; /* allocated RSS queues */ 433 u16 rss_size_max; /* HW defined max RSS queues */ 434 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 435 u16 num_alloc_vsi; /* num VSIs this driver supports */ 436 u8 atr_sample_rate; 437 bool wol_en; 438 439 struct hlist_head fdir_filter_list; 440 u16 fdir_pf_active_filters; 441 unsigned long fd_flush_timestamp; 442 u32 fd_flush_cnt; 443 u32 fd_add_err; 444 u32 fd_atr_cnt; 445 446 /* Book-keeping of side-band filter count per flow-type. 447 * This is used to detect and handle input set changes for 448 * respective flow-type. 449 */ 450 u16 fd_tcp4_filter_cnt; 451 u16 fd_udp4_filter_cnt; 452 u16 fd_sctp4_filter_cnt; 453 u16 fd_ip4_filter_cnt; 454 455 /* Flexible filter table values that need to be programmed into 456 * hardware, which expects L3 and L4 to be programmed separately. We 457 * need to ensure that the values are in ascended order and don't have 458 * duplicates, so we track each L3 and L4 values in separate lists. 459 */ 460 struct list_head l3_flex_pit_list; 461 struct list_head l4_flex_pit_list; 462 463 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 464 u16 pending_udp_bitmap; 465 466 struct hlist_head cloud_filter_list; 467 u16 num_cloud_filters; 468 469 enum i40e_interrupt_policy int_policy; 470 u16 rx_itr_default; 471 u16 tx_itr_default; 472 u32 msg_enable; 473 char int_name[I40E_INT_NAME_STR_LEN]; 474 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 475 unsigned long service_timer_period; 476 unsigned long service_timer_previous; 477 struct timer_list service_timer; 478 struct work_struct service_task; 479 480 u32 hw_features; 481 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 482 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 483 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 484 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 485 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 486 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 487 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 488 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 489 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 490 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 491 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 492 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 493 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 494 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 495 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 496 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 497 #define I40E_HW_STOP_FW_LLDP BIT(16) 498 #define I40E_HW_PORT_ID_VALID BIT(17) 499 #define I40E_HW_RESTART_AUTONEG BIT(18) 500 501 u32 flags; 502 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 503 #define I40E_FLAG_MSI_ENABLED BIT(1) 504 #define I40E_FLAG_MSIX_ENABLED BIT(2) 505 #define I40E_FLAG_RSS_ENABLED BIT(3) 506 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 507 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 508 #define I40E_FLAG_DCB_CAPABLE BIT(6) 509 #define I40E_FLAG_DCB_ENABLED BIT(7) 510 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 511 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 512 #define I40E_FLAG_MFP_ENABLED BIT(10) 513 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 514 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 515 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 516 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 517 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 518 #define I40E_FLAG_LEGACY_RX BIT(16) 519 #define I40E_FLAG_PTP BIT(17) 520 #define I40E_FLAG_IWARP_ENABLED BIT(18) 521 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 522 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 523 #define I40E_FLAG_TC_MQPRIO BIT(21) 524 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 525 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 526 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 527 #define I40E_FLAG_RS_FEC BIT(25) 528 #define I40E_FLAG_BASE_R_FEC BIT(26) 529 530 struct i40e_client_instance *cinst; 531 bool stat_offsets_loaded; 532 struct i40e_hw_port_stats stats; 533 struct i40e_hw_port_stats stats_offsets; 534 u32 tx_timeout_count; 535 u32 tx_timeout_recovery_level; 536 unsigned long tx_timeout_last_recovery; 537 u32 tx_sluggish_count; 538 u32 hw_csum_rx_error; 539 u32 led_status; 540 u16 corer_count; /* Core reset count */ 541 u16 globr_count; /* Global reset count */ 542 u16 empr_count; /* EMP reset count */ 543 u16 pfr_count; /* PF reset count */ 544 u16 sw_int_count; /* SW interrupt count */ 545 546 struct mutex switch_mutex; 547 u16 lan_vsi; /* our default LAN VSI */ 548 u16 lan_veb; /* initial relay, if exists */ 549 #define I40E_NO_VEB 0xffff 550 #define I40E_NO_VSI 0xffff 551 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 552 struct i40e_vsi **vsi; 553 struct i40e_veb *veb[I40E_MAX_VEB]; 554 555 struct i40e_lump_tracking *qp_pile; 556 struct i40e_lump_tracking *irq_pile; 557 558 /* switch config info */ 559 u16 pf_seid; 560 u16 main_vsi_seid; 561 u16 mac_seid; 562 struct kobject *switch_kobj; 563 #ifdef CONFIG_DEBUG_FS 564 struct dentry *i40e_dbg_pf; 565 #endif /* CONFIG_DEBUG_FS */ 566 bool cur_promisc; 567 568 u16 instance; /* A unique number per i40e_pf instance in the system */ 569 570 /* sr-iov config info */ 571 struct i40e_vf *vf; 572 int num_alloc_vfs; /* actual number of VFs allocated */ 573 u32 vf_aq_requests; 574 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 575 576 /* DCBx/DCBNL capability for PF that indicates 577 * whether DCBx is managed by firmware or host 578 * based agent (LLDPAD). Also, indicates what 579 * flavor of DCBx protocol (IEEE/CEE) is supported 580 * by the device. For now we're supporting IEEE 581 * mode only. 582 */ 583 u16 dcbx_cap; 584 585 struct i40e_filter_control_settings filter_settings; 586 587 struct ptp_clock *ptp_clock; 588 struct ptp_clock_info ptp_caps; 589 struct sk_buff *ptp_tx_skb; 590 unsigned long ptp_tx_start; 591 struct hwtstamp_config tstamp_config; 592 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 593 u32 ptp_adj_mult; 594 u32 tx_hwtstamp_timeouts; 595 u32 tx_hwtstamp_skipped; 596 u32 rx_hwtstamp_cleared; 597 u32 latch_event_flags; 598 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 599 unsigned long latch_events[4]; 600 bool ptp_tx; 601 bool ptp_rx; 602 u16 rss_table_size; /* HW RSS table size */ 603 u32 max_bw; 604 u32 min_bw; 605 606 u32 ioremap_len; 607 u32 fd_inv; 608 u16 phy_led_val; 609 610 u16 override_q_count; 611 u16 last_sw_conf_flags; 612 u16 last_sw_conf_valid_flags; 613 }; 614 615 /** 616 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 617 * @macaddr: the MAC Address as the base key 618 * 619 * Simply copies the address and returns it as a u64 for hashing 620 **/ 621 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 622 { 623 u64 key = 0; 624 625 ether_addr_copy((u8 *)&key, macaddr); 626 return key; 627 } 628 629 enum i40e_filter_state { 630 I40E_FILTER_INVALID = 0, /* Invalid state */ 631 I40E_FILTER_NEW, /* New, not sent to FW yet */ 632 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 633 I40E_FILTER_FAILED, /* Rejected by FW */ 634 I40E_FILTER_REMOVE, /* To be removed */ 635 /* There is no 'removed' state; the filter struct is freed */ 636 }; 637 struct i40e_mac_filter { 638 struct hlist_node hlist; 639 u8 macaddr[ETH_ALEN]; 640 #define I40E_VLAN_ANY -1 641 s16 vlan; 642 enum i40e_filter_state state; 643 }; 644 645 /* Wrapper structure to keep track of filters while we are preparing to send 646 * firmware commands. We cannot send firmware commands while holding a 647 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 648 * a separate structure, which will track the state change and update the real 649 * filter while under lock. We can't simply hold the filters in a separate 650 * list, as this opens a window for a race condition when adding new MAC 651 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 652 */ 653 struct i40e_new_mac_filter { 654 struct hlist_node hlist; 655 struct i40e_mac_filter *f; 656 657 /* Track future changes to state separately */ 658 enum i40e_filter_state state; 659 }; 660 661 struct i40e_veb { 662 struct i40e_pf *pf; 663 u16 idx; 664 u16 veb_idx; /* index of VEB parent */ 665 u16 seid; 666 u16 uplink_seid; 667 u16 stats_idx; /* index of VEB parent */ 668 u8 enabled_tc; 669 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 670 u16 flags; 671 u16 bw_limit; 672 u8 bw_max_quanta; 673 bool is_abs_credits; 674 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 675 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 676 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 677 struct kobject *kobj; 678 bool stat_offsets_loaded; 679 struct i40e_eth_stats stats; 680 struct i40e_eth_stats stats_offsets; 681 struct i40e_veb_tc_stats tc_stats; 682 struct i40e_veb_tc_stats tc_stats_offsets; 683 }; 684 685 /* struct that defines a VSI, associated with a dev */ 686 struct i40e_vsi { 687 struct net_device *netdev; 688 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 689 bool netdev_registered; 690 bool stat_offsets_loaded; 691 692 u32 current_netdev_flags; 693 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 694 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 695 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 696 unsigned long flags; 697 698 /* Per VSI lock to protect elements/hash (MAC filter) */ 699 spinlock_t mac_filter_hash_lock; 700 /* Fixed size hash table with 2^8 buckets for MAC filters */ 701 DECLARE_HASHTABLE(mac_filter_hash, 8); 702 bool has_vlan_filter; 703 704 /* VSI stats */ 705 struct rtnl_link_stats64 net_stats; 706 struct rtnl_link_stats64 net_stats_offsets; 707 struct i40e_eth_stats eth_stats; 708 struct i40e_eth_stats eth_stats_offsets; 709 u32 tx_restart; 710 u32 tx_busy; 711 u64 tx_linearize; 712 u64 tx_force_wb; 713 u32 rx_buf_failed; 714 u32 rx_page_failed; 715 716 /* These are containers of ring pointers, allocated at run-time */ 717 struct i40e_ring **rx_rings; 718 struct i40e_ring **tx_rings; 719 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 720 721 u32 active_filters; 722 u32 promisc_threshold; 723 724 u16 work_limit; 725 u16 int_rate_limit; /* value in usecs */ 726 727 u16 rss_table_size; /* HW RSS table size */ 728 u16 rss_size; /* Allocated RSS queues */ 729 u8 *rss_hkey_user; /* User configured hash keys */ 730 u8 *rss_lut_user; /* User configured lookup table entries */ 731 732 733 u16 max_frame; 734 u16 rx_buf_len; 735 736 struct bpf_prog *xdp_prog; 737 738 /* List of q_vectors allocated to this VSI */ 739 struct i40e_q_vector **q_vectors; 740 int num_q_vectors; 741 int base_vector; 742 bool irqs_ready; 743 744 u16 seid; /* HW index of this VSI (absolute index) */ 745 u16 id; /* VSI number */ 746 u16 uplink_seid; 747 748 u16 base_queue; /* vsi's first queue in hw array */ 749 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 750 u16 req_queue_pairs; /* User requested queue pairs */ 751 u16 num_queue_pairs; /* Used tx and rx pairs */ 752 u16 num_desc; 753 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 754 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 755 756 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 757 struct i40e_tc_configuration tc_config; 758 struct i40e_aqc_vsi_properties_data info; 759 760 /* VSI BW limit (absolute across all TCs) */ 761 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 762 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 763 764 /* Relative TC credits across VSIs */ 765 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 766 /* TC BW limit credits within VSI */ 767 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 768 /* TC BW limit max quanta within VSI */ 769 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 770 771 struct i40e_pf *back; /* Backreference to associated PF */ 772 u16 idx; /* index in pf->vsi[] */ 773 u16 veb_idx; /* index of VEB parent */ 774 struct kobject *kobj; /* sysfs object */ 775 bool current_isup; /* Sync 'link up' logging */ 776 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 777 778 /* channel specific fields */ 779 u16 cnt_q_avail; /* num of queues available for channel usage */ 780 u16 orig_rss_size; 781 u16 current_rss_size; 782 bool reconfig_rss; 783 784 u16 next_base_queue; /* next queue to be used for channel setup */ 785 786 struct list_head ch_list; 787 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 788 789 void *priv; /* client driver data reference. */ 790 791 /* VSI specific handlers */ 792 irqreturn_t (*irq_handler)(int irq, void *data); 793 794 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 795 } ____cacheline_internodealigned_in_smp; 796 797 struct i40e_netdev_priv { 798 struct i40e_vsi *vsi; 799 }; 800 801 /* struct that defines an interrupt vector */ 802 struct i40e_q_vector { 803 struct i40e_vsi *vsi; 804 805 u16 v_idx; /* index in the vsi->q_vector array. */ 806 u16 reg_idx; /* register index of the interrupt */ 807 808 struct napi_struct napi; 809 810 struct i40e_ring_container rx; 811 struct i40e_ring_container tx; 812 813 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 814 u8 num_ringpairs; /* total number of ring pairs in vector */ 815 816 cpumask_t affinity_mask; 817 struct irq_affinity_notify affinity_notify; 818 819 struct rcu_head rcu; /* to avoid race with update stats on free */ 820 char name[I40E_INT_NAME_STR_LEN]; 821 bool arm_wb_state; 822 } ____cacheline_internodealigned_in_smp; 823 824 /* lan device */ 825 struct i40e_device { 826 struct list_head list; 827 struct i40e_pf *pf; 828 }; 829 830 /** 831 * i40e_nvm_version_str - format the NVM version strings 832 * @hw: ptr to the hardware info 833 **/ 834 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 835 { 836 static char buf[32]; 837 u32 full_ver; 838 839 full_ver = hw->nvm.oem_ver; 840 841 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 842 u8 gen, snap; 843 u16 release; 844 845 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 846 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 847 I40E_OEM_SNAP_SHIFT); 848 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 849 850 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 851 } else { 852 u8 ver, patch; 853 u16 build; 854 855 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 856 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 857 I40E_OEM_VER_BUILD_MASK); 858 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 859 860 snprintf(buf, sizeof(buf), 861 "%x.%02x 0x%x %d.%d.%d", 862 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 863 I40E_NVM_VERSION_HI_SHIFT, 864 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 865 I40E_NVM_VERSION_LO_SHIFT, 866 hw->nvm.eetrack, ver, build, patch); 867 } 868 869 return buf; 870 } 871 872 /** 873 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 874 * @netdev: the corresponding netdev 875 * 876 * Return the PF struct for the given netdev 877 **/ 878 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 879 { 880 struct i40e_netdev_priv *np = netdev_priv(netdev); 881 struct i40e_vsi *vsi = np->vsi; 882 883 return vsi->back; 884 } 885 886 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 887 irqreturn_t (*irq_handler)(int, void *)) 888 { 889 vsi->irq_handler = irq_handler; 890 } 891 892 /** 893 * i40e_get_fd_cnt_all - get the total FD filter space available 894 * @pf: pointer to the PF struct 895 **/ 896 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 897 { 898 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 899 } 900 901 /** 902 * i40e_read_fd_input_set - reads value of flow director input set register 903 * @pf: pointer to the PF struct 904 * @addr: register addr 905 * 906 * This function reads value of flow director input set register 907 * specified by 'addr' (which is specific to flow-type) 908 **/ 909 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 910 { 911 u64 val; 912 913 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 914 val <<= 32; 915 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 916 917 return val; 918 } 919 920 /** 921 * i40e_write_fd_input_set - writes value into flow director input set register 922 * @pf: pointer to the PF struct 923 * @addr: register addr 924 * @val: value to be written 925 * 926 * This function writes specified value to the register specified by 'addr'. 927 * This register is input set register based on flow-type. 928 **/ 929 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 930 u16 addr, u64 val) 931 { 932 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 933 (u32)(val >> 32)); 934 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 935 (u32)(val & 0xFFFFFFFFULL)); 936 } 937 938 /* needed by i40e_ethtool.c */ 939 int i40e_up(struct i40e_vsi *vsi); 940 void i40e_down(struct i40e_vsi *vsi); 941 extern const char i40e_driver_name[]; 942 extern const char i40e_driver_version_str[]; 943 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 944 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 945 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 946 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 947 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 948 u16 rss_table_size, u16 rss_size); 949 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 950 /** 951 * i40e_find_vsi_by_type - Find and return Flow Director VSI 952 * @pf: PF to search for VSI 953 * @type: Value indicating type of VSI we are looking for 954 **/ 955 static inline struct i40e_vsi * 956 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 957 { 958 int i; 959 960 for (i = 0; i < pf->num_alloc_vsi; i++) { 961 struct i40e_vsi *vsi = pf->vsi[i]; 962 963 if (vsi && vsi->type == type) 964 return vsi; 965 } 966 967 return NULL; 968 } 969 void i40e_update_stats(struct i40e_vsi *vsi); 970 void i40e_update_eth_stats(struct i40e_vsi *vsi); 971 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 972 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 973 bool printconfig); 974 975 int i40e_add_del_fdir(struct i40e_vsi *vsi, 976 struct i40e_fdir_filter *input, bool add); 977 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 978 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 979 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 980 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 981 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 982 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 983 void i40e_set_ethtool_ops(struct net_device *netdev); 984 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 985 const u8 *macaddr, s16 vlan); 986 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 987 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 988 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 989 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 990 u16 uplink, u32 param1); 991 int i40e_vsi_release(struct i40e_vsi *vsi); 992 void i40e_service_event_schedule(struct i40e_pf *pf); 993 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 994 u8 *msg, u16 len); 995 996 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 997 bool enable); 998 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 999 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1000 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1001 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1002 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1003 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1004 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1005 u16 downlink_seid, u8 enabled_tc); 1006 void i40e_veb_release(struct i40e_veb *veb); 1007 1008 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1009 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1010 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1011 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1012 void i40e_pf_reset_stats(struct i40e_pf *pf); 1013 #ifdef CONFIG_DEBUG_FS 1014 void i40e_dbg_pf_init(struct i40e_pf *pf); 1015 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1016 void i40e_dbg_init(void); 1017 void i40e_dbg_exit(void); 1018 #else 1019 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1020 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1021 static inline void i40e_dbg_init(void) {} 1022 static inline void i40e_dbg_exit(void) {} 1023 #endif /* CONFIG_DEBUG_FS*/ 1024 /* needed by client drivers */ 1025 int i40e_lan_add_device(struct i40e_pf *pf); 1026 int i40e_lan_del_device(struct i40e_pf *pf); 1027 void i40e_client_subtask(struct i40e_pf *pf); 1028 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1029 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1030 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1031 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1032 void i40e_client_update_msix_info(struct i40e_pf *pf); 1033 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1034 /** 1035 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1036 * @vsi: pointer to a vsi 1037 * @vector: enable a particular Hw Interrupt vector, without base_vector 1038 **/ 1039 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1040 { 1041 struct i40e_pf *pf = vsi->back; 1042 struct i40e_hw *hw = &pf->hw; 1043 u32 val; 1044 1045 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1046 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1047 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1048 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1049 /* skip the flush */ 1050 } 1051 1052 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1053 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1054 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1055 int i40e_open(struct net_device *netdev); 1056 int i40e_close(struct net_device *netdev); 1057 int i40e_vsi_open(struct i40e_vsi *vsi); 1058 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1059 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1060 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1061 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1062 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1063 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1064 const u8 *macaddr); 1065 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1066 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1067 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1068 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1069 #ifdef CONFIG_I40E_DCB 1070 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1071 struct i40e_dcbx_config *old_cfg, 1072 struct i40e_dcbx_config *new_cfg); 1073 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1074 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1075 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1076 struct i40e_dcbx_config *old_cfg, 1077 struct i40e_dcbx_config *new_cfg); 1078 #endif /* CONFIG_I40E_DCB */ 1079 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1080 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1081 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1082 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1083 void i40e_ptp_set_increment(struct i40e_pf *pf); 1084 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1085 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1086 void i40e_ptp_init(struct i40e_pf *pf); 1087 void i40e_ptp_stop(struct i40e_pf *pf); 1088 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1089 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1090 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1091 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1092 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1093 1094 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1095 1096 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1097 { 1098 return !!vsi->xdp_prog; 1099 } 1100 1101 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1102 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1103 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1104 struct i40e_cloud_filter *filter, 1105 bool add); 1106 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1107 struct i40e_cloud_filter *filter, 1108 bool add); 1109 #endif /* _I40E_H_ */ 1110