1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_macvlan.h> 31 #include <linux/if_bridge.h> 32 #include <linux/clocksource.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_mirred.h> 38 #include <net/xdp_sock.h> 39 #include "i40e_type.h" 40 #include "i40e_prototype.h" 41 #include "i40e_client.h" 42 #include <linux/avf/virtchnl.h> 43 #include "i40e_virtchnl_pf.h" 44 #include "i40e_txrx.h" 45 #include "i40e_dcb.h" 46 47 /* Useful i40e defaults */ 48 #define I40E_MAX_VEB 16 49 50 #define I40E_MAX_NUM_DESCRIPTORS 4096 51 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 52 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 53 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 54 #define I40E_MIN_NUM_DESCRIPTORS 64 55 #define I40E_MIN_MSIX 2 56 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 57 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 58 /* max 16 qps */ 59 #define i40e_default_queues_per_vmdq(pf) \ 60 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 61 #define I40E_DEFAULT_QUEUES_PER_VF 4 62 #define I40E_MAX_VF_QUEUES 16 63 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 64 #define i40e_pf_get_max_q_per_tc(pf) \ 65 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 66 #define I40E_FDIR_RING 0 67 #define I40E_FDIR_RING_COUNT 32 68 #define I40E_MAX_AQ_BUF_SIZE 4096 69 #define I40E_AQ_LEN 256 70 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 71 #define I40E_MAX_USER_PRIORITY 8 72 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 73 #define I40E_DEFAULT_MSG_ENABLE 4 74 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 75 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 76 77 #define I40E_NVM_VERSION_LO_SHIFT 0 78 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 79 #define I40E_NVM_VERSION_HI_SHIFT 12 80 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 81 #define I40E_OEM_VER_BUILD_MASK 0xffff 82 #define I40E_OEM_VER_PATCH_MASK 0xff 83 #define I40E_OEM_VER_BUILD_SHIFT 8 84 #define I40E_OEM_VER_SHIFT 24 85 #define I40E_PHY_DEBUG_ALL \ 86 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 87 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 88 89 #define I40E_OEM_EETRACK_ID 0xffffffff 90 #define I40E_OEM_GEN_SHIFT 24 91 #define I40E_OEM_SNAP_MASK 0x00ff0000 92 #define I40E_OEM_SNAP_SHIFT 16 93 #define I40E_OEM_RELEASE_MASK 0x0000ffff 94 95 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 96 #define I40E_CURRENT_NVM_VERSION_HI 0x2 97 #define I40E_CURRENT_NVM_VERSION_LO 0x40 98 99 #define I40E_RX_DESC(R, i) \ 100 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 101 #define I40E_TX_DESC(R, i) \ 102 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 103 #define I40E_TX_CTXTDESC(R, i) \ 104 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 105 #define I40E_TX_FDIRDESC(R, i) \ 106 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 107 108 /* default to trying for four seconds */ 109 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 110 111 /* BW rate limiting */ 112 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 113 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 114 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 115 116 /* driver state flags */ 117 enum i40e_state_t { 118 __I40E_TESTING, 119 __I40E_CONFIG_BUSY, 120 __I40E_CONFIG_DONE, 121 __I40E_DOWN, 122 __I40E_SERVICE_SCHED, 123 __I40E_ADMINQ_EVENT_PENDING, 124 __I40E_MDD_EVENT_PENDING, 125 __I40E_VFLR_EVENT_PENDING, 126 __I40E_RESET_RECOVERY_PENDING, 127 __I40E_TIMEOUT_RECOVERY_PENDING, 128 __I40E_MISC_IRQ_REQUESTED, 129 __I40E_RESET_INTR_RECEIVED, 130 __I40E_REINIT_REQUESTED, 131 __I40E_PF_RESET_REQUESTED, 132 __I40E_CORE_RESET_REQUESTED, 133 __I40E_GLOBAL_RESET_REQUESTED, 134 __I40E_EMP_RESET_REQUESTED, 135 __I40E_EMP_RESET_INTR_RECEIVED, 136 __I40E_SUSPENDED, 137 __I40E_PTP_TX_IN_PROGRESS, 138 __I40E_BAD_EEPROM, 139 __I40E_DOWN_REQUESTED, 140 __I40E_FD_FLUSH_REQUESTED, 141 __I40E_FD_ATR_AUTO_DISABLED, 142 __I40E_FD_SB_AUTO_DISABLED, 143 __I40E_RESET_FAILED, 144 __I40E_PORT_SUSPENDED, 145 __I40E_VF_DISABLE, 146 __I40E_MACVLAN_SYNC_PENDING, 147 __I40E_UDP_FILTER_SYNC_PENDING, 148 __I40E_TEMP_LINK_POLLING, 149 __I40E_CLIENT_SERVICE_REQUESTED, 150 __I40E_CLIENT_L2_CHANGE, 151 __I40E_CLIENT_RESET, 152 __I40E_VIRTCHNL_OP_PENDING, 153 __I40E_RECOVERY_MODE, 154 /* This must be last as it determines the size of the BITMAP */ 155 __I40E_STATE_SIZE__, 156 }; 157 158 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 159 160 /* VSI state flags */ 161 enum i40e_vsi_state_t { 162 __I40E_VSI_DOWN, 163 __I40E_VSI_NEEDS_RESTART, 164 __I40E_VSI_SYNCING_FILTERS, 165 __I40E_VSI_OVERFLOW_PROMISC, 166 __I40E_VSI_REINIT_REQUESTED, 167 __I40E_VSI_DOWN_REQUESTED, 168 /* This must be last as it determines the size of the BITMAP */ 169 __I40E_VSI_STATE_SIZE__, 170 }; 171 172 enum i40e_interrupt_policy { 173 I40E_INTERRUPT_BEST_CASE, 174 I40E_INTERRUPT_MEDIUM, 175 I40E_INTERRUPT_LOWEST 176 }; 177 178 struct i40e_lump_tracking { 179 u16 num_entries; 180 u16 search_hint; 181 u16 list[0]; 182 #define I40E_PILE_VALID_BIT 0x8000 183 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 184 }; 185 186 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 187 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 188 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 189 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 190 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 191 192 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 193 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 194 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 195 196 enum i40e_fd_stat_idx { 197 I40E_FD_STAT_ATR, 198 I40E_FD_STAT_SB, 199 I40E_FD_STAT_ATR_TUNNEL, 200 I40E_FD_STAT_PF_COUNT 201 }; 202 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 203 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 205 #define I40E_FD_SB_STAT_IDX(pf_id) \ 206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 207 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 208 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 209 210 /* The following structure contains the data parsed from the user-defined 211 * field of the ethtool_rx_flow_spec structure. 212 */ 213 struct i40e_rx_flow_userdef { 214 bool flex_filter; 215 u16 flex_word; 216 u16 flex_offset; 217 }; 218 219 struct i40e_fdir_filter { 220 struct hlist_node fdir_node; 221 /* filter ipnut set */ 222 u8 flow_type; 223 u8 ip4_proto; 224 /* TX packet view of src and dst */ 225 __be32 dst_ip; 226 __be32 src_ip; 227 __be16 src_port; 228 __be16 dst_port; 229 __be32 sctp_v_tag; 230 231 /* Flexible data to match within the packet payload */ 232 __be16 flex_word; 233 u16 flex_offset; 234 bool flex_filter; 235 236 /* filter control */ 237 u16 q_index; 238 u8 flex_off; 239 u8 pctype; 240 u16 dest_vsi; 241 u8 dest_ctl; 242 u8 fd_status; 243 u16 cnt_index; 244 u32 fd_id; 245 }; 246 247 #define I40E_CLOUD_FIELD_OMAC 0x01 248 #define I40E_CLOUD_FIELD_IMAC 0x02 249 #define I40E_CLOUD_FIELD_IVLAN 0x04 250 #define I40E_CLOUD_FIELD_TEN_ID 0x08 251 #define I40E_CLOUD_FIELD_IIP 0x10 252 253 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 254 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 255 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_IVLAN) 257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 258 I40E_CLOUD_FIELD_TEN_ID) 259 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 260 I40E_CLOUD_FIELD_IMAC | \ 261 I40E_CLOUD_FIELD_TEN_ID) 262 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 263 I40E_CLOUD_FIELD_IVLAN | \ 264 I40E_CLOUD_FIELD_TEN_ID) 265 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 266 267 struct i40e_cloud_filter { 268 struct hlist_node cloud_node; 269 unsigned long cookie; 270 /* cloud filter input set follows */ 271 u8 dst_mac[ETH_ALEN]; 272 u8 src_mac[ETH_ALEN]; 273 __be16 vlan_id; 274 u16 seid; /* filter control */ 275 __be16 dst_port; 276 __be16 src_port; 277 u32 tenant_id; 278 union { 279 struct { 280 struct in_addr dst_ip; 281 struct in_addr src_ip; 282 } v4; 283 struct { 284 struct in6_addr dst_ip6; 285 struct in6_addr src_ip6; 286 } v6; 287 } ip; 288 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 289 #define src_ipv6 ip.v6.src_ip6.s6_addr32 290 #define dst_ipv4 ip.v4.dst_ip.s_addr 291 #define src_ipv4 ip.v4.src_ip.s_addr 292 u16 n_proto; /* Ethernet Protocol */ 293 u8 ip_proto; /* IPPROTO value */ 294 u8 flags; 295 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 296 u8 tunnel_type; 297 }; 298 299 #define I40E_DCB_PRIO_TYPE_STRICT 0 300 #define I40E_DCB_PRIO_TYPE_ETS 1 301 #define I40E_DCB_STRICT_PRIO_CREDITS 127 302 /* DCB per TC information data structure */ 303 struct i40e_tc_info { 304 u16 qoffset; /* Queue offset from base queue */ 305 u16 qcount; /* Total Queues */ 306 u8 netdev_tc; /* Netdev TC index if netdev associated */ 307 }; 308 309 /* TC configuration data structure */ 310 struct i40e_tc_configuration { 311 u8 numtc; /* Total number of enabled TCs */ 312 u8 enabled_tc; /* TC map */ 313 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 314 }; 315 316 #define I40E_UDP_PORT_INDEX_UNUSED 255 317 struct i40e_udp_port_config { 318 /* AdminQ command interface expects port number in Host byte order */ 319 u16 port; 320 u8 type; 321 u8 filter_index; 322 }; 323 324 #define I40_DDP_FLASH_REGION 100 325 #define I40E_PROFILE_INFO_SIZE 48 326 #define I40E_MAX_PROFILE_NUM 16 327 #define I40E_PROFILE_LIST_SIZE \ 328 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 329 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 330 #define I40E_DDP_PROFILE_NAME_MAX 64 331 332 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 333 bool is_add); 334 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 335 336 struct i40e_ddp_profile_list { 337 u32 p_count; 338 struct i40e_profile_info p_info[0]; 339 }; 340 341 struct i40e_ddp_old_profile_list { 342 struct list_head list; 343 size_t old_ddp_size; 344 u8 old_ddp_buf[0]; 345 }; 346 347 /* macros related to FLX_PIT */ 348 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 349 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 350 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 351 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 352 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 353 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 354 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 355 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 356 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 357 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 358 I40E_FLEX_SET_FSIZE(fsize) | \ 359 I40E_FLEX_SET_SRC_WORD(src)) 360 361 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 362 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 363 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 364 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 365 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 366 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 367 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 368 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 369 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 370 371 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 372 373 /* macros related to GLQF_ORT */ 374 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 375 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 376 I40E_GLQF_ORT_PIT_INDX_MASK) 377 378 #define I40E_ORT_SET_COUNT(count) (((count) << \ 379 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 380 I40E_GLQF_ORT_FIELD_CNT_MASK) 381 382 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 383 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 384 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 385 386 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 387 I40E_ORT_SET_COUNT(count) | \ 388 I40E_ORT_SET_PAYLOAD(payload)) 389 390 #define I40E_L3_GLQF_ORT_IDX 34 391 #define I40E_L4_GLQF_ORT_IDX 35 392 393 /* Flex PIT register index */ 394 #define I40E_FLEX_PIT_IDX_START_L2 0 395 #define I40E_FLEX_PIT_IDX_START_L3 3 396 #define I40E_FLEX_PIT_IDX_START_L4 6 397 398 #define I40E_FLEX_PIT_TABLE_SIZE 3 399 400 #define I40E_FLEX_DEST_UNUSED 63 401 402 #define I40E_FLEX_INDEX_ENTRIES 8 403 404 /* Flex MASK to disable all flexible entries */ 405 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 406 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 407 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 408 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 409 410 struct i40e_flex_pit { 411 struct list_head list; 412 u16 src_offset; 413 u8 pit_index; 414 }; 415 416 struct i40e_fwd_adapter { 417 struct net_device *netdev; 418 int bit_no; 419 }; 420 421 struct i40e_channel { 422 struct list_head list; 423 bool initialized; 424 u8 type; 425 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 426 u16 stat_counter_idx; 427 u16 base_queue; 428 u16 num_queue_pairs; /* Requested by user */ 429 u16 seid; 430 431 u8 enabled_tc; 432 struct i40e_aqc_vsi_properties_data info; 433 434 u64 max_tx_rate; 435 struct i40e_fwd_adapter *fwd; 436 437 /* track this channel belongs to which VSI */ 438 struct i40e_vsi *parent_vsi; 439 }; 440 441 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 442 { 443 return !!ch->fwd; 444 } 445 446 static inline u8 *i40e_channel_mac(struct i40e_channel *ch) 447 { 448 if (i40e_is_channel_macvlan(ch)) 449 return ch->fwd->netdev->dev_addr; 450 else 451 return NULL; 452 } 453 454 /* struct that defines the Ethernet device */ 455 struct i40e_pf { 456 struct pci_dev *pdev; 457 struct i40e_hw hw; 458 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 459 struct msix_entry *msix_entries; 460 bool fc_autoneg_status; 461 462 u16 eeprom_version; 463 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 464 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 465 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 466 u16 num_req_vfs; /* num VFs requested for this PF */ 467 u16 num_vf_qps; /* num queue pairs per VF */ 468 u16 num_lan_qps; /* num lan queues this PF has set up */ 469 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 470 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 471 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 472 int iwarp_base_vector; 473 int queues_left; /* queues left unclaimed */ 474 u16 alloc_rss_size; /* allocated RSS queues */ 475 u16 rss_size_max; /* HW defined max RSS queues */ 476 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 477 u16 num_alloc_vsi; /* num VSIs this driver supports */ 478 u8 atr_sample_rate; 479 bool wol_en; 480 481 struct hlist_head fdir_filter_list; 482 u16 fdir_pf_active_filters; 483 unsigned long fd_flush_timestamp; 484 u32 fd_flush_cnt; 485 u32 fd_add_err; 486 u32 fd_atr_cnt; 487 488 /* Book-keeping of side-band filter count per flow-type. 489 * This is used to detect and handle input set changes for 490 * respective flow-type. 491 */ 492 u16 fd_tcp4_filter_cnt; 493 u16 fd_udp4_filter_cnt; 494 u16 fd_sctp4_filter_cnt; 495 u16 fd_ip4_filter_cnt; 496 497 /* Flexible filter table values that need to be programmed into 498 * hardware, which expects L3 and L4 to be programmed separately. We 499 * need to ensure that the values are in ascended order and don't have 500 * duplicates, so we track each L3 and L4 values in separate lists. 501 */ 502 struct list_head l3_flex_pit_list; 503 struct list_head l4_flex_pit_list; 504 505 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 506 u16 pending_udp_bitmap; 507 508 struct hlist_head cloud_filter_list; 509 u16 num_cloud_filters; 510 511 enum i40e_interrupt_policy int_policy; 512 u16 rx_itr_default; 513 u16 tx_itr_default; 514 u32 msg_enable; 515 char int_name[I40E_INT_NAME_STR_LEN]; 516 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 517 unsigned long service_timer_period; 518 unsigned long service_timer_previous; 519 struct timer_list service_timer; 520 struct work_struct service_task; 521 522 u32 hw_features; 523 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 524 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 525 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 526 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 527 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 528 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 529 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 530 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 531 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 532 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 533 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 534 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 535 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 536 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 537 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 538 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 539 #define I40E_HW_STOP_FW_LLDP BIT(16) 540 #define I40E_HW_PORT_ID_VALID BIT(17) 541 #define I40E_HW_RESTART_AUTONEG BIT(18) 542 543 u32 flags; 544 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 545 #define I40E_FLAG_MSI_ENABLED BIT(1) 546 #define I40E_FLAG_MSIX_ENABLED BIT(2) 547 #define I40E_FLAG_RSS_ENABLED BIT(3) 548 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 549 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 550 #define I40E_FLAG_DCB_CAPABLE BIT(6) 551 #define I40E_FLAG_DCB_ENABLED BIT(7) 552 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 553 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 554 #define I40E_FLAG_MFP_ENABLED BIT(10) 555 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 556 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 557 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 558 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 559 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 560 #define I40E_FLAG_LEGACY_RX BIT(16) 561 #define I40E_FLAG_PTP BIT(17) 562 #define I40E_FLAG_IWARP_ENABLED BIT(18) 563 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 564 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 565 #define I40E_FLAG_TC_MQPRIO BIT(21) 566 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 567 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 568 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 569 #define I40E_FLAG_RS_FEC BIT(25) 570 #define I40E_FLAG_BASE_R_FEC BIT(26) 571 572 struct i40e_client_instance *cinst; 573 bool stat_offsets_loaded; 574 struct i40e_hw_port_stats stats; 575 struct i40e_hw_port_stats stats_offsets; 576 u32 tx_timeout_count; 577 u32 tx_timeout_recovery_level; 578 unsigned long tx_timeout_last_recovery; 579 u32 tx_sluggish_count; 580 u32 hw_csum_rx_error; 581 u32 led_status; 582 u16 corer_count; /* Core reset count */ 583 u16 globr_count; /* Global reset count */ 584 u16 empr_count; /* EMP reset count */ 585 u16 pfr_count; /* PF reset count */ 586 u16 sw_int_count; /* SW interrupt count */ 587 588 struct mutex switch_mutex; 589 u16 lan_vsi; /* our default LAN VSI */ 590 u16 lan_veb; /* initial relay, if exists */ 591 #define I40E_NO_VEB 0xffff 592 #define I40E_NO_VSI 0xffff 593 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 594 struct i40e_vsi **vsi; 595 struct i40e_veb *veb[I40E_MAX_VEB]; 596 597 struct i40e_lump_tracking *qp_pile; 598 struct i40e_lump_tracking *irq_pile; 599 600 /* switch config info */ 601 u16 pf_seid; 602 u16 main_vsi_seid; 603 u16 mac_seid; 604 struct kobject *switch_kobj; 605 #ifdef CONFIG_DEBUG_FS 606 struct dentry *i40e_dbg_pf; 607 #endif /* CONFIG_DEBUG_FS */ 608 bool cur_promisc; 609 610 u16 instance; /* A unique number per i40e_pf instance in the system */ 611 612 /* sr-iov config info */ 613 struct i40e_vf *vf; 614 int num_alloc_vfs; /* actual number of VFs allocated */ 615 u32 vf_aq_requests; 616 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 617 618 /* DCBx/DCBNL capability for PF that indicates 619 * whether DCBx is managed by firmware or host 620 * based agent (LLDPAD). Also, indicates what 621 * flavor of DCBx protocol (IEEE/CEE) is supported 622 * by the device. For now we're supporting IEEE 623 * mode only. 624 */ 625 u16 dcbx_cap; 626 627 struct i40e_filter_control_settings filter_settings; 628 629 struct ptp_clock *ptp_clock; 630 struct ptp_clock_info ptp_caps; 631 struct sk_buff *ptp_tx_skb; 632 unsigned long ptp_tx_start; 633 struct hwtstamp_config tstamp_config; 634 struct timespec64 ptp_prev_hw_time; 635 ktime_t ptp_reset_start; 636 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 637 u32 ptp_adj_mult; 638 u32 tx_hwtstamp_timeouts; 639 u32 tx_hwtstamp_skipped; 640 u32 rx_hwtstamp_cleared; 641 u32 latch_event_flags; 642 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 643 unsigned long latch_events[4]; 644 bool ptp_tx; 645 bool ptp_rx; 646 u16 rss_table_size; /* HW RSS table size */ 647 u32 max_bw; 648 u32 min_bw; 649 650 u32 ioremap_len; 651 u32 fd_inv; 652 u16 phy_led_val; 653 654 u16 override_q_count; 655 u16 last_sw_conf_flags; 656 u16 last_sw_conf_valid_flags; 657 /* List to keep previous DDP profiles to be rolled back in the future */ 658 struct list_head ddp_old_prof; 659 }; 660 661 /** 662 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 663 * @macaddr: the MAC Address as the base key 664 * 665 * Simply copies the address and returns it as a u64 for hashing 666 **/ 667 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 668 { 669 u64 key = 0; 670 671 ether_addr_copy((u8 *)&key, macaddr); 672 return key; 673 } 674 675 enum i40e_filter_state { 676 I40E_FILTER_INVALID = 0, /* Invalid state */ 677 I40E_FILTER_NEW, /* New, not sent to FW yet */ 678 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 679 I40E_FILTER_FAILED, /* Rejected by FW */ 680 I40E_FILTER_REMOVE, /* To be removed */ 681 /* There is no 'removed' state; the filter struct is freed */ 682 }; 683 struct i40e_mac_filter { 684 struct hlist_node hlist; 685 u8 macaddr[ETH_ALEN]; 686 #define I40E_VLAN_ANY -1 687 s16 vlan; 688 enum i40e_filter_state state; 689 }; 690 691 /* Wrapper structure to keep track of filters while we are preparing to send 692 * firmware commands. We cannot send firmware commands while holding a 693 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 694 * a separate structure, which will track the state change and update the real 695 * filter while under lock. We can't simply hold the filters in a separate 696 * list, as this opens a window for a race condition when adding new MAC 697 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 698 */ 699 struct i40e_new_mac_filter { 700 struct hlist_node hlist; 701 struct i40e_mac_filter *f; 702 703 /* Track future changes to state separately */ 704 enum i40e_filter_state state; 705 }; 706 707 struct i40e_veb { 708 struct i40e_pf *pf; 709 u16 idx; 710 u16 veb_idx; /* index of VEB parent */ 711 u16 seid; 712 u16 uplink_seid; 713 u16 stats_idx; /* index of VEB parent */ 714 u8 enabled_tc; 715 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 716 u16 flags; 717 u16 bw_limit; 718 u8 bw_max_quanta; 719 bool is_abs_credits; 720 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 721 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 722 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 723 struct kobject *kobj; 724 bool stat_offsets_loaded; 725 struct i40e_eth_stats stats; 726 struct i40e_eth_stats stats_offsets; 727 struct i40e_veb_tc_stats tc_stats; 728 struct i40e_veb_tc_stats tc_stats_offsets; 729 }; 730 731 /* struct that defines a VSI, associated with a dev */ 732 struct i40e_vsi { 733 struct net_device *netdev; 734 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 735 bool netdev_registered; 736 bool stat_offsets_loaded; 737 738 u32 current_netdev_flags; 739 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 740 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 741 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 742 unsigned long flags; 743 744 /* Per VSI lock to protect elements/hash (MAC filter) */ 745 spinlock_t mac_filter_hash_lock; 746 /* Fixed size hash table with 2^8 buckets for MAC filters */ 747 DECLARE_HASHTABLE(mac_filter_hash, 8); 748 bool has_vlan_filter; 749 750 /* VSI stats */ 751 struct rtnl_link_stats64 net_stats; 752 struct rtnl_link_stats64 net_stats_offsets; 753 struct i40e_eth_stats eth_stats; 754 struct i40e_eth_stats eth_stats_offsets; 755 u32 tx_restart; 756 u32 tx_busy; 757 u64 tx_linearize; 758 u64 tx_force_wb; 759 u32 rx_buf_failed; 760 u32 rx_page_failed; 761 762 /* These are containers of ring pointers, allocated at run-time */ 763 struct i40e_ring **rx_rings; 764 struct i40e_ring **tx_rings; 765 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 766 767 u32 active_filters; 768 u32 promisc_threshold; 769 770 u16 work_limit; 771 u16 int_rate_limit; /* value in usecs */ 772 773 u16 rss_table_size; /* HW RSS table size */ 774 u16 rss_size; /* Allocated RSS queues */ 775 u8 *rss_hkey_user; /* User configured hash keys */ 776 u8 *rss_lut_user; /* User configured lookup table entries */ 777 778 779 u16 max_frame; 780 u16 rx_buf_len; 781 782 struct bpf_prog *xdp_prog; 783 784 /* List of q_vectors allocated to this VSI */ 785 struct i40e_q_vector **q_vectors; 786 int num_q_vectors; 787 int base_vector; 788 bool irqs_ready; 789 790 u16 seid; /* HW index of this VSI (absolute index) */ 791 u16 id; /* VSI number */ 792 u16 uplink_seid; 793 794 u16 base_queue; /* vsi's first queue in hw array */ 795 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 796 u16 req_queue_pairs; /* User requested queue pairs */ 797 u16 num_queue_pairs; /* Used tx and rx pairs */ 798 u16 num_tx_desc; 799 u16 num_rx_desc; 800 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 801 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 802 803 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 804 struct i40e_tc_configuration tc_config; 805 struct i40e_aqc_vsi_properties_data info; 806 807 /* VSI BW limit (absolute across all TCs) */ 808 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 809 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 810 811 /* Relative TC credits across VSIs */ 812 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 813 /* TC BW limit credits within VSI */ 814 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 815 /* TC BW limit max quanta within VSI */ 816 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 817 818 struct i40e_pf *back; /* Backreference to associated PF */ 819 u16 idx; /* index in pf->vsi[] */ 820 u16 veb_idx; /* index of VEB parent */ 821 struct kobject *kobj; /* sysfs object */ 822 bool current_isup; /* Sync 'link up' logging */ 823 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 824 825 /* channel specific fields */ 826 u16 cnt_q_avail; /* num of queues available for channel usage */ 827 u16 orig_rss_size; 828 u16 current_rss_size; 829 bool reconfig_rss; 830 831 u16 next_base_queue; /* next queue to be used for channel setup */ 832 833 struct list_head ch_list; 834 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 835 836 /* macvlan fields */ 837 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 838 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 839 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 840 struct list_head macvlan_list; 841 int macvlan_cnt; 842 843 void *priv; /* client driver data reference. */ 844 845 /* VSI specific handlers */ 846 irqreturn_t (*irq_handler)(int irq, void *data); 847 848 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 849 } ____cacheline_internodealigned_in_smp; 850 851 struct i40e_netdev_priv { 852 struct i40e_vsi *vsi; 853 }; 854 855 /* struct that defines an interrupt vector */ 856 struct i40e_q_vector { 857 struct i40e_vsi *vsi; 858 859 u16 v_idx; /* index in the vsi->q_vector array. */ 860 u16 reg_idx; /* register index of the interrupt */ 861 862 struct napi_struct napi; 863 864 struct i40e_ring_container rx; 865 struct i40e_ring_container tx; 866 867 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 868 u8 num_ringpairs; /* total number of ring pairs in vector */ 869 870 cpumask_t affinity_mask; 871 struct irq_affinity_notify affinity_notify; 872 873 struct rcu_head rcu; /* to avoid race with update stats on free */ 874 char name[I40E_INT_NAME_STR_LEN]; 875 bool arm_wb_state; 876 } ____cacheline_internodealigned_in_smp; 877 878 /* lan device */ 879 struct i40e_device { 880 struct list_head list; 881 struct i40e_pf *pf; 882 }; 883 884 /** 885 * i40e_nvm_version_str - format the NVM version strings 886 * @hw: ptr to the hardware info 887 **/ 888 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 889 { 890 static char buf[32]; 891 u32 full_ver; 892 893 full_ver = hw->nvm.oem_ver; 894 895 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 896 u8 gen, snap; 897 u16 release; 898 899 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 900 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 901 I40E_OEM_SNAP_SHIFT); 902 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 903 904 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 905 } else { 906 u8 ver, patch; 907 u16 build; 908 909 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 910 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 911 I40E_OEM_VER_BUILD_MASK); 912 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 913 914 snprintf(buf, sizeof(buf), 915 "%x.%02x 0x%x %d.%d.%d", 916 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 917 I40E_NVM_VERSION_HI_SHIFT, 918 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 919 I40E_NVM_VERSION_LO_SHIFT, 920 hw->nvm.eetrack, ver, build, patch); 921 } 922 923 return buf; 924 } 925 926 /** 927 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 928 * @netdev: the corresponding netdev 929 * 930 * Return the PF struct for the given netdev 931 **/ 932 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 933 { 934 struct i40e_netdev_priv *np = netdev_priv(netdev); 935 struct i40e_vsi *vsi = np->vsi; 936 937 return vsi->back; 938 } 939 940 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 941 irqreturn_t (*irq_handler)(int, void *)) 942 { 943 vsi->irq_handler = irq_handler; 944 } 945 946 /** 947 * i40e_get_fd_cnt_all - get the total FD filter space available 948 * @pf: pointer to the PF struct 949 **/ 950 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 951 { 952 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 953 } 954 955 /** 956 * i40e_read_fd_input_set - reads value of flow director input set register 957 * @pf: pointer to the PF struct 958 * @addr: register addr 959 * 960 * This function reads value of flow director input set register 961 * specified by 'addr' (which is specific to flow-type) 962 **/ 963 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 964 { 965 u64 val; 966 967 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 968 val <<= 32; 969 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 970 971 return val; 972 } 973 974 /** 975 * i40e_write_fd_input_set - writes value into flow director input set register 976 * @pf: pointer to the PF struct 977 * @addr: register addr 978 * @val: value to be written 979 * 980 * This function writes specified value to the register specified by 'addr'. 981 * This register is input set register based on flow-type. 982 **/ 983 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 984 u16 addr, u64 val) 985 { 986 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 987 (u32)(val >> 32)); 988 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 989 (u32)(val & 0xFFFFFFFFULL)); 990 } 991 992 /* needed by i40e_ethtool.c */ 993 int i40e_up(struct i40e_vsi *vsi); 994 void i40e_down(struct i40e_vsi *vsi); 995 extern const char i40e_driver_name[]; 996 extern const char i40e_driver_version_str[]; 997 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 998 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 999 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1000 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1001 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1002 u16 rss_table_size, u16 rss_size); 1003 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1004 /** 1005 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1006 * @pf: PF to search for VSI 1007 * @type: Value indicating type of VSI we are looking for 1008 **/ 1009 static inline struct i40e_vsi * 1010 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1011 { 1012 int i; 1013 1014 for (i = 0; i < pf->num_alloc_vsi; i++) { 1015 struct i40e_vsi *vsi = pf->vsi[i]; 1016 1017 if (vsi && vsi->type == type) 1018 return vsi; 1019 } 1020 1021 return NULL; 1022 } 1023 void i40e_update_stats(struct i40e_vsi *vsi); 1024 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1025 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1026 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1027 bool printconfig); 1028 1029 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1030 struct i40e_fdir_filter *input, bool add); 1031 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1032 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1033 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1034 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1035 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1036 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1037 void i40e_set_ethtool_ops(struct net_device *netdev); 1038 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1039 const u8 *macaddr, s16 vlan); 1040 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1041 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1042 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1043 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1044 u16 uplink, u32 param1); 1045 int i40e_vsi_release(struct i40e_vsi *vsi); 1046 void i40e_service_event_schedule(struct i40e_pf *pf); 1047 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1048 u8 *msg, u16 len); 1049 1050 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1051 bool enable); 1052 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1053 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1054 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1055 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1056 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1057 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1058 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1059 u16 downlink_seid, u8 enabled_tc); 1060 void i40e_veb_release(struct i40e_veb *veb); 1061 1062 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1063 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1064 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1065 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1066 void i40e_pf_reset_stats(struct i40e_pf *pf); 1067 #ifdef CONFIG_DEBUG_FS 1068 void i40e_dbg_pf_init(struct i40e_pf *pf); 1069 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1070 void i40e_dbg_init(void); 1071 void i40e_dbg_exit(void); 1072 #else 1073 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1074 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1075 static inline void i40e_dbg_init(void) {} 1076 static inline void i40e_dbg_exit(void) {} 1077 #endif /* CONFIG_DEBUG_FS*/ 1078 /* needed by client drivers */ 1079 int i40e_lan_add_device(struct i40e_pf *pf); 1080 int i40e_lan_del_device(struct i40e_pf *pf); 1081 void i40e_client_subtask(struct i40e_pf *pf); 1082 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1083 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1084 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1085 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1086 void i40e_client_update_msix_info(struct i40e_pf *pf); 1087 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1088 /** 1089 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1090 * @vsi: pointer to a vsi 1091 * @vector: enable a particular Hw Interrupt vector, without base_vector 1092 **/ 1093 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1094 { 1095 struct i40e_pf *pf = vsi->back; 1096 struct i40e_hw *hw = &pf->hw; 1097 u32 val; 1098 1099 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1100 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1101 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1102 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1103 /* skip the flush */ 1104 } 1105 1106 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1107 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1108 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1109 int i40e_open(struct net_device *netdev); 1110 int i40e_close(struct net_device *netdev); 1111 int i40e_vsi_open(struct i40e_vsi *vsi); 1112 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1113 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1114 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1115 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1116 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1117 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1118 const u8 *macaddr); 1119 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1120 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1121 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1122 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1123 #ifdef CONFIG_I40E_DCB 1124 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1125 struct i40e_dcbx_config *old_cfg, 1126 struct i40e_dcbx_config *new_cfg); 1127 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1128 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1129 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1130 struct i40e_dcbx_config *old_cfg, 1131 struct i40e_dcbx_config *new_cfg); 1132 #endif /* CONFIG_I40E_DCB */ 1133 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1134 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1135 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1136 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1137 void i40e_ptp_set_increment(struct i40e_pf *pf); 1138 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1139 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1140 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1141 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1142 void i40e_ptp_init(struct i40e_pf *pf); 1143 void i40e_ptp_stop(struct i40e_pf *pf); 1144 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1145 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1146 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1147 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1148 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1149 1150 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1151 1152 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1153 { 1154 return !!vsi->xdp_prog; 1155 } 1156 1157 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1158 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1159 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1160 struct i40e_cloud_filter *filter, 1161 bool add); 1162 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1163 struct i40e_cloud_filter *filter, 1164 bool add); 1165 #endif /* _I40E_H_ */ 1166