1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3 
4 #ifndef _I40E_H_
5 #define _I40E_H_
6 
7 #include <linux/ethtool.h>
8 #include <linux/pci.h>
9 #include <linux/ptp_clock_kernel.h>
10 #include <linux/types.h>
11 #include <linux/avf/virtchnl.h>
12 #include <linux/net/intel/i40e_client.h>
13 #include <net/pkt_cls.h>
14 #include <net/udp_tunnel.h>
15 #include "i40e_dcb.h"
16 #include "i40e_debug.h"
17 #include "i40e_io.h"
18 #include "i40e_prototype.h"
19 #include "i40e_register.h"
20 #include "i40e_txrx.h"
21 
22 /* Useful i40e defaults */
23 #define I40E_MAX_VEB			16
24 
25 #define I40E_MAX_NUM_DESCRIPTORS	4096
26 #define I40E_MAX_CSR_SPACE		(4 * 1024 * 1024 - 64 * 1024)
27 #define I40E_DEFAULT_NUM_DESCRIPTORS	512
28 #define I40E_REQ_DESCRIPTOR_MULTIPLE	32
29 #define I40E_MIN_NUM_DESCRIPTORS	64
30 #define I40E_MIN_MSIX			2
31 #define I40E_DEFAULT_NUM_VMDQ_VSI	8 /* max 256 VSIs */
32 #define I40E_MIN_VSI_ALLOC		83 /* LAN, ATR, FCOE, 64 VF */
33 /* max 16 qps */
34 #define i40e_default_queues_per_vmdq(pf) \
35 		(((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
36 #define I40E_DEFAULT_QUEUES_PER_VF	4
37 #define I40E_MAX_VF_QUEUES		16
38 #define i40e_pf_get_max_q_per_tc(pf) \
39 		(((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
40 #define I40E_FDIR_RING_COUNT		32
41 #define I40E_MAX_AQ_BUF_SIZE		4096
42 #define I40E_AQ_LEN			256
43 #define I40E_MIN_ARQ_LEN		1
44 #define I40E_MIN_ASQ_LEN		2
45 #define I40E_AQ_WORK_LIMIT		66 /* max number of VFs + a little */
46 #define I40E_MAX_USER_PRIORITY		8
47 #define I40E_DEFAULT_TRAFFIC_CLASS	BIT(0)
48 #define I40E_QUEUE_WAIT_RETRY_LIMIT	10
49 #define I40E_INT_NAME_STR_LEN		(IFNAMSIZ + 16)
50 
51 #define I40E_NVM_VERSION_LO_SHIFT	0
52 #define I40E_NVM_VERSION_LO_MASK	(0xff << I40E_NVM_VERSION_LO_SHIFT)
53 #define I40E_NVM_VERSION_HI_SHIFT	12
54 #define I40E_NVM_VERSION_HI_MASK	(0xf << I40E_NVM_VERSION_HI_SHIFT)
55 #define I40E_OEM_VER_BUILD_MASK		0xffff
56 #define I40E_OEM_VER_PATCH_MASK		0xff
57 #define I40E_OEM_VER_BUILD_SHIFT	8
58 #define I40E_OEM_VER_SHIFT		24
59 #define I40E_PHY_DEBUG_ALL \
60 	(I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
61 	I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
62 
63 #define I40E_OEM_EETRACK_ID		0xffffffff
64 #define I40E_OEM_GEN_SHIFT		24
65 #define I40E_OEM_SNAP_MASK		0x00ff0000
66 #define I40E_OEM_SNAP_SHIFT		16
67 #define I40E_OEM_RELEASE_MASK		0x0000ffff
68 
69 #define I40E_RX_DESC(R, i)	\
70 	(&(((union i40e_rx_desc *)((R)->desc))[i]))
71 #define I40E_TX_DESC(R, i)	\
72 	(&(((struct i40e_tx_desc *)((R)->desc))[i]))
73 #define I40E_TX_CTXTDESC(R, i)	\
74 	(&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
75 #define I40E_TX_FDIRDESC(R, i)	\
76 	(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
77 
78 /* BW rate limiting */
79 #define I40E_BW_CREDIT_DIVISOR		50 /* 50Mbps per BW credit */
80 #define I40E_BW_MBPS_DIVISOR		125000 /* rate / (1000000 / 8) Mbps */
81 #define I40E_MAX_BW_INACTIVE_ACCUM	4 /* accumulate 4 credits max */
82 
83 /* driver state flags */
84 enum i40e_state {
85 	__I40E_TESTING,
86 	__I40E_CONFIG_BUSY,
87 	__I40E_CONFIG_DONE,
88 	__I40E_DOWN,
89 	__I40E_SERVICE_SCHED,
90 	__I40E_ADMINQ_EVENT_PENDING,
91 	__I40E_MDD_EVENT_PENDING,
92 	__I40E_VFLR_EVENT_PENDING,
93 	__I40E_RESET_RECOVERY_PENDING,
94 	__I40E_TIMEOUT_RECOVERY_PENDING,
95 	__I40E_MISC_IRQ_REQUESTED,
96 	__I40E_RESET_INTR_RECEIVED,
97 	__I40E_REINIT_REQUESTED,
98 	__I40E_PF_RESET_REQUESTED,
99 	__I40E_PF_RESET_AND_REBUILD_REQUESTED,
100 	__I40E_CORE_RESET_REQUESTED,
101 	__I40E_GLOBAL_RESET_REQUESTED,
102 	__I40E_EMP_RESET_INTR_RECEIVED,
103 	__I40E_SUSPENDED,
104 	__I40E_PTP_TX_IN_PROGRESS,
105 	__I40E_BAD_EEPROM,
106 	__I40E_DOWN_REQUESTED,
107 	__I40E_FD_FLUSH_REQUESTED,
108 	__I40E_FD_ATR_AUTO_DISABLED,
109 	__I40E_FD_SB_AUTO_DISABLED,
110 	__I40E_RESET_FAILED,
111 	__I40E_PORT_SUSPENDED,
112 	__I40E_VF_DISABLE,
113 	__I40E_MACVLAN_SYNC_PENDING,
114 	__I40E_TEMP_LINK_POLLING,
115 	__I40E_CLIENT_SERVICE_REQUESTED,
116 	__I40E_CLIENT_L2_CHANGE,
117 	__I40E_CLIENT_RESET,
118 	__I40E_VIRTCHNL_OP_PENDING,
119 	__I40E_RECOVERY_MODE,
120 	__I40E_VF_RESETS_DISABLED,	/* disable resets during i40e_remove */
121 	__I40E_IN_REMOVE,
122 	__I40E_VFS_RELEASING,
123 	/* This must be last as it determines the size of the BITMAP */
124 	__I40E_STATE_SIZE__,
125 };
126 
127 #define I40E_PF_RESET_FLAG	BIT_ULL(__I40E_PF_RESET_REQUESTED)
128 #define I40E_PF_RESET_AND_REBUILD_FLAG	\
129 	BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
130 
131 /* VSI state flags */
132 enum i40e_vsi_state {
133 	__I40E_VSI_DOWN,
134 	__I40E_VSI_NEEDS_RESTART,
135 	__I40E_VSI_SYNCING_FILTERS,
136 	__I40E_VSI_OVERFLOW_PROMISC,
137 	__I40E_VSI_REINIT_REQUESTED,
138 	__I40E_VSI_DOWN_REQUESTED,
139 	__I40E_VSI_RELEASING,
140 	/* This must be last as it determines the size of the BITMAP */
141 	__I40E_VSI_STATE_SIZE__,
142 };
143 
144 enum i40e_interrupt_policy {
145 	I40E_INTERRUPT_BEST_CASE,
146 	I40E_INTERRUPT_MEDIUM,
147 	I40E_INTERRUPT_LOWEST
148 };
149 
150 struct i40e_lump_tracking {
151 	u16 num_entries;
152 	u16 list[];
153 #define I40E_PILE_VALID_BIT  0x8000
154 #define I40E_IWARP_IRQ_PILE_ID  (I40E_PILE_VALID_BIT - 2)
155 };
156 
157 #define I40E_DEFAULT_ATR_SAMPLE_RATE	20
158 #define I40E_FDIR_MAX_RAW_PACKET_SIZE	512
159 #define I40E_FDIR_BUFFER_FULL_MARGIN	10
160 #define I40E_FDIR_BUFFER_HEAD_ROOM	32
161 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
162 
163 #define I40E_HKEY_ARRAY_SIZE	((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
164 #define I40E_HLUT_ARRAY_SIZE	((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
165 #define I40E_VF_HLUT_ARRAY_SIZE	((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
166 
167 enum i40e_fd_stat_idx {
168 	I40E_FD_STAT_ATR,
169 	I40E_FD_STAT_SB,
170 	I40E_FD_STAT_ATR_TUNNEL,
171 	I40E_FD_STAT_PF_COUNT
172 };
173 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
174 #define I40E_FD_ATR_STAT_IDX(pf_id) \
175 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
176 #define I40E_FD_SB_STAT_IDX(pf_id)  \
177 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
178 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
179 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
180 
181 /* The following structure contains the data parsed from the user-defined
182  * field of the ethtool_rx_flow_spec structure.
183  */
184 struct i40e_rx_flow_userdef {
185 	bool flex_filter;
186 	u16 flex_word;
187 	u16 flex_offset;
188 };
189 
190 struct i40e_fdir_filter {
191 	struct hlist_node fdir_node;
192 	/* filter ipnut set */
193 	u8 flow_type;
194 	u8 ipl4_proto;
195 	/* TX packet view of src and dst */
196 	__be32 dst_ip;
197 	__be32 src_ip;
198 	__be32 dst_ip6[4];
199 	__be32 src_ip6[4];
200 	__be16 src_port;
201 	__be16 dst_port;
202 	__be32 sctp_v_tag;
203 
204 	__be16 vlan_etype;
205 	__be16 vlan_tag;
206 	/* Flexible data to match within the packet payload */
207 	__be16 flex_word;
208 	u16 flex_offset;
209 	bool flex_filter;
210 
211 	/* filter control */
212 	u16 q_index;
213 	u8  flex_off;
214 	u8  pctype;
215 	u16 dest_vsi;
216 	u8  dest_ctl;
217 	u8  fd_status;
218 	u16 cnt_index;
219 	u32 fd_id;
220 };
221 
222 #define I40E_CLOUD_FIELD_OMAC		BIT(0)
223 #define I40E_CLOUD_FIELD_IMAC		BIT(1)
224 #define I40E_CLOUD_FIELD_IVLAN		BIT(2)
225 #define I40E_CLOUD_FIELD_TEN_ID		BIT(3)
226 #define I40E_CLOUD_FIELD_IIP		BIT(4)
227 
228 #define I40E_CLOUD_FILTER_FLAGS_OMAC	I40E_CLOUD_FIELD_OMAC
229 #define I40E_CLOUD_FILTER_FLAGS_IMAC	I40E_CLOUD_FIELD_IMAC
230 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN	(I40E_CLOUD_FIELD_IMAC | \
231 						 I40E_CLOUD_FIELD_IVLAN)
232 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID	(I40E_CLOUD_FIELD_IMAC | \
233 						 I40E_CLOUD_FIELD_TEN_ID)
234 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
235 						  I40E_CLOUD_FIELD_IMAC | \
236 						  I40E_CLOUD_FIELD_TEN_ID)
237 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
238 						   I40E_CLOUD_FIELD_IVLAN | \
239 						   I40E_CLOUD_FIELD_TEN_ID)
240 #define I40E_CLOUD_FILTER_FLAGS_IIP	I40E_CLOUD_FIELD_IIP
241 
242 struct i40e_cloud_filter {
243 	struct hlist_node cloud_node;
244 	unsigned long cookie;
245 	/* cloud filter input set follows */
246 	u8 dst_mac[ETH_ALEN];
247 	u8 src_mac[ETH_ALEN];
248 	__be16 vlan_id;
249 	u16 seid;       /* filter control */
250 	__be16 dst_port;
251 	__be16 src_port;
252 	u32 tenant_id;
253 	union {
254 		struct {
255 			struct in_addr dst_ip;
256 			struct in_addr src_ip;
257 		} v4;
258 		struct {
259 			struct in6_addr dst_ip6;
260 			struct in6_addr src_ip6;
261 		} v6;
262 	} ip;
263 #define dst_ipv6	ip.v6.dst_ip6.s6_addr32
264 #define src_ipv6	ip.v6.src_ip6.s6_addr32
265 #define dst_ipv4	ip.v4.dst_ip.s_addr
266 #define src_ipv4	ip.v4.src_ip.s_addr
267 	u16 n_proto;    /* Ethernet Protocol */
268 	u8 ip_proto;    /* IPPROTO value */
269 	u8 flags;
270 #define I40E_CLOUD_TNL_TYPE_NONE        0xff
271 	u8 tunnel_type;
272 };
273 
274 #define I40E_DCB_PRIO_TYPE_STRICT	0
275 #define I40E_DCB_PRIO_TYPE_ETS		1
276 #define I40E_DCB_STRICT_PRIO_CREDITS	127
277 /* DCB per TC information data structure */
278 struct i40e_tc_info {
279 	u16	qoffset;	/* Queue offset from base queue */
280 	u16	qcount;		/* Total Queues */
281 	u8	netdev_tc;	/* Netdev TC index if netdev associated */
282 };
283 
284 /* TC configuration data structure */
285 struct i40e_tc_configuration {
286 	u8	numtc;		/* Total number of enabled TCs */
287 	u8	enabled_tc;	/* TC map */
288 	struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
289 };
290 
291 #define I40E_UDP_PORT_INDEX_UNUSED	255
292 struct i40e_udp_port_config {
293 	/* AdminQ command interface expects port number in Host byte order */
294 	u16 port;
295 	u8 type;
296 	u8 filter_index;
297 };
298 
299 #define I40_DDP_FLASH_REGION 100
300 #define I40E_PROFILE_INFO_SIZE 48
301 #define I40E_MAX_PROFILE_NUM 16
302 #define I40E_PROFILE_LIST_SIZE \
303 	(I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
304 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
305 #define I40E_DDP_PROFILE_NAME_MAX 64
306 
307 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
308 		  bool is_add);
309 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
310 
311 struct i40e_ddp_profile_list {
312 	u32 p_count;
313 	struct i40e_profile_info p_info[];
314 };
315 
316 struct i40e_ddp_old_profile_list {
317 	struct list_head list;
318 	size_t old_ddp_size;
319 	u8 old_ddp_buf[];
320 };
321 
322 /* macros related to FLX_PIT */
323 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
324 				    I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
325 				    I40E_PRTQF_FLX_PIT_FSIZE_MASK)
326 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
327 				     I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
328 				     I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
329 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
330 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
331 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
332 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
333 					     I40E_FLEX_SET_FSIZE(fsize) | \
334 					     I40E_FLEX_SET_SRC_WORD(src))
335 
336 
337 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
338 
339 /* macros related to GLQF_ORT */
340 #define I40E_ORT_SET_IDX(idx)		(((idx) << \
341 					  I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
342 					 I40E_GLQF_ORT_PIT_INDX_MASK)
343 
344 #define I40E_ORT_SET_COUNT(count)	(((count) << \
345 					  I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
346 					 I40E_GLQF_ORT_FIELD_CNT_MASK)
347 
348 #define I40E_ORT_SET_PAYLOAD(payload)	(((payload) << \
349 					  I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
350 					 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
351 
352 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
353 						I40E_ORT_SET_COUNT(count) | \
354 						I40E_ORT_SET_PAYLOAD(payload))
355 
356 #define I40E_L3_GLQF_ORT_IDX		34
357 #define I40E_L4_GLQF_ORT_IDX		35
358 
359 /* Flex PIT register index */
360 #define I40E_FLEX_PIT_IDX_START_L3	3
361 #define I40E_FLEX_PIT_IDX_START_L4	6
362 
363 #define I40E_FLEX_PIT_TABLE_SIZE	3
364 
365 #define I40E_FLEX_DEST_UNUSED		63
366 
367 #define I40E_FLEX_INDEX_ENTRIES		8
368 
369 /* Flex MASK to disable all flexible entries */
370 #define I40E_FLEX_INPUT_MASK	(I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
371 				 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
372 				 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
373 				 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
374 
375 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
376 	(I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
377 	(I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
378 	((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
379 	((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
380 	(I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
381 
382 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
383 	(I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
384 	(I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
385 	((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
386 	((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
387 	(I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
388 
389 struct i40e_flex_pit {
390 	struct list_head list;
391 	u16 src_offset;
392 	u8 pit_index;
393 };
394 
395 struct i40e_fwd_adapter {
396 	struct net_device *netdev;
397 	int bit_no;
398 };
399 
400 struct i40e_channel {
401 	struct list_head list;
402 	bool initialized;
403 	u8 type;
404 	u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
405 	u16 stat_counter_idx;
406 	u16 base_queue;
407 	u16 num_queue_pairs; /* Requested by user */
408 	u16 seid;
409 
410 	u8 enabled_tc;
411 	struct i40e_aqc_vsi_properties_data info;
412 
413 	u64 max_tx_rate;
414 	struct i40e_fwd_adapter *fwd;
415 
416 	/* track this channel belongs to which VSI */
417 	struct i40e_vsi *parent_vsi;
418 };
419 
420 struct i40e_ptp_pins_settings;
421 
422 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
423 {
424 	return !!ch->fwd;
425 }
426 
427 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
428 {
429 	if (i40e_is_channel_macvlan(ch))
430 		return ch->fwd->netdev->dev_addr;
431 	else
432 		return NULL;
433 }
434 
435 /* struct that defines the Ethernet device */
436 struct i40e_pf {
437 	struct pci_dev *pdev;
438 	struct i40e_hw hw;
439 	DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
440 	struct msix_entry *msix_entries;
441 	bool fc_autoneg_status;
442 
443 	u16 eeprom_version;
444 	u16 num_vmdq_vsis;         /* num vmdq vsis this PF has set up */
445 	u16 num_vmdq_qps;          /* num queue pairs per vmdq pool */
446 	u16 num_vmdq_msix;         /* num queue vectors per vmdq pool */
447 	u16 num_req_vfs;           /* num VFs requested for this PF */
448 	u16 num_vf_qps;            /* num queue pairs per VF */
449 	u16 num_lan_qps;           /* num lan queues this PF has set up */
450 	u16 num_lan_msix;          /* num queue vectors for the base PF vsi */
451 	u16 num_fdsb_msix;         /* num queue vectors for sideband Fdir */
452 	u16 num_iwarp_msix;        /* num of iwarp vectors for this PF */
453 	int iwarp_base_vector;
454 	int queues_left;           /* queues left unclaimed */
455 	u16 alloc_rss_size;        /* allocated RSS queues */
456 	u16 rss_size_max;          /* HW defined max RSS queues */
457 	u16 fdir_pf_filter_count;  /* num of guaranteed filters for this PF */
458 	u16 num_alloc_vsi;         /* num VSIs this driver supports */
459 	u8 atr_sample_rate;
460 	bool wol_en;
461 
462 	struct hlist_head fdir_filter_list;
463 	u16 fdir_pf_active_filters;
464 	unsigned long fd_flush_timestamp;
465 	u32 fd_flush_cnt;
466 	u32 fd_add_err;
467 	u32 fd_atr_cnt;
468 
469 	/* Book-keeping of side-band filter count per flow-type.
470 	 * This is used to detect and handle input set changes for
471 	 * respective flow-type.
472 	 */
473 	u16 fd_tcp4_filter_cnt;
474 	u16 fd_udp4_filter_cnt;
475 	u16 fd_sctp4_filter_cnt;
476 	u16 fd_ip4_filter_cnt;
477 
478 	u16 fd_tcp6_filter_cnt;
479 	u16 fd_udp6_filter_cnt;
480 	u16 fd_sctp6_filter_cnt;
481 	u16 fd_ip6_filter_cnt;
482 
483 	/* Flexible filter table values that need to be programmed into
484 	 * hardware, which expects L3 and L4 to be programmed separately. We
485 	 * need to ensure that the values are in ascended order and don't have
486 	 * duplicates, so we track each L3 and L4 values in separate lists.
487 	 */
488 	struct list_head l3_flex_pit_list;
489 	struct list_head l4_flex_pit_list;
490 
491 	struct udp_tunnel_nic_shared udp_tunnel_shared;
492 	struct udp_tunnel_nic_info udp_tunnel_nic;
493 
494 	struct hlist_head cloud_filter_list;
495 	u16 num_cloud_filters;
496 
497 	enum i40e_interrupt_policy int_policy;
498 	u16 rx_itr_default;
499 	u16 tx_itr_default;
500 	u32 msg_enable;
501 	char int_name[I40E_INT_NAME_STR_LEN];
502 	u16 adminq_work_limit; /* num of admin receive queue desc to process */
503 	unsigned long service_timer_period;
504 	unsigned long service_timer_previous;
505 	struct timer_list service_timer;
506 	struct work_struct service_task;
507 
508 	u32 hw_features;
509 #define I40E_HW_RSS_AQ_CAPABLE			BIT(0)
510 #define I40E_HW_128_QP_RSS_CAPABLE		BIT(1)
511 #define I40E_HW_ATR_EVICT_CAPABLE		BIT(2)
512 #define I40E_HW_WB_ON_ITR_CAPABLE		BIT(3)
513 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE	BIT(4)
514 #define I40E_HW_NO_PCI_LINK_CHECK		BIT(5)
515 #define I40E_HW_100M_SGMII_CAPABLE		BIT(6)
516 #define I40E_HW_NO_DCB_SUPPORT			BIT(7)
517 #define I40E_HW_USE_SET_LLDP_MIB		BIT(8)
518 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE		BIT(9)
519 #define I40E_HW_PTP_L4_CAPABLE			BIT(10)
520 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE		BIT(11)
521 #define I40E_HW_HAVE_CRT_RETIMER		BIT(13)
522 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE		BIT(14)
523 #define I40E_HW_PHY_CONTROLS_LEDS		BIT(15)
524 #define I40E_HW_STOP_FW_LLDP			BIT(16)
525 #define I40E_HW_PORT_ID_VALID			BIT(17)
526 #define I40E_HW_RESTART_AUTONEG			BIT(18)
527 
528 	u32 flags;
529 #define I40E_FLAG_RX_CSUM_ENABLED		BIT(0)
530 #define I40E_FLAG_MSI_ENABLED			BIT(1)
531 #define I40E_FLAG_MSIX_ENABLED			BIT(2)
532 #define I40E_FLAG_RSS_ENABLED			BIT(3)
533 #define I40E_FLAG_VMDQ_ENABLED			BIT(4)
534 #define I40E_FLAG_SRIOV_ENABLED			BIT(5)
535 #define I40E_FLAG_DCB_CAPABLE			BIT(6)
536 #define I40E_FLAG_DCB_ENABLED			BIT(7)
537 #define I40E_FLAG_FD_SB_ENABLED			BIT(8)
538 #define I40E_FLAG_FD_ATR_ENABLED		BIT(9)
539 #define I40E_FLAG_MFP_ENABLED			BIT(10)
540 #define I40E_FLAG_HW_ATR_EVICT_ENABLED		BIT(11)
541 #define I40E_FLAG_VEB_MODE_ENABLED		BIT(12)
542 #define I40E_FLAG_VEB_STATS_ENABLED		BIT(13)
543 #define I40E_FLAG_LINK_POLLING_ENABLED		BIT(14)
544 #define I40E_FLAG_TRUE_PROMISC_SUPPORT		BIT(15)
545 #define I40E_FLAG_LEGACY_RX			BIT(16)
546 #define I40E_FLAG_PTP				BIT(17)
547 #define I40E_FLAG_IWARP_ENABLED			BIT(18)
548 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(19)
549 #define I40E_FLAG_SOURCE_PRUNING_DISABLED       BIT(20)
550 #define I40E_FLAG_TC_MQPRIO			BIT(21)
551 #define I40E_FLAG_FD_SB_INACTIVE		BIT(22)
552 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER		BIT(23)
553 #define I40E_FLAG_DISABLE_FW_LLDP		BIT(24)
554 #define I40E_FLAG_RS_FEC			BIT(25)
555 #define I40E_FLAG_BASE_R_FEC			BIT(26)
556 /* TOTAL_PORT_SHUTDOWN
557  * Allows to physically disable the link on the NIC's port.
558  * If enabled, (after link down request from the OS)
559  * no link, traffic or led activity is possible on that port.
560  *
561  * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
562  * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
563  * and cannot be disabled by system admin at that time.
564  * The functionalities are exclusive in terms of configuration, but they also
565  * have similar behavior (allowing to disable physical link of the port),
566  * with following differences:
567  * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
568  *   supported by whole family of 7xx Intel Ethernet Controllers
569  * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
570  *   only if motherboard's BIOS and NIC's FW has support of it
571  * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
572  *   by sending phy_type=0 to NIC's FW
573  * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
574  *   the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
575  *   in abilities field of i40e_aq_set_phy_config structure
576  */
577 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED	BIT(27)
578 #define I40E_FLAG_VF_VLAN_PRUNING		BIT(28)
579 
580 	struct i40e_client_instance *cinst;
581 	bool stat_offsets_loaded;
582 	struct i40e_hw_port_stats stats;
583 	struct i40e_hw_port_stats stats_offsets;
584 	u32 tx_timeout_count;
585 	u32 tx_timeout_recovery_level;
586 	unsigned long tx_timeout_last_recovery;
587 	u32 tx_sluggish_count;
588 	u32 hw_csum_rx_error;
589 	u32 led_status;
590 	u16 corer_count; /* Core reset count */
591 	u16 globr_count; /* Global reset count */
592 	u16 empr_count; /* EMP reset count */
593 	u16 pfr_count; /* PF reset count */
594 	u16 sw_int_count; /* SW interrupt count */
595 
596 	struct mutex switch_mutex;
597 	u16 lan_vsi;       /* our default LAN VSI */
598 	u16 lan_veb;       /* initial relay, if exists */
599 #define I40E_NO_VEB	0xffff
600 #define I40E_NO_VSI	0xffff
601 	u16 next_vsi;      /* Next unallocated VSI - 0-based! */
602 	struct i40e_vsi **vsi;
603 	struct i40e_veb *veb[I40E_MAX_VEB];
604 
605 	struct i40e_lump_tracking *qp_pile;
606 	struct i40e_lump_tracking *irq_pile;
607 
608 	/* switch config info */
609 	u16 pf_seid;
610 	u16 main_vsi_seid;
611 	u16 mac_seid;
612 	struct kobject *switch_kobj;
613 #ifdef CONFIG_DEBUG_FS
614 	struct dentry *i40e_dbg_pf;
615 #endif /* CONFIG_DEBUG_FS */
616 	bool cur_promisc;
617 
618 	u16 instance; /* A unique number per i40e_pf instance in the system */
619 
620 	/* sr-iov config info */
621 	struct i40e_vf *vf;
622 	int num_alloc_vfs;	/* actual number of VFs allocated */
623 	u32 vf_aq_requests;
624 	u32 arq_overflows;	/* Not fatal, possibly indicative of problems */
625 
626 	/* DCBx/DCBNL capability for PF that indicates
627 	 * whether DCBx is managed by firmware or host
628 	 * based agent (LLDPAD). Also, indicates what
629 	 * flavor of DCBx protocol (IEEE/CEE) is supported
630 	 * by the device. For now we're supporting IEEE
631 	 * mode only.
632 	 */
633 	u16 dcbx_cap;
634 
635 	struct i40e_filter_control_settings filter_settings;
636 	struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
637 	struct i40e_dcbx_config tmp_cfg;
638 
639 /* GPIO defines used by PTP */
640 #define I40E_SDP3_2			18
641 #define I40E_SDP3_3			19
642 #define I40E_GPIO_4			20
643 #define I40E_LED2_0			26
644 #define I40E_LED2_1			27
645 #define I40E_LED3_0			28
646 #define I40E_LED3_1			29
647 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
648 	(1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
649 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
650 	(1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
651 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
652 	(0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
653 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
654 	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
655 #define I40E_GLGEN_GPIO_CTL_RESERVED	BIT(2)
656 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
657 	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
658 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
659 	(1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
660 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
661 	(1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
662 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
663 	(1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
664 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
665 	(3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
666 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
667 	(4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
668 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
669 	(0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
670 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
671 	(1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
672 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
673 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
674 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
675 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
676 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
677 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
678 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
679 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
680 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
681 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
682 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
683 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
684 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
685 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
686 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
687 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
688 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
689 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
690 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
691 	(I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
692 	 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
693 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
694 	 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
695 	 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
696 	 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
697 #define I40E_PRTTSYN_AUX_1_INSTNT \
698 	(1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
699 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
700 	(1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
701 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD	(3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
702 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
703 	(I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
704 #define I40E_PTP_HALF_SECOND		500000000LL /* nano seconds */
705 #define I40E_PTP_2_SEC_DELAY		2
706 
707 	struct ptp_clock *ptp_clock;
708 	struct ptp_clock_info ptp_caps;
709 	struct sk_buff *ptp_tx_skb;
710 	unsigned long ptp_tx_start;
711 	struct hwtstamp_config tstamp_config;
712 	struct timespec64 ptp_prev_hw_time;
713 	struct work_struct ptp_pps_work;
714 	struct work_struct ptp_extts0_work;
715 	struct work_struct ptp_extts1_work;
716 	ktime_t ptp_reset_start;
717 	struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
718 	u32 ptp_adj_mult;
719 	u32 tx_hwtstamp_timeouts;
720 	u32 tx_hwtstamp_skipped;
721 	u32 rx_hwtstamp_cleared;
722 	u32 latch_event_flags;
723 	u64 ptp_pps_start;
724 	u32 pps_delay;
725 	spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
726 	struct ptp_pin_desc ptp_pin[3];
727 	unsigned long latch_events[4];
728 	bool ptp_tx;
729 	bool ptp_rx;
730 	struct i40e_ptp_pins_settings *ptp_pins;
731 	u16 rss_table_size; /* HW RSS table size */
732 	u32 max_bw;
733 	u32 min_bw;
734 
735 	u32 ioremap_len;
736 	u32 fd_inv;
737 	u16 phy_led_val;
738 
739 	u16 override_q_count;
740 	u16 last_sw_conf_flags;
741 	u16 last_sw_conf_valid_flags;
742 	/* List to keep previous DDP profiles to be rolled back in the future */
743 	struct list_head ddp_old_prof;
744 };
745 
746 /**
747  * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
748  * @macaddr: the MAC Address as the base key
749  *
750  * Simply copies the address and returns it as a u64 for hashing
751  **/
752 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
753 {
754 	u64 key = 0;
755 
756 	ether_addr_copy((u8 *)&key, macaddr);
757 	return key;
758 }
759 
760 enum i40e_filter_state {
761 	I40E_FILTER_INVALID = 0,	/* Invalid state */
762 	I40E_FILTER_NEW,		/* New, not sent to FW yet */
763 	I40E_FILTER_ACTIVE,		/* Added to switch by FW */
764 	I40E_FILTER_FAILED,		/* Rejected by FW */
765 	I40E_FILTER_REMOVE,		/* To be removed */
766 /* There is no 'removed' state; the filter struct is freed */
767 };
768 struct i40e_mac_filter {
769 	struct hlist_node hlist;
770 	u8 macaddr[ETH_ALEN];
771 #define I40E_VLAN_ANY -1
772 	s16 vlan;
773 	enum i40e_filter_state state;
774 };
775 
776 /* Wrapper structure to keep track of filters while we are preparing to send
777  * firmware commands. We cannot send firmware commands while holding a
778  * spinlock, since it might sleep. To avoid this, we wrap the added filters in
779  * a separate structure, which will track the state change and update the real
780  * filter while under lock. We can't simply hold the filters in a separate
781  * list, as this opens a window for a race condition when adding new MAC
782  * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
783  */
784 struct i40e_new_mac_filter {
785 	struct hlist_node hlist;
786 	struct i40e_mac_filter *f;
787 
788 	/* Track future changes to state separately */
789 	enum i40e_filter_state state;
790 };
791 
792 struct i40e_veb {
793 	struct i40e_pf *pf;
794 	u16 idx;
795 	u16 veb_idx;		/* index of VEB parent */
796 	u16 seid;
797 	u16 uplink_seid;
798 	u16 stats_idx;		/* index of VEB parent */
799 	u8  enabled_tc;
800 	u16 bridge_mode;	/* Bridge Mode (VEB/VEPA) */
801 	u16 flags;
802 	u16 bw_limit;
803 	u8  bw_max_quanta;
804 	bool is_abs_credits;
805 	u8  bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
806 	u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
807 	u8  bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
808 	struct kobject *kobj;
809 	bool stat_offsets_loaded;
810 	struct i40e_eth_stats stats;
811 	struct i40e_eth_stats stats_offsets;
812 	struct i40e_veb_tc_stats tc_stats;
813 	struct i40e_veb_tc_stats tc_stats_offsets;
814 };
815 
816 /* struct that defines a VSI, associated with a dev */
817 struct i40e_vsi {
818 	struct net_device *netdev;
819 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
820 	bool netdev_registered;
821 	bool stat_offsets_loaded;
822 
823 	u32 current_netdev_flags;
824 	DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
825 #define I40E_VSI_FLAG_FILTER_CHANGED	BIT(0)
826 #define I40E_VSI_FLAG_VEB_OWNER		BIT(1)
827 	unsigned long flags;
828 
829 	/* Per VSI lock to protect elements/hash (MAC filter) */
830 	spinlock_t mac_filter_hash_lock;
831 	/* Fixed size hash table with 2^8 buckets for MAC filters */
832 	DECLARE_HASHTABLE(mac_filter_hash, 8);
833 	bool has_vlan_filter;
834 
835 	/* VSI stats */
836 	struct rtnl_link_stats64 net_stats;
837 	struct rtnl_link_stats64 net_stats_offsets;
838 	struct i40e_eth_stats eth_stats;
839 	struct i40e_eth_stats eth_stats_offsets;
840 	u64 tx_restart;
841 	u64 tx_busy;
842 	u64 tx_linearize;
843 	u64 tx_force_wb;
844 	u64 tx_stopped;
845 	u64 rx_buf_failed;
846 	u64 rx_page_failed;
847 	u64 rx_page_reuse;
848 	u64 rx_page_alloc;
849 	u64 rx_page_waive;
850 	u64 rx_page_busy;
851 
852 	/* These are containers of ring pointers, allocated at run-time */
853 	struct i40e_ring **rx_rings;
854 	struct i40e_ring **tx_rings;
855 	struct i40e_ring **xdp_rings; /* XDP Tx rings */
856 
857 	u32  active_filters;
858 	u32  promisc_threshold;
859 
860 	u16 work_limit;
861 	u16 int_rate_limit;	/* value in usecs */
862 
863 	u16 rss_table_size;	/* HW RSS table size */
864 	u16 rss_size;		/* Allocated RSS queues */
865 	u8  *rss_hkey_user;	/* User configured hash keys */
866 	u8  *rss_lut_user;	/* User configured lookup table entries */
867 
868 
869 	u16 max_frame;
870 	u16 rx_buf_len;
871 
872 	struct bpf_prog *xdp_prog;
873 
874 	/* List of q_vectors allocated to this VSI */
875 	struct i40e_q_vector **q_vectors;
876 	int num_q_vectors;
877 	int base_vector;
878 	bool irqs_ready;
879 
880 	u16 seid;		/* HW index of this VSI (absolute index) */
881 	u16 id;			/* VSI number */
882 	u16 uplink_seid;
883 
884 	u16 base_queue;		/* vsi's first queue in hw array */
885 	u16 alloc_queue_pairs;	/* Allocated Tx/Rx queues */
886 	u16 req_queue_pairs;	/* User requested queue pairs */
887 	u16 num_queue_pairs;	/* Used tx and rx pairs */
888 	u16 num_tx_desc;
889 	u16 num_rx_desc;
890 	enum i40e_vsi_type type;  /* VSI type, e.g., LAN, FCoE, etc */
891 	s16 vf_id;		/* Virtual function ID for SRIOV VSIs */
892 
893 	struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
894 	struct i40e_tc_configuration tc_config;
895 	struct i40e_aqc_vsi_properties_data info;
896 
897 	/* VSI BW limit (absolute across all TCs) */
898 	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */
899 	u8  bw_max_quanta;	/* Max Quanta when BW limit is enabled */
900 
901 	/* Relative TC credits across VSIs */
902 	u8  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
903 	/* TC BW limit credits within VSI */
904 	u16  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
905 	/* TC BW limit max quanta within VSI */
906 	u8  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
907 
908 	struct i40e_pf *back;	/* Backreference to associated PF */
909 	u16 idx;		/* index in pf->vsi[] */
910 	u16 veb_idx;		/* index of VEB parent */
911 	struct kobject *kobj;	/* sysfs object */
912 	bool current_isup;	/* Sync 'link up' logging */
913 	enum i40e_aq_link_speed current_speed;	/* Sync link speed logging */
914 
915 	/* channel specific fields */
916 	u16 cnt_q_avail;	/* num of queues available for channel usage */
917 	u16 orig_rss_size;
918 	u16 current_rss_size;
919 	bool reconfig_rss;
920 
921 	u16 next_base_queue;	/* next queue to be used for channel setup */
922 
923 	struct list_head ch_list;
924 	u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
925 
926 	/* macvlan fields */
927 #define I40E_MAX_MACVLANS		128 /* Max HW vectors - 1 on FVL */
928 #define I40E_MIN_MACVLAN_VECTORS	2   /* Min vectors to enable macvlans */
929 	DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
930 	struct list_head macvlan_list;
931 	int macvlan_cnt;
932 
933 	void *priv;	/* client driver data reference. */
934 
935 	/* VSI specific handlers */
936 	irqreturn_t (*irq_handler)(int irq, void *data);
937 
938 	unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
939 } ____cacheline_internodealigned_in_smp;
940 
941 struct i40e_netdev_priv {
942 	struct i40e_vsi *vsi;
943 };
944 
945 extern struct ida i40e_client_ida;
946 
947 /* struct that defines an interrupt vector */
948 struct i40e_q_vector {
949 	struct i40e_vsi *vsi;
950 
951 	u16 v_idx;		/* index in the vsi->q_vector array. */
952 	u16 reg_idx;		/* register index of the interrupt */
953 
954 	struct napi_struct napi;
955 
956 	struct i40e_ring_container rx;
957 	struct i40e_ring_container tx;
958 
959 	u8 itr_countdown;	/* when 0 should adjust adaptive ITR */
960 	u8 num_ringpairs;	/* total number of ring pairs in vector */
961 
962 	cpumask_t affinity_mask;
963 	struct irq_affinity_notify affinity_notify;
964 
965 	struct rcu_head rcu;	/* to avoid race with update stats on free */
966 	char name[I40E_INT_NAME_STR_LEN];
967 	bool arm_wb_state;
968 	bool in_busy_poll;
969 	int irq_num;		/* IRQ assigned to this q_vector */
970 } ____cacheline_internodealigned_in_smp;
971 
972 /* lan device */
973 struct i40e_device {
974 	struct list_head list;
975 	struct i40e_pf *pf;
976 };
977 
978 /**
979  * i40e_nvm_version_str - format the NVM version strings
980  * @hw: ptr to the hardware info
981  **/
982 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
983 {
984 	static char buf[32];
985 	u32 full_ver;
986 
987 	full_ver = hw->nvm.oem_ver;
988 
989 	if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
990 		u8 gen, snap;
991 		u16 release;
992 
993 		gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
994 		snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
995 			I40E_OEM_SNAP_SHIFT);
996 		release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
997 
998 		snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
999 	} else {
1000 		u8 ver, patch;
1001 		u16 build;
1002 
1003 		ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1004 		build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1005 			 I40E_OEM_VER_BUILD_MASK);
1006 		patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1007 
1008 		snprintf(buf, sizeof(buf),
1009 			 "%x.%02x 0x%x %d.%d.%d",
1010 			 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1011 				I40E_NVM_VERSION_HI_SHIFT,
1012 			 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1013 				I40E_NVM_VERSION_LO_SHIFT,
1014 			 hw->nvm.eetrack, ver, build, patch);
1015 	}
1016 
1017 	return buf;
1018 }
1019 
1020 /**
1021  * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1022  * @netdev: the corresponding netdev
1023  *
1024  * Return the PF struct for the given netdev
1025  **/
1026 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1027 {
1028 	struct i40e_netdev_priv *np = netdev_priv(netdev);
1029 	struct i40e_vsi *vsi = np->vsi;
1030 
1031 	return vsi->back;
1032 }
1033 
1034 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1035 				irqreturn_t (*irq_handler)(int, void *))
1036 {
1037 	vsi->irq_handler = irq_handler;
1038 }
1039 
1040 /**
1041  * i40e_get_fd_cnt_all - get the total FD filter space available
1042  * @pf: pointer to the PF struct
1043  **/
1044 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1045 {
1046 	return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1047 }
1048 
1049 /**
1050  * i40e_read_fd_input_set - reads value of flow director input set register
1051  * @pf: pointer to the PF struct
1052  * @addr: register addr
1053  *
1054  * This function reads value of flow director input set register
1055  * specified by 'addr' (which is specific to flow-type)
1056  **/
1057 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1058 {
1059 	u64 val;
1060 
1061 	val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1062 	val <<= 32;
1063 	val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1064 
1065 	return val;
1066 }
1067 
1068 /**
1069  * i40e_write_fd_input_set - writes value into flow director input set register
1070  * @pf: pointer to the PF struct
1071  * @addr: register addr
1072  * @val: value to be written
1073  *
1074  * This function writes specified value to the register specified by 'addr'.
1075  * This register is input set register based on flow-type.
1076  **/
1077 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1078 					   u16 addr, u64 val)
1079 {
1080 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1081 			  (u32)(val >> 32));
1082 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1083 			  (u32)(val & 0xFFFFFFFFULL));
1084 }
1085 
1086 /**
1087  * i40e_get_pf_count - get PCI PF count.
1088  * @hw: pointer to a hw.
1089  *
1090  * Reports the function number of the highest PCI physical
1091  * function plus 1 as it is loaded from the NVM.
1092  *
1093  * Return: PCI PF count.
1094  **/
1095 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1096 {
1097 	return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1098 			 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1099 }
1100 
1101 /* needed by i40e_ethtool.c */
1102 int i40e_up(struct i40e_vsi *vsi);
1103 void i40e_down(struct i40e_vsi *vsi);
1104 extern const char i40e_driver_name[];
1105 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1106 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1107 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1108 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1109 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1110 		       u16 rss_table_size, u16 rss_size);
1111 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1112 /**
1113  * i40e_find_vsi_by_type - Find and return Flow Director VSI
1114  * @pf: PF to search for VSI
1115  * @type: Value indicating type of VSI we are looking for
1116  **/
1117 static inline struct i40e_vsi *
1118 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1119 {
1120 	int i;
1121 
1122 	for (i = 0; i < pf->num_alloc_vsi; i++) {
1123 		struct i40e_vsi *vsi = pf->vsi[i];
1124 
1125 		if (vsi && vsi->type == type)
1126 			return vsi;
1127 	}
1128 
1129 	return NULL;
1130 }
1131 void i40e_update_stats(struct i40e_vsi *vsi);
1132 void i40e_update_veb_stats(struct i40e_veb *veb);
1133 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1134 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1135 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1136 				    bool printconfig);
1137 
1138 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1139 		      struct i40e_fdir_filter *input, bool add);
1140 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1141 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1142 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1143 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1144 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1145 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1146 void i40e_set_ethtool_ops(struct net_device *netdev);
1147 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1148 					const u8 *macaddr, s16 vlan);
1149 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1150 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1151 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1152 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1153 				u16 uplink, u32 param1);
1154 int i40e_vsi_release(struct i40e_vsi *vsi);
1155 void i40e_service_event_schedule(struct i40e_pf *pf);
1156 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1157 				  u8 *msg, u16 len);
1158 
1159 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1160 			   bool enable);
1161 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1162 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1163 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1164 void i40e_vsi_stop_rings_no_wait(struct  i40e_vsi *vsi);
1165 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1166 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1167 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1168 				u16 downlink_seid, u8 enabled_tc);
1169 void i40e_veb_release(struct i40e_veb *veb);
1170 
1171 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1172 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1173 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1174 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1175 void i40e_pf_reset_stats(struct i40e_pf *pf);
1176 #ifdef CONFIG_DEBUG_FS
1177 void i40e_dbg_pf_init(struct i40e_pf *pf);
1178 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1179 void i40e_dbg_init(void);
1180 void i40e_dbg_exit(void);
1181 #else
1182 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1183 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1184 static inline void i40e_dbg_init(void) {}
1185 static inline void i40e_dbg_exit(void) {}
1186 #endif /* CONFIG_DEBUG_FS*/
1187 /* needed by client drivers */
1188 int i40e_lan_add_device(struct i40e_pf *pf);
1189 int i40e_lan_del_device(struct i40e_pf *pf);
1190 void i40e_client_subtask(struct i40e_pf *pf);
1191 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1192 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1193 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1194 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1195 void i40e_client_update_msix_info(struct i40e_pf *pf);
1196 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1197 /**
1198  * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1199  * @vsi: pointer to a vsi
1200  * @vector: enable a particular Hw Interrupt vector, without base_vector
1201  **/
1202 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1203 {
1204 	struct i40e_pf *pf = vsi->back;
1205 	struct i40e_hw *hw = &pf->hw;
1206 	u32 val;
1207 
1208 	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1209 	      I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1210 	      (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1211 	wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1212 	/* skip the flush */
1213 }
1214 
1215 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1216 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1217 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1218 int i40e_open(struct net_device *netdev);
1219 int i40e_close(struct net_device *netdev);
1220 int i40e_vsi_open(struct i40e_vsi *vsi);
1221 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1222 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1223 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1224 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1225 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1226 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1227 					    const u8 *macaddr);
1228 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1229 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1230 int i40e_count_filters(struct i40e_vsi *vsi);
1231 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1232 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1233 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1234 {
1235 	return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1236 }
1237 
1238 #ifdef CONFIG_I40E_DCB
1239 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1240 			   struct i40e_dcbx_config *old_cfg,
1241 			   struct i40e_dcbx_config *new_cfg);
1242 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1243 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1244 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1245 			    struct i40e_dcbx_config *old_cfg,
1246 			    struct i40e_dcbx_config *new_cfg);
1247 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1248 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1249 #endif /* CONFIG_I40E_DCB */
1250 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1251 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1252 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1253 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1254 void i40e_ptp_set_increment(struct i40e_pf *pf);
1255 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1256 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1257 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1258 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1259 void i40e_ptp_init(struct i40e_pf *pf);
1260 void i40e_ptp_stop(struct i40e_pf *pf);
1261 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1262 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1263 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1264 int i40e_get_partition_bw_setting(struct i40e_pf *pf);
1265 int i40e_set_partition_bw_setting(struct i40e_pf *pf);
1266 int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1267 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1268 
1269 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1270 
1271 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1272 {
1273 	return !!READ_ONCE(vsi->xdp_prog);
1274 }
1275 
1276 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1277 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1278 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1279 			      struct i40e_cloud_filter *filter,
1280 			      bool add);
1281 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1282 				      struct i40e_cloud_filter *filter,
1283 				      bool add);
1284 
1285 /**
1286  * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1287  * @pf: pointer to a pf.
1288  *
1289  * Check and return value of flag I40E_FLAG_TC_MQPRIO.
1290  *
1291  * Return: I40E_FLAG_TC_MQPRIO set state.
1292  **/
1293 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1294 {
1295 	return pf->flags & I40E_FLAG_TC_MQPRIO;
1296 }
1297 
1298 /**
1299  * i40e_hw_to_pf - get pf pointer from the hardware structure
1300  * @hw: pointer to the device HW structure
1301  **/
1302 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw)
1303 {
1304 	return container_of(hw, struct i40e_pf, hw);
1305 }
1306 
1307 struct device *i40e_hw_to_dev(struct i40e_hw *hw);
1308 
1309 #endif /* _I40E_H_ */
1310