1 /* Intel Ethernet Switch Host Interface Driver 2 * Copyright(c) 2013 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19 */ 20 21 #include "fm10k_pf.h" 22 #include "fm10k_vf.h" 23 24 /** 25 * fm10k_reset_hw_pf - PF hardware reset 26 * @hw: pointer to hardware structure 27 * 28 * This function should return the hardware to a state similar to the 29 * one it is in after being powered on. 30 **/ 31 static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) 32 { 33 s32 err; 34 u32 reg; 35 u16 i; 36 37 /* Disable interrupts */ 38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); 39 40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ 41 fm10k_write_reg(hw, FM10K_ITR2(0), 0); 42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 43 44 /* We assume here Tx and Rx queue 0 are owned by the PF */ 45 46 /* Shut off VF access to their queues forcing them to queue 0 */ 47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { 48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 50 } 51 52 /* shut down all rings */ 53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); 54 if (err) 55 return err; 56 57 /* Verify that DMA is no longer active */ 58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); 59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) 60 return FM10K_ERR_DMA_PENDING; 61 62 /* verify the switch is ready for reset */ 63 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 64 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY)) 65 goto out; 66 67 /* Inititate data path reset */ 68 reg |= FM10K_DMA_CTRL_DATAPATH_RESET; 69 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); 70 71 /* Flush write and allow 100us for reset to complete */ 72 fm10k_write_flush(hw); 73 udelay(FM10K_RESET_TIMEOUT); 74 75 /* Verify we made it out of reset */ 76 reg = fm10k_read_reg(hw, FM10K_IP); 77 if (!(reg & FM10K_IP_NOTINRESET)) 78 err = FM10K_ERR_RESET_FAILED; 79 80 out: 81 return err; 82 } 83 84 /** 85 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support 86 * @hw: pointer to hardware structure 87 * 88 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. 89 **/ 90 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) 91 { 92 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); 93 94 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); 95 } 96 97 /** 98 * fm10k_init_hw_pf - PF hardware initialization 99 * @hw: pointer to hardware structure 100 * 101 **/ 102 static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) 103 { 104 u32 dma_ctrl, txqctl; 105 u16 i; 106 107 /* Establish default VSI as valid */ 108 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); 109 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), 110 FM10K_DGLORTMAP_ANY); 111 112 /* Invalidate all other GLORT entries */ 113 for (i = 1; i < FM10K_DGLORT_COUNT; i++) 114 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); 115 116 /* reset ITR2(0) to point to itself */ 117 fm10k_write_reg(hw, FM10K_ITR2(0), 0); 118 119 /* reset VF ITR2(0) to point to 0 avoid PF registers */ 120 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); 121 122 /* loop through all PF ITR2 registers pointing them to the previous */ 123 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) 124 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 125 126 /* Enable interrupt moderator if not already enabled */ 127 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 128 129 /* compute the default txqctl configuration */ 130 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | 131 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); 132 133 for (i = 0; i < FM10K_MAX_QUEUES; i++) { 134 /* configure rings for 256 Queue / 32 Descriptor cache mode */ 135 fm10k_write_reg(hw, FM10K_TQDLOC(i), 136 (i * FM10K_TQDLOC_BASE_32_DESC) | 137 FM10K_TQDLOC_SIZE_32_DESC); 138 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 139 140 /* configure rings to provide TPH processing hints */ 141 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), 142 FM10K_TPH_TXCTRL_DESC_TPHEN | 143 FM10K_TPH_TXCTRL_DESC_RROEN | 144 FM10K_TPH_TXCTRL_DESC_WROEN | 145 FM10K_TPH_TXCTRL_DATA_RROEN); 146 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), 147 FM10K_TPH_RXCTRL_DESC_TPHEN | 148 FM10K_TPH_RXCTRL_DESC_RROEN | 149 FM10K_TPH_RXCTRL_DATA_WROEN | 150 FM10K_TPH_RXCTRL_HDR_WROEN); 151 } 152 153 /* set max hold interval to align with 1.024 usec in all modes and 154 * store ITR scale 155 */ 156 switch (hw->bus.speed) { 157 case fm10k_bus_speed_2500: 158 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; 159 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1; 160 break; 161 case fm10k_bus_speed_5000: 162 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; 163 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2; 164 break; 165 case fm10k_bus_speed_8000: 166 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; 167 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; 168 break; 169 default: 170 dma_ctrl = 0; 171 /* just in case, assume Gen3 ITR scale */ 172 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; 173 break; 174 } 175 176 /* Configure TSO flags */ 177 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); 178 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); 179 180 /* Enable DMA engine 181 * Set Rx Descriptor size to 32 182 * Set Minimum MSS to 64 183 * Set Maximum number of Rx queues to 256 / 32 Descriptor 184 */ 185 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | 186 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | 187 FM10K_DMA_CTRL_32_DESC; 188 189 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); 190 191 /* record maximum queue count, we limit ourselves to 128 */ 192 hw->mac.max_queues = FM10K_MAX_QUEUES_PF; 193 194 /* We support either 64 VFs or 7 VFs depending on if we have ARI */ 195 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; 196 197 return 0; 198 } 199 200 /** 201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table 202 * @hw: pointer to hardware structure 203 * @vid: VLAN ID to add to table 204 * @vsi: Index indicating VF ID or PF ID in table 205 * @set: Indicates if this is a set or clear operation 206 * 207 * This function adds or removes the corresponding VLAN ID from the VLAN 208 * filter table for the corresponding function. In addition to the 209 * standard set/clear that supports one bit a multi-bit write is 210 * supported to set 64 bits at a time. 211 **/ 212 static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) 213 { 214 u32 vlan_table, reg, mask, bit, len; 215 216 /* verify the VSI index is valid */ 217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX) 218 return FM10K_ERR_PARAM; 219 220 /* VLAN multi-bit write: 221 * The multi-bit write has several parts to it. 222 * 3 2 1 0 223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 225 * | RSVD0 | Length |C|RSVD0| VLAN ID | 226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 227 * 228 * VLAN ID: Vlan Starting value 229 * RSVD0: Reserved section, must be 0 230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) 231 * Length: Number of times to repeat the bit being set 232 */ 233 len = vid >> 16; 234 vid = (vid << 17) >> 17; 235 236 /* verify the reserved 0 fields are 0 */ 237 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) 238 return FM10K_ERR_PARAM; 239 240 /* Loop through the table updating all required VLANs */ 241 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; 242 len < FM10K_VLAN_TABLE_VID_MAX; 243 len -= 32 - bit, reg++, bit = 0) { 244 /* record the initial state of the register */ 245 vlan_table = fm10k_read_reg(hw, reg); 246 247 /* truncate mask if we are at the start or end of the run */ 248 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; 249 250 /* make necessary modifications to the register */ 251 mask &= set ? ~vlan_table : vlan_table; 252 if (mask) 253 fm10k_write_reg(hw, reg, vlan_table ^ mask); 254 } 255 256 return 0; 257 } 258 259 /** 260 * fm10k_read_mac_addr_pf - Read device MAC address 261 * @hw: pointer to the HW structure 262 * 263 * Reads the device MAC address from the SM_AREA and stores the value. 264 **/ 265 static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) 266 { 267 u8 perm_addr[ETH_ALEN]; 268 u32 serial_num; 269 270 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); 271 272 /* last byte should be all 1's */ 273 if ((~serial_num) << 24) 274 return FM10K_ERR_INVALID_MAC_ADDR; 275 276 perm_addr[0] = (u8)(serial_num >> 24); 277 perm_addr[1] = (u8)(serial_num >> 16); 278 perm_addr[2] = (u8)(serial_num >> 8); 279 280 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); 281 282 /* first byte should be all 1's */ 283 if ((~serial_num) >> 24) 284 return FM10K_ERR_INVALID_MAC_ADDR; 285 286 perm_addr[3] = (u8)(serial_num >> 16); 287 perm_addr[4] = (u8)(serial_num >> 8); 288 perm_addr[5] = (u8)(serial_num); 289 290 ether_addr_copy(hw->mac.perm_addr, perm_addr); 291 ether_addr_copy(hw->mac.addr, perm_addr); 292 293 return 0; 294 } 295 296 /** 297 * fm10k_glort_valid_pf - Validate that the provided glort is valid 298 * @hw: pointer to the HW structure 299 * @glort: base glort to be validated 300 * 301 * This function will return an error if the provided glort is invalid 302 **/ 303 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) 304 { 305 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; 306 307 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); 308 } 309 310 /** 311 * fm10k_update_xc_addr_pf - Update device addresses 312 * @hw: pointer to the HW structure 313 * @glort: base resource tag for this request 314 * @mac: MAC address to add/remove from table 315 * @vid: VLAN ID to add/remove from table 316 * @add: Indicates if this is an add or remove operation 317 * @flags: flags field to indicate add and secure 318 * 319 * This function generates a message to the Switch API requesting 320 * that the given logical port add/remove the given L2 MAC/VLAN address. 321 **/ 322 static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, 323 const u8 *mac, u16 vid, bool add, u8 flags) 324 { 325 struct fm10k_mbx_info *mbx = &hw->mbx; 326 struct fm10k_mac_update mac_update; 327 u32 msg[5]; 328 329 /* clear set bit from VLAN ID */ 330 vid &= ~FM10K_VLAN_CLEAR; 331 332 /* if glort or vlan are not valid return error */ 333 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) 334 return FM10K_ERR_PARAM; 335 336 /* record fields */ 337 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | 338 ((u32)mac[3] << 16) | 339 ((u32)mac[4] << 8) | 340 ((u32)mac[5])); 341 mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) | 342 ((u16)mac[1])); 343 mac_update.vlan = cpu_to_le16(vid); 344 mac_update.glort = cpu_to_le16(glort); 345 mac_update.action = add ? 0 : 1; 346 mac_update.flags = flags; 347 348 /* populate mac_update fields */ 349 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); 350 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, 351 &mac_update, sizeof(mac_update)); 352 353 /* load onto outgoing mailbox */ 354 return mbx->ops.enqueue_tx(hw, mbx, msg); 355 } 356 357 /** 358 * fm10k_update_uc_addr_pf - Update device unicast addresses 359 * @hw: pointer to the HW structure 360 * @glort: base resource tag for this request 361 * @mac: MAC address to add/remove from table 362 * @vid: VLAN ID to add/remove from table 363 * @add: Indicates if this is an add or remove operation 364 * @flags: flags field to indicate add and secure 365 * 366 * This function is used to add or remove unicast addresses for 367 * the PF. 368 **/ 369 static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, 370 const u8 *mac, u16 vid, bool add, u8 flags) 371 { 372 /* verify MAC address is valid */ 373 if (!is_valid_ether_addr(mac)) 374 return FM10K_ERR_PARAM; 375 376 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); 377 } 378 379 /** 380 * fm10k_update_mc_addr_pf - Update device multicast addresses 381 * @hw: pointer to the HW structure 382 * @glort: base resource tag for this request 383 * @mac: MAC address to add/remove from table 384 * @vid: VLAN ID to add/remove from table 385 * @add: Indicates if this is an add or remove operation 386 * 387 * This function is used to add or remove multicast MAC addresses for 388 * the PF. 389 **/ 390 static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, 391 const u8 *mac, u16 vid, bool add) 392 { 393 /* verify multicast address is valid */ 394 if (!is_multicast_ether_addr(mac)) 395 return FM10K_ERR_PARAM; 396 397 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); 398 } 399 400 /** 401 * fm10k_update_xcast_mode_pf - Request update of multicast mode 402 * @hw: pointer to hardware structure 403 * @glort: base resource tag for this request 404 * @mode: integer value indicating mode being requested 405 * 406 * This function will attempt to request a higher mode for the port 407 * so that it can enable either multicast, multicast promiscuous, or 408 * promiscuous mode of operation. 409 **/ 410 static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) 411 { 412 struct fm10k_mbx_info *mbx = &hw->mbx; 413 u32 msg[3], xcast_mode; 414 415 if (mode > FM10K_XCAST_MODE_NONE) 416 return FM10K_ERR_PARAM; 417 /* if glort is not valid return error */ 418 if (!fm10k_glort_valid_pf(hw, glort)) 419 return FM10K_ERR_PARAM; 420 421 /* write xcast mode as a single u32 value, 422 * lower 16 bits: glort 423 * upper 16 bits: mode 424 */ 425 xcast_mode = ((u32)mode << 16) | glort; 426 427 /* generate message requesting to change xcast mode */ 428 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); 429 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); 430 431 /* load onto outgoing mailbox */ 432 return mbx->ops.enqueue_tx(hw, mbx, msg); 433 } 434 435 /** 436 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list 437 * @hw: pointer to hardware structure 438 * 439 * This function walks through the MSI-X vector table to determine the 440 * number of active interrupts and based on that information updates the 441 * interrupt moderator linked list. 442 **/ 443 static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) 444 { 445 u32 i; 446 447 /* Disable interrupt moderator */ 448 fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 449 450 /* loop through PF from last to first looking enabled vectors */ 451 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { 452 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 453 break; 454 } 455 456 /* always reset VFITR2[0] to point to last enabled PF vector */ 457 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); 458 459 /* reset ITR2[0] to point to last enabled PF vector */ 460 if (!hw->iov.num_vfs) 461 fm10k_write_reg(hw, FM10K_ITR2(0), i); 462 463 /* Enable interrupt moderator */ 464 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 465 } 466 467 /** 468 * fm10k_update_lport_state_pf - Notify the switch of a change in port state 469 * @hw: pointer to the HW structure 470 * @glort: base resource tag for this request 471 * @count: number of logical ports being updated 472 * @enable: boolean value indicating enable or disable 473 * 474 * This function is used to add/remove a logical port from the switch. 475 **/ 476 static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, 477 u16 count, bool enable) 478 { 479 struct fm10k_mbx_info *mbx = &hw->mbx; 480 u32 msg[3], lport_msg; 481 482 /* do nothing if we are being asked to create or destroy 0 ports */ 483 if (!count) 484 return 0; 485 486 /* if glort is not valid return error */ 487 if (!fm10k_glort_valid_pf(hw, glort)) 488 return FM10K_ERR_PARAM; 489 490 /* construct the lport message from the 2 pieces of data we have */ 491 lport_msg = ((u32)count << 16) | glort; 492 493 /* generate lport create/delete message */ 494 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : 495 FM10K_PF_MSG_ID_LPORT_DELETE); 496 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); 497 498 /* load onto outgoing mailbox */ 499 return mbx->ops.enqueue_tx(hw, mbx, msg); 500 } 501 502 /** 503 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues 504 * @hw: pointer to hardware structure 505 * @dglort: pointer to dglort configuration structure 506 * 507 * Reads the configuration structure contained in dglort_cfg and uses 508 * that information to then populate a DGLORTMAP/DEC entry and the queues 509 * to which it has been assigned. 510 **/ 511 static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, 512 struct fm10k_dglort_cfg *dglort) 513 { 514 u16 glort, queue_count, vsi_count, pc_count; 515 u16 vsi, queue, pc, q_idx; 516 u32 txqctl, dglortdec, dglortmap; 517 518 /* verify the dglort pointer */ 519 if (!dglort) 520 return FM10K_ERR_PARAM; 521 522 /* verify the dglort values */ 523 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || 524 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || 525 (dglort->queue_l > 8) || (dglort->queue_b >= 256)) 526 return FM10K_ERR_PARAM; 527 528 /* determine count of VSIs and queues */ 529 queue_count = 1 << (dglort->rss_l + dglort->pc_l); 530 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l); 531 glort = dglort->glort; 532 q_idx = dglort->queue_b; 533 534 /* configure SGLORT for queues */ 535 for (vsi = 0; vsi < vsi_count; vsi++, glort++) { 536 for (queue = 0; queue < queue_count; queue++, q_idx++) { 537 if (q_idx >= FM10K_MAX_QUEUES) 538 break; 539 540 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); 541 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); 542 } 543 } 544 545 /* determine count of PCs and queues */ 546 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l); 547 pc_count = 1 << dglort->pc_l; 548 549 /* configure PC for Tx queues */ 550 for (pc = 0; pc < pc_count; pc++) { 551 q_idx = pc + dglort->queue_b; 552 for (queue = 0; queue < queue_count; queue++) { 553 if (q_idx >= FM10K_MAX_QUEUES) 554 break; 555 556 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); 557 txqctl &= ~FM10K_TXQCTL_PC_MASK; 558 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; 559 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); 560 561 q_idx += pc_count; 562 } 563 } 564 565 /* configure DGLORTDEC */ 566 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | 567 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | 568 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | 569 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | 570 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | 571 ((u32)(dglort->queue_l)); 572 if (dglort->inner_rss) 573 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; 574 575 /* configure DGLORTMAP */ 576 dglortmap = (dglort->idx == fm10k_dglort_default) ? 577 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; 578 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; 579 dglortmap |= dglort->glort; 580 581 /* write values to hardware */ 582 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); 583 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); 584 585 return 0; 586 } 587 588 u16 fm10k_queues_per_pool(struct fm10k_hw *hw) 589 { 590 u16 num_pools = hw->iov.num_pools; 591 592 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? 593 8 : FM10K_MAX_QUEUES_POOL; 594 } 595 596 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) 597 { 598 u16 num_vfs = hw->iov.num_vfs; 599 u16 vf_q_idx = FM10K_MAX_QUEUES; 600 601 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); 602 603 return vf_q_idx; 604 } 605 606 static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) 607 { 608 u16 num_pools = hw->iov.num_pools; 609 610 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : 611 FM10K_MAX_VECTORS_POOL; 612 } 613 614 static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) 615 { 616 u16 vf_v_idx = FM10K_MAX_VECTORS_PF; 617 618 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; 619 620 return vf_v_idx; 621 } 622 623 /** 624 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization 625 * @hw: pointer to the HW structure 626 * @num_vfs: number of VFs to be allocated 627 * @num_pools: number of virtualization pools to be allocated 628 * 629 * Allocates queues and traffic classes to virtualization entities to prepare 630 * the PF for SR-IOV and VMDq 631 **/ 632 static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, 633 u16 num_pools) 634 { 635 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; 636 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; 637 int i, j; 638 639 /* hardware only supports up to 64 pools */ 640 if (num_pools > 64) 641 return FM10K_ERR_PARAM; 642 643 /* the number of VFs cannot exceed the number of pools */ 644 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) 645 return FM10K_ERR_PARAM; 646 647 /* record number of virtualization entities */ 648 hw->iov.num_vfs = num_vfs; 649 hw->iov.num_pools = num_pools; 650 651 /* determine qmap offsets and counts */ 652 qmap_stride = (num_vfs > 8) ? 32 : 256; 653 qpp = fm10k_queues_per_pool(hw); 654 vpp = fm10k_vectors_per_pool(hw); 655 656 /* calculate starting index for queues */ 657 vf_q_idx = fm10k_vf_queue_index(hw, 0); 658 qmap_idx = 0; 659 660 /* establish TCs with -1 credits and no quanta to prevent transmit */ 661 for (i = 0; i < num_vfs; i++) { 662 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); 663 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); 664 fm10k_write_reg(hw, FM10K_TC_CREDIT(i), 665 FM10K_TC_CREDIT_CREDIT_MASK); 666 } 667 668 /* zero out all mbmem registers */ 669 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) 670 fm10k_write_reg(hw, FM10K_MBMEM(i), 0); 671 672 /* clear event notification of VF FLR */ 673 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); 674 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); 675 676 /* loop through unallocated rings assigning them back to PF */ 677 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { 678 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 679 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | 680 FM10K_TXQCTL_UNLIMITED_BW | vid); 681 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); 682 } 683 684 /* PF should have already updated VFITR2[0] */ 685 686 /* update all ITR registers to flow to VFITR2[0] */ 687 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { 688 if (!(i & (vpp - 1))) 689 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); 690 else 691 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 692 } 693 694 /* update PF ITR2[0] to reference the last vector */ 695 fm10k_write_reg(hw, FM10K_ITR2(0), 696 fm10k_vf_vector_index(hw, num_vfs - 1)); 697 698 /* loop through rings populating rings and TCs */ 699 for (i = 0; i < num_vfs; i++) { 700 /* record index for VF queue 0 for use in end of loop */ 701 vf_q_idx0 = vf_q_idx; 702 703 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { 704 /* assign VF and locked TC to queues */ 705 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 706 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), 707 (i << FM10K_TXQCTL_TC_SHIFT) | i | 708 FM10K_TXQCTL_VF | vid); 709 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), 710 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 711 FM10K_RXDCTL_DROP_ON_EMPTY); 712 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), 713 FM10K_RXQCTL_VF | 714 (i << FM10K_RXQCTL_VF_SHIFT)); 715 716 /* map queue pair to VF */ 717 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 718 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); 719 } 720 721 /* repeat the first ring for all of the remaining VF rings */ 722 for (; j < qmap_stride; j++, qmap_idx++) { 723 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); 724 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); 725 } 726 } 727 728 /* loop through remaining indexes assigning all to queue 0 */ 729 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { 730 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 731 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); 732 qmap_idx++; 733 } 734 735 return 0; 736 } 737 738 /** 739 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF 740 * @hw: pointer to the HW structure 741 * @vf_idx: index of VF receiving GLORT 742 * @rate: Rate indicated in Mb/s 743 * 744 * Configured the TC for a given VF to allow only up to a given number 745 * of Mb/s of outgoing Tx throughput. 746 **/ 747 static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) 748 { 749 /* configure defaults */ 750 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; 751 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; 752 753 /* verify vf is in range */ 754 if (vf_idx >= hw->iov.num_vfs) 755 return FM10K_ERR_PARAM; 756 757 /* set interval to align with 4.096 usec in all modes */ 758 switch (hw->bus.speed) { 759 case fm10k_bus_speed_2500: 760 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; 761 break; 762 case fm10k_bus_speed_5000: 763 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; 764 break; 765 default: 766 break; 767 } 768 769 if (rate) { 770 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) 771 return FM10K_ERR_PARAM; 772 773 /* The quanta is measured in Bytes per 4.096 or 8.192 usec 774 * The rate is provided in Mbits per second 775 * To tralslate from rate to quanta we need to multiply the 776 * rate by 8.192 usec and divide by 8 bits/byte. To avoid 777 * dealing with floating point we can round the values up 778 * to the nearest whole number ratio which gives us 128 / 125. 779 */ 780 tc_rate = (rate * 128) / 125; 781 782 /* try to keep the rate limiting accurate by increasing 783 * the number of credits and interval for rates less than 4Gb/s 784 */ 785 if (rate < 4000) 786 interval <<= 1; 787 else 788 tc_rate >>= 1; 789 } 790 791 /* update rate limiter with new values */ 792 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); 793 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 794 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 795 796 return 0; 797 } 798 799 /** 800 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list 801 * @hw: pointer to the HW structure 802 * @vf_idx: index of VF receiving GLORT 803 * 804 * Update the interrupt moderator linked list to include any MSI-X 805 * interrupts which the VF has enabled in the MSI-X vector table. 806 **/ 807 static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) 808 { 809 u16 vf_v_idx, vf_v_limit, i; 810 811 /* verify vf is in range */ 812 if (vf_idx >= hw->iov.num_vfs) 813 return FM10K_ERR_PARAM; 814 815 /* determine vector offset and count */ 816 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 817 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 818 819 /* search for first vector that is not masked */ 820 for (i = vf_v_limit - 1; i > vf_v_idx; i--) { 821 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 822 break; 823 } 824 825 /* reset linked list so it now includes our active vectors */ 826 if (vf_idx == (hw->iov.num_vfs - 1)) 827 fm10k_write_reg(hw, FM10K_ITR2(0), i); 828 else 829 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); 830 831 return 0; 832 } 833 834 /** 835 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF 836 * @hw: pointer to the HW structure 837 * @vf_info: pointer to VF information structure 838 * 839 * Assign a MAC address and default VLAN to a VF and notify it of the update 840 **/ 841 static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, 842 struct fm10k_vf_info *vf_info) 843 { 844 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; 845 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; 846 s32 err = 0; 847 u16 vf_idx, vf_vid; 848 849 /* verify vf is in range */ 850 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) 851 return FM10K_ERR_PARAM; 852 853 /* determine qmap offsets and counts */ 854 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 855 queues_per_pool = fm10k_queues_per_pool(hw); 856 857 /* calculate starting index for queues */ 858 vf_idx = vf_info->vf_idx; 859 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 860 qmap_idx = qmap_stride * vf_idx; 861 862 /* MAP Tx queue back to 0 temporarily, and disable it */ 863 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 864 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 865 866 /* determine correct default VLAN ID */ 867 if (vf_info->pf_vid) 868 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR; 869 else 870 vf_vid = vf_info->sw_vid; 871 872 /* generate MAC_ADDR request */ 873 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); 874 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, 875 vf_info->mac, vf_vid); 876 877 /* load onto outgoing mailbox, ignore any errors on enqueue */ 878 if (vf_info->mbx.ops.enqueue_tx) 879 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 880 881 /* verify ring has disabled before modifying base address registers */ 882 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 883 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { 884 /* limit ourselves to a 1ms timeout */ 885 if (timeout == 10) { 886 err = FM10K_ERR_DMA_PENDING; 887 goto err_out; 888 } 889 890 usleep_range(100, 200); 891 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 892 } 893 894 /* Update base address registers to contain MAC address */ 895 if (is_valid_ether_addr(vf_info->mac)) { 896 tdbal = (((u32)vf_info->mac[3]) << 24) | 897 (((u32)vf_info->mac[4]) << 16) | 898 (((u32)vf_info->mac[5]) << 8); 899 900 tdbah = (((u32)0xFF) << 24) | 901 (((u32)vf_info->mac[0]) << 16) | 902 (((u32)vf_info->mac[1]) << 8) | 903 ((u32)vf_info->mac[2]); 904 } 905 906 /* Record the base address into queue 0 */ 907 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); 908 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); 909 910 /* Provide the VF the ITR scale, using software-defined fields in TDLEN 911 * to pass the information during VF initialization. See definition of 912 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details. 913 */ 914 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale << 915 FM10K_TDLEN_ITR_SCALE_SHIFT); 916 917 err_out: 918 /* configure Queue control register */ 919 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & 920 FM10K_TXQCTL_VID_MASK; 921 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 922 FM10K_TXQCTL_VF | vf_idx; 923 924 /* assign VID */ 925 for (i = 0; i < queues_per_pool; i++) 926 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); 927 928 /* restore the queue back to VF ownership */ 929 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 930 return err; 931 } 932 933 /** 934 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF 935 * @hw: pointer to the HW structure 936 * @vf_info: pointer to VF information structure 937 * 938 * Reassign the interrupts and queues to a VF following an FLR 939 **/ 940 static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, 941 struct fm10k_vf_info *vf_info) 942 { 943 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; 944 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; 945 u16 vf_v_idx, vf_v_limit, vf_vid; 946 u8 vf_idx = vf_info->vf_idx; 947 int i; 948 949 /* verify vf is in range */ 950 if (vf_idx >= hw->iov.num_vfs) 951 return FM10K_ERR_PARAM; 952 953 /* clear event notification of VF FLR */ 954 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32)); 955 956 /* force timeout and then disconnect the mailbox */ 957 vf_info->mbx.timeout = 0; 958 if (vf_info->mbx.ops.disconnect) 959 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); 960 961 /* determine vector offset and count */ 962 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 963 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 964 965 /* determine qmap offsets and counts */ 966 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 967 queues_per_pool = fm10k_queues_per_pool(hw); 968 qmap_idx = qmap_stride * vf_idx; 969 970 /* make all the queues inaccessible to the VF */ 971 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { 972 fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 973 fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 974 } 975 976 /* calculate starting index for queues */ 977 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 978 979 /* determine correct default VLAN ID */ 980 if (vf_info->pf_vid) 981 vf_vid = vf_info->pf_vid; 982 else 983 vf_vid = vf_info->sw_vid; 984 985 /* configure Queue control register */ 986 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | 987 (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 988 FM10K_TXQCTL_VF | vf_idx; 989 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT); 990 991 /* stop further DMA and reset queue ownership back to VF */ 992 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { 993 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 994 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 995 fm10k_write_reg(hw, FM10K_RXDCTL(i), 996 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 997 FM10K_RXDCTL_DROP_ON_EMPTY); 998 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); 999 } 1000 1001 /* reset TC with -1 credits and no quanta to prevent transmit */ 1002 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); 1003 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); 1004 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), 1005 FM10K_TC_CREDIT_CREDIT_MASK); 1006 1007 /* update our first entry in the table based on previous VF */ 1008 if (!vf_idx) 1009 hw->mac.ops.update_int_moderator(hw); 1010 else 1011 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); 1012 1013 /* reset linked list so it now includes our active vectors */ 1014 if (vf_idx == (hw->iov.num_vfs - 1)) 1015 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); 1016 else 1017 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); 1018 1019 /* link remaining vectors so that next points to previous */ 1020 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) 1021 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); 1022 1023 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ 1024 for (i = FM10K_VFMBMEM_LEN; i--;) 1025 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); 1026 for (i = FM10K_VLAN_TABLE_SIZE; i--;) 1027 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); 1028 for (i = FM10K_RETA_SIZE; i--;) 1029 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); 1030 for (i = FM10K_RSSRK_SIZE; i--;) 1031 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); 1032 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); 1033 1034 /* Update base address registers to contain MAC address */ 1035 if (is_valid_ether_addr(vf_info->mac)) { 1036 tdbal = (((u32)vf_info->mac[3]) << 24) | 1037 (((u32)vf_info->mac[4]) << 16) | 1038 (((u32)vf_info->mac[5]) << 8); 1039 tdbah = (((u32)0xFF) << 24) | 1040 (((u32)vf_info->mac[0]) << 16) | 1041 (((u32)vf_info->mac[1]) << 8) | 1042 ((u32)vf_info->mac[2]); 1043 } 1044 1045 /* map queue pairs back to VF from last to first */ 1046 for (i = queues_per_pool; i--;) { 1047 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); 1048 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); 1049 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an 1050 * explanation of how TDLEN is used. 1051 */ 1052 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i), 1053 hw->mac.itr_scale << 1054 FM10K_TDLEN_ITR_SCALE_SHIFT); 1055 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); 1056 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); 1057 } 1058 1059 /* repeat the first ring for all the remaining VF rings */ 1060 for (i = queues_per_pool; i < qmap_stride; i++) { 1061 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); 1062 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); 1063 } 1064 1065 return 0; 1066 } 1067 1068 /** 1069 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF 1070 * @hw: pointer to hardware structure 1071 * @vf_info: pointer to VF information structure 1072 * @lport_idx: Logical port offset from the hardware glort 1073 * @flags: Set of capability flags to extend port beyond basic functionality 1074 * 1075 * This function allows enabling a VF port by assigning it a GLORT and 1076 * setting the flags so that it can enable an Rx mode. 1077 **/ 1078 static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, 1079 struct fm10k_vf_info *vf_info, 1080 u16 lport_idx, u8 flags) 1081 { 1082 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; 1083 1084 /* if glort is not valid return error */ 1085 if (!fm10k_glort_valid_pf(hw, glort)) 1086 return FM10K_ERR_PARAM; 1087 1088 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; 1089 vf_info->glort = glort; 1090 1091 return 0; 1092 } 1093 1094 /** 1095 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF 1096 * @hw: pointer to hardware structure 1097 * @vf_info: pointer to VF information structure 1098 * 1099 * This function disables a VF port by stripping it of a GLORT and 1100 * setting the flags so that it cannot enable any Rx mode. 1101 **/ 1102 static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, 1103 struct fm10k_vf_info *vf_info) 1104 { 1105 u32 msg[1]; 1106 1107 /* need to disable the port if it is already enabled */ 1108 if (FM10K_VF_FLAG_ENABLED(vf_info)) { 1109 /* notify switch that this port has been disabled */ 1110 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); 1111 1112 /* generate port state response to notify VF it is not ready */ 1113 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1114 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 1115 } 1116 1117 /* clear flags and glort if it exists */ 1118 vf_info->vf_flags = 0; 1119 vf_info->glort = 0; 1120 } 1121 1122 /** 1123 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs 1124 * @hw: pointer to hardware structure 1125 * @q: stats for all queues of a VF 1126 * @vf_idx: index of VF 1127 * 1128 * This function collects queue stats for VFs. 1129 **/ 1130 static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, 1131 struct fm10k_hw_stats_q *q, 1132 u16 vf_idx) 1133 { 1134 u32 idx, qpp; 1135 1136 /* get stats for all of the queues */ 1137 qpp = fm10k_queues_per_pool(hw); 1138 idx = fm10k_vf_queue_index(hw, vf_idx); 1139 fm10k_update_hw_stats_q(hw, q, idx, qpp); 1140 } 1141 1142 static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw, 1143 struct fm10k_vf_info *vf_info, 1144 u64 timestamp) 1145 { 1146 u32 msg[4]; 1147 1148 /* generate port state response to notify VF it is not ready */ 1149 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588); 1150 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp); 1151 1152 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 1153 } 1154 1155 /** 1156 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF 1157 * @hw: Pointer to hardware structure 1158 * @results: Pointer array to message, results[0] is pointer to message 1159 * @mbx: Pointer to mailbox information structure 1160 * 1161 * This function is a default handler for MSI-X requests from the VF. The 1162 * assumption is that in this case it is acceptable to just directly 1163 * hand off the message from the VF to the underlying shared code. 1164 **/ 1165 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, 1166 struct fm10k_mbx_info *mbx) 1167 { 1168 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1169 u8 vf_idx = vf_info->vf_idx; 1170 1171 return hw->iov.ops.assign_int_moderator(hw, vf_idx); 1172 } 1173 1174 /** 1175 * fm10k_iov_select_vid - Select correct default VID 1176 * @hw: Pointer to hardware structure 1177 * @vid: VID to correct 1178 * 1179 * Will report an error if VID is out of range. For VID = 0, it will return 1180 * either the pf_vid or sw_vid depending on which one is set. 1181 */ 1182 static inline s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid) 1183 { 1184 if (!vid) 1185 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid; 1186 else if (vf_info->pf_vid && vid != vf_info->pf_vid) 1187 return FM10K_ERR_PARAM; 1188 else 1189 return vid; 1190 } 1191 1192 /** 1193 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF 1194 * @hw: Pointer to hardware structure 1195 * @results: Pointer array to message, results[0] is pointer to message 1196 * @mbx: Pointer to mailbox information structure 1197 * 1198 * This function is a default handler for MAC/VLAN requests from the VF. 1199 * The assumption is that in this case it is acceptable to just directly 1200 * hand off the message from the VF to the underlying shared code. 1201 **/ 1202 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, 1203 struct fm10k_mbx_info *mbx) 1204 { 1205 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1206 u8 mac[ETH_ALEN]; 1207 u32 *result; 1208 int err = 0; 1209 bool set; 1210 u16 vlan; 1211 u32 vid; 1212 1213 /* we shouldn't be updating rules on a disabled interface */ 1214 if (!FM10K_VF_FLAG_ENABLED(vf_info)) 1215 err = FM10K_ERR_PARAM; 1216 1217 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { 1218 result = results[FM10K_MAC_VLAN_MSG_VLAN]; 1219 1220 /* record VLAN id requested */ 1221 err = fm10k_tlv_attr_get_u32(result, &vid); 1222 if (err) 1223 return err; 1224 1225 /* verify upper 16 bits are zero */ 1226 if (vid >> 16) 1227 return FM10K_ERR_PARAM; 1228 1229 set = !(vid & FM10K_VLAN_CLEAR); 1230 vid &= ~FM10K_VLAN_CLEAR; 1231 1232 err = fm10k_iov_select_vid(vf_info, (u16)vid); 1233 if (err < 0) 1234 return err; 1235 1236 vid = err; 1237 1238 /* update VSI info for VF in regards to VLAN table */ 1239 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set); 1240 } 1241 1242 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { 1243 result = results[FM10K_MAC_VLAN_MSG_MAC]; 1244 1245 /* record unicast MAC address requested */ 1246 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1247 if (err) 1248 return err; 1249 1250 /* block attempts to set MAC for a locked device */ 1251 if (is_valid_ether_addr(vf_info->mac) && 1252 memcmp(mac, vf_info->mac, ETH_ALEN)) 1253 return FM10K_ERR_PARAM; 1254 1255 set = !(vlan & FM10K_VLAN_CLEAR); 1256 vlan &= ~FM10K_VLAN_CLEAR; 1257 1258 err = fm10k_iov_select_vid(vf_info, vlan); 1259 if (err < 0) 1260 return err; 1261 1262 vlan = (u16)err; 1263 1264 /* notify switch of request for new unicast address */ 1265 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, 1266 mac, vlan, set, 0); 1267 } 1268 1269 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { 1270 result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; 1271 1272 /* record multicast MAC address requested */ 1273 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1274 if (err) 1275 return err; 1276 1277 /* verify that the VF is allowed to request multicast */ 1278 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) 1279 return FM10K_ERR_PARAM; 1280 1281 set = !(vlan & FM10K_VLAN_CLEAR); 1282 vlan &= ~FM10K_VLAN_CLEAR; 1283 1284 err = fm10k_iov_select_vid(vf_info, vlan); 1285 if (err < 0) 1286 return err; 1287 1288 vlan = (u16)err; 1289 1290 /* notify switch of request for new multicast address */ 1291 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, 1292 mac, vlan, set); 1293 } 1294 1295 return err; 1296 } 1297 1298 /** 1299 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode 1300 * @vf_info: VF info structure containing capability flags 1301 * @mode: Requested xcast mode 1302 * 1303 * This function outputs the mode that most closely matches the requested 1304 * mode. If not modes match it will request we disable the port 1305 **/ 1306 static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, 1307 u8 mode) 1308 { 1309 u8 vf_flags = vf_info->vf_flags; 1310 1311 /* match up mode to capabilities as best as possible */ 1312 switch (mode) { 1313 case FM10K_XCAST_MODE_PROMISC: 1314 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) 1315 return FM10K_XCAST_MODE_PROMISC; 1316 /* fallthough */ 1317 case FM10K_XCAST_MODE_ALLMULTI: 1318 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) 1319 return FM10K_XCAST_MODE_ALLMULTI; 1320 /* fallthough */ 1321 case FM10K_XCAST_MODE_MULTI: 1322 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) 1323 return FM10K_XCAST_MODE_MULTI; 1324 /* fallthough */ 1325 case FM10K_XCAST_MODE_NONE: 1326 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) 1327 return FM10K_XCAST_MODE_NONE; 1328 /* fallthough */ 1329 default: 1330 break; 1331 } 1332 1333 /* disable interface as it should not be able to request any */ 1334 return FM10K_XCAST_MODE_DISABLE; 1335 } 1336 1337 /** 1338 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests 1339 * @hw: Pointer to hardware structure 1340 * @results: Pointer array to message, results[0] is pointer to message 1341 * @mbx: Pointer to mailbox information structure 1342 * 1343 * This function is a default handler for port state requests. The port 1344 * state requests for now are basic and consist of enabling or disabling 1345 * the port. 1346 **/ 1347 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, 1348 struct fm10k_mbx_info *mbx) 1349 { 1350 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1351 u32 *result; 1352 s32 err = 0; 1353 u32 msg[2]; 1354 u8 mode = 0; 1355 1356 /* verify VF is allowed to enable even minimal mode */ 1357 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) 1358 return FM10K_ERR_PARAM; 1359 1360 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { 1361 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; 1362 1363 /* XCAST mode update requested */ 1364 err = fm10k_tlv_attr_get_u8(result, &mode); 1365 if (err) 1366 return FM10K_ERR_PARAM; 1367 1368 /* prep for possible demotion depending on capabilities */ 1369 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); 1370 1371 /* if mode is not currently enabled, enable it */ 1372 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode))) 1373 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); 1374 1375 /* swap mode back to a bit flag */ 1376 mode = FM10K_VF_FLAG_SET_MODE(mode); 1377 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { 1378 /* need to disable the port if it is already enabled */ 1379 if (FM10K_VF_FLAG_ENABLED(vf_info)) 1380 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1381 1, false); 1382 1383 /* we need to clear VF_FLAG_ENABLED flags in order to ensure 1384 * that we actually re-enable the LPORT state below. Note that 1385 * this has no impact if the VF is already disabled, as the 1386 * flags are already cleared. 1387 */ 1388 if (!err) 1389 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info); 1390 1391 /* when enabling the port we should reset the rate limiters */ 1392 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); 1393 1394 /* set mode for minimal functionality */ 1395 mode = FM10K_VF_FLAG_SET_MODE_NONE; 1396 1397 /* generate port state response to notify VF it is ready */ 1398 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1399 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); 1400 mbx->ops.enqueue_tx(hw, mbx, msg); 1401 } 1402 1403 /* if enable state toggled note the update */ 1404 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) 1405 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, 1406 !!mode); 1407 1408 /* if state change succeeded, then update our stored state */ 1409 mode |= FM10K_VF_FLAG_CAPABLE(vf_info); 1410 if (!err) 1411 vf_info->vf_flags = mode; 1412 1413 return err; 1414 } 1415 1416 /** 1417 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF 1418 * @hw: pointer to hardware structure 1419 * @stats: pointer to the stats structure to update 1420 * 1421 * This function collects and aggregates global and per queue hardware 1422 * statistics. 1423 **/ 1424 static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, 1425 struct fm10k_hw_stats *stats) 1426 { 1427 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; 1428 u32 id, id_prev; 1429 1430 /* Use Tx queue 0 as a canary to detect a reset */ 1431 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1432 1433 /* Read Global Statistics */ 1434 do { 1435 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, 1436 &stats->timeout); 1437 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); 1438 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); 1439 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); 1440 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); 1441 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, 1442 &stats->vlan_drop); 1443 loopback_drop = fm10k_read_hw_stats_32b(hw, 1444 FM10K_STATS_LOOPBACK_DROP, 1445 &stats->loopback_drop); 1446 nodesc_drop = fm10k_read_hw_stats_32b(hw, 1447 FM10K_STATS_NODESC_DROP, 1448 &stats->nodesc_drop); 1449 1450 /* if value has not changed then we have consistent data */ 1451 id_prev = id; 1452 id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1453 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); 1454 1455 /* drop non-ID bits and set VALID ID bit */ 1456 id &= FM10K_TXQCTL_ID_MASK; 1457 id |= FM10K_STAT_VALID; 1458 1459 /* Update Global Statistics */ 1460 if (stats->stats_idx == id) { 1461 stats->timeout.count += timeout; 1462 stats->ur.count += ur; 1463 stats->ca.count += ca; 1464 stats->um.count += um; 1465 stats->xec.count += xec; 1466 stats->vlan_drop.count += vlan_drop; 1467 stats->loopback_drop.count += loopback_drop; 1468 stats->nodesc_drop.count += nodesc_drop; 1469 } 1470 1471 /* Update bases and record current PF id */ 1472 fm10k_update_hw_base_32b(&stats->timeout, timeout); 1473 fm10k_update_hw_base_32b(&stats->ur, ur); 1474 fm10k_update_hw_base_32b(&stats->ca, ca); 1475 fm10k_update_hw_base_32b(&stats->um, um); 1476 fm10k_update_hw_base_32b(&stats->xec, xec); 1477 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); 1478 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); 1479 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); 1480 stats->stats_idx = id; 1481 1482 /* Update Queue Statistics */ 1483 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); 1484 } 1485 1486 /** 1487 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF 1488 * @hw: pointer to hardware structure 1489 * @stats: pointer to the stats structure to update 1490 * 1491 * This function resets the base for global and per queue hardware 1492 * statistics. 1493 **/ 1494 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, 1495 struct fm10k_hw_stats *stats) 1496 { 1497 /* Unbind Global Statistics */ 1498 fm10k_unbind_hw_stats_32b(&stats->timeout); 1499 fm10k_unbind_hw_stats_32b(&stats->ur); 1500 fm10k_unbind_hw_stats_32b(&stats->ca); 1501 fm10k_unbind_hw_stats_32b(&stats->um); 1502 fm10k_unbind_hw_stats_32b(&stats->xec); 1503 fm10k_unbind_hw_stats_32b(&stats->vlan_drop); 1504 fm10k_unbind_hw_stats_32b(&stats->loopback_drop); 1505 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); 1506 1507 /* Unbind Queue Statistics */ 1508 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); 1509 1510 /* Reinitialize bases for all stats */ 1511 fm10k_update_hw_stats_pf(hw, stats); 1512 } 1513 1514 /** 1515 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system 1516 * @hw: pointer to hardware structure 1517 * @dma_mask: 64 bit DMA mask required for platform 1518 * 1519 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order 1520 * to limit the access to memory beyond what is physically in the system. 1521 **/ 1522 static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) 1523 { 1524 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ 1525 u32 phyaddr = (u32)(dma_mask >> 32); 1526 1527 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); 1528 } 1529 1530 /** 1531 * fm10k_get_fault_pf - Record a fault in one of the interface units 1532 * @hw: pointer to hardware structure 1533 * @type: pointer to fault type register offset 1534 * @fault: pointer to memory location to record the fault 1535 * 1536 * Record the fault register contents to the fault data structure and 1537 * clear the entry from the register. 1538 * 1539 * Returns ERR_PARAM if invalid register is specified or no error is present. 1540 **/ 1541 static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, 1542 struct fm10k_fault *fault) 1543 { 1544 u32 func; 1545 1546 /* verify the fault register is in range and is aligned */ 1547 switch (type) { 1548 case FM10K_PCA_FAULT: 1549 case FM10K_THI_FAULT: 1550 case FM10K_FUM_FAULT: 1551 break; 1552 default: 1553 return FM10K_ERR_PARAM; 1554 } 1555 1556 /* only service faults that are valid */ 1557 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); 1558 if (!(func & FM10K_FAULT_FUNC_VALID)) 1559 return FM10K_ERR_PARAM; 1560 1561 /* read remaining fields */ 1562 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); 1563 fault->address <<= 32; 1564 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); 1565 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); 1566 1567 /* clear valid bit to allow for next error */ 1568 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); 1569 1570 /* Record which function triggered the error */ 1571 if (func & FM10K_FAULT_FUNC_PF) 1572 fault->func = 0; 1573 else 1574 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> 1575 FM10K_FAULT_FUNC_VF_SHIFT); 1576 1577 /* record fault type */ 1578 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; 1579 1580 return 0; 1581 } 1582 1583 /** 1584 * fm10k_request_lport_map_pf - Request LPORT map from the switch API 1585 * @hw: pointer to hardware structure 1586 * 1587 **/ 1588 static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) 1589 { 1590 struct fm10k_mbx_info *mbx = &hw->mbx; 1591 u32 msg[1]; 1592 1593 /* issue request asking for LPORT map */ 1594 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); 1595 1596 /* load onto outgoing mailbox */ 1597 return mbx->ops.enqueue_tx(hw, mbx, msg); 1598 } 1599 1600 /** 1601 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox 1602 * @hw: pointer to hardware structure 1603 * @switch_ready: pointer to boolean value that will record switch state 1604 * 1605 * This funciton will check the DMA_CTRL2 register and mailbox in order 1606 * to determine if the switch is ready for the PF to begin requesting 1607 * addresses and mapping traffic to the local interface. 1608 **/ 1609 static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) 1610 { 1611 s32 ret_val = 0; 1612 u32 dma_ctrl2; 1613 1614 /* verify the switch is ready for interaction */ 1615 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 1616 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) 1617 goto out; 1618 1619 /* retrieve generic host state info */ 1620 ret_val = fm10k_get_host_state_generic(hw, switch_ready); 1621 if (ret_val) 1622 goto out; 1623 1624 /* interface cannot receive traffic without logical ports */ 1625 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) 1626 ret_val = fm10k_request_lport_map_pf(hw); 1627 1628 out: 1629 return ret_val; 1630 } 1631 1632 /* This structure defines the attibutes to be parsed below */ 1633 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { 1634 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), 1635 FM10K_TLV_ATTR_LAST 1636 }; 1637 1638 /** 1639 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM 1640 * @hw: Pointer to hardware structure 1641 * @results: pointer array containing parsed data 1642 * @mbx: Pointer to mailbox information structure 1643 * 1644 * This handler configures the lport mapping based on the reply from the 1645 * switch API. 1646 **/ 1647 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, 1648 struct fm10k_mbx_info *mbx) 1649 { 1650 u16 glort, mask; 1651 u32 dglort_map; 1652 s32 err; 1653 1654 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], 1655 &dglort_map); 1656 if (err) 1657 return err; 1658 1659 /* extract values out of the header */ 1660 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); 1661 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); 1662 1663 /* verify mask is set and none of the masked bits in glort are set */ 1664 if (!mask || (glort & ~mask)) 1665 return FM10K_ERR_PARAM; 1666 1667 /* verify the mask is contiguous, and that it is 1's followed by 0's */ 1668 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) 1669 return FM10K_ERR_PARAM; 1670 1671 /* record the glort, mask, and port count */ 1672 hw->mac.dglort_map = dglort_map; 1673 1674 return 0; 1675 } 1676 1677 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { 1678 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), 1679 FM10K_TLV_ATTR_LAST 1680 }; 1681 1682 /** 1683 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM 1684 * @hw: Pointer to hardware structure 1685 * @results: pointer array containing parsed data 1686 * @mbx: Pointer to mailbox information structure 1687 * 1688 * This handler configures the default VLAN for the PF 1689 **/ 1690 s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, 1691 struct fm10k_mbx_info *mbx) 1692 { 1693 u16 glort, pvid; 1694 u32 pvid_update; 1695 s32 err; 1696 1697 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], 1698 &pvid_update); 1699 if (err) 1700 return err; 1701 1702 /* extract values from the pvid update */ 1703 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); 1704 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); 1705 1706 /* if glort is not valid return error */ 1707 if (!fm10k_glort_valid_pf(hw, glort)) 1708 return FM10K_ERR_PARAM; 1709 1710 /* verify VID is valid */ 1711 if (pvid >= FM10K_VLAN_TABLE_VID_MAX) 1712 return FM10K_ERR_PARAM; 1713 1714 /* record the port VLAN ID value */ 1715 hw->mac.default_vid = pvid; 1716 1717 return 0; 1718 } 1719 1720 /** 1721 * fm10k_record_global_table_data - Move global table data to swapi table info 1722 * @from: pointer to source table data structure 1723 * @to: pointer to destination table info structure 1724 * 1725 * This function is will copy table_data to the table_info contained in 1726 * the hw struct. 1727 **/ 1728 static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, 1729 struct fm10k_swapi_table_info *to) 1730 { 1731 /* convert from le32 struct to CPU byte ordered values */ 1732 to->used = le32_to_cpu(from->used); 1733 to->avail = le32_to_cpu(from->avail); 1734 } 1735 1736 const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { 1737 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, 1738 sizeof(struct fm10k_swapi_error)), 1739 FM10K_TLV_ATTR_LAST 1740 }; 1741 1742 /** 1743 * fm10k_msg_err_pf - Message handler for error reply 1744 * @hw: Pointer to hardware structure 1745 * @results: pointer array containing parsed data 1746 * @mbx: Pointer to mailbox information structure 1747 * 1748 * This handler will capture the data for any error replies to previous 1749 * messages that the PF has sent. 1750 **/ 1751 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, 1752 struct fm10k_mbx_info *mbx) 1753 { 1754 struct fm10k_swapi_error err_msg; 1755 s32 err; 1756 1757 /* extract structure from message */ 1758 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], 1759 &err_msg, sizeof(err_msg)); 1760 if (err) 1761 return err; 1762 1763 /* record table status */ 1764 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); 1765 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); 1766 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); 1767 1768 /* record SW API status value */ 1769 hw->swapi.status = le32_to_cpu(err_msg.status); 1770 1771 return 0; 1772 } 1773 1774 const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = { 1775 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP, 1776 sizeof(struct fm10k_swapi_1588_timestamp)), 1777 FM10K_TLV_ATTR_LAST 1778 }; 1779 1780 /* currently there is no shared 1588 timestamp handler */ 1781 1782 /** 1783 * fm10k_adjust_systime_pf - Adjust systime frequency 1784 * @hw: pointer to hardware structure 1785 * @ppb: adjustment rate in parts per billion 1786 * 1787 * This function will adjust the SYSTIME_CFG register contained in BAR 4 1788 * if this function is supported for BAR 4 access. The adjustment amount 1789 * is based on the parts per billion value provided and adjusted to a 1790 * value based on parts per 2^48 clock cycles. 1791 * 1792 * If adjustment is not supported or the requested value is too large 1793 * we will return an error. 1794 **/ 1795 static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb) 1796 { 1797 u64 systime_adjust; 1798 1799 /* if sw_addr is not set we don't have switch register access */ 1800 if (!hw->sw_addr) 1801 return ppb ? FM10K_ERR_PARAM : 0; 1802 1803 /* we must convert the value from parts per billion to parts per 1804 * 2^48 cycles. In addition I have opted to only use the 30 most 1805 * significant bits of the adjustment value as the 8 least 1806 * significant bits are located in another register and represent 1807 * a value significantly less than a part per billion, the result 1808 * of dropping the 8 least significant bits is that the adjustment 1809 * value is effectively multiplied by 2^8 when we write it. 1810 * 1811 * As a result of all this the math for this breaks down as follows: 1812 * ppb / 10^9 == adjust * 2^8 / 2^48 1813 * If we solve this for adjust, and simplify it comes out as: 1814 * ppb * 2^31 / 5^9 == adjust 1815 */ 1816 systime_adjust = (ppb < 0) ? -ppb : ppb; 1817 systime_adjust <<= 31; 1818 do_div(systime_adjust, 1953125); 1819 1820 /* verify the requested adjustment value is in range */ 1821 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK) 1822 return FM10K_ERR_PARAM; 1823 1824 if (ppb > 0) 1825 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE; 1826 1827 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust); 1828 1829 return 0; 1830 } 1831 1832 /** 1833 * fm10k_read_systime_pf - Reads value of systime registers 1834 * @hw: pointer to the hardware structure 1835 * 1836 * Function reads the content of 2 registers, combined to represent a 64 bit 1837 * value measured in nanosecods. In order to guarantee the value is accurate 1838 * we check the 32 most significant bits both before and after reading the 1839 * 32 least significant bits to verify they didn't change as we were reading 1840 * the registers. 1841 **/ 1842 static u64 fm10k_read_systime_pf(struct fm10k_hw *hw) 1843 { 1844 u32 systime_l, systime_h, systime_tmp; 1845 1846 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); 1847 1848 do { 1849 systime_tmp = systime_h; 1850 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME); 1851 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); 1852 } while (systime_tmp != systime_h); 1853 1854 return ((u64)systime_h << 32) | systime_l; 1855 } 1856 1857 static const struct fm10k_msg_data fm10k_msg_data_pf[] = { 1858 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), 1859 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), 1860 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), 1861 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), 1862 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), 1863 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), 1864 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), 1865 }; 1866 1867 static struct fm10k_mac_ops mac_ops_pf = { 1868 .get_bus_info = &fm10k_get_bus_info_generic, 1869 .reset_hw = &fm10k_reset_hw_pf, 1870 .init_hw = &fm10k_init_hw_pf, 1871 .start_hw = &fm10k_start_hw_generic, 1872 .stop_hw = &fm10k_stop_hw_generic, 1873 .update_vlan = &fm10k_update_vlan_pf, 1874 .read_mac_addr = &fm10k_read_mac_addr_pf, 1875 .update_uc_addr = &fm10k_update_uc_addr_pf, 1876 .update_mc_addr = &fm10k_update_mc_addr_pf, 1877 .update_xcast_mode = &fm10k_update_xcast_mode_pf, 1878 .update_int_moderator = &fm10k_update_int_moderator_pf, 1879 .update_lport_state = &fm10k_update_lport_state_pf, 1880 .update_hw_stats = &fm10k_update_hw_stats_pf, 1881 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf, 1882 .configure_dglort_map = &fm10k_configure_dglort_map_pf, 1883 .set_dma_mask = &fm10k_set_dma_mask_pf, 1884 .get_fault = &fm10k_get_fault_pf, 1885 .get_host_state = &fm10k_get_host_state_pf, 1886 .adjust_systime = &fm10k_adjust_systime_pf, 1887 .read_systime = &fm10k_read_systime_pf, 1888 }; 1889 1890 static struct fm10k_iov_ops iov_ops_pf = { 1891 .assign_resources = &fm10k_iov_assign_resources_pf, 1892 .configure_tc = &fm10k_iov_configure_tc_pf, 1893 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf, 1894 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, 1895 .reset_resources = &fm10k_iov_reset_resources_pf, 1896 .set_lport = &fm10k_iov_set_lport_pf, 1897 .reset_lport = &fm10k_iov_reset_lport_pf, 1898 .update_stats = &fm10k_iov_update_stats_pf, 1899 .report_timestamp = &fm10k_iov_report_timestamp_pf, 1900 }; 1901 1902 static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) 1903 { 1904 fm10k_get_invariants_generic(hw); 1905 1906 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); 1907 } 1908 1909 struct fm10k_info fm10k_pf_info = { 1910 .mac = fm10k_mac_pf, 1911 .get_invariants = &fm10k_get_invariants_pf, 1912 .mac_ops = &mac_ops_pf, 1913 .iov_ops = &iov_ops_pf, 1914 }; 1915