1b6fec18fSAlexander Duyck /* Intel Ethernet Switch Host Interface Driver 2b6fec18fSAlexander Duyck * Copyright(c) 2013 - 2014 Intel Corporation. 3b6fec18fSAlexander Duyck * 4b6fec18fSAlexander Duyck * This program is free software; you can redistribute it and/or modify it 5b6fec18fSAlexander Duyck * under the terms and conditions of the GNU General Public License, 6b6fec18fSAlexander Duyck * version 2, as published by the Free Software Foundation. 7b6fec18fSAlexander Duyck * 8b6fec18fSAlexander Duyck * This program is distributed in the hope it will be useful, but WITHOUT 9b6fec18fSAlexander Duyck * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10b6fec18fSAlexander Duyck * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11b6fec18fSAlexander Duyck * more details. 12b6fec18fSAlexander Duyck * 13b6fec18fSAlexander Duyck * The full GNU General Public License is included in this distribution in 14b6fec18fSAlexander Duyck * the file called "COPYING". 15b6fec18fSAlexander Duyck * 16b6fec18fSAlexander Duyck * Contact Information: 17b6fec18fSAlexander Duyck * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18b6fec18fSAlexander Duyck * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19b6fec18fSAlexander Duyck */ 20b6fec18fSAlexander Duyck 21b6fec18fSAlexander Duyck #include "fm10k_pf.h" 22c2653865SAlexander Duyck #include "fm10k_vf.h" 23b6fec18fSAlexander Duyck 24b6fec18fSAlexander Duyck /** 25b6fec18fSAlexander Duyck * fm10k_reset_hw_pf - PF hardware reset 26b6fec18fSAlexander Duyck * @hw: pointer to hardware structure 27b6fec18fSAlexander Duyck * 28b6fec18fSAlexander Duyck * This function should return the hardware to a state similar to the 29b6fec18fSAlexander Duyck * one it is in after being powered on. 30b6fec18fSAlexander Duyck **/ 31b6fec18fSAlexander Duyck static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) 32b6fec18fSAlexander Duyck { 33b6fec18fSAlexander Duyck s32 err; 34b6fec18fSAlexander Duyck u32 reg; 35b6fec18fSAlexander Duyck u16 i; 36b6fec18fSAlexander Duyck 37b6fec18fSAlexander Duyck /* Disable interrupts */ 38b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); 39b6fec18fSAlexander Duyck 40b6fec18fSAlexander Duyck /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ 41b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), 0); 42b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 43b6fec18fSAlexander Duyck 44b6fec18fSAlexander Duyck /* We assume here Tx and Rx queue 0 are owned by the PF */ 45b6fec18fSAlexander Duyck 46b6fec18fSAlexander Duyck /* Shut off VF access to their queues forcing them to queue 0 */ 47b6fec18fSAlexander Duyck for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { 48b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 49b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 50b6fec18fSAlexander Duyck } 51b6fec18fSAlexander Duyck 52b6fec18fSAlexander Duyck /* shut down all rings */ 53b6fec18fSAlexander Duyck err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); 54b6fec18fSAlexander Duyck if (err) 55b6fec18fSAlexander Duyck return err; 56b6fec18fSAlexander Duyck 57b6fec18fSAlexander Duyck /* Verify that DMA is no longer active */ 58b6fec18fSAlexander Duyck reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); 59b6fec18fSAlexander Duyck if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) 60b6fec18fSAlexander Duyck return FM10K_ERR_DMA_PENDING; 61b6fec18fSAlexander Duyck 62ac981003SAlexander Duyck /* verify the switch is ready for reset */ 63ac981003SAlexander Duyck reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 64ac981003SAlexander Duyck if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY)) 65ac981003SAlexander Duyck goto out; 66ac981003SAlexander Duyck 67b6fec18fSAlexander Duyck /* Inititate data path reset */ 68b6fec18fSAlexander Duyck reg |= FM10K_DMA_CTRL_DATAPATH_RESET; 69b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); 70b6fec18fSAlexander Duyck 71b6fec18fSAlexander Duyck /* Flush write and allow 100us for reset to complete */ 72b6fec18fSAlexander Duyck fm10k_write_flush(hw); 73b6fec18fSAlexander Duyck udelay(FM10K_RESET_TIMEOUT); 74b6fec18fSAlexander Duyck 75b6fec18fSAlexander Duyck /* Verify we made it out of reset */ 76b6fec18fSAlexander Duyck reg = fm10k_read_reg(hw, FM10K_IP); 77b6fec18fSAlexander Duyck if (!(reg & FM10K_IP_NOTINRESET)) 78b6fec18fSAlexander Duyck err = FM10K_ERR_RESET_FAILED; 79b6fec18fSAlexander Duyck 80ac981003SAlexander Duyck out: 81b6fec18fSAlexander Duyck return err; 82b6fec18fSAlexander Duyck } 83b6fec18fSAlexander Duyck 84b6fec18fSAlexander Duyck /** 85c2653865SAlexander Duyck * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support 86c2653865SAlexander Duyck * @hw: pointer to hardware structure 87c2653865SAlexander Duyck * 88c2653865SAlexander Duyck * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. 89c2653865SAlexander Duyck **/ 90c2653865SAlexander Duyck static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) 91c2653865SAlexander Duyck { 92c2653865SAlexander Duyck u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); 93c2653865SAlexander Duyck 94c2653865SAlexander Duyck return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); 95c2653865SAlexander Duyck } 96c2653865SAlexander Duyck 97c2653865SAlexander Duyck /** 98b6fec18fSAlexander Duyck * fm10k_init_hw_pf - PF hardware initialization 99b6fec18fSAlexander Duyck * @hw: pointer to hardware structure 100b6fec18fSAlexander Duyck * 101b6fec18fSAlexander Duyck **/ 102b6fec18fSAlexander Duyck static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) 103b6fec18fSAlexander Duyck { 104b6fec18fSAlexander Duyck u32 dma_ctrl, txqctl; 105b6fec18fSAlexander Duyck u16 i; 106b6fec18fSAlexander Duyck 107b6fec18fSAlexander Duyck /* Establish default VSI as valid */ 108b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); 109b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), 110b6fec18fSAlexander Duyck FM10K_DGLORTMAP_ANY); 111b6fec18fSAlexander Duyck 112b6fec18fSAlexander Duyck /* Invalidate all other GLORT entries */ 113b6fec18fSAlexander Duyck for (i = 1; i < FM10K_DGLORT_COUNT; i++) 114b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); 115b6fec18fSAlexander Duyck 116b6fec18fSAlexander Duyck /* reset ITR2(0) to point to itself */ 117b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), 0); 118b6fec18fSAlexander Duyck 119b6fec18fSAlexander Duyck /* reset VF ITR2(0) to point to 0 avoid PF registers */ 120b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); 121b6fec18fSAlexander Duyck 122b6fec18fSAlexander Duyck /* loop through all PF ITR2 registers pointing them to the previous */ 123b6fec18fSAlexander Duyck for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) 124b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 125b6fec18fSAlexander Duyck 126b6fec18fSAlexander Duyck /* Enable interrupt moderator if not already enabled */ 127b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 128b6fec18fSAlexander Duyck 129b6fec18fSAlexander Duyck /* compute the default txqctl configuration */ 130b6fec18fSAlexander Duyck txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | 131b6fec18fSAlexander Duyck (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); 132b6fec18fSAlexander Duyck 133b6fec18fSAlexander Duyck for (i = 0; i < FM10K_MAX_QUEUES; i++) { 134b6fec18fSAlexander Duyck /* configure rings for 256 Queue / 32 Descriptor cache mode */ 135b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_TQDLOC(i), 136b6fec18fSAlexander Duyck (i * FM10K_TQDLOC_BASE_32_DESC) | 137b6fec18fSAlexander Duyck FM10K_TQDLOC_SIZE_32_DESC); 138b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 139b6fec18fSAlexander Duyck 140b6fec18fSAlexander Duyck /* configure rings to provide TPH processing hints */ 141b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), 142b6fec18fSAlexander Duyck FM10K_TPH_TXCTRL_DESC_TPHEN | 143b6fec18fSAlexander Duyck FM10K_TPH_TXCTRL_DESC_RROEN | 144b6fec18fSAlexander Duyck FM10K_TPH_TXCTRL_DESC_WROEN | 145b6fec18fSAlexander Duyck FM10K_TPH_TXCTRL_DATA_RROEN); 146b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), 147b6fec18fSAlexander Duyck FM10K_TPH_RXCTRL_DESC_TPHEN | 148b6fec18fSAlexander Duyck FM10K_TPH_RXCTRL_DESC_RROEN | 149b6fec18fSAlexander Duyck FM10K_TPH_RXCTRL_DATA_WROEN | 150b6fec18fSAlexander Duyck FM10K_TPH_RXCTRL_HDR_WROEN); 151b6fec18fSAlexander Duyck } 152b6fec18fSAlexander Duyck 153b6fec18fSAlexander Duyck /* set max hold interval to align with 1.024 usec in all modes */ 154b6fec18fSAlexander Duyck switch (hw->bus.speed) { 155b6fec18fSAlexander Duyck case fm10k_bus_speed_2500: 156b6fec18fSAlexander Duyck dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; 157b6fec18fSAlexander Duyck break; 158b6fec18fSAlexander Duyck case fm10k_bus_speed_5000: 159b6fec18fSAlexander Duyck dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; 160b6fec18fSAlexander Duyck break; 161b6fec18fSAlexander Duyck case fm10k_bus_speed_8000: 162b6fec18fSAlexander Duyck dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; 163b6fec18fSAlexander Duyck break; 164b6fec18fSAlexander Duyck default: 165b6fec18fSAlexander Duyck dma_ctrl = 0; 166b6fec18fSAlexander Duyck break; 167b6fec18fSAlexander Duyck } 168b6fec18fSAlexander Duyck 169b6fec18fSAlexander Duyck /* Configure TSO flags */ 170b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); 171b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); 172b6fec18fSAlexander Duyck 173b6fec18fSAlexander Duyck /* Enable DMA engine 174b6fec18fSAlexander Duyck * Set Rx Descriptor size to 32 175b6fec18fSAlexander Duyck * Set Minimum MSS to 64 176b6fec18fSAlexander Duyck * Set Maximum number of Rx queues to 256 / 32 Descriptor 177b6fec18fSAlexander Duyck */ 178b6fec18fSAlexander Duyck dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | 179b6fec18fSAlexander Duyck FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | 180b6fec18fSAlexander Duyck FM10K_DMA_CTRL_32_DESC; 181b6fec18fSAlexander Duyck 182b6fec18fSAlexander Duyck fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); 183b6fec18fSAlexander Duyck 184b6fec18fSAlexander Duyck /* record maximum queue count, we limit ourselves to 128 */ 185b6fec18fSAlexander Duyck hw->mac.max_queues = FM10K_MAX_QUEUES_PF; 186b6fec18fSAlexander Duyck 187c2653865SAlexander Duyck /* We support either 64 VFs or 7 VFs depending on if we have ARI */ 188c2653865SAlexander Duyck hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; 189c2653865SAlexander Duyck 190b6fec18fSAlexander Duyck return 0; 191b6fec18fSAlexander Duyck } 192b6fec18fSAlexander Duyck 193b6fec18fSAlexander Duyck /** 194401b5383SAlexander Duyck * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table 195401b5383SAlexander Duyck * @hw: pointer to hardware structure 196401b5383SAlexander Duyck * @vid: VLAN ID to add to table 197401b5383SAlexander Duyck * @vsi: Index indicating VF ID or PF ID in table 198401b5383SAlexander Duyck * @set: Indicates if this is a set or clear operation 199401b5383SAlexander Duyck * 200401b5383SAlexander Duyck * This function adds or removes the corresponding VLAN ID from the VLAN 201401b5383SAlexander Duyck * filter table for the corresponding function. In addition to the 202401b5383SAlexander Duyck * standard set/clear that supports one bit a multi-bit write is 203401b5383SAlexander Duyck * supported to set 64 bits at a time. 204401b5383SAlexander Duyck **/ 205401b5383SAlexander Duyck static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) 206401b5383SAlexander Duyck { 207401b5383SAlexander Duyck u32 vlan_table, reg, mask, bit, len; 208401b5383SAlexander Duyck 209401b5383SAlexander Duyck /* verify the VSI index is valid */ 210401b5383SAlexander Duyck if (vsi > FM10K_VLAN_TABLE_VSI_MAX) 211401b5383SAlexander Duyck return FM10K_ERR_PARAM; 212401b5383SAlexander Duyck 213401b5383SAlexander Duyck /* VLAN multi-bit write: 214401b5383SAlexander Duyck * The multi-bit write has several parts to it. 215401b5383SAlexander Duyck * 3 2 1 0 216401b5383SAlexander Duyck * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 217401b5383SAlexander Duyck * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 218401b5383SAlexander Duyck * | RSVD0 | Length |C|RSVD0| VLAN ID | 219401b5383SAlexander Duyck * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 220401b5383SAlexander Duyck * 221401b5383SAlexander Duyck * VLAN ID: Vlan Starting value 222401b5383SAlexander Duyck * RSVD0: Reserved section, must be 0 223401b5383SAlexander Duyck * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) 224401b5383SAlexander Duyck * Length: Number of times to repeat the bit being set 225401b5383SAlexander Duyck */ 226401b5383SAlexander Duyck len = vid >> 16; 227401b5383SAlexander Duyck vid = (vid << 17) >> 17; 228401b5383SAlexander Duyck 229401b5383SAlexander Duyck /* verify the reserved 0 fields are 0 */ 230eca32047SMatthew Vick if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) 231401b5383SAlexander Duyck return FM10K_ERR_PARAM; 232401b5383SAlexander Duyck 233401b5383SAlexander Duyck /* Loop through the table updating all required VLANs */ 234401b5383SAlexander Duyck for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; 235401b5383SAlexander Duyck len < FM10K_VLAN_TABLE_VID_MAX; 236401b5383SAlexander Duyck len -= 32 - bit, reg++, bit = 0) { 237401b5383SAlexander Duyck /* record the initial state of the register */ 238401b5383SAlexander Duyck vlan_table = fm10k_read_reg(hw, reg); 239401b5383SAlexander Duyck 240401b5383SAlexander Duyck /* truncate mask if we are at the start or end of the run */ 241401b5383SAlexander Duyck mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; 242401b5383SAlexander Duyck 243401b5383SAlexander Duyck /* make necessary modifications to the register */ 244401b5383SAlexander Duyck mask &= set ? ~vlan_table : vlan_table; 245401b5383SAlexander Duyck if (mask) 246401b5383SAlexander Duyck fm10k_write_reg(hw, reg, vlan_table ^ mask); 247401b5383SAlexander Duyck } 248401b5383SAlexander Duyck 249401b5383SAlexander Duyck return 0; 250401b5383SAlexander Duyck } 251401b5383SAlexander Duyck 252401b5383SAlexander Duyck /** 253b6fec18fSAlexander Duyck * fm10k_read_mac_addr_pf - Read device MAC address 254b6fec18fSAlexander Duyck * @hw: pointer to the HW structure 255b6fec18fSAlexander Duyck * 256b6fec18fSAlexander Duyck * Reads the device MAC address from the SM_AREA and stores the value. 257b6fec18fSAlexander Duyck **/ 258b6fec18fSAlexander Duyck static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) 259b6fec18fSAlexander Duyck { 260b6fec18fSAlexander Duyck u8 perm_addr[ETH_ALEN]; 261b6fec18fSAlexander Duyck u32 serial_num; 262b6fec18fSAlexander Duyck int i; 263b6fec18fSAlexander Duyck 264b6fec18fSAlexander Duyck serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); 265b6fec18fSAlexander Duyck 266b6fec18fSAlexander Duyck /* last byte should be all 1's */ 267b6fec18fSAlexander Duyck if ((~serial_num) << 24) 268b6fec18fSAlexander Duyck return FM10K_ERR_INVALID_MAC_ADDR; 269b6fec18fSAlexander Duyck 270b6fec18fSAlexander Duyck perm_addr[0] = (u8)(serial_num >> 24); 271b6fec18fSAlexander Duyck perm_addr[1] = (u8)(serial_num >> 16); 272b6fec18fSAlexander Duyck perm_addr[2] = (u8)(serial_num >> 8); 273b6fec18fSAlexander Duyck 274b6fec18fSAlexander Duyck serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); 275b6fec18fSAlexander Duyck 276b6fec18fSAlexander Duyck /* first byte should be all 1's */ 277b6fec18fSAlexander Duyck if ((~serial_num) >> 24) 278b6fec18fSAlexander Duyck return FM10K_ERR_INVALID_MAC_ADDR; 279b6fec18fSAlexander Duyck 280b6fec18fSAlexander Duyck perm_addr[3] = (u8)(serial_num >> 16); 281b6fec18fSAlexander Duyck perm_addr[4] = (u8)(serial_num >> 8); 282b6fec18fSAlexander Duyck perm_addr[5] = (u8)(serial_num); 283b6fec18fSAlexander Duyck 284b6fec18fSAlexander Duyck for (i = 0; i < ETH_ALEN; i++) { 285b6fec18fSAlexander Duyck hw->mac.perm_addr[i] = perm_addr[i]; 286b6fec18fSAlexander Duyck hw->mac.addr[i] = perm_addr[i]; 287b6fec18fSAlexander Duyck } 288b6fec18fSAlexander Duyck 289b6fec18fSAlexander Duyck return 0; 290b6fec18fSAlexander Duyck } 291b6fec18fSAlexander Duyck 292b6fec18fSAlexander Duyck /** 293401b5383SAlexander Duyck * fm10k_glort_valid_pf - Validate that the provided glort is valid 294401b5383SAlexander Duyck * @hw: pointer to the HW structure 295401b5383SAlexander Duyck * @glort: base glort to be validated 296401b5383SAlexander Duyck * 297401b5383SAlexander Duyck * This function will return an error if the provided glort is invalid 298401b5383SAlexander Duyck **/ 299401b5383SAlexander Duyck bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) 300401b5383SAlexander Duyck { 301401b5383SAlexander Duyck glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; 302401b5383SAlexander Duyck 303401b5383SAlexander Duyck return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); 304401b5383SAlexander Duyck } 305401b5383SAlexander Duyck 306401b5383SAlexander Duyck /** 307eca32047SMatthew Vick * fm10k_update_xc_addr_pf - Update device addresses 308401b5383SAlexander Duyck * @hw: pointer to the HW structure 309401b5383SAlexander Duyck * @glort: base resource tag for this request 310401b5383SAlexander Duyck * @mac: MAC address to add/remove from table 311401b5383SAlexander Duyck * @vid: VLAN ID to add/remove from table 312401b5383SAlexander Duyck * @add: Indicates if this is an add or remove operation 313401b5383SAlexander Duyck * @flags: flags field to indicate add and secure 314401b5383SAlexander Duyck * 315401b5383SAlexander Duyck * This function generates a message to the Switch API requesting 316401b5383SAlexander Duyck * that the given logical port add/remove the given L2 MAC/VLAN address. 317401b5383SAlexander Duyck **/ 318401b5383SAlexander Duyck static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, 319401b5383SAlexander Duyck const u8 *mac, u16 vid, bool add, u8 flags) 320401b5383SAlexander Duyck { 321401b5383SAlexander Duyck struct fm10k_mbx_info *mbx = &hw->mbx; 322401b5383SAlexander Duyck struct fm10k_mac_update mac_update; 323401b5383SAlexander Duyck u32 msg[5]; 324401b5383SAlexander Duyck 325b32d15b9SJeff Kirsher /* clear set bit from VLAN ID */ 326b32d15b9SJeff Kirsher vid &= ~FM10K_VLAN_CLEAR; 327b32d15b9SJeff Kirsher 32833a44c28SMatthew Vick /* if glort or vlan are not valid return error */ 32933a44c28SMatthew Vick if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) 330401b5383SAlexander Duyck return FM10K_ERR_PARAM; 331401b5383SAlexander Duyck 332401b5383SAlexander Duyck /* record fields */ 333401b5383SAlexander Duyck mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | 334401b5383SAlexander Duyck ((u32)mac[3] << 16) | 335401b5383SAlexander Duyck ((u32)mac[4] << 8) | 336401b5383SAlexander Duyck ((u32)mac[5])); 337401b5383SAlexander Duyck mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) | 338401b5383SAlexander Duyck ((u32)mac[1])); 339401b5383SAlexander Duyck mac_update.vlan = cpu_to_le16(vid); 340401b5383SAlexander Duyck mac_update.glort = cpu_to_le16(glort); 341401b5383SAlexander Duyck mac_update.action = add ? 0 : 1; 342401b5383SAlexander Duyck mac_update.flags = flags; 343401b5383SAlexander Duyck 344401b5383SAlexander Duyck /* populate mac_update fields */ 345401b5383SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); 346401b5383SAlexander Duyck fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, 347401b5383SAlexander Duyck &mac_update, sizeof(mac_update)); 348401b5383SAlexander Duyck 349401b5383SAlexander Duyck /* load onto outgoing mailbox */ 350401b5383SAlexander Duyck return mbx->ops.enqueue_tx(hw, mbx, msg); 351401b5383SAlexander Duyck } 352401b5383SAlexander Duyck 353401b5383SAlexander Duyck /** 354eca32047SMatthew Vick * fm10k_update_uc_addr_pf - Update device unicast addresses 355401b5383SAlexander Duyck * @hw: pointer to the HW structure 356401b5383SAlexander Duyck * @glort: base resource tag for this request 357401b5383SAlexander Duyck * @mac: MAC address to add/remove from table 358401b5383SAlexander Duyck * @vid: VLAN ID to add/remove from table 359401b5383SAlexander Duyck * @add: Indicates if this is an add or remove operation 360401b5383SAlexander Duyck * @flags: flags field to indicate add and secure 361401b5383SAlexander Duyck * 362401b5383SAlexander Duyck * This function is used to add or remove unicast addresses for 363401b5383SAlexander Duyck * the PF. 364401b5383SAlexander Duyck **/ 365401b5383SAlexander Duyck static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, 366401b5383SAlexander Duyck const u8 *mac, u16 vid, bool add, u8 flags) 367401b5383SAlexander Duyck { 368401b5383SAlexander Duyck /* verify MAC address is valid */ 369401b5383SAlexander Duyck if (!is_valid_ether_addr(mac)) 370401b5383SAlexander Duyck return FM10K_ERR_PARAM; 371401b5383SAlexander Duyck 372401b5383SAlexander Duyck return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); 373401b5383SAlexander Duyck } 374401b5383SAlexander Duyck 375401b5383SAlexander Duyck /** 376401b5383SAlexander Duyck * fm10k_update_mc_addr_pf - Update device multicast addresses 377401b5383SAlexander Duyck * @hw: pointer to the HW structure 378401b5383SAlexander Duyck * @glort: base resource tag for this request 379401b5383SAlexander Duyck * @mac: MAC address to add/remove from table 380401b5383SAlexander Duyck * @vid: VLAN ID to add/remove from table 381401b5383SAlexander Duyck * @add: Indicates if this is an add or remove operation 382401b5383SAlexander Duyck * 383401b5383SAlexander Duyck * This function is used to add or remove multicast MAC addresses for 384401b5383SAlexander Duyck * the PF. 385401b5383SAlexander Duyck **/ 386401b5383SAlexander Duyck static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, 387401b5383SAlexander Duyck const u8 *mac, u16 vid, bool add) 388401b5383SAlexander Duyck { 389401b5383SAlexander Duyck /* verify multicast address is valid */ 390401b5383SAlexander Duyck if (!is_multicast_ether_addr(mac)) 391401b5383SAlexander Duyck return FM10K_ERR_PARAM; 392401b5383SAlexander Duyck 393401b5383SAlexander Duyck return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); 394401b5383SAlexander Duyck } 395401b5383SAlexander Duyck 396401b5383SAlexander Duyck /** 397401b5383SAlexander Duyck * fm10k_update_xcast_mode_pf - Request update of multicast mode 398401b5383SAlexander Duyck * @hw: pointer to hardware structure 399401b5383SAlexander Duyck * @glort: base resource tag for this request 400401b5383SAlexander Duyck * @mode: integer value indicating mode being requested 401401b5383SAlexander Duyck * 402401b5383SAlexander Duyck * This function will attempt to request a higher mode for the port 403401b5383SAlexander Duyck * so that it can enable either multicast, multicast promiscuous, or 404401b5383SAlexander Duyck * promiscuous mode of operation. 405401b5383SAlexander Duyck **/ 406401b5383SAlexander Duyck static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) 407401b5383SAlexander Duyck { 408401b5383SAlexander Duyck struct fm10k_mbx_info *mbx = &hw->mbx; 409401b5383SAlexander Duyck u32 msg[3], xcast_mode; 410401b5383SAlexander Duyck 411401b5383SAlexander Duyck if (mode > FM10K_XCAST_MODE_NONE) 412401b5383SAlexander Duyck return FM10K_ERR_PARAM; 413401b5383SAlexander Duyck /* if glort is not valid return error */ 414401b5383SAlexander Duyck if (!fm10k_glort_valid_pf(hw, glort)) 415401b5383SAlexander Duyck return FM10K_ERR_PARAM; 416401b5383SAlexander Duyck 417401b5383SAlexander Duyck /* write xcast mode as a single u32 value, 418401b5383SAlexander Duyck * lower 16 bits: glort 419401b5383SAlexander Duyck * upper 16 bits: mode 420401b5383SAlexander Duyck */ 421401b5383SAlexander Duyck xcast_mode = ((u32)mode << 16) | glort; 422401b5383SAlexander Duyck 423401b5383SAlexander Duyck /* generate message requesting to change xcast mode */ 424401b5383SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); 425401b5383SAlexander Duyck fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); 426401b5383SAlexander Duyck 427401b5383SAlexander Duyck /* load onto outgoing mailbox */ 428401b5383SAlexander Duyck return mbx->ops.enqueue_tx(hw, mbx, msg); 429401b5383SAlexander Duyck } 430401b5383SAlexander Duyck 431401b5383SAlexander Duyck /** 432401b5383SAlexander Duyck * fm10k_update_int_moderator_pf - Update interrupt moderator linked list 433401b5383SAlexander Duyck * @hw: pointer to hardware structure 434401b5383SAlexander Duyck * 435401b5383SAlexander Duyck * This function walks through the MSI-X vector table to determine the 436401b5383SAlexander Duyck * number of active interrupts and based on that information updates the 437401b5383SAlexander Duyck * interrupt moderator linked list. 438401b5383SAlexander Duyck **/ 439401b5383SAlexander Duyck static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) 440401b5383SAlexander Duyck { 441401b5383SAlexander Duyck u32 i; 442401b5383SAlexander Duyck 443401b5383SAlexander Duyck /* Disable interrupt moderator */ 444401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_INT_CTRL, 0); 445401b5383SAlexander Duyck 446401b5383SAlexander Duyck /* loop through PF from last to first looking enabled vectors */ 447401b5383SAlexander Duyck for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { 448401b5383SAlexander Duyck if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 449401b5383SAlexander Duyck break; 450401b5383SAlexander Duyck } 451401b5383SAlexander Duyck 452401b5383SAlexander Duyck /* always reset VFITR2[0] to point to last enabled PF vector */ 453401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); 454401b5383SAlexander Duyck 455401b5383SAlexander Duyck /* reset ITR2[0] to point to last enabled PF vector */ 456c2653865SAlexander Duyck if (!hw->iov.num_vfs) 457401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), i); 458401b5383SAlexander Duyck 459401b5383SAlexander Duyck /* Enable interrupt moderator */ 460401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); 461401b5383SAlexander Duyck } 462401b5383SAlexander Duyck 463401b5383SAlexander Duyck /** 464401b5383SAlexander Duyck * fm10k_update_lport_state_pf - Notify the switch of a change in port state 465401b5383SAlexander Duyck * @hw: pointer to the HW structure 466401b5383SAlexander Duyck * @glort: base resource tag for this request 467401b5383SAlexander Duyck * @count: number of logical ports being updated 468401b5383SAlexander Duyck * @enable: boolean value indicating enable or disable 469401b5383SAlexander Duyck * 470401b5383SAlexander Duyck * This function is used to add/remove a logical port from the switch. 471401b5383SAlexander Duyck **/ 472401b5383SAlexander Duyck static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, 473401b5383SAlexander Duyck u16 count, bool enable) 474401b5383SAlexander Duyck { 475401b5383SAlexander Duyck struct fm10k_mbx_info *mbx = &hw->mbx; 476401b5383SAlexander Duyck u32 msg[3], lport_msg; 477401b5383SAlexander Duyck 478401b5383SAlexander Duyck /* do nothing if we are being asked to create or destroy 0 ports */ 479401b5383SAlexander Duyck if (!count) 480401b5383SAlexander Duyck return 0; 481401b5383SAlexander Duyck 482401b5383SAlexander Duyck /* if glort is not valid return error */ 483401b5383SAlexander Duyck if (!fm10k_glort_valid_pf(hw, glort)) 484401b5383SAlexander Duyck return FM10K_ERR_PARAM; 485401b5383SAlexander Duyck 486401b5383SAlexander Duyck /* construct the lport message from the 2 pieces of data we have */ 487401b5383SAlexander Duyck lport_msg = ((u32)count << 16) | glort; 488401b5383SAlexander Duyck 489401b5383SAlexander Duyck /* generate lport create/delete message */ 490401b5383SAlexander Duyck fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : 491401b5383SAlexander Duyck FM10K_PF_MSG_ID_LPORT_DELETE); 492401b5383SAlexander Duyck fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); 493401b5383SAlexander Duyck 494401b5383SAlexander Duyck /* load onto outgoing mailbox */ 495401b5383SAlexander Duyck return mbx->ops.enqueue_tx(hw, mbx, msg); 496401b5383SAlexander Duyck } 497401b5383SAlexander Duyck 498401b5383SAlexander Duyck /** 499401b5383SAlexander Duyck * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues 500401b5383SAlexander Duyck * @hw: pointer to hardware structure 501401b5383SAlexander Duyck * @dglort: pointer to dglort configuration structure 502401b5383SAlexander Duyck * 503401b5383SAlexander Duyck * Reads the configuration structure contained in dglort_cfg and uses 504401b5383SAlexander Duyck * that information to then populate a DGLORTMAP/DEC entry and the queues 505401b5383SAlexander Duyck * to which it has been assigned. 506401b5383SAlexander Duyck **/ 507401b5383SAlexander Duyck static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, 508401b5383SAlexander Duyck struct fm10k_dglort_cfg *dglort) 509401b5383SAlexander Duyck { 510401b5383SAlexander Duyck u16 glort, queue_count, vsi_count, pc_count; 511401b5383SAlexander Duyck u16 vsi, queue, pc, q_idx; 512401b5383SAlexander Duyck u32 txqctl, dglortdec, dglortmap; 513401b5383SAlexander Duyck 514401b5383SAlexander Duyck /* verify the dglort pointer */ 515401b5383SAlexander Duyck if (!dglort) 516401b5383SAlexander Duyck return FM10K_ERR_PARAM; 517401b5383SAlexander Duyck 518401b5383SAlexander Duyck /* verify the dglort values */ 519401b5383SAlexander Duyck if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || 520401b5383SAlexander Duyck (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || 521401b5383SAlexander Duyck (dglort->queue_l > 8) || (dglort->queue_b >= 256)) 522401b5383SAlexander Duyck return FM10K_ERR_PARAM; 523401b5383SAlexander Duyck 524401b5383SAlexander Duyck /* determine count of VSIs and queues */ 525401b5383SAlexander Duyck queue_count = 1 << (dglort->rss_l + dglort->pc_l); 526401b5383SAlexander Duyck vsi_count = 1 << (dglort->vsi_l + dglort->queue_l); 527401b5383SAlexander Duyck glort = dglort->glort; 528401b5383SAlexander Duyck q_idx = dglort->queue_b; 529401b5383SAlexander Duyck 530401b5383SAlexander Duyck /* configure SGLORT for queues */ 531401b5383SAlexander Duyck for (vsi = 0; vsi < vsi_count; vsi++, glort++) { 532401b5383SAlexander Duyck for (queue = 0; queue < queue_count; queue++, q_idx++) { 533401b5383SAlexander Duyck if (q_idx >= FM10K_MAX_QUEUES) 534401b5383SAlexander Duyck break; 535401b5383SAlexander Duyck 536401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); 537401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); 538401b5383SAlexander Duyck } 539401b5383SAlexander Duyck } 540401b5383SAlexander Duyck 541401b5383SAlexander Duyck /* determine count of PCs and queues */ 542401b5383SAlexander Duyck queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l); 543401b5383SAlexander Duyck pc_count = 1 << dglort->pc_l; 544401b5383SAlexander Duyck 545401b5383SAlexander Duyck /* configure PC for Tx queues */ 546401b5383SAlexander Duyck for (pc = 0; pc < pc_count; pc++) { 547401b5383SAlexander Duyck q_idx = pc + dglort->queue_b; 548401b5383SAlexander Duyck for (queue = 0; queue < queue_count; queue++) { 549401b5383SAlexander Duyck if (q_idx >= FM10K_MAX_QUEUES) 550401b5383SAlexander Duyck break; 551401b5383SAlexander Duyck 552401b5383SAlexander Duyck txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); 553401b5383SAlexander Duyck txqctl &= ~FM10K_TXQCTL_PC_MASK; 554401b5383SAlexander Duyck txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; 555401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); 556401b5383SAlexander Duyck 557401b5383SAlexander Duyck q_idx += pc_count; 558401b5383SAlexander Duyck } 559401b5383SAlexander Duyck } 560401b5383SAlexander Duyck 561401b5383SAlexander Duyck /* configure DGLORTDEC */ 562401b5383SAlexander Duyck dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | 563401b5383SAlexander Duyck ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | 564401b5383SAlexander Duyck ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | 565401b5383SAlexander Duyck ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | 566401b5383SAlexander Duyck ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | 567401b5383SAlexander Duyck ((u32)(dglort->queue_l)); 568401b5383SAlexander Duyck if (dglort->inner_rss) 569401b5383SAlexander Duyck dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; 570401b5383SAlexander Duyck 571401b5383SAlexander Duyck /* configure DGLORTMAP */ 572401b5383SAlexander Duyck dglortmap = (dglort->idx == fm10k_dglort_default) ? 573401b5383SAlexander Duyck FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; 574401b5383SAlexander Duyck dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; 575401b5383SAlexander Duyck dglortmap |= dglort->glort; 576401b5383SAlexander Duyck 577401b5383SAlexander Duyck /* write values to hardware */ 578401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); 579401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); 580401b5383SAlexander Duyck 581401b5383SAlexander Duyck return 0; 582401b5383SAlexander Duyck } 583401b5383SAlexander Duyck 584c2653865SAlexander Duyck u16 fm10k_queues_per_pool(struct fm10k_hw *hw) 585c2653865SAlexander Duyck { 586c2653865SAlexander Duyck u16 num_pools = hw->iov.num_pools; 587c2653865SAlexander Duyck 588c2653865SAlexander Duyck return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? 589c2653865SAlexander Duyck 8 : FM10K_MAX_QUEUES_POOL; 590c2653865SAlexander Duyck } 591c2653865SAlexander Duyck 592c2653865SAlexander Duyck u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) 593c2653865SAlexander Duyck { 594c2653865SAlexander Duyck u16 num_vfs = hw->iov.num_vfs; 595c2653865SAlexander Duyck u16 vf_q_idx = FM10K_MAX_QUEUES; 596c2653865SAlexander Duyck 597c2653865SAlexander Duyck vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); 598c2653865SAlexander Duyck 599c2653865SAlexander Duyck return vf_q_idx; 600c2653865SAlexander Duyck } 601c2653865SAlexander Duyck 602c2653865SAlexander Duyck static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) 603c2653865SAlexander Duyck { 604c2653865SAlexander Duyck u16 num_pools = hw->iov.num_pools; 605c2653865SAlexander Duyck 606c2653865SAlexander Duyck return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : 607c2653865SAlexander Duyck FM10K_MAX_VECTORS_POOL; 608c2653865SAlexander Duyck } 609c2653865SAlexander Duyck 610c2653865SAlexander Duyck static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) 611c2653865SAlexander Duyck { 612c2653865SAlexander Duyck u16 vf_v_idx = FM10K_MAX_VECTORS_PF; 613c2653865SAlexander Duyck 614c2653865SAlexander Duyck vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; 615c2653865SAlexander Duyck 616c2653865SAlexander Duyck return vf_v_idx; 617c2653865SAlexander Duyck } 618c2653865SAlexander Duyck 619c2653865SAlexander Duyck /** 620c2653865SAlexander Duyck * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization 621c2653865SAlexander Duyck * @hw: pointer to the HW structure 622c2653865SAlexander Duyck * @num_vfs: number of VFs to be allocated 623c2653865SAlexander Duyck * @num_pools: number of virtualization pools to be allocated 624c2653865SAlexander Duyck * 625c2653865SAlexander Duyck * Allocates queues and traffic classes to virtualization entities to prepare 626c2653865SAlexander Duyck * the PF for SR-IOV and VMDq 627c2653865SAlexander Duyck **/ 628c2653865SAlexander Duyck static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, 629c2653865SAlexander Duyck u16 num_pools) 630c2653865SAlexander Duyck { 631c2653865SAlexander Duyck u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; 632c2653865SAlexander Duyck u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; 633c2653865SAlexander Duyck int i, j; 634c2653865SAlexander Duyck 635c2653865SAlexander Duyck /* hardware only supports up to 64 pools */ 636c2653865SAlexander Duyck if (num_pools > 64) 637c2653865SAlexander Duyck return FM10K_ERR_PARAM; 638c2653865SAlexander Duyck 639c2653865SAlexander Duyck /* the number of VFs cannot exceed the number of pools */ 640c2653865SAlexander Duyck if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) 641c2653865SAlexander Duyck return FM10K_ERR_PARAM; 642c2653865SAlexander Duyck 643c2653865SAlexander Duyck /* record number of virtualization entities */ 644c2653865SAlexander Duyck hw->iov.num_vfs = num_vfs; 645c2653865SAlexander Duyck hw->iov.num_pools = num_pools; 646c2653865SAlexander Duyck 647c2653865SAlexander Duyck /* determine qmap offsets and counts */ 648c2653865SAlexander Duyck qmap_stride = (num_vfs > 8) ? 32 : 256; 649c2653865SAlexander Duyck qpp = fm10k_queues_per_pool(hw); 650c2653865SAlexander Duyck vpp = fm10k_vectors_per_pool(hw); 651c2653865SAlexander Duyck 652c2653865SAlexander Duyck /* calculate starting index for queues */ 653c2653865SAlexander Duyck vf_q_idx = fm10k_vf_queue_index(hw, 0); 654c2653865SAlexander Duyck qmap_idx = 0; 655c2653865SAlexander Duyck 656c2653865SAlexander Duyck /* establish TCs with -1 credits and no quanta to prevent transmit */ 657c2653865SAlexander Duyck for (i = 0; i < num_vfs; i++) { 658c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); 659c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); 660c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_CREDIT(i), 661c2653865SAlexander Duyck FM10K_TC_CREDIT_CREDIT_MASK); 662c2653865SAlexander Duyck } 663c2653865SAlexander Duyck 664c2653865SAlexander Duyck /* zero out all mbmem registers */ 665c2653865SAlexander Duyck for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) 666c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_MBMEM(i), 0); 667c2653865SAlexander Duyck 668c2653865SAlexander Duyck /* clear event notification of VF FLR */ 669c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); 670c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); 671c2653865SAlexander Duyck 672c2653865SAlexander Duyck /* loop through unallocated rings assigning them back to PF */ 673c2653865SAlexander Duyck for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { 674c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 675ded8b20dSJeff Kirsher fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | 676ded8b20dSJeff Kirsher FM10K_TXQCTL_UNLIMITED_BW | vid); 677c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); 678c2653865SAlexander Duyck } 679c2653865SAlexander Duyck 680c2653865SAlexander Duyck /* PF should have already updated VFITR2[0] */ 681c2653865SAlexander Duyck 682c2653865SAlexander Duyck /* update all ITR registers to flow to VFITR2[0] */ 683c2653865SAlexander Duyck for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { 684c2653865SAlexander Duyck if (!(i & (vpp - 1))) 685c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); 686c2653865SAlexander Duyck else 687c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); 688c2653865SAlexander Duyck } 689c2653865SAlexander Duyck 690c2653865SAlexander Duyck /* update PF ITR2[0] to reference the last vector */ 691c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), 692c2653865SAlexander Duyck fm10k_vf_vector_index(hw, num_vfs - 1)); 693c2653865SAlexander Duyck 694c2653865SAlexander Duyck /* loop through rings populating rings and TCs */ 695c2653865SAlexander Duyck for (i = 0; i < num_vfs; i++) { 696c2653865SAlexander Duyck /* record index for VF queue 0 for use in end of loop */ 697c2653865SAlexander Duyck vf_q_idx0 = vf_q_idx; 698c2653865SAlexander Duyck 699c2653865SAlexander Duyck for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { 700c2653865SAlexander Duyck /* assign VF and locked TC to queues */ 701c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 702c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), 703c2653865SAlexander Duyck (i << FM10K_TXQCTL_TC_SHIFT) | i | 704c2653865SAlexander Duyck FM10K_TXQCTL_VF | vid); 705c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), 706c2653865SAlexander Duyck FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 707c2653865SAlexander Duyck FM10K_RXDCTL_DROP_ON_EMPTY); 708c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), 709c2653865SAlexander Duyck FM10K_RXQCTL_VF | 710c2653865SAlexander Duyck (i << FM10K_RXQCTL_VF_SHIFT)); 711c2653865SAlexander Duyck 712c2653865SAlexander Duyck /* map queue pair to VF */ 713c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 714c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); 715c2653865SAlexander Duyck } 716c2653865SAlexander Duyck 717c2653865SAlexander Duyck /* repeat the first ring for all of the remaining VF rings */ 718c2653865SAlexander Duyck for (; j < qmap_stride; j++, qmap_idx++) { 719c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); 720c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); 721c2653865SAlexander Duyck } 722c2653865SAlexander Duyck } 723c2653865SAlexander Duyck 724c2653865SAlexander Duyck /* loop through remaining indexes assigning all to queue 0 */ 725c2653865SAlexander Duyck while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { 726c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 727c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); 728c2653865SAlexander Duyck qmap_idx++; 729c2653865SAlexander Duyck } 730c2653865SAlexander Duyck 731c2653865SAlexander Duyck return 0; 732c2653865SAlexander Duyck } 733c2653865SAlexander Duyck 734c2653865SAlexander Duyck /** 735c2653865SAlexander Duyck * fm10k_iov_configure_tc_pf - Configure the shaping group for VF 736c2653865SAlexander Duyck * @hw: pointer to the HW structure 737c2653865SAlexander Duyck * @vf_idx: index of VF receiving GLORT 738c2653865SAlexander Duyck * @rate: Rate indicated in Mb/s 739c2653865SAlexander Duyck * 740c2653865SAlexander Duyck * Configured the TC for a given VF to allow only up to a given number 741c2653865SAlexander Duyck * of Mb/s of outgoing Tx throughput. 742c2653865SAlexander Duyck **/ 743c2653865SAlexander Duyck static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) 744c2653865SAlexander Duyck { 745c2653865SAlexander Duyck /* configure defaults */ 746c2653865SAlexander Duyck u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; 747c2653865SAlexander Duyck u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; 748c2653865SAlexander Duyck 749c2653865SAlexander Duyck /* verify vf is in range */ 750c2653865SAlexander Duyck if (vf_idx >= hw->iov.num_vfs) 751c2653865SAlexander Duyck return FM10K_ERR_PARAM; 752c2653865SAlexander Duyck 753c2653865SAlexander Duyck /* set interval to align with 4.096 usec in all modes */ 754c2653865SAlexander Duyck switch (hw->bus.speed) { 755c2653865SAlexander Duyck case fm10k_bus_speed_2500: 756c2653865SAlexander Duyck interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; 757c2653865SAlexander Duyck break; 758c2653865SAlexander Duyck case fm10k_bus_speed_5000: 759c2653865SAlexander Duyck interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; 760c2653865SAlexander Duyck break; 761c2653865SAlexander Duyck default: 762c2653865SAlexander Duyck break; 763c2653865SAlexander Duyck } 764c2653865SAlexander Duyck 765c2653865SAlexander Duyck if (rate) { 766c2653865SAlexander Duyck if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) 767c2653865SAlexander Duyck return FM10K_ERR_PARAM; 768c2653865SAlexander Duyck 769c2653865SAlexander Duyck /* The quanta is measured in Bytes per 4.096 or 8.192 usec 770c2653865SAlexander Duyck * The rate is provided in Mbits per second 771c2653865SAlexander Duyck * To tralslate from rate to quanta we need to multiply the 772c2653865SAlexander Duyck * rate by 8.192 usec and divide by 8 bits/byte. To avoid 773c2653865SAlexander Duyck * dealing with floating point we can round the values up 774c2653865SAlexander Duyck * to the nearest whole number ratio which gives us 128 / 125. 775c2653865SAlexander Duyck */ 776c2653865SAlexander Duyck tc_rate = (rate * 128) / 125; 777c2653865SAlexander Duyck 778c2653865SAlexander Duyck /* try to keep the rate limiting accurate by increasing 779c2653865SAlexander Duyck * the number of credits and interval for rates less than 4Gb/s 780c2653865SAlexander Duyck */ 781c2653865SAlexander Duyck if (rate < 4000) 782c2653865SAlexander Duyck interval <<= 1; 783c2653865SAlexander Duyck else 784c2653865SAlexander Duyck tc_rate >>= 1; 785c2653865SAlexander Duyck } 786c2653865SAlexander Duyck 787c2653865SAlexander Duyck /* update rate limiter with new values */ 788c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); 789c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 790c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); 791c2653865SAlexander Duyck 792c2653865SAlexander Duyck return 0; 793c2653865SAlexander Duyck } 794c2653865SAlexander Duyck 795c2653865SAlexander Duyck /** 796c2653865SAlexander Duyck * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list 797c2653865SAlexander Duyck * @hw: pointer to the HW structure 798c2653865SAlexander Duyck * @vf_idx: index of VF receiving GLORT 799c2653865SAlexander Duyck * 800c2653865SAlexander Duyck * Update the interrupt moderator linked list to include any MSI-X 801c2653865SAlexander Duyck * interrupts which the VF has enabled in the MSI-X vector table. 802c2653865SAlexander Duyck **/ 803c2653865SAlexander Duyck static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) 804c2653865SAlexander Duyck { 805c2653865SAlexander Duyck u16 vf_v_idx, vf_v_limit, i; 806c2653865SAlexander Duyck 807c2653865SAlexander Duyck /* verify vf is in range */ 808c2653865SAlexander Duyck if (vf_idx >= hw->iov.num_vfs) 809c2653865SAlexander Duyck return FM10K_ERR_PARAM; 810c2653865SAlexander Duyck 811c2653865SAlexander Duyck /* determine vector offset and count */ 812c2653865SAlexander Duyck vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 813c2653865SAlexander Duyck vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 814c2653865SAlexander Duyck 815c2653865SAlexander Duyck /* search for first vector that is not masked */ 816c2653865SAlexander Duyck for (i = vf_v_limit - 1; i > vf_v_idx; i--) { 817c2653865SAlexander Duyck if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) 818c2653865SAlexander Duyck break; 819c2653865SAlexander Duyck } 820c2653865SAlexander Duyck 821c2653865SAlexander Duyck /* reset linked list so it now includes our active vectors */ 822c2653865SAlexander Duyck if (vf_idx == (hw->iov.num_vfs - 1)) 823c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), i); 824c2653865SAlexander Duyck else 825c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); 826c2653865SAlexander Duyck 827c2653865SAlexander Duyck return 0; 828c2653865SAlexander Duyck } 829c2653865SAlexander Duyck 830c2653865SAlexander Duyck /** 831c2653865SAlexander Duyck * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF 832c2653865SAlexander Duyck * @hw: pointer to the HW structure 833c2653865SAlexander Duyck * @vf_info: pointer to VF information structure 834c2653865SAlexander Duyck * 835c2653865SAlexander Duyck * Assign a MAC address and default VLAN to a VF and notify it of the update 836c2653865SAlexander Duyck **/ 837c2653865SAlexander Duyck static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, 838c2653865SAlexander Duyck struct fm10k_vf_info *vf_info) 839c2653865SAlexander Duyck { 840c2653865SAlexander Duyck u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; 841c2653865SAlexander Duyck u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; 842c2653865SAlexander Duyck s32 err = 0; 843c2653865SAlexander Duyck u16 vf_idx, vf_vid; 844c2653865SAlexander Duyck 845c2653865SAlexander Duyck /* verify vf is in range */ 846c2653865SAlexander Duyck if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) 847c2653865SAlexander Duyck return FM10K_ERR_PARAM; 848c2653865SAlexander Duyck 849c2653865SAlexander Duyck /* determine qmap offsets and counts */ 850c2653865SAlexander Duyck qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 851c2653865SAlexander Duyck queues_per_pool = fm10k_queues_per_pool(hw); 852c2653865SAlexander Duyck 853c2653865SAlexander Duyck /* calculate starting index for queues */ 854c2653865SAlexander Duyck vf_idx = vf_info->vf_idx; 855c2653865SAlexander Duyck vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 856c2653865SAlexander Duyck qmap_idx = qmap_stride * vf_idx; 857c2653865SAlexander Duyck 858c2653865SAlexander Duyck /* MAP Tx queue back to 0 temporarily, and disable it */ 859c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); 860c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); 861c2653865SAlexander Duyck 862c2653865SAlexander Duyck /* determine correct default VLAN ID */ 863c2653865SAlexander Duyck if (vf_info->pf_vid) 864c2653865SAlexander Duyck vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR; 865c2653865SAlexander Duyck else 866c2653865SAlexander Duyck vf_vid = vf_info->sw_vid; 867c2653865SAlexander Duyck 868c2653865SAlexander Duyck /* generate MAC_ADDR request */ 869c2653865SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); 870c2653865SAlexander Duyck fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, 871c2653865SAlexander Duyck vf_info->mac, vf_vid); 872c2653865SAlexander Duyck 873c2653865SAlexander Duyck /* load onto outgoing mailbox, ignore any errors on enqueue */ 874c2653865SAlexander Duyck if (vf_info->mbx.ops.enqueue_tx) 875c2653865SAlexander Duyck vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 876c2653865SAlexander Duyck 877c2653865SAlexander Duyck /* verify ring has disabled before modifying base address registers */ 878c2653865SAlexander Duyck txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 879c2653865SAlexander Duyck for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { 880c2653865SAlexander Duyck /* limit ourselves to a 1ms timeout */ 881c2653865SAlexander Duyck if (timeout == 10) { 882c2653865SAlexander Duyck err = FM10K_ERR_DMA_PENDING; 883c2653865SAlexander Duyck goto err_out; 884c2653865SAlexander Duyck } 885c2653865SAlexander Duyck 886c2653865SAlexander Duyck usleep_range(100, 200); 887c2653865SAlexander Duyck txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); 888c2653865SAlexander Duyck } 889c2653865SAlexander Duyck 890c2653865SAlexander Duyck /* Update base address registers to contain MAC address */ 891c2653865SAlexander Duyck if (is_valid_ether_addr(vf_info->mac)) { 892c2653865SAlexander Duyck tdbal = (((u32)vf_info->mac[3]) << 24) | 893c2653865SAlexander Duyck (((u32)vf_info->mac[4]) << 16) | 894c2653865SAlexander Duyck (((u32)vf_info->mac[5]) << 8); 895c2653865SAlexander Duyck 896c2653865SAlexander Duyck tdbah = (((u32)0xFF) << 24) | 897c2653865SAlexander Duyck (((u32)vf_info->mac[0]) << 16) | 898c2653865SAlexander Duyck (((u32)vf_info->mac[1]) << 8) | 899c2653865SAlexander Duyck ((u32)vf_info->mac[2]); 900c2653865SAlexander Duyck } 901c2653865SAlexander Duyck 902c2653865SAlexander Duyck /* Record the base address into queue 0 */ 903c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); 904c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); 905c2653865SAlexander Duyck 906c2653865SAlexander Duyck err_out: 907c2653865SAlexander Duyck /* configure Queue control register */ 908c2653865SAlexander Duyck txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & 909c2653865SAlexander Duyck FM10K_TXQCTL_VID_MASK; 910c2653865SAlexander Duyck txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 911c2653865SAlexander Duyck FM10K_TXQCTL_VF | vf_idx; 912c2653865SAlexander Duyck 913c2653865SAlexander Duyck /* assign VID */ 914c2653865SAlexander Duyck for (i = 0; i < queues_per_pool; i++) 915c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); 916c2653865SAlexander Duyck 917c2653865SAlexander Duyck /* restore the queue back to VF ownership */ 918c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); 919c2653865SAlexander Duyck return err; 920c2653865SAlexander Duyck } 921c2653865SAlexander Duyck 922c2653865SAlexander Duyck /** 923c2653865SAlexander Duyck * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF 924c2653865SAlexander Duyck * @hw: pointer to the HW structure 925c2653865SAlexander Duyck * @vf_info: pointer to VF information structure 926c2653865SAlexander Duyck * 927c2653865SAlexander Duyck * Reassign the interrupts and queues to a VF following an FLR 928c2653865SAlexander Duyck **/ 929c2653865SAlexander Duyck static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, 930c2653865SAlexander Duyck struct fm10k_vf_info *vf_info) 931c2653865SAlexander Duyck { 932c2653865SAlexander Duyck u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; 933c2653865SAlexander Duyck u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; 934c2653865SAlexander Duyck u16 vf_v_idx, vf_v_limit, vf_vid; 935c2653865SAlexander Duyck u8 vf_idx = vf_info->vf_idx; 936c2653865SAlexander Duyck int i; 937c2653865SAlexander Duyck 938c2653865SAlexander Duyck /* verify vf is in range */ 939c2653865SAlexander Duyck if (vf_idx >= hw->iov.num_vfs) 940c2653865SAlexander Duyck return FM10K_ERR_PARAM; 941c2653865SAlexander Duyck 942c2653865SAlexander Duyck /* clear event notification of VF FLR */ 943c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32)); 944c2653865SAlexander Duyck 945c2653865SAlexander Duyck /* force timeout and then disconnect the mailbox */ 946c2653865SAlexander Duyck vf_info->mbx.timeout = 0; 947c2653865SAlexander Duyck if (vf_info->mbx.ops.disconnect) 948c2653865SAlexander Duyck vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); 949c2653865SAlexander Duyck 950c2653865SAlexander Duyck /* determine vector offset and count */ 951c2653865SAlexander Duyck vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); 952c2653865SAlexander Duyck vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); 953c2653865SAlexander Duyck 954c2653865SAlexander Duyck /* determine qmap offsets and counts */ 955c2653865SAlexander Duyck qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; 956c2653865SAlexander Duyck queues_per_pool = fm10k_queues_per_pool(hw); 957c2653865SAlexander Duyck qmap_idx = qmap_stride * vf_idx; 958c2653865SAlexander Duyck 959c2653865SAlexander Duyck /* make all the queues inaccessible to the VF */ 960c2653865SAlexander Duyck for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { 961c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(i), 0); 962c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(i), 0); 963c2653865SAlexander Duyck } 964c2653865SAlexander Duyck 965c2653865SAlexander Duyck /* calculate starting index for queues */ 966c2653865SAlexander Duyck vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); 967c2653865SAlexander Duyck 968c2653865SAlexander Duyck /* determine correct default VLAN ID */ 969c2653865SAlexander Duyck if (vf_info->pf_vid) 970c2653865SAlexander Duyck vf_vid = vf_info->pf_vid; 971c2653865SAlexander Duyck else 972c2653865SAlexander Duyck vf_vid = vf_info->sw_vid; 973c2653865SAlexander Duyck 974c2653865SAlexander Duyck /* configure Queue control register */ 975c2653865SAlexander Duyck txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | 976c2653865SAlexander Duyck (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 977c2653865SAlexander Duyck FM10K_TXQCTL_VF | vf_idx; 978c2653865SAlexander Duyck rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT); 979c2653865SAlexander Duyck 980c2653865SAlexander Duyck /* stop further DMA and reset queue ownership back to VF */ 981c2653865SAlexander Duyck for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { 982c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); 983c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); 984c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RXDCTL(i), 985c2653865SAlexander Duyck FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | 986c2653865SAlexander Duyck FM10K_RXDCTL_DROP_ON_EMPTY); 987c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); 988c2653865SAlexander Duyck } 989c2653865SAlexander Duyck 990c2653865SAlexander Duyck /* reset TC with -1 credits and no quanta to prevent transmit */ 991c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); 992c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); 993c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), 994c2653865SAlexander Duyck FM10K_TC_CREDIT_CREDIT_MASK); 995c2653865SAlexander Duyck 996c2653865SAlexander Duyck /* update our first entry in the table based on previous VF */ 997c2653865SAlexander Duyck if (!vf_idx) 998c2653865SAlexander Duyck hw->mac.ops.update_int_moderator(hw); 999c2653865SAlexander Duyck else 1000c2653865SAlexander Duyck hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); 1001c2653865SAlexander Duyck 1002c2653865SAlexander Duyck /* reset linked list so it now includes our active vectors */ 1003c2653865SAlexander Duyck if (vf_idx == (hw->iov.num_vfs - 1)) 1004c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); 1005c2653865SAlexander Duyck else 1006c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); 1007c2653865SAlexander Duyck 1008c2653865SAlexander Duyck /* link remaining vectors so that next points to previous */ 1009c2653865SAlexander Duyck for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) 1010c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); 1011c2653865SAlexander Duyck 1012c2653865SAlexander Duyck /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ 1013c2653865SAlexander Duyck for (i = FM10K_VFMBMEM_LEN; i--;) 1014c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); 1015c2653865SAlexander Duyck for (i = FM10K_VLAN_TABLE_SIZE; i--;) 1016c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); 1017c2653865SAlexander Duyck for (i = FM10K_RETA_SIZE; i--;) 1018c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); 1019c2653865SAlexander Duyck for (i = FM10K_RSSRK_SIZE; i--;) 1020c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); 1021c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); 1022c2653865SAlexander Duyck 1023c2653865SAlexander Duyck /* Update base address registers to contain MAC address */ 1024c2653865SAlexander Duyck if (is_valid_ether_addr(vf_info->mac)) { 1025c2653865SAlexander Duyck tdbal = (((u32)vf_info->mac[3]) << 24) | 1026c2653865SAlexander Duyck (((u32)vf_info->mac[4]) << 16) | 1027c2653865SAlexander Duyck (((u32)vf_info->mac[5]) << 8); 1028c2653865SAlexander Duyck tdbah = (((u32)0xFF) << 24) | 1029c2653865SAlexander Duyck (((u32)vf_info->mac[0]) << 16) | 1030c2653865SAlexander Duyck (((u32)vf_info->mac[1]) << 8) | 1031c2653865SAlexander Duyck ((u32)vf_info->mac[2]); 1032c2653865SAlexander Duyck } 1033c2653865SAlexander Duyck 1034c2653865SAlexander Duyck /* map queue pairs back to VF from last to first */ 1035c2653865SAlexander Duyck for (i = queues_per_pool; i--;) { 1036c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); 1037c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); 1038c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); 1039c2653865SAlexander Duyck fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); 1040c2653865SAlexander Duyck } 1041c2653865SAlexander Duyck 1042fba341d5SJacob Keller /* repeat the first ring for all the remaining VF rings */ 1043fba341d5SJacob Keller for (i = queues_per_pool; i < qmap_stride; i++) { 1044fba341d5SJacob Keller fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); 1045fba341d5SJacob Keller fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); 1046fba341d5SJacob Keller } 1047fba341d5SJacob Keller 1048c2653865SAlexander Duyck return 0; 1049c2653865SAlexander Duyck } 1050c2653865SAlexander Duyck 1051c2653865SAlexander Duyck /** 1052c2653865SAlexander Duyck * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF 1053c2653865SAlexander Duyck * @hw: pointer to hardware structure 1054c2653865SAlexander Duyck * @vf_info: pointer to VF information structure 1055c2653865SAlexander Duyck * @lport_idx: Logical port offset from the hardware glort 1056c2653865SAlexander Duyck * @flags: Set of capability flags to extend port beyond basic functionality 1057c2653865SAlexander Duyck * 1058c2653865SAlexander Duyck * This function allows enabling a VF port by assigning it a GLORT and 1059c2653865SAlexander Duyck * setting the flags so that it can enable an Rx mode. 1060c2653865SAlexander Duyck **/ 1061c2653865SAlexander Duyck static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, 1062c2653865SAlexander Duyck struct fm10k_vf_info *vf_info, 1063c2653865SAlexander Duyck u16 lport_idx, u8 flags) 1064c2653865SAlexander Duyck { 1065c2653865SAlexander Duyck u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; 1066c2653865SAlexander Duyck 1067c2653865SAlexander Duyck /* if glort is not valid return error */ 1068c2653865SAlexander Duyck if (!fm10k_glort_valid_pf(hw, glort)) 1069c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1070c2653865SAlexander Duyck 1071c2653865SAlexander Duyck vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; 1072c2653865SAlexander Duyck vf_info->glort = glort; 1073c2653865SAlexander Duyck 1074c2653865SAlexander Duyck return 0; 1075c2653865SAlexander Duyck } 1076c2653865SAlexander Duyck 1077c2653865SAlexander Duyck /** 1078c2653865SAlexander Duyck * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF 1079c2653865SAlexander Duyck * @hw: pointer to hardware structure 1080c2653865SAlexander Duyck * @vf_info: pointer to VF information structure 1081c2653865SAlexander Duyck * 1082c2653865SAlexander Duyck * This function disables a VF port by stripping it of a GLORT and 1083c2653865SAlexander Duyck * setting the flags so that it cannot enable any Rx mode. 1084c2653865SAlexander Duyck **/ 1085c2653865SAlexander Duyck static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, 1086c2653865SAlexander Duyck struct fm10k_vf_info *vf_info) 1087c2653865SAlexander Duyck { 1088c2653865SAlexander Duyck u32 msg[1]; 1089c2653865SAlexander Duyck 1090c2653865SAlexander Duyck /* need to disable the port if it is already enabled */ 1091c2653865SAlexander Duyck if (FM10K_VF_FLAG_ENABLED(vf_info)) { 1092c2653865SAlexander Duyck /* notify switch that this port has been disabled */ 1093c2653865SAlexander Duyck fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); 1094c2653865SAlexander Duyck 1095c2653865SAlexander Duyck /* generate port state response to notify VF it is not ready */ 1096c2653865SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1097c2653865SAlexander Duyck vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 1098c2653865SAlexander Duyck } 1099c2653865SAlexander Duyck 1100c2653865SAlexander Duyck /* clear flags and glort if it exists */ 1101c2653865SAlexander Duyck vf_info->vf_flags = 0; 1102c2653865SAlexander Duyck vf_info->glort = 0; 1103c2653865SAlexander Duyck } 1104c2653865SAlexander Duyck 1105c2653865SAlexander Duyck /** 1106c2653865SAlexander Duyck * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs 1107c2653865SAlexander Duyck * @hw: pointer to hardware structure 1108c2653865SAlexander Duyck * @q: stats for all queues of a VF 1109c2653865SAlexander Duyck * @vf_idx: index of VF 1110c2653865SAlexander Duyck * 1111c2653865SAlexander Duyck * This function collects queue stats for VFs. 1112c2653865SAlexander Duyck **/ 1113c2653865SAlexander Duyck static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, 1114c2653865SAlexander Duyck struct fm10k_hw_stats_q *q, 1115c2653865SAlexander Duyck u16 vf_idx) 1116c2653865SAlexander Duyck { 1117c2653865SAlexander Duyck u32 idx, qpp; 1118c2653865SAlexander Duyck 1119c2653865SAlexander Duyck /* get stats for all of the queues */ 1120c2653865SAlexander Duyck qpp = fm10k_queues_per_pool(hw); 1121c2653865SAlexander Duyck idx = fm10k_vf_queue_index(hw, vf_idx); 1122c2653865SAlexander Duyck fm10k_update_hw_stats_q(hw, q, idx, qpp); 1123c2653865SAlexander Duyck } 1124c2653865SAlexander Duyck 11255f226ddbSAlexander Duyck static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw, 11265f226ddbSAlexander Duyck struct fm10k_vf_info *vf_info, 11275f226ddbSAlexander Duyck u64 timestamp) 11285f226ddbSAlexander Duyck { 11295f226ddbSAlexander Duyck u32 msg[4]; 11305f226ddbSAlexander Duyck 11315f226ddbSAlexander Duyck /* generate port state response to notify VF it is not ready */ 11325f226ddbSAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588); 11335f226ddbSAlexander Duyck fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp); 11345f226ddbSAlexander Duyck 11355f226ddbSAlexander Duyck return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); 11365f226ddbSAlexander Duyck } 11375f226ddbSAlexander Duyck 1138c2653865SAlexander Duyck /** 1139c2653865SAlexander Duyck * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF 1140c2653865SAlexander Duyck * @hw: Pointer to hardware structure 1141c2653865SAlexander Duyck * @results: Pointer array to message, results[0] is pointer to message 1142c2653865SAlexander Duyck * @mbx: Pointer to mailbox information structure 1143c2653865SAlexander Duyck * 1144c2653865SAlexander Duyck * This function is a default handler for MSI-X requests from the VF. The 1145c2653865SAlexander Duyck * assumption is that in this case it is acceptable to just directly 1146eca32047SMatthew Vick * hand off the message from the VF to the underlying shared code. 1147c2653865SAlexander Duyck **/ 1148c2653865SAlexander Duyck s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, 1149c2653865SAlexander Duyck struct fm10k_mbx_info *mbx) 1150c2653865SAlexander Duyck { 1151c2653865SAlexander Duyck struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1152c2653865SAlexander Duyck u8 vf_idx = vf_info->vf_idx; 1153c2653865SAlexander Duyck 1154c2653865SAlexander Duyck return hw->iov.ops.assign_int_moderator(hw, vf_idx); 1155c2653865SAlexander Duyck } 1156c2653865SAlexander Duyck 1157c2653865SAlexander Duyck /** 1158c2653865SAlexander Duyck * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF 1159c2653865SAlexander Duyck * @hw: Pointer to hardware structure 1160c2653865SAlexander Duyck * @results: Pointer array to message, results[0] is pointer to message 1161c2653865SAlexander Duyck * @mbx: Pointer to mailbox information structure 1162c2653865SAlexander Duyck * 1163c2653865SAlexander Duyck * This function is a default handler for MAC/VLAN requests from the VF. 1164c2653865SAlexander Duyck * The assumption is that in this case it is acceptable to just directly 1165eca32047SMatthew Vick * hand off the message from the VF to the underlying shared code. 1166c2653865SAlexander Duyck **/ 1167c2653865SAlexander Duyck s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, 1168c2653865SAlexander Duyck struct fm10k_mbx_info *mbx) 1169c2653865SAlexander Duyck { 1170c2653865SAlexander Duyck struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1171c2653865SAlexander Duyck int err = 0; 1172c2653865SAlexander Duyck u8 mac[ETH_ALEN]; 1173c2653865SAlexander Duyck u32 *result; 1174c2653865SAlexander Duyck u16 vlan; 1175c2653865SAlexander Duyck u32 vid; 1176c2653865SAlexander Duyck 1177c2653865SAlexander Duyck /* we shouldn't be updating rules on a disabled interface */ 1178c2653865SAlexander Duyck if (!FM10K_VF_FLAG_ENABLED(vf_info)) 1179c2653865SAlexander Duyck err = FM10K_ERR_PARAM; 1180c2653865SAlexander Duyck 1181c2653865SAlexander Duyck if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { 1182c2653865SAlexander Duyck result = results[FM10K_MAC_VLAN_MSG_VLAN]; 1183c2653865SAlexander Duyck 1184c2653865SAlexander Duyck /* record VLAN id requested */ 1185c2653865SAlexander Duyck err = fm10k_tlv_attr_get_u32(result, &vid); 1186c2653865SAlexander Duyck if (err) 1187c2653865SAlexander Duyck return err; 1188c2653865SAlexander Duyck 1189c2653865SAlexander Duyck /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ 1190c2653865SAlexander Duyck if (!vid || (vid == FM10K_VLAN_CLEAR)) { 1191c2653865SAlexander Duyck if (vf_info->pf_vid) 1192c2653865SAlexander Duyck vid |= vf_info->pf_vid; 1193c2653865SAlexander Duyck else 1194c2653865SAlexander Duyck vid |= vf_info->sw_vid; 1195c2653865SAlexander Duyck } else if (vid != vf_info->pf_vid) { 1196c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1197c2653865SAlexander Duyck } 1198c2653865SAlexander Duyck 1199c2653865SAlexander Duyck /* update VSI info for VF in regards to VLAN table */ 1200c2653865SAlexander Duyck err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, 1201c2653865SAlexander Duyck !(vid & FM10K_VLAN_CLEAR)); 1202c2653865SAlexander Duyck } 1203c2653865SAlexander Duyck 1204c2653865SAlexander Duyck if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { 1205c2653865SAlexander Duyck result = results[FM10K_MAC_VLAN_MSG_MAC]; 1206c2653865SAlexander Duyck 1207c2653865SAlexander Duyck /* record unicast MAC address requested */ 1208c2653865SAlexander Duyck err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1209c2653865SAlexander Duyck if (err) 1210c2653865SAlexander Duyck return err; 1211c2653865SAlexander Duyck 1212c2653865SAlexander Duyck /* block attempts to set MAC for a locked device */ 1213c2653865SAlexander Duyck if (is_valid_ether_addr(vf_info->mac) && 1214c2653865SAlexander Duyck memcmp(mac, vf_info->mac, ETH_ALEN)) 1215c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1216c2653865SAlexander Duyck 1217c2653865SAlexander Duyck /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ 1218c2653865SAlexander Duyck if (!vlan || (vlan == FM10K_VLAN_CLEAR)) { 1219c2653865SAlexander Duyck if (vf_info->pf_vid) 1220c2653865SAlexander Duyck vlan |= vf_info->pf_vid; 1221c2653865SAlexander Duyck else 1222c2653865SAlexander Duyck vlan |= vf_info->sw_vid; 1223c2653865SAlexander Duyck } else if (vf_info->pf_vid) { 1224c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1225c2653865SAlexander Duyck } 1226c2653865SAlexander Duyck 1227c2653865SAlexander Duyck /* notify switch of request for new unicast address */ 1228c2653865SAlexander Duyck err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan, 1229c2653865SAlexander Duyck !(vlan & FM10K_VLAN_CLEAR), 0); 1230c2653865SAlexander Duyck } 1231c2653865SAlexander Duyck 1232c2653865SAlexander Duyck if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { 1233c2653865SAlexander Duyck result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; 1234c2653865SAlexander Duyck 1235c2653865SAlexander Duyck /* record multicast MAC address requested */ 1236c2653865SAlexander Duyck err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); 1237c2653865SAlexander Duyck if (err) 1238c2653865SAlexander Duyck return err; 1239c2653865SAlexander Duyck 1240c2653865SAlexander Duyck /* verify that the VF is allowed to request multicast */ 1241c2653865SAlexander Duyck if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) 1242c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1243c2653865SAlexander Duyck 1244c2653865SAlexander Duyck /* if VLAN ID is 0, set the default VLAN ID instead of 0 */ 1245c2653865SAlexander Duyck if (!vlan || (vlan == FM10K_VLAN_CLEAR)) { 1246c2653865SAlexander Duyck if (vf_info->pf_vid) 1247c2653865SAlexander Duyck vlan |= vf_info->pf_vid; 1248c2653865SAlexander Duyck else 1249c2653865SAlexander Duyck vlan |= vf_info->sw_vid; 1250c2653865SAlexander Duyck } else if (vf_info->pf_vid) { 1251c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1252c2653865SAlexander Duyck } 1253c2653865SAlexander Duyck 1254c2653865SAlexander Duyck /* notify switch of request for new multicast address */ 1255b32d15b9SJeff Kirsher err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac, vlan, 1256b32d15b9SJeff Kirsher !(vlan & FM10K_VLAN_CLEAR)); 1257c2653865SAlexander Duyck } 1258c2653865SAlexander Duyck 1259c2653865SAlexander Duyck return err; 1260c2653865SAlexander Duyck } 1261c2653865SAlexander Duyck 1262c2653865SAlexander Duyck /** 1263c2653865SAlexander Duyck * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode 1264c2653865SAlexander Duyck * @vf_info: VF info structure containing capability flags 1265c2653865SAlexander Duyck * @mode: Requested xcast mode 1266c2653865SAlexander Duyck * 1267c2653865SAlexander Duyck * This function outputs the mode that most closely matches the requested 1268c2653865SAlexander Duyck * mode. If not modes match it will request we disable the port 1269c2653865SAlexander Duyck **/ 1270c2653865SAlexander Duyck static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, 1271c2653865SAlexander Duyck u8 mode) 1272c2653865SAlexander Duyck { 1273c2653865SAlexander Duyck u8 vf_flags = vf_info->vf_flags; 1274c2653865SAlexander Duyck 1275c2653865SAlexander Duyck /* match up mode to capabilities as best as possible */ 1276c2653865SAlexander Duyck switch (mode) { 1277c2653865SAlexander Duyck case FM10K_XCAST_MODE_PROMISC: 1278c2653865SAlexander Duyck if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) 1279c2653865SAlexander Duyck return FM10K_XCAST_MODE_PROMISC; 1280c2653865SAlexander Duyck /* fallthough */ 1281c2653865SAlexander Duyck case FM10K_XCAST_MODE_ALLMULTI: 1282c2653865SAlexander Duyck if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) 1283c2653865SAlexander Duyck return FM10K_XCAST_MODE_ALLMULTI; 1284c2653865SAlexander Duyck /* fallthough */ 1285c2653865SAlexander Duyck case FM10K_XCAST_MODE_MULTI: 1286c2653865SAlexander Duyck if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) 1287c2653865SAlexander Duyck return FM10K_XCAST_MODE_MULTI; 1288c2653865SAlexander Duyck /* fallthough */ 1289c2653865SAlexander Duyck case FM10K_XCAST_MODE_NONE: 1290c2653865SAlexander Duyck if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) 1291c2653865SAlexander Duyck return FM10K_XCAST_MODE_NONE; 1292c2653865SAlexander Duyck /* fallthough */ 1293c2653865SAlexander Duyck default: 1294c2653865SAlexander Duyck break; 1295c2653865SAlexander Duyck } 1296c2653865SAlexander Duyck 1297c2653865SAlexander Duyck /* disable interface as it should not be able to request any */ 1298c2653865SAlexander Duyck return FM10K_XCAST_MODE_DISABLE; 1299c2653865SAlexander Duyck } 1300c2653865SAlexander Duyck 1301c2653865SAlexander Duyck /** 1302c2653865SAlexander Duyck * fm10k_iov_msg_lport_state_pf - Message handler for port state requests 1303c2653865SAlexander Duyck * @hw: Pointer to hardware structure 1304c2653865SAlexander Duyck * @results: Pointer array to message, results[0] is pointer to message 1305c2653865SAlexander Duyck * @mbx: Pointer to mailbox information structure 1306c2653865SAlexander Duyck * 1307c2653865SAlexander Duyck * This function is a default handler for port state requests. The port 1308c2653865SAlexander Duyck * state requests for now are basic and consist of enabling or disabling 1309c2653865SAlexander Duyck * the port. 1310c2653865SAlexander Duyck **/ 1311c2653865SAlexander Duyck s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, 1312c2653865SAlexander Duyck struct fm10k_mbx_info *mbx) 1313c2653865SAlexander Duyck { 1314c2653865SAlexander Duyck struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; 1315c2653865SAlexander Duyck u32 *result; 1316c2653865SAlexander Duyck s32 err = 0; 1317c2653865SAlexander Duyck u32 msg[2]; 1318c2653865SAlexander Duyck u8 mode = 0; 1319c2653865SAlexander Duyck 1320c2653865SAlexander Duyck /* verify VF is allowed to enable even minimal mode */ 1321c2653865SAlexander Duyck if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) 1322c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1323c2653865SAlexander Duyck 1324c2653865SAlexander Duyck if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { 1325c2653865SAlexander Duyck result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; 1326c2653865SAlexander Duyck 1327c2653865SAlexander Duyck /* XCAST mode update requested */ 1328c2653865SAlexander Duyck err = fm10k_tlv_attr_get_u8(result, &mode); 1329c2653865SAlexander Duyck if (err) 1330c2653865SAlexander Duyck return FM10K_ERR_PARAM; 1331c2653865SAlexander Duyck 1332c2653865SAlexander Duyck /* prep for possible demotion depending on capabilities */ 1333c2653865SAlexander Duyck mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); 1334c2653865SAlexander Duyck 1335c2653865SAlexander Duyck /* if mode is not currently enabled, enable it */ 1336c2653865SAlexander Duyck if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode))) 1337c2653865SAlexander Duyck fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); 1338c2653865SAlexander Duyck 1339c2653865SAlexander Duyck /* swap mode back to a bit flag */ 1340c2653865SAlexander Duyck mode = FM10K_VF_FLAG_SET_MODE(mode); 1341c2653865SAlexander Duyck } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { 1342c2653865SAlexander Duyck /* need to disable the port if it is already enabled */ 1343c2653865SAlexander Duyck if (FM10K_VF_FLAG_ENABLED(vf_info)) 1344c2653865SAlexander Duyck err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1345c2653865SAlexander Duyck 1, false); 1346c2653865SAlexander Duyck 1347ee4373e7SJacob Keller /* we need to clear VF_FLAG_ENABLED flags in order to ensure 1348ee4373e7SJacob Keller * that we actually re-enable the LPORT state below. Note that 1349ee4373e7SJacob Keller * this has no impact if the VF is already disabled, as the 1350ee4373e7SJacob Keller * flags are already cleared. 1351ee4373e7SJacob Keller */ 1352ee4373e7SJacob Keller if (!err) 1353ee4373e7SJacob Keller vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info); 1354ee4373e7SJacob Keller 1355c2653865SAlexander Duyck /* when enabling the port we should reset the rate limiters */ 1356c2653865SAlexander Duyck hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); 1357c2653865SAlexander Duyck 1358c2653865SAlexander Duyck /* set mode for minimal functionality */ 1359c2653865SAlexander Duyck mode = FM10K_VF_FLAG_SET_MODE_NONE; 1360c2653865SAlexander Duyck 1361c2653865SAlexander Duyck /* generate port state response to notify VF it is ready */ 1362c2653865SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); 1363c2653865SAlexander Duyck fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); 1364c2653865SAlexander Duyck mbx->ops.enqueue_tx(hw, mbx, msg); 1365c2653865SAlexander Duyck } 1366c2653865SAlexander Duyck 1367c2653865SAlexander Duyck /* if enable state toggled note the update */ 1368c2653865SAlexander Duyck if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) 1369c2653865SAlexander Duyck err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, 1370c2653865SAlexander Duyck !!mode); 1371c2653865SAlexander Duyck 1372c2653865SAlexander Duyck /* if state change succeeded, then update our stored state */ 1373c2653865SAlexander Duyck mode |= FM10K_VF_FLAG_CAPABLE(vf_info); 1374c2653865SAlexander Duyck if (!err) 1375c2653865SAlexander Duyck vf_info->vf_flags = mode; 1376c2653865SAlexander Duyck 1377c2653865SAlexander Duyck return err; 1378c2653865SAlexander Duyck } 1379c2653865SAlexander Duyck 1380c2653865SAlexander Duyck const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = { 1381c2653865SAlexander Duyck FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test), 1382c2653865SAlexander Duyck FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf), 1383c2653865SAlexander Duyck FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf), 1384c2653865SAlexander Duyck FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf), 1385c2653865SAlexander Duyck FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), 1386c2653865SAlexander Duyck }; 1387c2653865SAlexander Duyck 1388401b5383SAlexander Duyck /** 1389b6fec18fSAlexander Duyck * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF 1390b6fec18fSAlexander Duyck * @hw: pointer to hardware structure 1391b6fec18fSAlexander Duyck * @stats: pointer to the stats structure to update 1392b6fec18fSAlexander Duyck * 1393b6fec18fSAlexander Duyck * This function collects and aggregates global and per queue hardware 1394b6fec18fSAlexander Duyck * statistics. 1395b6fec18fSAlexander Duyck **/ 1396b6fec18fSAlexander Duyck static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, 1397b6fec18fSAlexander Duyck struct fm10k_hw_stats *stats) 1398b6fec18fSAlexander Duyck { 1399b6fec18fSAlexander Duyck u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; 1400b6fec18fSAlexander Duyck u32 id, id_prev; 1401b6fec18fSAlexander Duyck 1402b6fec18fSAlexander Duyck /* Use Tx queue 0 as a canary to detect a reset */ 1403b6fec18fSAlexander Duyck id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1404b6fec18fSAlexander Duyck 1405b6fec18fSAlexander Duyck /* Read Global Statistics */ 1406b6fec18fSAlexander Duyck do { 1407b6fec18fSAlexander Duyck timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, 1408b6fec18fSAlexander Duyck &stats->timeout); 1409b6fec18fSAlexander Duyck ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); 1410b6fec18fSAlexander Duyck ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); 1411b6fec18fSAlexander Duyck um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); 1412b6fec18fSAlexander Duyck xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); 1413b6fec18fSAlexander Duyck vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, 1414b6fec18fSAlexander Duyck &stats->vlan_drop); 1415b6fec18fSAlexander Duyck loopback_drop = fm10k_read_hw_stats_32b(hw, 1416b6fec18fSAlexander Duyck FM10K_STATS_LOOPBACK_DROP, 1417b6fec18fSAlexander Duyck &stats->loopback_drop); 1418b6fec18fSAlexander Duyck nodesc_drop = fm10k_read_hw_stats_32b(hw, 1419b6fec18fSAlexander Duyck FM10K_STATS_NODESC_DROP, 1420b6fec18fSAlexander Duyck &stats->nodesc_drop); 1421b6fec18fSAlexander Duyck 1422b6fec18fSAlexander Duyck /* if value has not changed then we have consistent data */ 1423b6fec18fSAlexander Duyck id_prev = id; 1424b6fec18fSAlexander Duyck id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); 1425b6fec18fSAlexander Duyck } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); 1426b6fec18fSAlexander Duyck 1427b6fec18fSAlexander Duyck /* drop non-ID bits and set VALID ID bit */ 1428b6fec18fSAlexander Duyck id &= FM10K_TXQCTL_ID_MASK; 1429b6fec18fSAlexander Duyck id |= FM10K_STAT_VALID; 1430b6fec18fSAlexander Duyck 1431b6fec18fSAlexander Duyck /* Update Global Statistics */ 1432b6fec18fSAlexander Duyck if (stats->stats_idx == id) { 1433b6fec18fSAlexander Duyck stats->timeout.count += timeout; 1434b6fec18fSAlexander Duyck stats->ur.count += ur; 1435b6fec18fSAlexander Duyck stats->ca.count += ca; 1436b6fec18fSAlexander Duyck stats->um.count += um; 1437b6fec18fSAlexander Duyck stats->xec.count += xec; 1438b6fec18fSAlexander Duyck stats->vlan_drop.count += vlan_drop; 1439b6fec18fSAlexander Duyck stats->loopback_drop.count += loopback_drop; 1440b6fec18fSAlexander Duyck stats->nodesc_drop.count += nodesc_drop; 1441b6fec18fSAlexander Duyck } 1442b6fec18fSAlexander Duyck 1443b6fec18fSAlexander Duyck /* Update bases and record current PF id */ 1444b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->timeout, timeout); 1445b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->ur, ur); 1446b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->ca, ca); 1447b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->um, um); 1448b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->xec, xec); 1449b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); 1450b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); 1451b6fec18fSAlexander Duyck fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); 1452b6fec18fSAlexander Duyck stats->stats_idx = id; 1453b6fec18fSAlexander Duyck 1454b6fec18fSAlexander Duyck /* Update Queue Statistics */ 1455b6fec18fSAlexander Duyck fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); 1456b6fec18fSAlexander Duyck } 1457b6fec18fSAlexander Duyck 1458b6fec18fSAlexander Duyck /** 1459b6fec18fSAlexander Duyck * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF 1460b6fec18fSAlexander Duyck * @hw: pointer to hardware structure 1461b6fec18fSAlexander Duyck * @stats: pointer to the stats structure to update 1462b6fec18fSAlexander Duyck * 1463b6fec18fSAlexander Duyck * This function resets the base for global and per queue hardware 1464b6fec18fSAlexander Duyck * statistics. 1465b6fec18fSAlexander Duyck **/ 1466b6fec18fSAlexander Duyck static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, 1467b6fec18fSAlexander Duyck struct fm10k_hw_stats *stats) 1468b6fec18fSAlexander Duyck { 1469b6fec18fSAlexander Duyck /* Unbind Global Statistics */ 1470b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->timeout); 1471b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->ur); 1472b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->ca); 1473b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->um); 1474b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->xec); 1475b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->vlan_drop); 1476b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->loopback_drop); 1477b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); 1478b6fec18fSAlexander Duyck 1479b6fec18fSAlexander Duyck /* Unbind Queue Statistics */ 1480b6fec18fSAlexander Duyck fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); 1481b6fec18fSAlexander Duyck 1482b6fec18fSAlexander Duyck /* Reinitialize bases for all stats */ 1483b6fec18fSAlexander Duyck fm10k_update_hw_stats_pf(hw, stats); 1484b6fec18fSAlexander Duyck } 1485b6fec18fSAlexander Duyck 1486b6fec18fSAlexander Duyck /** 1487401b5383SAlexander Duyck * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system 1488401b5383SAlexander Duyck * @hw: pointer to hardware structure 1489401b5383SAlexander Duyck * @dma_mask: 64 bit DMA mask required for platform 1490401b5383SAlexander Duyck * 1491401b5383SAlexander Duyck * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order 1492401b5383SAlexander Duyck * to limit the access to memory beyond what is physically in the system. 1493401b5383SAlexander Duyck **/ 1494401b5383SAlexander Duyck static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) 1495401b5383SAlexander Duyck { 1496401b5383SAlexander Duyck /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ 1497401b5383SAlexander Duyck u32 phyaddr = (u32)(dma_mask >> 32); 1498401b5383SAlexander Duyck 1499401b5383SAlexander Duyck fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); 1500401b5383SAlexander Duyck } 1501401b5383SAlexander Duyck 1502401b5383SAlexander Duyck /** 1503b6fec18fSAlexander Duyck * fm10k_get_fault_pf - Record a fault in one of the interface units 1504b6fec18fSAlexander Duyck * @hw: pointer to hardware structure 1505b6fec18fSAlexander Duyck * @type: pointer to fault type register offset 1506b6fec18fSAlexander Duyck * @fault: pointer to memory location to record the fault 1507b6fec18fSAlexander Duyck * 1508b6fec18fSAlexander Duyck * Record the fault register contents to the fault data structure and 1509b6fec18fSAlexander Duyck * clear the entry from the register. 1510b6fec18fSAlexander Duyck * 1511b6fec18fSAlexander Duyck * Returns ERR_PARAM if invalid register is specified or no error is present. 1512b6fec18fSAlexander Duyck **/ 1513b6fec18fSAlexander Duyck static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, 1514b6fec18fSAlexander Duyck struct fm10k_fault *fault) 1515b6fec18fSAlexander Duyck { 1516b6fec18fSAlexander Duyck u32 func; 1517b6fec18fSAlexander Duyck 1518b6fec18fSAlexander Duyck /* verify the fault register is in range and is aligned */ 1519b6fec18fSAlexander Duyck switch (type) { 1520b6fec18fSAlexander Duyck case FM10K_PCA_FAULT: 1521b6fec18fSAlexander Duyck case FM10K_THI_FAULT: 1522b6fec18fSAlexander Duyck case FM10K_FUM_FAULT: 1523b6fec18fSAlexander Duyck break; 1524b6fec18fSAlexander Duyck default: 1525b6fec18fSAlexander Duyck return FM10K_ERR_PARAM; 1526b6fec18fSAlexander Duyck } 1527b6fec18fSAlexander Duyck 1528b6fec18fSAlexander Duyck /* only service faults that are valid */ 1529b6fec18fSAlexander Duyck func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); 1530b6fec18fSAlexander Duyck if (!(func & FM10K_FAULT_FUNC_VALID)) 1531b6fec18fSAlexander Duyck return FM10K_ERR_PARAM; 1532b6fec18fSAlexander Duyck 1533b6fec18fSAlexander Duyck /* read remaining fields */ 1534b6fec18fSAlexander Duyck fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); 1535b6fec18fSAlexander Duyck fault->address <<= 32; 1536b6fec18fSAlexander Duyck fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); 1537b6fec18fSAlexander Duyck fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); 1538b6fec18fSAlexander Duyck 1539b6fec18fSAlexander Duyck /* clear valid bit to allow for next error */ 1540b6fec18fSAlexander Duyck fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); 1541b6fec18fSAlexander Duyck 1542b6fec18fSAlexander Duyck /* Record which function triggered the error */ 1543b6fec18fSAlexander Duyck if (func & FM10K_FAULT_FUNC_PF) 1544b6fec18fSAlexander Duyck fault->func = 0; 1545b6fec18fSAlexander Duyck else 1546b6fec18fSAlexander Duyck fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> 1547b6fec18fSAlexander Duyck FM10K_FAULT_FUNC_VF_SHIFT); 1548b6fec18fSAlexander Duyck 1549b6fec18fSAlexander Duyck /* record fault type */ 1550b6fec18fSAlexander Duyck fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; 1551b6fec18fSAlexander Duyck 1552b6fec18fSAlexander Duyck return 0; 1553b6fec18fSAlexander Duyck } 1554b6fec18fSAlexander Duyck 1555401b5383SAlexander Duyck /** 1556401b5383SAlexander Duyck * fm10k_request_lport_map_pf - Request LPORT map from the switch API 1557401b5383SAlexander Duyck * @hw: pointer to hardware structure 1558401b5383SAlexander Duyck * 1559401b5383SAlexander Duyck **/ 1560401b5383SAlexander Duyck static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) 1561401b5383SAlexander Duyck { 1562401b5383SAlexander Duyck struct fm10k_mbx_info *mbx = &hw->mbx; 1563401b5383SAlexander Duyck u32 msg[1]; 1564401b5383SAlexander Duyck 1565401b5383SAlexander Duyck /* issue request asking for LPORT map */ 1566401b5383SAlexander Duyck fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); 1567401b5383SAlexander Duyck 1568401b5383SAlexander Duyck /* load onto outgoing mailbox */ 1569401b5383SAlexander Duyck return mbx->ops.enqueue_tx(hw, mbx, msg); 1570401b5383SAlexander Duyck } 1571401b5383SAlexander Duyck 1572401b5383SAlexander Duyck /** 1573401b5383SAlexander Duyck * fm10k_get_host_state_pf - Returns the state of the switch and mailbox 1574401b5383SAlexander Duyck * @hw: pointer to hardware structure 1575401b5383SAlexander Duyck * @switch_ready: pointer to boolean value that will record switch state 1576401b5383SAlexander Duyck * 1577401b5383SAlexander Duyck * This funciton will check the DMA_CTRL2 register and mailbox in order 1578401b5383SAlexander Duyck * to determine if the switch is ready for the PF to begin requesting 1579401b5383SAlexander Duyck * addresses and mapping traffic to the local interface. 1580401b5383SAlexander Duyck **/ 1581401b5383SAlexander Duyck static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) 1582401b5383SAlexander Duyck { 1583401b5383SAlexander Duyck s32 ret_val = 0; 1584401b5383SAlexander Duyck u32 dma_ctrl2; 1585401b5383SAlexander Duyck 1586eca32047SMatthew Vick /* verify the switch is ready for interaction */ 1587401b5383SAlexander Duyck dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); 1588401b5383SAlexander Duyck if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) 1589401b5383SAlexander Duyck goto out; 1590401b5383SAlexander Duyck 1591401b5383SAlexander Duyck /* retrieve generic host state info */ 1592401b5383SAlexander Duyck ret_val = fm10k_get_host_state_generic(hw, switch_ready); 1593401b5383SAlexander Duyck if (ret_val) 1594401b5383SAlexander Duyck goto out; 1595401b5383SAlexander Duyck 1596401b5383SAlexander Duyck /* interface cannot receive traffic without logical ports */ 1597401b5383SAlexander Duyck if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) 1598401b5383SAlexander Duyck ret_val = fm10k_request_lport_map_pf(hw); 1599401b5383SAlexander Duyck 1600401b5383SAlexander Duyck out: 1601401b5383SAlexander Duyck return ret_val; 1602401b5383SAlexander Duyck } 1603401b5383SAlexander Duyck 1604401b5383SAlexander Duyck /* This structure defines the attibutes to be parsed below */ 1605401b5383SAlexander Duyck const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { 1606401b5383SAlexander Duyck FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), 1607401b5383SAlexander Duyck FM10K_TLV_ATTR_LAST 1608401b5383SAlexander Duyck }; 1609401b5383SAlexander Duyck 1610401b5383SAlexander Duyck /** 1611401b5383SAlexander Duyck * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM 1612401b5383SAlexander Duyck * @hw: Pointer to hardware structure 1613401b5383SAlexander Duyck * @results: pointer array containing parsed data 1614401b5383SAlexander Duyck * @mbx: Pointer to mailbox information structure 1615401b5383SAlexander Duyck * 1616401b5383SAlexander Duyck * This handler configures the lport mapping based on the reply from the 1617401b5383SAlexander Duyck * switch API. 1618401b5383SAlexander Duyck **/ 1619401b5383SAlexander Duyck s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, 1620401b5383SAlexander Duyck struct fm10k_mbx_info *mbx) 1621401b5383SAlexander Duyck { 1622401b5383SAlexander Duyck u16 glort, mask; 1623401b5383SAlexander Duyck u32 dglort_map; 1624401b5383SAlexander Duyck s32 err; 1625401b5383SAlexander Duyck 1626401b5383SAlexander Duyck err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], 1627401b5383SAlexander Duyck &dglort_map); 1628401b5383SAlexander Duyck if (err) 1629401b5383SAlexander Duyck return err; 1630401b5383SAlexander Duyck 1631401b5383SAlexander Duyck /* extract values out of the header */ 1632401b5383SAlexander Duyck glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); 1633401b5383SAlexander Duyck mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); 1634401b5383SAlexander Duyck 1635401b5383SAlexander Duyck /* verify mask is set and none of the masked bits in glort are set */ 1636401b5383SAlexander Duyck if (!mask || (glort & ~mask)) 1637401b5383SAlexander Duyck return FM10K_ERR_PARAM; 1638401b5383SAlexander Duyck 1639401b5383SAlexander Duyck /* verify the mask is contiguous, and that it is 1's followed by 0's */ 1640401b5383SAlexander Duyck if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) 1641401b5383SAlexander Duyck return FM10K_ERR_PARAM; 1642401b5383SAlexander Duyck 1643401b5383SAlexander Duyck /* record the glort, mask, and port count */ 1644401b5383SAlexander Duyck hw->mac.dglort_map = dglort_map; 1645401b5383SAlexander Duyck 1646401b5383SAlexander Duyck return 0; 1647401b5383SAlexander Duyck } 1648401b5383SAlexander Duyck 1649401b5383SAlexander Duyck const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { 1650401b5383SAlexander Duyck FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), 1651401b5383SAlexander Duyck FM10K_TLV_ATTR_LAST 1652401b5383SAlexander Duyck }; 1653401b5383SAlexander Duyck 1654401b5383SAlexander Duyck /** 1655401b5383SAlexander Duyck * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM 1656401b5383SAlexander Duyck * @hw: Pointer to hardware structure 1657401b5383SAlexander Duyck * @results: pointer array containing parsed data 1658401b5383SAlexander Duyck * @mbx: Pointer to mailbox information structure 1659401b5383SAlexander Duyck * 1660401b5383SAlexander Duyck * This handler configures the default VLAN for the PF 1661401b5383SAlexander Duyck **/ 1662401b5383SAlexander Duyck s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, 1663401b5383SAlexander Duyck struct fm10k_mbx_info *mbx) 1664401b5383SAlexander Duyck { 1665401b5383SAlexander Duyck u16 glort, pvid; 1666401b5383SAlexander Duyck u32 pvid_update; 1667401b5383SAlexander Duyck s32 err; 1668401b5383SAlexander Duyck 1669401b5383SAlexander Duyck err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], 1670401b5383SAlexander Duyck &pvid_update); 1671401b5383SAlexander Duyck if (err) 1672401b5383SAlexander Duyck return err; 1673401b5383SAlexander Duyck 1674401b5383SAlexander Duyck /* extract values from the pvid update */ 1675401b5383SAlexander Duyck glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); 1676401b5383SAlexander Duyck pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); 1677401b5383SAlexander Duyck 1678401b5383SAlexander Duyck /* if glort is not valid return error */ 1679401b5383SAlexander Duyck if (!fm10k_glort_valid_pf(hw, glort)) 1680401b5383SAlexander Duyck return FM10K_ERR_PARAM; 1681401b5383SAlexander Duyck 1682401b5383SAlexander Duyck /* verify VID is valid */ 1683401b5383SAlexander Duyck if (pvid >= FM10K_VLAN_TABLE_VID_MAX) 1684401b5383SAlexander Duyck return FM10K_ERR_PARAM; 1685401b5383SAlexander Duyck 1686401b5383SAlexander Duyck /* record the port VLAN ID value */ 1687401b5383SAlexander Duyck hw->mac.default_vid = pvid; 1688401b5383SAlexander Duyck 1689401b5383SAlexander Duyck return 0; 1690401b5383SAlexander Duyck } 1691401b5383SAlexander Duyck 1692401b5383SAlexander Duyck /** 1693401b5383SAlexander Duyck * fm10k_record_global_table_data - Move global table data to swapi table info 1694401b5383SAlexander Duyck * @from: pointer to source table data structure 1695401b5383SAlexander Duyck * @to: pointer to destination table info structure 1696401b5383SAlexander Duyck * 1697401b5383SAlexander Duyck * This function is will copy table_data to the table_info contained in 1698401b5383SAlexander Duyck * the hw struct. 1699401b5383SAlexander Duyck **/ 1700401b5383SAlexander Duyck static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, 1701401b5383SAlexander Duyck struct fm10k_swapi_table_info *to) 1702401b5383SAlexander Duyck { 1703401b5383SAlexander Duyck /* convert from le32 struct to CPU byte ordered values */ 1704401b5383SAlexander Duyck to->used = le32_to_cpu(from->used); 1705401b5383SAlexander Duyck to->avail = le32_to_cpu(from->avail); 1706401b5383SAlexander Duyck } 1707401b5383SAlexander Duyck 1708401b5383SAlexander Duyck const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { 1709401b5383SAlexander Duyck FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, 1710401b5383SAlexander Duyck sizeof(struct fm10k_swapi_error)), 1711401b5383SAlexander Duyck FM10K_TLV_ATTR_LAST 1712401b5383SAlexander Duyck }; 1713401b5383SAlexander Duyck 1714401b5383SAlexander Duyck /** 1715401b5383SAlexander Duyck * fm10k_msg_err_pf - Message handler for error reply 1716401b5383SAlexander Duyck * @hw: Pointer to hardware structure 1717401b5383SAlexander Duyck * @results: pointer array containing parsed data 1718401b5383SAlexander Duyck * @mbx: Pointer to mailbox information structure 1719401b5383SAlexander Duyck * 1720401b5383SAlexander Duyck * This handler will capture the data for any error replies to previous 1721401b5383SAlexander Duyck * messages that the PF has sent. 1722401b5383SAlexander Duyck **/ 1723401b5383SAlexander Duyck s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, 1724401b5383SAlexander Duyck struct fm10k_mbx_info *mbx) 1725401b5383SAlexander Duyck { 1726401b5383SAlexander Duyck struct fm10k_swapi_error err_msg; 1727401b5383SAlexander Duyck s32 err; 1728401b5383SAlexander Duyck 1729401b5383SAlexander Duyck /* extract structure from message */ 1730401b5383SAlexander Duyck err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], 1731401b5383SAlexander Duyck &err_msg, sizeof(err_msg)); 1732401b5383SAlexander Duyck if (err) 1733401b5383SAlexander Duyck return err; 1734401b5383SAlexander Duyck 1735401b5383SAlexander Duyck /* record table status */ 1736401b5383SAlexander Duyck fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); 1737401b5383SAlexander Duyck fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); 1738401b5383SAlexander Duyck fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); 1739401b5383SAlexander Duyck 1740401b5383SAlexander Duyck /* record SW API status value */ 1741401b5383SAlexander Duyck hw->swapi.status = le32_to_cpu(err_msg.status); 1742401b5383SAlexander Duyck 1743401b5383SAlexander Duyck return 0; 1744401b5383SAlexander Duyck } 1745401b5383SAlexander Duyck 17465f226ddbSAlexander Duyck const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = { 17475f226ddbSAlexander Duyck FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP, 17485f226ddbSAlexander Duyck sizeof(struct fm10k_swapi_1588_timestamp)), 17495f226ddbSAlexander Duyck FM10K_TLV_ATTR_LAST 17505f226ddbSAlexander Duyck }; 17515f226ddbSAlexander Duyck 17525f226ddbSAlexander Duyck /* currently there is no shared 1588 timestamp handler */ 17535f226ddbSAlexander Duyck 17545f226ddbSAlexander Duyck /** 17555f226ddbSAlexander Duyck * fm10k_adjust_systime_pf - Adjust systime frequency 17565f226ddbSAlexander Duyck * @hw: pointer to hardware structure 17575f226ddbSAlexander Duyck * @ppb: adjustment rate in parts per billion 17585f226ddbSAlexander Duyck * 17595f226ddbSAlexander Duyck * This function will adjust the SYSTIME_CFG register contained in BAR 4 17605f226ddbSAlexander Duyck * if this function is supported for BAR 4 access. The adjustment amount 17615f226ddbSAlexander Duyck * is based on the parts per billion value provided and adjusted to a 17625f226ddbSAlexander Duyck * value based on parts per 2^48 clock cycles. 17635f226ddbSAlexander Duyck * 17645f226ddbSAlexander Duyck * If adjustment is not supported or the requested value is too large 17655f226ddbSAlexander Duyck * we will return an error. 17665f226ddbSAlexander Duyck **/ 17675f226ddbSAlexander Duyck static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb) 17685f226ddbSAlexander Duyck { 17695f226ddbSAlexander Duyck u64 systime_adjust; 17705f226ddbSAlexander Duyck 17715f226ddbSAlexander Duyck /* if sw_addr is not set we don't have switch register access */ 17725f226ddbSAlexander Duyck if (!hw->sw_addr) 17735f226ddbSAlexander Duyck return ppb ? FM10K_ERR_PARAM : 0; 17745f226ddbSAlexander Duyck 17755f226ddbSAlexander Duyck /* we must convert the value from parts per billion to parts per 17765f226ddbSAlexander Duyck * 2^48 cycles. In addition I have opted to only use the 30 most 17775f226ddbSAlexander Duyck * significant bits of the adjustment value as the 8 least 17785f226ddbSAlexander Duyck * significant bits are located in another register and represent 17795f226ddbSAlexander Duyck * a value significantly less than a part per billion, the result 17805f226ddbSAlexander Duyck * of dropping the 8 least significant bits is that the adjustment 17815f226ddbSAlexander Duyck * value is effectively multiplied by 2^8 when we write it. 17825f226ddbSAlexander Duyck * 17835f226ddbSAlexander Duyck * As a result of all this the math for this breaks down as follows: 17845f226ddbSAlexander Duyck * ppb / 10^9 == adjust * 2^8 / 2^48 17855f226ddbSAlexander Duyck * If we solve this for adjust, and simplify it comes out as: 17865f226ddbSAlexander Duyck * ppb * 2^31 / 5^9 == adjust 17875f226ddbSAlexander Duyck */ 17885f226ddbSAlexander Duyck systime_adjust = (ppb < 0) ? -ppb : ppb; 17895f226ddbSAlexander Duyck systime_adjust <<= 31; 17905f226ddbSAlexander Duyck do_div(systime_adjust, 1953125); 17915f226ddbSAlexander Duyck 17925f226ddbSAlexander Duyck /* verify the requested adjustment value is in range */ 17935f226ddbSAlexander Duyck if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK) 17945f226ddbSAlexander Duyck return FM10K_ERR_PARAM; 17955f226ddbSAlexander Duyck 1796646725a7SJacob Keller if (ppb > 0) 1797646725a7SJacob Keller systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE; 17985f226ddbSAlexander Duyck 17995f226ddbSAlexander Duyck fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust); 18005f226ddbSAlexander Duyck 18015f226ddbSAlexander Duyck return 0; 18025f226ddbSAlexander Duyck } 18035f226ddbSAlexander Duyck 18045f226ddbSAlexander Duyck /** 18055f226ddbSAlexander Duyck * fm10k_read_systime_pf - Reads value of systime registers 18065f226ddbSAlexander Duyck * @hw: pointer to the hardware structure 18075f226ddbSAlexander Duyck * 18085f226ddbSAlexander Duyck * Function reads the content of 2 registers, combined to represent a 64 bit 18095f226ddbSAlexander Duyck * value measured in nanosecods. In order to guarantee the value is accurate 18105f226ddbSAlexander Duyck * we check the 32 most significant bits both before and after reading the 18115f226ddbSAlexander Duyck * 32 least significant bits to verify they didn't change as we were reading 18125f226ddbSAlexander Duyck * the registers. 18135f226ddbSAlexander Duyck **/ 18145f226ddbSAlexander Duyck static u64 fm10k_read_systime_pf(struct fm10k_hw *hw) 18155f226ddbSAlexander Duyck { 18165f226ddbSAlexander Duyck u32 systime_l, systime_h, systime_tmp; 18175f226ddbSAlexander Duyck 18185f226ddbSAlexander Duyck systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); 18195f226ddbSAlexander Duyck 18205f226ddbSAlexander Duyck do { 18215f226ddbSAlexander Duyck systime_tmp = systime_h; 18225f226ddbSAlexander Duyck systime_l = fm10k_read_reg(hw, FM10K_SYSTIME); 18235f226ddbSAlexander Duyck systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); 18245f226ddbSAlexander Duyck } while (systime_tmp != systime_h); 18255f226ddbSAlexander Duyck 18265f226ddbSAlexander Duyck return ((u64)systime_h << 32) | systime_l; 18275f226ddbSAlexander Duyck } 18285f226ddbSAlexander Duyck 1829401b5383SAlexander Duyck static const struct fm10k_msg_data fm10k_msg_data_pf[] = { 1830401b5383SAlexander Duyck FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), 1831401b5383SAlexander Duyck FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), 1832401b5383SAlexander Duyck FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), 1833401b5383SAlexander Duyck FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), 1834401b5383SAlexander Duyck FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), 1835401b5383SAlexander Duyck FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), 1836401b5383SAlexander Duyck FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), 1837401b5383SAlexander Duyck }; 1838401b5383SAlexander Duyck 1839b6fec18fSAlexander Duyck static struct fm10k_mac_ops mac_ops_pf = { 1840b6fec18fSAlexander Duyck .get_bus_info = &fm10k_get_bus_info_generic, 1841b6fec18fSAlexander Duyck .reset_hw = &fm10k_reset_hw_pf, 1842b6fec18fSAlexander Duyck .init_hw = &fm10k_init_hw_pf, 1843b6fec18fSAlexander Duyck .start_hw = &fm10k_start_hw_generic, 1844b6fec18fSAlexander Duyck .stop_hw = &fm10k_stop_hw_generic, 1845401b5383SAlexander Duyck .update_vlan = &fm10k_update_vlan_pf, 1846b6fec18fSAlexander Duyck .read_mac_addr = &fm10k_read_mac_addr_pf, 1847401b5383SAlexander Duyck .update_uc_addr = &fm10k_update_uc_addr_pf, 1848401b5383SAlexander Duyck .update_mc_addr = &fm10k_update_mc_addr_pf, 1849401b5383SAlexander Duyck .update_xcast_mode = &fm10k_update_xcast_mode_pf, 1850401b5383SAlexander Duyck .update_int_moderator = &fm10k_update_int_moderator_pf, 1851401b5383SAlexander Duyck .update_lport_state = &fm10k_update_lport_state_pf, 1852b6fec18fSAlexander Duyck .update_hw_stats = &fm10k_update_hw_stats_pf, 1853b6fec18fSAlexander Duyck .rebind_hw_stats = &fm10k_rebind_hw_stats_pf, 1854401b5383SAlexander Duyck .configure_dglort_map = &fm10k_configure_dglort_map_pf, 1855401b5383SAlexander Duyck .set_dma_mask = &fm10k_set_dma_mask_pf, 1856b6fec18fSAlexander Duyck .get_fault = &fm10k_get_fault_pf, 1857401b5383SAlexander Duyck .get_host_state = &fm10k_get_host_state_pf, 18585f226ddbSAlexander Duyck .adjust_systime = &fm10k_adjust_systime_pf, 18595f226ddbSAlexander Duyck .read_systime = &fm10k_read_systime_pf, 1860b6fec18fSAlexander Duyck }; 1861b6fec18fSAlexander Duyck 1862c2653865SAlexander Duyck static struct fm10k_iov_ops iov_ops_pf = { 1863c2653865SAlexander Duyck .assign_resources = &fm10k_iov_assign_resources_pf, 1864c2653865SAlexander Duyck .configure_tc = &fm10k_iov_configure_tc_pf, 1865c2653865SAlexander Duyck .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf, 1866c2653865SAlexander Duyck .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, 1867c2653865SAlexander Duyck .reset_resources = &fm10k_iov_reset_resources_pf, 1868c2653865SAlexander Duyck .set_lport = &fm10k_iov_set_lport_pf, 1869c2653865SAlexander Duyck .reset_lport = &fm10k_iov_reset_lport_pf, 1870c2653865SAlexander Duyck .update_stats = &fm10k_iov_update_stats_pf, 18715f226ddbSAlexander Duyck .report_timestamp = &fm10k_iov_report_timestamp_pf, 1872c2653865SAlexander Duyck }; 1873c2653865SAlexander Duyck 1874401b5383SAlexander Duyck static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) 1875401b5383SAlexander Duyck { 1876401b5383SAlexander Duyck fm10k_get_invariants_generic(hw); 1877401b5383SAlexander Duyck 1878401b5383SAlexander Duyck return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); 1879401b5383SAlexander Duyck } 1880401b5383SAlexander Duyck 1881b6fec18fSAlexander Duyck struct fm10k_info fm10k_pf_info = { 1882b6fec18fSAlexander Duyck .mac = fm10k_mac_pf, 1883401b5383SAlexander Duyck .get_invariants = &fm10k_get_invariants_pf, 1884b6fec18fSAlexander Duyck .mac_ops = &mac_ops_pf, 1885c2653865SAlexander Duyck .iov_ops = &iov_ops_pf, 1886b6fec18fSAlexander Duyck }; 1887