1 /* Intel(R) Ethernet Switch Host Interface Driver 2 * Copyright(c) 2013 - 2017 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19 */ 20 21 #include <linux/types.h> 22 #include <linux/module.h> 23 #include <net/ipv6.h> 24 #include <net/ip.h> 25 #include <net/tcp.h> 26 #include <linux/if_macvlan.h> 27 #include <linux/prefetch.h> 28 29 #include "fm10k.h" 30 31 #define DRV_VERSION "0.22.1-k" 32 #define DRV_SUMMARY "Intel(R) Ethernet Switch Host Interface Driver" 33 const char fm10k_driver_version[] = DRV_VERSION; 34 char fm10k_driver_name[] = "fm10k"; 35 static const char fm10k_driver_string[] = DRV_SUMMARY; 36 static const char fm10k_copyright[] = 37 "Copyright(c) 2013 - 2017 Intel Corporation."; 38 39 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 40 MODULE_DESCRIPTION(DRV_SUMMARY); 41 MODULE_LICENSE("GPL"); 42 MODULE_VERSION(DRV_VERSION); 43 44 /* single workqueue for entire fm10k driver */ 45 struct workqueue_struct *fm10k_workqueue; 46 47 /** 48 * fm10k_init_module - Driver Registration Routine 49 * 50 * fm10k_init_module is the first routine called when the driver is 51 * loaded. All it does is register with the PCI subsystem. 52 **/ 53 static int __init fm10k_init_module(void) 54 { 55 pr_info("%s - version %s\n", fm10k_driver_string, fm10k_driver_version); 56 pr_info("%s\n", fm10k_copyright); 57 58 /* create driver workqueue */ 59 fm10k_workqueue = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, 60 fm10k_driver_name); 61 62 fm10k_dbg_init(); 63 64 return fm10k_register_pci_driver(); 65 } 66 module_init(fm10k_init_module); 67 68 /** 69 * fm10k_exit_module - Driver Exit Cleanup Routine 70 * 71 * fm10k_exit_module is called just before the driver is removed 72 * from memory. 73 **/ 74 static void __exit fm10k_exit_module(void) 75 { 76 fm10k_unregister_pci_driver(); 77 78 fm10k_dbg_exit(); 79 80 /* destroy driver workqueue */ 81 destroy_workqueue(fm10k_workqueue); 82 } 83 module_exit(fm10k_exit_module); 84 85 static bool fm10k_alloc_mapped_page(struct fm10k_ring *rx_ring, 86 struct fm10k_rx_buffer *bi) 87 { 88 struct page *page = bi->page; 89 dma_addr_t dma; 90 91 /* Only page will be NULL if buffer was consumed */ 92 if (likely(page)) 93 return true; 94 95 /* alloc new page for storage */ 96 page = dev_alloc_page(); 97 if (unlikely(!page)) { 98 rx_ring->rx_stats.alloc_failed++; 99 return false; 100 } 101 102 /* map page for use */ 103 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 104 105 /* if mapping failed free memory back to system since 106 * there isn't much point in holding memory we can't use 107 */ 108 if (dma_mapping_error(rx_ring->dev, dma)) { 109 __free_page(page); 110 111 rx_ring->rx_stats.alloc_failed++; 112 return false; 113 } 114 115 bi->dma = dma; 116 bi->page = page; 117 bi->page_offset = 0; 118 119 return true; 120 } 121 122 /** 123 * fm10k_alloc_rx_buffers - Replace used receive buffers 124 * @rx_ring: ring to place buffers on 125 * @cleaned_count: number of buffers to replace 126 **/ 127 void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count) 128 { 129 union fm10k_rx_desc *rx_desc; 130 struct fm10k_rx_buffer *bi; 131 u16 i = rx_ring->next_to_use; 132 133 /* nothing to do */ 134 if (!cleaned_count) 135 return; 136 137 rx_desc = FM10K_RX_DESC(rx_ring, i); 138 bi = &rx_ring->rx_buffer[i]; 139 i -= rx_ring->count; 140 141 do { 142 if (!fm10k_alloc_mapped_page(rx_ring, bi)) 143 break; 144 145 /* Refresh the desc even if buffer_addrs didn't change 146 * because each write-back erases this info. 147 */ 148 rx_desc->q.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 149 150 rx_desc++; 151 bi++; 152 i++; 153 if (unlikely(!i)) { 154 rx_desc = FM10K_RX_DESC(rx_ring, 0); 155 bi = rx_ring->rx_buffer; 156 i -= rx_ring->count; 157 } 158 159 /* clear the status bits for the next_to_use descriptor */ 160 rx_desc->d.staterr = 0; 161 162 cleaned_count--; 163 } while (cleaned_count); 164 165 i += rx_ring->count; 166 167 if (rx_ring->next_to_use != i) { 168 /* record the next descriptor to use */ 169 rx_ring->next_to_use = i; 170 171 /* update next to alloc since we have filled the ring */ 172 rx_ring->next_to_alloc = i; 173 174 /* Force memory writes to complete before letting h/w 175 * know there are new descriptors to fetch. (Only 176 * applicable for weak-ordered memory model archs, 177 * such as IA-64). 178 */ 179 wmb(); 180 181 /* notify hardware of new descriptors */ 182 writel(i, rx_ring->tail); 183 } 184 } 185 186 /** 187 * fm10k_reuse_rx_page - page flip buffer and store it back on the ring 188 * @rx_ring: rx descriptor ring to store buffers on 189 * @old_buff: donor buffer to have page reused 190 * 191 * Synchronizes page for reuse by the interface 192 **/ 193 static void fm10k_reuse_rx_page(struct fm10k_ring *rx_ring, 194 struct fm10k_rx_buffer *old_buff) 195 { 196 struct fm10k_rx_buffer *new_buff; 197 u16 nta = rx_ring->next_to_alloc; 198 199 new_buff = &rx_ring->rx_buffer[nta]; 200 201 /* update, and store next to alloc */ 202 nta++; 203 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 204 205 /* transfer page from old buffer to new buffer */ 206 *new_buff = *old_buff; 207 208 /* sync the buffer for use by the device */ 209 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 210 old_buff->page_offset, 211 FM10K_RX_BUFSZ, 212 DMA_FROM_DEVICE); 213 } 214 215 static inline bool fm10k_page_is_reserved(struct page *page) 216 { 217 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 218 } 219 220 static bool fm10k_can_reuse_rx_page(struct fm10k_rx_buffer *rx_buffer, 221 struct page *page, 222 unsigned int __maybe_unused truesize) 223 { 224 /* avoid re-using remote pages */ 225 if (unlikely(fm10k_page_is_reserved(page))) 226 return false; 227 228 #if (PAGE_SIZE < 8192) 229 /* if we are only owner of page we can reuse it */ 230 if (unlikely(page_count(page) != 1)) 231 return false; 232 233 /* flip page offset to other buffer */ 234 rx_buffer->page_offset ^= FM10K_RX_BUFSZ; 235 #else 236 /* move offset up to the next cache line */ 237 rx_buffer->page_offset += truesize; 238 239 if (rx_buffer->page_offset > (PAGE_SIZE - FM10K_RX_BUFSZ)) 240 return false; 241 #endif 242 243 /* Even if we own the page, we are not allowed to use atomic_set() 244 * This would break get_page_unless_zero() users. 245 */ 246 page_ref_inc(page); 247 248 return true; 249 } 250 251 /** 252 * fm10k_add_rx_frag - Add contents of Rx buffer to sk_buff 253 * @rx_buffer: buffer containing page to add 254 * @size: packet size from rx_desc 255 * @rx_desc: descriptor containing length of buffer written by hardware 256 * @skb: sk_buff to place the data into 257 * 258 * This function will add the data contained in rx_buffer->page to the skb. 259 * This is done either through a direct copy if the data in the buffer is 260 * less than the skb header size, otherwise it will just attach the page as 261 * a frag to the skb. 262 * 263 * The function will then update the page offset if necessary and return 264 * true if the buffer can be reused by the interface. 265 **/ 266 static bool fm10k_add_rx_frag(struct fm10k_rx_buffer *rx_buffer, 267 unsigned int size, 268 union fm10k_rx_desc *rx_desc, 269 struct sk_buff *skb) 270 { 271 struct page *page = rx_buffer->page; 272 unsigned char *va = page_address(page) + rx_buffer->page_offset; 273 #if (PAGE_SIZE < 8192) 274 unsigned int truesize = FM10K_RX_BUFSZ; 275 #else 276 unsigned int truesize = ALIGN(size, 512); 277 #endif 278 unsigned int pull_len; 279 280 if (unlikely(skb_is_nonlinear(skb))) 281 goto add_tail_frag; 282 283 if (likely(size <= FM10K_RX_HDR_LEN)) { 284 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 285 286 /* page is not reserved, we can reuse buffer as-is */ 287 if (likely(!fm10k_page_is_reserved(page))) 288 return true; 289 290 /* this page cannot be reused so discard it */ 291 __free_page(page); 292 return false; 293 } 294 295 /* we need the header to contain the greater of either ETH_HLEN or 296 * 60 bytes if the skb->len is less than 60 for skb_pad. 297 */ 298 pull_len = eth_get_headlen(va, FM10K_RX_HDR_LEN); 299 300 /* align pull length to size of long to optimize memcpy performance */ 301 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 302 303 /* update all of the pointers */ 304 va += pull_len; 305 size -= pull_len; 306 307 add_tail_frag: 308 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 309 (unsigned long)va & ~PAGE_MASK, size, truesize); 310 311 return fm10k_can_reuse_rx_page(rx_buffer, page, truesize); 312 } 313 314 static struct sk_buff *fm10k_fetch_rx_buffer(struct fm10k_ring *rx_ring, 315 union fm10k_rx_desc *rx_desc, 316 struct sk_buff *skb) 317 { 318 unsigned int size = le16_to_cpu(rx_desc->w.length); 319 struct fm10k_rx_buffer *rx_buffer; 320 struct page *page; 321 322 rx_buffer = &rx_ring->rx_buffer[rx_ring->next_to_clean]; 323 page = rx_buffer->page; 324 prefetchw(page); 325 326 if (likely(!skb)) { 327 void *page_addr = page_address(page) + 328 rx_buffer->page_offset; 329 330 /* prefetch first cache line of first page */ 331 prefetch(page_addr); 332 #if L1_CACHE_BYTES < 128 333 prefetch(page_addr + L1_CACHE_BYTES); 334 #endif 335 336 /* allocate a skb to store the frags */ 337 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 338 FM10K_RX_HDR_LEN); 339 if (unlikely(!skb)) { 340 rx_ring->rx_stats.alloc_failed++; 341 return NULL; 342 } 343 344 /* we will be copying header into skb->data in 345 * pskb_may_pull so it is in our interest to prefetch 346 * it now to avoid a possible cache miss 347 */ 348 prefetchw(skb->data); 349 } 350 351 /* we are reusing so sync this buffer for CPU use */ 352 dma_sync_single_range_for_cpu(rx_ring->dev, 353 rx_buffer->dma, 354 rx_buffer->page_offset, 355 size, 356 DMA_FROM_DEVICE); 357 358 /* pull page into skb */ 359 if (fm10k_add_rx_frag(rx_buffer, size, rx_desc, skb)) { 360 /* hand second half of page back to the ring */ 361 fm10k_reuse_rx_page(rx_ring, rx_buffer); 362 } else { 363 /* we are not reusing the buffer so unmap it */ 364 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 365 PAGE_SIZE, DMA_FROM_DEVICE); 366 } 367 368 /* clear contents of rx_buffer */ 369 rx_buffer->page = NULL; 370 371 return skb; 372 } 373 374 static inline void fm10k_rx_checksum(struct fm10k_ring *ring, 375 union fm10k_rx_desc *rx_desc, 376 struct sk_buff *skb) 377 { 378 skb_checksum_none_assert(skb); 379 380 /* Rx checksum disabled via ethtool */ 381 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 382 return; 383 384 /* TCP/UDP checksum error bit is set */ 385 if (fm10k_test_staterr(rx_desc, 386 FM10K_RXD_STATUS_L4E | 387 FM10K_RXD_STATUS_L4E2 | 388 FM10K_RXD_STATUS_IPE | 389 FM10K_RXD_STATUS_IPE2)) { 390 ring->rx_stats.csum_err++; 391 return; 392 } 393 394 /* It must be a TCP or UDP packet with a valid checksum */ 395 if (fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS2)) 396 skb->encapsulation = true; 397 else if (!fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS)) 398 return; 399 400 skb->ip_summed = CHECKSUM_UNNECESSARY; 401 402 ring->rx_stats.csum_good++; 403 } 404 405 #define FM10K_RSS_L4_TYPES_MASK \ 406 (BIT(FM10K_RSSTYPE_IPV4_TCP) | \ 407 BIT(FM10K_RSSTYPE_IPV4_UDP) | \ 408 BIT(FM10K_RSSTYPE_IPV6_TCP) | \ 409 BIT(FM10K_RSSTYPE_IPV6_UDP)) 410 411 static inline void fm10k_rx_hash(struct fm10k_ring *ring, 412 union fm10k_rx_desc *rx_desc, 413 struct sk_buff *skb) 414 { 415 u16 rss_type; 416 417 if (!(ring->netdev->features & NETIF_F_RXHASH)) 418 return; 419 420 rss_type = le16_to_cpu(rx_desc->w.pkt_info) & FM10K_RXD_RSSTYPE_MASK; 421 if (!rss_type) 422 return; 423 424 skb_set_hash(skb, le32_to_cpu(rx_desc->d.rss), 425 (BIT(rss_type) & FM10K_RSS_L4_TYPES_MASK) ? 426 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 427 } 428 429 static void fm10k_type_trans(struct fm10k_ring *rx_ring, 430 union fm10k_rx_desc __maybe_unused *rx_desc, 431 struct sk_buff *skb) 432 { 433 struct net_device *dev = rx_ring->netdev; 434 struct fm10k_l2_accel *l2_accel = rcu_dereference_bh(rx_ring->l2_accel); 435 436 /* check to see if DGLORT belongs to a MACVLAN */ 437 if (l2_accel) { 438 u16 idx = le16_to_cpu(FM10K_CB(skb)->fi.w.dglort) - 1; 439 440 idx -= l2_accel->dglort; 441 if (idx < l2_accel->size && l2_accel->macvlan[idx]) 442 dev = l2_accel->macvlan[idx]; 443 else 444 l2_accel = NULL; 445 } 446 447 skb->protocol = eth_type_trans(skb, dev); 448 449 if (!l2_accel) 450 return; 451 452 /* update MACVLAN statistics */ 453 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, 1, 454 !!(rx_desc->w.hdr_info & 455 cpu_to_le16(FM10K_RXD_HDR_INFO_XC_MASK))); 456 } 457 458 /** 459 * fm10k_process_skb_fields - Populate skb header fields from Rx descriptor 460 * @rx_ring: rx descriptor ring packet is being transacted on 461 * @rx_desc: pointer to the EOP Rx descriptor 462 * @skb: pointer to current skb being populated 463 * 464 * This function checks the ring, descriptor, and packet information in 465 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 466 * other fields within the skb. 467 **/ 468 static unsigned int fm10k_process_skb_fields(struct fm10k_ring *rx_ring, 469 union fm10k_rx_desc *rx_desc, 470 struct sk_buff *skb) 471 { 472 unsigned int len = skb->len; 473 474 fm10k_rx_hash(rx_ring, rx_desc, skb); 475 476 fm10k_rx_checksum(rx_ring, rx_desc, skb); 477 478 FM10K_CB(skb)->tstamp = rx_desc->q.timestamp; 479 480 FM10K_CB(skb)->fi.w.vlan = rx_desc->w.vlan; 481 482 skb_record_rx_queue(skb, rx_ring->queue_index); 483 484 FM10K_CB(skb)->fi.d.glort = rx_desc->d.glort; 485 486 if (rx_desc->w.vlan) { 487 u16 vid = le16_to_cpu(rx_desc->w.vlan); 488 489 if ((vid & VLAN_VID_MASK) != rx_ring->vid) 490 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 491 else if (vid & VLAN_PRIO_MASK) 492 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 493 vid & VLAN_PRIO_MASK); 494 } 495 496 fm10k_type_trans(rx_ring, rx_desc, skb); 497 498 return len; 499 } 500 501 /** 502 * fm10k_is_non_eop - process handling of non-EOP buffers 503 * @rx_ring: Rx ring being processed 504 * @rx_desc: Rx descriptor for current buffer 505 * 506 * This function updates next to clean. If the buffer is an EOP buffer 507 * this function exits returning false, otherwise it will place the 508 * sk_buff in the next buffer to be chained and return true indicating 509 * that this is in fact a non-EOP buffer. 510 **/ 511 static bool fm10k_is_non_eop(struct fm10k_ring *rx_ring, 512 union fm10k_rx_desc *rx_desc) 513 { 514 u32 ntc = rx_ring->next_to_clean + 1; 515 516 /* fetch, update, and store next to clean */ 517 ntc = (ntc < rx_ring->count) ? ntc : 0; 518 rx_ring->next_to_clean = ntc; 519 520 prefetch(FM10K_RX_DESC(rx_ring, ntc)); 521 522 if (likely(fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_EOP))) 523 return false; 524 525 return true; 526 } 527 528 /** 529 * fm10k_cleanup_headers - Correct corrupted or empty headers 530 * @rx_ring: rx descriptor ring packet is being transacted on 531 * @rx_desc: pointer to the EOP Rx descriptor 532 * @skb: pointer to current skb being fixed 533 * 534 * Address the case where we are pulling data in on pages only 535 * and as such no data is present in the skb header. 536 * 537 * In addition if skb is not at least 60 bytes we need to pad it so that 538 * it is large enough to qualify as a valid Ethernet frame. 539 * 540 * Returns true if an error was encountered and skb was freed. 541 **/ 542 static bool fm10k_cleanup_headers(struct fm10k_ring *rx_ring, 543 union fm10k_rx_desc *rx_desc, 544 struct sk_buff *skb) 545 { 546 if (unlikely((fm10k_test_staterr(rx_desc, 547 FM10K_RXD_STATUS_RXE)))) { 548 #define FM10K_TEST_RXD_BIT(rxd, bit) \ 549 ((rxd)->w.csum_err & cpu_to_le16(bit)) 550 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_ERROR)) 551 rx_ring->rx_stats.switch_errors++; 552 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_NO_DESCRIPTOR)) 553 rx_ring->rx_stats.drops++; 554 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_PP_ERROR)) 555 rx_ring->rx_stats.pp_errors++; 556 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_READY)) 557 rx_ring->rx_stats.link_errors++; 558 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_TOO_BIG)) 559 rx_ring->rx_stats.length_errors++; 560 dev_kfree_skb_any(skb); 561 rx_ring->rx_stats.errors++; 562 return true; 563 } 564 565 /* if eth_skb_pad returns an error the skb was freed */ 566 if (eth_skb_pad(skb)) 567 return true; 568 569 return false; 570 } 571 572 /** 573 * fm10k_receive_skb - helper function to handle rx indications 574 * @q_vector: structure containing interrupt and ring information 575 * @skb: packet to send up 576 **/ 577 static void fm10k_receive_skb(struct fm10k_q_vector *q_vector, 578 struct sk_buff *skb) 579 { 580 napi_gro_receive(&q_vector->napi, skb); 581 } 582 583 static int fm10k_clean_rx_irq(struct fm10k_q_vector *q_vector, 584 struct fm10k_ring *rx_ring, 585 int budget) 586 { 587 struct sk_buff *skb = rx_ring->skb; 588 unsigned int total_bytes = 0, total_packets = 0; 589 u16 cleaned_count = fm10k_desc_unused(rx_ring); 590 591 while (likely(total_packets < budget)) { 592 union fm10k_rx_desc *rx_desc; 593 594 /* return some buffers to hardware, one at a time is too slow */ 595 if (cleaned_count >= FM10K_RX_BUFFER_WRITE) { 596 fm10k_alloc_rx_buffers(rx_ring, cleaned_count); 597 cleaned_count = 0; 598 } 599 600 rx_desc = FM10K_RX_DESC(rx_ring, rx_ring->next_to_clean); 601 602 if (!rx_desc->d.staterr) 603 break; 604 605 /* This memory barrier is needed to keep us from reading 606 * any other fields out of the rx_desc until we know the 607 * descriptor has been written back 608 */ 609 dma_rmb(); 610 611 /* retrieve a buffer from the ring */ 612 skb = fm10k_fetch_rx_buffer(rx_ring, rx_desc, skb); 613 614 /* exit if we failed to retrieve a buffer */ 615 if (!skb) 616 break; 617 618 cleaned_count++; 619 620 /* fetch next buffer in frame if non-eop */ 621 if (fm10k_is_non_eop(rx_ring, rx_desc)) 622 continue; 623 624 /* verify the packet layout is correct */ 625 if (fm10k_cleanup_headers(rx_ring, rx_desc, skb)) { 626 skb = NULL; 627 continue; 628 } 629 630 /* populate checksum, timestamp, VLAN, and protocol */ 631 total_bytes += fm10k_process_skb_fields(rx_ring, rx_desc, skb); 632 633 fm10k_receive_skb(q_vector, skb); 634 635 /* reset skb pointer */ 636 skb = NULL; 637 638 /* update budget accounting */ 639 total_packets++; 640 } 641 642 /* place incomplete frames back on ring for completion */ 643 rx_ring->skb = skb; 644 645 u64_stats_update_begin(&rx_ring->syncp); 646 rx_ring->stats.packets += total_packets; 647 rx_ring->stats.bytes += total_bytes; 648 u64_stats_update_end(&rx_ring->syncp); 649 q_vector->rx.total_packets += total_packets; 650 q_vector->rx.total_bytes += total_bytes; 651 652 return total_packets; 653 } 654 655 #define VXLAN_HLEN (sizeof(struct udphdr) + 8) 656 static struct ethhdr *fm10k_port_is_vxlan(struct sk_buff *skb) 657 { 658 struct fm10k_intfc *interface = netdev_priv(skb->dev); 659 struct fm10k_udp_port *vxlan_port; 660 661 /* we can only offload a vxlan if we recognize it as such */ 662 vxlan_port = list_first_entry_or_null(&interface->vxlan_port, 663 struct fm10k_udp_port, list); 664 665 if (!vxlan_port) 666 return NULL; 667 if (vxlan_port->port != udp_hdr(skb)->dest) 668 return NULL; 669 670 /* return offset of udp_hdr plus 8 bytes for VXLAN header */ 671 return (struct ethhdr *)(skb_transport_header(skb) + VXLAN_HLEN); 672 } 673 674 #define FM10K_NVGRE_RESERVED0_FLAGS htons(0x9FFF) 675 #define NVGRE_TNI htons(0x2000) 676 struct fm10k_nvgre_hdr { 677 __be16 flags; 678 __be16 proto; 679 __be32 tni; 680 }; 681 682 static struct ethhdr *fm10k_gre_is_nvgre(struct sk_buff *skb) 683 { 684 struct fm10k_nvgre_hdr *nvgre_hdr; 685 int hlen = ip_hdrlen(skb); 686 687 /* currently only IPv4 is supported due to hlen above */ 688 if (vlan_get_protocol(skb) != htons(ETH_P_IP)) 689 return NULL; 690 691 /* our transport header should be NVGRE */ 692 nvgre_hdr = (struct fm10k_nvgre_hdr *)(skb_network_header(skb) + hlen); 693 694 /* verify all reserved flags are 0 */ 695 if (nvgre_hdr->flags & FM10K_NVGRE_RESERVED0_FLAGS) 696 return NULL; 697 698 /* report start of ethernet header */ 699 if (nvgre_hdr->flags & NVGRE_TNI) 700 return (struct ethhdr *)(nvgre_hdr + 1); 701 702 return (struct ethhdr *)(&nvgre_hdr->tni); 703 } 704 705 __be16 fm10k_tx_encap_offload(struct sk_buff *skb) 706 { 707 u8 l4_hdr = 0, inner_l4_hdr = 0, inner_l4_hlen; 708 struct ethhdr *eth_hdr; 709 710 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 711 skb->inner_protocol != htons(ETH_P_TEB)) 712 return 0; 713 714 switch (vlan_get_protocol(skb)) { 715 case htons(ETH_P_IP): 716 l4_hdr = ip_hdr(skb)->protocol; 717 break; 718 case htons(ETH_P_IPV6): 719 l4_hdr = ipv6_hdr(skb)->nexthdr; 720 break; 721 default: 722 return 0; 723 } 724 725 switch (l4_hdr) { 726 case IPPROTO_UDP: 727 eth_hdr = fm10k_port_is_vxlan(skb); 728 break; 729 case IPPROTO_GRE: 730 eth_hdr = fm10k_gre_is_nvgre(skb); 731 break; 732 default: 733 return 0; 734 } 735 736 if (!eth_hdr) 737 return 0; 738 739 switch (eth_hdr->h_proto) { 740 case htons(ETH_P_IP): 741 inner_l4_hdr = inner_ip_hdr(skb)->protocol; 742 break; 743 case htons(ETH_P_IPV6): 744 inner_l4_hdr = inner_ipv6_hdr(skb)->nexthdr; 745 break; 746 default: 747 return 0; 748 } 749 750 switch (inner_l4_hdr) { 751 case IPPROTO_TCP: 752 inner_l4_hlen = inner_tcp_hdrlen(skb); 753 break; 754 case IPPROTO_UDP: 755 inner_l4_hlen = 8; 756 break; 757 default: 758 return 0; 759 } 760 761 /* The hardware allows tunnel offloads only if the combined inner and 762 * outer header is 184 bytes or less 763 */ 764 if (skb_inner_transport_header(skb) + inner_l4_hlen - 765 skb_mac_header(skb) > FM10K_TUNNEL_HEADER_LENGTH) 766 return 0; 767 768 return eth_hdr->h_proto; 769 } 770 771 static int fm10k_tso(struct fm10k_ring *tx_ring, 772 struct fm10k_tx_buffer *first) 773 { 774 struct sk_buff *skb = first->skb; 775 struct fm10k_tx_desc *tx_desc; 776 unsigned char *th; 777 u8 hdrlen; 778 779 if (skb->ip_summed != CHECKSUM_PARTIAL) 780 return 0; 781 782 if (!skb_is_gso(skb)) 783 return 0; 784 785 /* compute header lengths */ 786 if (skb->encapsulation) { 787 if (!fm10k_tx_encap_offload(skb)) 788 goto err_vxlan; 789 th = skb_inner_transport_header(skb); 790 } else { 791 th = skb_transport_header(skb); 792 } 793 794 /* compute offset from SOF to transport header and add header len */ 795 hdrlen = (th - skb->data) + (((struct tcphdr *)th)->doff << 2); 796 797 first->tx_flags |= FM10K_TX_FLAGS_CSUM; 798 799 /* update gso size and bytecount with header size */ 800 first->gso_segs = skb_shinfo(skb)->gso_segs; 801 first->bytecount += (first->gso_segs - 1) * hdrlen; 802 803 /* populate Tx descriptor header size and mss */ 804 tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); 805 tx_desc->hdrlen = hdrlen; 806 tx_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); 807 808 return 1; 809 810 err_vxlan: 811 tx_ring->netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL; 812 if (net_ratelimit()) 813 netdev_err(tx_ring->netdev, 814 "TSO requested for unsupported tunnel, disabling offload\n"); 815 return -1; 816 } 817 818 static void fm10k_tx_csum(struct fm10k_ring *tx_ring, 819 struct fm10k_tx_buffer *first) 820 { 821 struct sk_buff *skb = first->skb; 822 struct fm10k_tx_desc *tx_desc; 823 union { 824 struct iphdr *ipv4; 825 struct ipv6hdr *ipv6; 826 u8 *raw; 827 } network_hdr; 828 u8 *transport_hdr; 829 __be16 frag_off; 830 __be16 protocol; 831 u8 l4_hdr = 0; 832 833 if (skb->ip_summed != CHECKSUM_PARTIAL) 834 goto no_csum; 835 836 if (skb->encapsulation) { 837 protocol = fm10k_tx_encap_offload(skb); 838 if (!protocol) { 839 if (skb_checksum_help(skb)) { 840 dev_warn(tx_ring->dev, 841 "failed to offload encap csum!\n"); 842 tx_ring->tx_stats.csum_err++; 843 } 844 goto no_csum; 845 } 846 network_hdr.raw = skb_inner_network_header(skb); 847 transport_hdr = skb_inner_transport_header(skb); 848 } else { 849 protocol = vlan_get_protocol(skb); 850 network_hdr.raw = skb_network_header(skb); 851 transport_hdr = skb_transport_header(skb); 852 } 853 854 switch (protocol) { 855 case htons(ETH_P_IP): 856 l4_hdr = network_hdr.ipv4->protocol; 857 break; 858 case htons(ETH_P_IPV6): 859 l4_hdr = network_hdr.ipv6->nexthdr; 860 if (likely((transport_hdr - network_hdr.raw) == 861 sizeof(struct ipv6hdr))) 862 break; 863 ipv6_skip_exthdr(skb, network_hdr.raw - skb->data + 864 sizeof(struct ipv6hdr), 865 &l4_hdr, &frag_off); 866 if (unlikely(frag_off)) 867 l4_hdr = NEXTHDR_FRAGMENT; 868 break; 869 default: 870 break; 871 } 872 873 switch (l4_hdr) { 874 case IPPROTO_TCP: 875 case IPPROTO_UDP: 876 break; 877 case IPPROTO_GRE: 878 if (skb->encapsulation) 879 break; 880 /* fall through */ 881 default: 882 if (unlikely(net_ratelimit())) { 883 dev_warn(tx_ring->dev, 884 "partial checksum, version=%d l4 proto=%x\n", 885 protocol, l4_hdr); 886 } 887 skb_checksum_help(skb); 888 tx_ring->tx_stats.csum_err++; 889 goto no_csum; 890 } 891 892 /* update TX checksum flag */ 893 first->tx_flags |= FM10K_TX_FLAGS_CSUM; 894 tx_ring->tx_stats.csum_good++; 895 896 no_csum: 897 /* populate Tx descriptor header size and mss */ 898 tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); 899 tx_desc->hdrlen = 0; 900 tx_desc->mss = 0; 901 } 902 903 #define FM10K_SET_FLAG(_input, _flag, _result) \ 904 ((_flag <= _result) ? \ 905 ((u32)(_input & _flag) * (_result / _flag)) : \ 906 ((u32)(_input & _flag) / (_flag / _result))) 907 908 static u8 fm10k_tx_desc_flags(struct sk_buff *skb, u32 tx_flags) 909 { 910 /* set type for advanced descriptor with frame checksum insertion */ 911 u32 desc_flags = 0; 912 913 /* set checksum offload bits */ 914 desc_flags |= FM10K_SET_FLAG(tx_flags, FM10K_TX_FLAGS_CSUM, 915 FM10K_TXD_FLAG_CSUM); 916 917 return desc_flags; 918 } 919 920 static bool fm10k_tx_desc_push(struct fm10k_ring *tx_ring, 921 struct fm10k_tx_desc *tx_desc, u16 i, 922 dma_addr_t dma, unsigned int size, u8 desc_flags) 923 { 924 /* set RS and INT for last frame in a cache line */ 925 if ((++i & (FM10K_TXD_WB_FIFO_SIZE - 1)) == 0) 926 desc_flags |= FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_INT; 927 928 /* record values to descriptor */ 929 tx_desc->buffer_addr = cpu_to_le64(dma); 930 tx_desc->flags = desc_flags; 931 tx_desc->buflen = cpu_to_le16(size); 932 933 /* return true if we just wrapped the ring */ 934 return i == tx_ring->count; 935 } 936 937 static int __fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) 938 { 939 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 940 941 /* Memory barrier before checking head and tail */ 942 smp_mb(); 943 944 /* Check again in a case another CPU has just made room available */ 945 if (likely(fm10k_desc_unused(tx_ring) < size)) 946 return -EBUSY; 947 948 /* A reprieve! - use start_queue because it doesn't call schedule */ 949 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 950 ++tx_ring->tx_stats.restart_queue; 951 return 0; 952 } 953 954 static inline int fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) 955 { 956 if (likely(fm10k_desc_unused(tx_ring) >= size)) 957 return 0; 958 return __fm10k_maybe_stop_tx(tx_ring, size); 959 } 960 961 static void fm10k_tx_map(struct fm10k_ring *tx_ring, 962 struct fm10k_tx_buffer *first) 963 { 964 struct sk_buff *skb = first->skb; 965 struct fm10k_tx_buffer *tx_buffer; 966 struct fm10k_tx_desc *tx_desc; 967 struct skb_frag_struct *frag; 968 unsigned char *data; 969 dma_addr_t dma; 970 unsigned int data_len, size; 971 u32 tx_flags = first->tx_flags; 972 u16 i = tx_ring->next_to_use; 973 u8 flags = fm10k_tx_desc_flags(skb, tx_flags); 974 975 tx_desc = FM10K_TX_DESC(tx_ring, i); 976 977 /* add HW VLAN tag */ 978 if (skb_vlan_tag_present(skb)) 979 tx_desc->vlan = cpu_to_le16(skb_vlan_tag_get(skb)); 980 else 981 tx_desc->vlan = 0; 982 983 size = skb_headlen(skb); 984 data = skb->data; 985 986 dma = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); 987 988 data_len = skb->data_len; 989 tx_buffer = first; 990 991 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 992 if (dma_mapping_error(tx_ring->dev, dma)) 993 goto dma_error; 994 995 /* record length, and DMA address */ 996 dma_unmap_len_set(tx_buffer, len, size); 997 dma_unmap_addr_set(tx_buffer, dma, dma); 998 999 while (unlikely(size > FM10K_MAX_DATA_PER_TXD)) { 1000 if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, dma, 1001 FM10K_MAX_DATA_PER_TXD, flags)) { 1002 tx_desc = FM10K_TX_DESC(tx_ring, 0); 1003 i = 0; 1004 } 1005 1006 dma += FM10K_MAX_DATA_PER_TXD; 1007 size -= FM10K_MAX_DATA_PER_TXD; 1008 } 1009 1010 if (likely(!data_len)) 1011 break; 1012 1013 if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, 1014 dma, size, flags)) { 1015 tx_desc = FM10K_TX_DESC(tx_ring, 0); 1016 i = 0; 1017 } 1018 1019 size = skb_frag_size(frag); 1020 data_len -= size; 1021 1022 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1023 DMA_TO_DEVICE); 1024 1025 tx_buffer = &tx_ring->tx_buffer[i]; 1026 } 1027 1028 /* write last descriptor with LAST bit set */ 1029 flags |= FM10K_TXD_FLAG_LAST; 1030 1031 if (fm10k_tx_desc_push(tx_ring, tx_desc, i++, dma, size, flags)) 1032 i = 0; 1033 1034 /* record bytecount for BQL */ 1035 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 1036 1037 /* record SW timestamp if HW timestamp is not available */ 1038 skb_tx_timestamp(first->skb); 1039 1040 /* Force memory writes to complete before letting h/w know there 1041 * are new descriptors to fetch. (Only applicable for weak-ordered 1042 * memory model archs, such as IA-64). 1043 * 1044 * We also need this memory barrier to make certain all of the 1045 * status bits have been updated before next_to_watch is written. 1046 */ 1047 wmb(); 1048 1049 /* set next_to_watch value indicating a packet is present */ 1050 first->next_to_watch = tx_desc; 1051 1052 tx_ring->next_to_use = i; 1053 1054 /* Make sure there is space in the ring for the next send. */ 1055 fm10k_maybe_stop_tx(tx_ring, DESC_NEEDED); 1056 1057 /* notify HW of packet */ 1058 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 1059 writel(i, tx_ring->tail); 1060 1061 /* we need this if more than one processor can write to our tail 1062 * at a time, it synchronizes IO on IA64/Altix systems 1063 */ 1064 mmiowb(); 1065 } 1066 1067 return; 1068 dma_error: 1069 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1070 1071 /* clear dma mappings for failed tx_buffer map */ 1072 for (;;) { 1073 tx_buffer = &tx_ring->tx_buffer[i]; 1074 fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1075 if (tx_buffer == first) 1076 break; 1077 if (i == 0) 1078 i = tx_ring->count; 1079 i--; 1080 } 1081 1082 tx_ring->next_to_use = i; 1083 } 1084 1085 netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb, 1086 struct fm10k_ring *tx_ring) 1087 { 1088 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1089 struct fm10k_tx_buffer *first; 1090 unsigned short f; 1091 u32 tx_flags = 0; 1092 int tso; 1093 1094 /* need: 1 descriptor per page * PAGE_SIZE/FM10K_MAX_DATA_PER_TXD, 1095 * + 1 desc for skb_headlen/FM10K_MAX_DATA_PER_TXD, 1096 * + 2 desc gap to keep tail from touching head 1097 * otherwise try next time 1098 */ 1099 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1100 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 1101 1102 if (fm10k_maybe_stop_tx(tx_ring, count + 3)) { 1103 tx_ring->tx_stats.tx_busy++; 1104 return NETDEV_TX_BUSY; 1105 } 1106 1107 /* record the location of the first descriptor for this packet */ 1108 first = &tx_ring->tx_buffer[tx_ring->next_to_use]; 1109 first->skb = skb; 1110 first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN); 1111 first->gso_segs = 1; 1112 1113 /* record initial flags and protocol */ 1114 first->tx_flags = tx_flags; 1115 1116 tso = fm10k_tso(tx_ring, first); 1117 if (tso < 0) 1118 goto out_drop; 1119 else if (!tso) 1120 fm10k_tx_csum(tx_ring, first); 1121 1122 fm10k_tx_map(tx_ring, first); 1123 1124 return NETDEV_TX_OK; 1125 1126 out_drop: 1127 dev_kfree_skb_any(first->skb); 1128 first->skb = NULL; 1129 1130 return NETDEV_TX_OK; 1131 } 1132 1133 static u64 fm10k_get_tx_completed(struct fm10k_ring *ring) 1134 { 1135 return ring->stats.packets; 1136 } 1137 1138 /** 1139 * fm10k_get_tx_pending - how many Tx descriptors not processed 1140 * @ring: the ring structure 1141 * @in_sw: is tx_pending being checked in SW or in HW? 1142 */ 1143 u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw) 1144 { 1145 struct fm10k_intfc *interface = ring->q_vector->interface; 1146 struct fm10k_hw *hw = &interface->hw; 1147 u32 head, tail; 1148 1149 if (likely(in_sw)) { 1150 head = ring->next_to_clean; 1151 tail = ring->next_to_use; 1152 } else { 1153 head = fm10k_read_reg(hw, FM10K_TDH(ring->reg_idx)); 1154 tail = fm10k_read_reg(hw, FM10K_TDT(ring->reg_idx)); 1155 } 1156 1157 return ((head <= tail) ? tail : tail + ring->count) - head; 1158 } 1159 1160 bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring) 1161 { 1162 u32 tx_done = fm10k_get_tx_completed(tx_ring); 1163 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1164 u32 tx_pending = fm10k_get_tx_pending(tx_ring, true); 1165 1166 clear_check_for_tx_hang(tx_ring); 1167 1168 /* Check for a hung queue, but be thorough. This verifies 1169 * that a transmit has been completed since the previous 1170 * check AND there is at least one packet pending. By 1171 * requiring this to fail twice we avoid races with 1172 * clearing the ARMED bit and conditions where we 1173 * run the check_tx_hang logic with a transmit completion 1174 * pending but without time to complete it yet. 1175 */ 1176 if (!tx_pending || (tx_done_old != tx_done)) { 1177 /* update completed stats and continue */ 1178 tx_ring->tx_stats.tx_done_old = tx_done; 1179 /* reset the countdown */ 1180 clear_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state); 1181 1182 return false; 1183 } 1184 1185 /* make sure it is true for two checks in a row */ 1186 return test_and_set_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state); 1187 } 1188 1189 /** 1190 * fm10k_tx_timeout_reset - initiate reset due to Tx timeout 1191 * @interface: driver private struct 1192 **/ 1193 void fm10k_tx_timeout_reset(struct fm10k_intfc *interface) 1194 { 1195 /* Do the reset outside of interrupt context */ 1196 if (!test_bit(__FM10K_DOWN, interface->state)) { 1197 interface->tx_timeout_count++; 1198 set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags); 1199 fm10k_service_event_schedule(interface); 1200 } 1201 } 1202 1203 /** 1204 * fm10k_clean_tx_irq - Reclaim resources after transmit completes 1205 * @q_vector: structure containing interrupt and ring information 1206 * @tx_ring: tx ring to clean 1207 * @napi_budget: Used to determine if we are in netpoll 1208 **/ 1209 static bool fm10k_clean_tx_irq(struct fm10k_q_vector *q_vector, 1210 struct fm10k_ring *tx_ring, int napi_budget) 1211 { 1212 struct fm10k_intfc *interface = q_vector->interface; 1213 struct fm10k_tx_buffer *tx_buffer; 1214 struct fm10k_tx_desc *tx_desc; 1215 unsigned int total_bytes = 0, total_packets = 0; 1216 unsigned int budget = q_vector->tx.work_limit; 1217 unsigned int i = tx_ring->next_to_clean; 1218 1219 if (test_bit(__FM10K_DOWN, interface->state)) 1220 return true; 1221 1222 tx_buffer = &tx_ring->tx_buffer[i]; 1223 tx_desc = FM10K_TX_DESC(tx_ring, i); 1224 i -= tx_ring->count; 1225 1226 do { 1227 struct fm10k_tx_desc *eop_desc = tx_buffer->next_to_watch; 1228 1229 /* if next_to_watch is not set then there is no work pending */ 1230 if (!eop_desc) 1231 break; 1232 1233 /* prevent any other reads prior to eop_desc */ 1234 smp_rmb(); 1235 1236 /* if DD is not set pending work has not been completed */ 1237 if (!(eop_desc->flags & FM10K_TXD_FLAG_DONE)) 1238 break; 1239 1240 /* clear next_to_watch to prevent false hangs */ 1241 tx_buffer->next_to_watch = NULL; 1242 1243 /* update the statistics for this packet */ 1244 total_bytes += tx_buffer->bytecount; 1245 total_packets += tx_buffer->gso_segs; 1246 1247 /* free the skb */ 1248 napi_consume_skb(tx_buffer->skb, napi_budget); 1249 1250 /* unmap skb header data */ 1251 dma_unmap_single(tx_ring->dev, 1252 dma_unmap_addr(tx_buffer, dma), 1253 dma_unmap_len(tx_buffer, len), 1254 DMA_TO_DEVICE); 1255 1256 /* clear tx_buffer data */ 1257 tx_buffer->skb = NULL; 1258 dma_unmap_len_set(tx_buffer, len, 0); 1259 1260 /* unmap remaining buffers */ 1261 while (tx_desc != eop_desc) { 1262 tx_buffer++; 1263 tx_desc++; 1264 i++; 1265 if (unlikely(!i)) { 1266 i -= tx_ring->count; 1267 tx_buffer = tx_ring->tx_buffer; 1268 tx_desc = FM10K_TX_DESC(tx_ring, 0); 1269 } 1270 1271 /* unmap any remaining paged data */ 1272 if (dma_unmap_len(tx_buffer, len)) { 1273 dma_unmap_page(tx_ring->dev, 1274 dma_unmap_addr(tx_buffer, dma), 1275 dma_unmap_len(tx_buffer, len), 1276 DMA_TO_DEVICE); 1277 dma_unmap_len_set(tx_buffer, len, 0); 1278 } 1279 } 1280 1281 /* move us one more past the eop_desc for start of next pkt */ 1282 tx_buffer++; 1283 tx_desc++; 1284 i++; 1285 if (unlikely(!i)) { 1286 i -= tx_ring->count; 1287 tx_buffer = tx_ring->tx_buffer; 1288 tx_desc = FM10K_TX_DESC(tx_ring, 0); 1289 } 1290 1291 /* issue prefetch for next Tx descriptor */ 1292 prefetch(tx_desc); 1293 1294 /* update budget accounting */ 1295 budget--; 1296 } while (likely(budget)); 1297 1298 i += tx_ring->count; 1299 tx_ring->next_to_clean = i; 1300 u64_stats_update_begin(&tx_ring->syncp); 1301 tx_ring->stats.bytes += total_bytes; 1302 tx_ring->stats.packets += total_packets; 1303 u64_stats_update_end(&tx_ring->syncp); 1304 q_vector->tx.total_bytes += total_bytes; 1305 q_vector->tx.total_packets += total_packets; 1306 1307 if (check_for_tx_hang(tx_ring) && fm10k_check_tx_hang(tx_ring)) { 1308 /* schedule immediate reset if we believe we hung */ 1309 struct fm10k_hw *hw = &interface->hw; 1310 1311 netif_err(interface, drv, tx_ring->netdev, 1312 "Detected Tx Unit Hang\n" 1313 " Tx Queue <%d>\n" 1314 " TDH, TDT <%x>, <%x>\n" 1315 " next_to_use <%x>\n" 1316 " next_to_clean <%x>\n", 1317 tx_ring->queue_index, 1318 fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)), 1319 fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)), 1320 tx_ring->next_to_use, i); 1321 1322 netif_stop_subqueue(tx_ring->netdev, 1323 tx_ring->queue_index); 1324 1325 netif_info(interface, probe, tx_ring->netdev, 1326 "tx hang %d detected on queue %d, resetting interface\n", 1327 interface->tx_timeout_count + 1, 1328 tx_ring->queue_index); 1329 1330 fm10k_tx_timeout_reset(interface); 1331 1332 /* the netdev is about to reset, no point in enabling stuff */ 1333 return true; 1334 } 1335 1336 /* notify netdev of completed buffers */ 1337 netdev_tx_completed_queue(txring_txq(tx_ring), 1338 total_packets, total_bytes); 1339 1340 #define TX_WAKE_THRESHOLD min_t(u16, FM10K_MIN_TXD - 1, DESC_NEEDED * 2) 1341 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1342 (fm10k_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1343 /* Make sure that anybody stopping the queue after this 1344 * sees the new next_to_clean. 1345 */ 1346 smp_mb(); 1347 if (__netif_subqueue_stopped(tx_ring->netdev, 1348 tx_ring->queue_index) && 1349 !test_bit(__FM10K_DOWN, interface->state)) { 1350 netif_wake_subqueue(tx_ring->netdev, 1351 tx_ring->queue_index); 1352 ++tx_ring->tx_stats.restart_queue; 1353 } 1354 } 1355 1356 return !!budget; 1357 } 1358 1359 /** 1360 * fm10k_update_itr - update the dynamic ITR value based on packet size 1361 * 1362 * Stores a new ITR value based on strictly on packet size. The 1363 * divisors and thresholds used by this function were determined based 1364 * on theoretical maximum wire speed and testing data, in order to 1365 * minimize response time while increasing bulk throughput. 1366 * 1367 * @ring_container: Container for rings to have ITR updated 1368 **/ 1369 static void fm10k_update_itr(struct fm10k_ring_container *ring_container) 1370 { 1371 unsigned int avg_wire_size, packets, itr_round; 1372 1373 /* Only update ITR if we are using adaptive setting */ 1374 if (!ITR_IS_ADAPTIVE(ring_container->itr)) 1375 goto clear_counts; 1376 1377 packets = ring_container->total_packets; 1378 if (!packets) 1379 goto clear_counts; 1380 1381 avg_wire_size = ring_container->total_bytes / packets; 1382 1383 /* The following is a crude approximation of: 1384 * wmem_default / (size + overhead) = desired_pkts_per_int 1385 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 1386 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 1387 * 1388 * Assuming wmem_default is 212992 and overhead is 640 bytes per 1389 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 1390 * formula down to 1391 * 1392 * (34 * (size + 24)) / (size + 640) = ITR 1393 * 1394 * We first do some math on the packet size and then finally bitshift 1395 * by 8 after rounding up. We also have to account for PCIe link speed 1396 * difference as ITR scales based on this. 1397 */ 1398 if (avg_wire_size <= 360) { 1399 /* Start at 250K ints/sec and gradually drop to 77K ints/sec */ 1400 avg_wire_size *= 8; 1401 avg_wire_size += 376; 1402 } else if (avg_wire_size <= 1152) { 1403 /* 77K ints/sec to 45K ints/sec */ 1404 avg_wire_size *= 3; 1405 avg_wire_size += 2176; 1406 } else if (avg_wire_size <= 1920) { 1407 /* 45K ints/sec to 38K ints/sec */ 1408 avg_wire_size += 4480; 1409 } else { 1410 /* plateau at a limit of 38K ints/sec */ 1411 avg_wire_size = 6656; 1412 } 1413 1414 /* Perform final bitshift for division after rounding up to ensure 1415 * that the calculation will never get below a 1. The bit shift 1416 * accounts for changes in the ITR due to PCIe link speed. 1417 */ 1418 itr_round = READ_ONCE(ring_container->itr_scale) + 8; 1419 avg_wire_size += BIT(itr_round) - 1; 1420 avg_wire_size >>= itr_round; 1421 1422 /* write back value and retain adaptive flag */ 1423 ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE; 1424 1425 clear_counts: 1426 ring_container->total_bytes = 0; 1427 ring_container->total_packets = 0; 1428 } 1429 1430 static void fm10k_qv_enable(struct fm10k_q_vector *q_vector) 1431 { 1432 /* Enable auto-mask and clear the current mask */ 1433 u32 itr = FM10K_ITR_ENABLE; 1434 1435 /* Update Tx ITR */ 1436 fm10k_update_itr(&q_vector->tx); 1437 1438 /* Update Rx ITR */ 1439 fm10k_update_itr(&q_vector->rx); 1440 1441 /* Store Tx itr in timer slot 0 */ 1442 itr |= (q_vector->tx.itr & FM10K_ITR_MAX); 1443 1444 /* Shift Rx itr to timer slot 1 */ 1445 itr |= (q_vector->rx.itr & FM10K_ITR_MAX) << FM10K_ITR_INTERVAL1_SHIFT; 1446 1447 /* Write the final value to the ITR register */ 1448 writel(itr, q_vector->itr); 1449 } 1450 1451 static int fm10k_poll(struct napi_struct *napi, int budget) 1452 { 1453 struct fm10k_q_vector *q_vector = 1454 container_of(napi, struct fm10k_q_vector, napi); 1455 struct fm10k_ring *ring; 1456 int per_ring_budget, work_done = 0; 1457 bool clean_complete = true; 1458 1459 fm10k_for_each_ring(ring, q_vector->tx) { 1460 if (!fm10k_clean_tx_irq(q_vector, ring, budget)) 1461 clean_complete = false; 1462 } 1463 1464 /* Handle case where we are called by netpoll with a budget of 0 */ 1465 if (budget <= 0) 1466 return budget; 1467 1468 /* attempt to distribute budget to each queue fairly, but don't 1469 * allow the budget to go below 1 because we'll exit polling 1470 */ 1471 if (q_vector->rx.count > 1) 1472 per_ring_budget = max(budget / q_vector->rx.count, 1); 1473 else 1474 per_ring_budget = budget; 1475 1476 fm10k_for_each_ring(ring, q_vector->rx) { 1477 int work = fm10k_clean_rx_irq(q_vector, ring, per_ring_budget); 1478 1479 work_done += work; 1480 if (work >= per_ring_budget) 1481 clean_complete = false; 1482 } 1483 1484 /* If all work not completed, return budget and keep polling */ 1485 if (!clean_complete) 1486 return budget; 1487 1488 /* all work done, exit the polling mode */ 1489 napi_complete_done(napi, work_done); 1490 1491 /* re-enable the q_vector */ 1492 fm10k_qv_enable(q_vector); 1493 1494 return min(work_done, budget - 1); 1495 } 1496 1497 /** 1498 * fm10k_set_qos_queues: Allocate queues for a QOS-enabled device 1499 * @interface: board private structure to initialize 1500 * 1501 * When QoS (Quality of Service) is enabled, allocate queues for 1502 * each traffic class. If multiqueue isn't available,then abort QoS 1503 * initialization. 1504 * 1505 * This function handles all combinations of Qos and RSS. 1506 * 1507 **/ 1508 static bool fm10k_set_qos_queues(struct fm10k_intfc *interface) 1509 { 1510 struct net_device *dev = interface->netdev; 1511 struct fm10k_ring_feature *f; 1512 int rss_i, i; 1513 int pcs; 1514 1515 /* Map queue offset and counts onto allocated tx queues */ 1516 pcs = netdev_get_num_tc(dev); 1517 1518 if (pcs <= 1) 1519 return false; 1520 1521 /* set QoS mask and indices */ 1522 f = &interface->ring_feature[RING_F_QOS]; 1523 f->indices = pcs; 1524 f->mask = BIT(fls(pcs - 1)) - 1; 1525 1526 /* determine the upper limit for our current DCB mode */ 1527 rss_i = interface->hw.mac.max_queues / pcs; 1528 rss_i = BIT(fls(rss_i) - 1); 1529 1530 /* set RSS mask and indices */ 1531 f = &interface->ring_feature[RING_F_RSS]; 1532 rss_i = min_t(u16, rss_i, f->limit); 1533 f->indices = rss_i; 1534 f->mask = BIT(fls(rss_i - 1)) - 1; 1535 1536 /* configure pause class to queue mapping */ 1537 for (i = 0; i < pcs; i++) 1538 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 1539 1540 interface->num_rx_queues = rss_i * pcs; 1541 interface->num_tx_queues = rss_i * pcs; 1542 1543 return true; 1544 } 1545 1546 /** 1547 * fm10k_set_rss_queues: Allocate queues for RSS 1548 * @interface: board private structure to initialize 1549 * 1550 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1551 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1552 * 1553 **/ 1554 static bool fm10k_set_rss_queues(struct fm10k_intfc *interface) 1555 { 1556 struct fm10k_ring_feature *f; 1557 u16 rss_i; 1558 1559 f = &interface->ring_feature[RING_F_RSS]; 1560 rss_i = min_t(u16, interface->hw.mac.max_queues, f->limit); 1561 1562 /* record indices and power of 2 mask for RSS */ 1563 f->indices = rss_i; 1564 f->mask = BIT(fls(rss_i - 1)) - 1; 1565 1566 interface->num_rx_queues = rss_i; 1567 interface->num_tx_queues = rss_i; 1568 1569 return true; 1570 } 1571 1572 /** 1573 * fm10k_set_num_queues: Allocate queues for device, feature dependent 1574 * @interface: board private structure to initialize 1575 * 1576 * This is the top level queue allocation routine. The order here is very 1577 * important, starting with the "most" number of features turned on at once, 1578 * and ending with the smallest set of features. This way large combinations 1579 * can be allocated if they're turned on, and smaller combinations are the 1580 * fallthrough conditions. 1581 * 1582 **/ 1583 static void fm10k_set_num_queues(struct fm10k_intfc *interface) 1584 { 1585 /* Attempt to setup QoS and RSS first */ 1586 if (fm10k_set_qos_queues(interface)) 1587 return; 1588 1589 /* If we don't have QoS, just fallback to only RSS. */ 1590 fm10k_set_rss_queues(interface); 1591 } 1592 1593 /** 1594 * fm10k_reset_num_queues - Reset the number of queues to zero 1595 * @interface: board private structure 1596 * 1597 * This function should be called whenever we need to reset the number of 1598 * queues after an error condition. 1599 */ 1600 static void fm10k_reset_num_queues(struct fm10k_intfc *interface) 1601 { 1602 interface->num_tx_queues = 0; 1603 interface->num_rx_queues = 0; 1604 interface->num_q_vectors = 0; 1605 } 1606 1607 /** 1608 * fm10k_alloc_q_vector - Allocate memory for a single interrupt vector 1609 * @interface: board private structure to initialize 1610 * @v_count: q_vectors allocated on interface, used for ring interleaving 1611 * @v_idx: index of vector in interface struct 1612 * @txr_count: total number of Tx rings to allocate 1613 * @txr_idx: index of first Tx ring to allocate 1614 * @rxr_count: total number of Rx rings to allocate 1615 * @rxr_idx: index of first Rx ring to allocate 1616 * 1617 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1618 **/ 1619 static int fm10k_alloc_q_vector(struct fm10k_intfc *interface, 1620 unsigned int v_count, unsigned int v_idx, 1621 unsigned int txr_count, unsigned int txr_idx, 1622 unsigned int rxr_count, unsigned int rxr_idx) 1623 { 1624 struct fm10k_q_vector *q_vector; 1625 struct fm10k_ring *ring; 1626 int ring_count, size; 1627 1628 ring_count = txr_count + rxr_count; 1629 size = sizeof(struct fm10k_q_vector) + 1630 (sizeof(struct fm10k_ring) * ring_count); 1631 1632 /* allocate q_vector and rings */ 1633 q_vector = kzalloc(size, GFP_KERNEL); 1634 if (!q_vector) 1635 return -ENOMEM; 1636 1637 /* initialize NAPI */ 1638 netif_napi_add(interface->netdev, &q_vector->napi, 1639 fm10k_poll, NAPI_POLL_WEIGHT); 1640 1641 /* tie q_vector and interface together */ 1642 interface->q_vector[v_idx] = q_vector; 1643 q_vector->interface = interface; 1644 q_vector->v_idx = v_idx; 1645 1646 /* initialize pointer to rings */ 1647 ring = q_vector->ring; 1648 1649 /* save Tx ring container info */ 1650 q_vector->tx.ring = ring; 1651 q_vector->tx.work_limit = FM10K_DEFAULT_TX_WORK; 1652 q_vector->tx.itr = interface->tx_itr; 1653 q_vector->tx.itr_scale = interface->hw.mac.itr_scale; 1654 q_vector->tx.count = txr_count; 1655 1656 while (txr_count) { 1657 /* assign generic ring traits */ 1658 ring->dev = &interface->pdev->dev; 1659 ring->netdev = interface->netdev; 1660 1661 /* configure backlink on ring */ 1662 ring->q_vector = q_vector; 1663 1664 /* apply Tx specific ring traits */ 1665 ring->count = interface->tx_ring_count; 1666 ring->queue_index = txr_idx; 1667 1668 /* assign ring to interface */ 1669 interface->tx_ring[txr_idx] = ring; 1670 1671 /* update count and index */ 1672 txr_count--; 1673 txr_idx += v_count; 1674 1675 /* push pointer to next ring */ 1676 ring++; 1677 } 1678 1679 /* save Rx ring container info */ 1680 q_vector->rx.ring = ring; 1681 q_vector->rx.itr = interface->rx_itr; 1682 q_vector->rx.itr_scale = interface->hw.mac.itr_scale; 1683 q_vector->rx.count = rxr_count; 1684 1685 while (rxr_count) { 1686 /* assign generic ring traits */ 1687 ring->dev = &interface->pdev->dev; 1688 ring->netdev = interface->netdev; 1689 rcu_assign_pointer(ring->l2_accel, interface->l2_accel); 1690 1691 /* configure backlink on ring */ 1692 ring->q_vector = q_vector; 1693 1694 /* apply Rx specific ring traits */ 1695 ring->count = interface->rx_ring_count; 1696 ring->queue_index = rxr_idx; 1697 1698 /* assign ring to interface */ 1699 interface->rx_ring[rxr_idx] = ring; 1700 1701 /* update count and index */ 1702 rxr_count--; 1703 rxr_idx += v_count; 1704 1705 /* push pointer to next ring */ 1706 ring++; 1707 } 1708 1709 fm10k_dbg_q_vector_init(q_vector); 1710 1711 return 0; 1712 } 1713 1714 /** 1715 * fm10k_free_q_vector - Free memory allocated for specific interrupt vector 1716 * @interface: board private structure to initialize 1717 * @v_idx: Index of vector to be freed 1718 * 1719 * This function frees the memory allocated to the q_vector. In addition if 1720 * NAPI is enabled it will delete any references to the NAPI struct prior 1721 * to freeing the q_vector. 1722 **/ 1723 static void fm10k_free_q_vector(struct fm10k_intfc *interface, int v_idx) 1724 { 1725 struct fm10k_q_vector *q_vector = interface->q_vector[v_idx]; 1726 struct fm10k_ring *ring; 1727 1728 fm10k_dbg_q_vector_exit(q_vector); 1729 1730 fm10k_for_each_ring(ring, q_vector->tx) 1731 interface->tx_ring[ring->queue_index] = NULL; 1732 1733 fm10k_for_each_ring(ring, q_vector->rx) 1734 interface->rx_ring[ring->queue_index] = NULL; 1735 1736 interface->q_vector[v_idx] = NULL; 1737 netif_napi_del(&q_vector->napi); 1738 kfree_rcu(q_vector, rcu); 1739 } 1740 1741 /** 1742 * fm10k_alloc_q_vectors - Allocate memory for interrupt vectors 1743 * @interface: board private structure to initialize 1744 * 1745 * We allocate one q_vector per queue interrupt. If allocation fails we 1746 * return -ENOMEM. 1747 **/ 1748 static int fm10k_alloc_q_vectors(struct fm10k_intfc *interface) 1749 { 1750 unsigned int q_vectors = interface->num_q_vectors; 1751 unsigned int rxr_remaining = interface->num_rx_queues; 1752 unsigned int txr_remaining = interface->num_tx_queues; 1753 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1754 int err; 1755 1756 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1757 for (; rxr_remaining; v_idx++) { 1758 err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, 1759 0, 0, 1, rxr_idx); 1760 if (err) 1761 goto err_out; 1762 1763 /* update counts and index */ 1764 rxr_remaining--; 1765 rxr_idx++; 1766 } 1767 } 1768 1769 for (; v_idx < q_vectors; v_idx++) { 1770 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1771 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1772 1773 err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, 1774 tqpv, txr_idx, 1775 rqpv, rxr_idx); 1776 1777 if (err) 1778 goto err_out; 1779 1780 /* update counts and index */ 1781 rxr_remaining -= rqpv; 1782 txr_remaining -= tqpv; 1783 rxr_idx++; 1784 txr_idx++; 1785 } 1786 1787 return 0; 1788 1789 err_out: 1790 fm10k_reset_num_queues(interface); 1791 1792 while (v_idx--) 1793 fm10k_free_q_vector(interface, v_idx); 1794 1795 return -ENOMEM; 1796 } 1797 1798 /** 1799 * fm10k_free_q_vectors - Free memory allocated for interrupt vectors 1800 * @interface: board private structure to initialize 1801 * 1802 * This function frees the memory allocated to the q_vectors. In addition if 1803 * NAPI is enabled it will delete any references to the NAPI struct prior 1804 * to freeing the q_vector. 1805 **/ 1806 static void fm10k_free_q_vectors(struct fm10k_intfc *interface) 1807 { 1808 int v_idx = interface->num_q_vectors; 1809 1810 fm10k_reset_num_queues(interface); 1811 1812 while (v_idx--) 1813 fm10k_free_q_vector(interface, v_idx); 1814 } 1815 1816 /** 1817 * f10k_reset_msix_capability - reset MSI-X capability 1818 * @interface: board private structure to initialize 1819 * 1820 * Reset the MSI-X capability back to its starting state 1821 **/ 1822 static void fm10k_reset_msix_capability(struct fm10k_intfc *interface) 1823 { 1824 pci_disable_msix(interface->pdev); 1825 kfree(interface->msix_entries); 1826 interface->msix_entries = NULL; 1827 } 1828 1829 /** 1830 * f10k_init_msix_capability - configure MSI-X capability 1831 * @interface: board private structure to initialize 1832 * 1833 * Attempt to configure the interrupts using the best available 1834 * capabilities of the hardware and the kernel. 1835 **/ 1836 static int fm10k_init_msix_capability(struct fm10k_intfc *interface) 1837 { 1838 struct fm10k_hw *hw = &interface->hw; 1839 int v_budget, vector; 1840 1841 /* It's easy to be greedy for MSI-X vectors, but it really 1842 * doesn't do us much good if we have a lot more vectors 1843 * than CPU's. So let's be conservative and only ask for 1844 * (roughly) the same number of vectors as there are CPU's. 1845 * the default is to use pairs of vectors 1846 */ 1847 v_budget = max(interface->num_rx_queues, interface->num_tx_queues); 1848 v_budget = min_t(u16, v_budget, num_online_cpus()); 1849 1850 /* account for vectors not related to queues */ 1851 v_budget += NON_Q_VECTORS(hw); 1852 1853 /* At the same time, hardware can only support a maximum of 1854 * hw.mac->max_msix_vectors vectors. With features 1855 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 1856 * descriptor queues supported by our device. Thus, we cap it off in 1857 * those rare cases where the cpu count also exceeds our vector limit. 1858 */ 1859 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 1860 1861 /* A failure in MSI-X entry allocation is fatal. */ 1862 interface->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), 1863 GFP_KERNEL); 1864 if (!interface->msix_entries) 1865 return -ENOMEM; 1866 1867 /* populate entry values */ 1868 for (vector = 0; vector < v_budget; vector++) 1869 interface->msix_entries[vector].entry = vector; 1870 1871 /* Attempt to enable MSI-X with requested value */ 1872 v_budget = pci_enable_msix_range(interface->pdev, 1873 interface->msix_entries, 1874 MIN_MSIX_COUNT(hw), 1875 v_budget); 1876 if (v_budget < 0) { 1877 kfree(interface->msix_entries); 1878 interface->msix_entries = NULL; 1879 return v_budget; 1880 } 1881 1882 /* record the number of queues available for q_vectors */ 1883 interface->num_q_vectors = v_budget - NON_Q_VECTORS(hw); 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * fm10k_cache_ring_qos - Descriptor ring to register mapping for QoS 1890 * @interface: Interface structure continaining rings and devices 1891 * 1892 * Cache the descriptor ring offsets for Qos 1893 **/ 1894 static bool fm10k_cache_ring_qos(struct fm10k_intfc *interface) 1895 { 1896 struct net_device *dev = interface->netdev; 1897 int pc, offset, rss_i, i, q_idx; 1898 u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1; 1899 u8 num_pcs = netdev_get_num_tc(dev); 1900 1901 if (num_pcs <= 1) 1902 return false; 1903 1904 rss_i = interface->ring_feature[RING_F_RSS].indices; 1905 1906 for (pc = 0, offset = 0; pc < num_pcs; pc++, offset += rss_i) { 1907 q_idx = pc; 1908 for (i = 0; i < rss_i; i++) { 1909 interface->tx_ring[offset + i]->reg_idx = q_idx; 1910 interface->tx_ring[offset + i]->qos_pc = pc; 1911 interface->rx_ring[offset + i]->reg_idx = q_idx; 1912 interface->rx_ring[offset + i]->qos_pc = pc; 1913 q_idx += pc_stride; 1914 } 1915 } 1916 1917 return true; 1918 } 1919 1920 /** 1921 * fm10k_cache_ring_rss - Descriptor ring to register mapping for RSS 1922 * @interface: Interface structure continaining rings and devices 1923 * 1924 * Cache the descriptor ring offsets for RSS 1925 **/ 1926 static void fm10k_cache_ring_rss(struct fm10k_intfc *interface) 1927 { 1928 int i; 1929 1930 for (i = 0; i < interface->num_rx_queues; i++) 1931 interface->rx_ring[i]->reg_idx = i; 1932 1933 for (i = 0; i < interface->num_tx_queues; i++) 1934 interface->tx_ring[i]->reg_idx = i; 1935 } 1936 1937 /** 1938 * fm10k_assign_rings - Map rings to network devices 1939 * @interface: Interface structure containing rings and devices 1940 * 1941 * This function is meant to go though and configure both the network 1942 * devices so that they contain rings, and configure the rings so that 1943 * they function with their network devices. 1944 **/ 1945 static void fm10k_assign_rings(struct fm10k_intfc *interface) 1946 { 1947 if (fm10k_cache_ring_qos(interface)) 1948 return; 1949 1950 fm10k_cache_ring_rss(interface); 1951 } 1952 1953 static void fm10k_init_reta(struct fm10k_intfc *interface) 1954 { 1955 u16 i, rss_i = interface->ring_feature[RING_F_RSS].indices; 1956 u32 reta; 1957 1958 /* If the Rx flow indirection table has been configured manually, we 1959 * need to maintain it when possible. 1960 */ 1961 if (netif_is_rxfh_configured(interface->netdev)) { 1962 for (i = FM10K_RETA_SIZE; i--;) { 1963 reta = interface->reta[i]; 1964 if ((((reta << 24) >> 24) < rss_i) && 1965 (((reta << 16) >> 24) < rss_i) && 1966 (((reta << 8) >> 24) < rss_i) && 1967 (((reta) >> 24) < rss_i)) 1968 continue; 1969 1970 /* this should never happen */ 1971 dev_err(&interface->pdev->dev, 1972 "RSS indirection table assigned flows out of queue bounds. Reconfiguring.\n"); 1973 goto repopulate_reta; 1974 } 1975 1976 /* do nothing if all of the elements are in bounds */ 1977 return; 1978 } 1979 1980 repopulate_reta: 1981 fm10k_write_reta(interface, NULL); 1982 } 1983 1984 /** 1985 * fm10k_init_queueing_scheme - Determine proper queueing scheme 1986 * @interface: board private structure to initialize 1987 * 1988 * We determine which queueing scheme to use based on... 1989 * - Hardware queue count (num_*_queues) 1990 * - defined by miscellaneous hardware support/features (RSS, etc.) 1991 **/ 1992 int fm10k_init_queueing_scheme(struct fm10k_intfc *interface) 1993 { 1994 int err; 1995 1996 /* Number of supported queues */ 1997 fm10k_set_num_queues(interface); 1998 1999 /* Configure MSI-X capability */ 2000 err = fm10k_init_msix_capability(interface); 2001 if (err) { 2002 dev_err(&interface->pdev->dev, 2003 "Unable to initialize MSI-X capability\n"); 2004 goto err_init_msix; 2005 } 2006 2007 /* Allocate memory for queues */ 2008 err = fm10k_alloc_q_vectors(interface); 2009 if (err) { 2010 dev_err(&interface->pdev->dev, 2011 "Unable to allocate queue vectors\n"); 2012 goto err_alloc_q_vectors; 2013 } 2014 2015 /* Map rings to devices, and map devices to physical queues */ 2016 fm10k_assign_rings(interface); 2017 2018 /* Initialize RSS redirection table */ 2019 fm10k_init_reta(interface); 2020 2021 return 0; 2022 2023 err_alloc_q_vectors: 2024 fm10k_reset_msix_capability(interface); 2025 err_init_msix: 2026 fm10k_reset_num_queues(interface); 2027 return err; 2028 } 2029 2030 /** 2031 * fm10k_clear_queueing_scheme - Clear the current queueing scheme settings 2032 * @interface: board private structure to clear queueing scheme on 2033 * 2034 * We go through and clear queueing specific resources and reset the structure 2035 * to pre-load conditions 2036 **/ 2037 void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface) 2038 { 2039 fm10k_free_q_vectors(interface); 2040 fm10k_reset_msix_capability(interface); 2041 } 2042