1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
3 
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <net/ipv6.h>
7 #include <net/ip.h>
8 #include <net/tcp.h>
9 #include <linux/if_macvlan.h>
10 #include <linux/prefetch.h>
11 
12 #include "fm10k.h"
13 
14 #define DRV_SUMMARY	"Intel(R) Ethernet Switch Host Interface Driver"
15 char fm10k_driver_name[] = "fm10k";
16 static const char fm10k_driver_string[] = DRV_SUMMARY;
17 static const char fm10k_copyright[] =
18 	"Copyright(c) 2013 - 2019 Intel Corporation.";
19 
20 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
21 MODULE_DESCRIPTION(DRV_SUMMARY);
22 MODULE_LICENSE("GPL v2");
23 
24 /* single workqueue for entire fm10k driver */
25 struct workqueue_struct *fm10k_workqueue;
26 
27 /**
28  * fm10k_init_module - Driver Registration Routine
29  *
30  * fm10k_init_module is the first routine called when the driver is
31  * loaded.  All it does is register with the PCI subsystem.
32  **/
33 static int __init fm10k_init_module(void)
34 {
35 	pr_info("%s\n", fm10k_driver_string);
36 	pr_info("%s\n", fm10k_copyright);
37 
38 	/* create driver workqueue */
39 	fm10k_workqueue = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0,
40 					  fm10k_driver_name);
41 	if (!fm10k_workqueue)
42 		return -ENOMEM;
43 
44 	fm10k_dbg_init();
45 
46 	return fm10k_register_pci_driver();
47 }
48 module_init(fm10k_init_module);
49 
50 /**
51  * fm10k_exit_module - Driver Exit Cleanup Routine
52  *
53  * fm10k_exit_module is called just before the driver is removed
54  * from memory.
55  **/
56 static void __exit fm10k_exit_module(void)
57 {
58 	fm10k_unregister_pci_driver();
59 
60 	fm10k_dbg_exit();
61 
62 	/* destroy driver workqueue */
63 	destroy_workqueue(fm10k_workqueue);
64 }
65 module_exit(fm10k_exit_module);
66 
67 static bool fm10k_alloc_mapped_page(struct fm10k_ring *rx_ring,
68 				    struct fm10k_rx_buffer *bi)
69 {
70 	struct page *page = bi->page;
71 	dma_addr_t dma;
72 
73 	/* Only page will be NULL if buffer was consumed */
74 	if (likely(page))
75 		return true;
76 
77 	/* alloc new page for storage */
78 	page = dev_alloc_page();
79 	if (unlikely(!page)) {
80 		rx_ring->rx_stats.alloc_failed++;
81 		return false;
82 	}
83 
84 	/* map page for use */
85 	dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
86 
87 	/* if mapping failed free memory back to system since
88 	 * there isn't much point in holding memory we can't use
89 	 */
90 	if (dma_mapping_error(rx_ring->dev, dma)) {
91 		__free_page(page);
92 
93 		rx_ring->rx_stats.alloc_failed++;
94 		return false;
95 	}
96 
97 	bi->dma = dma;
98 	bi->page = page;
99 	bi->page_offset = 0;
100 
101 	return true;
102 }
103 
104 /**
105  * fm10k_alloc_rx_buffers - Replace used receive buffers
106  * @rx_ring: ring to place buffers on
107  * @cleaned_count: number of buffers to replace
108  **/
109 void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count)
110 {
111 	union fm10k_rx_desc *rx_desc;
112 	struct fm10k_rx_buffer *bi;
113 	u16 i = rx_ring->next_to_use;
114 
115 	/* nothing to do */
116 	if (!cleaned_count)
117 		return;
118 
119 	rx_desc = FM10K_RX_DESC(rx_ring, i);
120 	bi = &rx_ring->rx_buffer[i];
121 	i -= rx_ring->count;
122 
123 	do {
124 		if (!fm10k_alloc_mapped_page(rx_ring, bi))
125 			break;
126 
127 		/* Refresh the desc even if buffer_addrs didn't change
128 		 * because each write-back erases this info.
129 		 */
130 		rx_desc->q.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
131 
132 		rx_desc++;
133 		bi++;
134 		i++;
135 		if (unlikely(!i)) {
136 			rx_desc = FM10K_RX_DESC(rx_ring, 0);
137 			bi = rx_ring->rx_buffer;
138 			i -= rx_ring->count;
139 		}
140 
141 		/* clear the status bits for the next_to_use descriptor */
142 		rx_desc->d.staterr = 0;
143 
144 		cleaned_count--;
145 	} while (cleaned_count);
146 
147 	i += rx_ring->count;
148 
149 	if (rx_ring->next_to_use != i) {
150 		/* record the next descriptor to use */
151 		rx_ring->next_to_use = i;
152 
153 		/* update next to alloc since we have filled the ring */
154 		rx_ring->next_to_alloc = i;
155 
156 		/* Force memory writes to complete before letting h/w
157 		 * know there are new descriptors to fetch.  (Only
158 		 * applicable for weak-ordered memory model archs,
159 		 * such as IA-64).
160 		 */
161 		wmb();
162 
163 		/* notify hardware of new descriptors */
164 		writel(i, rx_ring->tail);
165 	}
166 }
167 
168 /**
169  * fm10k_reuse_rx_page - page flip buffer and store it back on the ring
170  * @rx_ring: rx descriptor ring to store buffers on
171  * @old_buff: donor buffer to have page reused
172  *
173  * Synchronizes page for reuse by the interface
174  **/
175 static void fm10k_reuse_rx_page(struct fm10k_ring *rx_ring,
176 				struct fm10k_rx_buffer *old_buff)
177 {
178 	struct fm10k_rx_buffer *new_buff;
179 	u16 nta = rx_ring->next_to_alloc;
180 
181 	new_buff = &rx_ring->rx_buffer[nta];
182 
183 	/* update, and store next to alloc */
184 	nta++;
185 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
186 
187 	/* transfer page from old buffer to new buffer */
188 	*new_buff = *old_buff;
189 
190 	/* sync the buffer for use by the device */
191 	dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
192 					 old_buff->page_offset,
193 					 FM10K_RX_BUFSZ,
194 					 DMA_FROM_DEVICE);
195 }
196 
197 static bool fm10k_can_reuse_rx_page(struct fm10k_rx_buffer *rx_buffer,
198 				    struct page *page,
199 				    unsigned int __maybe_unused truesize)
200 {
201 	/* avoid re-using remote and pfmemalloc pages */
202 	if (!dev_page_is_reusable(page))
203 		return false;
204 
205 #if (PAGE_SIZE < 8192)
206 	/* if we are only owner of page we can reuse it */
207 	if (unlikely(page_count(page) != 1))
208 		return false;
209 
210 	/* flip page offset to other buffer */
211 	rx_buffer->page_offset ^= FM10K_RX_BUFSZ;
212 #else
213 	/* move offset up to the next cache line */
214 	rx_buffer->page_offset += truesize;
215 
216 	if (rx_buffer->page_offset > (PAGE_SIZE - FM10K_RX_BUFSZ))
217 		return false;
218 #endif
219 
220 	/* Even if we own the page, we are not allowed to use atomic_set()
221 	 * This would break get_page_unless_zero() users.
222 	 */
223 	page_ref_inc(page);
224 
225 	return true;
226 }
227 
228 /**
229  * fm10k_add_rx_frag - Add contents of Rx buffer to sk_buff
230  * @rx_buffer: buffer containing page to add
231  * @size: packet size from rx_desc
232  * @rx_desc: descriptor containing length of buffer written by hardware
233  * @skb: sk_buff to place the data into
234  *
235  * This function will add the data contained in rx_buffer->page to the skb.
236  * This is done either through a direct copy if the data in the buffer is
237  * less than the skb header size, otherwise it will just attach the page as
238  * a frag to the skb.
239  *
240  * The function will then update the page offset if necessary and return
241  * true if the buffer can be reused by the interface.
242  **/
243 static bool fm10k_add_rx_frag(struct fm10k_rx_buffer *rx_buffer,
244 			      unsigned int size,
245 			      union fm10k_rx_desc *rx_desc,
246 			      struct sk_buff *skb)
247 {
248 	struct page *page = rx_buffer->page;
249 	unsigned char *va = page_address(page) + rx_buffer->page_offset;
250 #if (PAGE_SIZE < 8192)
251 	unsigned int truesize = FM10K_RX_BUFSZ;
252 #else
253 	unsigned int truesize = ALIGN(size, 512);
254 #endif
255 	unsigned int pull_len;
256 
257 	if (unlikely(skb_is_nonlinear(skb)))
258 		goto add_tail_frag;
259 
260 	if (likely(size <= FM10K_RX_HDR_LEN)) {
261 		memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
262 
263 		/* page is reusable, we can reuse buffer as-is */
264 		if (dev_page_is_reusable(page))
265 			return true;
266 
267 		/* this page cannot be reused so discard it */
268 		__free_page(page);
269 		return false;
270 	}
271 
272 	/* we need the header to contain the greater of either ETH_HLEN or
273 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
274 	 */
275 	pull_len = eth_get_headlen(skb->dev, va, FM10K_RX_HDR_LEN);
276 
277 	/* align pull length to size of long to optimize memcpy performance */
278 	memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
279 
280 	/* update all of the pointers */
281 	va += pull_len;
282 	size -= pull_len;
283 
284 add_tail_frag:
285 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
286 			(unsigned long)va & ~PAGE_MASK, size, truesize);
287 
288 	return fm10k_can_reuse_rx_page(rx_buffer, page, truesize);
289 }
290 
291 static struct sk_buff *fm10k_fetch_rx_buffer(struct fm10k_ring *rx_ring,
292 					     union fm10k_rx_desc *rx_desc,
293 					     struct sk_buff *skb)
294 {
295 	unsigned int size = le16_to_cpu(rx_desc->w.length);
296 	struct fm10k_rx_buffer *rx_buffer;
297 	struct page *page;
298 
299 	rx_buffer = &rx_ring->rx_buffer[rx_ring->next_to_clean];
300 	page = rx_buffer->page;
301 	prefetchw(page);
302 
303 	if (likely(!skb)) {
304 		void *page_addr = page_address(page) +
305 				  rx_buffer->page_offset;
306 
307 		/* prefetch first cache line of first page */
308 		net_prefetch(page_addr);
309 
310 		/* allocate a skb to store the frags */
311 		skb = napi_alloc_skb(&rx_ring->q_vector->napi,
312 				     FM10K_RX_HDR_LEN);
313 		if (unlikely(!skb)) {
314 			rx_ring->rx_stats.alloc_failed++;
315 			return NULL;
316 		}
317 
318 		/* we will be copying header into skb->data in
319 		 * pskb_may_pull so it is in our interest to prefetch
320 		 * it now to avoid a possible cache miss
321 		 */
322 		prefetchw(skb->data);
323 	}
324 
325 	/* we are reusing so sync this buffer for CPU use */
326 	dma_sync_single_range_for_cpu(rx_ring->dev,
327 				      rx_buffer->dma,
328 				      rx_buffer->page_offset,
329 				      size,
330 				      DMA_FROM_DEVICE);
331 
332 	/* pull page into skb */
333 	if (fm10k_add_rx_frag(rx_buffer, size, rx_desc, skb)) {
334 		/* hand second half of page back to the ring */
335 		fm10k_reuse_rx_page(rx_ring, rx_buffer);
336 	} else {
337 		/* we are not reusing the buffer so unmap it */
338 		dma_unmap_page(rx_ring->dev, rx_buffer->dma,
339 			       PAGE_SIZE, DMA_FROM_DEVICE);
340 	}
341 
342 	/* clear contents of rx_buffer */
343 	rx_buffer->page = NULL;
344 
345 	return skb;
346 }
347 
348 static inline void fm10k_rx_checksum(struct fm10k_ring *ring,
349 				     union fm10k_rx_desc *rx_desc,
350 				     struct sk_buff *skb)
351 {
352 	skb_checksum_none_assert(skb);
353 
354 	/* Rx checksum disabled via ethtool */
355 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
356 		return;
357 
358 	/* TCP/UDP checksum error bit is set */
359 	if (fm10k_test_staterr(rx_desc,
360 			       FM10K_RXD_STATUS_L4E |
361 			       FM10K_RXD_STATUS_L4E2 |
362 			       FM10K_RXD_STATUS_IPE |
363 			       FM10K_RXD_STATUS_IPE2)) {
364 		ring->rx_stats.csum_err++;
365 		return;
366 	}
367 
368 	/* It must be a TCP or UDP packet with a valid checksum */
369 	if (fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS2))
370 		skb->encapsulation = true;
371 	else if (!fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS))
372 		return;
373 
374 	skb->ip_summed = CHECKSUM_UNNECESSARY;
375 
376 	ring->rx_stats.csum_good++;
377 }
378 
379 #define FM10K_RSS_L4_TYPES_MASK \
380 	(BIT(FM10K_RSSTYPE_IPV4_TCP) | \
381 	 BIT(FM10K_RSSTYPE_IPV4_UDP) | \
382 	 BIT(FM10K_RSSTYPE_IPV6_TCP) | \
383 	 BIT(FM10K_RSSTYPE_IPV6_UDP))
384 
385 static inline void fm10k_rx_hash(struct fm10k_ring *ring,
386 				 union fm10k_rx_desc *rx_desc,
387 				 struct sk_buff *skb)
388 {
389 	u16 rss_type;
390 
391 	if (!(ring->netdev->features & NETIF_F_RXHASH))
392 		return;
393 
394 	rss_type = le16_to_cpu(rx_desc->w.pkt_info) & FM10K_RXD_RSSTYPE_MASK;
395 	if (!rss_type)
396 		return;
397 
398 	skb_set_hash(skb, le32_to_cpu(rx_desc->d.rss),
399 		     (BIT(rss_type) & FM10K_RSS_L4_TYPES_MASK) ?
400 		     PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
401 }
402 
403 static void fm10k_type_trans(struct fm10k_ring *rx_ring,
404 			     union fm10k_rx_desc __maybe_unused *rx_desc,
405 			     struct sk_buff *skb)
406 {
407 	struct net_device *dev = rx_ring->netdev;
408 	struct fm10k_l2_accel *l2_accel = rcu_dereference_bh(rx_ring->l2_accel);
409 
410 	/* check to see if DGLORT belongs to a MACVLAN */
411 	if (l2_accel) {
412 		u16 idx = le16_to_cpu(FM10K_CB(skb)->fi.w.dglort) - 1;
413 
414 		idx -= l2_accel->dglort;
415 		if (idx < l2_accel->size && l2_accel->macvlan[idx])
416 			dev = l2_accel->macvlan[idx];
417 		else
418 			l2_accel = NULL;
419 	}
420 
421 	/* Record Rx queue, or update macvlan statistics */
422 	if (!l2_accel)
423 		skb_record_rx_queue(skb, rx_ring->queue_index);
424 	else
425 		macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
426 				 false);
427 
428 	skb->protocol = eth_type_trans(skb, dev);
429 }
430 
431 /**
432  * fm10k_process_skb_fields - Populate skb header fields from Rx descriptor
433  * @rx_ring: rx descriptor ring packet is being transacted on
434  * @rx_desc: pointer to the EOP Rx descriptor
435  * @skb: pointer to current skb being populated
436  *
437  * This function checks the ring, descriptor, and packet information in
438  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
439  * other fields within the skb.
440  **/
441 static unsigned int fm10k_process_skb_fields(struct fm10k_ring *rx_ring,
442 					     union fm10k_rx_desc *rx_desc,
443 					     struct sk_buff *skb)
444 {
445 	unsigned int len = skb->len;
446 
447 	fm10k_rx_hash(rx_ring, rx_desc, skb);
448 
449 	fm10k_rx_checksum(rx_ring, rx_desc, skb);
450 
451 	FM10K_CB(skb)->tstamp = rx_desc->q.timestamp;
452 
453 	FM10K_CB(skb)->fi.w.vlan = rx_desc->w.vlan;
454 
455 	FM10K_CB(skb)->fi.d.glort = rx_desc->d.glort;
456 
457 	if (rx_desc->w.vlan) {
458 		u16 vid = le16_to_cpu(rx_desc->w.vlan);
459 
460 		if ((vid & VLAN_VID_MASK) != rx_ring->vid)
461 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
462 		else if (vid & VLAN_PRIO_MASK)
463 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
464 					       vid & VLAN_PRIO_MASK);
465 	}
466 
467 	fm10k_type_trans(rx_ring, rx_desc, skb);
468 
469 	return len;
470 }
471 
472 /**
473  * fm10k_is_non_eop - process handling of non-EOP buffers
474  * @rx_ring: Rx ring being processed
475  * @rx_desc: Rx descriptor for current buffer
476  *
477  * This function updates next to clean.  If the buffer is an EOP buffer
478  * this function exits returning false, otherwise it will place the
479  * sk_buff in the next buffer to be chained and return true indicating
480  * that this is in fact a non-EOP buffer.
481  **/
482 static bool fm10k_is_non_eop(struct fm10k_ring *rx_ring,
483 			     union fm10k_rx_desc *rx_desc)
484 {
485 	u32 ntc = rx_ring->next_to_clean + 1;
486 
487 	/* fetch, update, and store next to clean */
488 	ntc = (ntc < rx_ring->count) ? ntc : 0;
489 	rx_ring->next_to_clean = ntc;
490 
491 	prefetch(FM10K_RX_DESC(rx_ring, ntc));
492 
493 	if (likely(fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_EOP)))
494 		return false;
495 
496 	return true;
497 }
498 
499 /**
500  * fm10k_cleanup_headers - Correct corrupted or empty headers
501  * @rx_ring: rx descriptor ring packet is being transacted on
502  * @rx_desc: pointer to the EOP Rx descriptor
503  * @skb: pointer to current skb being fixed
504  *
505  * Address the case where we are pulling data in on pages only
506  * and as such no data is present in the skb header.
507  *
508  * In addition if skb is not at least 60 bytes we need to pad it so that
509  * it is large enough to qualify as a valid Ethernet frame.
510  *
511  * Returns true if an error was encountered and skb was freed.
512  **/
513 static bool fm10k_cleanup_headers(struct fm10k_ring *rx_ring,
514 				  union fm10k_rx_desc *rx_desc,
515 				  struct sk_buff *skb)
516 {
517 	if (unlikely((fm10k_test_staterr(rx_desc,
518 					 FM10K_RXD_STATUS_RXE)))) {
519 #define FM10K_TEST_RXD_BIT(rxd, bit) \
520 	((rxd)->w.csum_err & cpu_to_le16(bit))
521 		if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_ERROR))
522 			rx_ring->rx_stats.switch_errors++;
523 		if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_NO_DESCRIPTOR))
524 			rx_ring->rx_stats.drops++;
525 		if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_PP_ERROR))
526 			rx_ring->rx_stats.pp_errors++;
527 		if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_READY))
528 			rx_ring->rx_stats.link_errors++;
529 		if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_TOO_BIG))
530 			rx_ring->rx_stats.length_errors++;
531 		dev_kfree_skb_any(skb);
532 		rx_ring->rx_stats.errors++;
533 		return true;
534 	}
535 
536 	/* if eth_skb_pad returns an error the skb was freed */
537 	if (eth_skb_pad(skb))
538 		return true;
539 
540 	return false;
541 }
542 
543 /**
544  * fm10k_receive_skb - helper function to handle rx indications
545  * @q_vector: structure containing interrupt and ring information
546  * @skb: packet to send up
547  **/
548 static void fm10k_receive_skb(struct fm10k_q_vector *q_vector,
549 			      struct sk_buff *skb)
550 {
551 	napi_gro_receive(&q_vector->napi, skb);
552 }
553 
554 static int fm10k_clean_rx_irq(struct fm10k_q_vector *q_vector,
555 			      struct fm10k_ring *rx_ring,
556 			      int budget)
557 {
558 	struct sk_buff *skb = rx_ring->skb;
559 	unsigned int total_bytes = 0, total_packets = 0;
560 	u16 cleaned_count = fm10k_desc_unused(rx_ring);
561 
562 	while (likely(total_packets < budget)) {
563 		union fm10k_rx_desc *rx_desc;
564 
565 		/* return some buffers to hardware, one at a time is too slow */
566 		if (cleaned_count >= FM10K_RX_BUFFER_WRITE) {
567 			fm10k_alloc_rx_buffers(rx_ring, cleaned_count);
568 			cleaned_count = 0;
569 		}
570 
571 		rx_desc = FM10K_RX_DESC(rx_ring, rx_ring->next_to_clean);
572 
573 		if (!rx_desc->d.staterr)
574 			break;
575 
576 		/* This memory barrier is needed to keep us from reading
577 		 * any other fields out of the rx_desc until we know the
578 		 * descriptor has been written back
579 		 */
580 		dma_rmb();
581 
582 		/* retrieve a buffer from the ring */
583 		skb = fm10k_fetch_rx_buffer(rx_ring, rx_desc, skb);
584 
585 		/* exit if we failed to retrieve a buffer */
586 		if (!skb)
587 			break;
588 
589 		cleaned_count++;
590 
591 		/* fetch next buffer in frame if non-eop */
592 		if (fm10k_is_non_eop(rx_ring, rx_desc))
593 			continue;
594 
595 		/* verify the packet layout is correct */
596 		if (fm10k_cleanup_headers(rx_ring, rx_desc, skb)) {
597 			skb = NULL;
598 			continue;
599 		}
600 
601 		/* populate checksum, timestamp, VLAN, and protocol */
602 		total_bytes += fm10k_process_skb_fields(rx_ring, rx_desc, skb);
603 
604 		fm10k_receive_skb(q_vector, skb);
605 
606 		/* reset skb pointer */
607 		skb = NULL;
608 
609 		/* update budget accounting */
610 		total_packets++;
611 	}
612 
613 	/* place incomplete frames back on ring for completion */
614 	rx_ring->skb = skb;
615 
616 	u64_stats_update_begin(&rx_ring->syncp);
617 	rx_ring->stats.packets += total_packets;
618 	rx_ring->stats.bytes += total_bytes;
619 	u64_stats_update_end(&rx_ring->syncp);
620 	q_vector->rx.total_packets += total_packets;
621 	q_vector->rx.total_bytes += total_bytes;
622 
623 	return total_packets;
624 }
625 
626 #define VXLAN_HLEN (sizeof(struct udphdr) + 8)
627 static struct ethhdr *fm10k_port_is_vxlan(struct sk_buff *skb)
628 {
629 	struct fm10k_intfc *interface = netdev_priv(skb->dev);
630 
631 	if (interface->vxlan_port != udp_hdr(skb)->dest)
632 		return NULL;
633 
634 	/* return offset of udp_hdr plus 8 bytes for VXLAN header */
635 	return (struct ethhdr *)(skb_transport_header(skb) + VXLAN_HLEN);
636 }
637 
638 #define FM10K_NVGRE_RESERVED0_FLAGS htons(0x9FFF)
639 #define NVGRE_TNI htons(0x2000)
640 struct fm10k_nvgre_hdr {
641 	__be16 flags;
642 	__be16 proto;
643 	__be32 tni;
644 };
645 
646 static struct ethhdr *fm10k_gre_is_nvgre(struct sk_buff *skb)
647 {
648 	struct fm10k_nvgre_hdr *nvgre_hdr;
649 	int hlen = ip_hdrlen(skb);
650 
651 	/* currently only IPv4 is supported due to hlen above */
652 	if (vlan_get_protocol(skb) != htons(ETH_P_IP))
653 		return NULL;
654 
655 	/* our transport header should be NVGRE */
656 	nvgre_hdr = (struct fm10k_nvgre_hdr *)(skb_network_header(skb) + hlen);
657 
658 	/* verify all reserved flags are 0 */
659 	if (nvgre_hdr->flags & FM10K_NVGRE_RESERVED0_FLAGS)
660 		return NULL;
661 
662 	/* report start of ethernet header */
663 	if (nvgre_hdr->flags & NVGRE_TNI)
664 		return (struct ethhdr *)(nvgre_hdr + 1);
665 
666 	return (struct ethhdr *)(&nvgre_hdr->tni);
667 }
668 
669 __be16 fm10k_tx_encap_offload(struct sk_buff *skb)
670 {
671 	u8 l4_hdr = 0, inner_l4_hdr = 0, inner_l4_hlen;
672 	struct ethhdr *eth_hdr;
673 
674 	if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
675 	    skb->inner_protocol != htons(ETH_P_TEB))
676 		return 0;
677 
678 	switch (vlan_get_protocol(skb)) {
679 	case htons(ETH_P_IP):
680 		l4_hdr = ip_hdr(skb)->protocol;
681 		break;
682 	case htons(ETH_P_IPV6):
683 		l4_hdr = ipv6_hdr(skb)->nexthdr;
684 		break;
685 	default:
686 		return 0;
687 	}
688 
689 	switch (l4_hdr) {
690 	case IPPROTO_UDP:
691 		eth_hdr = fm10k_port_is_vxlan(skb);
692 		break;
693 	case IPPROTO_GRE:
694 		eth_hdr = fm10k_gre_is_nvgre(skb);
695 		break;
696 	default:
697 		return 0;
698 	}
699 
700 	if (!eth_hdr)
701 		return 0;
702 
703 	switch (eth_hdr->h_proto) {
704 	case htons(ETH_P_IP):
705 		inner_l4_hdr = inner_ip_hdr(skb)->protocol;
706 		break;
707 	case htons(ETH_P_IPV6):
708 		inner_l4_hdr = inner_ipv6_hdr(skb)->nexthdr;
709 		break;
710 	default:
711 		return 0;
712 	}
713 
714 	switch (inner_l4_hdr) {
715 	case IPPROTO_TCP:
716 		inner_l4_hlen = inner_tcp_hdrlen(skb);
717 		break;
718 	case IPPROTO_UDP:
719 		inner_l4_hlen = 8;
720 		break;
721 	default:
722 		return 0;
723 	}
724 
725 	/* The hardware allows tunnel offloads only if the combined inner and
726 	 * outer header is 184 bytes or less
727 	 */
728 	if (skb_inner_transport_header(skb) + inner_l4_hlen -
729 	    skb_mac_header(skb) > FM10K_TUNNEL_HEADER_LENGTH)
730 		return 0;
731 
732 	return eth_hdr->h_proto;
733 }
734 
735 static int fm10k_tso(struct fm10k_ring *tx_ring,
736 		     struct fm10k_tx_buffer *first)
737 {
738 	struct sk_buff *skb = first->skb;
739 	struct fm10k_tx_desc *tx_desc;
740 	unsigned char *th;
741 	u8 hdrlen;
742 
743 	if (skb->ip_summed != CHECKSUM_PARTIAL)
744 		return 0;
745 
746 	if (!skb_is_gso(skb))
747 		return 0;
748 
749 	/* compute header lengths */
750 	if (skb->encapsulation) {
751 		if (!fm10k_tx_encap_offload(skb))
752 			goto err_vxlan;
753 		th = skb_inner_transport_header(skb);
754 	} else {
755 		th = skb_transport_header(skb);
756 	}
757 
758 	/* compute offset from SOF to transport header and add header len */
759 	hdrlen = (th - skb->data) + (((struct tcphdr *)th)->doff << 2);
760 
761 	first->tx_flags |= FM10K_TX_FLAGS_CSUM;
762 
763 	/* update gso size and bytecount with header size */
764 	first->gso_segs = skb_shinfo(skb)->gso_segs;
765 	first->bytecount += (first->gso_segs - 1) * hdrlen;
766 
767 	/* populate Tx descriptor header size and mss */
768 	tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use);
769 	tx_desc->hdrlen = hdrlen;
770 	tx_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
771 
772 	return 1;
773 
774 err_vxlan:
775 	tx_ring->netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
776 	if (net_ratelimit())
777 		netdev_err(tx_ring->netdev,
778 			   "TSO requested for unsupported tunnel, disabling offload\n");
779 	return -1;
780 }
781 
782 static void fm10k_tx_csum(struct fm10k_ring *tx_ring,
783 			  struct fm10k_tx_buffer *first)
784 {
785 	struct sk_buff *skb = first->skb;
786 	struct fm10k_tx_desc *tx_desc;
787 	union {
788 		struct iphdr *ipv4;
789 		struct ipv6hdr *ipv6;
790 		u8 *raw;
791 	} network_hdr;
792 	u8 *transport_hdr;
793 	__be16 frag_off;
794 	__be16 protocol;
795 	u8 l4_hdr = 0;
796 
797 	if (skb->ip_summed != CHECKSUM_PARTIAL)
798 		goto no_csum;
799 
800 	if (skb->encapsulation) {
801 		protocol = fm10k_tx_encap_offload(skb);
802 		if (!protocol) {
803 			if (skb_checksum_help(skb)) {
804 				dev_warn(tx_ring->dev,
805 					 "failed to offload encap csum!\n");
806 				tx_ring->tx_stats.csum_err++;
807 			}
808 			goto no_csum;
809 		}
810 		network_hdr.raw = skb_inner_network_header(skb);
811 		transport_hdr = skb_inner_transport_header(skb);
812 	} else {
813 		protocol = vlan_get_protocol(skb);
814 		network_hdr.raw = skb_network_header(skb);
815 		transport_hdr = skb_transport_header(skb);
816 	}
817 
818 	switch (protocol) {
819 	case htons(ETH_P_IP):
820 		l4_hdr = network_hdr.ipv4->protocol;
821 		break;
822 	case htons(ETH_P_IPV6):
823 		l4_hdr = network_hdr.ipv6->nexthdr;
824 		if (likely((transport_hdr - network_hdr.raw) ==
825 			   sizeof(struct ipv6hdr)))
826 			break;
827 		ipv6_skip_exthdr(skb, network_hdr.raw - skb->data +
828 				      sizeof(struct ipv6hdr),
829 				 &l4_hdr, &frag_off);
830 		if (unlikely(frag_off))
831 			l4_hdr = NEXTHDR_FRAGMENT;
832 		break;
833 	default:
834 		break;
835 	}
836 
837 	switch (l4_hdr) {
838 	case IPPROTO_TCP:
839 	case IPPROTO_UDP:
840 		break;
841 	case IPPROTO_GRE:
842 		if (skb->encapsulation)
843 			break;
844 		fallthrough;
845 	default:
846 		if (unlikely(net_ratelimit())) {
847 			dev_warn(tx_ring->dev,
848 				 "partial checksum, version=%d l4 proto=%x\n",
849 				 protocol, l4_hdr);
850 		}
851 		skb_checksum_help(skb);
852 		tx_ring->tx_stats.csum_err++;
853 		goto no_csum;
854 	}
855 
856 	/* update TX checksum flag */
857 	first->tx_flags |= FM10K_TX_FLAGS_CSUM;
858 	tx_ring->tx_stats.csum_good++;
859 
860 no_csum:
861 	/* populate Tx descriptor header size and mss */
862 	tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use);
863 	tx_desc->hdrlen = 0;
864 	tx_desc->mss = 0;
865 }
866 
867 #define FM10K_SET_FLAG(_input, _flag, _result) \
868 	((_flag <= _result) ? \
869 	 ((u32)(_input & _flag) * (_result / _flag)) : \
870 	 ((u32)(_input & _flag) / (_flag / _result)))
871 
872 static u8 fm10k_tx_desc_flags(struct sk_buff *skb, u32 tx_flags)
873 {
874 	/* set type for advanced descriptor with frame checksum insertion */
875 	u32 desc_flags = 0;
876 
877 	/* set checksum offload bits */
878 	desc_flags |= FM10K_SET_FLAG(tx_flags, FM10K_TX_FLAGS_CSUM,
879 				     FM10K_TXD_FLAG_CSUM);
880 
881 	return desc_flags;
882 }
883 
884 static bool fm10k_tx_desc_push(struct fm10k_ring *tx_ring,
885 			       struct fm10k_tx_desc *tx_desc, u16 i,
886 			       dma_addr_t dma, unsigned int size, u8 desc_flags)
887 {
888 	/* set RS and INT for last frame in a cache line */
889 	if ((++i & (FM10K_TXD_WB_FIFO_SIZE - 1)) == 0)
890 		desc_flags |= FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_INT;
891 
892 	/* record values to descriptor */
893 	tx_desc->buffer_addr = cpu_to_le64(dma);
894 	tx_desc->flags = desc_flags;
895 	tx_desc->buflen = cpu_to_le16(size);
896 
897 	/* return true if we just wrapped the ring */
898 	return i == tx_ring->count;
899 }
900 
901 static int __fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size)
902 {
903 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
904 
905 	/* Memory barrier before checking head and tail */
906 	smp_mb();
907 
908 	/* Check again in a case another CPU has just made room available */
909 	if (likely(fm10k_desc_unused(tx_ring) < size))
910 		return -EBUSY;
911 
912 	/* A reprieve! - use start_queue because it doesn't call schedule */
913 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
914 	++tx_ring->tx_stats.restart_queue;
915 	return 0;
916 }
917 
918 static inline int fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size)
919 {
920 	if (likely(fm10k_desc_unused(tx_ring) >= size))
921 		return 0;
922 	return __fm10k_maybe_stop_tx(tx_ring, size);
923 }
924 
925 static void fm10k_tx_map(struct fm10k_ring *tx_ring,
926 			 struct fm10k_tx_buffer *first)
927 {
928 	struct sk_buff *skb = first->skb;
929 	struct fm10k_tx_buffer *tx_buffer;
930 	struct fm10k_tx_desc *tx_desc;
931 	skb_frag_t *frag;
932 	unsigned char *data;
933 	dma_addr_t dma;
934 	unsigned int data_len, size;
935 	u32 tx_flags = first->tx_flags;
936 	u16 i = tx_ring->next_to_use;
937 	u8 flags = fm10k_tx_desc_flags(skb, tx_flags);
938 
939 	tx_desc = FM10K_TX_DESC(tx_ring, i);
940 
941 	/* add HW VLAN tag */
942 	if (skb_vlan_tag_present(skb))
943 		tx_desc->vlan = cpu_to_le16(skb_vlan_tag_get(skb));
944 	else
945 		tx_desc->vlan = 0;
946 
947 	size = skb_headlen(skb);
948 	data = skb->data;
949 
950 	dma = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE);
951 
952 	data_len = skb->data_len;
953 	tx_buffer = first;
954 
955 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
956 		if (dma_mapping_error(tx_ring->dev, dma))
957 			goto dma_error;
958 
959 		/* record length, and DMA address */
960 		dma_unmap_len_set(tx_buffer, len, size);
961 		dma_unmap_addr_set(tx_buffer, dma, dma);
962 
963 		while (unlikely(size > FM10K_MAX_DATA_PER_TXD)) {
964 			if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, dma,
965 					       FM10K_MAX_DATA_PER_TXD, flags)) {
966 				tx_desc = FM10K_TX_DESC(tx_ring, 0);
967 				i = 0;
968 			}
969 
970 			dma += FM10K_MAX_DATA_PER_TXD;
971 			size -= FM10K_MAX_DATA_PER_TXD;
972 		}
973 
974 		if (likely(!data_len))
975 			break;
976 
977 		if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++,
978 				       dma, size, flags)) {
979 			tx_desc = FM10K_TX_DESC(tx_ring, 0);
980 			i = 0;
981 		}
982 
983 		size = skb_frag_size(frag);
984 		data_len -= size;
985 
986 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
987 				       DMA_TO_DEVICE);
988 
989 		tx_buffer = &tx_ring->tx_buffer[i];
990 	}
991 
992 	/* write last descriptor with LAST bit set */
993 	flags |= FM10K_TXD_FLAG_LAST;
994 
995 	if (fm10k_tx_desc_push(tx_ring, tx_desc, i++, dma, size, flags))
996 		i = 0;
997 
998 	/* record bytecount for BQL */
999 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1000 
1001 	/* record SW timestamp if HW timestamp is not available */
1002 	skb_tx_timestamp(first->skb);
1003 
1004 	/* Force memory writes to complete before letting h/w know there
1005 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
1006 	 * memory model archs, such as IA-64).
1007 	 *
1008 	 * We also need this memory barrier to make certain all of the
1009 	 * status bits have been updated before next_to_watch is written.
1010 	 */
1011 	wmb();
1012 
1013 	/* set next_to_watch value indicating a packet is present */
1014 	first->next_to_watch = tx_desc;
1015 
1016 	tx_ring->next_to_use = i;
1017 
1018 	/* Make sure there is space in the ring for the next send. */
1019 	fm10k_maybe_stop_tx(tx_ring, DESC_NEEDED);
1020 
1021 	/* notify HW of packet */
1022 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
1023 		writel(i, tx_ring->tail);
1024 	}
1025 
1026 	return;
1027 dma_error:
1028 	dev_err(tx_ring->dev, "TX DMA map failed\n");
1029 
1030 	/* clear dma mappings for failed tx_buffer map */
1031 	for (;;) {
1032 		tx_buffer = &tx_ring->tx_buffer[i];
1033 		fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1034 		if (tx_buffer == first)
1035 			break;
1036 		if (i == 0)
1037 			i = tx_ring->count;
1038 		i--;
1039 	}
1040 
1041 	tx_ring->next_to_use = i;
1042 }
1043 
1044 netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
1045 				  struct fm10k_ring *tx_ring)
1046 {
1047 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
1048 	struct fm10k_tx_buffer *first;
1049 	unsigned short f;
1050 	u32 tx_flags = 0;
1051 	int tso;
1052 
1053 	/* need: 1 descriptor per page * PAGE_SIZE/FM10K_MAX_DATA_PER_TXD,
1054 	 *       + 1 desc for skb_headlen/FM10K_MAX_DATA_PER_TXD,
1055 	 *       + 2 desc gap to keep tail from touching head
1056 	 * otherwise try next time
1057 	 */
1058 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1059 		skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1060 
1061 		count += TXD_USE_COUNT(skb_frag_size(frag));
1062 	}
1063 
1064 	if (fm10k_maybe_stop_tx(tx_ring, count + 3)) {
1065 		tx_ring->tx_stats.tx_busy++;
1066 		return NETDEV_TX_BUSY;
1067 	}
1068 
1069 	/* record the location of the first descriptor for this packet */
1070 	first = &tx_ring->tx_buffer[tx_ring->next_to_use];
1071 	first->skb = skb;
1072 	first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN);
1073 	first->gso_segs = 1;
1074 
1075 	/* record initial flags and protocol */
1076 	first->tx_flags = tx_flags;
1077 
1078 	tso = fm10k_tso(tx_ring, first);
1079 	if (tso < 0)
1080 		goto out_drop;
1081 	else if (!tso)
1082 		fm10k_tx_csum(tx_ring, first);
1083 
1084 	fm10k_tx_map(tx_ring, first);
1085 
1086 	return NETDEV_TX_OK;
1087 
1088 out_drop:
1089 	dev_kfree_skb_any(first->skb);
1090 	first->skb = NULL;
1091 
1092 	return NETDEV_TX_OK;
1093 }
1094 
1095 static u64 fm10k_get_tx_completed(struct fm10k_ring *ring)
1096 {
1097 	return ring->stats.packets;
1098 }
1099 
1100 /**
1101  * fm10k_get_tx_pending - how many Tx descriptors not processed
1102  * @ring: the ring structure
1103  * @in_sw: is tx_pending being checked in SW or in HW?
1104  */
1105 u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw)
1106 {
1107 	struct fm10k_intfc *interface = ring->q_vector->interface;
1108 	struct fm10k_hw *hw = &interface->hw;
1109 	u32 head, tail;
1110 
1111 	if (likely(in_sw)) {
1112 		head = ring->next_to_clean;
1113 		tail = ring->next_to_use;
1114 	} else {
1115 		head = fm10k_read_reg(hw, FM10K_TDH(ring->reg_idx));
1116 		tail = fm10k_read_reg(hw, FM10K_TDT(ring->reg_idx));
1117 	}
1118 
1119 	return ((head <= tail) ? tail : tail + ring->count) - head;
1120 }
1121 
1122 bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring)
1123 {
1124 	u32 tx_done = fm10k_get_tx_completed(tx_ring);
1125 	u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1126 	u32 tx_pending = fm10k_get_tx_pending(tx_ring, true);
1127 
1128 	clear_check_for_tx_hang(tx_ring);
1129 
1130 	/* Check for a hung queue, but be thorough. This verifies
1131 	 * that a transmit has been completed since the previous
1132 	 * check AND there is at least one packet pending. By
1133 	 * requiring this to fail twice we avoid races with
1134 	 * clearing the ARMED bit and conditions where we
1135 	 * run the check_tx_hang logic with a transmit completion
1136 	 * pending but without time to complete it yet.
1137 	 */
1138 	if (!tx_pending || (tx_done_old != tx_done)) {
1139 		/* update completed stats and continue */
1140 		tx_ring->tx_stats.tx_done_old = tx_done;
1141 		/* reset the countdown */
1142 		clear_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state);
1143 
1144 		return false;
1145 	}
1146 
1147 	/* make sure it is true for two checks in a row */
1148 	return test_and_set_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state);
1149 }
1150 
1151 /**
1152  * fm10k_tx_timeout_reset - initiate reset due to Tx timeout
1153  * @interface: driver private struct
1154  **/
1155 void fm10k_tx_timeout_reset(struct fm10k_intfc *interface)
1156 {
1157 	/* Do the reset outside of interrupt context */
1158 	if (!test_bit(__FM10K_DOWN, interface->state)) {
1159 		interface->tx_timeout_count++;
1160 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1161 		fm10k_service_event_schedule(interface);
1162 	}
1163 }
1164 
1165 /**
1166  * fm10k_clean_tx_irq - Reclaim resources after transmit completes
1167  * @q_vector: structure containing interrupt and ring information
1168  * @tx_ring: tx ring to clean
1169  * @napi_budget: Used to determine if we are in netpoll
1170  **/
1171 static bool fm10k_clean_tx_irq(struct fm10k_q_vector *q_vector,
1172 			       struct fm10k_ring *tx_ring, int napi_budget)
1173 {
1174 	struct fm10k_intfc *interface = q_vector->interface;
1175 	struct fm10k_tx_buffer *tx_buffer;
1176 	struct fm10k_tx_desc *tx_desc;
1177 	unsigned int total_bytes = 0, total_packets = 0;
1178 	unsigned int budget = q_vector->tx.work_limit;
1179 	unsigned int i = tx_ring->next_to_clean;
1180 
1181 	if (test_bit(__FM10K_DOWN, interface->state))
1182 		return true;
1183 
1184 	tx_buffer = &tx_ring->tx_buffer[i];
1185 	tx_desc = FM10K_TX_DESC(tx_ring, i);
1186 	i -= tx_ring->count;
1187 
1188 	do {
1189 		struct fm10k_tx_desc *eop_desc = tx_buffer->next_to_watch;
1190 
1191 		/* if next_to_watch is not set then there is no work pending */
1192 		if (!eop_desc)
1193 			break;
1194 
1195 		/* prevent any other reads prior to eop_desc */
1196 		smp_rmb();
1197 
1198 		/* if DD is not set pending work has not been completed */
1199 		if (!(eop_desc->flags & FM10K_TXD_FLAG_DONE))
1200 			break;
1201 
1202 		/* clear next_to_watch to prevent false hangs */
1203 		tx_buffer->next_to_watch = NULL;
1204 
1205 		/* update the statistics for this packet */
1206 		total_bytes += tx_buffer->bytecount;
1207 		total_packets += tx_buffer->gso_segs;
1208 
1209 		/* free the skb */
1210 		napi_consume_skb(tx_buffer->skb, napi_budget);
1211 
1212 		/* unmap skb header data */
1213 		dma_unmap_single(tx_ring->dev,
1214 				 dma_unmap_addr(tx_buffer, dma),
1215 				 dma_unmap_len(tx_buffer, len),
1216 				 DMA_TO_DEVICE);
1217 
1218 		/* clear tx_buffer data */
1219 		tx_buffer->skb = NULL;
1220 		dma_unmap_len_set(tx_buffer, len, 0);
1221 
1222 		/* unmap remaining buffers */
1223 		while (tx_desc != eop_desc) {
1224 			tx_buffer++;
1225 			tx_desc++;
1226 			i++;
1227 			if (unlikely(!i)) {
1228 				i -= tx_ring->count;
1229 				tx_buffer = tx_ring->tx_buffer;
1230 				tx_desc = FM10K_TX_DESC(tx_ring, 0);
1231 			}
1232 
1233 			/* unmap any remaining paged data */
1234 			if (dma_unmap_len(tx_buffer, len)) {
1235 				dma_unmap_page(tx_ring->dev,
1236 					       dma_unmap_addr(tx_buffer, dma),
1237 					       dma_unmap_len(tx_buffer, len),
1238 					       DMA_TO_DEVICE);
1239 				dma_unmap_len_set(tx_buffer, len, 0);
1240 			}
1241 		}
1242 
1243 		/* move us one more past the eop_desc for start of next pkt */
1244 		tx_buffer++;
1245 		tx_desc++;
1246 		i++;
1247 		if (unlikely(!i)) {
1248 			i -= tx_ring->count;
1249 			tx_buffer = tx_ring->tx_buffer;
1250 			tx_desc = FM10K_TX_DESC(tx_ring, 0);
1251 		}
1252 
1253 		/* issue prefetch for next Tx descriptor */
1254 		prefetch(tx_desc);
1255 
1256 		/* update budget accounting */
1257 		budget--;
1258 	} while (likely(budget));
1259 
1260 	i += tx_ring->count;
1261 	tx_ring->next_to_clean = i;
1262 	u64_stats_update_begin(&tx_ring->syncp);
1263 	tx_ring->stats.bytes += total_bytes;
1264 	tx_ring->stats.packets += total_packets;
1265 	u64_stats_update_end(&tx_ring->syncp);
1266 	q_vector->tx.total_bytes += total_bytes;
1267 	q_vector->tx.total_packets += total_packets;
1268 
1269 	if (check_for_tx_hang(tx_ring) && fm10k_check_tx_hang(tx_ring)) {
1270 		/* schedule immediate reset if we believe we hung */
1271 		struct fm10k_hw *hw = &interface->hw;
1272 
1273 		netif_err(interface, drv, tx_ring->netdev,
1274 			  "Detected Tx Unit Hang\n"
1275 			  "  Tx Queue             <%d>\n"
1276 			  "  TDH, TDT             <%x>, <%x>\n"
1277 			  "  next_to_use          <%x>\n"
1278 			  "  next_to_clean        <%x>\n",
1279 			  tx_ring->queue_index,
1280 			  fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)),
1281 			  fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)),
1282 			  tx_ring->next_to_use, i);
1283 
1284 		netif_stop_subqueue(tx_ring->netdev,
1285 				    tx_ring->queue_index);
1286 
1287 		netif_info(interface, probe, tx_ring->netdev,
1288 			   "tx hang %d detected on queue %d, resetting interface\n",
1289 			   interface->tx_timeout_count + 1,
1290 			   tx_ring->queue_index);
1291 
1292 		fm10k_tx_timeout_reset(interface);
1293 
1294 		/* the netdev is about to reset, no point in enabling stuff */
1295 		return true;
1296 	}
1297 
1298 	/* notify netdev of completed buffers */
1299 	netdev_tx_completed_queue(txring_txq(tx_ring),
1300 				  total_packets, total_bytes);
1301 
1302 #define TX_WAKE_THRESHOLD min_t(u16, FM10K_MIN_TXD - 1, DESC_NEEDED * 2)
1303 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1304 		     (fm10k_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1305 		/* Make sure that anybody stopping the queue after this
1306 		 * sees the new next_to_clean.
1307 		 */
1308 		smp_mb();
1309 		if (__netif_subqueue_stopped(tx_ring->netdev,
1310 					     tx_ring->queue_index) &&
1311 		    !test_bit(__FM10K_DOWN, interface->state)) {
1312 			netif_wake_subqueue(tx_ring->netdev,
1313 					    tx_ring->queue_index);
1314 			++tx_ring->tx_stats.restart_queue;
1315 		}
1316 	}
1317 
1318 	return !!budget;
1319 }
1320 
1321 /**
1322  * fm10k_update_itr - update the dynamic ITR value based on packet size
1323  *
1324  *      Stores a new ITR value based on strictly on packet size.  The
1325  *      divisors and thresholds used by this function were determined based
1326  *      on theoretical maximum wire speed and testing data, in order to
1327  *      minimize response time while increasing bulk throughput.
1328  *
1329  * @ring_container: Container for rings to have ITR updated
1330  **/
1331 static void fm10k_update_itr(struct fm10k_ring_container *ring_container)
1332 {
1333 	unsigned int avg_wire_size, packets, itr_round;
1334 
1335 	/* Only update ITR if we are using adaptive setting */
1336 	if (!ITR_IS_ADAPTIVE(ring_container->itr))
1337 		goto clear_counts;
1338 
1339 	packets = ring_container->total_packets;
1340 	if (!packets)
1341 		goto clear_counts;
1342 
1343 	avg_wire_size = ring_container->total_bytes / packets;
1344 
1345 	/* The following is a crude approximation of:
1346 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
1347 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1348 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1349 	 *
1350 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1351 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1352 	 * formula down to
1353 	 *
1354 	 *  (34 * (size + 24)) / (size + 640) = ITR
1355 	 *
1356 	 * We first do some math on the packet size and then finally bitshift
1357 	 * by 8 after rounding up. We also have to account for PCIe link speed
1358 	 * difference as ITR scales based on this.
1359 	 */
1360 	if (avg_wire_size <= 360) {
1361 		/* Start at 250K ints/sec and gradually drop to 77K ints/sec */
1362 		avg_wire_size *= 8;
1363 		avg_wire_size += 376;
1364 	} else if (avg_wire_size <= 1152) {
1365 		/* 77K ints/sec to 45K ints/sec */
1366 		avg_wire_size *= 3;
1367 		avg_wire_size += 2176;
1368 	} else if (avg_wire_size <= 1920) {
1369 		/* 45K ints/sec to 38K ints/sec */
1370 		avg_wire_size += 4480;
1371 	} else {
1372 		/* plateau at a limit of 38K ints/sec */
1373 		avg_wire_size = 6656;
1374 	}
1375 
1376 	/* Perform final bitshift for division after rounding up to ensure
1377 	 * that the calculation will never get below a 1. The bit shift
1378 	 * accounts for changes in the ITR due to PCIe link speed.
1379 	 */
1380 	itr_round = READ_ONCE(ring_container->itr_scale) + 8;
1381 	avg_wire_size += BIT(itr_round) - 1;
1382 	avg_wire_size >>= itr_round;
1383 
1384 	/* write back value and retain adaptive flag */
1385 	ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE;
1386 
1387 clear_counts:
1388 	ring_container->total_bytes = 0;
1389 	ring_container->total_packets = 0;
1390 }
1391 
1392 static void fm10k_qv_enable(struct fm10k_q_vector *q_vector)
1393 {
1394 	/* Enable auto-mask and clear the current mask */
1395 	u32 itr = FM10K_ITR_ENABLE;
1396 
1397 	/* Update Tx ITR */
1398 	fm10k_update_itr(&q_vector->tx);
1399 
1400 	/* Update Rx ITR */
1401 	fm10k_update_itr(&q_vector->rx);
1402 
1403 	/* Store Tx itr in timer slot 0 */
1404 	itr |= (q_vector->tx.itr & FM10K_ITR_MAX);
1405 
1406 	/* Shift Rx itr to timer slot 1 */
1407 	itr |= (q_vector->rx.itr & FM10K_ITR_MAX) << FM10K_ITR_INTERVAL1_SHIFT;
1408 
1409 	/* Write the final value to the ITR register */
1410 	writel(itr, q_vector->itr);
1411 }
1412 
1413 static int fm10k_poll(struct napi_struct *napi, int budget)
1414 {
1415 	struct fm10k_q_vector *q_vector =
1416 			       container_of(napi, struct fm10k_q_vector, napi);
1417 	struct fm10k_ring *ring;
1418 	int per_ring_budget, work_done = 0;
1419 	bool clean_complete = true;
1420 
1421 	fm10k_for_each_ring(ring, q_vector->tx) {
1422 		if (!fm10k_clean_tx_irq(q_vector, ring, budget))
1423 			clean_complete = false;
1424 	}
1425 
1426 	/* Handle case where we are called by netpoll with a budget of 0 */
1427 	if (budget <= 0)
1428 		return budget;
1429 
1430 	/* attempt to distribute budget to each queue fairly, but don't
1431 	 * allow the budget to go below 1 because we'll exit polling
1432 	 */
1433 	if (q_vector->rx.count > 1)
1434 		per_ring_budget = max(budget / q_vector->rx.count, 1);
1435 	else
1436 		per_ring_budget = budget;
1437 
1438 	fm10k_for_each_ring(ring, q_vector->rx) {
1439 		int work = fm10k_clean_rx_irq(q_vector, ring, per_ring_budget);
1440 
1441 		work_done += work;
1442 		if (work >= per_ring_budget)
1443 			clean_complete = false;
1444 	}
1445 
1446 	/* If all work not completed, return budget and keep polling */
1447 	if (!clean_complete)
1448 		return budget;
1449 
1450 	/* Exit the polling mode, but don't re-enable interrupts if stack might
1451 	 * poll us due to busy-polling
1452 	 */
1453 	if (likely(napi_complete_done(napi, work_done)))
1454 		fm10k_qv_enable(q_vector);
1455 
1456 	return min(work_done, budget - 1);
1457 }
1458 
1459 /**
1460  * fm10k_set_qos_queues: Allocate queues for a QOS-enabled device
1461  * @interface: board private structure to initialize
1462  *
1463  * When QoS (Quality of Service) is enabled, allocate queues for
1464  * each traffic class.  If multiqueue isn't available,then abort QoS
1465  * initialization.
1466  *
1467  * This function handles all combinations of Qos and RSS.
1468  *
1469  **/
1470 static bool fm10k_set_qos_queues(struct fm10k_intfc *interface)
1471 {
1472 	struct net_device *dev = interface->netdev;
1473 	struct fm10k_ring_feature *f;
1474 	int rss_i, i;
1475 	int pcs;
1476 
1477 	/* Map queue offset and counts onto allocated tx queues */
1478 	pcs = netdev_get_num_tc(dev);
1479 
1480 	if (pcs <= 1)
1481 		return false;
1482 
1483 	/* set QoS mask and indices */
1484 	f = &interface->ring_feature[RING_F_QOS];
1485 	f->indices = pcs;
1486 	f->mask = BIT(fls(pcs - 1)) - 1;
1487 
1488 	/* determine the upper limit for our current DCB mode */
1489 	rss_i = interface->hw.mac.max_queues / pcs;
1490 	rss_i = BIT(fls(rss_i) - 1);
1491 
1492 	/* set RSS mask and indices */
1493 	f = &interface->ring_feature[RING_F_RSS];
1494 	rss_i = min_t(u16, rss_i, f->limit);
1495 	f->indices = rss_i;
1496 	f->mask = BIT(fls(rss_i - 1)) - 1;
1497 
1498 	/* configure pause class to queue mapping */
1499 	for (i = 0; i < pcs; i++)
1500 		netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
1501 
1502 	interface->num_rx_queues = rss_i * pcs;
1503 	interface->num_tx_queues = rss_i * pcs;
1504 
1505 	return true;
1506 }
1507 
1508 /**
1509  * fm10k_set_rss_queues: Allocate queues for RSS
1510  * @interface: board private structure to initialize
1511  *
1512  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
1513  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1514  *
1515  **/
1516 static bool fm10k_set_rss_queues(struct fm10k_intfc *interface)
1517 {
1518 	struct fm10k_ring_feature *f;
1519 	u16 rss_i;
1520 
1521 	f = &interface->ring_feature[RING_F_RSS];
1522 	rss_i = min_t(u16, interface->hw.mac.max_queues, f->limit);
1523 
1524 	/* record indices and power of 2 mask for RSS */
1525 	f->indices = rss_i;
1526 	f->mask = BIT(fls(rss_i - 1)) - 1;
1527 
1528 	interface->num_rx_queues = rss_i;
1529 	interface->num_tx_queues = rss_i;
1530 
1531 	return true;
1532 }
1533 
1534 /**
1535  * fm10k_set_num_queues: Allocate queues for device, feature dependent
1536  * @interface: board private structure to initialize
1537  *
1538  * This is the top level queue allocation routine.  The order here is very
1539  * important, starting with the "most" number of features turned on at once,
1540  * and ending with the smallest set of features.  This way large combinations
1541  * can be allocated if they're turned on, and smaller combinations are the
1542  * fall through conditions.
1543  *
1544  **/
1545 static void fm10k_set_num_queues(struct fm10k_intfc *interface)
1546 {
1547 	/* Attempt to setup QoS and RSS first */
1548 	if (fm10k_set_qos_queues(interface))
1549 		return;
1550 
1551 	/* If we don't have QoS, just fallback to only RSS. */
1552 	fm10k_set_rss_queues(interface);
1553 }
1554 
1555 /**
1556  * fm10k_reset_num_queues - Reset the number of queues to zero
1557  * @interface: board private structure
1558  *
1559  * This function should be called whenever we need to reset the number of
1560  * queues after an error condition.
1561  */
1562 static void fm10k_reset_num_queues(struct fm10k_intfc *interface)
1563 {
1564 	interface->num_tx_queues = 0;
1565 	interface->num_rx_queues = 0;
1566 	interface->num_q_vectors = 0;
1567 }
1568 
1569 /**
1570  * fm10k_alloc_q_vector - Allocate memory for a single interrupt vector
1571  * @interface: board private structure to initialize
1572  * @v_count: q_vectors allocated on interface, used for ring interleaving
1573  * @v_idx: index of vector in interface struct
1574  * @txr_count: total number of Tx rings to allocate
1575  * @txr_idx: index of first Tx ring to allocate
1576  * @rxr_count: total number of Rx rings to allocate
1577  * @rxr_idx: index of first Rx ring to allocate
1578  *
1579  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1580  **/
1581 static int fm10k_alloc_q_vector(struct fm10k_intfc *interface,
1582 				unsigned int v_count, unsigned int v_idx,
1583 				unsigned int txr_count, unsigned int txr_idx,
1584 				unsigned int rxr_count, unsigned int rxr_idx)
1585 {
1586 	struct fm10k_q_vector *q_vector;
1587 	struct fm10k_ring *ring;
1588 	int ring_count;
1589 
1590 	ring_count = txr_count + rxr_count;
1591 
1592 	/* allocate q_vector and rings */
1593 	q_vector = kzalloc(struct_size(q_vector, ring, ring_count), GFP_KERNEL);
1594 	if (!q_vector)
1595 		return -ENOMEM;
1596 
1597 	/* initialize NAPI */
1598 	netif_napi_add(interface->netdev, &q_vector->napi, fm10k_poll);
1599 
1600 	/* tie q_vector and interface together */
1601 	interface->q_vector[v_idx] = q_vector;
1602 	q_vector->interface = interface;
1603 	q_vector->v_idx = v_idx;
1604 
1605 	/* initialize pointer to rings */
1606 	ring = q_vector->ring;
1607 
1608 	/* save Tx ring container info */
1609 	q_vector->tx.ring = ring;
1610 	q_vector->tx.work_limit = FM10K_DEFAULT_TX_WORK;
1611 	q_vector->tx.itr = interface->tx_itr;
1612 	q_vector->tx.itr_scale = interface->hw.mac.itr_scale;
1613 	q_vector->tx.count = txr_count;
1614 
1615 	while (txr_count) {
1616 		/* assign generic ring traits */
1617 		ring->dev = &interface->pdev->dev;
1618 		ring->netdev = interface->netdev;
1619 
1620 		/* configure backlink on ring */
1621 		ring->q_vector = q_vector;
1622 
1623 		/* apply Tx specific ring traits */
1624 		ring->count = interface->tx_ring_count;
1625 		ring->queue_index = txr_idx;
1626 
1627 		/* assign ring to interface */
1628 		interface->tx_ring[txr_idx] = ring;
1629 
1630 		/* update count and index */
1631 		txr_count--;
1632 		txr_idx += v_count;
1633 
1634 		/* push pointer to next ring */
1635 		ring++;
1636 	}
1637 
1638 	/* save Rx ring container info */
1639 	q_vector->rx.ring = ring;
1640 	q_vector->rx.itr = interface->rx_itr;
1641 	q_vector->rx.itr_scale = interface->hw.mac.itr_scale;
1642 	q_vector->rx.count = rxr_count;
1643 
1644 	while (rxr_count) {
1645 		/* assign generic ring traits */
1646 		ring->dev = &interface->pdev->dev;
1647 		ring->netdev = interface->netdev;
1648 		rcu_assign_pointer(ring->l2_accel, interface->l2_accel);
1649 
1650 		/* configure backlink on ring */
1651 		ring->q_vector = q_vector;
1652 
1653 		/* apply Rx specific ring traits */
1654 		ring->count = interface->rx_ring_count;
1655 		ring->queue_index = rxr_idx;
1656 
1657 		/* assign ring to interface */
1658 		interface->rx_ring[rxr_idx] = ring;
1659 
1660 		/* update count and index */
1661 		rxr_count--;
1662 		rxr_idx += v_count;
1663 
1664 		/* push pointer to next ring */
1665 		ring++;
1666 	}
1667 
1668 	fm10k_dbg_q_vector_init(q_vector);
1669 
1670 	return 0;
1671 }
1672 
1673 /**
1674  * fm10k_free_q_vector - Free memory allocated for specific interrupt vector
1675  * @interface: board private structure to initialize
1676  * @v_idx: Index of vector to be freed
1677  *
1678  * This function frees the memory allocated to the q_vector.  In addition if
1679  * NAPI is enabled it will delete any references to the NAPI struct prior
1680  * to freeing the q_vector.
1681  **/
1682 static void fm10k_free_q_vector(struct fm10k_intfc *interface, int v_idx)
1683 {
1684 	struct fm10k_q_vector *q_vector = interface->q_vector[v_idx];
1685 	struct fm10k_ring *ring;
1686 
1687 	fm10k_dbg_q_vector_exit(q_vector);
1688 
1689 	fm10k_for_each_ring(ring, q_vector->tx)
1690 		interface->tx_ring[ring->queue_index] = NULL;
1691 
1692 	fm10k_for_each_ring(ring, q_vector->rx)
1693 		interface->rx_ring[ring->queue_index] = NULL;
1694 
1695 	interface->q_vector[v_idx] = NULL;
1696 	netif_napi_del(&q_vector->napi);
1697 	kfree_rcu(q_vector, rcu);
1698 }
1699 
1700 /**
1701  * fm10k_alloc_q_vectors - Allocate memory for interrupt vectors
1702  * @interface: board private structure to initialize
1703  *
1704  * We allocate one q_vector per queue interrupt.  If allocation fails we
1705  * return -ENOMEM.
1706  **/
1707 static int fm10k_alloc_q_vectors(struct fm10k_intfc *interface)
1708 {
1709 	unsigned int q_vectors = interface->num_q_vectors;
1710 	unsigned int rxr_remaining = interface->num_rx_queues;
1711 	unsigned int txr_remaining = interface->num_tx_queues;
1712 	unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1713 	int err;
1714 
1715 	if (q_vectors >= (rxr_remaining + txr_remaining)) {
1716 		for (; rxr_remaining; v_idx++) {
1717 			err = fm10k_alloc_q_vector(interface, q_vectors, v_idx,
1718 						   0, 0, 1, rxr_idx);
1719 			if (err)
1720 				goto err_out;
1721 
1722 			/* update counts and index */
1723 			rxr_remaining--;
1724 			rxr_idx++;
1725 		}
1726 	}
1727 
1728 	for (; v_idx < q_vectors; v_idx++) {
1729 		int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1730 		int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1731 
1732 		err = fm10k_alloc_q_vector(interface, q_vectors, v_idx,
1733 					   tqpv, txr_idx,
1734 					   rqpv, rxr_idx);
1735 
1736 		if (err)
1737 			goto err_out;
1738 
1739 		/* update counts and index */
1740 		rxr_remaining -= rqpv;
1741 		txr_remaining -= tqpv;
1742 		rxr_idx++;
1743 		txr_idx++;
1744 	}
1745 
1746 	return 0;
1747 
1748 err_out:
1749 	fm10k_reset_num_queues(interface);
1750 
1751 	while (v_idx--)
1752 		fm10k_free_q_vector(interface, v_idx);
1753 
1754 	return -ENOMEM;
1755 }
1756 
1757 /**
1758  * fm10k_free_q_vectors - Free memory allocated for interrupt vectors
1759  * @interface: board private structure to initialize
1760  *
1761  * This function frees the memory allocated to the q_vectors.  In addition if
1762  * NAPI is enabled it will delete any references to the NAPI struct prior
1763  * to freeing the q_vector.
1764  **/
1765 static void fm10k_free_q_vectors(struct fm10k_intfc *interface)
1766 {
1767 	int v_idx = interface->num_q_vectors;
1768 
1769 	fm10k_reset_num_queues(interface);
1770 
1771 	while (v_idx--)
1772 		fm10k_free_q_vector(interface, v_idx);
1773 }
1774 
1775 /**
1776  * fm10k_reset_msix_capability - reset MSI-X capability
1777  * @interface: board private structure to initialize
1778  *
1779  * Reset the MSI-X capability back to its starting state
1780  **/
1781 static void fm10k_reset_msix_capability(struct fm10k_intfc *interface)
1782 {
1783 	pci_disable_msix(interface->pdev);
1784 	kfree(interface->msix_entries);
1785 	interface->msix_entries = NULL;
1786 }
1787 
1788 /**
1789  * fm10k_init_msix_capability - configure MSI-X capability
1790  * @interface: board private structure to initialize
1791  *
1792  * Attempt to configure the interrupts using the best available
1793  * capabilities of the hardware and the kernel.
1794  **/
1795 static int fm10k_init_msix_capability(struct fm10k_intfc *interface)
1796 {
1797 	struct fm10k_hw *hw = &interface->hw;
1798 	int v_budget, vector;
1799 
1800 	/* It's easy to be greedy for MSI-X vectors, but it really
1801 	 * doesn't do us much good if we have a lot more vectors
1802 	 * than CPU's.  So let's be conservative and only ask for
1803 	 * (roughly) the same number of vectors as there are CPU's.
1804 	 * the default is to use pairs of vectors
1805 	 */
1806 	v_budget = max(interface->num_rx_queues, interface->num_tx_queues);
1807 	v_budget = min_t(u16, v_budget, num_online_cpus());
1808 
1809 	/* account for vectors not related to queues */
1810 	v_budget += NON_Q_VECTORS;
1811 
1812 	/* At the same time, hardware can only support a maximum of
1813 	 * hw.mac->max_msix_vectors vectors.  With features
1814 	 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
1815 	 * descriptor queues supported by our device.  Thus, we cap it off in
1816 	 * those rare cases where the cpu count also exceeds our vector limit.
1817 	 */
1818 	v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
1819 
1820 	/* A failure in MSI-X entry allocation is fatal. */
1821 	interface->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
1822 					  GFP_KERNEL);
1823 	if (!interface->msix_entries)
1824 		return -ENOMEM;
1825 
1826 	/* populate entry values */
1827 	for (vector = 0; vector < v_budget; vector++)
1828 		interface->msix_entries[vector].entry = vector;
1829 
1830 	/* Attempt to enable MSI-X with requested value */
1831 	v_budget = pci_enable_msix_range(interface->pdev,
1832 					 interface->msix_entries,
1833 					 MIN_MSIX_COUNT(hw),
1834 					 v_budget);
1835 	if (v_budget < 0) {
1836 		kfree(interface->msix_entries);
1837 		interface->msix_entries = NULL;
1838 		return v_budget;
1839 	}
1840 
1841 	/* record the number of queues available for q_vectors */
1842 	interface->num_q_vectors = v_budget - NON_Q_VECTORS;
1843 
1844 	return 0;
1845 }
1846 
1847 /**
1848  * fm10k_cache_ring_qos - Descriptor ring to register mapping for QoS
1849  * @interface: Interface structure continaining rings and devices
1850  *
1851  * Cache the descriptor ring offsets for Qos
1852  **/
1853 static bool fm10k_cache_ring_qos(struct fm10k_intfc *interface)
1854 {
1855 	struct net_device *dev = interface->netdev;
1856 	int pc, offset, rss_i, i;
1857 	u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1;
1858 	u8 num_pcs = netdev_get_num_tc(dev);
1859 
1860 	if (num_pcs <= 1)
1861 		return false;
1862 
1863 	rss_i = interface->ring_feature[RING_F_RSS].indices;
1864 
1865 	for (pc = 0, offset = 0; pc < num_pcs; pc++, offset += rss_i) {
1866 		int q_idx = pc;
1867 
1868 		for (i = 0; i < rss_i; i++) {
1869 			interface->tx_ring[offset + i]->reg_idx = q_idx;
1870 			interface->tx_ring[offset + i]->qos_pc = pc;
1871 			interface->rx_ring[offset + i]->reg_idx = q_idx;
1872 			interface->rx_ring[offset + i]->qos_pc = pc;
1873 			q_idx += pc_stride;
1874 		}
1875 	}
1876 
1877 	return true;
1878 }
1879 
1880 /**
1881  * fm10k_cache_ring_rss - Descriptor ring to register mapping for RSS
1882  * @interface: Interface structure continaining rings and devices
1883  *
1884  * Cache the descriptor ring offsets for RSS
1885  **/
1886 static void fm10k_cache_ring_rss(struct fm10k_intfc *interface)
1887 {
1888 	int i;
1889 
1890 	for (i = 0; i < interface->num_rx_queues; i++)
1891 		interface->rx_ring[i]->reg_idx = i;
1892 
1893 	for (i = 0; i < interface->num_tx_queues; i++)
1894 		interface->tx_ring[i]->reg_idx = i;
1895 }
1896 
1897 /**
1898  * fm10k_assign_rings - Map rings to network devices
1899  * @interface: Interface structure containing rings and devices
1900  *
1901  * This function is meant to go though and configure both the network
1902  * devices so that they contain rings, and configure the rings so that
1903  * they function with their network devices.
1904  **/
1905 static void fm10k_assign_rings(struct fm10k_intfc *interface)
1906 {
1907 	if (fm10k_cache_ring_qos(interface))
1908 		return;
1909 
1910 	fm10k_cache_ring_rss(interface);
1911 }
1912 
1913 static void fm10k_init_reta(struct fm10k_intfc *interface)
1914 {
1915 	u16 i, rss_i = interface->ring_feature[RING_F_RSS].indices;
1916 	u32 reta;
1917 
1918 	/* If the Rx flow indirection table has been configured manually, we
1919 	 * need to maintain it when possible.
1920 	 */
1921 	if (netif_is_rxfh_configured(interface->netdev)) {
1922 		for (i = FM10K_RETA_SIZE; i--;) {
1923 			reta = interface->reta[i];
1924 			if ((((reta << 24) >> 24) < rss_i) &&
1925 			    (((reta << 16) >> 24) < rss_i) &&
1926 			    (((reta <<  8) >> 24) < rss_i) &&
1927 			    (((reta)       >> 24) < rss_i))
1928 				continue;
1929 
1930 			/* this should never happen */
1931 			dev_err(&interface->pdev->dev,
1932 				"RSS indirection table assigned flows out of queue bounds. Reconfiguring.\n");
1933 			goto repopulate_reta;
1934 		}
1935 
1936 		/* do nothing if all of the elements are in bounds */
1937 		return;
1938 	}
1939 
1940 repopulate_reta:
1941 	fm10k_write_reta(interface, NULL);
1942 }
1943 
1944 /**
1945  * fm10k_init_queueing_scheme - Determine proper queueing scheme
1946  * @interface: board private structure to initialize
1947  *
1948  * We determine which queueing scheme to use based on...
1949  * - Hardware queue count (num_*_queues)
1950  *   - defined by miscellaneous hardware support/features (RSS, etc.)
1951  **/
1952 int fm10k_init_queueing_scheme(struct fm10k_intfc *interface)
1953 {
1954 	int err;
1955 
1956 	/* Number of supported queues */
1957 	fm10k_set_num_queues(interface);
1958 
1959 	/* Configure MSI-X capability */
1960 	err = fm10k_init_msix_capability(interface);
1961 	if (err) {
1962 		dev_err(&interface->pdev->dev,
1963 			"Unable to initialize MSI-X capability\n");
1964 		goto err_init_msix;
1965 	}
1966 
1967 	/* Allocate memory for queues */
1968 	err = fm10k_alloc_q_vectors(interface);
1969 	if (err) {
1970 		dev_err(&interface->pdev->dev,
1971 			"Unable to allocate queue vectors\n");
1972 		goto err_alloc_q_vectors;
1973 	}
1974 
1975 	/* Map rings to devices, and map devices to physical queues */
1976 	fm10k_assign_rings(interface);
1977 
1978 	/* Initialize RSS redirection table */
1979 	fm10k_init_reta(interface);
1980 
1981 	return 0;
1982 
1983 err_alloc_q_vectors:
1984 	fm10k_reset_msix_capability(interface);
1985 err_init_msix:
1986 	fm10k_reset_num_queues(interface);
1987 	return err;
1988 }
1989 
1990 /**
1991  * fm10k_clear_queueing_scheme - Clear the current queueing scheme settings
1992  * @interface: board private structure to clear queueing scheme on
1993  *
1994  * We go through and clear queueing specific resources and reset the structure
1995  * to pre-load conditions
1996  **/
1997 void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface)
1998 {
1999 	fm10k_free_q_vectors(interface);
2000 	fm10k_reset_msix_capability(interface);
2001 }
2002