1b3890e30SAlexander Duyck /* Intel Ethernet Switch Host Interface Driver 2b3890e30SAlexander Duyck * Copyright(c) 2013 - 2014 Intel Corporation. 3b3890e30SAlexander Duyck * 4b3890e30SAlexander Duyck * This program is free software; you can redistribute it and/or modify it 5b3890e30SAlexander Duyck * under the terms and conditions of the GNU General Public License, 6b3890e30SAlexander Duyck * version 2, as published by the Free Software Foundation. 7b3890e30SAlexander Duyck * 8b3890e30SAlexander Duyck * This program is distributed in the hope it will be useful, but WITHOUT 9b3890e30SAlexander Duyck * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10b3890e30SAlexander Duyck * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11b3890e30SAlexander Duyck * more details. 12b3890e30SAlexander Duyck * 13b3890e30SAlexander Duyck * The full GNU General Public License is included in this distribution in 14b3890e30SAlexander Duyck * the file called "COPYING". 15b3890e30SAlexander Duyck * 16b3890e30SAlexander Duyck * Contact Information: 17b3890e30SAlexander Duyck * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 18b3890e30SAlexander Duyck * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 19b3890e30SAlexander Duyck */ 20b3890e30SAlexander Duyck 21b3890e30SAlexander Duyck #include <linux/types.h> 22b3890e30SAlexander Duyck #include <linux/module.h> 23b3890e30SAlexander Duyck #include <net/ipv6.h> 24b3890e30SAlexander Duyck #include <net/ip.h> 25b3890e30SAlexander Duyck #include <net/tcp.h> 26b3890e30SAlexander Duyck #include <linux/if_macvlan.h> 27b101c962SAlexander Duyck #include <linux/prefetch.h> 28b3890e30SAlexander Duyck 29b3890e30SAlexander Duyck #include "fm10k.h" 30b3890e30SAlexander Duyck 31e3b6e95dSJacob Keller #define DRV_VERSION "0.19.3-k" 32b3890e30SAlexander Duyck const char fm10k_driver_version[] = DRV_VERSION; 33b3890e30SAlexander Duyck char fm10k_driver_name[] = "fm10k"; 34b3890e30SAlexander Duyck static const char fm10k_driver_string[] = 35b3890e30SAlexander Duyck "Intel(R) Ethernet Switch Host Interface Driver"; 36b3890e30SAlexander Duyck static const char fm10k_copyright[] = 37b3890e30SAlexander Duyck "Copyright (c) 2013 Intel Corporation."; 38b3890e30SAlexander Duyck 39b3890e30SAlexander Duyck MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 40b3890e30SAlexander Duyck MODULE_DESCRIPTION("Intel(R) Ethernet Switch Host Interface Driver"); 41b3890e30SAlexander Duyck MODULE_LICENSE("GPL"); 42b3890e30SAlexander Duyck MODULE_VERSION(DRV_VERSION); 43b3890e30SAlexander Duyck 44b382bb1bSJeff Kirsher /* single workqueue for entire fm10k driver */ 45b382bb1bSJeff Kirsher struct workqueue_struct *fm10k_workqueue = NULL; 46b382bb1bSJeff Kirsher 476d2ce900SAlexander Duyck /** 486d2ce900SAlexander Duyck * fm10k_init_module - Driver Registration Routine 49b3890e30SAlexander Duyck * 50b3890e30SAlexander Duyck * fm10k_init_module is the first routine called when the driver is 51b3890e30SAlexander Duyck * loaded. All it does is register with the PCI subsystem. 52b3890e30SAlexander Duyck **/ 53b3890e30SAlexander Duyck static int __init fm10k_init_module(void) 54b3890e30SAlexander Duyck { 55b3890e30SAlexander Duyck pr_info("%s - version %s\n", fm10k_driver_string, fm10k_driver_version); 56b3890e30SAlexander Duyck pr_info("%s\n", fm10k_copyright); 57b3890e30SAlexander Duyck 58b382bb1bSJeff Kirsher /* create driver workqueue */ 59b382bb1bSJeff Kirsher if (!fm10k_workqueue) 60b382bb1bSJeff Kirsher fm10k_workqueue = create_workqueue("fm10k"); 61b382bb1bSJeff Kirsher 627461fd91SAlexander Duyck fm10k_dbg_init(); 637461fd91SAlexander Duyck 64b3890e30SAlexander Duyck return fm10k_register_pci_driver(); 65b3890e30SAlexander Duyck } 66b3890e30SAlexander Duyck module_init(fm10k_init_module); 67b3890e30SAlexander Duyck 68b3890e30SAlexander Duyck /** 69b3890e30SAlexander Duyck * fm10k_exit_module - Driver Exit Cleanup Routine 70b3890e30SAlexander Duyck * 71b3890e30SAlexander Duyck * fm10k_exit_module is called just before the driver is removed 72b3890e30SAlexander Duyck * from memory. 73b3890e30SAlexander Duyck **/ 74b3890e30SAlexander Duyck static void __exit fm10k_exit_module(void) 75b3890e30SAlexander Duyck { 76b3890e30SAlexander Duyck fm10k_unregister_pci_driver(); 777461fd91SAlexander Duyck 787461fd91SAlexander Duyck fm10k_dbg_exit(); 79b382bb1bSJeff Kirsher 80b382bb1bSJeff Kirsher /* destroy driver workqueue */ 81b382bb1bSJeff Kirsher flush_workqueue(fm10k_workqueue); 82b382bb1bSJeff Kirsher destroy_workqueue(fm10k_workqueue); 83b382bb1bSJeff Kirsher fm10k_workqueue = NULL; 84b3890e30SAlexander Duyck } 85b3890e30SAlexander Duyck module_exit(fm10k_exit_module); 8618283cadSAlexander Duyck 87b101c962SAlexander Duyck static bool fm10k_alloc_mapped_page(struct fm10k_ring *rx_ring, 88b101c962SAlexander Duyck struct fm10k_rx_buffer *bi) 89b101c962SAlexander Duyck { 90b101c962SAlexander Duyck struct page *page = bi->page; 91b101c962SAlexander Duyck dma_addr_t dma; 92b101c962SAlexander Duyck 93b101c962SAlexander Duyck /* Only page will be NULL if buffer was consumed */ 94b101c962SAlexander Duyck if (likely(page)) 95b101c962SAlexander Duyck return true; 96b101c962SAlexander Duyck 97b101c962SAlexander Duyck /* alloc new page for storage */ 9842b17f09SAlexander Duyck page = dev_alloc_page(); 99b101c962SAlexander Duyck if (unlikely(!page)) { 100b101c962SAlexander Duyck rx_ring->rx_stats.alloc_failed++; 101b101c962SAlexander Duyck return false; 102b101c962SAlexander Duyck } 103b101c962SAlexander Duyck 104b101c962SAlexander Duyck /* map page for use */ 105b101c962SAlexander Duyck dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 106b101c962SAlexander Duyck 107b101c962SAlexander Duyck /* if mapping failed free memory back to system since 108b101c962SAlexander Duyck * there isn't much point in holding memory we can't use 109b101c962SAlexander Duyck */ 110b101c962SAlexander Duyck if (dma_mapping_error(rx_ring->dev, dma)) { 111b101c962SAlexander Duyck __free_page(page); 112b101c962SAlexander Duyck 113b101c962SAlexander Duyck rx_ring->rx_stats.alloc_failed++; 114b101c962SAlexander Duyck return false; 115b101c962SAlexander Duyck } 116b101c962SAlexander Duyck 117b101c962SAlexander Duyck bi->dma = dma; 118b101c962SAlexander Duyck bi->page = page; 119b101c962SAlexander Duyck bi->page_offset = 0; 120b101c962SAlexander Duyck 121b101c962SAlexander Duyck return true; 122b101c962SAlexander Duyck } 123b101c962SAlexander Duyck 124b101c962SAlexander Duyck /** 125b101c962SAlexander Duyck * fm10k_alloc_rx_buffers - Replace used receive buffers 126b101c962SAlexander Duyck * @rx_ring: ring to place buffers on 127b101c962SAlexander Duyck * @cleaned_count: number of buffers to replace 128b101c962SAlexander Duyck **/ 129b101c962SAlexander Duyck void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count) 130b101c962SAlexander Duyck { 131b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc; 132b101c962SAlexander Duyck struct fm10k_rx_buffer *bi; 133b101c962SAlexander Duyck u16 i = rx_ring->next_to_use; 134b101c962SAlexander Duyck 135b101c962SAlexander Duyck /* nothing to do */ 136b101c962SAlexander Duyck if (!cleaned_count) 137b101c962SAlexander Duyck return; 138b101c962SAlexander Duyck 139b101c962SAlexander Duyck rx_desc = FM10K_RX_DESC(rx_ring, i); 140b101c962SAlexander Duyck bi = &rx_ring->rx_buffer[i]; 141b101c962SAlexander Duyck i -= rx_ring->count; 142b101c962SAlexander Duyck 143b101c962SAlexander Duyck do { 144b101c962SAlexander Duyck if (!fm10k_alloc_mapped_page(rx_ring, bi)) 145b101c962SAlexander Duyck break; 146b101c962SAlexander Duyck 147b101c962SAlexander Duyck /* Refresh the desc even if buffer_addrs didn't change 148b101c962SAlexander Duyck * because each write-back erases this info. 149b101c962SAlexander Duyck */ 150b101c962SAlexander Duyck rx_desc->q.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 151b101c962SAlexander Duyck 152b101c962SAlexander Duyck rx_desc++; 153b101c962SAlexander Duyck bi++; 154b101c962SAlexander Duyck i++; 155b101c962SAlexander Duyck if (unlikely(!i)) { 156b101c962SAlexander Duyck rx_desc = FM10K_RX_DESC(rx_ring, 0); 157b101c962SAlexander Duyck bi = rx_ring->rx_buffer; 158b101c962SAlexander Duyck i -= rx_ring->count; 159b101c962SAlexander Duyck } 160b101c962SAlexander Duyck 161ba5b8dcdSAlexander Duyck /* clear the status bits for the next_to_use descriptor */ 162ba5b8dcdSAlexander Duyck rx_desc->d.staterr = 0; 163b101c962SAlexander Duyck 164b101c962SAlexander Duyck cleaned_count--; 165b101c962SAlexander Duyck } while (cleaned_count); 166b101c962SAlexander Duyck 167b101c962SAlexander Duyck i += rx_ring->count; 168b101c962SAlexander Duyck 169b101c962SAlexander Duyck if (rx_ring->next_to_use != i) { 170b101c962SAlexander Duyck /* record the next descriptor to use */ 171b101c962SAlexander Duyck rx_ring->next_to_use = i; 172b101c962SAlexander Duyck 173b101c962SAlexander Duyck /* update next to alloc since we have filled the ring */ 174b101c962SAlexander Duyck rx_ring->next_to_alloc = i; 175b101c962SAlexander Duyck 176b101c962SAlexander Duyck /* Force memory writes to complete before letting h/w 177b101c962SAlexander Duyck * know there are new descriptors to fetch. (Only 178b101c962SAlexander Duyck * applicable for weak-ordered memory model archs, 179b101c962SAlexander Duyck * such as IA-64). 180b101c962SAlexander Duyck */ 181b101c962SAlexander Duyck wmb(); 182b101c962SAlexander Duyck 183b101c962SAlexander Duyck /* notify hardware of new descriptors */ 184b101c962SAlexander Duyck writel(i, rx_ring->tail); 185b101c962SAlexander Duyck } 186b101c962SAlexander Duyck } 187b101c962SAlexander Duyck 188b101c962SAlexander Duyck /** 189b101c962SAlexander Duyck * fm10k_reuse_rx_page - page flip buffer and store it back on the ring 190b101c962SAlexander Duyck * @rx_ring: rx descriptor ring to store buffers on 191b101c962SAlexander Duyck * @old_buff: donor buffer to have page reused 192b101c962SAlexander Duyck * 193b101c962SAlexander Duyck * Synchronizes page for reuse by the interface 194b101c962SAlexander Duyck **/ 195b101c962SAlexander Duyck static void fm10k_reuse_rx_page(struct fm10k_ring *rx_ring, 196b101c962SAlexander Duyck struct fm10k_rx_buffer *old_buff) 197b101c962SAlexander Duyck { 198b101c962SAlexander Duyck struct fm10k_rx_buffer *new_buff; 199b101c962SAlexander Duyck u16 nta = rx_ring->next_to_alloc; 200b101c962SAlexander Duyck 201b101c962SAlexander Duyck new_buff = &rx_ring->rx_buffer[nta]; 202b101c962SAlexander Duyck 203b101c962SAlexander Duyck /* update, and store next to alloc */ 204b101c962SAlexander Duyck nta++; 205b101c962SAlexander Duyck rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 206b101c962SAlexander Duyck 207b101c962SAlexander Duyck /* transfer page from old buffer to new buffer */ 208ba5b8dcdSAlexander Duyck *new_buff = *old_buff; 209b101c962SAlexander Duyck 210b101c962SAlexander Duyck /* sync the buffer for use by the device */ 211b101c962SAlexander Duyck dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 212b101c962SAlexander Duyck old_buff->page_offset, 213b101c962SAlexander Duyck FM10K_RX_BUFSZ, 214b101c962SAlexander Duyck DMA_FROM_DEVICE); 215b101c962SAlexander Duyck } 216b101c962SAlexander Duyck 217ba5b8dcdSAlexander Duyck static inline bool fm10k_page_is_reserved(struct page *page) 218ba5b8dcdSAlexander Duyck { 2192f064f34SMichal Hocko return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 220ba5b8dcdSAlexander Duyck } 221ba5b8dcdSAlexander Duyck 222b101c962SAlexander Duyck static bool fm10k_can_reuse_rx_page(struct fm10k_rx_buffer *rx_buffer, 223b101c962SAlexander Duyck struct page *page, 224de445199SJeff Kirsher unsigned int __maybe_unused truesize) 225b101c962SAlexander Duyck { 226b101c962SAlexander Duyck /* avoid re-using remote pages */ 227ba5b8dcdSAlexander Duyck if (unlikely(fm10k_page_is_reserved(page))) 228b101c962SAlexander Duyck return false; 229b101c962SAlexander Duyck 230b101c962SAlexander Duyck #if (PAGE_SIZE < 8192) 231b101c962SAlexander Duyck /* if we are only owner of page we can reuse it */ 232b101c962SAlexander Duyck if (unlikely(page_count(page) != 1)) 233b101c962SAlexander Duyck return false; 234b101c962SAlexander Duyck 235b101c962SAlexander Duyck /* flip page offset to other buffer */ 236b101c962SAlexander Duyck rx_buffer->page_offset ^= FM10K_RX_BUFSZ; 237b101c962SAlexander Duyck #else 238b101c962SAlexander Duyck /* move offset up to the next cache line */ 239b101c962SAlexander Duyck rx_buffer->page_offset += truesize; 240b101c962SAlexander Duyck 241b101c962SAlexander Duyck if (rx_buffer->page_offset > (PAGE_SIZE - FM10K_RX_BUFSZ)) 242b101c962SAlexander Duyck return false; 243b101c962SAlexander Duyck #endif 244b101c962SAlexander Duyck 245ba5b8dcdSAlexander Duyck /* Even if we own the page, we are not allowed to use atomic_set() 246ba5b8dcdSAlexander Duyck * This would break get_page_unless_zero() users. 247ba5b8dcdSAlexander Duyck */ 248ba5b8dcdSAlexander Duyck atomic_inc(&page->_count); 249ba5b8dcdSAlexander Duyck 250b101c962SAlexander Duyck return true; 251b101c962SAlexander Duyck } 252b101c962SAlexander Duyck 253b101c962SAlexander Duyck /** 254b101c962SAlexander Duyck * fm10k_add_rx_frag - Add contents of Rx buffer to sk_buff 255b101c962SAlexander Duyck * @rx_buffer: buffer containing page to add 256b101c962SAlexander Duyck * @rx_desc: descriptor containing length of buffer written by hardware 257b101c962SAlexander Duyck * @skb: sk_buff to place the data into 258b101c962SAlexander Duyck * 259b101c962SAlexander Duyck * This function will add the data contained in rx_buffer->page to the skb. 260b101c962SAlexander Duyck * This is done either through a direct copy if the data in the buffer is 261b101c962SAlexander Duyck * less than the skb header size, otherwise it will just attach the page as 262b101c962SAlexander Duyck * a frag to the skb. 263b101c962SAlexander Duyck * 264b101c962SAlexander Duyck * The function will then update the page offset if necessary and return 265b101c962SAlexander Duyck * true if the buffer can be reused by the interface. 266b101c962SAlexander Duyck **/ 267de445199SJeff Kirsher static bool fm10k_add_rx_frag(struct fm10k_rx_buffer *rx_buffer, 268b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc, 269b101c962SAlexander Duyck struct sk_buff *skb) 270b101c962SAlexander Duyck { 271b101c962SAlexander Duyck struct page *page = rx_buffer->page; 2721a8782e5SAlexander Duyck unsigned char *va = page_address(page) + rx_buffer->page_offset; 273b101c962SAlexander Duyck unsigned int size = le16_to_cpu(rx_desc->w.length); 274b101c962SAlexander Duyck #if (PAGE_SIZE < 8192) 275b101c962SAlexander Duyck unsigned int truesize = FM10K_RX_BUFSZ; 276b101c962SAlexander Duyck #else 2771a8782e5SAlexander Duyck unsigned int truesize = SKB_DATA_ALIGN(size); 278b101c962SAlexander Duyck #endif 2791a8782e5SAlexander Duyck unsigned int pull_len; 280b101c962SAlexander Duyck 2811a8782e5SAlexander Duyck if (unlikely(skb_is_nonlinear(skb))) 2821a8782e5SAlexander Duyck goto add_tail_frag; 283b101c962SAlexander Duyck 2841a8782e5SAlexander Duyck if (likely(size <= FM10K_RX_HDR_LEN)) { 285b101c962SAlexander Duyck memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 286b101c962SAlexander Duyck 287ba5b8dcdSAlexander Duyck /* page is not reserved, we can reuse buffer as-is */ 288ba5b8dcdSAlexander Duyck if (likely(!fm10k_page_is_reserved(page))) 289b101c962SAlexander Duyck return true; 290b101c962SAlexander Duyck 291b101c962SAlexander Duyck /* this page cannot be reused so discard it */ 292ba5b8dcdSAlexander Duyck __free_page(page); 293b101c962SAlexander Duyck return false; 294b101c962SAlexander Duyck } 295b101c962SAlexander Duyck 2961a8782e5SAlexander Duyck /* we need the header to contain the greater of either ETH_HLEN or 2971a8782e5SAlexander Duyck * 60 bytes if the skb->len is less than 60 for skb_pad. 2981a8782e5SAlexander Duyck */ 2991a8782e5SAlexander Duyck pull_len = eth_get_headlen(va, FM10K_RX_HDR_LEN); 3001a8782e5SAlexander Duyck 3011a8782e5SAlexander Duyck /* align pull length to size of long to optimize memcpy performance */ 3021a8782e5SAlexander Duyck memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); 3031a8782e5SAlexander Duyck 3041a8782e5SAlexander Duyck /* update all of the pointers */ 3051a8782e5SAlexander Duyck va += pull_len; 3061a8782e5SAlexander Duyck size -= pull_len; 3071a8782e5SAlexander Duyck 3081a8782e5SAlexander Duyck add_tail_frag: 309b101c962SAlexander Duyck skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 3101a8782e5SAlexander Duyck (unsigned long)va & ~PAGE_MASK, size, truesize); 311b101c962SAlexander Duyck 312b101c962SAlexander Duyck return fm10k_can_reuse_rx_page(rx_buffer, page, truesize); 313b101c962SAlexander Duyck } 314b101c962SAlexander Duyck 315b101c962SAlexander Duyck static struct sk_buff *fm10k_fetch_rx_buffer(struct fm10k_ring *rx_ring, 316b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc, 317b101c962SAlexander Duyck struct sk_buff *skb) 318b101c962SAlexander Duyck { 319b101c962SAlexander Duyck struct fm10k_rx_buffer *rx_buffer; 320b101c962SAlexander Duyck struct page *page; 321b101c962SAlexander Duyck 322b101c962SAlexander Duyck rx_buffer = &rx_ring->rx_buffer[rx_ring->next_to_clean]; 323b101c962SAlexander Duyck page = rx_buffer->page; 324b101c962SAlexander Duyck prefetchw(page); 325b101c962SAlexander Duyck 326b101c962SAlexander Duyck if (likely(!skb)) { 327b101c962SAlexander Duyck void *page_addr = page_address(page) + 328b101c962SAlexander Duyck rx_buffer->page_offset; 329b101c962SAlexander Duyck 330b101c962SAlexander Duyck /* prefetch first cache line of first page */ 331b101c962SAlexander Duyck prefetch(page_addr); 332b101c962SAlexander Duyck #if L1_CACHE_BYTES < 128 333b101c962SAlexander Duyck prefetch(page_addr + L1_CACHE_BYTES); 334b101c962SAlexander Duyck #endif 335b101c962SAlexander Duyck 336b101c962SAlexander Duyck /* allocate a skb to store the frags */ 33767fd893eSAlexander Duyck skb = napi_alloc_skb(&rx_ring->q_vector->napi, 338b101c962SAlexander Duyck FM10K_RX_HDR_LEN); 339b101c962SAlexander Duyck if (unlikely(!skb)) { 340b101c962SAlexander Duyck rx_ring->rx_stats.alloc_failed++; 341b101c962SAlexander Duyck return NULL; 342b101c962SAlexander Duyck } 343b101c962SAlexander Duyck 344b101c962SAlexander Duyck /* we will be copying header into skb->data in 345b101c962SAlexander Duyck * pskb_may_pull so it is in our interest to prefetch 346b101c962SAlexander Duyck * it now to avoid a possible cache miss 347b101c962SAlexander Duyck */ 348b101c962SAlexander Duyck prefetchw(skb->data); 349b101c962SAlexander Duyck } 350b101c962SAlexander Duyck 351b101c962SAlexander Duyck /* we are reusing so sync this buffer for CPU use */ 352b101c962SAlexander Duyck dma_sync_single_range_for_cpu(rx_ring->dev, 353b101c962SAlexander Duyck rx_buffer->dma, 354b101c962SAlexander Duyck rx_buffer->page_offset, 355b101c962SAlexander Duyck FM10K_RX_BUFSZ, 356b101c962SAlexander Duyck DMA_FROM_DEVICE); 357b101c962SAlexander Duyck 358b101c962SAlexander Duyck /* pull page into skb */ 359de445199SJeff Kirsher if (fm10k_add_rx_frag(rx_buffer, rx_desc, skb)) { 360b101c962SAlexander Duyck /* hand second half of page back to the ring */ 361b101c962SAlexander Duyck fm10k_reuse_rx_page(rx_ring, rx_buffer); 362b101c962SAlexander Duyck } else { 363b101c962SAlexander Duyck /* we are not reusing the buffer so unmap it */ 364b101c962SAlexander Duyck dma_unmap_page(rx_ring->dev, rx_buffer->dma, 365b101c962SAlexander Duyck PAGE_SIZE, DMA_FROM_DEVICE); 366b101c962SAlexander Duyck } 367b101c962SAlexander Duyck 368b101c962SAlexander Duyck /* clear contents of rx_buffer */ 369b101c962SAlexander Duyck rx_buffer->page = NULL; 370b101c962SAlexander Duyck 371b101c962SAlexander Duyck return skb; 372b101c962SAlexander Duyck } 373b101c962SAlexander Duyck 37476a540d4SAlexander Duyck static inline void fm10k_rx_checksum(struct fm10k_ring *ring, 37576a540d4SAlexander Duyck union fm10k_rx_desc *rx_desc, 37676a540d4SAlexander Duyck struct sk_buff *skb) 37776a540d4SAlexander Duyck { 37876a540d4SAlexander Duyck skb_checksum_none_assert(skb); 37976a540d4SAlexander Duyck 38076a540d4SAlexander Duyck /* Rx checksum disabled via ethtool */ 38176a540d4SAlexander Duyck if (!(ring->netdev->features & NETIF_F_RXCSUM)) 38276a540d4SAlexander Duyck return; 38376a540d4SAlexander Duyck 38476a540d4SAlexander Duyck /* TCP/UDP checksum error bit is set */ 38576a540d4SAlexander Duyck if (fm10k_test_staterr(rx_desc, 38676a540d4SAlexander Duyck FM10K_RXD_STATUS_L4E | 38776a540d4SAlexander Duyck FM10K_RXD_STATUS_L4E2 | 38876a540d4SAlexander Duyck FM10K_RXD_STATUS_IPE | 38976a540d4SAlexander Duyck FM10K_RXD_STATUS_IPE2)) { 39076a540d4SAlexander Duyck ring->rx_stats.csum_err++; 39176a540d4SAlexander Duyck return; 39276a540d4SAlexander Duyck } 39376a540d4SAlexander Duyck 39476a540d4SAlexander Duyck /* It must be a TCP or UDP packet with a valid checksum */ 39576a540d4SAlexander Duyck if (fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS2)) 39676a540d4SAlexander Duyck skb->encapsulation = true; 39776a540d4SAlexander Duyck else if (!fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS)) 39876a540d4SAlexander Duyck return; 39976a540d4SAlexander Duyck 40076a540d4SAlexander Duyck skb->ip_summed = CHECKSUM_UNNECESSARY; 40180043f3bSJacob Keller 40280043f3bSJacob Keller ring->rx_stats.csum_good++; 40376a540d4SAlexander Duyck } 40476a540d4SAlexander Duyck 40576a540d4SAlexander Duyck #define FM10K_RSS_L4_TYPES_MASK \ 40676a540d4SAlexander Duyck ((1ul << FM10K_RSSTYPE_IPV4_TCP) | \ 40776a540d4SAlexander Duyck (1ul << FM10K_RSSTYPE_IPV4_UDP) | \ 40876a540d4SAlexander Duyck (1ul << FM10K_RSSTYPE_IPV6_TCP) | \ 40976a540d4SAlexander Duyck (1ul << FM10K_RSSTYPE_IPV6_UDP)) 41076a540d4SAlexander Duyck 41176a540d4SAlexander Duyck static inline void fm10k_rx_hash(struct fm10k_ring *ring, 41276a540d4SAlexander Duyck union fm10k_rx_desc *rx_desc, 41376a540d4SAlexander Duyck struct sk_buff *skb) 41476a540d4SAlexander Duyck { 41576a540d4SAlexander Duyck u16 rss_type; 41676a540d4SAlexander Duyck 41776a540d4SAlexander Duyck if (!(ring->netdev->features & NETIF_F_RXHASH)) 41876a540d4SAlexander Duyck return; 41976a540d4SAlexander Duyck 42076a540d4SAlexander Duyck rss_type = le16_to_cpu(rx_desc->w.pkt_info) & FM10K_RXD_RSSTYPE_MASK; 42176a540d4SAlexander Duyck if (!rss_type) 42276a540d4SAlexander Duyck return; 42376a540d4SAlexander Duyck 42476a540d4SAlexander Duyck skb_set_hash(skb, le32_to_cpu(rx_desc->d.rss), 42576a540d4SAlexander Duyck (FM10K_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 42676a540d4SAlexander Duyck PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 42776a540d4SAlexander Duyck } 42876a540d4SAlexander Duyck 429a211e013SAlexander Duyck static void fm10k_rx_hwtstamp(struct fm10k_ring *rx_ring, 430a211e013SAlexander Duyck union fm10k_rx_desc *rx_desc, 431a211e013SAlexander Duyck struct sk_buff *skb) 432a211e013SAlexander Duyck { 433a211e013SAlexander Duyck struct fm10k_intfc *interface = rx_ring->q_vector->interface; 434a211e013SAlexander Duyck 435a211e013SAlexander Duyck FM10K_CB(skb)->tstamp = rx_desc->q.timestamp; 436a211e013SAlexander Duyck 437a211e013SAlexander Duyck if (unlikely(interface->flags & FM10K_FLAG_RX_TS_ENABLED)) 438a211e013SAlexander Duyck fm10k_systime_to_hwtstamp(interface, skb_hwtstamps(skb), 439a211e013SAlexander Duyck le64_to_cpu(rx_desc->q.timestamp)); 440a211e013SAlexander Duyck } 441a211e013SAlexander Duyck 4425cd5e2e9SAlexander Duyck static void fm10k_type_trans(struct fm10k_ring *rx_ring, 443de445199SJeff Kirsher union fm10k_rx_desc __maybe_unused *rx_desc, 4445cd5e2e9SAlexander Duyck struct sk_buff *skb) 4455cd5e2e9SAlexander Duyck { 4465cd5e2e9SAlexander Duyck struct net_device *dev = rx_ring->netdev; 4475cd5e2e9SAlexander Duyck struct fm10k_l2_accel *l2_accel = rcu_dereference_bh(rx_ring->l2_accel); 4485cd5e2e9SAlexander Duyck 4495cd5e2e9SAlexander Duyck /* check to see if DGLORT belongs to a MACVLAN */ 4505cd5e2e9SAlexander Duyck if (l2_accel) { 4515cd5e2e9SAlexander Duyck u16 idx = le16_to_cpu(FM10K_CB(skb)->fi.w.dglort) - 1; 4525cd5e2e9SAlexander Duyck 4535cd5e2e9SAlexander Duyck idx -= l2_accel->dglort; 4545cd5e2e9SAlexander Duyck if (idx < l2_accel->size && l2_accel->macvlan[idx]) 4555cd5e2e9SAlexander Duyck dev = l2_accel->macvlan[idx]; 4565cd5e2e9SAlexander Duyck else 4575cd5e2e9SAlexander Duyck l2_accel = NULL; 4585cd5e2e9SAlexander Duyck } 4595cd5e2e9SAlexander Duyck 4605cd5e2e9SAlexander Duyck skb->protocol = eth_type_trans(skb, dev); 4615cd5e2e9SAlexander Duyck 4625cd5e2e9SAlexander Duyck if (!l2_accel) 4635cd5e2e9SAlexander Duyck return; 4645cd5e2e9SAlexander Duyck 4655cd5e2e9SAlexander Duyck /* update MACVLAN statistics */ 4665cd5e2e9SAlexander Duyck macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, 1, 4675cd5e2e9SAlexander Duyck !!(rx_desc->w.hdr_info & 4685cd5e2e9SAlexander Duyck cpu_to_le16(FM10K_RXD_HDR_INFO_XC_MASK))); 4695cd5e2e9SAlexander Duyck } 4705cd5e2e9SAlexander Duyck 471b101c962SAlexander Duyck /** 472b101c962SAlexander Duyck * fm10k_process_skb_fields - Populate skb header fields from Rx descriptor 473b101c962SAlexander Duyck * @rx_ring: rx descriptor ring packet is being transacted on 474b101c962SAlexander Duyck * @rx_desc: pointer to the EOP Rx descriptor 475b101c962SAlexander Duyck * @skb: pointer to current skb being populated 476b101c962SAlexander Duyck * 477b101c962SAlexander Duyck * This function checks the ring, descriptor, and packet information in 478b101c962SAlexander Duyck * order to populate the hash, checksum, VLAN, timestamp, protocol, and 479b101c962SAlexander Duyck * other fields within the skb. 480b101c962SAlexander Duyck **/ 481b101c962SAlexander Duyck static unsigned int fm10k_process_skb_fields(struct fm10k_ring *rx_ring, 482b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc, 483b101c962SAlexander Duyck struct sk_buff *skb) 484b101c962SAlexander Duyck { 485b101c962SAlexander Duyck unsigned int len = skb->len; 486b101c962SAlexander Duyck 48776a540d4SAlexander Duyck fm10k_rx_hash(rx_ring, rx_desc, skb); 48876a540d4SAlexander Duyck 48976a540d4SAlexander Duyck fm10k_rx_checksum(rx_ring, rx_desc, skb); 49076a540d4SAlexander Duyck 491a211e013SAlexander Duyck fm10k_rx_hwtstamp(rx_ring, rx_desc, skb); 492a211e013SAlexander Duyck 493b101c962SAlexander Duyck FM10K_CB(skb)->fi.w.vlan = rx_desc->w.vlan; 494b101c962SAlexander Duyck 495b101c962SAlexander Duyck skb_record_rx_queue(skb, rx_ring->queue_index); 496b101c962SAlexander Duyck 497b101c962SAlexander Duyck FM10K_CB(skb)->fi.d.glort = rx_desc->d.glort; 498b101c962SAlexander Duyck 499b101c962SAlexander Duyck if (rx_desc->w.vlan) { 500b101c962SAlexander Duyck u16 vid = le16_to_cpu(rx_desc->w.vlan); 501b101c962SAlexander Duyck 502e71c9318SJacob Keller if ((vid & VLAN_VID_MASK) != rx_ring->vid) 503b101c962SAlexander Duyck __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 504e71c9318SJacob Keller else if (vid & VLAN_PRIO_MASK) 505e71c9318SJacob Keller __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 506e71c9318SJacob Keller vid & VLAN_PRIO_MASK); 507b101c962SAlexander Duyck } 508b101c962SAlexander Duyck 5095cd5e2e9SAlexander Duyck fm10k_type_trans(rx_ring, rx_desc, skb); 510b101c962SAlexander Duyck 511b101c962SAlexander Duyck return len; 512b101c962SAlexander Duyck } 513b101c962SAlexander Duyck 514b101c962SAlexander Duyck /** 515b101c962SAlexander Duyck * fm10k_is_non_eop - process handling of non-EOP buffers 516b101c962SAlexander Duyck * @rx_ring: Rx ring being processed 517b101c962SAlexander Duyck * @rx_desc: Rx descriptor for current buffer 518b101c962SAlexander Duyck * 519b101c962SAlexander Duyck * This function updates next to clean. If the buffer is an EOP buffer 520b101c962SAlexander Duyck * this function exits returning false, otherwise it will place the 521b101c962SAlexander Duyck * sk_buff in the next buffer to be chained and return true indicating 522b101c962SAlexander Duyck * that this is in fact a non-EOP buffer. 523b101c962SAlexander Duyck **/ 524b101c962SAlexander Duyck static bool fm10k_is_non_eop(struct fm10k_ring *rx_ring, 525b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc) 526b101c962SAlexander Duyck { 527b101c962SAlexander Duyck u32 ntc = rx_ring->next_to_clean + 1; 528b101c962SAlexander Duyck 529b101c962SAlexander Duyck /* fetch, update, and store next to clean */ 530b101c962SAlexander Duyck ntc = (ntc < rx_ring->count) ? ntc : 0; 531b101c962SAlexander Duyck rx_ring->next_to_clean = ntc; 532b101c962SAlexander Duyck 533b101c962SAlexander Duyck prefetch(FM10K_RX_DESC(rx_ring, ntc)); 534b101c962SAlexander Duyck 535b101c962SAlexander Duyck if (likely(fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_EOP))) 536b101c962SAlexander Duyck return false; 537b101c962SAlexander Duyck 538b101c962SAlexander Duyck return true; 539b101c962SAlexander Duyck } 540b101c962SAlexander Duyck 541b101c962SAlexander Duyck /** 542b101c962SAlexander Duyck * fm10k_cleanup_headers - Correct corrupted or empty headers 543b101c962SAlexander Duyck * @rx_ring: rx descriptor ring packet is being transacted on 544b101c962SAlexander Duyck * @rx_desc: pointer to the EOP Rx descriptor 545b101c962SAlexander Duyck * @skb: pointer to current skb being fixed 546b101c962SAlexander Duyck * 547b101c962SAlexander Duyck * Address the case where we are pulling data in on pages only 548b101c962SAlexander Duyck * and as such no data is present in the skb header. 549b101c962SAlexander Duyck * 550b101c962SAlexander Duyck * In addition if skb is not at least 60 bytes we need to pad it so that 551b101c962SAlexander Duyck * it is large enough to qualify as a valid Ethernet frame. 552b101c962SAlexander Duyck * 553b101c962SAlexander Duyck * Returns true if an error was encountered and skb was freed. 554b101c962SAlexander Duyck **/ 555b101c962SAlexander Duyck static bool fm10k_cleanup_headers(struct fm10k_ring *rx_ring, 556b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc, 557b101c962SAlexander Duyck struct sk_buff *skb) 558b101c962SAlexander Duyck { 559b101c962SAlexander Duyck if (unlikely((fm10k_test_staterr(rx_desc, 560b101c962SAlexander Duyck FM10K_RXD_STATUS_RXE)))) { 56180043f3bSJacob Keller #define FM10K_TEST_RXD_BIT(rxd, bit) \ 56280043f3bSJacob Keller ((rxd)->w.csum_err & cpu_to_le16(bit)) 56380043f3bSJacob Keller if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_ERROR)) 56480043f3bSJacob Keller rx_ring->rx_stats.switch_errors++; 56580043f3bSJacob Keller if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_NO_DESCRIPTOR)) 56680043f3bSJacob Keller rx_ring->rx_stats.drops++; 56780043f3bSJacob Keller if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_PP_ERROR)) 56880043f3bSJacob Keller rx_ring->rx_stats.pp_errors++; 56980043f3bSJacob Keller if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_READY)) 57080043f3bSJacob Keller rx_ring->rx_stats.link_errors++; 57180043f3bSJacob Keller if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_TOO_BIG)) 57280043f3bSJacob Keller rx_ring->rx_stats.length_errors++; 573b101c962SAlexander Duyck dev_kfree_skb_any(skb); 574b101c962SAlexander Duyck rx_ring->rx_stats.errors++; 575b101c962SAlexander Duyck return true; 576b101c962SAlexander Duyck } 577b101c962SAlexander Duyck 578a94d9e22SAlexander Duyck /* if eth_skb_pad returns an error the skb was freed */ 579a94d9e22SAlexander Duyck if (eth_skb_pad(skb)) 580b101c962SAlexander Duyck return true; 581b101c962SAlexander Duyck 582b101c962SAlexander Duyck return false; 583b101c962SAlexander Duyck } 584b101c962SAlexander Duyck 585b101c962SAlexander Duyck /** 586b101c962SAlexander Duyck * fm10k_receive_skb - helper function to handle rx indications 587b101c962SAlexander Duyck * @q_vector: structure containing interrupt and ring information 588b101c962SAlexander Duyck * @skb: packet to send up 589b101c962SAlexander Duyck **/ 590b101c962SAlexander Duyck static void fm10k_receive_skb(struct fm10k_q_vector *q_vector, 591b101c962SAlexander Duyck struct sk_buff *skb) 592b101c962SAlexander Duyck { 593b101c962SAlexander Duyck napi_gro_receive(&q_vector->napi, skb); 594b101c962SAlexander Duyck } 595b101c962SAlexander Duyck 59632b3e08fSJesse Brandeburg static int fm10k_clean_rx_irq(struct fm10k_q_vector *q_vector, 597b101c962SAlexander Duyck struct fm10k_ring *rx_ring, 598b101c962SAlexander Duyck int budget) 599b101c962SAlexander Duyck { 600b101c962SAlexander Duyck struct sk_buff *skb = rx_ring->skb; 601b101c962SAlexander Duyck unsigned int total_bytes = 0, total_packets = 0; 602b101c962SAlexander Duyck u16 cleaned_count = fm10k_desc_unused(rx_ring); 603b101c962SAlexander Duyck 60459486329SAlexander Duyck while (likely(total_packets < budget)) { 605b101c962SAlexander Duyck union fm10k_rx_desc *rx_desc; 606b101c962SAlexander Duyck 607b101c962SAlexander Duyck /* return some buffers to hardware, one at a time is too slow */ 608b101c962SAlexander Duyck if (cleaned_count >= FM10K_RX_BUFFER_WRITE) { 609b101c962SAlexander Duyck fm10k_alloc_rx_buffers(rx_ring, cleaned_count); 610b101c962SAlexander Duyck cleaned_count = 0; 611b101c962SAlexander Duyck } 612b101c962SAlexander Duyck 613b101c962SAlexander Duyck rx_desc = FM10K_RX_DESC(rx_ring, rx_ring->next_to_clean); 614b101c962SAlexander Duyck 615124b74c1SAlexander Duyck if (!rx_desc->d.staterr) 616b101c962SAlexander Duyck break; 617b101c962SAlexander Duyck 618b101c962SAlexander Duyck /* This memory barrier is needed to keep us from reading 619b101c962SAlexander Duyck * any other fields out of the rx_desc until we know the 620124b74c1SAlexander Duyck * descriptor has been written back 621b101c962SAlexander Duyck */ 622124b74c1SAlexander Duyck dma_rmb(); 623b101c962SAlexander Duyck 624b101c962SAlexander Duyck /* retrieve a buffer from the ring */ 625b101c962SAlexander Duyck skb = fm10k_fetch_rx_buffer(rx_ring, rx_desc, skb); 626b101c962SAlexander Duyck 627b101c962SAlexander Duyck /* exit if we failed to retrieve a buffer */ 628b101c962SAlexander Duyck if (!skb) 629b101c962SAlexander Duyck break; 630b101c962SAlexander Duyck 631b101c962SAlexander Duyck cleaned_count++; 632b101c962SAlexander Duyck 633b101c962SAlexander Duyck /* fetch next buffer in frame if non-eop */ 634b101c962SAlexander Duyck if (fm10k_is_non_eop(rx_ring, rx_desc)) 635b101c962SAlexander Duyck continue; 636b101c962SAlexander Duyck 637b101c962SAlexander Duyck /* verify the packet layout is correct */ 638b101c962SAlexander Duyck if (fm10k_cleanup_headers(rx_ring, rx_desc, skb)) { 639b101c962SAlexander Duyck skb = NULL; 640b101c962SAlexander Duyck continue; 641b101c962SAlexander Duyck } 642b101c962SAlexander Duyck 643b101c962SAlexander Duyck /* populate checksum, timestamp, VLAN, and protocol */ 644b101c962SAlexander Duyck total_bytes += fm10k_process_skb_fields(rx_ring, rx_desc, skb); 645b101c962SAlexander Duyck 646b101c962SAlexander Duyck fm10k_receive_skb(q_vector, skb); 647b101c962SAlexander Duyck 648b101c962SAlexander Duyck /* reset skb pointer */ 649b101c962SAlexander Duyck skb = NULL; 650b101c962SAlexander Duyck 651b101c962SAlexander Duyck /* update budget accounting */ 652b101c962SAlexander Duyck total_packets++; 65359486329SAlexander Duyck } 654b101c962SAlexander Duyck 655b101c962SAlexander Duyck /* place incomplete frames back on ring for completion */ 656b101c962SAlexander Duyck rx_ring->skb = skb; 657b101c962SAlexander Duyck 658b101c962SAlexander Duyck u64_stats_update_begin(&rx_ring->syncp); 659b101c962SAlexander Duyck rx_ring->stats.packets += total_packets; 660b101c962SAlexander Duyck rx_ring->stats.bytes += total_bytes; 661b101c962SAlexander Duyck u64_stats_update_end(&rx_ring->syncp); 662b101c962SAlexander Duyck q_vector->rx.total_packets += total_packets; 663b101c962SAlexander Duyck q_vector->rx.total_bytes += total_bytes; 664b101c962SAlexander Duyck 66532b3e08fSJesse Brandeburg return total_packets; 666b101c962SAlexander Duyck } 667b101c962SAlexander Duyck 66876a540d4SAlexander Duyck #define VXLAN_HLEN (sizeof(struct udphdr) + 8) 66976a540d4SAlexander Duyck static struct ethhdr *fm10k_port_is_vxlan(struct sk_buff *skb) 67076a540d4SAlexander Duyck { 67176a540d4SAlexander Duyck struct fm10k_intfc *interface = netdev_priv(skb->dev); 67276a540d4SAlexander Duyck struct fm10k_vxlan_port *vxlan_port; 67376a540d4SAlexander Duyck 67476a540d4SAlexander Duyck /* we can only offload a vxlan if we recognize it as such */ 67576a540d4SAlexander Duyck vxlan_port = list_first_entry_or_null(&interface->vxlan_port, 67676a540d4SAlexander Duyck struct fm10k_vxlan_port, list); 67776a540d4SAlexander Duyck 67876a540d4SAlexander Duyck if (!vxlan_port) 67976a540d4SAlexander Duyck return NULL; 68076a540d4SAlexander Duyck if (vxlan_port->port != udp_hdr(skb)->dest) 68176a540d4SAlexander Duyck return NULL; 68276a540d4SAlexander Duyck 68376a540d4SAlexander Duyck /* return offset of udp_hdr plus 8 bytes for VXLAN header */ 68476a540d4SAlexander Duyck return (struct ethhdr *)(skb_transport_header(skb) + VXLAN_HLEN); 68576a540d4SAlexander Duyck } 68676a540d4SAlexander Duyck 68776a540d4SAlexander Duyck #define FM10K_NVGRE_RESERVED0_FLAGS htons(0x9FFF) 68876a540d4SAlexander Duyck #define NVGRE_TNI htons(0x2000) 68976a540d4SAlexander Duyck struct fm10k_nvgre_hdr { 69076a540d4SAlexander Duyck __be16 flags; 69176a540d4SAlexander Duyck __be16 proto; 69276a540d4SAlexander Duyck __be32 tni; 69376a540d4SAlexander Duyck }; 69476a540d4SAlexander Duyck 69576a540d4SAlexander Duyck static struct ethhdr *fm10k_gre_is_nvgre(struct sk_buff *skb) 69676a540d4SAlexander Duyck { 69776a540d4SAlexander Duyck struct fm10k_nvgre_hdr *nvgre_hdr; 69876a540d4SAlexander Duyck int hlen = ip_hdrlen(skb); 69976a540d4SAlexander Duyck 70076a540d4SAlexander Duyck /* currently only IPv4 is supported due to hlen above */ 70176a540d4SAlexander Duyck if (vlan_get_protocol(skb) != htons(ETH_P_IP)) 70276a540d4SAlexander Duyck return NULL; 70376a540d4SAlexander Duyck 70476a540d4SAlexander Duyck /* our transport header should be NVGRE */ 70576a540d4SAlexander Duyck nvgre_hdr = (struct fm10k_nvgre_hdr *)(skb_network_header(skb) + hlen); 70676a540d4SAlexander Duyck 70776a540d4SAlexander Duyck /* verify all reserved flags are 0 */ 70876a540d4SAlexander Duyck if (nvgre_hdr->flags & FM10K_NVGRE_RESERVED0_FLAGS) 70976a540d4SAlexander Duyck return NULL; 71076a540d4SAlexander Duyck 71176a540d4SAlexander Duyck /* report start of ethernet header */ 71276a540d4SAlexander Duyck if (nvgre_hdr->flags & NVGRE_TNI) 71376a540d4SAlexander Duyck return (struct ethhdr *)(nvgre_hdr + 1); 71476a540d4SAlexander Duyck 71576a540d4SAlexander Duyck return (struct ethhdr *)(&nvgre_hdr->tni); 71676a540d4SAlexander Duyck } 71776a540d4SAlexander Duyck 7185bf33dc6SMatthew Vick __be16 fm10k_tx_encap_offload(struct sk_buff *skb) 71976a540d4SAlexander Duyck { 7208c1a90aaSMatthew Vick u8 l4_hdr = 0, inner_l4_hdr = 0, inner_l4_hlen; 72176a540d4SAlexander Duyck struct ethhdr *eth_hdr; 72276a540d4SAlexander Duyck 7238c1a90aaSMatthew Vick if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 7248c1a90aaSMatthew Vick skb->inner_protocol != htons(ETH_P_TEB)) 725b66b6d9fSJoe Stringer return 0; 726b66b6d9fSJoe Stringer 72776a540d4SAlexander Duyck switch (vlan_get_protocol(skb)) { 72876a540d4SAlexander Duyck case htons(ETH_P_IP): 72976a540d4SAlexander Duyck l4_hdr = ip_hdr(skb)->protocol; 73076a540d4SAlexander Duyck break; 73176a540d4SAlexander Duyck case htons(ETH_P_IPV6): 73276a540d4SAlexander Duyck l4_hdr = ipv6_hdr(skb)->nexthdr; 73376a540d4SAlexander Duyck break; 73476a540d4SAlexander Duyck default: 73576a540d4SAlexander Duyck return 0; 73676a540d4SAlexander Duyck } 73776a540d4SAlexander Duyck 73876a540d4SAlexander Duyck switch (l4_hdr) { 73976a540d4SAlexander Duyck case IPPROTO_UDP: 74076a540d4SAlexander Duyck eth_hdr = fm10k_port_is_vxlan(skb); 74176a540d4SAlexander Duyck break; 74276a540d4SAlexander Duyck case IPPROTO_GRE: 74376a540d4SAlexander Duyck eth_hdr = fm10k_gre_is_nvgre(skb); 74476a540d4SAlexander Duyck break; 74576a540d4SAlexander Duyck default: 74676a540d4SAlexander Duyck return 0; 74776a540d4SAlexander Duyck } 74876a540d4SAlexander Duyck 74976a540d4SAlexander Duyck if (!eth_hdr) 75076a540d4SAlexander Duyck return 0; 75176a540d4SAlexander Duyck 75276a540d4SAlexander Duyck switch (eth_hdr->h_proto) { 75376a540d4SAlexander Duyck case htons(ETH_P_IP): 7548c1a90aaSMatthew Vick inner_l4_hdr = inner_ip_hdr(skb)->protocol; 7558c1a90aaSMatthew Vick break; 75676a540d4SAlexander Duyck case htons(ETH_P_IPV6): 7578c1a90aaSMatthew Vick inner_l4_hdr = inner_ipv6_hdr(skb)->nexthdr; 75876a540d4SAlexander Duyck break; 75976a540d4SAlexander Duyck default: 76076a540d4SAlexander Duyck return 0; 76176a540d4SAlexander Duyck } 76276a540d4SAlexander Duyck 7638c1a90aaSMatthew Vick switch (inner_l4_hdr) { 7648c1a90aaSMatthew Vick case IPPROTO_TCP: 7658c1a90aaSMatthew Vick inner_l4_hlen = inner_tcp_hdrlen(skb); 7668c1a90aaSMatthew Vick break; 7678c1a90aaSMatthew Vick case IPPROTO_UDP: 7688c1a90aaSMatthew Vick inner_l4_hlen = 8; 7698c1a90aaSMatthew Vick break; 7708c1a90aaSMatthew Vick default: 7718c1a90aaSMatthew Vick return 0; 7728c1a90aaSMatthew Vick } 7738c1a90aaSMatthew Vick 7748c1a90aaSMatthew Vick /* The hardware allows tunnel offloads only if the combined inner and 7758c1a90aaSMatthew Vick * outer header is 184 bytes or less 7768c1a90aaSMatthew Vick */ 7778c1a90aaSMatthew Vick if (skb_inner_transport_header(skb) + inner_l4_hlen - 7788c1a90aaSMatthew Vick skb_mac_header(skb) > FM10K_TUNNEL_HEADER_LENGTH) 7798c1a90aaSMatthew Vick return 0; 7808c1a90aaSMatthew Vick 78176a540d4SAlexander Duyck return eth_hdr->h_proto; 78276a540d4SAlexander Duyck } 78376a540d4SAlexander Duyck 78476a540d4SAlexander Duyck static int fm10k_tso(struct fm10k_ring *tx_ring, 78576a540d4SAlexander Duyck struct fm10k_tx_buffer *first) 78676a540d4SAlexander Duyck { 78776a540d4SAlexander Duyck struct sk_buff *skb = first->skb; 78876a540d4SAlexander Duyck struct fm10k_tx_desc *tx_desc; 78976a540d4SAlexander Duyck unsigned char *th; 79076a540d4SAlexander Duyck u8 hdrlen; 79176a540d4SAlexander Duyck 79276a540d4SAlexander Duyck if (skb->ip_summed != CHECKSUM_PARTIAL) 79376a540d4SAlexander Duyck return 0; 79476a540d4SAlexander Duyck 79576a540d4SAlexander Duyck if (!skb_is_gso(skb)) 79676a540d4SAlexander Duyck return 0; 79776a540d4SAlexander Duyck 79876a540d4SAlexander Duyck /* compute header lengths */ 79976a540d4SAlexander Duyck if (skb->encapsulation) { 80076a540d4SAlexander Duyck if (!fm10k_tx_encap_offload(skb)) 80176a540d4SAlexander Duyck goto err_vxlan; 80276a540d4SAlexander Duyck th = skb_inner_transport_header(skb); 80376a540d4SAlexander Duyck } else { 80476a540d4SAlexander Duyck th = skb_transport_header(skb); 80576a540d4SAlexander Duyck } 80676a540d4SAlexander Duyck 80776a540d4SAlexander Duyck /* compute offset from SOF to transport header and add header len */ 80876a540d4SAlexander Duyck hdrlen = (th - skb->data) + (((struct tcphdr *)th)->doff << 2); 80976a540d4SAlexander Duyck 81076a540d4SAlexander Duyck first->tx_flags |= FM10K_TX_FLAGS_CSUM; 81176a540d4SAlexander Duyck 81276a540d4SAlexander Duyck /* update gso size and bytecount with header size */ 81376a540d4SAlexander Duyck first->gso_segs = skb_shinfo(skb)->gso_segs; 81476a540d4SAlexander Duyck first->bytecount += (first->gso_segs - 1) * hdrlen; 81576a540d4SAlexander Duyck 81676a540d4SAlexander Duyck /* populate Tx descriptor header size and mss */ 81776a540d4SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); 81876a540d4SAlexander Duyck tx_desc->hdrlen = hdrlen; 81976a540d4SAlexander Duyck tx_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); 82076a540d4SAlexander Duyck 82176a540d4SAlexander Duyck return 1; 82276a540d4SAlexander Duyck err_vxlan: 82376a540d4SAlexander Duyck tx_ring->netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL; 82476a540d4SAlexander Duyck if (!net_ratelimit()) 82576a540d4SAlexander Duyck netdev_err(tx_ring->netdev, 82676a540d4SAlexander Duyck "TSO requested for unsupported tunnel, disabling offload\n"); 82776a540d4SAlexander Duyck return -1; 82876a540d4SAlexander Duyck } 82976a540d4SAlexander Duyck 83076a540d4SAlexander Duyck static void fm10k_tx_csum(struct fm10k_ring *tx_ring, 83176a540d4SAlexander Duyck struct fm10k_tx_buffer *first) 83276a540d4SAlexander Duyck { 83376a540d4SAlexander Duyck struct sk_buff *skb = first->skb; 83476a540d4SAlexander Duyck struct fm10k_tx_desc *tx_desc; 83576a540d4SAlexander Duyck union { 83676a540d4SAlexander Duyck struct iphdr *ipv4; 83776a540d4SAlexander Duyck struct ipv6hdr *ipv6; 83876a540d4SAlexander Duyck u8 *raw; 83976a540d4SAlexander Duyck } network_hdr; 84076a540d4SAlexander Duyck __be16 protocol; 84176a540d4SAlexander Duyck u8 l4_hdr = 0; 84276a540d4SAlexander Duyck 84376a540d4SAlexander Duyck if (skb->ip_summed != CHECKSUM_PARTIAL) 84476a540d4SAlexander Duyck goto no_csum; 84576a540d4SAlexander Duyck 84676a540d4SAlexander Duyck if (skb->encapsulation) { 84776a540d4SAlexander Duyck protocol = fm10k_tx_encap_offload(skb); 84876a540d4SAlexander Duyck if (!protocol) { 84976a540d4SAlexander Duyck if (skb_checksum_help(skb)) { 85076a540d4SAlexander Duyck dev_warn(tx_ring->dev, 85176a540d4SAlexander Duyck "failed to offload encap csum!\n"); 85276a540d4SAlexander Duyck tx_ring->tx_stats.csum_err++; 85376a540d4SAlexander Duyck } 85476a540d4SAlexander Duyck goto no_csum; 85576a540d4SAlexander Duyck } 85676a540d4SAlexander Duyck network_hdr.raw = skb_inner_network_header(skb); 85776a540d4SAlexander Duyck } else { 85876a540d4SAlexander Duyck protocol = vlan_get_protocol(skb); 85976a540d4SAlexander Duyck network_hdr.raw = skb_network_header(skb); 86076a540d4SAlexander Duyck } 86176a540d4SAlexander Duyck 86276a540d4SAlexander Duyck switch (protocol) { 86376a540d4SAlexander Duyck case htons(ETH_P_IP): 86476a540d4SAlexander Duyck l4_hdr = network_hdr.ipv4->protocol; 86576a540d4SAlexander Duyck break; 86676a540d4SAlexander Duyck case htons(ETH_P_IPV6): 86776a540d4SAlexander Duyck l4_hdr = network_hdr.ipv6->nexthdr; 86876a540d4SAlexander Duyck break; 86976a540d4SAlexander Duyck default: 87076a540d4SAlexander Duyck if (unlikely(net_ratelimit())) { 87176a540d4SAlexander Duyck dev_warn(tx_ring->dev, 87276a540d4SAlexander Duyck "partial checksum but ip version=%x!\n", 87376a540d4SAlexander Duyck protocol); 87476a540d4SAlexander Duyck } 87576a540d4SAlexander Duyck tx_ring->tx_stats.csum_err++; 87676a540d4SAlexander Duyck goto no_csum; 87776a540d4SAlexander Duyck } 87876a540d4SAlexander Duyck 87976a540d4SAlexander Duyck switch (l4_hdr) { 88076a540d4SAlexander Duyck case IPPROTO_TCP: 88176a540d4SAlexander Duyck case IPPROTO_UDP: 88276a540d4SAlexander Duyck break; 88376a540d4SAlexander Duyck case IPPROTO_GRE: 88476a540d4SAlexander Duyck if (skb->encapsulation) 88576a540d4SAlexander Duyck break; 88676a540d4SAlexander Duyck default: 88776a540d4SAlexander Duyck if (unlikely(net_ratelimit())) { 88876a540d4SAlexander Duyck dev_warn(tx_ring->dev, 88976a540d4SAlexander Duyck "partial checksum but l4 proto=%x!\n", 89076a540d4SAlexander Duyck l4_hdr); 89176a540d4SAlexander Duyck } 89276a540d4SAlexander Duyck tx_ring->tx_stats.csum_err++; 89376a540d4SAlexander Duyck goto no_csum; 89476a540d4SAlexander Duyck } 89576a540d4SAlexander Duyck 89676a540d4SAlexander Duyck /* update TX checksum flag */ 89776a540d4SAlexander Duyck first->tx_flags |= FM10K_TX_FLAGS_CSUM; 89880043f3bSJacob Keller tx_ring->tx_stats.csum_good++; 89976a540d4SAlexander Duyck 90076a540d4SAlexander Duyck no_csum: 90176a540d4SAlexander Duyck /* populate Tx descriptor header size and mss */ 90276a540d4SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); 90376a540d4SAlexander Duyck tx_desc->hdrlen = 0; 90476a540d4SAlexander Duyck tx_desc->mss = 0; 90576a540d4SAlexander Duyck } 90676a540d4SAlexander Duyck 90776a540d4SAlexander Duyck #define FM10K_SET_FLAG(_input, _flag, _result) \ 90876a540d4SAlexander Duyck ((_flag <= _result) ? \ 90976a540d4SAlexander Duyck ((u32)(_input & _flag) * (_result / _flag)) : \ 91076a540d4SAlexander Duyck ((u32)(_input & _flag) / (_flag / _result))) 91176a540d4SAlexander Duyck 91276a540d4SAlexander Duyck static u8 fm10k_tx_desc_flags(struct sk_buff *skb, u32 tx_flags) 91376a540d4SAlexander Duyck { 91476a540d4SAlexander Duyck /* set type for advanced descriptor with frame checksum insertion */ 91576a540d4SAlexander Duyck u32 desc_flags = 0; 91676a540d4SAlexander Duyck 917a211e013SAlexander Duyck /* set timestamping bits */ 918a211e013SAlexander Duyck if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 919a211e013SAlexander Duyck likely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 920a211e013SAlexander Duyck desc_flags |= FM10K_TXD_FLAG_TIME; 921a211e013SAlexander Duyck 92276a540d4SAlexander Duyck /* set checksum offload bits */ 92376a540d4SAlexander Duyck desc_flags |= FM10K_SET_FLAG(tx_flags, FM10K_TX_FLAGS_CSUM, 92476a540d4SAlexander Duyck FM10K_TXD_FLAG_CSUM); 92576a540d4SAlexander Duyck 92676a540d4SAlexander Duyck return desc_flags; 92776a540d4SAlexander Duyck } 92876a540d4SAlexander Duyck 929b101c962SAlexander Duyck static bool fm10k_tx_desc_push(struct fm10k_ring *tx_ring, 930b101c962SAlexander Duyck struct fm10k_tx_desc *tx_desc, u16 i, 931b101c962SAlexander Duyck dma_addr_t dma, unsigned int size, u8 desc_flags) 932b101c962SAlexander Duyck { 933b101c962SAlexander Duyck /* set RS and INT for last frame in a cache line */ 934b101c962SAlexander Duyck if ((++i & (FM10K_TXD_WB_FIFO_SIZE - 1)) == 0) 935b101c962SAlexander Duyck desc_flags |= FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_INT; 936b101c962SAlexander Duyck 937b101c962SAlexander Duyck /* record values to descriptor */ 938b101c962SAlexander Duyck tx_desc->buffer_addr = cpu_to_le64(dma); 939b101c962SAlexander Duyck tx_desc->flags = desc_flags; 940b101c962SAlexander Duyck tx_desc->buflen = cpu_to_le16(size); 941b101c962SAlexander Duyck 942b101c962SAlexander Duyck /* return true if we just wrapped the ring */ 943b101c962SAlexander Duyck return i == tx_ring->count; 944b101c962SAlexander Duyck } 945b101c962SAlexander Duyck 9462c2b2f0cSAlexander Duyck static int __fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) 9472c2b2f0cSAlexander Duyck { 9482c2b2f0cSAlexander Duyck netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 9492c2b2f0cSAlexander Duyck 950eca32047SMatthew Vick /* Memory barrier before checking head and tail */ 9512c2b2f0cSAlexander Duyck smp_mb(); 9522c2b2f0cSAlexander Duyck 953eca32047SMatthew Vick /* Check again in a case another CPU has just made room available */ 9542c2b2f0cSAlexander Duyck if (likely(fm10k_desc_unused(tx_ring) < size)) 9552c2b2f0cSAlexander Duyck return -EBUSY; 9562c2b2f0cSAlexander Duyck 9572c2b2f0cSAlexander Duyck /* A reprieve! - use start_queue because it doesn't call schedule */ 9582c2b2f0cSAlexander Duyck netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 9592c2b2f0cSAlexander Duyck ++tx_ring->tx_stats.restart_queue; 9602c2b2f0cSAlexander Duyck return 0; 9612c2b2f0cSAlexander Duyck } 9622c2b2f0cSAlexander Duyck 9632c2b2f0cSAlexander Duyck static inline int fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) 9642c2b2f0cSAlexander Duyck { 9652c2b2f0cSAlexander Duyck if (likely(fm10k_desc_unused(tx_ring) >= size)) 9662c2b2f0cSAlexander Duyck return 0; 9672c2b2f0cSAlexander Duyck return __fm10k_maybe_stop_tx(tx_ring, size); 9682c2b2f0cSAlexander Duyck } 9692c2b2f0cSAlexander Duyck 970b101c962SAlexander Duyck static void fm10k_tx_map(struct fm10k_ring *tx_ring, 971b101c962SAlexander Duyck struct fm10k_tx_buffer *first) 972b101c962SAlexander Duyck { 973b101c962SAlexander Duyck struct sk_buff *skb = first->skb; 974b101c962SAlexander Duyck struct fm10k_tx_buffer *tx_buffer; 975b101c962SAlexander Duyck struct fm10k_tx_desc *tx_desc; 976b101c962SAlexander Duyck struct skb_frag_struct *frag; 977b101c962SAlexander Duyck unsigned char *data; 978b101c962SAlexander Duyck dma_addr_t dma; 979b101c962SAlexander Duyck unsigned int data_len, size; 98076a540d4SAlexander Duyck u32 tx_flags = first->tx_flags; 981b101c962SAlexander Duyck u16 i = tx_ring->next_to_use; 98276a540d4SAlexander Duyck u8 flags = fm10k_tx_desc_flags(skb, tx_flags); 983b101c962SAlexander Duyck 984b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, i); 985b101c962SAlexander Duyck 986b101c962SAlexander Duyck /* add HW VLAN tag */ 987df8a39deSJiri Pirko if (skb_vlan_tag_present(skb)) 988df8a39deSJiri Pirko tx_desc->vlan = cpu_to_le16(skb_vlan_tag_get(skb)); 989b101c962SAlexander Duyck else 990b101c962SAlexander Duyck tx_desc->vlan = 0; 991b101c962SAlexander Duyck 992b101c962SAlexander Duyck size = skb_headlen(skb); 993b101c962SAlexander Duyck data = skb->data; 994b101c962SAlexander Duyck 995b101c962SAlexander Duyck dma = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); 996b101c962SAlexander Duyck 997b101c962SAlexander Duyck data_len = skb->data_len; 998b101c962SAlexander Duyck tx_buffer = first; 999b101c962SAlexander Duyck 1000b101c962SAlexander Duyck for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1001b101c962SAlexander Duyck if (dma_mapping_error(tx_ring->dev, dma)) 1002b101c962SAlexander Duyck goto dma_error; 1003b101c962SAlexander Duyck 1004b101c962SAlexander Duyck /* record length, and DMA address */ 1005b101c962SAlexander Duyck dma_unmap_len_set(tx_buffer, len, size); 1006b101c962SAlexander Duyck dma_unmap_addr_set(tx_buffer, dma, dma); 1007b101c962SAlexander Duyck 1008b101c962SAlexander Duyck while (unlikely(size > FM10K_MAX_DATA_PER_TXD)) { 1009b101c962SAlexander Duyck if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, dma, 1010b101c962SAlexander Duyck FM10K_MAX_DATA_PER_TXD, flags)) { 1011b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, 0); 1012b101c962SAlexander Duyck i = 0; 1013b101c962SAlexander Duyck } 1014b101c962SAlexander Duyck 1015b101c962SAlexander Duyck dma += FM10K_MAX_DATA_PER_TXD; 1016b101c962SAlexander Duyck size -= FM10K_MAX_DATA_PER_TXD; 1017b101c962SAlexander Duyck } 1018b101c962SAlexander Duyck 1019b101c962SAlexander Duyck if (likely(!data_len)) 1020b101c962SAlexander Duyck break; 1021b101c962SAlexander Duyck 1022b101c962SAlexander Duyck if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, 1023b101c962SAlexander Duyck dma, size, flags)) { 1024b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, 0); 1025b101c962SAlexander Duyck i = 0; 1026b101c962SAlexander Duyck } 1027b101c962SAlexander Duyck 1028b101c962SAlexander Duyck size = skb_frag_size(frag); 1029b101c962SAlexander Duyck data_len -= size; 1030b101c962SAlexander Duyck 1031b101c962SAlexander Duyck dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1032b101c962SAlexander Duyck DMA_TO_DEVICE); 1033b101c962SAlexander Duyck 1034b101c962SAlexander Duyck tx_buffer = &tx_ring->tx_buffer[i]; 1035b101c962SAlexander Duyck } 1036b101c962SAlexander Duyck 1037b101c962SAlexander Duyck /* write last descriptor with LAST bit set */ 1038b101c962SAlexander Duyck flags |= FM10K_TXD_FLAG_LAST; 1039b101c962SAlexander Duyck 1040b101c962SAlexander Duyck if (fm10k_tx_desc_push(tx_ring, tx_desc, i++, dma, size, flags)) 1041b101c962SAlexander Duyck i = 0; 1042b101c962SAlexander Duyck 1043b101c962SAlexander Duyck /* record bytecount for BQL */ 1044b101c962SAlexander Duyck netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 1045b101c962SAlexander Duyck 1046b101c962SAlexander Duyck /* record SW timestamp if HW timestamp is not available */ 1047b101c962SAlexander Duyck skb_tx_timestamp(first->skb); 1048b101c962SAlexander Duyck 1049b101c962SAlexander Duyck /* Force memory writes to complete before letting h/w know there 1050b101c962SAlexander Duyck * are new descriptors to fetch. (Only applicable for weak-ordered 1051b101c962SAlexander Duyck * memory model archs, such as IA-64). 1052b101c962SAlexander Duyck * 1053b101c962SAlexander Duyck * We also need this memory barrier to make certain all of the 1054b101c962SAlexander Duyck * status bits have been updated before next_to_watch is written. 1055b101c962SAlexander Duyck */ 1056b101c962SAlexander Duyck wmb(); 1057b101c962SAlexander Duyck 1058b101c962SAlexander Duyck /* set next_to_watch value indicating a packet is present */ 1059b101c962SAlexander Duyck first->next_to_watch = tx_desc; 1060b101c962SAlexander Duyck 1061b101c962SAlexander Duyck tx_ring->next_to_use = i; 1062b101c962SAlexander Duyck 10632c2b2f0cSAlexander Duyck /* Make sure there is space in the ring for the next send. */ 10642c2b2f0cSAlexander Duyck fm10k_maybe_stop_tx(tx_ring, DESC_NEEDED); 10652c2b2f0cSAlexander Duyck 1066b101c962SAlexander Duyck /* notify HW of packet */ 10672c2b2f0cSAlexander Duyck if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 1068b101c962SAlexander Duyck writel(i, tx_ring->tail); 1069b101c962SAlexander Duyck 1070b101c962SAlexander Duyck /* we need this if more than one processor can write to our tail 1071b101c962SAlexander Duyck * at a time, it synchronizes IO on IA64/Altix systems 1072b101c962SAlexander Duyck */ 1073b101c962SAlexander Duyck mmiowb(); 10742c2b2f0cSAlexander Duyck } 1075b101c962SAlexander Duyck 1076b101c962SAlexander Duyck return; 1077b101c962SAlexander Duyck dma_error: 1078b101c962SAlexander Duyck dev_err(tx_ring->dev, "TX DMA map failed\n"); 1079b101c962SAlexander Duyck 1080b101c962SAlexander Duyck /* clear dma mappings for failed tx_buffer map */ 1081b101c962SAlexander Duyck for (;;) { 1082b101c962SAlexander Duyck tx_buffer = &tx_ring->tx_buffer[i]; 1083b101c962SAlexander Duyck fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1084b101c962SAlexander Duyck if (tx_buffer == first) 1085b101c962SAlexander Duyck break; 1086b101c962SAlexander Duyck if (i == 0) 1087b101c962SAlexander Duyck i = tx_ring->count; 1088b101c962SAlexander Duyck i--; 1089b101c962SAlexander Duyck } 1090b101c962SAlexander Duyck 1091b101c962SAlexander Duyck tx_ring->next_to_use = i; 1092b101c962SAlexander Duyck } 1093b101c962SAlexander Duyck 1094b101c962SAlexander Duyck netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb, 1095b101c962SAlexander Duyck struct fm10k_ring *tx_ring) 1096b101c962SAlexander Duyck { 1097b101c962SAlexander Duyck u16 count = TXD_USE_COUNT(skb_headlen(skb)); 109803d13a51SJacob Keller struct fm10k_tx_buffer *first; 109903d13a51SJacob Keller unsigned short f; 110003d13a51SJacob Keller u32 tx_flags = 0; 110103d13a51SJacob Keller int tso; 1102b101c962SAlexander Duyck 1103b101c962SAlexander Duyck /* need: 1 descriptor per page * PAGE_SIZE/FM10K_MAX_DATA_PER_TXD, 1104b101c962SAlexander Duyck * + 1 desc for skb_headlen/FM10K_MAX_DATA_PER_TXD, 1105b101c962SAlexander Duyck * + 2 desc gap to keep tail from touching head 1106b101c962SAlexander Duyck * otherwise try next time 1107b101c962SAlexander Duyck */ 1108b101c962SAlexander Duyck for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1109b101c962SAlexander Duyck count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 1110aae072e3SAlexander Duyck 1111b101c962SAlexander Duyck if (fm10k_maybe_stop_tx(tx_ring, count + 3)) { 1112b101c962SAlexander Duyck tx_ring->tx_stats.tx_busy++; 1113b101c962SAlexander Duyck return NETDEV_TX_BUSY; 1114b101c962SAlexander Duyck } 1115b101c962SAlexander Duyck 1116b101c962SAlexander Duyck /* record the location of the first descriptor for this packet */ 1117b101c962SAlexander Duyck first = &tx_ring->tx_buffer[tx_ring->next_to_use]; 1118b101c962SAlexander Duyck first->skb = skb; 1119b101c962SAlexander Duyck first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN); 1120b101c962SAlexander Duyck first->gso_segs = 1; 1121b101c962SAlexander Duyck 1122b101c962SAlexander Duyck /* record initial flags and protocol */ 1123b101c962SAlexander Duyck first->tx_flags = tx_flags; 1124b101c962SAlexander Duyck 112576a540d4SAlexander Duyck tso = fm10k_tso(tx_ring, first); 112676a540d4SAlexander Duyck if (tso < 0) 112776a540d4SAlexander Duyck goto out_drop; 112876a540d4SAlexander Duyck else if (!tso) 112976a540d4SAlexander Duyck fm10k_tx_csum(tx_ring, first); 113076a540d4SAlexander Duyck 1131b101c962SAlexander Duyck fm10k_tx_map(tx_ring, first); 1132b101c962SAlexander Duyck 1133b101c962SAlexander Duyck return NETDEV_TX_OK; 113476a540d4SAlexander Duyck 113576a540d4SAlexander Duyck out_drop: 113676a540d4SAlexander Duyck dev_kfree_skb_any(first->skb); 113776a540d4SAlexander Duyck first->skb = NULL; 113876a540d4SAlexander Duyck 113976a540d4SAlexander Duyck return NETDEV_TX_OK; 1140b101c962SAlexander Duyck } 1141b101c962SAlexander Duyck 1142b101c962SAlexander Duyck static u64 fm10k_get_tx_completed(struct fm10k_ring *ring) 1143b101c962SAlexander Duyck { 1144b101c962SAlexander Duyck return ring->stats.packets; 1145b101c962SAlexander Duyck } 1146b101c962SAlexander Duyck 1147b101c962SAlexander Duyck static u64 fm10k_get_tx_pending(struct fm10k_ring *ring) 1148b101c962SAlexander Duyck { 1149b101c962SAlexander Duyck /* use SW head and tail until we have real hardware */ 1150b101c962SAlexander Duyck u32 head = ring->next_to_clean; 1151b101c962SAlexander Duyck u32 tail = ring->next_to_use; 1152b101c962SAlexander Duyck 1153b101c962SAlexander Duyck return ((head <= tail) ? tail : tail + ring->count) - head; 1154b101c962SAlexander Duyck } 1155b101c962SAlexander Duyck 1156b101c962SAlexander Duyck bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring) 1157b101c962SAlexander Duyck { 1158b101c962SAlexander Duyck u32 tx_done = fm10k_get_tx_completed(tx_ring); 1159b101c962SAlexander Duyck u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1160b101c962SAlexander Duyck u32 tx_pending = fm10k_get_tx_pending(tx_ring); 1161b101c962SAlexander Duyck 1162b101c962SAlexander Duyck clear_check_for_tx_hang(tx_ring); 1163b101c962SAlexander Duyck 1164b101c962SAlexander Duyck /* Check for a hung queue, but be thorough. This verifies 1165b101c962SAlexander Duyck * that a transmit has been completed since the previous 1166b101c962SAlexander Duyck * check AND there is at least one packet pending. By 1167b101c962SAlexander Duyck * requiring this to fail twice we avoid races with 1168b101c962SAlexander Duyck * clearing the ARMED bit and conditions where we 1169b101c962SAlexander Duyck * run the check_tx_hang logic with a transmit completion 1170b101c962SAlexander Duyck * pending but without time to complete it yet. 1171b101c962SAlexander Duyck */ 1172b101c962SAlexander Duyck if (!tx_pending || (tx_done_old != tx_done)) { 1173b101c962SAlexander Duyck /* update completed stats and continue */ 1174b101c962SAlexander Duyck tx_ring->tx_stats.tx_done_old = tx_done; 1175b101c962SAlexander Duyck /* reset the countdown */ 1176b101c962SAlexander Duyck clear_bit(__FM10K_HANG_CHECK_ARMED, &tx_ring->state); 1177b101c962SAlexander Duyck 1178b101c962SAlexander Duyck return false; 1179b101c962SAlexander Duyck } 1180b101c962SAlexander Duyck 1181b101c962SAlexander Duyck /* make sure it is true for two checks in a row */ 1182b101c962SAlexander Duyck return test_and_set_bit(__FM10K_HANG_CHECK_ARMED, &tx_ring->state); 1183b101c962SAlexander Duyck } 1184b101c962SAlexander Duyck 1185b101c962SAlexander Duyck /** 1186b101c962SAlexander Duyck * fm10k_tx_timeout_reset - initiate reset due to Tx timeout 1187b101c962SAlexander Duyck * @interface: driver private struct 1188b101c962SAlexander Duyck **/ 1189b101c962SAlexander Duyck void fm10k_tx_timeout_reset(struct fm10k_intfc *interface) 1190b101c962SAlexander Duyck { 1191b101c962SAlexander Duyck /* Do the reset outside of interrupt context */ 1192b101c962SAlexander Duyck if (!test_bit(__FM10K_DOWN, &interface->state)) { 1193b101c962SAlexander Duyck interface->tx_timeout_count++; 1194b101c962SAlexander Duyck interface->flags |= FM10K_FLAG_RESET_REQUESTED; 1195b101c962SAlexander Duyck fm10k_service_event_schedule(interface); 1196b101c962SAlexander Duyck } 1197b101c962SAlexander Duyck } 1198b101c962SAlexander Duyck 1199b101c962SAlexander Duyck /** 1200b101c962SAlexander Duyck * fm10k_clean_tx_irq - Reclaim resources after transmit completes 1201b101c962SAlexander Duyck * @q_vector: structure containing interrupt and ring information 1202b101c962SAlexander Duyck * @tx_ring: tx ring to clean 1203b101c962SAlexander Duyck **/ 1204b101c962SAlexander Duyck static bool fm10k_clean_tx_irq(struct fm10k_q_vector *q_vector, 1205b101c962SAlexander Duyck struct fm10k_ring *tx_ring) 1206b101c962SAlexander Duyck { 1207b101c962SAlexander Duyck struct fm10k_intfc *interface = q_vector->interface; 1208b101c962SAlexander Duyck struct fm10k_tx_buffer *tx_buffer; 1209b101c962SAlexander Duyck struct fm10k_tx_desc *tx_desc; 1210b101c962SAlexander Duyck unsigned int total_bytes = 0, total_packets = 0; 1211b101c962SAlexander Duyck unsigned int budget = q_vector->tx.work_limit; 1212b101c962SAlexander Duyck unsigned int i = tx_ring->next_to_clean; 1213b101c962SAlexander Duyck 1214b101c962SAlexander Duyck if (test_bit(__FM10K_DOWN, &interface->state)) 1215b101c962SAlexander Duyck return true; 1216b101c962SAlexander Duyck 1217b101c962SAlexander Duyck tx_buffer = &tx_ring->tx_buffer[i]; 1218b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, i); 1219b101c962SAlexander Duyck i -= tx_ring->count; 1220b101c962SAlexander Duyck 1221b101c962SAlexander Duyck do { 1222b101c962SAlexander Duyck struct fm10k_tx_desc *eop_desc = tx_buffer->next_to_watch; 1223b101c962SAlexander Duyck 1224b101c962SAlexander Duyck /* if next_to_watch is not set then there is no work pending */ 1225b101c962SAlexander Duyck if (!eop_desc) 1226b101c962SAlexander Duyck break; 1227b101c962SAlexander Duyck 1228b101c962SAlexander Duyck /* prevent any other reads prior to eop_desc */ 1229b101c962SAlexander Duyck read_barrier_depends(); 1230b101c962SAlexander Duyck 1231b101c962SAlexander Duyck /* if DD is not set pending work has not been completed */ 1232b101c962SAlexander Duyck if (!(eop_desc->flags & FM10K_TXD_FLAG_DONE)) 1233b101c962SAlexander Duyck break; 1234b101c962SAlexander Duyck 1235b101c962SAlexander Duyck /* clear next_to_watch to prevent false hangs */ 1236b101c962SAlexander Duyck tx_buffer->next_to_watch = NULL; 1237b101c962SAlexander Duyck 1238b101c962SAlexander Duyck /* update the statistics for this packet */ 1239b101c962SAlexander Duyck total_bytes += tx_buffer->bytecount; 1240b101c962SAlexander Duyck total_packets += tx_buffer->gso_segs; 1241b101c962SAlexander Duyck 1242b101c962SAlexander Duyck /* free the skb */ 1243b101c962SAlexander Duyck dev_consume_skb_any(tx_buffer->skb); 1244b101c962SAlexander Duyck 1245b101c962SAlexander Duyck /* unmap skb header data */ 1246b101c962SAlexander Duyck dma_unmap_single(tx_ring->dev, 1247b101c962SAlexander Duyck dma_unmap_addr(tx_buffer, dma), 1248b101c962SAlexander Duyck dma_unmap_len(tx_buffer, len), 1249b101c962SAlexander Duyck DMA_TO_DEVICE); 1250b101c962SAlexander Duyck 1251b101c962SAlexander Duyck /* clear tx_buffer data */ 1252b101c962SAlexander Duyck tx_buffer->skb = NULL; 1253b101c962SAlexander Duyck dma_unmap_len_set(tx_buffer, len, 0); 1254b101c962SAlexander Duyck 1255b101c962SAlexander Duyck /* unmap remaining buffers */ 1256b101c962SAlexander Duyck while (tx_desc != eop_desc) { 1257b101c962SAlexander Duyck tx_buffer++; 1258b101c962SAlexander Duyck tx_desc++; 1259b101c962SAlexander Duyck i++; 1260b101c962SAlexander Duyck if (unlikely(!i)) { 1261b101c962SAlexander Duyck i -= tx_ring->count; 1262b101c962SAlexander Duyck tx_buffer = tx_ring->tx_buffer; 1263b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, 0); 1264b101c962SAlexander Duyck } 1265b101c962SAlexander Duyck 1266b101c962SAlexander Duyck /* unmap any remaining paged data */ 1267b101c962SAlexander Duyck if (dma_unmap_len(tx_buffer, len)) { 1268b101c962SAlexander Duyck dma_unmap_page(tx_ring->dev, 1269b101c962SAlexander Duyck dma_unmap_addr(tx_buffer, dma), 1270b101c962SAlexander Duyck dma_unmap_len(tx_buffer, len), 1271b101c962SAlexander Duyck DMA_TO_DEVICE); 1272b101c962SAlexander Duyck dma_unmap_len_set(tx_buffer, len, 0); 1273b101c962SAlexander Duyck } 1274b101c962SAlexander Duyck } 1275b101c962SAlexander Duyck 1276b101c962SAlexander Duyck /* move us one more past the eop_desc for start of next pkt */ 1277b101c962SAlexander Duyck tx_buffer++; 1278b101c962SAlexander Duyck tx_desc++; 1279b101c962SAlexander Duyck i++; 1280b101c962SAlexander Duyck if (unlikely(!i)) { 1281b101c962SAlexander Duyck i -= tx_ring->count; 1282b101c962SAlexander Duyck tx_buffer = tx_ring->tx_buffer; 1283b101c962SAlexander Duyck tx_desc = FM10K_TX_DESC(tx_ring, 0); 1284b101c962SAlexander Duyck } 1285b101c962SAlexander Duyck 1286b101c962SAlexander Duyck /* issue prefetch for next Tx descriptor */ 1287b101c962SAlexander Duyck prefetch(tx_desc); 1288b101c962SAlexander Duyck 1289b101c962SAlexander Duyck /* update budget accounting */ 1290b101c962SAlexander Duyck budget--; 1291b101c962SAlexander Duyck } while (likely(budget)); 1292b101c962SAlexander Duyck 1293b101c962SAlexander Duyck i += tx_ring->count; 1294b101c962SAlexander Duyck tx_ring->next_to_clean = i; 1295b101c962SAlexander Duyck u64_stats_update_begin(&tx_ring->syncp); 1296b101c962SAlexander Duyck tx_ring->stats.bytes += total_bytes; 1297b101c962SAlexander Duyck tx_ring->stats.packets += total_packets; 1298b101c962SAlexander Duyck u64_stats_update_end(&tx_ring->syncp); 1299b101c962SAlexander Duyck q_vector->tx.total_bytes += total_bytes; 1300b101c962SAlexander Duyck q_vector->tx.total_packets += total_packets; 1301b101c962SAlexander Duyck 1302b101c962SAlexander Duyck if (check_for_tx_hang(tx_ring) && fm10k_check_tx_hang(tx_ring)) { 1303b101c962SAlexander Duyck /* schedule immediate reset if we believe we hung */ 1304b101c962SAlexander Duyck struct fm10k_hw *hw = &interface->hw; 1305b101c962SAlexander Duyck 1306b101c962SAlexander Duyck netif_err(interface, drv, tx_ring->netdev, 1307b101c962SAlexander Duyck "Detected Tx Unit Hang\n" 1308b101c962SAlexander Duyck " Tx Queue <%d>\n" 1309b101c962SAlexander Duyck " TDH, TDT <%x>, <%x>\n" 1310b101c962SAlexander Duyck " next_to_use <%x>\n" 1311b101c962SAlexander Duyck " next_to_clean <%x>\n", 1312b101c962SAlexander Duyck tx_ring->queue_index, 1313b101c962SAlexander Duyck fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)), 1314b101c962SAlexander Duyck fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)), 1315b101c962SAlexander Duyck tx_ring->next_to_use, i); 1316b101c962SAlexander Duyck 1317b101c962SAlexander Duyck netif_stop_subqueue(tx_ring->netdev, 1318b101c962SAlexander Duyck tx_ring->queue_index); 1319b101c962SAlexander Duyck 1320b101c962SAlexander Duyck netif_info(interface, probe, tx_ring->netdev, 1321b101c962SAlexander Duyck "tx hang %d detected on queue %d, resetting interface\n", 1322b101c962SAlexander Duyck interface->tx_timeout_count + 1, 1323b101c962SAlexander Duyck tx_ring->queue_index); 1324b101c962SAlexander Duyck 1325b101c962SAlexander Duyck fm10k_tx_timeout_reset(interface); 1326b101c962SAlexander Duyck 1327b101c962SAlexander Duyck /* the netdev is about to reset, no point in enabling stuff */ 1328b101c962SAlexander Duyck return true; 1329b101c962SAlexander Duyck } 1330b101c962SAlexander Duyck 1331b101c962SAlexander Duyck /* notify netdev of completed buffers */ 1332b101c962SAlexander Duyck netdev_tx_completed_queue(txring_txq(tx_ring), 1333b101c962SAlexander Duyck total_packets, total_bytes); 1334b101c962SAlexander Duyck 1335b101c962SAlexander Duyck #define TX_WAKE_THRESHOLD min_t(u16, FM10K_MIN_TXD - 1, DESC_NEEDED * 2) 1336b101c962SAlexander Duyck if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1337b101c962SAlexander Duyck (fm10k_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1338b101c962SAlexander Duyck /* Make sure that anybody stopping the queue after this 1339b101c962SAlexander Duyck * sees the new next_to_clean. 1340b101c962SAlexander Duyck */ 1341b101c962SAlexander Duyck smp_mb(); 1342b101c962SAlexander Duyck if (__netif_subqueue_stopped(tx_ring->netdev, 1343b101c962SAlexander Duyck tx_ring->queue_index) && 1344b101c962SAlexander Duyck !test_bit(__FM10K_DOWN, &interface->state)) { 1345b101c962SAlexander Duyck netif_wake_subqueue(tx_ring->netdev, 1346b101c962SAlexander Duyck tx_ring->queue_index); 1347b101c962SAlexander Duyck ++tx_ring->tx_stats.restart_queue; 1348b101c962SAlexander Duyck } 1349b101c962SAlexander Duyck } 1350b101c962SAlexander Duyck 1351b101c962SAlexander Duyck return !!budget; 1352b101c962SAlexander Duyck } 1353b101c962SAlexander Duyck 135418283cadSAlexander Duyck /** 135518283cadSAlexander Duyck * fm10k_update_itr - update the dynamic ITR value based on packet size 135618283cadSAlexander Duyck * 135718283cadSAlexander Duyck * Stores a new ITR value based on strictly on packet size. The 135818283cadSAlexander Duyck * divisors and thresholds used by this function were determined based 135918283cadSAlexander Duyck * on theoretical maximum wire speed and testing data, in order to 136018283cadSAlexander Duyck * minimize response time while increasing bulk throughput. 136118283cadSAlexander Duyck * 136218283cadSAlexander Duyck * @ring_container: Container for rings to have ITR updated 136318283cadSAlexander Duyck **/ 136418283cadSAlexander Duyck static void fm10k_update_itr(struct fm10k_ring_container *ring_container) 136518283cadSAlexander Duyck { 1366242722ddSJacob Keller unsigned int avg_wire_size, packets, itr_round; 136718283cadSAlexander Duyck 136818283cadSAlexander Duyck /* Only update ITR if we are using adaptive setting */ 1369584373f5SJacob Keller if (!ITR_IS_ADAPTIVE(ring_container->itr)) 137018283cadSAlexander Duyck goto clear_counts; 137118283cadSAlexander Duyck 137218283cadSAlexander Duyck packets = ring_container->total_packets; 137318283cadSAlexander Duyck if (!packets) 137418283cadSAlexander Duyck goto clear_counts; 137518283cadSAlexander Duyck 137618283cadSAlexander Duyck avg_wire_size = ring_container->total_bytes / packets; 137718283cadSAlexander Duyck 1378242722ddSJacob Keller /* The following is a crude approximation of: 1379242722ddSJacob Keller * wmem_default / (size + overhead) = desired_pkts_per_int 1380242722ddSJacob Keller * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 1381242722ddSJacob Keller * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 1382242722ddSJacob Keller * 1383242722ddSJacob Keller * Assuming wmem_default is 212992 and overhead is 640 bytes per 1384242722ddSJacob Keller * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 1385242722ddSJacob Keller * formula down to 1386242722ddSJacob Keller * 1387242722ddSJacob Keller * (34 * (size + 24)) / (size + 640) = ITR 1388242722ddSJacob Keller * 1389242722ddSJacob Keller * We first do some math on the packet size and then finally bitshift 1390242722ddSJacob Keller * by 8 after rounding up. We also have to account for PCIe link speed 1391242722ddSJacob Keller * difference as ITR scales based on this. 1392242722ddSJacob Keller */ 1393242722ddSJacob Keller if (avg_wire_size <= 360) { 1394242722ddSJacob Keller /* Start at 250K ints/sec and gradually drop to 77K ints/sec */ 1395242722ddSJacob Keller avg_wire_size *= 8; 1396242722ddSJacob Keller avg_wire_size += 376; 1397242722ddSJacob Keller } else if (avg_wire_size <= 1152) { 1398242722ddSJacob Keller /* 77K ints/sec to 45K ints/sec */ 1399242722ddSJacob Keller avg_wire_size *= 3; 1400242722ddSJacob Keller avg_wire_size += 2176; 1401242722ddSJacob Keller } else if (avg_wire_size <= 1920) { 1402242722ddSJacob Keller /* 45K ints/sec to 38K ints/sec */ 1403242722ddSJacob Keller avg_wire_size += 4480; 1404242722ddSJacob Keller } else { 1405242722ddSJacob Keller /* plateau at a limit of 38K ints/sec */ 1406242722ddSJacob Keller avg_wire_size = 6656; 1407242722ddSJacob Keller } 140818283cadSAlexander Duyck 1409242722ddSJacob Keller /* Perform final bitshift for division after rounding up to ensure 1410242722ddSJacob Keller * that the calculation will never get below a 1. The bit shift 1411242722ddSJacob Keller * accounts for changes in the ITR due to PCIe link speed. 1412242722ddSJacob Keller */ 1413242722ddSJacob Keller itr_round = ACCESS_ONCE(ring_container->itr_scale) + 8; 1414242722ddSJacob Keller avg_wire_size += (1 << itr_round) - 1; 1415242722ddSJacob Keller avg_wire_size >>= itr_round; 141618283cadSAlexander Duyck 141718283cadSAlexander Duyck /* write back value and retain adaptive flag */ 141818283cadSAlexander Duyck ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE; 141918283cadSAlexander Duyck 142018283cadSAlexander Duyck clear_counts: 142118283cadSAlexander Duyck ring_container->total_bytes = 0; 142218283cadSAlexander Duyck ring_container->total_packets = 0; 142318283cadSAlexander Duyck } 142418283cadSAlexander Duyck 142518283cadSAlexander Duyck static void fm10k_qv_enable(struct fm10k_q_vector *q_vector) 142618283cadSAlexander Duyck { 142718283cadSAlexander Duyck /* Enable auto-mask and clear the current mask */ 142818283cadSAlexander Duyck u32 itr = FM10K_ITR_ENABLE; 142918283cadSAlexander Duyck 143018283cadSAlexander Duyck /* Update Tx ITR */ 143118283cadSAlexander Duyck fm10k_update_itr(&q_vector->tx); 143218283cadSAlexander Duyck 143318283cadSAlexander Duyck /* Update Rx ITR */ 143418283cadSAlexander Duyck fm10k_update_itr(&q_vector->rx); 143518283cadSAlexander Duyck 143618283cadSAlexander Duyck /* Store Tx itr in timer slot 0 */ 143718283cadSAlexander Duyck itr |= (q_vector->tx.itr & FM10K_ITR_MAX); 143818283cadSAlexander Duyck 143918283cadSAlexander Duyck /* Shift Rx itr to timer slot 1 */ 144018283cadSAlexander Duyck itr |= (q_vector->rx.itr & FM10K_ITR_MAX) << FM10K_ITR_INTERVAL1_SHIFT; 144118283cadSAlexander Duyck 144218283cadSAlexander Duyck /* Write the final value to the ITR register */ 144318283cadSAlexander Duyck writel(itr, q_vector->itr); 144418283cadSAlexander Duyck } 144518283cadSAlexander Duyck 144618283cadSAlexander Duyck static int fm10k_poll(struct napi_struct *napi, int budget) 144718283cadSAlexander Duyck { 144818283cadSAlexander Duyck struct fm10k_q_vector *q_vector = 144918283cadSAlexander Duyck container_of(napi, struct fm10k_q_vector, napi); 1450b101c962SAlexander Duyck struct fm10k_ring *ring; 145132b3e08fSJesse Brandeburg int per_ring_budget, work_done = 0; 1452b101c962SAlexander Duyck bool clean_complete = true; 1453b101c962SAlexander Duyck 1454b101c962SAlexander Duyck fm10k_for_each_ring(ring, q_vector->tx) 1455b101c962SAlexander Duyck clean_complete &= fm10k_clean_tx_irq(q_vector, ring); 1456b101c962SAlexander Duyck 14579f872986SAlexander Duyck /* Handle case where we are called by netpoll with a budget of 0 */ 14589f872986SAlexander Duyck if (budget <= 0) 14599f872986SAlexander Duyck return budget; 14609f872986SAlexander Duyck 1461b101c962SAlexander Duyck /* attempt to distribute budget to each queue fairly, but don't 1462b101c962SAlexander Duyck * allow the budget to go below 1 because we'll exit polling 1463b101c962SAlexander Duyck */ 1464b101c962SAlexander Duyck if (q_vector->rx.count > 1) 1465b101c962SAlexander Duyck per_ring_budget = max(budget/q_vector->rx.count, 1); 1466b101c962SAlexander Duyck else 1467b101c962SAlexander Duyck per_ring_budget = budget; 1468b101c962SAlexander Duyck 146932b3e08fSJesse Brandeburg fm10k_for_each_ring(ring, q_vector->rx) { 147032b3e08fSJesse Brandeburg int work = fm10k_clean_rx_irq(q_vector, ring, per_ring_budget); 147132b3e08fSJesse Brandeburg 147232b3e08fSJesse Brandeburg work_done += work; 147332b3e08fSJesse Brandeburg clean_complete &= !!(work < per_ring_budget); 147432b3e08fSJesse Brandeburg } 1475b101c962SAlexander Duyck 1476b101c962SAlexander Duyck /* If all work not completed, return budget and keep polling */ 1477b101c962SAlexander Duyck if (!clean_complete) 1478b101c962SAlexander Duyck return budget; 147918283cadSAlexander Duyck 148018283cadSAlexander Duyck /* all work done, exit the polling mode */ 148132b3e08fSJesse Brandeburg napi_complete_done(napi, work_done); 148218283cadSAlexander Duyck 148318283cadSAlexander Duyck /* re-enable the q_vector */ 148418283cadSAlexander Duyck fm10k_qv_enable(q_vector); 148518283cadSAlexander Duyck 148618283cadSAlexander Duyck return 0; 148718283cadSAlexander Duyck } 148818283cadSAlexander Duyck 148918283cadSAlexander Duyck /** 1490aa3ac822SAlexander Duyck * fm10k_set_qos_queues: Allocate queues for a QOS-enabled device 1491aa3ac822SAlexander Duyck * @interface: board private structure to initialize 1492aa3ac822SAlexander Duyck * 1493aa3ac822SAlexander Duyck * When QoS (Quality of Service) is enabled, allocate queues for 1494aa3ac822SAlexander Duyck * each traffic class. If multiqueue isn't available,then abort QoS 1495aa3ac822SAlexander Duyck * initialization. 1496aa3ac822SAlexander Duyck * 1497aa3ac822SAlexander Duyck * This function handles all combinations of Qos and RSS. 1498aa3ac822SAlexander Duyck * 1499aa3ac822SAlexander Duyck **/ 1500aa3ac822SAlexander Duyck static bool fm10k_set_qos_queues(struct fm10k_intfc *interface) 1501aa3ac822SAlexander Duyck { 1502aa3ac822SAlexander Duyck struct net_device *dev = interface->netdev; 1503aa3ac822SAlexander Duyck struct fm10k_ring_feature *f; 1504aa3ac822SAlexander Duyck int rss_i, i; 1505aa3ac822SAlexander Duyck int pcs; 1506aa3ac822SAlexander Duyck 1507aa3ac822SAlexander Duyck /* Map queue offset and counts onto allocated tx queues */ 1508aa3ac822SAlexander Duyck pcs = netdev_get_num_tc(dev); 1509aa3ac822SAlexander Duyck 1510aa3ac822SAlexander Duyck if (pcs <= 1) 1511aa3ac822SAlexander Duyck return false; 1512aa3ac822SAlexander Duyck 1513aa3ac822SAlexander Duyck /* set QoS mask and indices */ 1514aa3ac822SAlexander Duyck f = &interface->ring_feature[RING_F_QOS]; 1515aa3ac822SAlexander Duyck f->indices = pcs; 1516aa3ac822SAlexander Duyck f->mask = (1 << fls(pcs - 1)) - 1; 1517aa3ac822SAlexander Duyck 1518aa3ac822SAlexander Duyck /* determine the upper limit for our current DCB mode */ 1519aa3ac822SAlexander Duyck rss_i = interface->hw.mac.max_queues / pcs; 1520aa3ac822SAlexander Duyck rss_i = 1 << (fls(rss_i) - 1); 1521aa3ac822SAlexander Duyck 1522aa3ac822SAlexander Duyck /* set RSS mask and indices */ 1523aa3ac822SAlexander Duyck f = &interface->ring_feature[RING_F_RSS]; 1524aa3ac822SAlexander Duyck rss_i = min_t(u16, rss_i, f->limit); 1525aa3ac822SAlexander Duyck f->indices = rss_i; 1526aa3ac822SAlexander Duyck f->mask = (1 << fls(rss_i - 1)) - 1; 1527aa3ac822SAlexander Duyck 1528aa3ac822SAlexander Duyck /* configure pause class to queue mapping */ 1529aa3ac822SAlexander Duyck for (i = 0; i < pcs; i++) 1530aa3ac822SAlexander Duyck netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 1531aa3ac822SAlexander Duyck 1532aa3ac822SAlexander Duyck interface->num_rx_queues = rss_i * pcs; 1533aa3ac822SAlexander Duyck interface->num_tx_queues = rss_i * pcs; 1534aa3ac822SAlexander Duyck 1535aa3ac822SAlexander Duyck return true; 1536aa3ac822SAlexander Duyck } 1537aa3ac822SAlexander Duyck 1538aa3ac822SAlexander Duyck /** 1539aa3ac822SAlexander Duyck * fm10k_set_rss_queues: Allocate queues for RSS 1540aa3ac822SAlexander Duyck * @interface: board private structure to initialize 1541aa3ac822SAlexander Duyck * 1542aa3ac822SAlexander Duyck * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1543aa3ac822SAlexander Duyck * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1544aa3ac822SAlexander Duyck * 1545aa3ac822SAlexander Duyck **/ 1546aa3ac822SAlexander Duyck static bool fm10k_set_rss_queues(struct fm10k_intfc *interface) 1547aa3ac822SAlexander Duyck { 1548aa3ac822SAlexander Duyck struct fm10k_ring_feature *f; 1549aa3ac822SAlexander Duyck u16 rss_i; 1550aa3ac822SAlexander Duyck 1551aa3ac822SAlexander Duyck f = &interface->ring_feature[RING_F_RSS]; 1552aa3ac822SAlexander Duyck rss_i = min_t(u16, interface->hw.mac.max_queues, f->limit); 1553aa3ac822SAlexander Duyck 1554aa3ac822SAlexander Duyck /* record indices and power of 2 mask for RSS */ 1555aa3ac822SAlexander Duyck f->indices = rss_i; 1556aa3ac822SAlexander Duyck f->mask = (1 << fls(rss_i - 1)) - 1; 1557aa3ac822SAlexander Duyck 1558aa3ac822SAlexander Duyck interface->num_rx_queues = rss_i; 1559aa3ac822SAlexander Duyck interface->num_tx_queues = rss_i; 1560aa3ac822SAlexander Duyck 1561aa3ac822SAlexander Duyck return true; 1562aa3ac822SAlexander Duyck } 1563aa3ac822SAlexander Duyck 1564aa3ac822SAlexander Duyck /** 156518283cadSAlexander Duyck * fm10k_set_num_queues: Allocate queues for device, feature dependent 156618283cadSAlexander Duyck * @interface: board private structure to initialize 156718283cadSAlexander Duyck * 156818283cadSAlexander Duyck * This is the top level queue allocation routine. The order here is very 156918283cadSAlexander Duyck * important, starting with the "most" number of features turned on at once, 157018283cadSAlexander Duyck * and ending with the smallest set of features. This way large combinations 157118283cadSAlexander Duyck * can be allocated if they're turned on, and smaller combinations are the 157218283cadSAlexander Duyck * fallthrough conditions. 157318283cadSAlexander Duyck * 157418283cadSAlexander Duyck **/ 157518283cadSAlexander Duyck static void fm10k_set_num_queues(struct fm10k_intfc *interface) 157618283cadSAlexander Duyck { 157718283cadSAlexander Duyck /* Start with base case */ 157818283cadSAlexander Duyck interface->num_rx_queues = 1; 157918283cadSAlexander Duyck interface->num_tx_queues = 1; 1580aa3ac822SAlexander Duyck 1581aa3ac822SAlexander Duyck if (fm10k_set_qos_queues(interface)) 1582aa3ac822SAlexander Duyck return; 1583aa3ac822SAlexander Duyck 1584aa3ac822SAlexander Duyck fm10k_set_rss_queues(interface); 158518283cadSAlexander Duyck } 158618283cadSAlexander Duyck 158718283cadSAlexander Duyck /** 158818283cadSAlexander Duyck * fm10k_alloc_q_vector - Allocate memory for a single interrupt vector 158918283cadSAlexander Duyck * @interface: board private structure to initialize 159018283cadSAlexander Duyck * @v_count: q_vectors allocated on interface, used for ring interleaving 159118283cadSAlexander Duyck * @v_idx: index of vector in interface struct 159218283cadSAlexander Duyck * @txr_count: total number of Tx rings to allocate 159318283cadSAlexander Duyck * @txr_idx: index of first Tx ring to allocate 159418283cadSAlexander Duyck * @rxr_count: total number of Rx rings to allocate 159518283cadSAlexander Duyck * @rxr_idx: index of first Rx ring to allocate 159618283cadSAlexander Duyck * 159718283cadSAlexander Duyck * We allocate one q_vector. If allocation fails we return -ENOMEM. 159818283cadSAlexander Duyck **/ 159918283cadSAlexander Duyck static int fm10k_alloc_q_vector(struct fm10k_intfc *interface, 160018283cadSAlexander Duyck unsigned int v_count, unsigned int v_idx, 160118283cadSAlexander Duyck unsigned int txr_count, unsigned int txr_idx, 160218283cadSAlexander Duyck unsigned int rxr_count, unsigned int rxr_idx) 160318283cadSAlexander Duyck { 160418283cadSAlexander Duyck struct fm10k_q_vector *q_vector; 1605e27ef599SAlexander Duyck struct fm10k_ring *ring; 160618283cadSAlexander Duyck int ring_count, size; 160718283cadSAlexander Duyck 160818283cadSAlexander Duyck ring_count = txr_count + rxr_count; 1609e27ef599SAlexander Duyck size = sizeof(struct fm10k_q_vector) + 1610e27ef599SAlexander Duyck (sizeof(struct fm10k_ring) * ring_count); 161118283cadSAlexander Duyck 161218283cadSAlexander Duyck /* allocate q_vector and rings */ 161318283cadSAlexander Duyck q_vector = kzalloc(size, GFP_KERNEL); 161418283cadSAlexander Duyck if (!q_vector) 161518283cadSAlexander Duyck return -ENOMEM; 161618283cadSAlexander Duyck 161718283cadSAlexander Duyck /* initialize NAPI */ 161818283cadSAlexander Duyck netif_napi_add(interface->netdev, &q_vector->napi, 161918283cadSAlexander Duyck fm10k_poll, NAPI_POLL_WEIGHT); 162018283cadSAlexander Duyck 162118283cadSAlexander Duyck /* tie q_vector and interface together */ 162218283cadSAlexander Duyck interface->q_vector[v_idx] = q_vector; 162318283cadSAlexander Duyck q_vector->interface = interface; 162418283cadSAlexander Duyck q_vector->v_idx = v_idx; 162518283cadSAlexander Duyck 1626e27ef599SAlexander Duyck /* initialize pointer to rings */ 1627e27ef599SAlexander Duyck ring = q_vector->ring; 1628e27ef599SAlexander Duyck 162918283cadSAlexander Duyck /* save Tx ring container info */ 1630e27ef599SAlexander Duyck q_vector->tx.ring = ring; 1631e27ef599SAlexander Duyck q_vector->tx.work_limit = FM10K_DEFAULT_TX_WORK; 163218283cadSAlexander Duyck q_vector->tx.itr = interface->tx_itr; 1633242722ddSJacob Keller q_vector->tx.itr_scale = interface->hw.mac.itr_scale; 163418283cadSAlexander Duyck q_vector->tx.count = txr_count; 163518283cadSAlexander Duyck 1636e27ef599SAlexander Duyck while (txr_count) { 1637e27ef599SAlexander Duyck /* assign generic ring traits */ 1638e27ef599SAlexander Duyck ring->dev = &interface->pdev->dev; 1639e27ef599SAlexander Duyck ring->netdev = interface->netdev; 1640e27ef599SAlexander Duyck 1641e27ef599SAlexander Duyck /* configure backlink on ring */ 1642e27ef599SAlexander Duyck ring->q_vector = q_vector; 1643e27ef599SAlexander Duyck 1644e27ef599SAlexander Duyck /* apply Tx specific ring traits */ 1645e27ef599SAlexander Duyck ring->count = interface->tx_ring_count; 1646e27ef599SAlexander Duyck ring->queue_index = txr_idx; 1647e27ef599SAlexander Duyck 1648e27ef599SAlexander Duyck /* assign ring to interface */ 1649e27ef599SAlexander Duyck interface->tx_ring[txr_idx] = ring; 1650e27ef599SAlexander Duyck 1651e27ef599SAlexander Duyck /* update count and index */ 1652e27ef599SAlexander Duyck txr_count--; 1653e27ef599SAlexander Duyck txr_idx += v_count; 1654e27ef599SAlexander Duyck 1655e27ef599SAlexander Duyck /* push pointer to next ring */ 1656e27ef599SAlexander Duyck ring++; 1657e27ef599SAlexander Duyck } 1658e27ef599SAlexander Duyck 165918283cadSAlexander Duyck /* save Rx ring container info */ 1660e27ef599SAlexander Duyck q_vector->rx.ring = ring; 166118283cadSAlexander Duyck q_vector->rx.itr = interface->rx_itr; 1662242722ddSJacob Keller q_vector->rx.itr_scale = interface->hw.mac.itr_scale; 166318283cadSAlexander Duyck q_vector->rx.count = rxr_count; 166418283cadSAlexander Duyck 1665e27ef599SAlexander Duyck while (rxr_count) { 1666e27ef599SAlexander Duyck /* assign generic ring traits */ 1667e27ef599SAlexander Duyck ring->dev = &interface->pdev->dev; 1668e27ef599SAlexander Duyck ring->netdev = interface->netdev; 16695cd5e2e9SAlexander Duyck rcu_assign_pointer(ring->l2_accel, interface->l2_accel); 1670e27ef599SAlexander Duyck 1671e27ef599SAlexander Duyck /* configure backlink on ring */ 1672e27ef599SAlexander Duyck ring->q_vector = q_vector; 1673e27ef599SAlexander Duyck 1674e27ef599SAlexander Duyck /* apply Rx specific ring traits */ 1675e27ef599SAlexander Duyck ring->count = interface->rx_ring_count; 1676e27ef599SAlexander Duyck ring->queue_index = rxr_idx; 1677e27ef599SAlexander Duyck 1678e27ef599SAlexander Duyck /* assign ring to interface */ 1679e27ef599SAlexander Duyck interface->rx_ring[rxr_idx] = ring; 1680e27ef599SAlexander Duyck 1681e27ef599SAlexander Duyck /* update count and index */ 1682e27ef599SAlexander Duyck rxr_count--; 1683e27ef599SAlexander Duyck rxr_idx += v_count; 1684e27ef599SAlexander Duyck 1685e27ef599SAlexander Duyck /* push pointer to next ring */ 1686e27ef599SAlexander Duyck ring++; 1687e27ef599SAlexander Duyck } 1688e27ef599SAlexander Duyck 16897461fd91SAlexander Duyck fm10k_dbg_q_vector_init(q_vector); 16907461fd91SAlexander Duyck 169118283cadSAlexander Duyck return 0; 169218283cadSAlexander Duyck } 169318283cadSAlexander Duyck 169418283cadSAlexander Duyck /** 169518283cadSAlexander Duyck * fm10k_free_q_vector - Free memory allocated for specific interrupt vector 169618283cadSAlexander Duyck * @interface: board private structure to initialize 169718283cadSAlexander Duyck * @v_idx: Index of vector to be freed 169818283cadSAlexander Duyck * 169918283cadSAlexander Duyck * This function frees the memory allocated to the q_vector. In addition if 170018283cadSAlexander Duyck * NAPI is enabled it will delete any references to the NAPI struct prior 170118283cadSAlexander Duyck * to freeing the q_vector. 170218283cadSAlexander Duyck **/ 170318283cadSAlexander Duyck static void fm10k_free_q_vector(struct fm10k_intfc *interface, int v_idx) 170418283cadSAlexander Duyck { 170518283cadSAlexander Duyck struct fm10k_q_vector *q_vector = interface->q_vector[v_idx]; 1706e27ef599SAlexander Duyck struct fm10k_ring *ring; 1707e27ef599SAlexander Duyck 17087461fd91SAlexander Duyck fm10k_dbg_q_vector_exit(q_vector); 17097461fd91SAlexander Duyck 1710e27ef599SAlexander Duyck fm10k_for_each_ring(ring, q_vector->tx) 1711e27ef599SAlexander Duyck interface->tx_ring[ring->queue_index] = NULL; 1712e27ef599SAlexander Duyck 1713e27ef599SAlexander Duyck fm10k_for_each_ring(ring, q_vector->rx) 1714e27ef599SAlexander Duyck interface->rx_ring[ring->queue_index] = NULL; 171518283cadSAlexander Duyck 171618283cadSAlexander Duyck interface->q_vector[v_idx] = NULL; 171718283cadSAlexander Duyck netif_napi_del(&q_vector->napi); 171818283cadSAlexander Duyck kfree_rcu(q_vector, rcu); 171918283cadSAlexander Duyck } 172018283cadSAlexander Duyck 172118283cadSAlexander Duyck /** 172218283cadSAlexander Duyck * fm10k_alloc_q_vectors - Allocate memory for interrupt vectors 172318283cadSAlexander Duyck * @interface: board private structure to initialize 172418283cadSAlexander Duyck * 172518283cadSAlexander Duyck * We allocate one q_vector per queue interrupt. If allocation fails we 172618283cadSAlexander Duyck * return -ENOMEM. 172718283cadSAlexander Duyck **/ 172818283cadSAlexander Duyck static int fm10k_alloc_q_vectors(struct fm10k_intfc *interface) 172918283cadSAlexander Duyck { 173018283cadSAlexander Duyck unsigned int q_vectors = interface->num_q_vectors; 173118283cadSAlexander Duyck unsigned int rxr_remaining = interface->num_rx_queues; 173218283cadSAlexander Duyck unsigned int txr_remaining = interface->num_tx_queues; 173318283cadSAlexander Duyck unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 173418283cadSAlexander Duyck int err; 173518283cadSAlexander Duyck 173618283cadSAlexander Duyck if (q_vectors >= (rxr_remaining + txr_remaining)) { 173718283cadSAlexander Duyck for (; rxr_remaining; v_idx++) { 173818283cadSAlexander Duyck err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, 173918283cadSAlexander Duyck 0, 0, 1, rxr_idx); 174018283cadSAlexander Duyck if (err) 174118283cadSAlexander Duyck goto err_out; 174218283cadSAlexander Duyck 174318283cadSAlexander Duyck /* update counts and index */ 174418283cadSAlexander Duyck rxr_remaining--; 174518283cadSAlexander Duyck rxr_idx++; 174618283cadSAlexander Duyck } 174718283cadSAlexander Duyck } 174818283cadSAlexander Duyck 174918283cadSAlexander Duyck for (; v_idx < q_vectors; v_idx++) { 175018283cadSAlexander Duyck int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 175118283cadSAlexander Duyck int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 175218283cadSAlexander Duyck 175318283cadSAlexander Duyck err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, 175418283cadSAlexander Duyck tqpv, txr_idx, 175518283cadSAlexander Duyck rqpv, rxr_idx); 175618283cadSAlexander Duyck 175718283cadSAlexander Duyck if (err) 175818283cadSAlexander Duyck goto err_out; 175918283cadSAlexander Duyck 176018283cadSAlexander Duyck /* update counts and index */ 176118283cadSAlexander Duyck rxr_remaining -= rqpv; 176218283cadSAlexander Duyck txr_remaining -= tqpv; 176318283cadSAlexander Duyck rxr_idx++; 176418283cadSAlexander Duyck txr_idx++; 176518283cadSAlexander Duyck } 176618283cadSAlexander Duyck 176718283cadSAlexander Duyck return 0; 176818283cadSAlexander Duyck 176918283cadSAlexander Duyck err_out: 177018283cadSAlexander Duyck interface->num_tx_queues = 0; 177118283cadSAlexander Duyck interface->num_rx_queues = 0; 177218283cadSAlexander Duyck interface->num_q_vectors = 0; 177318283cadSAlexander Duyck 177418283cadSAlexander Duyck while (v_idx--) 177518283cadSAlexander Duyck fm10k_free_q_vector(interface, v_idx); 177618283cadSAlexander Duyck 177718283cadSAlexander Duyck return -ENOMEM; 177818283cadSAlexander Duyck } 177918283cadSAlexander Duyck 178018283cadSAlexander Duyck /** 178118283cadSAlexander Duyck * fm10k_free_q_vectors - Free memory allocated for interrupt vectors 178218283cadSAlexander Duyck * @interface: board private structure to initialize 178318283cadSAlexander Duyck * 178418283cadSAlexander Duyck * This function frees the memory allocated to the q_vectors. In addition if 178518283cadSAlexander Duyck * NAPI is enabled it will delete any references to the NAPI struct prior 178618283cadSAlexander Duyck * to freeing the q_vector. 178718283cadSAlexander Duyck **/ 178818283cadSAlexander Duyck static void fm10k_free_q_vectors(struct fm10k_intfc *interface) 178918283cadSAlexander Duyck { 179018283cadSAlexander Duyck int v_idx = interface->num_q_vectors; 179118283cadSAlexander Duyck 179218283cadSAlexander Duyck interface->num_tx_queues = 0; 179318283cadSAlexander Duyck interface->num_rx_queues = 0; 179418283cadSAlexander Duyck interface->num_q_vectors = 0; 179518283cadSAlexander Duyck 179618283cadSAlexander Duyck while (v_idx--) 179718283cadSAlexander Duyck fm10k_free_q_vector(interface, v_idx); 179818283cadSAlexander Duyck } 179918283cadSAlexander Duyck 180018283cadSAlexander Duyck /** 180118283cadSAlexander Duyck * f10k_reset_msix_capability - reset MSI-X capability 180218283cadSAlexander Duyck * @interface: board private structure to initialize 180318283cadSAlexander Duyck * 180418283cadSAlexander Duyck * Reset the MSI-X capability back to its starting state 180518283cadSAlexander Duyck **/ 180618283cadSAlexander Duyck static void fm10k_reset_msix_capability(struct fm10k_intfc *interface) 180718283cadSAlexander Duyck { 180818283cadSAlexander Duyck pci_disable_msix(interface->pdev); 180918283cadSAlexander Duyck kfree(interface->msix_entries); 181018283cadSAlexander Duyck interface->msix_entries = NULL; 181118283cadSAlexander Duyck } 181218283cadSAlexander Duyck 181318283cadSAlexander Duyck /** 181418283cadSAlexander Duyck * f10k_init_msix_capability - configure MSI-X capability 181518283cadSAlexander Duyck * @interface: board private structure to initialize 181618283cadSAlexander Duyck * 181718283cadSAlexander Duyck * Attempt to configure the interrupts using the best available 181818283cadSAlexander Duyck * capabilities of the hardware and the kernel. 181918283cadSAlexander Duyck **/ 182018283cadSAlexander Duyck static int fm10k_init_msix_capability(struct fm10k_intfc *interface) 182118283cadSAlexander Duyck { 182218283cadSAlexander Duyck struct fm10k_hw *hw = &interface->hw; 182318283cadSAlexander Duyck int v_budget, vector; 182418283cadSAlexander Duyck 182518283cadSAlexander Duyck /* It's easy to be greedy for MSI-X vectors, but it really 182618283cadSAlexander Duyck * doesn't do us much good if we have a lot more vectors 182718283cadSAlexander Duyck * than CPU's. So let's be conservative and only ask for 182818283cadSAlexander Duyck * (roughly) the same number of vectors as there are CPU's. 182918283cadSAlexander Duyck * the default is to use pairs of vectors 183018283cadSAlexander Duyck */ 183118283cadSAlexander Duyck v_budget = max(interface->num_rx_queues, interface->num_tx_queues); 183218283cadSAlexander Duyck v_budget = min_t(u16, v_budget, num_online_cpus()); 183318283cadSAlexander Duyck 183418283cadSAlexander Duyck /* account for vectors not related to queues */ 183518283cadSAlexander Duyck v_budget += NON_Q_VECTORS(hw); 183618283cadSAlexander Duyck 183718283cadSAlexander Duyck /* At the same time, hardware can only support a maximum of 183818283cadSAlexander Duyck * hw.mac->max_msix_vectors vectors. With features 183918283cadSAlexander Duyck * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 184018283cadSAlexander Duyck * descriptor queues supported by our device. Thus, we cap it off in 184118283cadSAlexander Duyck * those rare cases where the cpu count also exceeds our vector limit. 184218283cadSAlexander Duyck */ 184318283cadSAlexander Duyck v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 184418283cadSAlexander Duyck 184518283cadSAlexander Duyck /* A failure in MSI-X entry allocation is fatal. */ 184618283cadSAlexander Duyck interface->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), 184718283cadSAlexander Duyck GFP_KERNEL); 184818283cadSAlexander Duyck if (!interface->msix_entries) 184918283cadSAlexander Duyck return -ENOMEM; 185018283cadSAlexander Duyck 185118283cadSAlexander Duyck /* populate entry values */ 185218283cadSAlexander Duyck for (vector = 0; vector < v_budget; vector++) 185318283cadSAlexander Duyck interface->msix_entries[vector].entry = vector; 185418283cadSAlexander Duyck 185518283cadSAlexander Duyck /* Attempt to enable MSI-X with requested value */ 185618283cadSAlexander Duyck v_budget = pci_enable_msix_range(interface->pdev, 185718283cadSAlexander Duyck interface->msix_entries, 185818283cadSAlexander Duyck MIN_MSIX_COUNT(hw), 185918283cadSAlexander Duyck v_budget); 186018283cadSAlexander Duyck if (v_budget < 0) { 186118283cadSAlexander Duyck kfree(interface->msix_entries); 186218283cadSAlexander Duyck interface->msix_entries = NULL; 186318283cadSAlexander Duyck return -ENOMEM; 186418283cadSAlexander Duyck } 186518283cadSAlexander Duyck 186618283cadSAlexander Duyck /* record the number of queues available for q_vectors */ 186718283cadSAlexander Duyck interface->num_q_vectors = v_budget - NON_Q_VECTORS(hw); 186818283cadSAlexander Duyck 186918283cadSAlexander Duyck return 0; 187018283cadSAlexander Duyck } 187118283cadSAlexander Duyck 1872aa3ac822SAlexander Duyck /** 1873aa3ac822SAlexander Duyck * fm10k_cache_ring_qos - Descriptor ring to register mapping for QoS 1874aa3ac822SAlexander Duyck * @interface: Interface structure continaining rings and devices 1875aa3ac822SAlexander Duyck * 1876aa3ac822SAlexander Duyck * Cache the descriptor ring offsets for Qos 1877aa3ac822SAlexander Duyck **/ 1878aa3ac822SAlexander Duyck static bool fm10k_cache_ring_qos(struct fm10k_intfc *interface) 1879aa3ac822SAlexander Duyck { 1880aa3ac822SAlexander Duyck struct net_device *dev = interface->netdev; 1881aa3ac822SAlexander Duyck int pc, offset, rss_i, i, q_idx; 1882aa3ac822SAlexander Duyck u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1; 1883aa3ac822SAlexander Duyck u8 num_pcs = netdev_get_num_tc(dev); 1884aa3ac822SAlexander Duyck 1885aa3ac822SAlexander Duyck if (num_pcs <= 1) 1886aa3ac822SAlexander Duyck return false; 1887aa3ac822SAlexander Duyck 1888aa3ac822SAlexander Duyck rss_i = interface->ring_feature[RING_F_RSS].indices; 1889aa3ac822SAlexander Duyck 1890aa3ac822SAlexander Duyck for (pc = 0, offset = 0; pc < num_pcs; pc++, offset += rss_i) { 1891aa3ac822SAlexander Duyck q_idx = pc; 1892aa3ac822SAlexander Duyck for (i = 0; i < rss_i; i++) { 1893aa3ac822SAlexander Duyck interface->tx_ring[offset + i]->reg_idx = q_idx; 1894aa3ac822SAlexander Duyck interface->tx_ring[offset + i]->qos_pc = pc; 1895aa3ac822SAlexander Duyck interface->rx_ring[offset + i]->reg_idx = q_idx; 1896aa3ac822SAlexander Duyck interface->rx_ring[offset + i]->qos_pc = pc; 1897aa3ac822SAlexander Duyck q_idx += pc_stride; 1898aa3ac822SAlexander Duyck } 1899aa3ac822SAlexander Duyck } 1900aa3ac822SAlexander Duyck 1901aa3ac822SAlexander Duyck return true; 1902aa3ac822SAlexander Duyck } 1903aa3ac822SAlexander Duyck 1904aa3ac822SAlexander Duyck /** 1905aa3ac822SAlexander Duyck * fm10k_cache_ring_rss - Descriptor ring to register mapping for RSS 1906aa3ac822SAlexander Duyck * @interface: Interface structure continaining rings and devices 1907aa3ac822SAlexander Duyck * 1908aa3ac822SAlexander Duyck * Cache the descriptor ring offsets for RSS 1909aa3ac822SAlexander Duyck **/ 1910aa3ac822SAlexander Duyck static void fm10k_cache_ring_rss(struct fm10k_intfc *interface) 1911aa3ac822SAlexander Duyck { 1912aa3ac822SAlexander Duyck int i; 1913aa3ac822SAlexander Duyck 1914aa3ac822SAlexander Duyck for (i = 0; i < interface->num_rx_queues; i++) 1915aa3ac822SAlexander Duyck interface->rx_ring[i]->reg_idx = i; 1916aa3ac822SAlexander Duyck 1917aa3ac822SAlexander Duyck for (i = 0; i < interface->num_tx_queues; i++) 1918aa3ac822SAlexander Duyck interface->tx_ring[i]->reg_idx = i; 1919aa3ac822SAlexander Duyck } 1920aa3ac822SAlexander Duyck 1921aa3ac822SAlexander Duyck /** 1922aa3ac822SAlexander Duyck * fm10k_assign_rings - Map rings to network devices 1923aa3ac822SAlexander Duyck * @interface: Interface structure containing rings and devices 1924aa3ac822SAlexander Duyck * 1925aa3ac822SAlexander Duyck * This function is meant to go though and configure both the network 1926aa3ac822SAlexander Duyck * devices so that they contain rings, and configure the rings so that 1927aa3ac822SAlexander Duyck * they function with their network devices. 1928aa3ac822SAlexander Duyck **/ 1929aa3ac822SAlexander Duyck static void fm10k_assign_rings(struct fm10k_intfc *interface) 1930aa3ac822SAlexander Duyck { 1931aa3ac822SAlexander Duyck if (fm10k_cache_ring_qos(interface)) 1932aa3ac822SAlexander Duyck return; 1933aa3ac822SAlexander Duyck 1934aa3ac822SAlexander Duyck fm10k_cache_ring_rss(interface); 1935aa3ac822SAlexander Duyck } 1936aa3ac822SAlexander Duyck 193718283cadSAlexander Duyck static void fm10k_init_reta(struct fm10k_intfc *interface) 193818283cadSAlexander Duyck { 193918283cadSAlexander Duyck u16 i, rss_i = interface->ring_feature[RING_F_RSS].indices; 194018283cadSAlexander Duyck u32 reta, base; 194118283cadSAlexander Duyck 194218283cadSAlexander Duyck /* If the netdev is initialized we have to maintain table if possible */ 1943b4a5127bSJacob Keller if (interface->netdev->reg_state != NETREG_UNINITIALIZED) { 194418283cadSAlexander Duyck for (i = FM10K_RETA_SIZE; i--;) { 194518283cadSAlexander Duyck reta = interface->reta[i]; 194618283cadSAlexander Duyck if ((((reta << 24) >> 24) < rss_i) && 194718283cadSAlexander Duyck (((reta << 16) >> 24) < rss_i) && 194818283cadSAlexander Duyck (((reta << 8) >> 24) < rss_i) && 194918283cadSAlexander Duyck (((reta) >> 24) < rss_i)) 195018283cadSAlexander Duyck continue; 195118283cadSAlexander Duyck goto repopulate_reta; 195218283cadSAlexander Duyck } 195318283cadSAlexander Duyck 195418283cadSAlexander Duyck /* do nothing if all of the elements are in bounds */ 195518283cadSAlexander Duyck return; 195618283cadSAlexander Duyck } 195718283cadSAlexander Duyck 195818283cadSAlexander Duyck repopulate_reta: 195918283cadSAlexander Duyck /* Populate the redirection table 4 entries at a time. To do this 196018283cadSAlexander Duyck * we are generating the results for n and n+2 and then interleaving 196118283cadSAlexander Duyck * those with the results with n+1 and n+3. 196218283cadSAlexander Duyck */ 196318283cadSAlexander Duyck for (i = FM10K_RETA_SIZE; i--;) { 196418283cadSAlexander Duyck /* first pass generates n and n+2 */ 196518283cadSAlexander Duyck base = ((i * 0x00040004) + 0x00020000) * rss_i; 196618283cadSAlexander Duyck reta = (base & 0x3F803F80) >> 7; 196718283cadSAlexander Duyck 196818283cadSAlexander Duyck /* second pass generates n+1 and n+3 */ 196918283cadSAlexander Duyck base += 0x00010001 * rss_i; 197018283cadSAlexander Duyck reta |= (base & 0x3F803F80) << 1; 197118283cadSAlexander Duyck 197218283cadSAlexander Duyck interface->reta[i] = reta; 197318283cadSAlexander Duyck } 197418283cadSAlexander Duyck } 197518283cadSAlexander Duyck 197618283cadSAlexander Duyck /** 197718283cadSAlexander Duyck * fm10k_init_queueing_scheme - Determine proper queueing scheme 197818283cadSAlexander Duyck * @interface: board private structure to initialize 197918283cadSAlexander Duyck * 198018283cadSAlexander Duyck * We determine which queueing scheme to use based on... 198118283cadSAlexander Duyck * - Hardware queue count (num_*_queues) 198218283cadSAlexander Duyck * - defined by miscellaneous hardware support/features (RSS, etc.) 198318283cadSAlexander Duyck **/ 198418283cadSAlexander Duyck int fm10k_init_queueing_scheme(struct fm10k_intfc *interface) 198518283cadSAlexander Duyck { 198618283cadSAlexander Duyck int err; 198718283cadSAlexander Duyck 198818283cadSAlexander Duyck /* Number of supported queues */ 198918283cadSAlexander Duyck fm10k_set_num_queues(interface); 199018283cadSAlexander Duyck 199118283cadSAlexander Duyck /* Configure MSI-X capability */ 199218283cadSAlexander Duyck err = fm10k_init_msix_capability(interface); 199318283cadSAlexander Duyck if (err) { 199418283cadSAlexander Duyck dev_err(&interface->pdev->dev, 199518283cadSAlexander Duyck "Unable to initialize MSI-X capability\n"); 199618283cadSAlexander Duyck return err; 199718283cadSAlexander Duyck } 199818283cadSAlexander Duyck 199918283cadSAlexander Duyck /* Allocate memory for queues */ 200018283cadSAlexander Duyck err = fm10k_alloc_q_vectors(interface); 200118283cadSAlexander Duyck if (err) 200218283cadSAlexander Duyck return err; 200318283cadSAlexander Duyck 2004aa3ac822SAlexander Duyck /* Map rings to devices, and map devices to physical queues */ 2005aa3ac822SAlexander Duyck fm10k_assign_rings(interface); 2006aa3ac822SAlexander Duyck 200718283cadSAlexander Duyck /* Initialize RSS redirection table */ 200818283cadSAlexander Duyck fm10k_init_reta(interface); 200918283cadSAlexander Duyck 201018283cadSAlexander Duyck return 0; 201118283cadSAlexander Duyck } 201218283cadSAlexander Duyck 201318283cadSAlexander Duyck /** 201418283cadSAlexander Duyck * fm10k_clear_queueing_scheme - Clear the current queueing scheme settings 201518283cadSAlexander Duyck * @interface: board private structure to clear queueing scheme on 201618283cadSAlexander Duyck * 201718283cadSAlexander Duyck * We go through and clear queueing specific resources and reset the structure 201818283cadSAlexander Duyck * to pre-load conditions 201918283cadSAlexander Duyck **/ 202018283cadSAlexander Duyck void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface) 202118283cadSAlexander Duyck { 202218283cadSAlexander Duyck fm10k_free_q_vectors(interface); 202318283cadSAlexander Duyck fm10k_reset_msix_capability(interface); 202418283cadSAlexander Duyck } 2025