1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/delay.h> 30 31 #include "e1000.h" 32 33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 36 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 ARRAY_SIZE(e1000_m88_cable_length_table) 49 50 static const u16 e1000_igp_2_cable_length_table[] = { 51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 58 124}; 59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 60 ARRAY_SIZE(e1000_igp_2_cable_length_table) 61 62 #define BM_PHY_REG_PAGE(offset) \ 63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 64 #define BM_PHY_REG_NUM(offset) \ 65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 67 ~MAX_PHY_REG_ADDRESS))) 68 69 #define HV_INTC_FC_PAGE_START 768 70 #define I82578_ADDR_REG 29 71 #define I82577_ADDR_REG 16 72 #define I82577_CFG_REG 22 73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 75 #define I82577_CTRL_REG 23 76 77 /* 82577 specific PHY registers */ 78 #define I82577_PHY_CTRL_2 18 79 #define I82577_PHY_STATUS_2 26 80 #define I82577_PHY_DIAG_STATUS 31 81 82 /* I82577 PHY Status 2 */ 83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 84 #define I82577_PHY_STATUS2_MDIX 0x0800 85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 87 88 /* I82577 PHY Control 2 */ 89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 91 92 /* I82577 PHY Diagnostics Status */ 93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 95 96 /* BM PHY Copper Specific Control 1 */ 97 #define BM_CS_CTRL1 16 98 99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 102 103 /** 104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 105 * @hw: pointer to the HW structure 106 * 107 * Read the PHY management control register and check whether a PHY reset 108 * is blocked. If a reset is not blocked return 0, otherwise 109 * return E1000_BLK_PHY_RESET (12). 110 **/ 111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) 112 { 113 u32 manc; 114 115 manc = er32(MANC); 116 117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 118 E1000_BLK_PHY_RESET : 0; 119 } 120 121 /** 122 * e1000e_get_phy_id - Retrieve the PHY ID and revision 123 * @hw: pointer to the HW structure 124 * 125 * Reads the PHY registers and stores the PHY ID and possibly the PHY 126 * revision in the hardware structure. 127 **/ 128 s32 e1000e_get_phy_id(struct e1000_hw *hw) 129 { 130 struct e1000_phy_info *phy = &hw->phy; 131 s32 ret_val = 0; 132 u16 phy_id; 133 u16 retry_count = 0; 134 135 if (!(phy->ops.read_reg)) 136 goto out; 137 138 while (retry_count < 2) { 139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 140 if (ret_val) 141 goto out; 142 143 phy->id = (u32)(phy_id << 16); 144 udelay(20); 145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 146 if (ret_val) 147 goto out; 148 149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 151 152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 153 goto out; 154 155 retry_count++; 156 } 157 out: 158 return ret_val; 159 } 160 161 /** 162 * e1000e_phy_reset_dsp - Reset PHY DSP 163 * @hw: pointer to the HW structure 164 * 165 * Reset the digital signal processor. 166 **/ 167 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) 168 { 169 s32 ret_val; 170 171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 172 if (ret_val) 173 return ret_val; 174 175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 176 } 177 178 /** 179 * e1000e_read_phy_reg_mdic - Read MDI control register 180 * @hw: pointer to the HW structure 181 * @offset: register offset to be read 182 * @data: pointer to the read data 183 * 184 * Reads the MDI control register in the PHY at offset and stores the 185 * information read to data. 186 **/ 187 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 188 { 189 struct e1000_phy_info *phy = &hw->phy; 190 u32 i, mdic = 0; 191 192 if (offset > MAX_PHY_REG_ADDRESS) { 193 e_dbg("PHY Address %d is out of range\n", offset); 194 return -E1000_ERR_PARAM; 195 } 196 197 /* 198 * Set up Op-code, Phy Address, and register offset in the MDI 199 * Control register. The MAC will take care of interfacing with the 200 * PHY to retrieve the desired data. 201 */ 202 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 203 (phy->addr << E1000_MDIC_PHY_SHIFT) | 204 (E1000_MDIC_OP_READ)); 205 206 ew32(MDIC, mdic); 207 208 /* 209 * Poll the ready bit to see if the MDI read completed 210 * Increasing the time out as testing showed failures with 211 * the lower time out 212 */ 213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 214 udelay(50); 215 mdic = er32(MDIC); 216 if (mdic & E1000_MDIC_READY) 217 break; 218 } 219 if (!(mdic & E1000_MDIC_READY)) { 220 e_dbg("MDI Read did not complete\n"); 221 return -E1000_ERR_PHY; 222 } 223 if (mdic & E1000_MDIC_ERROR) { 224 e_dbg("MDI Error\n"); 225 return -E1000_ERR_PHY; 226 } 227 *data = (u16) mdic; 228 229 /* 230 * Allow some time after each MDIC transaction to avoid 231 * reading duplicate data in the next MDIC transaction. 232 */ 233 if (hw->mac.type == e1000_pch2lan) 234 udelay(100); 235 236 return 0; 237 } 238 239 /** 240 * e1000e_write_phy_reg_mdic - Write MDI control register 241 * @hw: pointer to the HW structure 242 * @offset: register offset to write to 243 * @data: data to write to register at offset 244 * 245 * Writes data to MDI control register in the PHY at offset. 246 **/ 247 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 248 { 249 struct e1000_phy_info *phy = &hw->phy; 250 u32 i, mdic = 0; 251 252 if (offset > MAX_PHY_REG_ADDRESS) { 253 e_dbg("PHY Address %d is out of range\n", offset); 254 return -E1000_ERR_PARAM; 255 } 256 257 /* 258 * Set up Op-code, Phy Address, and register offset in the MDI 259 * Control register. The MAC will take care of interfacing with the 260 * PHY to retrieve the desired data. 261 */ 262 mdic = (((u32)data) | 263 (offset << E1000_MDIC_REG_SHIFT) | 264 (phy->addr << E1000_MDIC_PHY_SHIFT) | 265 (E1000_MDIC_OP_WRITE)); 266 267 ew32(MDIC, mdic); 268 269 /* 270 * Poll the ready bit to see if the MDI read completed 271 * Increasing the time out as testing showed failures with 272 * the lower time out 273 */ 274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 275 udelay(50); 276 mdic = er32(MDIC); 277 if (mdic & E1000_MDIC_READY) 278 break; 279 } 280 if (!(mdic & E1000_MDIC_READY)) { 281 e_dbg("MDI Write did not complete\n"); 282 return -E1000_ERR_PHY; 283 } 284 if (mdic & E1000_MDIC_ERROR) { 285 e_dbg("MDI Error\n"); 286 return -E1000_ERR_PHY; 287 } 288 289 /* 290 * Allow some time after each MDIC transaction to avoid 291 * reading duplicate data in the next MDIC transaction. 292 */ 293 if (hw->mac.type == e1000_pch2lan) 294 udelay(100); 295 296 return 0; 297 } 298 299 /** 300 * e1000e_read_phy_reg_m88 - Read m88 PHY register 301 * @hw: pointer to the HW structure 302 * @offset: register offset to be read 303 * @data: pointer to the read data 304 * 305 * Acquires semaphore, if necessary, then reads the PHY register at offset 306 * and storing the retrieved information in data. Release any acquired 307 * semaphores before exiting. 308 **/ 309 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 310 { 311 s32 ret_val; 312 313 ret_val = hw->phy.ops.acquire(hw); 314 if (ret_val) 315 return ret_val; 316 317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 318 data); 319 320 hw->phy.ops.release(hw); 321 322 return ret_val; 323 } 324 325 /** 326 * e1000e_write_phy_reg_m88 - Write m88 PHY register 327 * @hw: pointer to the HW structure 328 * @offset: register offset to write to 329 * @data: data to write at register offset 330 * 331 * Acquires semaphore, if necessary, then writes the data to PHY register 332 * at the offset. Release any acquired semaphores before exiting. 333 **/ 334 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 335 { 336 s32 ret_val; 337 338 ret_val = hw->phy.ops.acquire(hw); 339 if (ret_val) 340 return ret_val; 341 342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 343 data); 344 345 hw->phy.ops.release(hw); 346 347 return ret_val; 348 } 349 350 /** 351 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 352 * @hw: pointer to the HW structure 353 * @page: page to set (shifted left when necessary) 354 * 355 * Sets PHY page required for PHY register access. Assumes semaphore is 356 * already acquired. Note, this function sets phy.addr to 1 so the caller 357 * must set it appropriately (if necessary) after this function returns. 358 **/ 359 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 360 { 361 e_dbg("Setting page 0x%x\n", page); 362 363 hw->phy.addr = 1; 364 365 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 366 } 367 368 /** 369 * __e1000e_read_phy_reg_igp - Read igp PHY register 370 * @hw: pointer to the HW structure 371 * @offset: register offset to be read 372 * @data: pointer to the read data 373 * @locked: semaphore has already been acquired or not 374 * 375 * Acquires semaphore, if necessary, then reads the PHY register at offset 376 * and stores the retrieved information in data. Release any acquired 377 * semaphores before exiting. 378 **/ 379 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 380 bool locked) 381 { 382 s32 ret_val = 0; 383 384 if (!locked) { 385 if (!(hw->phy.ops.acquire)) 386 goto out; 387 388 ret_val = hw->phy.ops.acquire(hw); 389 if (ret_val) 390 goto out; 391 } 392 393 if (offset > MAX_PHY_MULTI_PAGE_REG) { 394 ret_val = e1000e_write_phy_reg_mdic(hw, 395 IGP01E1000_PHY_PAGE_SELECT, 396 (u16)offset); 397 if (ret_val) 398 goto release; 399 } 400 401 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 402 data); 403 404 release: 405 if (!locked) 406 hw->phy.ops.release(hw); 407 out: 408 return ret_val; 409 } 410 411 /** 412 * e1000e_read_phy_reg_igp - Read igp PHY register 413 * @hw: pointer to the HW structure 414 * @offset: register offset to be read 415 * @data: pointer to the read data 416 * 417 * Acquires semaphore then reads the PHY register at offset and stores the 418 * retrieved information in data. 419 * Release the acquired semaphore before exiting. 420 **/ 421 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 422 { 423 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 424 } 425 426 /** 427 * e1000e_read_phy_reg_igp_locked - Read igp PHY register 428 * @hw: pointer to the HW structure 429 * @offset: register offset to be read 430 * @data: pointer to the read data 431 * 432 * Reads the PHY register at offset and stores the retrieved information 433 * in data. Assumes semaphore already acquired. 434 **/ 435 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 436 { 437 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 438 } 439 440 /** 441 * e1000e_write_phy_reg_igp - Write igp PHY register 442 * @hw: pointer to the HW structure 443 * @offset: register offset to write to 444 * @data: data to write at register offset 445 * @locked: semaphore has already been acquired or not 446 * 447 * Acquires semaphore, if necessary, then writes the data to PHY register 448 * at the offset. Release any acquired semaphores before exiting. 449 **/ 450 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 451 bool locked) 452 { 453 s32 ret_val = 0; 454 455 if (!locked) { 456 if (!(hw->phy.ops.acquire)) 457 goto out; 458 459 ret_val = hw->phy.ops.acquire(hw); 460 if (ret_val) 461 goto out; 462 } 463 464 if (offset > MAX_PHY_MULTI_PAGE_REG) { 465 ret_val = e1000e_write_phy_reg_mdic(hw, 466 IGP01E1000_PHY_PAGE_SELECT, 467 (u16)offset); 468 if (ret_val) 469 goto release; 470 } 471 472 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 473 data); 474 475 release: 476 if (!locked) 477 hw->phy.ops.release(hw); 478 479 out: 480 return ret_val; 481 } 482 483 /** 484 * e1000e_write_phy_reg_igp - Write igp PHY register 485 * @hw: pointer to the HW structure 486 * @offset: register offset to write to 487 * @data: data to write at register offset 488 * 489 * Acquires semaphore then writes the data to PHY register 490 * at the offset. Release any acquired semaphores before exiting. 491 **/ 492 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 493 { 494 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 495 } 496 497 /** 498 * e1000e_write_phy_reg_igp_locked - Write igp PHY register 499 * @hw: pointer to the HW structure 500 * @offset: register offset to write to 501 * @data: data to write at register offset 502 * 503 * Writes the data to PHY register at the offset. 504 * Assumes semaphore already acquired. 505 **/ 506 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 507 { 508 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 509 } 510 511 /** 512 * __e1000_read_kmrn_reg - Read kumeran register 513 * @hw: pointer to the HW structure 514 * @offset: register offset to be read 515 * @data: pointer to the read data 516 * @locked: semaphore has already been acquired or not 517 * 518 * Acquires semaphore, if necessary. Then reads the PHY register at offset 519 * using the kumeran interface. The information retrieved is stored in data. 520 * Release any acquired semaphores before exiting. 521 **/ 522 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 523 bool locked) 524 { 525 u32 kmrnctrlsta; 526 s32 ret_val = 0; 527 528 if (!locked) { 529 if (!(hw->phy.ops.acquire)) 530 goto out; 531 532 ret_val = hw->phy.ops.acquire(hw); 533 if (ret_val) 534 goto out; 535 } 536 537 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 538 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 539 ew32(KMRNCTRLSTA, kmrnctrlsta); 540 e1e_flush(); 541 542 udelay(2); 543 544 kmrnctrlsta = er32(KMRNCTRLSTA); 545 *data = (u16)kmrnctrlsta; 546 547 if (!locked) 548 hw->phy.ops.release(hw); 549 550 out: 551 return ret_val; 552 } 553 554 /** 555 * e1000e_read_kmrn_reg - Read kumeran register 556 * @hw: pointer to the HW structure 557 * @offset: register offset to be read 558 * @data: pointer to the read data 559 * 560 * Acquires semaphore then reads the PHY register at offset using the 561 * kumeran interface. The information retrieved is stored in data. 562 * Release the acquired semaphore before exiting. 563 **/ 564 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) 565 { 566 return __e1000_read_kmrn_reg(hw, offset, data, false); 567 } 568 569 /** 570 * e1000e_read_kmrn_reg_locked - Read kumeran register 571 * @hw: pointer to the HW structure 572 * @offset: register offset to be read 573 * @data: pointer to the read data 574 * 575 * Reads the PHY register at offset using the kumeran interface. The 576 * information retrieved is stored in data. 577 * Assumes semaphore already acquired. 578 **/ 579 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 580 { 581 return __e1000_read_kmrn_reg(hw, offset, data, true); 582 } 583 584 /** 585 * __e1000_write_kmrn_reg - Write kumeran register 586 * @hw: pointer to the HW structure 587 * @offset: register offset to write to 588 * @data: data to write at register offset 589 * @locked: semaphore has already been acquired or not 590 * 591 * Acquires semaphore, if necessary. Then write the data to PHY register 592 * at the offset using the kumeran interface. Release any acquired semaphores 593 * before exiting. 594 **/ 595 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 596 bool locked) 597 { 598 u32 kmrnctrlsta; 599 s32 ret_val = 0; 600 601 if (!locked) { 602 if (!(hw->phy.ops.acquire)) 603 goto out; 604 605 ret_val = hw->phy.ops.acquire(hw); 606 if (ret_val) 607 goto out; 608 } 609 610 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 611 E1000_KMRNCTRLSTA_OFFSET) | data; 612 ew32(KMRNCTRLSTA, kmrnctrlsta); 613 e1e_flush(); 614 615 udelay(2); 616 617 if (!locked) 618 hw->phy.ops.release(hw); 619 620 out: 621 return ret_val; 622 } 623 624 /** 625 * e1000e_write_kmrn_reg - Write kumeran register 626 * @hw: pointer to the HW structure 627 * @offset: register offset to write to 628 * @data: data to write at register offset 629 * 630 * Acquires semaphore then writes the data to the PHY register at the offset 631 * using the kumeran interface. Release the acquired semaphore before exiting. 632 **/ 633 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) 634 { 635 return __e1000_write_kmrn_reg(hw, offset, data, false); 636 } 637 638 /** 639 * e1000e_write_kmrn_reg_locked - Write kumeran register 640 * @hw: pointer to the HW structure 641 * @offset: register offset to write to 642 * @data: data to write at register offset 643 * 644 * Write the data to PHY register at the offset using the kumeran interface. 645 * Assumes semaphore already acquired. 646 **/ 647 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 648 { 649 return __e1000_write_kmrn_reg(hw, offset, data, true); 650 } 651 652 /** 653 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 654 * @hw: pointer to the HW structure 655 * 656 * Sets up Carrier-sense on Transmit and downshift values. 657 **/ 658 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 659 { 660 s32 ret_val; 661 u16 phy_data; 662 663 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 664 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 665 if (ret_val) 666 goto out; 667 668 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 669 670 /* Enable downshift */ 671 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 672 673 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 674 675 out: 676 return ret_val; 677 } 678 679 /** 680 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 681 * @hw: pointer to the HW structure 682 * 683 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 684 * and downshift values are set also. 685 **/ 686 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) 687 { 688 struct e1000_phy_info *phy = &hw->phy; 689 s32 ret_val; 690 u16 phy_data; 691 692 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 693 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 694 if (ret_val) 695 return ret_val; 696 697 /* For BM PHY this bit is downshift enable */ 698 if (phy->type != e1000_phy_bm) 699 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 700 701 /* 702 * Options: 703 * MDI/MDI-X = 0 (default) 704 * 0 - Auto for all speeds 705 * 1 - MDI mode 706 * 2 - MDI-X mode 707 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 708 */ 709 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 710 711 switch (phy->mdix) { 712 case 1: 713 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 714 break; 715 case 2: 716 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 717 break; 718 case 3: 719 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 720 break; 721 case 0: 722 default: 723 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 724 break; 725 } 726 727 /* 728 * Options: 729 * disable_polarity_correction = 0 (default) 730 * Automatic Correction for Reversed Cable Polarity 731 * 0 - Disabled 732 * 1 - Enabled 733 */ 734 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 735 if (phy->disable_polarity_correction == 1) 736 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 737 738 /* Enable downshift on BM (disabled by default) */ 739 if (phy->type == e1000_phy_bm) 740 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 741 742 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 743 if (ret_val) 744 return ret_val; 745 746 if ((phy->type == e1000_phy_m88) && 747 (phy->revision < E1000_REVISION_4) && 748 (phy->id != BME1000_E_PHY_ID_R2)) { 749 /* 750 * Force TX_CLK in the Extended PHY Specific Control Register 751 * to 25MHz clock. 752 */ 753 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 754 if (ret_val) 755 return ret_val; 756 757 phy_data |= M88E1000_EPSCR_TX_CLK_25; 758 759 if ((phy->revision == 2) && 760 (phy->id == M88E1111_I_PHY_ID)) { 761 /* 82573L PHY - set the downshift counter to 5x. */ 762 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 763 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 764 } else { 765 /* Configure Master and Slave downshift values */ 766 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 767 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 768 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 769 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 770 } 771 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 772 if (ret_val) 773 return ret_val; 774 } 775 776 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 777 /* Set PHY page 0, register 29 to 0x0003 */ 778 ret_val = e1e_wphy(hw, 29, 0x0003); 779 if (ret_val) 780 return ret_val; 781 782 /* Set PHY page 0, register 30 to 0x0000 */ 783 ret_val = e1e_wphy(hw, 30, 0x0000); 784 if (ret_val) 785 return ret_val; 786 } 787 788 /* Commit the changes. */ 789 ret_val = e1000e_commit_phy(hw); 790 if (ret_val) { 791 e_dbg("Error committing the PHY changes\n"); 792 return ret_val; 793 } 794 795 if (phy->type == e1000_phy_82578) { 796 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 797 if (ret_val) 798 return ret_val; 799 800 /* 82578 PHY - set the downshift count to 1x. */ 801 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 802 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 803 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 804 if (ret_val) 805 return ret_val; 806 } 807 808 return 0; 809 } 810 811 /** 812 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link 813 * @hw: pointer to the HW structure 814 * 815 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 816 * igp PHY's. 817 **/ 818 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) 819 { 820 struct e1000_phy_info *phy = &hw->phy; 821 s32 ret_val; 822 u16 data; 823 824 ret_val = e1000_phy_hw_reset(hw); 825 if (ret_val) { 826 e_dbg("Error resetting the PHY.\n"); 827 return ret_val; 828 } 829 830 /* 831 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 832 * timeout issues when LFS is enabled. 833 */ 834 msleep(100); 835 836 /* disable lplu d0 during driver init */ 837 ret_val = e1000_set_d0_lplu_state(hw, false); 838 if (ret_val) { 839 e_dbg("Error Disabling LPLU D0\n"); 840 return ret_val; 841 } 842 /* Configure mdi-mdix settings */ 843 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 844 if (ret_val) 845 return ret_val; 846 847 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 848 849 switch (phy->mdix) { 850 case 1: 851 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 852 break; 853 case 2: 854 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 855 break; 856 case 0: 857 default: 858 data |= IGP01E1000_PSCR_AUTO_MDIX; 859 break; 860 } 861 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 862 if (ret_val) 863 return ret_val; 864 865 /* set auto-master slave resolution settings */ 866 if (hw->mac.autoneg) { 867 /* 868 * when autonegotiation advertisement is only 1000Mbps then we 869 * should disable SmartSpeed and enable Auto MasterSlave 870 * resolution as hardware default. 871 */ 872 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 873 /* Disable SmartSpeed */ 874 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 875 &data); 876 if (ret_val) 877 return ret_val; 878 879 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 880 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 881 data); 882 if (ret_val) 883 return ret_val; 884 885 /* Set auto Master/Slave resolution process */ 886 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 887 if (ret_val) 888 return ret_val; 889 890 data &= ~CR_1000T_MS_ENABLE; 891 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 892 if (ret_val) 893 return ret_val; 894 } 895 896 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 897 if (ret_val) 898 return ret_val; 899 900 /* load defaults for future use */ 901 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 902 ((data & CR_1000T_MS_VALUE) ? 903 e1000_ms_force_master : 904 e1000_ms_force_slave) : 905 e1000_ms_auto; 906 907 switch (phy->ms_type) { 908 case e1000_ms_force_master: 909 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 910 break; 911 case e1000_ms_force_slave: 912 data |= CR_1000T_MS_ENABLE; 913 data &= ~(CR_1000T_MS_VALUE); 914 break; 915 case e1000_ms_auto: 916 data &= ~CR_1000T_MS_ENABLE; 917 default: 918 break; 919 } 920 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 921 } 922 923 return ret_val; 924 } 925 926 /** 927 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 928 * @hw: pointer to the HW structure 929 * 930 * Reads the MII auto-neg advertisement register and/or the 1000T control 931 * register and if the PHY is already setup for auto-negotiation, then 932 * return successful. Otherwise, setup advertisement and flow control to 933 * the appropriate values for the wanted auto-negotiation. 934 **/ 935 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 936 { 937 struct e1000_phy_info *phy = &hw->phy; 938 s32 ret_val; 939 u16 mii_autoneg_adv_reg; 940 u16 mii_1000t_ctrl_reg = 0; 941 942 phy->autoneg_advertised &= phy->autoneg_mask; 943 944 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 945 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 946 if (ret_val) 947 return ret_val; 948 949 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 950 /* Read the MII 1000Base-T Control Register (Address 9). */ 951 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 952 if (ret_val) 953 return ret_val; 954 } 955 956 /* 957 * Need to parse both autoneg_advertised and fc and set up 958 * the appropriate PHY registers. First we will parse for 959 * autoneg_advertised software override. Since we can advertise 960 * a plethora of combinations, we need to check each bit 961 * individually. 962 */ 963 964 /* 965 * First we clear all the 10/100 mb speed bits in the Auto-Neg 966 * Advertisement Register (Address 4) and the 1000 mb speed bits in 967 * the 1000Base-T Control Register (Address 9). 968 */ 969 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 970 NWAY_AR_100TX_HD_CAPS | 971 NWAY_AR_10T_FD_CAPS | 972 NWAY_AR_10T_HD_CAPS); 973 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 974 975 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 976 977 /* Do we want to advertise 10 Mb Half Duplex? */ 978 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 979 e_dbg("Advertise 10mb Half duplex\n"); 980 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 981 } 982 983 /* Do we want to advertise 10 Mb Full Duplex? */ 984 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 985 e_dbg("Advertise 10mb Full duplex\n"); 986 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 987 } 988 989 /* Do we want to advertise 100 Mb Half Duplex? */ 990 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 991 e_dbg("Advertise 100mb Half duplex\n"); 992 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 993 } 994 995 /* Do we want to advertise 100 Mb Full Duplex? */ 996 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 997 e_dbg("Advertise 100mb Full duplex\n"); 998 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 999 } 1000 1001 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1002 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1003 e_dbg("Advertise 1000mb Half duplex request denied!\n"); 1004 1005 /* Do we want to advertise 1000 Mb Full Duplex? */ 1006 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1007 e_dbg("Advertise 1000mb Full duplex\n"); 1008 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1009 } 1010 1011 /* 1012 * Check for a software override of the flow control settings, and 1013 * setup the PHY advertisement registers accordingly. If 1014 * auto-negotiation is enabled, then software will have to set the 1015 * "PAUSE" bits to the correct value in the Auto-Negotiation 1016 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1017 * negotiation. 1018 * 1019 * The possible values of the "fc" parameter are: 1020 * 0: Flow control is completely disabled 1021 * 1: Rx flow control is enabled (we can receive pause frames 1022 * but not send pause frames). 1023 * 2: Tx flow control is enabled (we can send pause frames 1024 * but we do not support receiving pause frames). 1025 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1026 * other: No software override. The flow control configuration 1027 * in the EEPROM is used. 1028 */ 1029 switch (hw->fc.current_mode) { 1030 case e1000_fc_none: 1031 /* 1032 * Flow control (Rx & Tx) is completely disabled by a 1033 * software over-ride. 1034 */ 1035 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1036 break; 1037 case e1000_fc_rx_pause: 1038 /* 1039 * Rx Flow control is enabled, and Tx Flow control is 1040 * disabled, by a software over-ride. 1041 * 1042 * Since there really isn't a way to advertise that we are 1043 * capable of Rx Pause ONLY, we will advertise that we 1044 * support both symmetric and asymmetric Rx PAUSE. Later 1045 * (in e1000e_config_fc_after_link_up) we will disable the 1046 * hw's ability to send PAUSE frames. 1047 */ 1048 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1049 break; 1050 case e1000_fc_tx_pause: 1051 /* 1052 * Tx Flow control is enabled, and Rx Flow control is 1053 * disabled, by a software over-ride. 1054 */ 1055 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1056 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1057 break; 1058 case e1000_fc_full: 1059 /* 1060 * Flow control (both Rx and Tx) is enabled by a software 1061 * over-ride. 1062 */ 1063 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1064 break; 1065 default: 1066 e_dbg("Flow control param set incorrectly\n"); 1067 ret_val = -E1000_ERR_CONFIG; 1068 return ret_val; 1069 } 1070 1071 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1072 if (ret_val) 1073 return ret_val; 1074 1075 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1076 1077 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1078 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1079 1080 return ret_val; 1081 } 1082 1083 /** 1084 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1085 * @hw: pointer to the HW structure 1086 * 1087 * Performs initial bounds checking on autoneg advertisement parameter, then 1088 * configure to advertise the full capability. Setup the PHY to autoneg 1089 * and restart the negotiation process between the link partner. If 1090 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1091 **/ 1092 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1093 { 1094 struct e1000_phy_info *phy = &hw->phy; 1095 s32 ret_val; 1096 u16 phy_ctrl; 1097 1098 /* 1099 * Perform some bounds checking on the autoneg advertisement 1100 * parameter. 1101 */ 1102 phy->autoneg_advertised &= phy->autoneg_mask; 1103 1104 /* 1105 * If autoneg_advertised is zero, we assume it was not defaulted 1106 * by the calling code so we set to advertise full capability. 1107 */ 1108 if (phy->autoneg_advertised == 0) 1109 phy->autoneg_advertised = phy->autoneg_mask; 1110 1111 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1112 ret_val = e1000_phy_setup_autoneg(hw); 1113 if (ret_val) { 1114 e_dbg("Error Setting up Auto-Negotiation\n"); 1115 return ret_val; 1116 } 1117 e_dbg("Restarting Auto-Neg\n"); 1118 1119 /* 1120 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1121 * the Auto Neg Restart bit in the PHY control register. 1122 */ 1123 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 1124 if (ret_val) 1125 return ret_val; 1126 1127 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1128 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 1129 if (ret_val) 1130 return ret_val; 1131 1132 /* 1133 * Does the user want to wait for Auto-Neg to complete here, or 1134 * check at a later time (for example, callback routine). 1135 */ 1136 if (phy->autoneg_wait_to_complete) { 1137 ret_val = e1000_wait_autoneg(hw); 1138 if (ret_val) { 1139 e_dbg("Error while waiting for " 1140 "autoneg to complete\n"); 1141 return ret_val; 1142 } 1143 } 1144 1145 hw->mac.get_link_status = 1; 1146 1147 return ret_val; 1148 } 1149 1150 /** 1151 * e1000e_setup_copper_link - Configure copper link settings 1152 * @hw: pointer to the HW structure 1153 * 1154 * Calls the appropriate function to configure the link for auto-neg or forced 1155 * speed and duplex. Then we check for link, once link is established calls 1156 * to configure collision distance and flow control are called. If link is 1157 * not established, we return -E1000_ERR_PHY (-2). 1158 **/ 1159 s32 e1000e_setup_copper_link(struct e1000_hw *hw) 1160 { 1161 s32 ret_val; 1162 bool link; 1163 1164 if (hw->mac.autoneg) { 1165 /* 1166 * Setup autoneg and flow control advertisement and perform 1167 * autonegotiation. 1168 */ 1169 ret_val = e1000_copper_link_autoneg(hw); 1170 if (ret_val) 1171 return ret_val; 1172 } else { 1173 /* 1174 * PHY will be set to 10H, 10F, 100H or 100F 1175 * depending on user settings. 1176 */ 1177 e_dbg("Forcing Speed and Duplex\n"); 1178 ret_val = e1000_phy_force_speed_duplex(hw); 1179 if (ret_val) { 1180 e_dbg("Error Forcing Speed and Duplex\n"); 1181 return ret_val; 1182 } 1183 } 1184 1185 /* 1186 * Check link status. Wait up to 100 microseconds for link to become 1187 * valid. 1188 */ 1189 ret_val = e1000e_phy_has_link_generic(hw, 1190 COPPER_LINK_UP_LIMIT, 1191 10, 1192 &link); 1193 if (ret_val) 1194 return ret_val; 1195 1196 if (link) { 1197 e_dbg("Valid link established!!!\n"); 1198 e1000e_config_collision_dist(hw); 1199 ret_val = e1000e_config_fc_after_link_up(hw); 1200 } else { 1201 e_dbg("Unable to establish link!!!\n"); 1202 } 1203 1204 return ret_val; 1205 } 1206 1207 /** 1208 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1209 * @hw: pointer to the HW structure 1210 * 1211 * Calls the PHY setup function to force speed and duplex. Clears the 1212 * auto-crossover to force MDI manually. Waits for link and returns 1213 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1214 **/ 1215 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1216 { 1217 struct e1000_phy_info *phy = &hw->phy; 1218 s32 ret_val; 1219 u16 phy_data; 1220 bool link; 1221 1222 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1223 if (ret_val) 1224 return ret_val; 1225 1226 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1227 1228 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1229 if (ret_val) 1230 return ret_val; 1231 1232 /* 1233 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1234 * forced whenever speed and duplex are forced. 1235 */ 1236 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1237 if (ret_val) 1238 return ret_val; 1239 1240 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1241 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1242 1243 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1244 if (ret_val) 1245 return ret_val; 1246 1247 e_dbg("IGP PSCR: %X\n", phy_data); 1248 1249 udelay(1); 1250 1251 if (phy->autoneg_wait_to_complete) { 1252 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1253 1254 ret_val = e1000e_phy_has_link_generic(hw, 1255 PHY_FORCE_LIMIT, 1256 100000, 1257 &link); 1258 if (ret_val) 1259 return ret_val; 1260 1261 if (!link) 1262 e_dbg("Link taking longer than expected.\n"); 1263 1264 /* Try once more */ 1265 ret_val = e1000e_phy_has_link_generic(hw, 1266 PHY_FORCE_LIMIT, 1267 100000, 1268 &link); 1269 if (ret_val) 1270 return ret_val; 1271 } 1272 1273 return ret_val; 1274 } 1275 1276 /** 1277 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1278 * @hw: pointer to the HW structure 1279 * 1280 * Calls the PHY setup function to force speed and duplex. Clears the 1281 * auto-crossover to force MDI manually. Resets the PHY to commit the 1282 * changes. If time expires while waiting for link up, we reset the DSP. 1283 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1284 * successful completion, else return corresponding error code. 1285 **/ 1286 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1287 { 1288 struct e1000_phy_info *phy = &hw->phy; 1289 s32 ret_val; 1290 u16 phy_data; 1291 bool link; 1292 1293 /* 1294 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1295 * forced whenever speed and duplex are forced. 1296 */ 1297 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1298 if (ret_val) 1299 return ret_val; 1300 1301 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1302 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1303 if (ret_val) 1304 return ret_val; 1305 1306 e_dbg("M88E1000 PSCR: %X\n", phy_data); 1307 1308 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1309 if (ret_val) 1310 return ret_val; 1311 1312 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1313 1314 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 1315 if (ret_val) 1316 return ret_val; 1317 1318 /* Reset the phy to commit changes. */ 1319 ret_val = e1000e_commit_phy(hw); 1320 if (ret_val) 1321 return ret_val; 1322 1323 if (phy->autoneg_wait_to_complete) { 1324 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1325 1326 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1327 100000, &link); 1328 if (ret_val) 1329 return ret_val; 1330 1331 if (!link) { 1332 if (hw->phy.type != e1000_phy_m88) { 1333 e_dbg("Link taking longer than expected.\n"); 1334 } else { 1335 /* 1336 * We didn't get link. 1337 * Reset the DSP and cross our fingers. 1338 */ 1339 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1340 0x001d); 1341 if (ret_val) 1342 return ret_val; 1343 ret_val = e1000e_phy_reset_dsp(hw); 1344 if (ret_val) 1345 return ret_val; 1346 } 1347 } 1348 1349 /* Try once more */ 1350 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1351 100000, &link); 1352 if (ret_val) 1353 return ret_val; 1354 } 1355 1356 if (hw->phy.type != e1000_phy_m88) 1357 return 0; 1358 1359 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1360 if (ret_val) 1361 return ret_val; 1362 1363 /* 1364 * Resetting the phy means we need to re-force TX_CLK in the 1365 * Extended PHY Specific Control Register to 25MHz clock from 1366 * the reset value of 2.5MHz. 1367 */ 1368 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1369 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1370 if (ret_val) 1371 return ret_val; 1372 1373 /* 1374 * In addition, we must re-enable CRS on Tx for both half and full 1375 * duplex. 1376 */ 1377 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1378 if (ret_val) 1379 return ret_val; 1380 1381 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1382 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1383 1384 return ret_val; 1385 } 1386 1387 /** 1388 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1389 * @hw: pointer to the HW structure 1390 * 1391 * Forces the speed and duplex settings of the PHY. 1392 * This is a function pointer entry point only called by 1393 * PHY setup routines. 1394 **/ 1395 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1396 { 1397 struct e1000_phy_info *phy = &hw->phy; 1398 s32 ret_val; 1399 u16 data; 1400 bool link; 1401 1402 ret_val = e1e_rphy(hw, PHY_CONTROL, &data); 1403 if (ret_val) 1404 goto out; 1405 1406 e1000e_phy_force_speed_duplex_setup(hw, &data); 1407 1408 ret_val = e1e_wphy(hw, PHY_CONTROL, data); 1409 if (ret_val) 1410 goto out; 1411 1412 /* Disable MDI-X support for 10/100 */ 1413 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 1414 if (ret_val) 1415 goto out; 1416 1417 data &= ~IFE_PMC_AUTO_MDIX; 1418 data &= ~IFE_PMC_FORCE_MDIX; 1419 1420 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); 1421 if (ret_val) 1422 goto out; 1423 1424 e_dbg("IFE PMC: %X\n", data); 1425 1426 udelay(1); 1427 1428 if (phy->autoneg_wait_to_complete) { 1429 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); 1430 1431 ret_val = e1000e_phy_has_link_generic(hw, 1432 PHY_FORCE_LIMIT, 1433 100000, 1434 &link); 1435 if (ret_val) 1436 goto out; 1437 1438 if (!link) 1439 e_dbg("Link taking longer than expected.\n"); 1440 1441 /* Try once more */ 1442 ret_val = e1000e_phy_has_link_generic(hw, 1443 PHY_FORCE_LIMIT, 1444 100000, 1445 &link); 1446 if (ret_val) 1447 goto out; 1448 } 1449 1450 out: 1451 return ret_val; 1452 } 1453 1454 /** 1455 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1456 * @hw: pointer to the HW structure 1457 * @phy_ctrl: pointer to current value of PHY_CONTROL 1458 * 1459 * Forces speed and duplex on the PHY by doing the following: disable flow 1460 * control, force speed/duplex on the MAC, disable auto speed detection, 1461 * disable auto-negotiation, configure duplex, configure speed, configure 1462 * the collision distance, write configuration to CTRL register. The 1463 * caller must write to the PHY_CONTROL register for these settings to 1464 * take affect. 1465 **/ 1466 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1467 { 1468 struct e1000_mac_info *mac = &hw->mac; 1469 u32 ctrl; 1470 1471 /* Turn off flow control when forcing speed/duplex */ 1472 hw->fc.current_mode = e1000_fc_none; 1473 1474 /* Force speed/duplex on the mac */ 1475 ctrl = er32(CTRL); 1476 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1477 ctrl &= ~E1000_CTRL_SPD_SEL; 1478 1479 /* Disable Auto Speed Detection */ 1480 ctrl &= ~E1000_CTRL_ASDE; 1481 1482 /* Disable autoneg on the phy */ 1483 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1484 1485 /* Forcing Full or Half Duplex? */ 1486 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1487 ctrl &= ~E1000_CTRL_FD; 1488 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1489 e_dbg("Half Duplex\n"); 1490 } else { 1491 ctrl |= E1000_CTRL_FD; 1492 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1493 e_dbg("Full Duplex\n"); 1494 } 1495 1496 /* Forcing 10mb or 100mb? */ 1497 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1498 ctrl |= E1000_CTRL_SPD_100; 1499 *phy_ctrl |= MII_CR_SPEED_100; 1500 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1501 e_dbg("Forcing 100mb\n"); 1502 } else { 1503 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1504 *phy_ctrl |= MII_CR_SPEED_10; 1505 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1506 e_dbg("Forcing 10mb\n"); 1507 } 1508 1509 e1000e_config_collision_dist(hw); 1510 1511 ew32(CTRL, ctrl); 1512 } 1513 1514 /** 1515 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 1516 * @hw: pointer to the HW structure 1517 * @active: boolean used to enable/disable lplu 1518 * 1519 * Success returns 0, Failure returns 1 1520 * 1521 * The low power link up (lplu) state is set to the power management level D3 1522 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1523 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1524 * is used during Dx states where the power conservation is most important. 1525 * During driver activity, SmartSpeed should be enabled so performance is 1526 * maintained. 1527 **/ 1528 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1529 { 1530 struct e1000_phy_info *phy = &hw->phy; 1531 s32 ret_val; 1532 u16 data; 1533 1534 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1535 if (ret_val) 1536 return ret_val; 1537 1538 if (!active) { 1539 data &= ~IGP02E1000_PM_D3_LPLU; 1540 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1541 if (ret_val) 1542 return ret_val; 1543 /* 1544 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1545 * during Dx states where the power conservation is most 1546 * important. During driver activity we should enable 1547 * SmartSpeed, so performance is maintained. 1548 */ 1549 if (phy->smart_speed == e1000_smart_speed_on) { 1550 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1551 &data); 1552 if (ret_val) 1553 return ret_val; 1554 1555 data |= IGP01E1000_PSCFR_SMART_SPEED; 1556 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1557 data); 1558 if (ret_val) 1559 return ret_val; 1560 } else if (phy->smart_speed == e1000_smart_speed_off) { 1561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1562 &data); 1563 if (ret_val) 1564 return ret_val; 1565 1566 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1567 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1568 data); 1569 if (ret_val) 1570 return ret_val; 1571 } 1572 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1573 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1574 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1575 data |= IGP02E1000_PM_D3_LPLU; 1576 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1577 if (ret_val) 1578 return ret_val; 1579 1580 /* When LPLU is enabled, we should disable SmartSpeed */ 1581 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1582 if (ret_val) 1583 return ret_val; 1584 1585 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1586 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1587 } 1588 1589 return ret_val; 1590 } 1591 1592 /** 1593 * e1000e_check_downshift - Checks whether a downshift in speed occurred 1594 * @hw: pointer to the HW structure 1595 * 1596 * Success returns 0, Failure returns 1 1597 * 1598 * A downshift is detected by querying the PHY link health. 1599 **/ 1600 s32 e1000e_check_downshift(struct e1000_hw *hw) 1601 { 1602 struct e1000_phy_info *phy = &hw->phy; 1603 s32 ret_val; 1604 u16 phy_data, offset, mask; 1605 1606 switch (phy->type) { 1607 case e1000_phy_m88: 1608 case e1000_phy_gg82563: 1609 case e1000_phy_bm: 1610 case e1000_phy_82578: 1611 offset = M88E1000_PHY_SPEC_STATUS; 1612 mask = M88E1000_PSSR_DOWNSHIFT; 1613 break; 1614 case e1000_phy_igp_2: 1615 case e1000_phy_igp_3: 1616 offset = IGP01E1000_PHY_LINK_HEALTH; 1617 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1618 break; 1619 default: 1620 /* speed downshift not supported */ 1621 phy->speed_downgraded = false; 1622 return 0; 1623 } 1624 1625 ret_val = e1e_rphy(hw, offset, &phy_data); 1626 1627 if (!ret_val) 1628 phy->speed_downgraded = (phy_data & mask); 1629 1630 return ret_val; 1631 } 1632 1633 /** 1634 * e1000_check_polarity_m88 - Checks the polarity. 1635 * @hw: pointer to the HW structure 1636 * 1637 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1638 * 1639 * Polarity is determined based on the PHY specific status register. 1640 **/ 1641 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1642 { 1643 struct e1000_phy_info *phy = &hw->phy; 1644 s32 ret_val; 1645 u16 data; 1646 1647 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 1648 1649 if (!ret_val) 1650 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1651 ? e1000_rev_polarity_reversed 1652 : e1000_rev_polarity_normal; 1653 1654 return ret_val; 1655 } 1656 1657 /** 1658 * e1000_check_polarity_igp - Checks the polarity. 1659 * @hw: pointer to the HW structure 1660 * 1661 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1662 * 1663 * Polarity is determined based on the PHY port status register, and the 1664 * current speed (since there is no polarity at 100Mbps). 1665 **/ 1666 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1667 { 1668 struct e1000_phy_info *phy = &hw->phy; 1669 s32 ret_val; 1670 u16 data, offset, mask; 1671 1672 /* 1673 * Polarity is determined based on the speed of 1674 * our connection. 1675 */ 1676 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1677 if (ret_val) 1678 return ret_val; 1679 1680 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1681 IGP01E1000_PSSR_SPEED_1000MBPS) { 1682 offset = IGP01E1000_PHY_PCS_INIT_REG; 1683 mask = IGP01E1000_PHY_POLARITY_MASK; 1684 } else { 1685 /* 1686 * This really only applies to 10Mbps since 1687 * there is no polarity for 100Mbps (always 0). 1688 */ 1689 offset = IGP01E1000_PHY_PORT_STATUS; 1690 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1691 } 1692 1693 ret_val = e1e_rphy(hw, offset, &data); 1694 1695 if (!ret_val) 1696 phy->cable_polarity = (data & mask) 1697 ? e1000_rev_polarity_reversed 1698 : e1000_rev_polarity_normal; 1699 1700 return ret_val; 1701 } 1702 1703 /** 1704 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1705 * @hw: pointer to the HW structure 1706 * 1707 * Polarity is determined on the polarity reversal feature being enabled. 1708 **/ 1709 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1710 { 1711 struct e1000_phy_info *phy = &hw->phy; 1712 s32 ret_val; 1713 u16 phy_data, offset, mask; 1714 1715 /* 1716 * Polarity is determined based on the reversal feature being enabled. 1717 */ 1718 if (phy->polarity_correction) { 1719 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1720 mask = IFE_PESC_POLARITY_REVERSED; 1721 } else { 1722 offset = IFE_PHY_SPECIAL_CONTROL; 1723 mask = IFE_PSC_FORCE_POLARITY; 1724 } 1725 1726 ret_val = e1e_rphy(hw, offset, &phy_data); 1727 1728 if (!ret_val) 1729 phy->cable_polarity = (phy_data & mask) 1730 ? e1000_rev_polarity_reversed 1731 : e1000_rev_polarity_normal; 1732 1733 return ret_val; 1734 } 1735 1736 /** 1737 * e1000_wait_autoneg - Wait for auto-neg completion 1738 * @hw: pointer to the HW structure 1739 * 1740 * Waits for auto-negotiation to complete or for the auto-negotiation time 1741 * limit to expire, which ever happens first. 1742 **/ 1743 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 1744 { 1745 s32 ret_val = 0; 1746 u16 i, phy_status; 1747 1748 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1749 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1750 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1751 if (ret_val) 1752 break; 1753 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1754 if (ret_val) 1755 break; 1756 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1757 break; 1758 msleep(100); 1759 } 1760 1761 /* 1762 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1763 * has completed. 1764 */ 1765 return ret_val; 1766 } 1767 1768 /** 1769 * e1000e_phy_has_link_generic - Polls PHY for link 1770 * @hw: pointer to the HW structure 1771 * @iterations: number of times to poll for link 1772 * @usec_interval: delay between polling attempts 1773 * @success: pointer to whether polling was successful or not 1774 * 1775 * Polls the PHY status register for link, 'iterations' number of times. 1776 **/ 1777 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1778 u32 usec_interval, bool *success) 1779 { 1780 s32 ret_val = 0; 1781 u16 i, phy_status; 1782 1783 for (i = 0; i < iterations; i++) { 1784 /* 1785 * Some PHYs require the PHY_STATUS register to be read 1786 * twice due to the link bit being sticky. No harm doing 1787 * it across the board. 1788 */ 1789 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1790 if (ret_val) 1791 /* 1792 * If the first read fails, another entity may have 1793 * ownership of the resources, wait and try again to 1794 * see if they have relinquished the resources yet. 1795 */ 1796 udelay(usec_interval); 1797 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1798 if (ret_val) 1799 break; 1800 if (phy_status & MII_SR_LINK_STATUS) 1801 break; 1802 if (usec_interval >= 1000) 1803 mdelay(usec_interval/1000); 1804 else 1805 udelay(usec_interval); 1806 } 1807 1808 *success = (i < iterations); 1809 1810 return ret_val; 1811 } 1812 1813 /** 1814 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY 1815 * @hw: pointer to the HW structure 1816 * 1817 * Reads the PHY specific status register to retrieve the cable length 1818 * information. The cable length is determined by averaging the minimum and 1819 * maximum values to get the "average" cable length. The m88 PHY has four 1820 * possible cable length values, which are: 1821 * Register Value Cable Length 1822 * 0 < 50 meters 1823 * 1 50 - 80 meters 1824 * 2 80 - 110 meters 1825 * 3 110 - 140 meters 1826 * 4 > 140 meters 1827 **/ 1828 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) 1829 { 1830 struct e1000_phy_info *phy = &hw->phy; 1831 s32 ret_val; 1832 u16 phy_data, index; 1833 1834 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1835 if (ret_val) 1836 goto out; 1837 1838 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1839 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1840 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1841 ret_val = -E1000_ERR_PHY; 1842 goto out; 1843 } 1844 1845 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1846 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1847 1848 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1849 1850 out: 1851 return ret_val; 1852 } 1853 1854 /** 1855 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1856 * @hw: pointer to the HW structure 1857 * 1858 * The automatic gain control (agc) normalizes the amplitude of the 1859 * received signal, adjusting for the attenuation produced by the 1860 * cable. By reading the AGC registers, which represent the 1861 * combination of coarse and fine gain value, the value can be put 1862 * into a lookup table to obtain the approximate cable length 1863 * for each channel. 1864 **/ 1865 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) 1866 { 1867 struct e1000_phy_info *phy = &hw->phy; 1868 s32 ret_val; 1869 u16 phy_data, i, agc_value = 0; 1870 u16 cur_agc_index, max_agc_index = 0; 1871 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1872 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1873 IGP02E1000_PHY_AGC_A, 1874 IGP02E1000_PHY_AGC_B, 1875 IGP02E1000_PHY_AGC_C, 1876 IGP02E1000_PHY_AGC_D 1877 }; 1878 1879 /* Read the AGC registers for all channels */ 1880 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1881 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); 1882 if (ret_val) 1883 return ret_val; 1884 1885 /* 1886 * Getting bits 15:9, which represent the combination of 1887 * coarse and fine gain values. The result is a number 1888 * that can be put into the lookup table to obtain the 1889 * approximate cable length. 1890 */ 1891 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1892 IGP02E1000_AGC_LENGTH_MASK; 1893 1894 /* Array index bound check. */ 1895 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1896 (cur_agc_index == 0)) 1897 return -E1000_ERR_PHY; 1898 1899 /* Remove min & max AGC values from calculation. */ 1900 if (e1000_igp_2_cable_length_table[min_agc_index] > 1901 e1000_igp_2_cable_length_table[cur_agc_index]) 1902 min_agc_index = cur_agc_index; 1903 if (e1000_igp_2_cable_length_table[max_agc_index] < 1904 e1000_igp_2_cable_length_table[cur_agc_index]) 1905 max_agc_index = cur_agc_index; 1906 1907 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1908 } 1909 1910 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1911 e1000_igp_2_cable_length_table[max_agc_index]); 1912 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1913 1914 /* Calculate cable length with the error range of +/- 10 meters. */ 1915 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1916 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1917 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1918 1919 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1920 1921 return ret_val; 1922 } 1923 1924 /** 1925 * e1000e_get_phy_info_m88 - Retrieve PHY information 1926 * @hw: pointer to the HW structure 1927 * 1928 * Valid for only copper links. Read the PHY status register (sticky read) 1929 * to verify that link is up. Read the PHY special control register to 1930 * determine the polarity and 10base-T extended distance. Read the PHY 1931 * special status register to determine MDI/MDIx and current speed. If 1932 * speed is 1000, then determine cable length, local and remote receiver. 1933 **/ 1934 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) 1935 { 1936 struct e1000_phy_info *phy = &hw->phy; 1937 s32 ret_val; 1938 u16 phy_data; 1939 bool link; 1940 1941 if (phy->media_type != e1000_media_type_copper) { 1942 e_dbg("Phy info is only valid for copper media\n"); 1943 return -E1000_ERR_CONFIG; 1944 } 1945 1946 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1947 if (ret_val) 1948 return ret_val; 1949 1950 if (!link) { 1951 e_dbg("Phy info is only valid if link is up\n"); 1952 return -E1000_ERR_CONFIG; 1953 } 1954 1955 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1956 if (ret_val) 1957 return ret_val; 1958 1959 phy->polarity_correction = (phy_data & 1960 M88E1000_PSCR_POLARITY_REVERSAL); 1961 1962 ret_val = e1000_check_polarity_m88(hw); 1963 if (ret_val) 1964 return ret_val; 1965 1966 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1967 if (ret_val) 1968 return ret_val; 1969 1970 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); 1971 1972 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1973 ret_val = e1000_get_cable_length(hw); 1974 if (ret_val) 1975 return ret_val; 1976 1977 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); 1978 if (ret_val) 1979 return ret_val; 1980 1981 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1982 ? e1000_1000t_rx_status_ok 1983 : e1000_1000t_rx_status_not_ok; 1984 1985 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1986 ? e1000_1000t_rx_status_ok 1987 : e1000_1000t_rx_status_not_ok; 1988 } else { 1989 /* Set values to "undefined" */ 1990 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1991 phy->local_rx = e1000_1000t_rx_status_undefined; 1992 phy->remote_rx = e1000_1000t_rx_status_undefined; 1993 } 1994 1995 return ret_val; 1996 } 1997 1998 /** 1999 * e1000e_get_phy_info_igp - Retrieve igp PHY information 2000 * @hw: pointer to the HW structure 2001 * 2002 * Read PHY status to determine if link is up. If link is up, then 2003 * set/determine 10base-T extended distance and polarity correction. Read 2004 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2005 * determine on the cable length, local and remote receiver. 2006 **/ 2007 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) 2008 { 2009 struct e1000_phy_info *phy = &hw->phy; 2010 s32 ret_val; 2011 u16 data; 2012 bool link; 2013 2014 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2015 if (ret_val) 2016 return ret_val; 2017 2018 if (!link) { 2019 e_dbg("Phy info is only valid if link is up\n"); 2020 return -E1000_ERR_CONFIG; 2021 } 2022 2023 phy->polarity_correction = true; 2024 2025 ret_val = e1000_check_polarity_igp(hw); 2026 if (ret_val) 2027 return ret_val; 2028 2029 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2030 if (ret_val) 2031 return ret_val; 2032 2033 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); 2034 2035 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2036 IGP01E1000_PSSR_SPEED_1000MBPS) { 2037 ret_val = e1000_get_cable_length(hw); 2038 if (ret_val) 2039 return ret_val; 2040 2041 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 2042 if (ret_val) 2043 return ret_val; 2044 2045 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2046 ? e1000_1000t_rx_status_ok 2047 : e1000_1000t_rx_status_not_ok; 2048 2049 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2050 ? e1000_1000t_rx_status_ok 2051 : e1000_1000t_rx_status_not_ok; 2052 } else { 2053 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2054 phy->local_rx = e1000_1000t_rx_status_undefined; 2055 phy->remote_rx = e1000_1000t_rx_status_undefined; 2056 } 2057 2058 return ret_val; 2059 } 2060 2061 /** 2062 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2063 * @hw: pointer to the HW structure 2064 * 2065 * Populates "phy" structure with various feature states. 2066 **/ 2067 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2068 { 2069 struct e1000_phy_info *phy = &hw->phy; 2070 s32 ret_val; 2071 u16 data; 2072 bool link; 2073 2074 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2075 if (ret_val) 2076 goto out; 2077 2078 if (!link) { 2079 e_dbg("Phy info is only valid if link is up\n"); 2080 ret_val = -E1000_ERR_CONFIG; 2081 goto out; 2082 } 2083 2084 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2085 if (ret_val) 2086 goto out; 2087 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2088 ? false : true; 2089 2090 if (phy->polarity_correction) { 2091 ret_val = e1000_check_polarity_ife(hw); 2092 if (ret_val) 2093 goto out; 2094 } else { 2095 /* Polarity is forced */ 2096 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2097 ? e1000_rev_polarity_reversed 2098 : e1000_rev_polarity_normal; 2099 } 2100 2101 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 2102 if (ret_val) 2103 goto out; 2104 2105 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; 2106 2107 /* The following parameters are undefined for 10/100 operation. */ 2108 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2109 phy->local_rx = e1000_1000t_rx_status_undefined; 2110 phy->remote_rx = e1000_1000t_rx_status_undefined; 2111 2112 out: 2113 return ret_val; 2114 } 2115 2116 /** 2117 * e1000e_phy_sw_reset - PHY software reset 2118 * @hw: pointer to the HW structure 2119 * 2120 * Does a software reset of the PHY by reading the PHY control register and 2121 * setting/write the control register reset bit to the PHY. 2122 **/ 2123 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) 2124 { 2125 s32 ret_val; 2126 u16 phy_ctrl; 2127 2128 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 2129 if (ret_val) 2130 return ret_val; 2131 2132 phy_ctrl |= MII_CR_RESET; 2133 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 2134 if (ret_val) 2135 return ret_val; 2136 2137 udelay(1); 2138 2139 return ret_val; 2140 } 2141 2142 /** 2143 * e1000e_phy_hw_reset_generic - PHY hardware reset 2144 * @hw: pointer to the HW structure 2145 * 2146 * Verify the reset block is not blocking us from resetting. Acquire 2147 * semaphore (if necessary) and read/set/write the device control reset 2148 * bit in the PHY. Wait the appropriate delay time for the device to 2149 * reset and release the semaphore (if necessary). 2150 **/ 2151 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) 2152 { 2153 struct e1000_phy_info *phy = &hw->phy; 2154 s32 ret_val; 2155 u32 ctrl; 2156 2157 ret_val = e1000_check_reset_block(hw); 2158 if (ret_val) 2159 return 0; 2160 2161 ret_val = phy->ops.acquire(hw); 2162 if (ret_val) 2163 return ret_val; 2164 2165 ctrl = er32(CTRL); 2166 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2167 e1e_flush(); 2168 2169 udelay(phy->reset_delay_us); 2170 2171 ew32(CTRL, ctrl); 2172 e1e_flush(); 2173 2174 udelay(150); 2175 2176 phy->ops.release(hw); 2177 2178 return e1000_get_phy_cfg_done(hw); 2179 } 2180 2181 /** 2182 * e1000e_get_cfg_done - Generic configuration done 2183 * @hw: pointer to the HW structure 2184 * 2185 * Generic function to wait 10 milli-seconds for configuration to complete 2186 * and return success. 2187 **/ 2188 s32 e1000e_get_cfg_done(struct e1000_hw *hw) 2189 { 2190 mdelay(10); 2191 return 0; 2192 } 2193 2194 /** 2195 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY 2196 * @hw: pointer to the HW structure 2197 * 2198 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2199 **/ 2200 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2201 { 2202 e_dbg("Running IGP 3 PHY init script\n"); 2203 2204 /* PHY init IGP 3 */ 2205 /* Enable rise/fall, 10-mode work in class-A */ 2206 e1e_wphy(hw, 0x2F5B, 0x9018); 2207 /* Remove all caps from Replica path filter */ 2208 e1e_wphy(hw, 0x2F52, 0x0000); 2209 /* Bias trimming for ADC, AFE and Driver (Default) */ 2210 e1e_wphy(hw, 0x2FB1, 0x8B24); 2211 /* Increase Hybrid poly bias */ 2212 e1e_wphy(hw, 0x2FB2, 0xF8F0); 2213 /* Add 4% to Tx amplitude in Gig mode */ 2214 e1e_wphy(hw, 0x2010, 0x10B0); 2215 /* Disable trimming (TTT) */ 2216 e1e_wphy(hw, 0x2011, 0x0000); 2217 /* Poly DC correction to 94.6% + 2% for all channels */ 2218 e1e_wphy(hw, 0x20DD, 0x249A); 2219 /* ABS DC correction to 95.9% */ 2220 e1e_wphy(hw, 0x20DE, 0x00D3); 2221 /* BG temp curve trim */ 2222 e1e_wphy(hw, 0x28B4, 0x04CE); 2223 /* Increasing ADC OPAMP stage 1 currents to max */ 2224 e1e_wphy(hw, 0x2F70, 0x29E4); 2225 /* Force 1000 ( required for enabling PHY regs configuration) */ 2226 e1e_wphy(hw, 0x0000, 0x0140); 2227 /* Set upd_freq to 6 */ 2228 e1e_wphy(hw, 0x1F30, 0x1606); 2229 /* Disable NPDFE */ 2230 e1e_wphy(hw, 0x1F31, 0xB814); 2231 /* Disable adaptive fixed FFE (Default) */ 2232 e1e_wphy(hw, 0x1F35, 0x002A); 2233 /* Enable FFE hysteresis */ 2234 e1e_wphy(hw, 0x1F3E, 0x0067); 2235 /* Fixed FFE for short cable lengths */ 2236 e1e_wphy(hw, 0x1F54, 0x0065); 2237 /* Fixed FFE for medium cable lengths */ 2238 e1e_wphy(hw, 0x1F55, 0x002A); 2239 /* Fixed FFE for long cable lengths */ 2240 e1e_wphy(hw, 0x1F56, 0x002A); 2241 /* Enable Adaptive Clip Threshold */ 2242 e1e_wphy(hw, 0x1F72, 0x3FB0); 2243 /* AHT reset limit to 1 */ 2244 e1e_wphy(hw, 0x1F76, 0xC0FF); 2245 /* Set AHT master delay to 127 msec */ 2246 e1e_wphy(hw, 0x1F77, 0x1DEC); 2247 /* Set scan bits for AHT */ 2248 e1e_wphy(hw, 0x1F78, 0xF9EF); 2249 /* Set AHT Preset bits */ 2250 e1e_wphy(hw, 0x1F79, 0x0210); 2251 /* Change integ_factor of channel A to 3 */ 2252 e1e_wphy(hw, 0x1895, 0x0003); 2253 /* Change prop_factor of channels BCD to 8 */ 2254 e1e_wphy(hw, 0x1796, 0x0008); 2255 /* Change cg_icount + enable integbp for channels BCD */ 2256 e1e_wphy(hw, 0x1798, 0xD008); 2257 /* 2258 * Change cg_icount + enable integbp + change prop_factor_master 2259 * to 8 for channel A 2260 */ 2261 e1e_wphy(hw, 0x1898, 0xD918); 2262 /* Disable AHT in Slave mode on channel A */ 2263 e1e_wphy(hw, 0x187A, 0x0800); 2264 /* 2265 * Enable LPLU and disable AN to 1000 in non-D0a states, 2266 * Enable SPD+B2B 2267 */ 2268 e1e_wphy(hw, 0x0019, 0x008D); 2269 /* Enable restart AN on an1000_dis change */ 2270 e1e_wphy(hw, 0x001B, 0x2080); 2271 /* Enable wh_fifo read clock in 10/100 modes */ 2272 e1e_wphy(hw, 0x0014, 0x0045); 2273 /* Restart AN, Speed selection is 1000 */ 2274 e1e_wphy(hw, 0x0000, 0x1340); 2275 2276 return 0; 2277 } 2278 2279 /* Internal function pointers */ 2280 2281 /** 2282 * e1000_get_phy_cfg_done - Generic PHY configuration done 2283 * @hw: pointer to the HW structure 2284 * 2285 * Return success if silicon family did not implement a family specific 2286 * get_cfg_done function. 2287 **/ 2288 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 2289 { 2290 if (hw->phy.ops.get_cfg_done) 2291 return hw->phy.ops.get_cfg_done(hw); 2292 2293 return 0; 2294 } 2295 2296 /** 2297 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex 2298 * @hw: pointer to the HW structure 2299 * 2300 * When the silicon family has not implemented a forced speed/duplex 2301 * function for the PHY, simply return 0. 2302 **/ 2303 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2304 { 2305 if (hw->phy.ops.force_speed_duplex) 2306 return hw->phy.ops.force_speed_duplex(hw); 2307 2308 return 0; 2309 } 2310 2311 /** 2312 * e1000e_get_phy_type_from_id - Get PHY type from id 2313 * @phy_id: phy_id read from the phy 2314 * 2315 * Returns the phy type from the id. 2316 **/ 2317 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) 2318 { 2319 enum e1000_phy_type phy_type = e1000_phy_unknown; 2320 2321 switch (phy_id) { 2322 case M88E1000_I_PHY_ID: 2323 case M88E1000_E_PHY_ID: 2324 case M88E1111_I_PHY_ID: 2325 case M88E1011_I_PHY_ID: 2326 phy_type = e1000_phy_m88; 2327 break; 2328 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2329 phy_type = e1000_phy_igp_2; 2330 break; 2331 case GG82563_E_PHY_ID: 2332 phy_type = e1000_phy_gg82563; 2333 break; 2334 case IGP03E1000_E_PHY_ID: 2335 phy_type = e1000_phy_igp_3; 2336 break; 2337 case IFE_E_PHY_ID: 2338 case IFE_PLUS_E_PHY_ID: 2339 case IFE_C_E_PHY_ID: 2340 phy_type = e1000_phy_ife; 2341 break; 2342 case BME1000_E_PHY_ID: 2343 case BME1000_E_PHY_ID_R2: 2344 phy_type = e1000_phy_bm; 2345 break; 2346 case I82578_E_PHY_ID: 2347 phy_type = e1000_phy_82578; 2348 break; 2349 case I82577_E_PHY_ID: 2350 phy_type = e1000_phy_82577; 2351 break; 2352 case I82579_E_PHY_ID: 2353 phy_type = e1000_phy_82579; 2354 break; 2355 default: 2356 phy_type = e1000_phy_unknown; 2357 break; 2358 } 2359 return phy_type; 2360 } 2361 2362 /** 2363 * e1000e_determine_phy_address - Determines PHY address. 2364 * @hw: pointer to the HW structure 2365 * 2366 * This uses a trial and error method to loop through possible PHY 2367 * addresses. It tests each by reading the PHY ID registers and 2368 * checking for a match. 2369 **/ 2370 s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2371 { 2372 s32 ret_val = -E1000_ERR_PHY_TYPE; 2373 u32 phy_addr = 0; 2374 u32 i; 2375 enum e1000_phy_type phy_type = e1000_phy_unknown; 2376 2377 hw->phy.id = phy_type; 2378 2379 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2380 hw->phy.addr = phy_addr; 2381 i = 0; 2382 2383 do { 2384 e1000e_get_phy_id(hw); 2385 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2386 2387 /* 2388 * If phy_type is valid, break - we found our 2389 * PHY address 2390 */ 2391 if (phy_type != e1000_phy_unknown) { 2392 ret_val = 0; 2393 goto out; 2394 } 2395 usleep_range(1000, 2000); 2396 i++; 2397 } while (i < 10); 2398 } 2399 2400 out: 2401 return ret_val; 2402 } 2403 2404 /** 2405 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2406 * @page: page to access 2407 * 2408 * Returns the phy address for the page requested. 2409 **/ 2410 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2411 { 2412 u32 phy_addr = 2; 2413 2414 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2415 phy_addr = 1; 2416 2417 return phy_addr; 2418 } 2419 2420 /** 2421 * e1000e_write_phy_reg_bm - Write BM PHY register 2422 * @hw: pointer to the HW structure 2423 * @offset: register offset to write to 2424 * @data: data to write at register offset 2425 * 2426 * Acquires semaphore, if necessary, then writes the data to PHY register 2427 * at the offset. Release any acquired semaphores before exiting. 2428 **/ 2429 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2430 { 2431 s32 ret_val; 2432 u32 page = offset >> IGP_PAGE_SHIFT; 2433 2434 ret_val = hw->phy.ops.acquire(hw); 2435 if (ret_val) 2436 return ret_val; 2437 2438 /* Page 800 works differently than the rest so it has its own func */ 2439 if (page == BM_WUC_PAGE) { 2440 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2441 false, false); 2442 goto out; 2443 } 2444 2445 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2446 2447 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2448 u32 page_shift, page_select; 2449 2450 /* 2451 * Page select is register 31 for phy address 1 and 22 for 2452 * phy address 2 and 3. Page select is shifted only for 2453 * phy address 1. 2454 */ 2455 if (hw->phy.addr == 1) { 2456 page_shift = IGP_PAGE_SHIFT; 2457 page_select = IGP01E1000_PHY_PAGE_SELECT; 2458 } else { 2459 page_shift = 0; 2460 page_select = BM_PHY_PAGE_SELECT; 2461 } 2462 2463 /* Page is shifted left, PHY expects (page x 32) */ 2464 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2465 (page << page_shift)); 2466 if (ret_val) 2467 goto out; 2468 } 2469 2470 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2471 data); 2472 2473 out: 2474 hw->phy.ops.release(hw); 2475 return ret_val; 2476 } 2477 2478 /** 2479 * e1000e_read_phy_reg_bm - Read BM PHY register 2480 * @hw: pointer to the HW structure 2481 * @offset: register offset to be read 2482 * @data: pointer to the read data 2483 * 2484 * Acquires semaphore, if necessary, then reads the PHY register at offset 2485 * and storing the retrieved information in data. Release any acquired 2486 * semaphores before exiting. 2487 **/ 2488 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2489 { 2490 s32 ret_val; 2491 u32 page = offset >> IGP_PAGE_SHIFT; 2492 2493 ret_val = hw->phy.ops.acquire(hw); 2494 if (ret_val) 2495 return ret_val; 2496 2497 /* Page 800 works differently than the rest so it has its own func */ 2498 if (page == BM_WUC_PAGE) { 2499 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2500 true, false); 2501 goto out; 2502 } 2503 2504 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2505 2506 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2507 u32 page_shift, page_select; 2508 2509 /* 2510 * Page select is register 31 for phy address 1 and 22 for 2511 * phy address 2 and 3. Page select is shifted only for 2512 * phy address 1. 2513 */ 2514 if (hw->phy.addr == 1) { 2515 page_shift = IGP_PAGE_SHIFT; 2516 page_select = IGP01E1000_PHY_PAGE_SELECT; 2517 } else { 2518 page_shift = 0; 2519 page_select = BM_PHY_PAGE_SELECT; 2520 } 2521 2522 /* Page is shifted left, PHY expects (page x 32) */ 2523 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2524 (page << page_shift)); 2525 if (ret_val) 2526 goto out; 2527 } 2528 2529 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2530 data); 2531 out: 2532 hw->phy.ops.release(hw); 2533 return ret_val; 2534 } 2535 2536 /** 2537 * e1000e_read_phy_reg_bm2 - Read BM PHY register 2538 * @hw: pointer to the HW structure 2539 * @offset: register offset to be read 2540 * @data: pointer to the read data 2541 * 2542 * Acquires semaphore, if necessary, then reads the PHY register at offset 2543 * and storing the retrieved information in data. Release any acquired 2544 * semaphores before exiting. 2545 **/ 2546 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2547 { 2548 s32 ret_val; 2549 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2550 2551 ret_val = hw->phy.ops.acquire(hw); 2552 if (ret_val) 2553 return ret_val; 2554 2555 /* Page 800 works differently than the rest so it has its own func */ 2556 if (page == BM_WUC_PAGE) { 2557 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2558 true, false); 2559 goto out; 2560 } 2561 2562 hw->phy.addr = 1; 2563 2564 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2565 2566 /* Page is shifted left, PHY expects (page x 32) */ 2567 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2568 page); 2569 2570 if (ret_val) 2571 goto out; 2572 } 2573 2574 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2575 data); 2576 out: 2577 hw->phy.ops.release(hw); 2578 return ret_val; 2579 } 2580 2581 /** 2582 * e1000e_write_phy_reg_bm2 - Write BM PHY register 2583 * @hw: pointer to the HW structure 2584 * @offset: register offset to write to 2585 * @data: data to write at register offset 2586 * 2587 * Acquires semaphore, if necessary, then writes the data to PHY register 2588 * at the offset. Release any acquired semaphores before exiting. 2589 **/ 2590 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2591 { 2592 s32 ret_val; 2593 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2594 2595 ret_val = hw->phy.ops.acquire(hw); 2596 if (ret_val) 2597 return ret_val; 2598 2599 /* Page 800 works differently than the rest so it has its own func */ 2600 if (page == BM_WUC_PAGE) { 2601 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2602 false, false); 2603 goto out; 2604 } 2605 2606 hw->phy.addr = 1; 2607 2608 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2609 /* Page is shifted left, PHY expects (page x 32) */ 2610 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2611 page); 2612 2613 if (ret_val) 2614 goto out; 2615 } 2616 2617 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2618 data); 2619 2620 out: 2621 hw->phy.ops.release(hw); 2622 return ret_val; 2623 } 2624 2625 /** 2626 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 2627 * @hw: pointer to the HW structure 2628 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 2629 * 2630 * Assumes semaphore already acquired and phy_reg points to a valid memory 2631 * address to store contents of the BM_WUC_ENABLE_REG register. 2632 **/ 2633 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2634 { 2635 s32 ret_val; 2636 u16 temp; 2637 2638 /* All page select, port ctrl and wakeup registers use phy address 1 */ 2639 hw->phy.addr = 1; 2640 2641 /* Select Port Control Registers page */ 2642 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2643 if (ret_val) { 2644 e_dbg("Could not set Port Control page\n"); 2645 goto out; 2646 } 2647 2648 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2649 if (ret_val) { 2650 e_dbg("Could not read PHY register %d.%d\n", 2651 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2652 goto out; 2653 } 2654 2655 /* 2656 * Enable both PHY wakeup mode and Wakeup register page writes. 2657 * Prevent a power state change by disabling ME and Host PHY wakeup. 2658 */ 2659 temp = *phy_reg; 2660 temp |= BM_WUC_ENABLE_BIT; 2661 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 2662 2663 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 2664 if (ret_val) { 2665 e_dbg("Could not write PHY register %d.%d\n", 2666 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2667 goto out; 2668 } 2669 2670 /* Select Host Wakeup Registers page */ 2671 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2672 2673 /* caller now able to write registers on the Wakeup registers page */ 2674 out: 2675 return ret_val; 2676 } 2677 2678 /** 2679 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 2680 * @hw: pointer to the HW structure 2681 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 2682 * 2683 * Restore BM_WUC_ENABLE_REG to its original value. 2684 * 2685 * Assumes semaphore already acquired and *phy_reg is the contents of the 2686 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 2687 * caller. 2688 **/ 2689 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2690 { 2691 s32 ret_val = 0; 2692 2693 /* Select Port Control Registers page */ 2694 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2695 if (ret_val) { 2696 e_dbg("Could not set Port Control page\n"); 2697 goto out; 2698 } 2699 2700 /* Restore 769.17 to its original value */ 2701 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 2702 if (ret_val) 2703 e_dbg("Could not restore PHY register %d.%d\n", 2704 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2705 out: 2706 return ret_val; 2707 } 2708 2709 /** 2710 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 2711 * @hw: pointer to the HW structure 2712 * @offset: register offset to be read or written 2713 * @data: pointer to the data to read or write 2714 * @read: determines if operation is read or write 2715 * @page_set: BM_WUC_PAGE already set and access enabled 2716 * 2717 * Read the PHY register at offset and store the retrieved information in 2718 * data, or write data to PHY register at offset. Note the procedure to 2719 * access the PHY wakeup registers is different than reading the other PHY 2720 * registers. It works as such: 2721 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 2722 * 2) Set page to 800 for host (801 if we were manageability) 2723 * 3) Write the address using the address opcode (0x11) 2724 * 4) Read or write the data using the data opcode (0x12) 2725 * 5) Restore 769.17.2 to its original value 2726 * 2727 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 2728 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 2729 * 2730 * Assumes semaphore is already acquired. When page_set==true, assumes 2731 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 2732 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 2733 **/ 2734 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2735 u16 *data, bool read, bool page_set) 2736 { 2737 s32 ret_val; 2738 u16 reg = BM_PHY_REG_NUM(offset); 2739 u16 page = BM_PHY_REG_PAGE(offset); 2740 u16 phy_reg = 0; 2741 2742 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 2743 if ((hw->mac.type == e1000_pchlan) && 2744 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2745 e_dbg("Attempting to access page %d while gig enabled.\n", 2746 page); 2747 2748 if (!page_set) { 2749 /* Enable access to PHY wakeup registers */ 2750 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2751 if (ret_val) { 2752 e_dbg("Could not enable PHY wakeup reg access\n"); 2753 goto out; 2754 } 2755 } 2756 2757 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); 2758 2759 /* Write the Wakeup register page offset value using opcode 0x11 */ 2760 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2761 if (ret_val) { 2762 e_dbg("Could not write address opcode to page %d\n", page); 2763 goto out; 2764 } 2765 2766 if (read) { 2767 /* Read the Wakeup register page value using opcode 0x12 */ 2768 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2769 data); 2770 } else { 2771 /* Write the Wakeup register page value using opcode 0x12 */ 2772 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2773 *data); 2774 } 2775 2776 if (ret_val) { 2777 e_dbg("Could not access PHY reg %d.%d\n", page, reg); 2778 goto out; 2779 } 2780 2781 if (!page_set) 2782 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2783 2784 out: 2785 return ret_val; 2786 } 2787 2788 /** 2789 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2790 * @hw: pointer to the HW structure 2791 * 2792 * In the case of a PHY power down to save power, or to turn off link during a 2793 * driver unload, or wake on lan is not enabled, restore the link to previous 2794 * settings. 2795 **/ 2796 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2797 { 2798 u16 mii_reg = 0; 2799 2800 /* The PHY will retain its settings across a power down/up cycle */ 2801 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2802 mii_reg &= ~MII_CR_POWER_DOWN; 2803 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2804 } 2805 2806 /** 2807 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2808 * @hw: pointer to the HW structure 2809 * 2810 * In the case of a PHY power down to save power, or to turn off link during a 2811 * driver unload, or wake on lan is not enabled, restore the link to previous 2812 * settings. 2813 **/ 2814 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2815 { 2816 u16 mii_reg = 0; 2817 2818 /* The PHY will retain its settings across a power down/up cycle */ 2819 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 2820 mii_reg |= MII_CR_POWER_DOWN; 2821 e1e_wphy(hw, PHY_CONTROL, mii_reg); 2822 usleep_range(1000, 2000); 2823 } 2824 2825 /** 2826 * e1000e_commit_phy - Soft PHY reset 2827 * @hw: pointer to the HW structure 2828 * 2829 * Performs a soft PHY reset on those that apply. This is a function pointer 2830 * entry point called by drivers. 2831 **/ 2832 s32 e1000e_commit_phy(struct e1000_hw *hw) 2833 { 2834 if (hw->phy.ops.commit) 2835 return hw->phy.ops.commit(hw); 2836 2837 return 0; 2838 } 2839 2840 /** 2841 * e1000_set_d0_lplu_state - Sets low power link up state for D0 2842 * @hw: pointer to the HW structure 2843 * @active: boolean used to enable/disable lplu 2844 * 2845 * Success returns 0, Failure returns 1 2846 * 2847 * The low power link up (lplu) state is set to the power management level D0 2848 * and SmartSpeed is disabled when active is true, else clear lplu for D0 2849 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2850 * is used during Dx states where the power conservation is most important. 2851 * During driver activity, SmartSpeed should be enabled so performance is 2852 * maintained. This is a function pointer entry point called by drivers. 2853 **/ 2854 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 2855 { 2856 if (hw->phy.ops.set_d0_lplu_state) 2857 return hw->phy.ops.set_d0_lplu_state(hw, active); 2858 2859 return 0; 2860 } 2861 2862 /** 2863 * __e1000_read_phy_reg_hv - Read HV PHY register 2864 * @hw: pointer to the HW structure 2865 * @offset: register offset to be read 2866 * @data: pointer to the read data 2867 * @locked: semaphore has already been acquired or not 2868 * 2869 * Acquires semaphore, if necessary, then reads the PHY register at offset 2870 * and stores the retrieved information in data. Release any acquired 2871 * semaphore before exiting. 2872 **/ 2873 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2874 bool locked, bool page_set) 2875 { 2876 s32 ret_val; 2877 u16 page = BM_PHY_REG_PAGE(offset); 2878 u16 reg = BM_PHY_REG_NUM(offset); 2879 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2880 2881 if (!locked) { 2882 ret_val = hw->phy.ops.acquire(hw); 2883 if (ret_val) 2884 return ret_val; 2885 } 2886 2887 /* Page 800 works differently than the rest so it has its own func */ 2888 if (page == BM_WUC_PAGE) { 2889 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2890 true, page_set); 2891 goto out; 2892 } 2893 2894 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2895 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2896 data, true); 2897 goto out; 2898 } 2899 2900 if (!page_set) { 2901 if (page == HV_INTC_FC_PAGE_START) 2902 page = 0; 2903 2904 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2905 /* Page is shifted left, PHY expects (page x 32) */ 2906 ret_val = e1000_set_page_igp(hw, 2907 (page << IGP_PAGE_SHIFT)); 2908 2909 hw->phy.addr = phy_addr; 2910 2911 if (ret_val) 2912 goto out; 2913 } 2914 } 2915 2916 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2917 page << IGP_PAGE_SHIFT, reg); 2918 2919 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2920 data); 2921 out: 2922 if (!locked) 2923 hw->phy.ops.release(hw); 2924 2925 return ret_val; 2926 } 2927 2928 /** 2929 * e1000_read_phy_reg_hv - Read HV PHY register 2930 * @hw: pointer to the HW structure 2931 * @offset: register offset to be read 2932 * @data: pointer to the read data 2933 * 2934 * Acquires semaphore then reads the PHY register at offset and stores 2935 * the retrieved information in data. Release the acquired semaphore 2936 * before exiting. 2937 **/ 2938 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2939 { 2940 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 2941 } 2942 2943 /** 2944 * e1000_read_phy_reg_hv_locked - Read HV PHY register 2945 * @hw: pointer to the HW structure 2946 * @offset: register offset to be read 2947 * @data: pointer to the read data 2948 * 2949 * Reads the PHY register at offset and stores the retrieved information 2950 * in data. Assumes semaphore already acquired. 2951 **/ 2952 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 2953 { 2954 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 2955 } 2956 2957 /** 2958 * e1000_read_phy_reg_page_hv - Read HV PHY register 2959 * @hw: pointer to the HW structure 2960 * @offset: register offset to write to 2961 * @data: data to write at register offset 2962 * 2963 * Reads the PHY register at offset and stores the retrieved information 2964 * in data. Assumes semaphore already acquired and page already set. 2965 **/ 2966 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2967 { 2968 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 2969 } 2970 2971 /** 2972 * __e1000_write_phy_reg_hv - Write HV PHY register 2973 * @hw: pointer to the HW structure 2974 * @offset: register offset to write to 2975 * @data: data to write at register offset 2976 * @locked: semaphore has already been acquired or not 2977 * 2978 * Acquires semaphore, if necessary, then writes the data to PHY register 2979 * at the offset. Release any acquired semaphores before exiting. 2980 **/ 2981 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 2982 bool locked, bool page_set) 2983 { 2984 s32 ret_val; 2985 u16 page = BM_PHY_REG_PAGE(offset); 2986 u16 reg = BM_PHY_REG_NUM(offset); 2987 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2988 2989 if (!locked) { 2990 ret_val = hw->phy.ops.acquire(hw); 2991 if (ret_val) 2992 return ret_val; 2993 } 2994 2995 /* Page 800 works differently than the rest so it has its own func */ 2996 if (page == BM_WUC_PAGE) { 2997 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2998 false, page_set); 2999 goto out; 3000 } 3001 3002 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3003 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3004 &data, false); 3005 goto out; 3006 } 3007 3008 if (!page_set) { 3009 if (page == HV_INTC_FC_PAGE_START) 3010 page = 0; 3011 3012 /* 3013 * Workaround MDIO accesses being disabled after entering IEEE 3014 * Power Down (when bit 11 of the PHY Control register is set) 3015 */ 3016 if ((hw->phy.type == e1000_phy_82578) && 3017 (hw->phy.revision >= 1) && 3018 (hw->phy.addr == 2) && 3019 ((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) { 3020 u16 data2 = 0x7EFF; 3021 ret_val = e1000_access_phy_debug_regs_hv(hw, 3022 (1 << 6) | 0x3, 3023 &data2, false); 3024 if (ret_val) 3025 goto out; 3026 } 3027 3028 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3029 /* Page is shifted left, PHY expects (page x 32) */ 3030 ret_val = e1000_set_page_igp(hw, 3031 (page << IGP_PAGE_SHIFT)); 3032 3033 hw->phy.addr = phy_addr; 3034 3035 if (ret_val) 3036 goto out; 3037 } 3038 } 3039 3040 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3041 page << IGP_PAGE_SHIFT, reg); 3042 3043 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3044 data); 3045 3046 out: 3047 if (!locked) 3048 hw->phy.ops.release(hw); 3049 3050 return ret_val; 3051 } 3052 3053 /** 3054 * e1000_write_phy_reg_hv - Write HV PHY register 3055 * @hw: pointer to the HW structure 3056 * @offset: register offset to write to 3057 * @data: data to write at register offset 3058 * 3059 * Acquires semaphore then writes the data to PHY register at the offset. 3060 * Release the acquired semaphores before exiting. 3061 **/ 3062 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3063 { 3064 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 3065 } 3066 3067 /** 3068 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3069 * @hw: pointer to the HW structure 3070 * @offset: register offset to write to 3071 * @data: data to write at register offset 3072 * 3073 * Writes the data to PHY register at the offset. Assumes semaphore 3074 * already acquired. 3075 **/ 3076 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3077 { 3078 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 3079 } 3080 3081 /** 3082 * e1000_write_phy_reg_page_hv - Write HV PHY register 3083 * @hw: pointer to the HW structure 3084 * @offset: register offset to write to 3085 * @data: data to write at register offset 3086 * 3087 * Writes the data to PHY register at the offset. Assumes semaphore 3088 * already acquired and page already set. 3089 **/ 3090 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3091 { 3092 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 3093 } 3094 3095 /** 3096 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page 3097 * @page: page to be accessed 3098 **/ 3099 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3100 { 3101 u32 phy_addr = 2; 3102 3103 if (page >= HV_INTC_FC_PAGE_START) 3104 phy_addr = 1; 3105 3106 return phy_addr; 3107 } 3108 3109 /** 3110 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3111 * @hw: pointer to the HW structure 3112 * @offset: register offset to be read or written 3113 * @data: pointer to the data to be read or written 3114 * @read: determines if operation is read or write 3115 * 3116 * Reads the PHY register at offset and stores the retreived information 3117 * in data. Assumes semaphore already acquired. Note that the procedure 3118 * to access these regs uses the address port and data port to read/write. 3119 * These accesses done with PHY address 2 and without using pages. 3120 **/ 3121 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3122 u16 *data, bool read) 3123 { 3124 s32 ret_val; 3125 u32 addr_reg = 0; 3126 u32 data_reg = 0; 3127 3128 /* This takes care of the difference with desktop vs mobile phy */ 3129 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3130 I82578_ADDR_REG : I82577_ADDR_REG; 3131 data_reg = addr_reg + 1; 3132 3133 /* All operations in this function are phy address 2 */ 3134 hw->phy.addr = 2; 3135 3136 /* masking with 0x3F to remove the page from offset */ 3137 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3138 if (ret_val) { 3139 e_dbg("Could not write the Address Offset port register\n"); 3140 goto out; 3141 } 3142 3143 /* Read or write the data value next */ 3144 if (read) 3145 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); 3146 else 3147 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3148 3149 if (ret_val) { 3150 e_dbg("Could not access the Data port register\n"); 3151 goto out; 3152 } 3153 3154 out: 3155 return ret_val; 3156 } 3157 3158 /** 3159 * e1000_link_stall_workaround_hv - Si workaround 3160 * @hw: pointer to the HW structure 3161 * 3162 * This function works around a Si bug where the link partner can get 3163 * a link up indication before the PHY does. If small packets are sent 3164 * by the link partner they can be placed in the packet buffer without 3165 * being properly accounted for by the PHY and will stall preventing 3166 * further packets from being received. The workaround is to clear the 3167 * packet buffer after the PHY detects link up. 3168 **/ 3169 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3170 { 3171 s32 ret_val = 0; 3172 u16 data; 3173 3174 if (hw->phy.type != e1000_phy_82578) 3175 goto out; 3176 3177 /* Do not apply workaround if in PHY loopback bit 14 set */ 3178 e1e_rphy(hw, PHY_CONTROL, &data); 3179 if (data & PHY_CONTROL_LB) 3180 goto out; 3181 3182 /* check if link is up and at 1Gbps */ 3183 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 3184 if (ret_val) 3185 goto out; 3186 3187 data &= BM_CS_STATUS_LINK_UP | 3188 BM_CS_STATUS_RESOLVED | 3189 BM_CS_STATUS_SPEED_MASK; 3190 3191 if (data != (BM_CS_STATUS_LINK_UP | 3192 BM_CS_STATUS_RESOLVED | 3193 BM_CS_STATUS_SPEED_1000)) 3194 goto out; 3195 3196 mdelay(200); 3197 3198 /* flush the packets in the fifo buffer */ 3199 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | 3200 HV_MUX_DATA_CTRL_FORCE_SPEED); 3201 if (ret_val) 3202 goto out; 3203 3204 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); 3205 3206 out: 3207 return ret_val; 3208 } 3209 3210 /** 3211 * e1000_check_polarity_82577 - Checks the polarity. 3212 * @hw: pointer to the HW structure 3213 * 3214 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3215 * 3216 * Polarity is determined based on the PHY specific status register. 3217 **/ 3218 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3219 { 3220 struct e1000_phy_info *phy = &hw->phy; 3221 s32 ret_val; 3222 u16 data; 3223 3224 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3225 3226 if (!ret_val) 3227 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3228 ? e1000_rev_polarity_reversed 3229 : e1000_rev_polarity_normal; 3230 3231 return ret_val; 3232 } 3233 3234 /** 3235 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3236 * @hw: pointer to the HW structure 3237 * 3238 * Calls the PHY setup function to force speed and duplex. 3239 **/ 3240 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3241 { 3242 struct e1000_phy_info *phy = &hw->phy; 3243 s32 ret_val; 3244 u16 phy_data; 3245 bool link; 3246 3247 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 3248 if (ret_val) 3249 goto out; 3250 3251 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3252 3253 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); 3254 if (ret_val) 3255 goto out; 3256 3257 udelay(1); 3258 3259 if (phy->autoneg_wait_to_complete) { 3260 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); 3261 3262 ret_val = e1000e_phy_has_link_generic(hw, 3263 PHY_FORCE_LIMIT, 3264 100000, 3265 &link); 3266 if (ret_val) 3267 goto out; 3268 3269 if (!link) 3270 e_dbg("Link taking longer than expected.\n"); 3271 3272 /* Try once more */ 3273 ret_val = e1000e_phy_has_link_generic(hw, 3274 PHY_FORCE_LIMIT, 3275 100000, 3276 &link); 3277 if (ret_val) 3278 goto out; 3279 } 3280 3281 out: 3282 return ret_val; 3283 } 3284 3285 /** 3286 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3287 * @hw: pointer to the HW structure 3288 * 3289 * Read PHY status to determine if link is up. If link is up, then 3290 * set/determine 10base-T extended distance and polarity correction. Read 3291 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3292 * determine on the cable length, local and remote receiver. 3293 **/ 3294 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3295 { 3296 struct e1000_phy_info *phy = &hw->phy; 3297 s32 ret_val; 3298 u16 data; 3299 bool link; 3300 3301 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3302 if (ret_val) 3303 goto out; 3304 3305 if (!link) { 3306 e_dbg("Phy info is only valid if link is up\n"); 3307 ret_val = -E1000_ERR_CONFIG; 3308 goto out; 3309 } 3310 3311 phy->polarity_correction = true; 3312 3313 ret_val = e1000_check_polarity_82577(hw); 3314 if (ret_val) 3315 goto out; 3316 3317 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3318 if (ret_val) 3319 goto out; 3320 3321 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; 3322 3323 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3324 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3325 ret_val = hw->phy.ops.get_cable_length(hw); 3326 if (ret_val) 3327 goto out; 3328 3329 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 3330 if (ret_val) 3331 goto out; 3332 3333 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3334 ? e1000_1000t_rx_status_ok 3335 : e1000_1000t_rx_status_not_ok; 3336 3337 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3338 ? e1000_1000t_rx_status_ok 3339 : e1000_1000t_rx_status_not_ok; 3340 } else { 3341 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3342 phy->local_rx = e1000_1000t_rx_status_undefined; 3343 phy->remote_rx = e1000_1000t_rx_status_undefined; 3344 } 3345 3346 out: 3347 return ret_val; 3348 } 3349 3350 /** 3351 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3352 * @hw: pointer to the HW structure 3353 * 3354 * Reads the diagnostic status register and verifies result is valid before 3355 * placing it in the phy_cable_length field. 3356 **/ 3357 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3358 { 3359 struct e1000_phy_info *phy = &hw->phy; 3360 s32 ret_val; 3361 u16 phy_data, length; 3362 3363 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3364 if (ret_val) 3365 goto out; 3366 3367 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3368 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3369 3370 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3371 ret_val = -E1000_ERR_PHY; 3372 3373 phy->cable_length = length; 3374 3375 out: 3376 return ret_val; 3377 } 3378