1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "e1000.h" 30 31 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 33 u16 *data, bool read, bool page_set); 34 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 35 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 36 u16 *data, bool read); 37 38 /* Cable length tables */ 39 static const u16 e1000_m88_cable_length_table[] = { 40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED 41 }; 42 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 ARRAY_SIZE(e1000_m88_cable_length_table) 45 46 static const u16 e1000_igp_2_cable_length_table[] = { 47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 48 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 49 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 50 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 51 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 52 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 53 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 54 124 55 }; 56 57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 58 ARRAY_SIZE(e1000_igp_2_cable_length_table) 59 60 /** 61 * e1000e_check_reset_block_generic - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = er32(MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 75 } 76 77 /** 78 * e1000e_get_phy_id - Retrieve the PHY ID and revision 79 * @hw: pointer to the HW structure 80 * 81 * Reads the PHY registers and stores the PHY ID and possibly the PHY 82 * revision in the hardware structure. 83 **/ 84 s32 e1000e_get_phy_id(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = 0; 88 u16 phy_id; 89 u16 retry_count = 0; 90 91 if (!phy->ops.read_reg) 92 return 0; 93 94 while (retry_count < 2) { 95 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); 96 if (ret_val) 97 return ret_val; 98 99 phy->id = (u32)(phy_id << 16); 100 usleep_range(20, 40); 101 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); 102 if (ret_val) 103 return ret_val; 104 105 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 106 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 107 108 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 109 return 0; 110 111 retry_count++; 112 } 113 114 return 0; 115 } 116 117 /** 118 * e1000e_phy_reset_dsp - Reset PHY DSP 119 * @hw: pointer to the HW structure 120 * 121 * Reset the digital signal processor. 122 **/ 123 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) 124 { 125 s32 ret_val; 126 127 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 128 if (ret_val) 129 return ret_val; 130 131 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 132 } 133 134 /** 135 * e1000e_read_phy_reg_mdic - Read MDI control register 136 * @hw: pointer to the HW structure 137 * @offset: register offset to be read 138 * @data: pointer to the read data 139 * 140 * Reads the MDI control register in the PHY at offset and stores the 141 * information read to data. 142 **/ 143 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 144 { 145 struct e1000_phy_info *phy = &hw->phy; 146 u32 i, mdic = 0; 147 148 if (offset > MAX_PHY_REG_ADDRESS) { 149 e_dbg("PHY Address %d is out of range\n", offset); 150 return -E1000_ERR_PARAM; 151 } 152 153 /* Set up Op-code, Phy Address, and register offset in the MDI 154 * Control register. The MAC will take care of interfacing with the 155 * PHY to retrieve the desired data. 156 */ 157 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 158 (phy->addr << E1000_MDIC_PHY_SHIFT) | 159 (E1000_MDIC_OP_READ)); 160 161 ew32(MDIC, mdic); 162 163 /* Poll the ready bit to see if the MDI read completed 164 * Increasing the time out as testing showed failures with 165 * the lower time out 166 */ 167 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 168 udelay(50); 169 mdic = er32(MDIC); 170 if (mdic & E1000_MDIC_READY) 171 break; 172 } 173 if (!(mdic & E1000_MDIC_READY)) { 174 e_dbg("MDI Read did not complete\n"); 175 return -E1000_ERR_PHY; 176 } 177 if (mdic & E1000_MDIC_ERROR) { 178 e_dbg("MDI Error\n"); 179 return -E1000_ERR_PHY; 180 } 181 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 182 e_dbg("MDI Read offset error - requested %d, returned %d\n", 183 offset, 184 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 185 return -E1000_ERR_PHY; 186 } 187 *data = (u16)mdic; 188 189 /* Allow some time after each MDIC transaction to avoid 190 * reading duplicate data in the next MDIC transaction. 191 */ 192 if (hw->mac.type == e1000_pch2lan) 193 udelay(100); 194 195 return 0; 196 } 197 198 /** 199 * e1000e_write_phy_reg_mdic - Write MDI control register 200 * @hw: pointer to the HW structure 201 * @offset: register offset to write to 202 * @data: data to write to register at offset 203 * 204 * Writes data to MDI control register in the PHY at offset. 205 **/ 206 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 207 { 208 struct e1000_phy_info *phy = &hw->phy; 209 u32 i, mdic = 0; 210 211 if (offset > MAX_PHY_REG_ADDRESS) { 212 e_dbg("PHY Address %d is out of range\n", offset); 213 return -E1000_ERR_PARAM; 214 } 215 216 /* Set up Op-code, Phy Address, and register offset in the MDI 217 * Control register. The MAC will take care of interfacing with the 218 * PHY to retrieve the desired data. 219 */ 220 mdic = (((u32)data) | 221 (offset << E1000_MDIC_REG_SHIFT) | 222 (phy->addr << E1000_MDIC_PHY_SHIFT) | 223 (E1000_MDIC_OP_WRITE)); 224 225 ew32(MDIC, mdic); 226 227 /* Poll the ready bit to see if the MDI read completed 228 * Increasing the time out as testing showed failures with 229 * the lower time out 230 */ 231 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 232 udelay(50); 233 mdic = er32(MDIC); 234 if (mdic & E1000_MDIC_READY) 235 break; 236 } 237 if (!(mdic & E1000_MDIC_READY)) { 238 e_dbg("MDI Write did not complete\n"); 239 return -E1000_ERR_PHY; 240 } 241 if (mdic & E1000_MDIC_ERROR) { 242 e_dbg("MDI Error\n"); 243 return -E1000_ERR_PHY; 244 } 245 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 246 e_dbg("MDI Write offset error - requested %d, returned %d\n", 247 offset, 248 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 249 return -E1000_ERR_PHY; 250 } 251 252 /* Allow some time after each MDIC transaction to avoid 253 * reading duplicate data in the next MDIC transaction. 254 */ 255 if (hw->mac.type == e1000_pch2lan) 256 udelay(100); 257 258 return 0; 259 } 260 261 /** 262 * e1000e_read_phy_reg_m88 - Read m88 PHY register 263 * @hw: pointer to the HW structure 264 * @offset: register offset to be read 265 * @data: pointer to the read data 266 * 267 * Acquires semaphore, if necessary, then reads the PHY register at offset 268 * and storing the retrieved information in data. Release any acquired 269 * semaphores before exiting. 270 **/ 271 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 272 { 273 s32 ret_val; 274 275 ret_val = hw->phy.ops.acquire(hw); 276 if (ret_val) 277 return ret_val; 278 279 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 280 data); 281 282 hw->phy.ops.release(hw); 283 284 return ret_val; 285 } 286 287 /** 288 * e1000e_write_phy_reg_m88 - Write m88 PHY register 289 * @hw: pointer to the HW structure 290 * @offset: register offset to write to 291 * @data: data to write at register offset 292 * 293 * Acquires semaphore, if necessary, then writes the data to PHY register 294 * at the offset. Release any acquired semaphores before exiting. 295 **/ 296 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 297 { 298 s32 ret_val; 299 300 ret_val = hw->phy.ops.acquire(hw); 301 if (ret_val) 302 return ret_val; 303 304 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 305 data); 306 307 hw->phy.ops.release(hw); 308 309 return ret_val; 310 } 311 312 /** 313 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 314 * @hw: pointer to the HW structure 315 * @page: page to set (shifted left when necessary) 316 * 317 * Sets PHY page required for PHY register access. Assumes semaphore is 318 * already acquired. Note, this function sets phy.addr to 1 so the caller 319 * must set it appropriately (if necessary) after this function returns. 320 **/ 321 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 322 { 323 e_dbg("Setting page 0x%x\n", page); 324 325 hw->phy.addr = 1; 326 327 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 328 } 329 330 /** 331 * __e1000e_read_phy_reg_igp - Read igp PHY register 332 * @hw: pointer to the HW structure 333 * @offset: register offset to be read 334 * @data: pointer to the read data 335 * @locked: semaphore has already been acquired or not 336 * 337 * Acquires semaphore, if necessary, then reads the PHY register at offset 338 * and stores the retrieved information in data. Release any acquired 339 * semaphores before exiting. 340 **/ 341 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 342 bool locked) 343 { 344 s32 ret_val = 0; 345 346 if (!locked) { 347 if (!hw->phy.ops.acquire) 348 return 0; 349 350 ret_val = hw->phy.ops.acquire(hw); 351 if (ret_val) 352 return ret_val; 353 } 354 355 if (offset > MAX_PHY_MULTI_PAGE_REG) 356 ret_val = e1000e_write_phy_reg_mdic(hw, 357 IGP01E1000_PHY_PAGE_SELECT, 358 (u16)offset); 359 if (!ret_val) 360 ret_val = e1000e_read_phy_reg_mdic(hw, 361 MAX_PHY_REG_ADDRESS & offset, 362 data); 363 if (!locked) 364 hw->phy.ops.release(hw); 365 366 return ret_val; 367 } 368 369 /** 370 * e1000e_read_phy_reg_igp - Read igp PHY register 371 * @hw: pointer to the HW structure 372 * @offset: register offset to be read 373 * @data: pointer to the read data 374 * 375 * Acquires semaphore then reads the PHY register at offset and stores the 376 * retrieved information in data. 377 * Release the acquired semaphore before exiting. 378 **/ 379 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 380 { 381 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 382 } 383 384 /** 385 * e1000e_read_phy_reg_igp_locked - Read igp PHY register 386 * @hw: pointer to the HW structure 387 * @offset: register offset to be read 388 * @data: pointer to the read data 389 * 390 * Reads the PHY register at offset and stores the retrieved information 391 * in data. Assumes semaphore already acquired. 392 **/ 393 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 394 { 395 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 396 } 397 398 /** 399 * e1000e_write_phy_reg_igp - Write igp PHY register 400 * @hw: pointer to the HW structure 401 * @offset: register offset to write to 402 * @data: data to write at register offset 403 * @locked: semaphore has already been acquired or not 404 * 405 * Acquires semaphore, if necessary, then writes the data to PHY register 406 * at the offset. Release any acquired semaphores before exiting. 407 **/ 408 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 409 bool locked) 410 { 411 s32 ret_val = 0; 412 413 if (!locked) { 414 if (!hw->phy.ops.acquire) 415 return 0; 416 417 ret_val = hw->phy.ops.acquire(hw); 418 if (ret_val) 419 return ret_val; 420 } 421 422 if (offset > MAX_PHY_MULTI_PAGE_REG) 423 ret_val = e1000e_write_phy_reg_mdic(hw, 424 IGP01E1000_PHY_PAGE_SELECT, 425 (u16)offset); 426 if (!ret_val) 427 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 428 offset, data); 429 if (!locked) 430 hw->phy.ops.release(hw); 431 432 return ret_val; 433 } 434 435 /** 436 * e1000e_write_phy_reg_igp - Write igp PHY register 437 * @hw: pointer to the HW structure 438 * @offset: register offset to write to 439 * @data: data to write at register offset 440 * 441 * Acquires semaphore then writes the data to PHY register 442 * at the offset. Release any acquired semaphores before exiting. 443 **/ 444 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 445 { 446 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 447 } 448 449 /** 450 * e1000e_write_phy_reg_igp_locked - Write igp PHY register 451 * @hw: pointer to the HW structure 452 * @offset: register offset to write to 453 * @data: data to write at register offset 454 * 455 * Writes the data to PHY register at the offset. 456 * Assumes semaphore already acquired. 457 **/ 458 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 459 { 460 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 461 } 462 463 /** 464 * __e1000_read_kmrn_reg - Read kumeran register 465 * @hw: pointer to the HW structure 466 * @offset: register offset to be read 467 * @data: pointer to the read data 468 * @locked: semaphore has already been acquired or not 469 * 470 * Acquires semaphore, if necessary. Then reads the PHY register at offset 471 * using the kumeran interface. The information retrieved is stored in data. 472 * Release any acquired semaphores before exiting. 473 **/ 474 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 475 bool locked) 476 { 477 u32 kmrnctrlsta; 478 479 if (!locked) { 480 s32 ret_val = 0; 481 482 if (!hw->phy.ops.acquire) 483 return 0; 484 485 ret_val = hw->phy.ops.acquire(hw); 486 if (ret_val) 487 return ret_val; 488 } 489 490 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 491 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 492 ew32(KMRNCTRLSTA, kmrnctrlsta); 493 e1e_flush(); 494 495 udelay(2); 496 497 kmrnctrlsta = er32(KMRNCTRLSTA); 498 *data = (u16)kmrnctrlsta; 499 500 if (!locked) 501 hw->phy.ops.release(hw); 502 503 return 0; 504 } 505 506 /** 507 * e1000e_read_kmrn_reg - Read kumeran register 508 * @hw: pointer to the HW structure 509 * @offset: register offset to be read 510 * @data: pointer to the read data 511 * 512 * Acquires semaphore then reads the PHY register at offset using the 513 * kumeran interface. The information retrieved is stored in data. 514 * Release the acquired semaphore before exiting. 515 **/ 516 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) 517 { 518 return __e1000_read_kmrn_reg(hw, offset, data, false); 519 } 520 521 /** 522 * e1000e_read_kmrn_reg_locked - Read kumeran register 523 * @hw: pointer to the HW structure 524 * @offset: register offset to be read 525 * @data: pointer to the read data 526 * 527 * Reads the PHY register at offset using the kumeran interface. The 528 * information retrieved is stored in data. 529 * Assumes semaphore already acquired. 530 **/ 531 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 532 { 533 return __e1000_read_kmrn_reg(hw, offset, data, true); 534 } 535 536 /** 537 * __e1000_write_kmrn_reg - Write kumeran register 538 * @hw: pointer to the HW structure 539 * @offset: register offset to write to 540 * @data: data to write at register offset 541 * @locked: semaphore has already been acquired or not 542 * 543 * Acquires semaphore, if necessary. Then write the data to PHY register 544 * at the offset using the kumeran interface. Release any acquired semaphores 545 * before exiting. 546 **/ 547 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 548 bool locked) 549 { 550 u32 kmrnctrlsta; 551 552 if (!locked) { 553 s32 ret_val = 0; 554 555 if (!hw->phy.ops.acquire) 556 return 0; 557 558 ret_val = hw->phy.ops.acquire(hw); 559 if (ret_val) 560 return ret_val; 561 } 562 563 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 564 E1000_KMRNCTRLSTA_OFFSET) | data; 565 ew32(KMRNCTRLSTA, kmrnctrlsta); 566 e1e_flush(); 567 568 udelay(2); 569 570 if (!locked) 571 hw->phy.ops.release(hw); 572 573 return 0; 574 } 575 576 /** 577 * e1000e_write_kmrn_reg - Write kumeran register 578 * @hw: pointer to the HW structure 579 * @offset: register offset to write to 580 * @data: data to write at register offset 581 * 582 * Acquires semaphore then writes the data to the PHY register at the offset 583 * using the kumeran interface. Release the acquired semaphore before exiting. 584 **/ 585 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) 586 { 587 return __e1000_write_kmrn_reg(hw, offset, data, false); 588 } 589 590 /** 591 * e1000e_write_kmrn_reg_locked - Write kumeran register 592 * @hw: pointer to the HW structure 593 * @offset: register offset to write to 594 * @data: data to write at register offset 595 * 596 * Write the data to PHY register at the offset using the kumeran interface. 597 * Assumes semaphore already acquired. 598 **/ 599 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 600 { 601 return __e1000_write_kmrn_reg(hw, offset, data, true); 602 } 603 604 /** 605 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 606 * @hw: pointer to the HW structure 607 * 608 * Sets up Master/slave mode 609 **/ 610 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 611 { 612 s32 ret_val; 613 u16 phy_data; 614 615 /* Resolve Master/Slave mode */ 616 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); 617 if (ret_val) 618 return ret_val; 619 620 /* load defaults for future use */ 621 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? 622 ((phy_data & CTL1000_AS_MASTER) ? 623 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; 624 625 switch (hw->phy.ms_type) { 626 case e1000_ms_force_master: 627 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 628 break; 629 case e1000_ms_force_slave: 630 phy_data |= CTL1000_ENABLE_MASTER; 631 phy_data &= ~(CTL1000_AS_MASTER); 632 break; 633 case e1000_ms_auto: 634 phy_data &= ~CTL1000_ENABLE_MASTER; 635 /* fall-through */ 636 default: 637 break; 638 } 639 640 return e1e_wphy(hw, MII_CTRL1000, phy_data); 641 } 642 643 /** 644 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 645 * @hw: pointer to the HW structure 646 * 647 * Sets up Carrier-sense on Transmit and downshift values. 648 **/ 649 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 650 { 651 s32 ret_val; 652 u16 phy_data; 653 654 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 655 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 656 if (ret_val) 657 return ret_val; 658 659 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 660 661 /* Enable downshift */ 662 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 663 664 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 665 if (ret_val) 666 return ret_val; 667 668 /* Set MDI/MDIX mode */ 669 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); 670 if (ret_val) 671 return ret_val; 672 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 673 /* Options: 674 * 0 - Auto (default) 675 * 1 - MDI mode 676 * 2 - MDI-X mode 677 */ 678 switch (hw->phy.mdix) { 679 case 1: 680 break; 681 case 2: 682 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 683 break; 684 case 0: 685 default: 686 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 687 break; 688 } 689 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); 690 if (ret_val) 691 return ret_val; 692 693 return e1000_set_master_slave_mode(hw); 694 } 695 696 /** 697 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link 698 * @hw: pointer to the HW structure 699 * 700 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 701 * and downshift values are set also. 702 **/ 703 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) 704 { 705 struct e1000_phy_info *phy = &hw->phy; 706 s32 ret_val; 707 u16 phy_data; 708 709 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 710 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 711 if (ret_val) 712 return ret_val; 713 714 /* For BM PHY this bit is downshift enable */ 715 if (phy->type != e1000_phy_bm) 716 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 717 718 /* Options: 719 * MDI/MDI-X = 0 (default) 720 * 0 - Auto for all speeds 721 * 1 - MDI mode 722 * 2 - MDI-X mode 723 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 724 */ 725 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 726 727 switch (phy->mdix) { 728 case 1: 729 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 730 break; 731 case 2: 732 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 733 break; 734 case 3: 735 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 736 break; 737 case 0: 738 default: 739 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 740 break; 741 } 742 743 /* Options: 744 * disable_polarity_correction = 0 (default) 745 * Automatic Correction for Reversed Cable Polarity 746 * 0 - Disabled 747 * 1 - Enabled 748 */ 749 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 750 if (phy->disable_polarity_correction) 751 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 752 753 /* Enable downshift on BM (disabled by default) */ 754 if (phy->type == e1000_phy_bm) { 755 /* For 82574/82583, first disable then enable downshift */ 756 if (phy->id == BME1000_E_PHY_ID_R2) { 757 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 758 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 759 phy_data); 760 if (ret_val) 761 return ret_val; 762 /* Commit the changes. */ 763 ret_val = phy->ops.commit(hw); 764 if (ret_val) { 765 e_dbg("Error committing the PHY changes\n"); 766 return ret_val; 767 } 768 } 769 770 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 771 } 772 773 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 774 if (ret_val) 775 return ret_val; 776 777 if ((phy->type == e1000_phy_m88) && 778 (phy->revision < E1000_REVISION_4) && 779 (phy->id != BME1000_E_PHY_ID_R2)) { 780 /* Force TX_CLK in the Extended PHY Specific Control Register 781 * to 25MHz clock. 782 */ 783 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 784 if (ret_val) 785 return ret_val; 786 787 phy_data |= M88E1000_EPSCR_TX_CLK_25; 788 789 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) { 790 /* 82573L PHY - set the downshift counter to 5x. */ 791 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 792 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 793 } else { 794 /* Configure Master and Slave downshift values */ 795 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 796 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 797 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 798 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 799 } 800 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 801 if (ret_val) 802 return ret_val; 803 } 804 805 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 806 /* Set PHY page 0, register 29 to 0x0003 */ 807 ret_val = e1e_wphy(hw, 29, 0x0003); 808 if (ret_val) 809 return ret_val; 810 811 /* Set PHY page 0, register 30 to 0x0000 */ 812 ret_val = e1e_wphy(hw, 30, 0x0000); 813 if (ret_val) 814 return ret_val; 815 } 816 817 /* Commit the changes. */ 818 if (phy->ops.commit) { 819 ret_val = phy->ops.commit(hw); 820 if (ret_val) { 821 e_dbg("Error committing the PHY changes\n"); 822 return ret_val; 823 } 824 } 825 826 if (phy->type == e1000_phy_82578) { 827 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 828 if (ret_val) 829 return ret_val; 830 831 /* 82578 PHY - set the downshift count to 1x. */ 832 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 833 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 834 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 835 if (ret_val) 836 return ret_val; 837 } 838 839 return 0; 840 } 841 842 /** 843 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link 844 * @hw: pointer to the HW structure 845 * 846 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 847 * igp PHY's. 848 **/ 849 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) 850 { 851 struct e1000_phy_info *phy = &hw->phy; 852 s32 ret_val; 853 u16 data; 854 855 ret_val = e1000_phy_hw_reset(hw); 856 if (ret_val) { 857 e_dbg("Error resetting the PHY.\n"); 858 return ret_val; 859 } 860 861 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 862 * timeout issues when LFS is enabled. 863 */ 864 msleep(100); 865 866 /* disable lplu d0 during driver init */ 867 if (hw->phy.ops.set_d0_lplu_state) { 868 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 869 if (ret_val) { 870 e_dbg("Error Disabling LPLU D0\n"); 871 return ret_val; 872 } 873 } 874 /* Configure mdi-mdix settings */ 875 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 876 if (ret_val) 877 return ret_val; 878 879 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 880 881 switch (phy->mdix) { 882 case 1: 883 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 884 break; 885 case 2: 886 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 887 break; 888 case 0: 889 default: 890 data |= IGP01E1000_PSCR_AUTO_MDIX; 891 break; 892 } 893 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 894 if (ret_val) 895 return ret_val; 896 897 /* set auto-master slave resolution settings */ 898 if (hw->mac.autoneg) { 899 /* when autonegotiation advertisement is only 1000Mbps then we 900 * should disable SmartSpeed and enable Auto MasterSlave 901 * resolution as hardware default. 902 */ 903 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 904 /* Disable SmartSpeed */ 905 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 906 &data); 907 if (ret_val) 908 return ret_val; 909 910 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 911 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 912 data); 913 if (ret_val) 914 return ret_val; 915 916 /* Set auto Master/Slave resolution process */ 917 ret_val = e1e_rphy(hw, MII_CTRL1000, &data); 918 if (ret_val) 919 return ret_val; 920 921 data &= ~CTL1000_ENABLE_MASTER; 922 ret_val = e1e_wphy(hw, MII_CTRL1000, data); 923 if (ret_val) 924 return ret_val; 925 } 926 927 ret_val = e1000_set_master_slave_mode(hw); 928 } 929 930 return ret_val; 931 } 932 933 /** 934 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 935 * @hw: pointer to the HW structure 936 * 937 * Reads the MII auto-neg advertisement register and/or the 1000T control 938 * register and if the PHY is already setup for auto-negotiation, then 939 * return successful. Otherwise, setup advertisement and flow control to 940 * the appropriate values for the wanted auto-negotiation. 941 **/ 942 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 943 { 944 struct e1000_phy_info *phy = &hw->phy; 945 s32 ret_val; 946 u16 mii_autoneg_adv_reg; 947 u16 mii_1000t_ctrl_reg = 0; 948 949 phy->autoneg_advertised &= phy->autoneg_mask; 950 951 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 952 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); 953 if (ret_val) 954 return ret_val; 955 956 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 957 /* Read the MII 1000Base-T Control Register (Address 9). */ 958 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); 959 if (ret_val) 960 return ret_val; 961 } 962 963 /* Need to parse both autoneg_advertised and fc and set up 964 * the appropriate PHY registers. First we will parse for 965 * autoneg_advertised software override. Since we can advertise 966 * a plethora of combinations, we need to check each bit 967 * individually. 968 */ 969 970 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 971 * Advertisement Register (Address 4) and the 1000 mb speed bits in 972 * the 1000Base-T Control Register (Address 9). 973 */ 974 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | 975 ADVERTISE_100HALF | 976 ADVERTISE_10FULL | ADVERTISE_10HALF); 977 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); 978 979 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 980 981 /* Do we want to advertise 10 Mb Half Duplex? */ 982 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 983 e_dbg("Advertise 10mb Half duplex\n"); 984 mii_autoneg_adv_reg |= ADVERTISE_10HALF; 985 } 986 987 /* Do we want to advertise 10 Mb Full Duplex? */ 988 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 989 e_dbg("Advertise 10mb Full duplex\n"); 990 mii_autoneg_adv_reg |= ADVERTISE_10FULL; 991 } 992 993 /* Do we want to advertise 100 Mb Half Duplex? */ 994 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 995 e_dbg("Advertise 100mb Half duplex\n"); 996 mii_autoneg_adv_reg |= ADVERTISE_100HALF; 997 } 998 999 /* Do we want to advertise 100 Mb Full Duplex? */ 1000 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1001 e_dbg("Advertise 100mb Full duplex\n"); 1002 mii_autoneg_adv_reg |= ADVERTISE_100FULL; 1003 } 1004 1005 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1006 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1007 e_dbg("Advertise 1000mb Half duplex request denied!\n"); 1008 1009 /* Do we want to advertise 1000 Mb Full Duplex? */ 1010 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1011 e_dbg("Advertise 1000mb Full duplex\n"); 1012 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; 1013 } 1014 1015 /* Check for a software override of the flow control settings, and 1016 * setup the PHY advertisement registers accordingly. If 1017 * auto-negotiation is enabled, then software will have to set the 1018 * "PAUSE" bits to the correct value in the Auto-Negotiation 1019 * Advertisement Register (MII_ADVERTISE) and re-start auto- 1020 * negotiation. 1021 * 1022 * The possible values of the "fc" parameter are: 1023 * 0: Flow control is completely disabled 1024 * 1: Rx flow control is enabled (we can receive pause frames 1025 * but not send pause frames). 1026 * 2: Tx flow control is enabled (we can send pause frames 1027 * but we do not support receiving pause frames). 1028 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1029 * other: No software override. The flow control configuration 1030 * in the EEPROM is used. 1031 */ 1032 switch (hw->fc.current_mode) { 1033 case e1000_fc_none: 1034 /* Flow control (Rx & Tx) is completely disabled by a 1035 * software over-ride. 1036 */ 1037 mii_autoneg_adv_reg &= 1038 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1039 break; 1040 case e1000_fc_rx_pause: 1041 /* Rx Flow control is enabled, and Tx Flow control is 1042 * disabled, by a software over-ride. 1043 * 1044 * Since there really isn't a way to advertise that we are 1045 * capable of Rx Pause ONLY, we will advertise that we 1046 * support both symmetric and asymmetric Rx PAUSE. Later 1047 * (in e1000e_config_fc_after_link_up) we will disable the 1048 * hw's ability to send PAUSE frames. 1049 */ 1050 mii_autoneg_adv_reg |= 1051 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1052 break; 1053 case e1000_fc_tx_pause: 1054 /* Tx Flow control is enabled, and Rx Flow control is 1055 * disabled, by a software over-ride. 1056 */ 1057 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; 1058 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; 1059 break; 1060 case e1000_fc_full: 1061 /* Flow control (both Rx and Tx) is enabled by a software 1062 * over-ride. 1063 */ 1064 mii_autoneg_adv_reg |= 1065 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 1066 break; 1067 default: 1068 e_dbg("Flow control param set incorrectly\n"); 1069 return -E1000_ERR_CONFIG; 1070 } 1071 1072 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 1073 if (ret_val) 1074 return ret_val; 1075 1076 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1077 1078 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1079 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); 1080 1081 return ret_val; 1082 } 1083 1084 /** 1085 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1086 * @hw: pointer to the HW structure 1087 * 1088 * Performs initial bounds checking on autoneg advertisement parameter, then 1089 * configure to advertise the full capability. Setup the PHY to autoneg 1090 * and restart the negotiation process between the link partner. If 1091 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1092 **/ 1093 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1094 { 1095 struct e1000_phy_info *phy = &hw->phy; 1096 s32 ret_val; 1097 u16 phy_ctrl; 1098 1099 /* Perform some bounds checking on the autoneg advertisement 1100 * parameter. 1101 */ 1102 phy->autoneg_advertised &= phy->autoneg_mask; 1103 1104 /* If autoneg_advertised is zero, we assume it was not defaulted 1105 * by the calling code so we set to advertise full capability. 1106 */ 1107 if (!phy->autoneg_advertised) 1108 phy->autoneg_advertised = phy->autoneg_mask; 1109 1110 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1111 ret_val = e1000_phy_setup_autoneg(hw); 1112 if (ret_val) { 1113 e_dbg("Error Setting up Auto-Negotiation\n"); 1114 return ret_val; 1115 } 1116 e_dbg("Restarting Auto-Neg\n"); 1117 1118 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1119 * the Auto Neg Restart bit in the PHY control register. 1120 */ 1121 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); 1122 if (ret_val) 1123 return ret_val; 1124 1125 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); 1126 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); 1127 if (ret_val) 1128 return ret_val; 1129 1130 /* Does the user want to wait for Auto-Neg to complete here, or 1131 * check at a later time (for example, callback routine). 1132 */ 1133 if (phy->autoneg_wait_to_complete) { 1134 ret_val = e1000_wait_autoneg(hw); 1135 if (ret_val) { 1136 e_dbg("Error while waiting for autoneg to complete\n"); 1137 return ret_val; 1138 } 1139 } 1140 1141 hw->mac.get_link_status = true; 1142 1143 return ret_val; 1144 } 1145 1146 /** 1147 * e1000e_setup_copper_link - Configure copper link settings 1148 * @hw: pointer to the HW structure 1149 * 1150 * Calls the appropriate function to configure the link for auto-neg or forced 1151 * speed and duplex. Then we check for link, once link is established calls 1152 * to configure collision distance and flow control are called. If link is 1153 * not established, we return -E1000_ERR_PHY (-2). 1154 **/ 1155 s32 e1000e_setup_copper_link(struct e1000_hw *hw) 1156 { 1157 s32 ret_val; 1158 bool link; 1159 1160 if (hw->mac.autoneg) { 1161 /* Setup autoneg and flow control advertisement and perform 1162 * autonegotiation. 1163 */ 1164 ret_val = e1000_copper_link_autoneg(hw); 1165 if (ret_val) 1166 return ret_val; 1167 } else { 1168 /* PHY will be set to 10H, 10F, 100H or 100F 1169 * depending on user settings. 1170 */ 1171 e_dbg("Forcing Speed and Duplex\n"); 1172 ret_val = hw->phy.ops.force_speed_duplex(hw); 1173 if (ret_val) { 1174 e_dbg("Error Forcing Speed and Duplex\n"); 1175 return ret_val; 1176 } 1177 } 1178 1179 /* Check link status. Wait up to 100 microseconds for link to become 1180 * valid. 1181 */ 1182 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1183 &link); 1184 if (ret_val) 1185 return ret_val; 1186 1187 if (link) { 1188 e_dbg("Valid link established!!!\n"); 1189 hw->mac.ops.config_collision_dist(hw); 1190 ret_val = e1000e_config_fc_after_link_up(hw); 1191 } else { 1192 e_dbg("Unable to establish link!!!\n"); 1193 } 1194 1195 return ret_val; 1196 } 1197 1198 /** 1199 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1200 * @hw: pointer to the HW structure 1201 * 1202 * Calls the PHY setup function to force speed and duplex. Clears the 1203 * auto-crossover to force MDI manually. Waits for link and returns 1204 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1205 **/ 1206 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1207 { 1208 struct e1000_phy_info *phy = &hw->phy; 1209 s32 ret_val; 1210 u16 phy_data; 1211 bool link; 1212 1213 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 1214 if (ret_val) 1215 return ret_val; 1216 1217 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1218 1219 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 1220 if (ret_val) 1221 return ret_val; 1222 1223 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1224 * forced whenever speed and duplex are forced. 1225 */ 1226 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1227 if (ret_val) 1228 return ret_val; 1229 1230 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1231 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1232 1233 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1234 if (ret_val) 1235 return ret_val; 1236 1237 e_dbg("IGP PSCR: %X\n", phy_data); 1238 1239 udelay(1); 1240 1241 if (phy->autoneg_wait_to_complete) { 1242 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1243 1244 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1245 100000, &link); 1246 if (ret_val) 1247 return ret_val; 1248 1249 if (!link) 1250 e_dbg("Link taking longer than expected.\n"); 1251 1252 /* Try once more */ 1253 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1254 100000, &link); 1255 } 1256 1257 return ret_val; 1258 } 1259 1260 /** 1261 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1262 * @hw: pointer to the HW structure 1263 * 1264 * Calls the PHY setup function to force speed and duplex. Clears the 1265 * auto-crossover to force MDI manually. Resets the PHY to commit the 1266 * changes. If time expires while waiting for link up, we reset the DSP. 1267 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1268 * successful completion, else return corresponding error code. 1269 **/ 1270 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1271 { 1272 struct e1000_phy_info *phy = &hw->phy; 1273 s32 ret_val; 1274 u16 phy_data; 1275 bool link; 1276 1277 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1278 * forced whenever speed and duplex are forced. 1279 */ 1280 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1281 if (ret_val) 1282 return ret_val; 1283 1284 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1285 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1286 if (ret_val) 1287 return ret_val; 1288 1289 e_dbg("M88E1000 PSCR: %X\n", phy_data); 1290 1291 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 1292 if (ret_val) 1293 return ret_val; 1294 1295 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 1296 1297 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 1298 if (ret_val) 1299 return ret_val; 1300 1301 /* Reset the phy to commit changes. */ 1302 if (hw->phy.ops.commit) { 1303 ret_val = hw->phy.ops.commit(hw); 1304 if (ret_val) 1305 return ret_val; 1306 } 1307 1308 if (phy->autoneg_wait_to_complete) { 1309 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1310 1311 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1312 100000, &link); 1313 if (ret_val) 1314 return ret_val; 1315 1316 if (!link) { 1317 if (hw->phy.type != e1000_phy_m88) { 1318 e_dbg("Link taking longer than expected.\n"); 1319 } else { 1320 /* We didn't get link. 1321 * Reset the DSP and cross our fingers. 1322 */ 1323 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1324 0x001d); 1325 if (ret_val) 1326 return ret_val; 1327 ret_val = e1000e_phy_reset_dsp(hw); 1328 if (ret_val) 1329 return ret_val; 1330 } 1331 } 1332 1333 /* Try once more */ 1334 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1335 100000, &link); 1336 if (ret_val) 1337 return ret_val; 1338 } 1339 1340 if (hw->phy.type != e1000_phy_m88) 1341 return 0; 1342 1343 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1344 if (ret_val) 1345 return ret_val; 1346 1347 /* Resetting the phy means we need to re-force TX_CLK in the 1348 * Extended PHY Specific Control Register to 25MHz clock from 1349 * the reset value of 2.5MHz. 1350 */ 1351 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1352 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1353 if (ret_val) 1354 return ret_val; 1355 1356 /* In addition, we must re-enable CRS on Tx for both half and full 1357 * duplex. 1358 */ 1359 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1360 if (ret_val) 1361 return ret_val; 1362 1363 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1364 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1365 1366 return ret_val; 1367 } 1368 1369 /** 1370 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1371 * @hw: pointer to the HW structure 1372 * 1373 * Forces the speed and duplex settings of the PHY. 1374 * This is a function pointer entry point only called by 1375 * PHY setup routines. 1376 **/ 1377 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1378 { 1379 struct e1000_phy_info *phy = &hw->phy; 1380 s32 ret_val; 1381 u16 data; 1382 bool link; 1383 1384 ret_val = e1e_rphy(hw, MII_BMCR, &data); 1385 if (ret_val) 1386 return ret_val; 1387 1388 e1000e_phy_force_speed_duplex_setup(hw, &data); 1389 1390 ret_val = e1e_wphy(hw, MII_BMCR, data); 1391 if (ret_val) 1392 return ret_val; 1393 1394 /* Disable MDI-X support for 10/100 */ 1395 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 1396 if (ret_val) 1397 return ret_val; 1398 1399 data &= ~IFE_PMC_AUTO_MDIX; 1400 data &= ~IFE_PMC_FORCE_MDIX; 1401 1402 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); 1403 if (ret_val) 1404 return ret_val; 1405 1406 e_dbg("IFE PMC: %X\n", data); 1407 1408 udelay(1); 1409 1410 if (phy->autoneg_wait_to_complete) { 1411 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); 1412 1413 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1414 100000, &link); 1415 if (ret_val) 1416 return ret_val; 1417 1418 if (!link) 1419 e_dbg("Link taking longer than expected.\n"); 1420 1421 /* Try once more */ 1422 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1423 100000, &link); 1424 if (ret_val) 1425 return ret_val; 1426 } 1427 1428 return 0; 1429 } 1430 1431 /** 1432 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1433 * @hw: pointer to the HW structure 1434 * @phy_ctrl: pointer to current value of MII_BMCR 1435 * 1436 * Forces speed and duplex on the PHY by doing the following: disable flow 1437 * control, force speed/duplex on the MAC, disable auto speed detection, 1438 * disable auto-negotiation, configure duplex, configure speed, configure 1439 * the collision distance, write configuration to CTRL register. The 1440 * caller must write to the MII_BMCR register for these settings to 1441 * take affect. 1442 **/ 1443 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1444 { 1445 struct e1000_mac_info *mac = &hw->mac; 1446 u32 ctrl; 1447 1448 /* Turn off flow control when forcing speed/duplex */ 1449 hw->fc.current_mode = e1000_fc_none; 1450 1451 /* Force speed/duplex on the mac */ 1452 ctrl = er32(CTRL); 1453 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1454 ctrl &= ~E1000_CTRL_SPD_SEL; 1455 1456 /* Disable Auto Speed Detection */ 1457 ctrl &= ~E1000_CTRL_ASDE; 1458 1459 /* Disable autoneg on the phy */ 1460 *phy_ctrl &= ~BMCR_ANENABLE; 1461 1462 /* Forcing Full or Half Duplex? */ 1463 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1464 ctrl &= ~E1000_CTRL_FD; 1465 *phy_ctrl &= ~BMCR_FULLDPLX; 1466 e_dbg("Half Duplex\n"); 1467 } else { 1468 ctrl |= E1000_CTRL_FD; 1469 *phy_ctrl |= BMCR_FULLDPLX; 1470 e_dbg("Full Duplex\n"); 1471 } 1472 1473 /* Forcing 10mb or 100mb? */ 1474 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1475 ctrl |= E1000_CTRL_SPD_100; 1476 *phy_ctrl |= BMCR_SPEED100; 1477 *phy_ctrl &= ~BMCR_SPEED1000; 1478 e_dbg("Forcing 100mb\n"); 1479 } else { 1480 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1481 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); 1482 e_dbg("Forcing 10mb\n"); 1483 } 1484 1485 hw->mac.ops.config_collision_dist(hw); 1486 1487 ew32(CTRL, ctrl); 1488 } 1489 1490 /** 1491 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 1492 * @hw: pointer to the HW structure 1493 * @active: boolean used to enable/disable lplu 1494 * 1495 * Success returns 0, Failure returns 1 1496 * 1497 * The low power link up (lplu) state is set to the power management level D3 1498 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1499 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1500 * is used during Dx states where the power conservation is most important. 1501 * During driver activity, SmartSpeed should be enabled so performance is 1502 * maintained. 1503 **/ 1504 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1505 { 1506 struct e1000_phy_info *phy = &hw->phy; 1507 s32 ret_val; 1508 u16 data; 1509 1510 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1511 if (ret_val) 1512 return ret_val; 1513 1514 if (!active) { 1515 data &= ~IGP02E1000_PM_D3_LPLU; 1516 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1517 if (ret_val) 1518 return ret_val; 1519 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1520 * during Dx states where the power conservation is most 1521 * important. During driver activity we should enable 1522 * SmartSpeed, so performance is maintained. 1523 */ 1524 if (phy->smart_speed == e1000_smart_speed_on) { 1525 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1526 &data); 1527 if (ret_val) 1528 return ret_val; 1529 1530 data |= IGP01E1000_PSCFR_SMART_SPEED; 1531 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1532 data); 1533 if (ret_val) 1534 return ret_val; 1535 } else if (phy->smart_speed == e1000_smart_speed_off) { 1536 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1537 &data); 1538 if (ret_val) 1539 return ret_val; 1540 1541 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1542 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 1543 data); 1544 if (ret_val) 1545 return ret_val; 1546 } 1547 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1548 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1549 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1550 data |= IGP02E1000_PM_D3_LPLU; 1551 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1552 if (ret_val) 1553 return ret_val; 1554 1555 /* When LPLU is enabled, we should disable SmartSpeed */ 1556 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 1557 if (ret_val) 1558 return ret_val; 1559 1560 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1561 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 1562 } 1563 1564 return ret_val; 1565 } 1566 1567 /** 1568 * e1000e_check_downshift - Checks whether a downshift in speed occurred 1569 * @hw: pointer to the HW structure 1570 * 1571 * Success returns 0, Failure returns 1 1572 * 1573 * A downshift is detected by querying the PHY link health. 1574 **/ 1575 s32 e1000e_check_downshift(struct e1000_hw *hw) 1576 { 1577 struct e1000_phy_info *phy = &hw->phy; 1578 s32 ret_val; 1579 u16 phy_data, offset, mask; 1580 1581 switch (phy->type) { 1582 case e1000_phy_m88: 1583 case e1000_phy_gg82563: 1584 case e1000_phy_bm: 1585 case e1000_phy_82578: 1586 offset = M88E1000_PHY_SPEC_STATUS; 1587 mask = M88E1000_PSSR_DOWNSHIFT; 1588 break; 1589 case e1000_phy_igp_2: 1590 case e1000_phy_igp_3: 1591 offset = IGP01E1000_PHY_LINK_HEALTH; 1592 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1593 break; 1594 default: 1595 /* speed downshift not supported */ 1596 phy->speed_downgraded = false; 1597 return 0; 1598 } 1599 1600 ret_val = e1e_rphy(hw, offset, &phy_data); 1601 1602 if (!ret_val) 1603 phy->speed_downgraded = !!(phy_data & mask); 1604 1605 return ret_val; 1606 } 1607 1608 /** 1609 * e1000_check_polarity_m88 - Checks the polarity. 1610 * @hw: pointer to the HW structure 1611 * 1612 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1613 * 1614 * Polarity is determined based on the PHY specific status register. 1615 **/ 1616 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1617 { 1618 struct e1000_phy_info *phy = &hw->phy; 1619 s32 ret_val; 1620 u16 data; 1621 1622 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 1623 1624 if (!ret_val) 1625 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 1626 ? e1000_rev_polarity_reversed 1627 : e1000_rev_polarity_normal); 1628 1629 return ret_val; 1630 } 1631 1632 /** 1633 * e1000_check_polarity_igp - Checks the polarity. 1634 * @hw: pointer to the HW structure 1635 * 1636 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1637 * 1638 * Polarity is determined based on the PHY port status register, and the 1639 * current speed (since there is no polarity at 100Mbps). 1640 **/ 1641 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1642 { 1643 struct e1000_phy_info *phy = &hw->phy; 1644 s32 ret_val; 1645 u16 data, offset, mask; 1646 1647 /* Polarity is determined based on the speed of 1648 * our connection. 1649 */ 1650 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1651 if (ret_val) 1652 return ret_val; 1653 1654 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1655 IGP01E1000_PSSR_SPEED_1000MBPS) { 1656 offset = IGP01E1000_PHY_PCS_INIT_REG; 1657 mask = IGP01E1000_PHY_POLARITY_MASK; 1658 } else { 1659 /* This really only applies to 10Mbps since 1660 * there is no polarity for 100Mbps (always 0). 1661 */ 1662 offset = IGP01E1000_PHY_PORT_STATUS; 1663 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1664 } 1665 1666 ret_val = e1e_rphy(hw, offset, &data); 1667 1668 if (!ret_val) 1669 phy->cable_polarity = ((data & mask) 1670 ? e1000_rev_polarity_reversed 1671 : e1000_rev_polarity_normal); 1672 1673 return ret_val; 1674 } 1675 1676 /** 1677 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1678 * @hw: pointer to the HW structure 1679 * 1680 * Polarity is determined on the polarity reversal feature being enabled. 1681 **/ 1682 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1683 { 1684 struct e1000_phy_info *phy = &hw->phy; 1685 s32 ret_val; 1686 u16 phy_data, offset, mask; 1687 1688 /* Polarity is determined based on the reversal feature being enabled. 1689 */ 1690 if (phy->polarity_correction) { 1691 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1692 mask = IFE_PESC_POLARITY_REVERSED; 1693 } else { 1694 offset = IFE_PHY_SPECIAL_CONTROL; 1695 mask = IFE_PSC_FORCE_POLARITY; 1696 } 1697 1698 ret_val = e1e_rphy(hw, offset, &phy_data); 1699 1700 if (!ret_val) 1701 phy->cable_polarity = ((phy_data & mask) 1702 ? e1000_rev_polarity_reversed 1703 : e1000_rev_polarity_normal); 1704 1705 return ret_val; 1706 } 1707 1708 /** 1709 * e1000_wait_autoneg - Wait for auto-neg completion 1710 * @hw: pointer to the HW structure 1711 * 1712 * Waits for auto-negotiation to complete or for the auto-negotiation time 1713 * limit to expire, which ever happens first. 1714 **/ 1715 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 1716 { 1717 s32 ret_val = 0; 1718 u16 i, phy_status; 1719 1720 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1721 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1722 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1723 if (ret_val) 1724 break; 1725 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1726 if (ret_val) 1727 break; 1728 if (phy_status & BMSR_ANEGCOMPLETE) 1729 break; 1730 msleep(100); 1731 } 1732 1733 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1734 * has completed. 1735 */ 1736 return ret_val; 1737 } 1738 1739 /** 1740 * e1000e_phy_has_link_generic - Polls PHY for link 1741 * @hw: pointer to the HW structure 1742 * @iterations: number of times to poll for link 1743 * @usec_interval: delay between polling attempts 1744 * @success: pointer to whether polling was successful or not 1745 * 1746 * Polls the PHY status register for link, 'iterations' number of times. 1747 **/ 1748 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1749 u32 usec_interval, bool *success) 1750 { 1751 s32 ret_val = 0; 1752 u16 i, phy_status; 1753 1754 for (i = 0; i < iterations; i++) { 1755 /* Some PHYs require the MII_BMSR register to be read 1756 * twice due to the link bit being sticky. No harm doing 1757 * it across the board. 1758 */ 1759 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1760 if (ret_val) 1761 /* If the first read fails, another entity may have 1762 * ownership of the resources, wait and try again to 1763 * see if they have relinquished the resources yet. 1764 */ 1765 udelay(usec_interval); 1766 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); 1767 if (ret_val) 1768 break; 1769 if (phy_status & BMSR_LSTATUS) 1770 break; 1771 if (usec_interval >= 1000) 1772 mdelay(usec_interval / 1000); 1773 else 1774 udelay(usec_interval); 1775 } 1776 1777 *success = (i < iterations); 1778 1779 return ret_val; 1780 } 1781 1782 /** 1783 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY 1784 * @hw: pointer to the HW structure 1785 * 1786 * Reads the PHY specific status register to retrieve the cable length 1787 * information. The cable length is determined by averaging the minimum and 1788 * maximum values to get the "average" cable length. The m88 PHY has four 1789 * possible cable length values, which are: 1790 * Register Value Cable Length 1791 * 0 < 50 meters 1792 * 1 50 - 80 meters 1793 * 2 80 - 110 meters 1794 * 3 110 - 140 meters 1795 * 4 > 140 meters 1796 **/ 1797 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) 1798 { 1799 struct e1000_phy_info *phy = &hw->phy; 1800 s32 ret_val; 1801 u16 phy_data, index; 1802 1803 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1804 if (ret_val) 1805 return ret_val; 1806 1807 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1808 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 1809 1810 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 1811 return -E1000_ERR_PHY; 1812 1813 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1814 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1815 1816 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1817 1818 return 0; 1819 } 1820 1821 /** 1822 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1823 * @hw: pointer to the HW structure 1824 * 1825 * The automatic gain control (agc) normalizes the amplitude of the 1826 * received signal, adjusting for the attenuation produced by the 1827 * cable. By reading the AGC registers, which represent the 1828 * combination of coarse and fine gain value, the value can be put 1829 * into a lookup table to obtain the approximate cable length 1830 * for each channel. 1831 **/ 1832 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) 1833 { 1834 struct e1000_phy_info *phy = &hw->phy; 1835 s32 ret_val; 1836 u16 phy_data, i, agc_value = 0; 1837 u16 cur_agc_index, max_agc_index = 0; 1838 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1839 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1840 IGP02E1000_PHY_AGC_A, 1841 IGP02E1000_PHY_AGC_B, 1842 IGP02E1000_PHY_AGC_C, 1843 IGP02E1000_PHY_AGC_D 1844 }; 1845 1846 /* Read the AGC registers for all channels */ 1847 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1848 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); 1849 if (ret_val) 1850 return ret_val; 1851 1852 /* Getting bits 15:9, which represent the combination of 1853 * coarse and fine gain values. The result is a number 1854 * that can be put into the lookup table to obtain the 1855 * approximate cable length. 1856 */ 1857 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1858 IGP02E1000_AGC_LENGTH_MASK); 1859 1860 /* Array index bound check. */ 1861 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1862 (cur_agc_index == 0)) 1863 return -E1000_ERR_PHY; 1864 1865 /* Remove min & max AGC values from calculation. */ 1866 if (e1000_igp_2_cable_length_table[min_agc_index] > 1867 e1000_igp_2_cable_length_table[cur_agc_index]) 1868 min_agc_index = cur_agc_index; 1869 if (e1000_igp_2_cable_length_table[max_agc_index] < 1870 e1000_igp_2_cable_length_table[cur_agc_index]) 1871 max_agc_index = cur_agc_index; 1872 1873 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1874 } 1875 1876 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1877 e1000_igp_2_cable_length_table[max_agc_index]); 1878 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1879 1880 /* Calculate cable length with the error range of +/- 10 meters. */ 1881 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1882 (agc_value - IGP02E1000_AGC_RANGE) : 0); 1883 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1884 1885 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1886 1887 return 0; 1888 } 1889 1890 /** 1891 * e1000e_get_phy_info_m88 - Retrieve PHY information 1892 * @hw: pointer to the HW structure 1893 * 1894 * Valid for only copper links. Read the PHY status register (sticky read) 1895 * to verify that link is up. Read the PHY special control register to 1896 * determine the polarity and 10base-T extended distance. Read the PHY 1897 * special status register to determine MDI/MDIx and current speed. If 1898 * speed is 1000, then determine cable length, local and remote receiver. 1899 **/ 1900 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) 1901 { 1902 struct e1000_phy_info *phy = &hw->phy; 1903 s32 ret_val; 1904 u16 phy_data; 1905 bool link; 1906 1907 if (phy->media_type != e1000_media_type_copper) { 1908 e_dbg("Phy info is only valid for copper media\n"); 1909 return -E1000_ERR_CONFIG; 1910 } 1911 1912 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1913 if (ret_val) 1914 return ret_val; 1915 1916 if (!link) { 1917 e_dbg("Phy info is only valid if link is up\n"); 1918 return -E1000_ERR_CONFIG; 1919 } 1920 1921 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1922 if (ret_val) 1923 return ret_val; 1924 1925 phy->polarity_correction = !!(phy_data & 1926 M88E1000_PSCR_POLARITY_REVERSAL); 1927 1928 ret_val = e1000_check_polarity_m88(hw); 1929 if (ret_val) 1930 return ret_val; 1931 1932 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1933 if (ret_val) 1934 return ret_val; 1935 1936 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 1937 1938 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1939 ret_val = hw->phy.ops.get_cable_length(hw); 1940 if (ret_val) 1941 return ret_val; 1942 1943 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); 1944 if (ret_val) 1945 return ret_val; 1946 1947 phy->local_rx = (phy_data & LPA_1000LOCALRXOK) 1948 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 1949 1950 phy->remote_rx = (phy_data & LPA_1000REMRXOK) 1951 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 1952 } else { 1953 /* Set values to "undefined" */ 1954 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1955 phy->local_rx = e1000_1000t_rx_status_undefined; 1956 phy->remote_rx = e1000_1000t_rx_status_undefined; 1957 } 1958 1959 return ret_val; 1960 } 1961 1962 /** 1963 * e1000e_get_phy_info_igp - Retrieve igp PHY information 1964 * @hw: pointer to the HW structure 1965 * 1966 * Read PHY status to determine if link is up. If link is up, then 1967 * set/determine 10base-T extended distance and polarity correction. Read 1968 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1969 * determine on the cable length, local and remote receiver. 1970 **/ 1971 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) 1972 { 1973 struct e1000_phy_info *phy = &hw->phy; 1974 s32 ret_val; 1975 u16 data; 1976 bool link; 1977 1978 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1979 if (ret_val) 1980 return ret_val; 1981 1982 if (!link) { 1983 e_dbg("Phy info is only valid if link is up\n"); 1984 return -E1000_ERR_CONFIG; 1985 } 1986 1987 phy->polarity_correction = true; 1988 1989 ret_val = e1000_check_polarity_igp(hw); 1990 if (ret_val) 1991 return ret_val; 1992 1993 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1994 if (ret_val) 1995 return ret_val; 1996 1997 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 1998 1999 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2000 IGP01E1000_PSSR_SPEED_1000MBPS) { 2001 ret_val = phy->ops.get_cable_length(hw); 2002 if (ret_val) 2003 return ret_val; 2004 2005 ret_val = e1e_rphy(hw, MII_STAT1000, &data); 2006 if (ret_val) 2007 return ret_val; 2008 2009 phy->local_rx = (data & LPA_1000LOCALRXOK) 2010 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 2011 2012 phy->remote_rx = (data & LPA_1000REMRXOK) 2013 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 2014 } else { 2015 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2016 phy->local_rx = e1000_1000t_rx_status_undefined; 2017 phy->remote_rx = e1000_1000t_rx_status_undefined; 2018 } 2019 2020 return ret_val; 2021 } 2022 2023 /** 2024 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2025 * @hw: pointer to the HW structure 2026 * 2027 * Populates "phy" structure with various feature states. 2028 **/ 2029 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2030 { 2031 struct e1000_phy_info *phy = &hw->phy; 2032 s32 ret_val; 2033 u16 data; 2034 bool link; 2035 2036 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 2037 if (ret_val) 2038 return ret_val; 2039 2040 if (!link) { 2041 e_dbg("Phy info is only valid if link is up\n"); 2042 return -E1000_ERR_CONFIG; 2043 } 2044 2045 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2046 if (ret_val) 2047 return ret_val; 2048 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2049 2050 if (phy->polarity_correction) { 2051 ret_val = e1000_check_polarity_ife(hw); 2052 if (ret_val) 2053 return ret_val; 2054 } else { 2055 /* Polarity is forced */ 2056 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2057 ? e1000_rev_polarity_reversed 2058 : e1000_rev_polarity_normal); 2059 } 2060 2061 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 2062 if (ret_val) 2063 return ret_val; 2064 2065 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2066 2067 /* The following parameters are undefined for 10/100 operation. */ 2068 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2069 phy->local_rx = e1000_1000t_rx_status_undefined; 2070 phy->remote_rx = e1000_1000t_rx_status_undefined; 2071 2072 return 0; 2073 } 2074 2075 /** 2076 * e1000e_phy_sw_reset - PHY software reset 2077 * @hw: pointer to the HW structure 2078 * 2079 * Does a software reset of the PHY by reading the PHY control register and 2080 * setting/write the control register reset bit to the PHY. 2081 **/ 2082 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) 2083 { 2084 s32 ret_val; 2085 u16 phy_ctrl; 2086 2087 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); 2088 if (ret_val) 2089 return ret_val; 2090 2091 phy_ctrl |= BMCR_RESET; 2092 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); 2093 if (ret_val) 2094 return ret_val; 2095 2096 udelay(1); 2097 2098 return ret_val; 2099 } 2100 2101 /** 2102 * e1000e_phy_hw_reset_generic - PHY hardware reset 2103 * @hw: pointer to the HW structure 2104 * 2105 * Verify the reset block is not blocking us from resetting. Acquire 2106 * semaphore (if necessary) and read/set/write the device control reset 2107 * bit in the PHY. Wait the appropriate delay time for the device to 2108 * reset and release the semaphore (if necessary). 2109 **/ 2110 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) 2111 { 2112 struct e1000_phy_info *phy = &hw->phy; 2113 s32 ret_val; 2114 u32 ctrl; 2115 2116 if (phy->ops.check_reset_block) { 2117 ret_val = phy->ops.check_reset_block(hw); 2118 if (ret_val) 2119 return 0; 2120 } 2121 2122 ret_val = phy->ops.acquire(hw); 2123 if (ret_val) 2124 return ret_val; 2125 2126 ctrl = er32(CTRL); 2127 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2128 e1e_flush(); 2129 2130 udelay(phy->reset_delay_us); 2131 2132 ew32(CTRL, ctrl); 2133 e1e_flush(); 2134 2135 usleep_range(150, 300); 2136 2137 phy->ops.release(hw); 2138 2139 return phy->ops.get_cfg_done(hw); 2140 } 2141 2142 /** 2143 * e1000e_get_cfg_done_generic - Generic configuration done 2144 * @hw: pointer to the HW structure 2145 * 2146 * Generic function to wait 10 milli-seconds for configuration to complete 2147 * and return success. 2148 **/ 2149 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) 2150 { 2151 mdelay(10); 2152 2153 return 0; 2154 } 2155 2156 /** 2157 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY 2158 * @hw: pointer to the HW structure 2159 * 2160 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2161 **/ 2162 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2163 { 2164 e_dbg("Running IGP 3 PHY init script\n"); 2165 2166 /* PHY init IGP 3 */ 2167 /* Enable rise/fall, 10-mode work in class-A */ 2168 e1e_wphy(hw, 0x2F5B, 0x9018); 2169 /* Remove all caps from Replica path filter */ 2170 e1e_wphy(hw, 0x2F52, 0x0000); 2171 /* Bias trimming for ADC, AFE and Driver (Default) */ 2172 e1e_wphy(hw, 0x2FB1, 0x8B24); 2173 /* Increase Hybrid poly bias */ 2174 e1e_wphy(hw, 0x2FB2, 0xF8F0); 2175 /* Add 4% to Tx amplitude in Gig mode */ 2176 e1e_wphy(hw, 0x2010, 0x10B0); 2177 /* Disable trimming (TTT) */ 2178 e1e_wphy(hw, 0x2011, 0x0000); 2179 /* Poly DC correction to 94.6% + 2% for all channels */ 2180 e1e_wphy(hw, 0x20DD, 0x249A); 2181 /* ABS DC correction to 95.9% */ 2182 e1e_wphy(hw, 0x20DE, 0x00D3); 2183 /* BG temp curve trim */ 2184 e1e_wphy(hw, 0x28B4, 0x04CE); 2185 /* Increasing ADC OPAMP stage 1 currents to max */ 2186 e1e_wphy(hw, 0x2F70, 0x29E4); 2187 /* Force 1000 ( required for enabling PHY regs configuration) */ 2188 e1e_wphy(hw, 0x0000, 0x0140); 2189 /* Set upd_freq to 6 */ 2190 e1e_wphy(hw, 0x1F30, 0x1606); 2191 /* Disable NPDFE */ 2192 e1e_wphy(hw, 0x1F31, 0xB814); 2193 /* Disable adaptive fixed FFE (Default) */ 2194 e1e_wphy(hw, 0x1F35, 0x002A); 2195 /* Enable FFE hysteresis */ 2196 e1e_wphy(hw, 0x1F3E, 0x0067); 2197 /* Fixed FFE for short cable lengths */ 2198 e1e_wphy(hw, 0x1F54, 0x0065); 2199 /* Fixed FFE for medium cable lengths */ 2200 e1e_wphy(hw, 0x1F55, 0x002A); 2201 /* Fixed FFE for long cable lengths */ 2202 e1e_wphy(hw, 0x1F56, 0x002A); 2203 /* Enable Adaptive Clip Threshold */ 2204 e1e_wphy(hw, 0x1F72, 0x3FB0); 2205 /* AHT reset limit to 1 */ 2206 e1e_wphy(hw, 0x1F76, 0xC0FF); 2207 /* Set AHT master delay to 127 msec */ 2208 e1e_wphy(hw, 0x1F77, 0x1DEC); 2209 /* Set scan bits for AHT */ 2210 e1e_wphy(hw, 0x1F78, 0xF9EF); 2211 /* Set AHT Preset bits */ 2212 e1e_wphy(hw, 0x1F79, 0x0210); 2213 /* Change integ_factor of channel A to 3 */ 2214 e1e_wphy(hw, 0x1895, 0x0003); 2215 /* Change prop_factor of channels BCD to 8 */ 2216 e1e_wphy(hw, 0x1796, 0x0008); 2217 /* Change cg_icount + enable integbp for channels BCD */ 2218 e1e_wphy(hw, 0x1798, 0xD008); 2219 /* Change cg_icount + enable integbp + change prop_factor_master 2220 * to 8 for channel A 2221 */ 2222 e1e_wphy(hw, 0x1898, 0xD918); 2223 /* Disable AHT in Slave mode on channel A */ 2224 e1e_wphy(hw, 0x187A, 0x0800); 2225 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2226 * Enable SPD+B2B 2227 */ 2228 e1e_wphy(hw, 0x0019, 0x008D); 2229 /* Enable restart AN on an1000_dis change */ 2230 e1e_wphy(hw, 0x001B, 0x2080); 2231 /* Enable wh_fifo read clock in 10/100 modes */ 2232 e1e_wphy(hw, 0x0014, 0x0045); 2233 /* Restart AN, Speed selection is 1000 */ 2234 e1e_wphy(hw, 0x0000, 0x1340); 2235 2236 return 0; 2237 } 2238 2239 /** 2240 * e1000e_get_phy_type_from_id - Get PHY type from id 2241 * @phy_id: phy_id read from the phy 2242 * 2243 * Returns the phy type from the id. 2244 **/ 2245 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) 2246 { 2247 enum e1000_phy_type phy_type = e1000_phy_unknown; 2248 2249 switch (phy_id) { 2250 case M88E1000_I_PHY_ID: 2251 case M88E1000_E_PHY_ID: 2252 case M88E1111_I_PHY_ID: 2253 case M88E1011_I_PHY_ID: 2254 phy_type = e1000_phy_m88; 2255 break; 2256 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2257 phy_type = e1000_phy_igp_2; 2258 break; 2259 case GG82563_E_PHY_ID: 2260 phy_type = e1000_phy_gg82563; 2261 break; 2262 case IGP03E1000_E_PHY_ID: 2263 phy_type = e1000_phy_igp_3; 2264 break; 2265 case IFE_E_PHY_ID: 2266 case IFE_PLUS_E_PHY_ID: 2267 case IFE_C_E_PHY_ID: 2268 phy_type = e1000_phy_ife; 2269 break; 2270 case BME1000_E_PHY_ID: 2271 case BME1000_E_PHY_ID_R2: 2272 phy_type = e1000_phy_bm; 2273 break; 2274 case I82578_E_PHY_ID: 2275 phy_type = e1000_phy_82578; 2276 break; 2277 case I82577_E_PHY_ID: 2278 phy_type = e1000_phy_82577; 2279 break; 2280 case I82579_E_PHY_ID: 2281 phy_type = e1000_phy_82579; 2282 break; 2283 case I217_E_PHY_ID: 2284 phy_type = e1000_phy_i217; 2285 break; 2286 default: 2287 phy_type = e1000_phy_unknown; 2288 break; 2289 } 2290 return phy_type; 2291 } 2292 2293 /** 2294 * e1000e_determine_phy_address - Determines PHY address. 2295 * @hw: pointer to the HW structure 2296 * 2297 * This uses a trial and error method to loop through possible PHY 2298 * addresses. It tests each by reading the PHY ID registers and 2299 * checking for a match. 2300 **/ 2301 s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2302 { 2303 u32 phy_addr = 0; 2304 u32 i; 2305 enum e1000_phy_type phy_type = e1000_phy_unknown; 2306 2307 hw->phy.id = phy_type; 2308 2309 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2310 hw->phy.addr = phy_addr; 2311 i = 0; 2312 2313 do { 2314 e1000e_get_phy_id(hw); 2315 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2316 2317 /* If phy_type is valid, break - we found our 2318 * PHY address 2319 */ 2320 if (phy_type != e1000_phy_unknown) 2321 return 0; 2322 2323 usleep_range(1000, 2000); 2324 i++; 2325 } while (i < 10); 2326 } 2327 2328 return -E1000_ERR_PHY_TYPE; 2329 } 2330 2331 /** 2332 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2333 * @page: page to access 2334 * 2335 * Returns the phy address for the page requested. 2336 **/ 2337 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2338 { 2339 u32 phy_addr = 2; 2340 2341 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2342 phy_addr = 1; 2343 2344 return phy_addr; 2345 } 2346 2347 /** 2348 * e1000e_write_phy_reg_bm - Write BM PHY register 2349 * @hw: pointer to the HW structure 2350 * @offset: register offset to write to 2351 * @data: data to write at register offset 2352 * 2353 * Acquires semaphore, if necessary, then writes the data to PHY register 2354 * at the offset. Release any acquired semaphores before exiting. 2355 **/ 2356 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2357 { 2358 s32 ret_val; 2359 u32 page = offset >> IGP_PAGE_SHIFT; 2360 2361 ret_val = hw->phy.ops.acquire(hw); 2362 if (ret_val) 2363 return ret_val; 2364 2365 /* Page 800 works differently than the rest so it has its own func */ 2366 if (page == BM_WUC_PAGE) { 2367 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2368 false, false); 2369 goto release; 2370 } 2371 2372 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2373 2374 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2375 u32 page_shift, page_select; 2376 2377 /* Page select is register 31 for phy address 1 and 22 for 2378 * phy address 2 and 3. Page select is shifted only for 2379 * phy address 1. 2380 */ 2381 if (hw->phy.addr == 1) { 2382 page_shift = IGP_PAGE_SHIFT; 2383 page_select = IGP01E1000_PHY_PAGE_SELECT; 2384 } else { 2385 page_shift = 0; 2386 page_select = BM_PHY_PAGE_SELECT; 2387 } 2388 2389 /* Page is shifted left, PHY expects (page x 32) */ 2390 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2391 (page << page_shift)); 2392 if (ret_val) 2393 goto release; 2394 } 2395 2396 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2397 data); 2398 2399 release: 2400 hw->phy.ops.release(hw); 2401 return ret_val; 2402 } 2403 2404 /** 2405 * e1000e_read_phy_reg_bm - Read BM PHY register 2406 * @hw: pointer to the HW structure 2407 * @offset: register offset to be read 2408 * @data: pointer to the read data 2409 * 2410 * Acquires semaphore, if necessary, then reads the PHY register at offset 2411 * and storing the retrieved information in data. Release any acquired 2412 * semaphores before exiting. 2413 **/ 2414 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2415 { 2416 s32 ret_val; 2417 u32 page = offset >> IGP_PAGE_SHIFT; 2418 2419 ret_val = hw->phy.ops.acquire(hw); 2420 if (ret_val) 2421 return ret_val; 2422 2423 /* Page 800 works differently than the rest so it has its own func */ 2424 if (page == BM_WUC_PAGE) { 2425 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2426 true, false); 2427 goto release; 2428 } 2429 2430 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2431 2432 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2433 u32 page_shift, page_select; 2434 2435 /* Page select is register 31 for phy address 1 and 22 for 2436 * phy address 2 and 3. Page select is shifted only for 2437 * phy address 1. 2438 */ 2439 if (hw->phy.addr == 1) { 2440 page_shift = IGP_PAGE_SHIFT; 2441 page_select = IGP01E1000_PHY_PAGE_SELECT; 2442 } else { 2443 page_shift = 0; 2444 page_select = BM_PHY_PAGE_SELECT; 2445 } 2446 2447 /* Page is shifted left, PHY expects (page x 32) */ 2448 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 2449 (page << page_shift)); 2450 if (ret_val) 2451 goto release; 2452 } 2453 2454 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2455 data); 2456 release: 2457 hw->phy.ops.release(hw); 2458 return ret_val; 2459 } 2460 2461 /** 2462 * e1000e_read_phy_reg_bm2 - Read BM PHY register 2463 * @hw: pointer to the HW structure 2464 * @offset: register offset to be read 2465 * @data: pointer to the read data 2466 * 2467 * Acquires semaphore, if necessary, then reads the PHY register at offset 2468 * and storing the retrieved information in data. Release any acquired 2469 * semaphores before exiting. 2470 **/ 2471 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2472 { 2473 s32 ret_val; 2474 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2475 2476 ret_val = hw->phy.ops.acquire(hw); 2477 if (ret_val) 2478 return ret_val; 2479 2480 /* Page 800 works differently than the rest so it has its own func */ 2481 if (page == BM_WUC_PAGE) { 2482 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2483 true, false); 2484 goto release; 2485 } 2486 2487 hw->phy.addr = 1; 2488 2489 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2490 /* Page is shifted left, PHY expects (page x 32) */ 2491 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2492 page); 2493 2494 if (ret_val) 2495 goto release; 2496 } 2497 2498 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2499 data); 2500 release: 2501 hw->phy.ops.release(hw); 2502 return ret_val; 2503 } 2504 2505 /** 2506 * e1000e_write_phy_reg_bm2 - Write BM PHY register 2507 * @hw: pointer to the HW structure 2508 * @offset: register offset to write to 2509 * @data: data to write at register offset 2510 * 2511 * Acquires semaphore, if necessary, then writes the data to PHY register 2512 * at the offset. Release any acquired semaphores before exiting. 2513 **/ 2514 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2515 { 2516 s32 ret_val; 2517 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2518 2519 ret_val = hw->phy.ops.acquire(hw); 2520 if (ret_val) 2521 return ret_val; 2522 2523 /* Page 800 works differently than the rest so it has its own func */ 2524 if (page == BM_WUC_PAGE) { 2525 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2526 false, false); 2527 goto release; 2528 } 2529 2530 hw->phy.addr = 1; 2531 2532 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2533 /* Page is shifted left, PHY expects (page x 32) */ 2534 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2535 page); 2536 2537 if (ret_val) 2538 goto release; 2539 } 2540 2541 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2542 data); 2543 2544 release: 2545 hw->phy.ops.release(hw); 2546 return ret_val; 2547 } 2548 2549 /** 2550 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 2551 * @hw: pointer to the HW structure 2552 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 2553 * 2554 * Assumes semaphore already acquired and phy_reg points to a valid memory 2555 * address to store contents of the BM_WUC_ENABLE_REG register. 2556 **/ 2557 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2558 { 2559 s32 ret_val; 2560 u16 temp; 2561 2562 /* All page select, port ctrl and wakeup registers use phy address 1 */ 2563 hw->phy.addr = 1; 2564 2565 /* Select Port Control Registers page */ 2566 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2567 if (ret_val) { 2568 e_dbg("Could not set Port Control page\n"); 2569 return ret_val; 2570 } 2571 2572 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2573 if (ret_val) { 2574 e_dbg("Could not read PHY register %d.%d\n", 2575 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2576 return ret_val; 2577 } 2578 2579 /* Enable both PHY wakeup mode and Wakeup register page writes. 2580 * Prevent a power state change by disabling ME and Host PHY wakeup. 2581 */ 2582 temp = *phy_reg; 2583 temp |= BM_WUC_ENABLE_BIT; 2584 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 2585 2586 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 2587 if (ret_val) { 2588 e_dbg("Could not write PHY register %d.%d\n", 2589 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2590 return ret_val; 2591 } 2592 2593 /* Select Host Wakeup Registers page - caller now able to write 2594 * registers on the Wakeup registers page 2595 */ 2596 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2597 } 2598 2599 /** 2600 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 2601 * @hw: pointer to the HW structure 2602 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 2603 * 2604 * Restore BM_WUC_ENABLE_REG to its original value. 2605 * 2606 * Assumes semaphore already acquired and *phy_reg is the contents of the 2607 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 2608 * caller. 2609 **/ 2610 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 2611 { 2612 s32 ret_val; 2613 2614 /* Select Port Control Registers page */ 2615 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 2616 if (ret_val) { 2617 e_dbg("Could not set Port Control page\n"); 2618 return ret_val; 2619 } 2620 2621 /* Restore 769.17 to its original value */ 2622 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 2623 if (ret_val) 2624 e_dbg("Could not restore PHY register %d.%d\n", 2625 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 2626 2627 return ret_val; 2628 } 2629 2630 /** 2631 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 2632 * @hw: pointer to the HW structure 2633 * @offset: register offset to be read or written 2634 * @data: pointer to the data to read or write 2635 * @read: determines if operation is read or write 2636 * @page_set: BM_WUC_PAGE already set and access enabled 2637 * 2638 * Read the PHY register at offset and store the retrieved information in 2639 * data, or write data to PHY register at offset. Note the procedure to 2640 * access the PHY wakeup registers is different than reading the other PHY 2641 * registers. It works as such: 2642 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 2643 * 2) Set page to 800 for host (801 if we were manageability) 2644 * 3) Write the address using the address opcode (0x11) 2645 * 4) Read or write the data using the data opcode (0x12) 2646 * 5) Restore 769.17.2 to its original value 2647 * 2648 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 2649 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 2650 * 2651 * Assumes semaphore is already acquired. When page_set==true, assumes 2652 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 2653 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 2654 **/ 2655 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2656 u16 *data, bool read, bool page_set) 2657 { 2658 s32 ret_val; 2659 u16 reg = BM_PHY_REG_NUM(offset); 2660 u16 page = BM_PHY_REG_PAGE(offset); 2661 u16 phy_reg = 0; 2662 2663 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 2664 if ((hw->mac.type == e1000_pchlan) && 2665 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2666 e_dbg("Attempting to access page %d while gig enabled.\n", 2667 page); 2668 2669 if (!page_set) { 2670 /* Enable access to PHY wakeup registers */ 2671 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2672 if (ret_val) { 2673 e_dbg("Could not enable PHY wakeup reg access\n"); 2674 return ret_val; 2675 } 2676 } 2677 2678 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); 2679 2680 /* Write the Wakeup register page offset value using opcode 0x11 */ 2681 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2682 if (ret_val) { 2683 e_dbg("Could not write address opcode to page %d\n", page); 2684 return ret_val; 2685 } 2686 2687 if (read) { 2688 /* Read the Wakeup register page value using opcode 0x12 */ 2689 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2690 data); 2691 } else { 2692 /* Write the Wakeup register page value using opcode 0x12 */ 2693 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2694 *data); 2695 } 2696 2697 if (ret_val) { 2698 e_dbg("Could not access PHY reg %d.%d\n", page, reg); 2699 return ret_val; 2700 } 2701 2702 if (!page_set) 2703 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2704 2705 return ret_val; 2706 } 2707 2708 /** 2709 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2710 * @hw: pointer to the HW structure 2711 * 2712 * In the case of a PHY power down to save power, or to turn off link during a 2713 * driver unload, or wake on lan is not enabled, restore the link to previous 2714 * settings. 2715 **/ 2716 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2717 { 2718 u16 mii_reg = 0; 2719 2720 /* The PHY will retain its settings across a power down/up cycle */ 2721 e1e_rphy(hw, MII_BMCR, &mii_reg); 2722 mii_reg &= ~BMCR_PDOWN; 2723 e1e_wphy(hw, MII_BMCR, mii_reg); 2724 } 2725 2726 /** 2727 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2728 * @hw: pointer to the HW structure 2729 * 2730 * In the case of a PHY power down to save power, or to turn off link during a 2731 * driver unload, or wake on lan is not enabled, restore the link to previous 2732 * settings. 2733 **/ 2734 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2735 { 2736 u16 mii_reg = 0; 2737 2738 /* The PHY will retain its settings across a power down/up cycle */ 2739 e1e_rphy(hw, MII_BMCR, &mii_reg); 2740 mii_reg |= BMCR_PDOWN; 2741 e1e_wphy(hw, MII_BMCR, mii_reg); 2742 usleep_range(1000, 2000); 2743 } 2744 2745 /** 2746 * __e1000_read_phy_reg_hv - Read HV PHY register 2747 * @hw: pointer to the HW structure 2748 * @offset: register offset to be read 2749 * @data: pointer to the read data 2750 * @locked: semaphore has already been acquired or not 2751 * 2752 * Acquires semaphore, if necessary, then reads the PHY register at offset 2753 * and stores the retrieved information in data. Release any acquired 2754 * semaphore before exiting. 2755 **/ 2756 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2757 bool locked, bool page_set) 2758 { 2759 s32 ret_val; 2760 u16 page = BM_PHY_REG_PAGE(offset); 2761 u16 reg = BM_PHY_REG_NUM(offset); 2762 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2763 2764 if (!locked) { 2765 ret_val = hw->phy.ops.acquire(hw); 2766 if (ret_val) 2767 return ret_val; 2768 } 2769 2770 /* Page 800 works differently than the rest so it has its own func */ 2771 if (page == BM_WUC_PAGE) { 2772 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2773 true, page_set); 2774 goto out; 2775 } 2776 2777 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2778 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2779 data, true); 2780 goto out; 2781 } 2782 2783 if (!page_set) { 2784 if (page == HV_INTC_FC_PAGE_START) 2785 page = 0; 2786 2787 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2788 /* Page is shifted left, PHY expects (page x 32) */ 2789 ret_val = e1000_set_page_igp(hw, 2790 (page << IGP_PAGE_SHIFT)); 2791 2792 hw->phy.addr = phy_addr; 2793 2794 if (ret_val) 2795 goto out; 2796 } 2797 } 2798 2799 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2800 page << IGP_PAGE_SHIFT, reg); 2801 2802 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); 2803 out: 2804 if (!locked) 2805 hw->phy.ops.release(hw); 2806 2807 return ret_val; 2808 } 2809 2810 /** 2811 * e1000_read_phy_reg_hv - Read HV PHY register 2812 * @hw: pointer to the HW structure 2813 * @offset: register offset to be read 2814 * @data: pointer to the read data 2815 * 2816 * Acquires semaphore then reads the PHY register at offset and stores 2817 * the retrieved information in data. Release the acquired semaphore 2818 * before exiting. 2819 **/ 2820 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2821 { 2822 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 2823 } 2824 2825 /** 2826 * e1000_read_phy_reg_hv_locked - Read HV PHY register 2827 * @hw: pointer to the HW structure 2828 * @offset: register offset to be read 2829 * @data: pointer to the read data 2830 * 2831 * Reads the PHY register at offset and stores the retrieved information 2832 * in data. Assumes semaphore already acquired. 2833 **/ 2834 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 2835 { 2836 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 2837 } 2838 2839 /** 2840 * e1000_read_phy_reg_page_hv - Read HV PHY register 2841 * @hw: pointer to the HW structure 2842 * @offset: register offset to write to 2843 * @data: data to write at register offset 2844 * 2845 * Reads the PHY register at offset and stores the retrieved information 2846 * in data. Assumes semaphore already acquired and page already set. 2847 **/ 2848 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 2849 { 2850 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 2851 } 2852 2853 /** 2854 * __e1000_write_phy_reg_hv - Write HV PHY register 2855 * @hw: pointer to the HW structure 2856 * @offset: register offset to write to 2857 * @data: data to write at register offset 2858 * @locked: semaphore has already been acquired or not 2859 * 2860 * Acquires semaphore, if necessary, then writes the data to PHY register 2861 * at the offset. Release any acquired semaphores before exiting. 2862 **/ 2863 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 2864 bool locked, bool page_set) 2865 { 2866 s32 ret_val; 2867 u16 page = BM_PHY_REG_PAGE(offset); 2868 u16 reg = BM_PHY_REG_NUM(offset); 2869 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 2870 2871 if (!locked) { 2872 ret_val = hw->phy.ops.acquire(hw); 2873 if (ret_val) 2874 return ret_val; 2875 } 2876 2877 /* Page 800 works differently than the rest so it has its own func */ 2878 if (page == BM_WUC_PAGE) { 2879 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2880 false, page_set); 2881 goto out; 2882 } 2883 2884 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2885 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 2886 &data, false); 2887 goto out; 2888 } 2889 2890 if (!page_set) { 2891 if (page == HV_INTC_FC_PAGE_START) 2892 page = 0; 2893 2894 /* Workaround MDIO accesses being disabled after entering IEEE 2895 * Power Down (when bit 11 of the PHY Control register is set) 2896 */ 2897 if ((hw->phy.type == e1000_phy_82578) && 2898 (hw->phy.revision >= 1) && 2899 (hw->phy.addr == 2) && 2900 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { 2901 u16 data2 = 0x7EFF; 2902 ret_val = e1000_access_phy_debug_regs_hv(hw, 2903 (1 << 6) | 0x3, 2904 &data2, false); 2905 if (ret_val) 2906 goto out; 2907 } 2908 2909 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2910 /* Page is shifted left, PHY expects (page x 32) */ 2911 ret_val = e1000_set_page_igp(hw, 2912 (page << IGP_PAGE_SHIFT)); 2913 2914 hw->phy.addr = phy_addr; 2915 2916 if (ret_val) 2917 goto out; 2918 } 2919 } 2920 2921 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 2922 page << IGP_PAGE_SHIFT, reg); 2923 2924 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2925 data); 2926 2927 out: 2928 if (!locked) 2929 hw->phy.ops.release(hw); 2930 2931 return ret_val; 2932 } 2933 2934 /** 2935 * e1000_write_phy_reg_hv - Write HV PHY register 2936 * @hw: pointer to the HW structure 2937 * @offset: register offset to write to 2938 * @data: data to write at register offset 2939 * 2940 * Acquires semaphore then writes the data to PHY register at the offset. 2941 * Release the acquired semaphores before exiting. 2942 **/ 2943 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 2944 { 2945 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 2946 } 2947 2948 /** 2949 * e1000_write_phy_reg_hv_locked - Write HV PHY register 2950 * @hw: pointer to the HW structure 2951 * @offset: register offset to write to 2952 * @data: data to write at register offset 2953 * 2954 * Writes the data to PHY register at the offset. Assumes semaphore 2955 * already acquired. 2956 **/ 2957 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 2958 { 2959 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 2960 } 2961 2962 /** 2963 * e1000_write_phy_reg_page_hv - Write HV PHY register 2964 * @hw: pointer to the HW structure 2965 * @offset: register offset to write to 2966 * @data: data to write at register offset 2967 * 2968 * Writes the data to PHY register at the offset. Assumes semaphore 2969 * already acquired and page already set. 2970 **/ 2971 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 2972 { 2973 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 2974 } 2975 2976 /** 2977 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page 2978 * @page: page to be accessed 2979 **/ 2980 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 2981 { 2982 u32 phy_addr = 2; 2983 2984 if (page >= HV_INTC_FC_PAGE_START) 2985 phy_addr = 1; 2986 2987 return phy_addr; 2988 } 2989 2990 /** 2991 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 2992 * @hw: pointer to the HW structure 2993 * @offset: register offset to be read or written 2994 * @data: pointer to the data to be read or written 2995 * @read: determines if operation is read or write 2996 * 2997 * Reads the PHY register at offset and stores the retreived information 2998 * in data. Assumes semaphore already acquired. Note that the procedure 2999 * to access these regs uses the address port and data port to read/write. 3000 * These accesses done with PHY address 2 and without using pages. 3001 **/ 3002 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3003 u16 *data, bool read) 3004 { 3005 s32 ret_val; 3006 u32 addr_reg; 3007 u32 data_reg; 3008 3009 /* This takes care of the difference with desktop vs mobile phy */ 3010 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3011 I82578_ADDR_REG : I82577_ADDR_REG); 3012 data_reg = addr_reg + 1; 3013 3014 /* All operations in this function are phy address 2 */ 3015 hw->phy.addr = 2; 3016 3017 /* masking with 0x3F to remove the page from offset */ 3018 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3019 if (ret_val) { 3020 e_dbg("Could not write the Address Offset port register\n"); 3021 return ret_val; 3022 } 3023 3024 /* Read or write the data value next */ 3025 if (read) 3026 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); 3027 else 3028 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3029 3030 if (ret_val) 3031 e_dbg("Could not access the Data port register\n"); 3032 3033 return ret_val; 3034 } 3035 3036 /** 3037 * e1000_link_stall_workaround_hv - Si workaround 3038 * @hw: pointer to the HW structure 3039 * 3040 * This function works around a Si bug where the link partner can get 3041 * a link up indication before the PHY does. If small packets are sent 3042 * by the link partner they can be placed in the packet buffer without 3043 * being properly accounted for by the PHY and will stall preventing 3044 * further packets from being received. The workaround is to clear the 3045 * packet buffer after the PHY detects link up. 3046 **/ 3047 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3048 { 3049 s32 ret_val = 0; 3050 u16 data; 3051 3052 if (hw->phy.type != e1000_phy_82578) 3053 return 0; 3054 3055 /* Do not apply workaround if in PHY loopback bit 14 set */ 3056 e1e_rphy(hw, MII_BMCR, &data); 3057 if (data & BMCR_LOOPBACK) 3058 return 0; 3059 3060 /* check if link is up and at 1Gbps */ 3061 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 3062 if (ret_val) 3063 return ret_val; 3064 3065 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3066 BM_CS_STATUS_SPEED_MASK); 3067 3068 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3069 BM_CS_STATUS_SPEED_1000)) 3070 return 0; 3071 3072 msleep(200); 3073 3074 /* flush the packets in the fifo buffer */ 3075 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, 3076 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3077 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3078 if (ret_val) 3079 return ret_val; 3080 3081 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); 3082 } 3083 3084 /** 3085 * e1000_check_polarity_82577 - Checks the polarity. 3086 * @hw: pointer to the HW structure 3087 * 3088 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3089 * 3090 * Polarity is determined based on the PHY specific status register. 3091 **/ 3092 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3093 { 3094 struct e1000_phy_info *phy = &hw->phy; 3095 s32 ret_val; 3096 u16 data; 3097 3098 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3099 3100 if (!ret_val) 3101 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3102 ? e1000_rev_polarity_reversed 3103 : e1000_rev_polarity_normal); 3104 3105 return ret_val; 3106 } 3107 3108 /** 3109 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3110 * @hw: pointer to the HW structure 3111 * 3112 * Calls the PHY setup function to force speed and duplex. 3113 **/ 3114 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3115 { 3116 struct e1000_phy_info *phy = &hw->phy; 3117 s32 ret_val; 3118 u16 phy_data; 3119 bool link; 3120 3121 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 3122 if (ret_val) 3123 return ret_val; 3124 3125 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3126 3127 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 3128 if (ret_val) 3129 return ret_val; 3130 3131 udelay(1); 3132 3133 if (phy->autoneg_wait_to_complete) { 3134 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); 3135 3136 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3137 100000, &link); 3138 if (ret_val) 3139 return ret_val; 3140 3141 if (!link) 3142 e_dbg("Link taking longer than expected.\n"); 3143 3144 /* Try once more */ 3145 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3146 100000, &link); 3147 } 3148 3149 return ret_val; 3150 } 3151 3152 /** 3153 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3154 * @hw: pointer to the HW structure 3155 * 3156 * Read PHY status to determine if link is up. If link is up, then 3157 * set/determine 10base-T extended distance and polarity correction. Read 3158 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3159 * determine on the cable length, local and remote receiver. 3160 **/ 3161 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3162 { 3163 struct e1000_phy_info *phy = &hw->phy; 3164 s32 ret_val; 3165 u16 data; 3166 bool link; 3167 3168 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3169 if (ret_val) 3170 return ret_val; 3171 3172 if (!link) { 3173 e_dbg("Phy info is only valid if link is up\n"); 3174 return -E1000_ERR_CONFIG; 3175 } 3176 3177 phy->polarity_correction = true; 3178 3179 ret_val = e1000_check_polarity_82577(hw); 3180 if (ret_val) 3181 return ret_val; 3182 3183 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 3184 if (ret_val) 3185 return ret_val; 3186 3187 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3188 3189 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3190 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3191 ret_val = hw->phy.ops.get_cable_length(hw); 3192 if (ret_val) 3193 return ret_val; 3194 3195 ret_val = e1e_rphy(hw, MII_STAT1000, &data); 3196 if (ret_val) 3197 return ret_val; 3198 3199 phy->local_rx = (data & LPA_1000LOCALRXOK) 3200 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3201 3202 phy->remote_rx = (data & LPA_1000REMRXOK) 3203 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3204 } else { 3205 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3206 phy->local_rx = e1000_1000t_rx_status_undefined; 3207 phy->remote_rx = e1000_1000t_rx_status_undefined; 3208 } 3209 3210 return 0; 3211 } 3212 3213 /** 3214 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3215 * @hw: pointer to the HW structure 3216 * 3217 * Reads the diagnostic status register and verifies result is valid before 3218 * placing it in the phy_cable_length field. 3219 **/ 3220 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3221 { 3222 struct e1000_phy_info *phy = &hw->phy; 3223 s32 ret_val; 3224 u16 phy_data, length; 3225 3226 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3227 if (ret_val) 3228 return ret_val; 3229 3230 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3231 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 3232 3233 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3234 return -E1000_ERR_PHY; 3235 3236 phy->cable_length = length; 3237 3238 return 0; 3239 } 3240