1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "e1000.h" 30 31 /** 32 * e1000_raise_eec_clk - Raise EEPROM clock 33 * @hw: pointer to the HW structure 34 * @eecd: pointer to the EEPROM 35 * 36 * Enable/Raise the EEPROM clock bit. 37 **/ 38 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 39 { 40 *eecd = *eecd | E1000_EECD_SK; 41 ew32(EECD, *eecd); 42 e1e_flush(); 43 udelay(hw->nvm.delay_usec); 44 } 45 46 /** 47 * e1000_lower_eec_clk - Lower EEPROM clock 48 * @hw: pointer to the HW structure 49 * @eecd: pointer to the EEPROM 50 * 51 * Clear/Lower the EEPROM clock bit. 52 **/ 53 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 54 { 55 *eecd = *eecd & ~E1000_EECD_SK; 56 ew32(EECD, *eecd); 57 e1e_flush(); 58 udelay(hw->nvm.delay_usec); 59 } 60 61 /** 62 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 63 * @hw: pointer to the HW structure 64 * @data: data to send to the EEPROM 65 * @count: number of bits to shift out 66 * 67 * We need to shift 'count' bits out to the EEPROM. So, the value in the 68 * "data" parameter will be shifted out to the EEPROM one bit at a time. 69 * In order to do this, "data" must be broken down into bits. 70 **/ 71 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 72 { 73 struct e1000_nvm_info *nvm = &hw->nvm; 74 u32 eecd = er32(EECD); 75 u32 mask; 76 77 mask = 0x01 << (count - 1); 78 if (nvm->type == e1000_nvm_eeprom_spi) 79 eecd |= E1000_EECD_DO; 80 81 do { 82 eecd &= ~E1000_EECD_DI; 83 84 if (data & mask) 85 eecd |= E1000_EECD_DI; 86 87 ew32(EECD, eecd); 88 e1e_flush(); 89 90 udelay(nvm->delay_usec); 91 92 e1000_raise_eec_clk(hw, &eecd); 93 e1000_lower_eec_clk(hw, &eecd); 94 95 mask >>= 1; 96 } while (mask); 97 98 eecd &= ~E1000_EECD_DI; 99 ew32(EECD, eecd); 100 } 101 102 /** 103 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 104 * @hw: pointer to the HW structure 105 * @count: number of bits to shift in 106 * 107 * In order to read a register from the EEPROM, we need to shift 'count' bits 108 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 109 * the EEPROM (setting the SK bit), and then reading the value of the data out 110 * "DO" bit. During this "shifting in" process the data in "DI" bit should 111 * always be clear. 112 **/ 113 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 114 { 115 u32 eecd; 116 u32 i; 117 u16 data; 118 119 eecd = er32(EECD); 120 121 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 122 data = 0; 123 124 for (i = 0; i < count; i++) { 125 data <<= 1; 126 e1000_raise_eec_clk(hw, &eecd); 127 128 eecd = er32(EECD); 129 130 eecd &= ~E1000_EECD_DI; 131 if (eecd & E1000_EECD_DO) 132 data |= 1; 133 134 e1000_lower_eec_clk(hw, &eecd); 135 } 136 137 return data; 138 } 139 140 /** 141 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion 142 * @hw: pointer to the HW structure 143 * @ee_reg: EEPROM flag for polling 144 * 145 * Polls the EEPROM status bit for either read or write completion based 146 * upon the value of 'ee_reg'. 147 **/ 148 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 149 { 150 u32 attempts = 100000; 151 u32 i, reg = 0; 152 153 for (i = 0; i < attempts; i++) { 154 if (ee_reg == E1000_NVM_POLL_READ) 155 reg = er32(EERD); 156 else 157 reg = er32(EEWR); 158 159 if (reg & E1000_NVM_RW_REG_DONE) 160 return 0; 161 162 udelay(5); 163 } 164 165 return -E1000_ERR_NVM; 166 } 167 168 /** 169 * e1000e_acquire_nvm - Generic request for access to EEPROM 170 * @hw: pointer to the HW structure 171 * 172 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 173 * Return successful if access grant bit set, else clear the request for 174 * EEPROM access and return -E1000_ERR_NVM (-1). 175 **/ 176 s32 e1000e_acquire_nvm(struct e1000_hw *hw) 177 { 178 u32 eecd = er32(EECD); 179 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 180 181 ew32(EECD, eecd | E1000_EECD_REQ); 182 eecd = er32(EECD); 183 184 while (timeout) { 185 if (eecd & E1000_EECD_GNT) 186 break; 187 udelay(5); 188 eecd = er32(EECD); 189 timeout--; 190 } 191 192 if (!timeout) { 193 eecd &= ~E1000_EECD_REQ; 194 ew32(EECD, eecd); 195 e_dbg("Could not acquire NVM grant\n"); 196 return -E1000_ERR_NVM; 197 } 198 199 return 0; 200 } 201 202 /** 203 * e1000_standby_nvm - Return EEPROM to standby state 204 * @hw: pointer to the HW structure 205 * 206 * Return the EEPROM to a standby state. 207 **/ 208 static void e1000_standby_nvm(struct e1000_hw *hw) 209 { 210 struct e1000_nvm_info *nvm = &hw->nvm; 211 u32 eecd = er32(EECD); 212 213 if (nvm->type == e1000_nvm_eeprom_spi) { 214 /* Toggle CS to flush commands */ 215 eecd |= E1000_EECD_CS; 216 ew32(EECD, eecd); 217 e1e_flush(); 218 udelay(nvm->delay_usec); 219 eecd &= ~E1000_EECD_CS; 220 ew32(EECD, eecd); 221 e1e_flush(); 222 udelay(nvm->delay_usec); 223 } 224 } 225 226 /** 227 * e1000_stop_nvm - Terminate EEPROM command 228 * @hw: pointer to the HW structure 229 * 230 * Terminates the current command by inverting the EEPROM's chip select pin. 231 **/ 232 static void e1000_stop_nvm(struct e1000_hw *hw) 233 { 234 u32 eecd; 235 236 eecd = er32(EECD); 237 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 238 /* Pull CS high */ 239 eecd |= E1000_EECD_CS; 240 e1000_lower_eec_clk(hw, &eecd); 241 } 242 } 243 244 /** 245 * e1000e_release_nvm - Release exclusive access to EEPROM 246 * @hw: pointer to the HW structure 247 * 248 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 249 **/ 250 void e1000e_release_nvm(struct e1000_hw *hw) 251 { 252 u32 eecd; 253 254 e1000_stop_nvm(hw); 255 256 eecd = er32(EECD); 257 eecd &= ~E1000_EECD_REQ; 258 ew32(EECD, eecd); 259 } 260 261 /** 262 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 263 * @hw: pointer to the HW structure 264 * 265 * Setups the EEPROM for reading and writing. 266 **/ 267 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 268 { 269 struct e1000_nvm_info *nvm = &hw->nvm; 270 u32 eecd = er32(EECD); 271 u8 spi_stat_reg; 272 273 if (nvm->type == e1000_nvm_eeprom_spi) { 274 u16 timeout = NVM_MAX_RETRY_SPI; 275 276 /* Clear SK and CS */ 277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 278 ew32(EECD, eecd); 279 e1e_flush(); 280 udelay(1); 281 282 /* 283 * Read "Status Register" repeatedly until the LSB is cleared. 284 * The EEPROM will signal that the command has been completed 285 * by clearing bit 0 of the internal status register. If it's 286 * not cleared within 'timeout', then error out. 287 */ 288 while (timeout) { 289 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 290 hw->nvm.opcode_bits); 291 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 292 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 293 break; 294 295 udelay(5); 296 e1000_standby_nvm(hw); 297 timeout--; 298 } 299 300 if (!timeout) { 301 e_dbg("SPI NVM Status error\n"); 302 return -E1000_ERR_NVM; 303 } 304 } 305 306 return 0; 307 } 308 309 /** 310 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register 311 * @hw: pointer to the HW structure 312 * @offset: offset of word in the EEPROM to read 313 * @words: number of words to read 314 * @data: word read from the EEPROM 315 * 316 * Reads a 16 bit word from the EEPROM using the EERD register. 317 **/ 318 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 319 { 320 struct e1000_nvm_info *nvm = &hw->nvm; 321 u32 i, eerd = 0; 322 s32 ret_val = 0; 323 324 /* 325 * A check for invalid values: offset too large, too many words, 326 * too many words for the offset, and not enough words. 327 */ 328 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 329 (words == 0)) { 330 e_dbg("nvm parameter(s) out of bounds\n"); 331 return -E1000_ERR_NVM; 332 } 333 334 for (i = 0; i < words; i++) { 335 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 336 E1000_NVM_RW_REG_START; 337 338 ew32(EERD, eerd); 339 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 340 if (ret_val) 341 break; 342 343 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); 344 } 345 346 return ret_val; 347 } 348 349 /** 350 * e1000e_write_nvm_spi - Write to EEPROM using SPI 351 * @hw: pointer to the HW structure 352 * @offset: offset within the EEPROM to be written to 353 * @words: number of words to write 354 * @data: 16 bit word(s) to be written to the EEPROM 355 * 356 * Writes data to EEPROM at offset using SPI interface. 357 * 358 * If e1000e_update_nvm_checksum is not called after this function , the 359 * EEPROM will most likely contain an invalid checksum. 360 **/ 361 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 362 { 363 struct e1000_nvm_info *nvm = &hw->nvm; 364 s32 ret_val; 365 u16 widx = 0; 366 367 /* 368 * A check for invalid values: offset too large, too many words, 369 * and not enough words. 370 */ 371 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 372 (words == 0)) { 373 e_dbg("nvm parameter(s) out of bounds\n"); 374 return -E1000_ERR_NVM; 375 } 376 377 ret_val = nvm->ops.acquire(hw); 378 if (ret_val) 379 return ret_val; 380 381 while (widx < words) { 382 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 383 384 ret_val = e1000_ready_nvm_eeprom(hw); 385 if (ret_val) 386 goto release; 387 388 e1000_standby_nvm(hw); 389 390 /* Send the WRITE ENABLE command (8 bit opcode) */ 391 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 392 nvm->opcode_bits); 393 394 e1000_standby_nvm(hw); 395 396 /* 397 * Some SPI eeproms use the 8th address bit embedded in the 398 * opcode 399 */ 400 if ((nvm->address_bits == 8) && (offset >= 128)) 401 write_opcode |= NVM_A8_OPCODE_SPI; 402 403 /* Send the Write command (8-bit opcode + addr) */ 404 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 405 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 406 nvm->address_bits); 407 408 /* Loop to allow for up to whole page write of eeprom */ 409 while (widx < words) { 410 u16 word_out = data[widx]; 411 word_out = (word_out >> 8) | (word_out << 8); 412 e1000_shift_out_eec_bits(hw, word_out, 16); 413 widx++; 414 415 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 416 e1000_standby_nvm(hw); 417 break; 418 } 419 } 420 } 421 422 usleep_range(10000, 20000); 423 release: 424 nvm->ops.release(hw); 425 426 return ret_val; 427 } 428 429 /** 430 * e1000_read_pba_string_generic - Read device part number 431 * @hw: pointer to the HW structure 432 * @pba_num: pointer to device part number 433 * @pba_num_size: size of part number buffer 434 * 435 * Reads the product board assembly (PBA) number from the EEPROM and stores 436 * the value in pba_num. 437 **/ 438 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 439 u32 pba_num_size) 440 { 441 s32 ret_val; 442 u16 nvm_data; 443 u16 pba_ptr; 444 u16 offset; 445 u16 length; 446 447 if (pba_num == NULL) { 448 e_dbg("PBA string buffer was null\n"); 449 return -E1000_ERR_INVALID_ARGUMENT; 450 } 451 452 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 453 if (ret_val) { 454 e_dbg("NVM Read Error\n"); 455 return ret_val; 456 } 457 458 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 459 if (ret_val) { 460 e_dbg("NVM Read Error\n"); 461 return ret_val; 462 } 463 464 /* 465 * if nvm_data is not ptr guard the PBA must be in legacy format which 466 * means pba_ptr is actually our second data word for the PBA number 467 * and we can decode it into an ascii string 468 */ 469 if (nvm_data != NVM_PBA_PTR_GUARD) { 470 e_dbg("NVM PBA number is not stored as string\n"); 471 472 /* we will need 11 characters to store the PBA */ 473 if (pba_num_size < 11) { 474 e_dbg("PBA string buffer too small\n"); 475 return E1000_ERR_NO_SPACE; 476 } 477 478 /* extract hex string from data and pba_ptr */ 479 pba_num[0] = (nvm_data >> 12) & 0xF; 480 pba_num[1] = (nvm_data >> 8) & 0xF; 481 pba_num[2] = (nvm_data >> 4) & 0xF; 482 pba_num[3] = nvm_data & 0xF; 483 pba_num[4] = (pba_ptr >> 12) & 0xF; 484 pba_num[5] = (pba_ptr >> 8) & 0xF; 485 pba_num[6] = '-'; 486 pba_num[7] = 0; 487 pba_num[8] = (pba_ptr >> 4) & 0xF; 488 pba_num[9] = pba_ptr & 0xF; 489 490 /* put a null character on the end of our string */ 491 pba_num[10] = '\0'; 492 493 /* switch all the data but the '-' to hex char */ 494 for (offset = 0; offset < 10; offset++) { 495 if (pba_num[offset] < 0xA) 496 pba_num[offset] += '0'; 497 else if (pba_num[offset] < 0x10) 498 pba_num[offset] += 'A' - 0xA; 499 } 500 501 return 0; 502 } 503 504 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); 505 if (ret_val) { 506 e_dbg("NVM Read Error\n"); 507 return ret_val; 508 } 509 510 if (length == 0xFFFF || length == 0) { 511 e_dbg("NVM PBA number section invalid length\n"); 512 return -E1000_ERR_NVM_PBA_SECTION; 513 } 514 /* check if pba_num buffer is big enough */ 515 if (pba_num_size < (((u32)length * 2) - 1)) { 516 e_dbg("PBA string buffer too small\n"); 517 return -E1000_ERR_NO_SPACE; 518 } 519 520 /* trim pba length from start of string */ 521 pba_ptr++; 522 length--; 523 524 for (offset = 0; offset < length; offset++) { 525 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); 526 if (ret_val) { 527 e_dbg("NVM Read Error\n"); 528 return ret_val; 529 } 530 pba_num[offset * 2] = (u8)(nvm_data >> 8); 531 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 532 } 533 pba_num[offset * 2] = '\0'; 534 535 return 0; 536 } 537 538 /** 539 * e1000_read_mac_addr_generic - Read device MAC address 540 * @hw: pointer to the HW structure 541 * 542 * Reads the device MAC address from the EEPROM and stores the value. 543 * Since devices with two ports use the same EEPROM, we increment the 544 * last bit in the MAC address for the second port. 545 **/ 546 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 547 { 548 u32 rar_high; 549 u32 rar_low; 550 u16 i; 551 552 rar_high = er32(RAH(0)); 553 rar_low = er32(RAL(0)); 554 555 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 556 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); 557 558 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 559 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); 560 561 for (i = 0; i < ETH_ALEN; i++) 562 hw->mac.addr[i] = hw->mac.perm_addr[i]; 563 564 return 0; 565 } 566 567 /** 568 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum 569 * @hw: pointer to the HW structure 570 * 571 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 572 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 573 **/ 574 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) 575 { 576 s32 ret_val; 577 u16 checksum = 0; 578 u16 i, nvm_data; 579 580 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 581 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 582 if (ret_val) { 583 e_dbg("NVM Read Error\n"); 584 return ret_val; 585 } 586 checksum += nvm_data; 587 } 588 589 if (checksum != (u16)NVM_SUM) { 590 e_dbg("NVM Checksum Invalid\n"); 591 return -E1000_ERR_NVM; 592 } 593 594 return 0; 595 } 596 597 /** 598 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum 599 * @hw: pointer to the HW structure 600 * 601 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 602 * up to the checksum. Then calculates the EEPROM checksum and writes the 603 * value to the EEPROM. 604 **/ 605 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) 606 { 607 s32 ret_val; 608 u16 checksum = 0; 609 u16 i, nvm_data; 610 611 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 612 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 613 if (ret_val) { 614 e_dbg("NVM Read Error while updating checksum.\n"); 615 return ret_val; 616 } 617 checksum += nvm_data; 618 } 619 checksum = (u16)NVM_SUM - checksum; 620 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 621 if (ret_val) 622 e_dbg("NVM Write Error while updating checksum.\n"); 623 624 return ret_val; 625 } 626 627 /** 628 * e1000e_reload_nvm_generic - Reloads EEPROM 629 * @hw: pointer to the HW structure 630 * 631 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 632 * extended control register. 633 **/ 634 void e1000e_reload_nvm_generic(struct e1000_hw *hw) 635 { 636 u32 ctrl_ext; 637 638 udelay(10); 639 ctrl_ext = er32(CTRL_EXT); 640 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 641 ew32(CTRL_EXT, ctrl_ext); 642 e1e_flush(); 643 } 644