1 /*******************************************************************************
2 
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2013 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #include "e1000.h"
30 
31 /**
32  *  e1000_raise_eec_clk - Raise EEPROM clock
33  *  @hw: pointer to the HW structure
34  *  @eecd: pointer to the EEPROM
35  *
36  *  Enable/Raise the EEPROM clock bit.
37  **/
38 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
39 {
40 	*eecd = *eecd | E1000_EECD_SK;
41 	ew32(EECD, *eecd);
42 	e1e_flush();
43 	udelay(hw->nvm.delay_usec);
44 }
45 
46 /**
47  *  e1000_lower_eec_clk - Lower EEPROM clock
48  *  @hw: pointer to the HW structure
49  *  @eecd: pointer to the EEPROM
50  *
51  *  Clear/Lower the EEPROM clock bit.
52  **/
53 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
54 {
55 	*eecd = *eecd & ~E1000_EECD_SK;
56 	ew32(EECD, *eecd);
57 	e1e_flush();
58 	udelay(hw->nvm.delay_usec);
59 }
60 
61 /**
62  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
63  *  @hw: pointer to the HW structure
64  *  @data: data to send to the EEPROM
65  *  @count: number of bits to shift out
66  *
67  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
68  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
69  *  In order to do this, "data" must be broken down into bits.
70  **/
71 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
72 {
73 	struct e1000_nvm_info *nvm = &hw->nvm;
74 	u32 eecd = er32(EECD);
75 	u32 mask;
76 
77 	mask = 0x01 << (count - 1);
78 	if (nvm->type == e1000_nvm_eeprom_spi)
79 		eecd |= E1000_EECD_DO;
80 
81 	do {
82 		eecd &= ~E1000_EECD_DI;
83 
84 		if (data & mask)
85 			eecd |= E1000_EECD_DI;
86 
87 		ew32(EECD, eecd);
88 		e1e_flush();
89 
90 		udelay(nvm->delay_usec);
91 
92 		e1000_raise_eec_clk(hw, &eecd);
93 		e1000_lower_eec_clk(hw, &eecd);
94 
95 		mask >>= 1;
96 	} while (mask);
97 
98 	eecd &= ~E1000_EECD_DI;
99 	ew32(EECD, eecd);
100 }
101 
102 /**
103  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
104  *  @hw: pointer to the HW structure
105  *  @count: number of bits to shift in
106  *
107  *  In order to read a register from the EEPROM, we need to shift 'count' bits
108  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
109  *  the EEPROM (setting the SK bit), and then reading the value of the data out
110  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
111  *  always be clear.
112  **/
113 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
114 {
115 	u32 eecd;
116 	u32 i;
117 	u16 data;
118 
119 	eecd = er32(EECD);
120 
121 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
122 	data = 0;
123 
124 	for (i = 0; i < count; i++) {
125 		data <<= 1;
126 		e1000_raise_eec_clk(hw, &eecd);
127 
128 		eecd = er32(EECD);
129 
130 		eecd &= ~E1000_EECD_DI;
131 		if (eecd & E1000_EECD_DO)
132 			data |= 1;
133 
134 		e1000_lower_eec_clk(hw, &eecd);
135 	}
136 
137 	return data;
138 }
139 
140 /**
141  *  e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
142  *  @hw: pointer to the HW structure
143  *  @ee_reg: EEPROM flag for polling
144  *
145  *  Polls the EEPROM status bit for either read or write completion based
146  *  upon the value of 'ee_reg'.
147  **/
148 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
149 {
150 	u32 attempts = 100000;
151 	u32 i, reg = 0;
152 
153 	for (i = 0; i < attempts; i++) {
154 		if (ee_reg == E1000_NVM_POLL_READ)
155 			reg = er32(EERD);
156 		else
157 			reg = er32(EEWR);
158 
159 		if (reg & E1000_NVM_RW_REG_DONE)
160 			return 0;
161 
162 		udelay(5);
163 	}
164 
165 	return -E1000_ERR_NVM;
166 }
167 
168 /**
169  *  e1000e_acquire_nvm - Generic request for access to EEPROM
170  *  @hw: pointer to the HW structure
171  *
172  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
173  *  Return successful if access grant bit set, else clear the request for
174  *  EEPROM access and return -E1000_ERR_NVM (-1).
175  **/
176 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
177 {
178 	u32 eecd = er32(EECD);
179 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
180 
181 	ew32(EECD, eecd | E1000_EECD_REQ);
182 	eecd = er32(EECD);
183 
184 	while (timeout) {
185 		if (eecd & E1000_EECD_GNT)
186 			break;
187 		udelay(5);
188 		eecd = er32(EECD);
189 		timeout--;
190 	}
191 
192 	if (!timeout) {
193 		eecd &= ~E1000_EECD_REQ;
194 		ew32(EECD, eecd);
195 		e_dbg("Could not acquire NVM grant\n");
196 		return -E1000_ERR_NVM;
197 	}
198 
199 	return 0;
200 }
201 
202 /**
203  *  e1000_standby_nvm - Return EEPROM to standby state
204  *  @hw: pointer to the HW structure
205  *
206  *  Return the EEPROM to a standby state.
207  **/
208 static void e1000_standby_nvm(struct e1000_hw *hw)
209 {
210 	struct e1000_nvm_info *nvm = &hw->nvm;
211 	u32 eecd = er32(EECD);
212 
213 	if (nvm->type == e1000_nvm_eeprom_spi) {
214 		/* Toggle CS to flush commands */
215 		eecd |= E1000_EECD_CS;
216 		ew32(EECD, eecd);
217 		e1e_flush();
218 		udelay(nvm->delay_usec);
219 		eecd &= ~E1000_EECD_CS;
220 		ew32(EECD, eecd);
221 		e1e_flush();
222 		udelay(nvm->delay_usec);
223 	}
224 }
225 
226 /**
227  *  e1000_stop_nvm - Terminate EEPROM command
228  *  @hw: pointer to the HW structure
229  *
230  *  Terminates the current command by inverting the EEPROM's chip select pin.
231  **/
232 static void e1000_stop_nvm(struct e1000_hw *hw)
233 {
234 	u32 eecd;
235 
236 	eecd = er32(EECD);
237 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
238 		/* Pull CS high */
239 		eecd |= E1000_EECD_CS;
240 		e1000_lower_eec_clk(hw, &eecd);
241 	}
242 }
243 
244 /**
245  *  e1000e_release_nvm - Release exclusive access to EEPROM
246  *  @hw: pointer to the HW structure
247  *
248  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
249  **/
250 void e1000e_release_nvm(struct e1000_hw *hw)
251 {
252 	u32 eecd;
253 
254 	e1000_stop_nvm(hw);
255 
256 	eecd = er32(EECD);
257 	eecd &= ~E1000_EECD_REQ;
258 	ew32(EECD, eecd);
259 }
260 
261 /**
262  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
263  *  @hw: pointer to the HW structure
264  *
265  *  Setups the EEPROM for reading and writing.
266  **/
267 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
268 {
269 	struct e1000_nvm_info *nvm = &hw->nvm;
270 	u32 eecd = er32(EECD);
271 	u8 spi_stat_reg;
272 
273 	if (nvm->type == e1000_nvm_eeprom_spi) {
274 		u16 timeout = NVM_MAX_RETRY_SPI;
275 
276 		/* Clear SK and CS */
277 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
278 		ew32(EECD, eecd);
279 		e1e_flush();
280 		udelay(1);
281 
282 		/* Read "Status Register" repeatedly until the LSB is cleared.
283 		 * The EEPROM will signal that the command has been completed
284 		 * by clearing bit 0 of the internal status register.  If it's
285 		 * not cleared within 'timeout', then error out.
286 		 */
287 		while (timeout) {
288 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
289 						 hw->nvm.opcode_bits);
290 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
291 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
292 				break;
293 
294 			udelay(5);
295 			e1000_standby_nvm(hw);
296 			timeout--;
297 		}
298 
299 		if (!timeout) {
300 			e_dbg("SPI NVM Status error\n");
301 			return -E1000_ERR_NVM;
302 		}
303 	}
304 
305 	return 0;
306 }
307 
308 /**
309  *  e1000e_read_nvm_eerd - Reads EEPROM using EERD register
310  *  @hw: pointer to the HW structure
311  *  @offset: offset of word in the EEPROM to read
312  *  @words: number of words to read
313  *  @data: word read from the EEPROM
314  *
315  *  Reads a 16 bit word from the EEPROM using the EERD register.
316  **/
317 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
318 {
319 	struct e1000_nvm_info *nvm = &hw->nvm;
320 	u32 i, eerd = 0;
321 	s32 ret_val = 0;
322 
323 	/* A check for invalid values:  offset too large, too many words,
324 	 * too many words for the offset, and not enough words.
325 	 */
326 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
327 	    (words == 0)) {
328 		e_dbg("nvm parameter(s) out of bounds\n");
329 		return -E1000_ERR_NVM;
330 	}
331 
332 	for (i = 0; i < words; i++) {
333 		eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
334 		    E1000_NVM_RW_REG_START;
335 
336 		ew32(EERD, eerd);
337 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
338 		if (ret_val)
339 			break;
340 
341 		data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
342 	}
343 
344 	return ret_val;
345 }
346 
347 /**
348  *  e1000e_write_nvm_spi - Write to EEPROM using SPI
349  *  @hw: pointer to the HW structure
350  *  @offset: offset within the EEPROM to be written to
351  *  @words: number of words to write
352  *  @data: 16 bit word(s) to be written to the EEPROM
353  *
354  *  Writes data to EEPROM at offset using SPI interface.
355  *
356  *  If e1000e_update_nvm_checksum is not called after this function , the
357  *  EEPROM will most likely contain an invalid checksum.
358  **/
359 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
360 {
361 	struct e1000_nvm_info *nvm = &hw->nvm;
362 	s32 ret_val = -E1000_ERR_NVM;
363 	u16 widx = 0;
364 
365 	/* A check for invalid values:  offset too large, too many words,
366 	 * and not enough words.
367 	 */
368 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
369 	    (words == 0)) {
370 		e_dbg("nvm parameter(s) out of bounds\n");
371 		return -E1000_ERR_NVM;
372 	}
373 
374 	while (widx < words) {
375 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
376 
377 		ret_val = nvm->ops.acquire(hw);
378 		if (ret_val)
379 			return ret_val;
380 
381 		ret_val = e1000_ready_nvm_eeprom(hw);
382 		if (ret_val) {
383 			nvm->ops.release(hw);
384 			return ret_val;
385 		}
386 
387 		e1000_standby_nvm(hw);
388 
389 		/* Send the WRITE ENABLE command (8 bit opcode) */
390 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
391 					 nvm->opcode_bits);
392 
393 		e1000_standby_nvm(hw);
394 
395 		/* Some SPI eeproms use the 8th address bit embedded in the
396 		 * opcode
397 		 */
398 		if ((nvm->address_bits == 8) && (offset >= 128))
399 			write_opcode |= NVM_A8_OPCODE_SPI;
400 
401 		/* Send the Write command (8-bit opcode + addr) */
402 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
403 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
404 					 nvm->address_bits);
405 
406 		/* Loop to allow for up to whole page write of eeprom */
407 		while (widx < words) {
408 			u16 word_out = data[widx];
409 			word_out = (word_out >> 8) | (word_out << 8);
410 			e1000_shift_out_eec_bits(hw, word_out, 16);
411 			widx++;
412 
413 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
414 				e1000_standby_nvm(hw);
415 				break;
416 			}
417 		}
418 		usleep_range(10000, 20000);
419 		nvm->ops.release(hw);
420 	}
421 
422 	return ret_val;
423 }
424 
425 /**
426  *  e1000_read_pba_string_generic - Read device part number
427  *  @hw: pointer to the HW structure
428  *  @pba_num: pointer to device part number
429  *  @pba_num_size: size of part number buffer
430  *
431  *  Reads the product board assembly (PBA) number from the EEPROM and stores
432  *  the value in pba_num.
433  **/
434 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
435 				  u32 pba_num_size)
436 {
437 	s32 ret_val;
438 	u16 nvm_data;
439 	u16 pba_ptr;
440 	u16 offset;
441 	u16 length;
442 
443 	if (pba_num == NULL) {
444 		e_dbg("PBA string buffer was null\n");
445 		return -E1000_ERR_INVALID_ARGUMENT;
446 	}
447 
448 	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
449 	if (ret_val) {
450 		e_dbg("NVM Read Error\n");
451 		return ret_val;
452 	}
453 
454 	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
455 	if (ret_val) {
456 		e_dbg("NVM Read Error\n");
457 		return ret_val;
458 	}
459 
460 	/* if nvm_data is not ptr guard the PBA must be in legacy format which
461 	 * means pba_ptr is actually our second data word for the PBA number
462 	 * and we can decode it into an ascii string
463 	 */
464 	if (nvm_data != NVM_PBA_PTR_GUARD) {
465 		e_dbg("NVM PBA number is not stored as string\n");
466 
467 		/* make sure callers buffer is big enough to store the PBA */
468 		if (pba_num_size < E1000_PBANUM_LENGTH) {
469 			e_dbg("PBA string buffer too small\n");
470 			return E1000_ERR_NO_SPACE;
471 		}
472 
473 		/* extract hex string from data and pba_ptr */
474 		pba_num[0] = (nvm_data >> 12) & 0xF;
475 		pba_num[1] = (nvm_data >> 8) & 0xF;
476 		pba_num[2] = (nvm_data >> 4) & 0xF;
477 		pba_num[3] = nvm_data & 0xF;
478 		pba_num[4] = (pba_ptr >> 12) & 0xF;
479 		pba_num[5] = (pba_ptr >> 8) & 0xF;
480 		pba_num[6] = '-';
481 		pba_num[7] = 0;
482 		pba_num[8] = (pba_ptr >> 4) & 0xF;
483 		pba_num[9] = pba_ptr & 0xF;
484 
485 		/* put a null character on the end of our string */
486 		pba_num[10] = '\0';
487 
488 		/* switch all the data but the '-' to hex char */
489 		for (offset = 0; offset < 10; offset++) {
490 			if (pba_num[offset] < 0xA)
491 				pba_num[offset] += '0';
492 			else if (pba_num[offset] < 0x10)
493 				pba_num[offset] += 'A' - 0xA;
494 		}
495 
496 		return 0;
497 	}
498 
499 	ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
500 	if (ret_val) {
501 		e_dbg("NVM Read Error\n");
502 		return ret_val;
503 	}
504 
505 	if (length == 0xFFFF || length == 0) {
506 		e_dbg("NVM PBA number section invalid length\n");
507 		return -E1000_ERR_NVM_PBA_SECTION;
508 	}
509 	/* check if pba_num buffer is big enough */
510 	if (pba_num_size < (((u32)length * 2) - 1)) {
511 		e_dbg("PBA string buffer too small\n");
512 		return -E1000_ERR_NO_SPACE;
513 	}
514 
515 	/* trim pba length from start of string */
516 	pba_ptr++;
517 	length--;
518 
519 	for (offset = 0; offset < length; offset++) {
520 		ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
521 		if (ret_val) {
522 			e_dbg("NVM Read Error\n");
523 			return ret_val;
524 		}
525 		pba_num[offset * 2] = (u8)(nvm_data >> 8);
526 		pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
527 	}
528 	pba_num[offset * 2] = '\0';
529 
530 	return 0;
531 }
532 
533 /**
534  *  e1000_read_mac_addr_generic - Read device MAC address
535  *  @hw: pointer to the HW structure
536  *
537  *  Reads the device MAC address from the EEPROM and stores the value.
538  *  Since devices with two ports use the same EEPROM, we increment the
539  *  last bit in the MAC address for the second port.
540  **/
541 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
542 {
543 	u32 rar_high;
544 	u32 rar_low;
545 	u16 i;
546 
547 	rar_high = er32(RAH(0));
548 	rar_low = er32(RAL(0));
549 
550 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
551 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
552 
553 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
554 		hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
555 
556 	for (i = 0; i < ETH_ALEN; i++)
557 		hw->mac.addr[i] = hw->mac.perm_addr[i];
558 
559 	return 0;
560 }
561 
562 /**
563  *  e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
564  *  @hw: pointer to the HW structure
565  *
566  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
567  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
568  **/
569 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
570 {
571 	s32 ret_val;
572 	u16 checksum = 0;
573 	u16 i, nvm_data;
574 
575 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
576 		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
577 		if (ret_val) {
578 			e_dbg("NVM Read Error\n");
579 			return ret_val;
580 		}
581 		checksum += nvm_data;
582 	}
583 
584 	if (checksum != (u16)NVM_SUM) {
585 		e_dbg("NVM Checksum Invalid\n");
586 		return -E1000_ERR_NVM;
587 	}
588 
589 	return 0;
590 }
591 
592 /**
593  *  e1000e_update_nvm_checksum_generic - Update EEPROM checksum
594  *  @hw: pointer to the HW structure
595  *
596  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
597  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
598  *  value to the EEPROM.
599  **/
600 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
601 {
602 	s32 ret_val;
603 	u16 checksum = 0;
604 	u16 i, nvm_data;
605 
606 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
607 		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
608 		if (ret_val) {
609 			e_dbg("NVM Read Error while updating checksum.\n");
610 			return ret_val;
611 		}
612 		checksum += nvm_data;
613 	}
614 	checksum = (u16)NVM_SUM - checksum;
615 	ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
616 	if (ret_val)
617 		e_dbg("NVM Write Error while updating checksum.\n");
618 
619 	return ret_val;
620 }
621 
622 /**
623  *  e1000e_reload_nvm_generic - Reloads EEPROM
624  *  @hw: pointer to the HW structure
625  *
626  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
627  *  extended control register.
628  **/
629 void e1000e_reload_nvm_generic(struct e1000_hw *hw)
630 {
631 	u32 ctrl_ext;
632 
633 	usleep_range(10, 20);
634 	ctrl_ext = er32(CTRL_EXT);
635 	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
636 	ew32(CTRL_EXT, ctrl_ext);
637 	e1e_flush();
638 }
639