1 // SPDX-License-Identifier: GPL-2.0 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 #include "e1000.h" 24 25 /** 26 * e1000_raise_eec_clk - Raise EEPROM clock 27 * @hw: pointer to the HW structure 28 * @eecd: pointer to the EEPROM 29 * 30 * Enable/Raise the EEPROM clock bit. 31 **/ 32 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 33 { 34 *eecd = *eecd | E1000_EECD_SK; 35 ew32(EECD, *eecd); 36 e1e_flush(); 37 udelay(hw->nvm.delay_usec); 38 } 39 40 /** 41 * e1000_lower_eec_clk - Lower EEPROM clock 42 * @hw: pointer to the HW structure 43 * @eecd: pointer to the EEPROM 44 * 45 * Clear/Lower the EEPROM clock bit. 46 **/ 47 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 48 { 49 *eecd = *eecd & ~E1000_EECD_SK; 50 ew32(EECD, *eecd); 51 e1e_flush(); 52 udelay(hw->nvm.delay_usec); 53 } 54 55 /** 56 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 57 * @hw: pointer to the HW structure 58 * @data: data to send to the EEPROM 59 * @count: number of bits to shift out 60 * 61 * We need to shift 'count' bits out to the EEPROM. So, the value in the 62 * "data" parameter will be shifted out to the EEPROM one bit at a time. 63 * In order to do this, "data" must be broken down into bits. 64 **/ 65 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 66 { 67 struct e1000_nvm_info *nvm = &hw->nvm; 68 u32 eecd = er32(EECD); 69 u32 mask; 70 71 mask = BIT(count - 1); 72 if (nvm->type == e1000_nvm_eeprom_spi) 73 eecd |= E1000_EECD_DO; 74 75 do { 76 eecd &= ~E1000_EECD_DI; 77 78 if (data & mask) 79 eecd |= E1000_EECD_DI; 80 81 ew32(EECD, eecd); 82 e1e_flush(); 83 84 udelay(nvm->delay_usec); 85 86 e1000_raise_eec_clk(hw, &eecd); 87 e1000_lower_eec_clk(hw, &eecd); 88 89 mask >>= 1; 90 } while (mask); 91 92 eecd &= ~E1000_EECD_DI; 93 ew32(EECD, eecd); 94 } 95 96 /** 97 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 98 * @hw: pointer to the HW structure 99 * @count: number of bits to shift in 100 * 101 * In order to read a register from the EEPROM, we need to shift 'count' bits 102 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 103 * the EEPROM (setting the SK bit), and then reading the value of the data out 104 * "DO" bit. During this "shifting in" process the data in "DI" bit should 105 * always be clear. 106 **/ 107 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 108 { 109 u32 eecd; 110 u32 i; 111 u16 data; 112 113 eecd = er32(EECD); 114 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 115 data = 0; 116 117 for (i = 0; i < count; i++) { 118 data <<= 1; 119 e1000_raise_eec_clk(hw, &eecd); 120 121 eecd = er32(EECD); 122 123 eecd &= ~E1000_EECD_DI; 124 if (eecd & E1000_EECD_DO) 125 data |= 1; 126 127 e1000_lower_eec_clk(hw, &eecd); 128 } 129 130 return data; 131 } 132 133 /** 134 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion 135 * @hw: pointer to the HW structure 136 * @ee_reg: EEPROM flag for polling 137 * 138 * Polls the EEPROM status bit for either read or write completion based 139 * upon the value of 'ee_reg'. 140 **/ 141 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 142 { 143 u32 attempts = 100000; 144 u32 i, reg = 0; 145 146 for (i = 0; i < attempts; i++) { 147 if (ee_reg == E1000_NVM_POLL_READ) 148 reg = er32(EERD); 149 else 150 reg = er32(EEWR); 151 152 if (reg & E1000_NVM_RW_REG_DONE) 153 return 0; 154 155 udelay(5); 156 } 157 158 return -E1000_ERR_NVM; 159 } 160 161 /** 162 * e1000e_acquire_nvm - Generic request for access to EEPROM 163 * @hw: pointer to the HW structure 164 * 165 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 166 * Return successful if access grant bit set, else clear the request for 167 * EEPROM access and return -E1000_ERR_NVM (-1). 168 **/ 169 s32 e1000e_acquire_nvm(struct e1000_hw *hw) 170 { 171 u32 eecd = er32(EECD); 172 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 173 174 ew32(EECD, eecd | E1000_EECD_REQ); 175 eecd = er32(EECD); 176 177 while (timeout) { 178 if (eecd & E1000_EECD_GNT) 179 break; 180 udelay(5); 181 eecd = er32(EECD); 182 timeout--; 183 } 184 185 if (!timeout) { 186 eecd &= ~E1000_EECD_REQ; 187 ew32(EECD, eecd); 188 e_dbg("Could not acquire NVM grant\n"); 189 return -E1000_ERR_NVM; 190 } 191 192 return 0; 193 } 194 195 /** 196 * e1000_standby_nvm - Return EEPROM to standby state 197 * @hw: pointer to the HW structure 198 * 199 * Return the EEPROM to a standby state. 200 **/ 201 static void e1000_standby_nvm(struct e1000_hw *hw) 202 { 203 struct e1000_nvm_info *nvm = &hw->nvm; 204 u32 eecd = er32(EECD); 205 206 if (nvm->type == e1000_nvm_eeprom_spi) { 207 /* Toggle CS to flush commands */ 208 eecd |= E1000_EECD_CS; 209 ew32(EECD, eecd); 210 e1e_flush(); 211 udelay(nvm->delay_usec); 212 eecd &= ~E1000_EECD_CS; 213 ew32(EECD, eecd); 214 e1e_flush(); 215 udelay(nvm->delay_usec); 216 } 217 } 218 219 /** 220 * e1000_stop_nvm - Terminate EEPROM command 221 * @hw: pointer to the HW structure 222 * 223 * Terminates the current command by inverting the EEPROM's chip select pin. 224 **/ 225 static void e1000_stop_nvm(struct e1000_hw *hw) 226 { 227 u32 eecd; 228 229 eecd = er32(EECD); 230 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 231 /* Pull CS high */ 232 eecd |= E1000_EECD_CS; 233 e1000_lower_eec_clk(hw, &eecd); 234 } 235 } 236 237 /** 238 * e1000e_release_nvm - Release exclusive access to EEPROM 239 * @hw: pointer to the HW structure 240 * 241 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 242 **/ 243 void e1000e_release_nvm(struct e1000_hw *hw) 244 { 245 u32 eecd; 246 247 e1000_stop_nvm(hw); 248 249 eecd = er32(EECD); 250 eecd &= ~E1000_EECD_REQ; 251 ew32(EECD, eecd); 252 } 253 254 /** 255 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 256 * @hw: pointer to the HW structure 257 * 258 * Setups the EEPROM for reading and writing. 259 **/ 260 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 261 { 262 struct e1000_nvm_info *nvm = &hw->nvm; 263 u32 eecd = er32(EECD); 264 u8 spi_stat_reg; 265 266 if (nvm->type == e1000_nvm_eeprom_spi) { 267 u16 timeout = NVM_MAX_RETRY_SPI; 268 269 /* Clear SK and CS */ 270 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 271 ew32(EECD, eecd); 272 e1e_flush(); 273 udelay(1); 274 275 /* Read "Status Register" repeatedly until the LSB is cleared. 276 * The EEPROM will signal that the command has been completed 277 * by clearing bit 0 of the internal status register. If it's 278 * not cleared within 'timeout', then error out. 279 */ 280 while (timeout) { 281 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 282 hw->nvm.opcode_bits); 283 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 284 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 285 break; 286 287 udelay(5); 288 e1000_standby_nvm(hw); 289 timeout--; 290 } 291 292 if (!timeout) { 293 e_dbg("SPI NVM Status error\n"); 294 return -E1000_ERR_NVM; 295 } 296 } 297 298 return 0; 299 } 300 301 /** 302 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register 303 * @hw: pointer to the HW structure 304 * @offset: offset of word in the EEPROM to read 305 * @words: number of words to read 306 * @data: word read from the EEPROM 307 * 308 * Reads a 16 bit word from the EEPROM using the EERD register. 309 **/ 310 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 311 { 312 struct e1000_nvm_info *nvm = &hw->nvm; 313 u32 i, eerd = 0; 314 s32 ret_val = 0; 315 316 /* A check for invalid values: offset too large, too many words, 317 * too many words for the offset, and not enough words. 318 */ 319 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 320 (words == 0)) { 321 e_dbg("nvm parameter(s) out of bounds\n"); 322 return -E1000_ERR_NVM; 323 } 324 325 for (i = 0; i < words; i++) { 326 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 327 E1000_NVM_RW_REG_START; 328 329 ew32(EERD, eerd); 330 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 331 if (ret_val) { 332 e_dbg("NVM read error: %d\n", ret_val); 333 break; 334 } 335 336 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); 337 } 338 339 return ret_val; 340 } 341 342 /** 343 * e1000e_write_nvm_spi - Write to EEPROM using SPI 344 * @hw: pointer to the HW structure 345 * @offset: offset within the EEPROM to be written to 346 * @words: number of words to write 347 * @data: 16 bit word(s) to be written to the EEPROM 348 * 349 * Writes data to EEPROM at offset using SPI interface. 350 * 351 * If e1000e_update_nvm_checksum is not called after this function , the 352 * EEPROM will most likely contain an invalid checksum. 353 **/ 354 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 355 { 356 struct e1000_nvm_info *nvm = &hw->nvm; 357 s32 ret_val = -E1000_ERR_NVM; 358 u16 widx = 0; 359 360 /* A check for invalid values: offset too large, too many words, 361 * and not enough words. 362 */ 363 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 364 (words == 0)) { 365 e_dbg("nvm parameter(s) out of bounds\n"); 366 return -E1000_ERR_NVM; 367 } 368 369 while (widx < words) { 370 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 371 372 ret_val = nvm->ops.acquire(hw); 373 if (ret_val) 374 return ret_val; 375 376 ret_val = e1000_ready_nvm_eeprom(hw); 377 if (ret_val) { 378 nvm->ops.release(hw); 379 return ret_val; 380 } 381 382 e1000_standby_nvm(hw); 383 384 /* Send the WRITE ENABLE command (8 bit opcode) */ 385 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 386 nvm->opcode_bits); 387 388 e1000_standby_nvm(hw); 389 390 /* Some SPI eeproms use the 8th address bit embedded in the 391 * opcode 392 */ 393 if ((nvm->address_bits == 8) && (offset >= 128)) 394 write_opcode |= NVM_A8_OPCODE_SPI; 395 396 /* Send the Write command (8-bit opcode + addr) */ 397 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 398 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 399 nvm->address_bits); 400 401 /* Loop to allow for up to whole page write of eeprom */ 402 while (widx < words) { 403 u16 word_out = data[widx]; 404 405 word_out = (word_out >> 8) | (word_out << 8); 406 e1000_shift_out_eec_bits(hw, word_out, 16); 407 widx++; 408 409 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 410 e1000_standby_nvm(hw); 411 break; 412 } 413 } 414 usleep_range(10000, 20000); 415 nvm->ops.release(hw); 416 } 417 418 return ret_val; 419 } 420 421 /** 422 * e1000_read_pba_string_generic - Read device part number 423 * @hw: pointer to the HW structure 424 * @pba_num: pointer to device part number 425 * @pba_num_size: size of part number buffer 426 * 427 * Reads the product board assembly (PBA) number from the EEPROM and stores 428 * the value in pba_num. 429 **/ 430 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 431 u32 pba_num_size) 432 { 433 s32 ret_val; 434 u16 nvm_data; 435 u16 pba_ptr; 436 u16 offset; 437 u16 length; 438 439 if (pba_num == NULL) { 440 e_dbg("PBA string buffer was null\n"); 441 return -E1000_ERR_INVALID_ARGUMENT; 442 } 443 444 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 445 if (ret_val) { 446 e_dbg("NVM Read Error\n"); 447 return ret_val; 448 } 449 450 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 451 if (ret_val) { 452 e_dbg("NVM Read Error\n"); 453 return ret_val; 454 } 455 456 /* if nvm_data is not ptr guard the PBA must be in legacy format which 457 * means pba_ptr is actually our second data word for the PBA number 458 * and we can decode it into an ascii string 459 */ 460 if (nvm_data != NVM_PBA_PTR_GUARD) { 461 e_dbg("NVM PBA number is not stored as string\n"); 462 463 /* make sure callers buffer is big enough to store the PBA */ 464 if (pba_num_size < E1000_PBANUM_LENGTH) { 465 e_dbg("PBA string buffer too small\n"); 466 return E1000_ERR_NO_SPACE; 467 } 468 469 /* extract hex string from data and pba_ptr */ 470 pba_num[0] = (nvm_data >> 12) & 0xF; 471 pba_num[1] = (nvm_data >> 8) & 0xF; 472 pba_num[2] = (nvm_data >> 4) & 0xF; 473 pba_num[3] = nvm_data & 0xF; 474 pba_num[4] = (pba_ptr >> 12) & 0xF; 475 pba_num[5] = (pba_ptr >> 8) & 0xF; 476 pba_num[6] = '-'; 477 pba_num[7] = 0; 478 pba_num[8] = (pba_ptr >> 4) & 0xF; 479 pba_num[9] = pba_ptr & 0xF; 480 481 /* put a null character on the end of our string */ 482 pba_num[10] = '\0'; 483 484 /* switch all the data but the '-' to hex char */ 485 for (offset = 0; offset < 10; offset++) { 486 if (pba_num[offset] < 0xA) 487 pba_num[offset] += '0'; 488 else if (pba_num[offset] < 0x10) 489 pba_num[offset] += 'A' - 0xA; 490 } 491 492 return 0; 493 } 494 495 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); 496 if (ret_val) { 497 e_dbg("NVM Read Error\n"); 498 return ret_val; 499 } 500 501 if (length == 0xFFFF || length == 0) { 502 e_dbg("NVM PBA number section invalid length\n"); 503 return -E1000_ERR_NVM_PBA_SECTION; 504 } 505 /* check if pba_num buffer is big enough */ 506 if (pba_num_size < (((u32)length * 2) - 1)) { 507 e_dbg("PBA string buffer too small\n"); 508 return -E1000_ERR_NO_SPACE; 509 } 510 511 /* trim pba length from start of string */ 512 pba_ptr++; 513 length--; 514 515 for (offset = 0; offset < length; offset++) { 516 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); 517 if (ret_val) { 518 e_dbg("NVM Read Error\n"); 519 return ret_val; 520 } 521 pba_num[offset * 2] = (u8)(nvm_data >> 8); 522 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 523 } 524 pba_num[offset * 2] = '\0'; 525 526 return 0; 527 } 528 529 /** 530 * e1000_read_mac_addr_generic - Read device MAC address 531 * @hw: pointer to the HW structure 532 * 533 * Reads the device MAC address from the EEPROM and stores the value. 534 * Since devices with two ports use the same EEPROM, we increment the 535 * last bit in the MAC address for the second port. 536 **/ 537 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 538 { 539 u32 rar_high; 540 u32 rar_low; 541 u16 i; 542 543 rar_high = er32(RAH(0)); 544 rar_low = er32(RAL(0)); 545 546 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 547 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); 548 549 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 550 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); 551 552 for (i = 0; i < ETH_ALEN; i++) 553 hw->mac.addr[i] = hw->mac.perm_addr[i]; 554 555 return 0; 556 } 557 558 /** 559 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum 560 * @hw: pointer to the HW structure 561 * 562 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 563 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 564 **/ 565 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) 566 { 567 s32 ret_val; 568 u16 checksum = 0; 569 u16 i, nvm_data; 570 571 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 572 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 573 if (ret_val) { 574 e_dbg("NVM Read Error\n"); 575 return ret_val; 576 } 577 checksum += nvm_data; 578 } 579 580 if (checksum != (u16)NVM_SUM) { 581 e_dbg("NVM Checksum Invalid\n"); 582 return -E1000_ERR_NVM; 583 } 584 585 return 0; 586 } 587 588 /** 589 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum 590 * @hw: pointer to the HW structure 591 * 592 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 593 * up to the checksum. Then calculates the EEPROM checksum and writes the 594 * value to the EEPROM. 595 **/ 596 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) 597 { 598 s32 ret_val; 599 u16 checksum = 0; 600 u16 i, nvm_data; 601 602 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 603 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); 604 if (ret_val) { 605 e_dbg("NVM Read Error while updating checksum.\n"); 606 return ret_val; 607 } 608 checksum += nvm_data; 609 } 610 checksum = (u16)NVM_SUM - checksum; 611 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 612 if (ret_val) 613 e_dbg("NVM Write Error while updating checksum.\n"); 614 615 return ret_val; 616 } 617 618 /** 619 * e1000e_reload_nvm_generic - Reloads EEPROM 620 * @hw: pointer to the HW structure 621 * 622 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 623 * extended control register. 624 **/ 625 void e1000e_reload_nvm_generic(struct e1000_hw *hw) 626 { 627 u32 ctrl_ext; 628 629 usleep_range(10, 20); 630 ctrl_ext = er32(CTRL_EXT); 631 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 632 ew32(CTRL_EXT, ctrl_ext); 633 e1e_flush(); 634 } 635