1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 29 #include "e1000.h" 30 31 #define DRV_EXTRAVERSION "-k" 32 33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 34 char e1000e_driver_name[] = "e1000e"; 35 const char e1000e_driver_version[] = DRV_VERSION; 36 37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 38 static int debug = -1; 39 module_param(debug, int, 0); 40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 41 42 static const struct e1000_info *e1000_info_tbl[] = { 43 [board_82571] = &e1000_82571_info, 44 [board_82572] = &e1000_82572_info, 45 [board_82573] = &e1000_82573_info, 46 [board_82574] = &e1000_82574_info, 47 [board_82583] = &e1000_82583_info, 48 [board_80003es2lan] = &e1000_es2_info, 49 [board_ich8lan] = &e1000_ich8_info, 50 [board_ich9lan] = &e1000_ich9_info, 51 [board_ich10lan] = &e1000_ich10_info, 52 [board_pchlan] = &e1000_pch_info, 53 [board_pch2lan] = &e1000_pch2_info, 54 [board_pch_lpt] = &e1000_pch_lpt_info, 55 [board_pch_spt] = &e1000_pch_spt_info, 56 [board_pch_cnp] = &e1000_pch_cnp_info, 57 }; 58 59 struct e1000_reg_info { 60 u32 ofs; 61 char *name; 62 }; 63 64 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 65 /* General Registers */ 66 {E1000_CTRL, "CTRL"}, 67 {E1000_STATUS, "STATUS"}, 68 {E1000_CTRL_EXT, "CTRL_EXT"}, 69 70 /* Interrupt Registers */ 71 {E1000_ICR, "ICR"}, 72 73 /* Rx Registers */ 74 {E1000_RCTL, "RCTL"}, 75 {E1000_RDLEN(0), "RDLEN"}, 76 {E1000_RDH(0), "RDH"}, 77 {E1000_RDT(0), "RDT"}, 78 {E1000_RDTR, "RDTR"}, 79 {E1000_RXDCTL(0), "RXDCTL"}, 80 {E1000_ERT, "ERT"}, 81 {E1000_RDBAL(0), "RDBAL"}, 82 {E1000_RDBAH(0), "RDBAH"}, 83 {E1000_RDFH, "RDFH"}, 84 {E1000_RDFT, "RDFT"}, 85 {E1000_RDFHS, "RDFHS"}, 86 {E1000_RDFTS, "RDFTS"}, 87 {E1000_RDFPC, "RDFPC"}, 88 89 /* Tx Registers */ 90 {E1000_TCTL, "TCTL"}, 91 {E1000_TDBAL(0), "TDBAL"}, 92 {E1000_TDBAH(0), "TDBAH"}, 93 {E1000_TDLEN(0), "TDLEN"}, 94 {E1000_TDH(0), "TDH"}, 95 {E1000_TDT(0), "TDT"}, 96 {E1000_TIDV, "TIDV"}, 97 {E1000_TXDCTL(0), "TXDCTL"}, 98 {E1000_TADV, "TADV"}, 99 {E1000_TARC(0), "TARC"}, 100 {E1000_TDFH, "TDFH"}, 101 {E1000_TDFT, "TDFT"}, 102 {E1000_TDFHS, "TDFHS"}, 103 {E1000_TDFTS, "TDFTS"}, 104 {E1000_TDFPC, "TDFPC"}, 105 106 /* List Terminator */ 107 {0, NULL} 108 }; 109 110 /** 111 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 112 * @hw: pointer to the HW structure 113 * 114 * When updating the MAC CSR registers, the Manageability Engine (ME) could 115 * be accessing the registers at the same time. Normally, this is handled in 116 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 117 * accesses later than it should which could result in the register to have 118 * an incorrect value. Workaround this by checking the FWSM register which 119 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 120 * and try again a number of times. 121 **/ 122 s32 __ew32_prepare(struct e1000_hw *hw) 123 { 124 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 125 126 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 127 udelay(50); 128 129 return i; 130 } 131 132 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 133 { 134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 135 __ew32_prepare(hw); 136 137 writel(val, hw->hw_addr + reg); 138 } 139 140 /** 141 * e1000_regdump - register printout routine 142 * @hw: pointer to the HW structure 143 * @reginfo: pointer to the register info table 144 **/ 145 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 146 { 147 int n = 0; 148 char rname[16]; 149 u32 regs[8]; 150 151 switch (reginfo->ofs) { 152 case E1000_RXDCTL(0): 153 for (n = 0; n < 2; n++) 154 regs[n] = __er32(hw, E1000_RXDCTL(n)); 155 break; 156 case E1000_TXDCTL(0): 157 for (n = 0; n < 2; n++) 158 regs[n] = __er32(hw, E1000_TXDCTL(n)); 159 break; 160 case E1000_TARC(0): 161 for (n = 0; n < 2; n++) 162 regs[n] = __er32(hw, E1000_TARC(n)); 163 break; 164 default: 165 pr_info("%-15s %08x\n", 166 reginfo->name, __er32(hw, reginfo->ofs)); 167 return; 168 } 169 170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 172 } 173 174 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 175 struct e1000_buffer *bi) 176 { 177 int i; 178 struct e1000_ps_page *ps_page; 179 180 for (i = 0; i < adapter->rx_ps_pages; i++) { 181 ps_page = &bi->ps_pages[i]; 182 183 if (ps_page->page) { 184 pr_info("packet dump for ps_page %d:\n", i); 185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 186 16, 1, page_address(ps_page->page), 187 PAGE_SIZE, true); 188 } 189 } 190 } 191 192 /** 193 * e1000e_dump - Print registers, Tx-ring and Rx-ring 194 * @adapter: board private structure 195 **/ 196 static void e1000e_dump(struct e1000_adapter *adapter) 197 { 198 struct net_device *netdev = adapter->netdev; 199 struct e1000_hw *hw = &adapter->hw; 200 struct e1000_reg_info *reginfo; 201 struct e1000_ring *tx_ring = adapter->tx_ring; 202 struct e1000_tx_desc *tx_desc; 203 struct my_u0 { 204 __le64 a; 205 __le64 b; 206 } *u0; 207 struct e1000_buffer *buffer_info; 208 struct e1000_ring *rx_ring = adapter->rx_ring; 209 union e1000_rx_desc_packet_split *rx_desc_ps; 210 union e1000_rx_desc_extended *rx_desc; 211 struct my_u1 { 212 __le64 a; 213 __le64 b; 214 __le64 c; 215 __le64 d; 216 } *u1; 217 u32 staterr; 218 int i = 0; 219 220 if (!netif_msg_hw(adapter)) 221 return; 222 223 /* Print netdevice Info */ 224 if (netdev) { 225 dev_info(&adapter->pdev->dev, "Net device Info\n"); 226 pr_info("Device Name state trans_start\n"); 227 pr_info("%-15s %016lX %016lX\n", netdev->name, 228 netdev->state, dev_trans_start(netdev)); 229 } 230 231 /* Print Registers */ 232 dev_info(&adapter->pdev->dev, "Register Dump\n"); 233 pr_info(" Register Name Value\n"); 234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 235 reginfo->name; reginfo++) { 236 e1000_regdump(hw, reginfo); 237 } 238 239 /* Print Tx Ring Summary */ 240 if (!netdev || !netif_running(netdev)) 241 return; 242 243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 247 0, tx_ring->next_to_use, tx_ring->next_to_clean, 248 (unsigned long long)buffer_info->dma, 249 buffer_info->length, 250 buffer_info->next_to_watch, 251 (unsigned long long)buffer_info->time_stamp); 252 253 /* Print Tx Ring */ 254 if (!netif_msg_tx_done(adapter)) 255 goto rx_ring_summary; 256 257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 258 259 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 260 * 261 * Legacy Transmit Descriptor 262 * +--------------------------------------------------------------+ 263 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 264 * +--------------------------------------------------------------+ 265 * 8 | Special | CSS | Status | CMD | CSO | Length | 266 * +--------------------------------------------------------------+ 267 * 63 48 47 36 35 32 31 24 23 16 15 0 268 * 269 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 270 * 63 48 47 40 39 32 31 16 15 8 7 0 271 * +----------------------------------------------------------------+ 272 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 273 * +----------------------------------------------------------------+ 274 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 275 * +----------------------------------------------------------------+ 276 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 277 * 278 * Extended Data Descriptor (DTYP=0x1) 279 * +----------------------------------------------------------------+ 280 * 0 | Buffer Address [63:0] | 281 * +----------------------------------------------------------------+ 282 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 283 * +----------------------------------------------------------------+ 284 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 285 */ 286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 290 const char *next_desc; 291 tx_desc = E1000_TX_DESC(*tx_ring, i); 292 buffer_info = &tx_ring->buffer_info[i]; 293 u0 = (struct my_u0 *)tx_desc; 294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 295 next_desc = " NTC/U"; 296 else if (i == tx_ring->next_to_use) 297 next_desc = " NTU"; 298 else if (i == tx_ring->next_to_clean) 299 next_desc = " NTC"; 300 else 301 next_desc = ""; 302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 305 i, 306 (unsigned long long)le64_to_cpu(u0->a), 307 (unsigned long long)le64_to_cpu(u0->b), 308 (unsigned long long)buffer_info->dma, 309 buffer_info->length, buffer_info->next_to_watch, 310 (unsigned long long)buffer_info->time_stamp, 311 buffer_info->skb, next_desc); 312 313 if (netif_msg_pktdata(adapter) && buffer_info->skb) 314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 315 16, 1, buffer_info->skb->data, 316 buffer_info->skb->len, true); 317 } 318 319 /* Print Rx Ring Summary */ 320 rx_ring_summary: 321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 322 pr_info("Queue [NTU] [NTC]\n"); 323 pr_info(" %5d %5X %5X\n", 324 0, rx_ring->next_to_use, rx_ring->next_to_clean); 325 326 /* Print Rx Ring */ 327 if (!netif_msg_rx_status(adapter)) 328 return; 329 330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 331 switch (adapter->rx_ps_pages) { 332 case 1: 333 case 2: 334 case 3: 335 /* [Extended] Packet Split Receive Descriptor Format 336 * 337 * +-----------------------------------------------------+ 338 * 0 | Buffer Address 0 [63:0] | 339 * +-----------------------------------------------------+ 340 * 8 | Buffer Address 1 [63:0] | 341 * +-----------------------------------------------------+ 342 * 16 | Buffer Address 2 [63:0] | 343 * +-----------------------------------------------------+ 344 * 24 | Buffer Address 3 [63:0] | 345 * +-----------------------------------------------------+ 346 */ 347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 348 /* [Extended] Receive Descriptor (Write-Back) Format 349 * 350 * 63 48 47 32 31 13 12 8 7 4 3 0 351 * +------------------------------------------------------+ 352 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 353 * | Checksum | Ident | | Queue | | Type | 354 * +------------------------------------------------------+ 355 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 356 * +------------------------------------------------------+ 357 * 63 48 47 32 31 20 19 0 358 */ 359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 360 for (i = 0; i < rx_ring->count; i++) { 361 const char *next_desc; 362 buffer_info = &rx_ring->buffer_info[i]; 363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 364 u1 = (struct my_u1 *)rx_desc_ps; 365 staterr = 366 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 367 368 if (i == rx_ring->next_to_use) 369 next_desc = " NTU"; 370 else if (i == rx_ring->next_to_clean) 371 next_desc = " NTC"; 372 else 373 next_desc = ""; 374 375 if (staterr & E1000_RXD_STAT_DD) { 376 /* Descriptor Done */ 377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 378 "RWB", i, 379 (unsigned long long)le64_to_cpu(u1->a), 380 (unsigned long long)le64_to_cpu(u1->b), 381 (unsigned long long)le64_to_cpu(u1->c), 382 (unsigned long long)le64_to_cpu(u1->d), 383 buffer_info->skb, next_desc); 384 } else { 385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 386 "R ", i, 387 (unsigned long long)le64_to_cpu(u1->a), 388 (unsigned long long)le64_to_cpu(u1->b), 389 (unsigned long long)le64_to_cpu(u1->c), 390 (unsigned long long)le64_to_cpu(u1->d), 391 (unsigned long long)buffer_info->dma, 392 buffer_info->skb, next_desc); 393 394 if (netif_msg_pktdata(adapter)) 395 e1000e_dump_ps_pages(adapter, 396 buffer_info); 397 } 398 } 399 break; 400 default: 401 case 0: 402 /* Extended Receive Descriptor (Read) Format 403 * 404 * +-----------------------------------------------------+ 405 * 0 | Buffer Address [63:0] | 406 * +-----------------------------------------------------+ 407 * 8 | Reserved | 408 * +-----------------------------------------------------+ 409 */ 410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 411 /* Extended Receive Descriptor (Write-Back) Format 412 * 413 * 63 48 47 32 31 24 23 4 3 0 414 * +------------------------------------------------------+ 415 * | RSS Hash | | | | 416 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 417 * | Packet | IP | | | Type | 418 * | Checksum | Ident | | | | 419 * +------------------------------------------------------+ 420 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 421 * +------------------------------------------------------+ 422 * 63 48 47 32 31 20 19 0 423 */ 424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 425 426 for (i = 0; i < rx_ring->count; i++) { 427 const char *next_desc; 428 429 buffer_info = &rx_ring->buffer_info[i]; 430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 431 u1 = (struct my_u1 *)rx_desc; 432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 433 434 if (i == rx_ring->next_to_use) 435 next_desc = " NTU"; 436 else if (i == rx_ring->next_to_clean) 437 next_desc = " NTC"; 438 else 439 next_desc = ""; 440 441 if (staterr & E1000_RXD_STAT_DD) { 442 /* Descriptor Done */ 443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 444 "RWB", i, 445 (unsigned long long)le64_to_cpu(u1->a), 446 (unsigned long long)le64_to_cpu(u1->b), 447 buffer_info->skb, next_desc); 448 } else { 449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 450 "R ", i, 451 (unsigned long long)le64_to_cpu(u1->a), 452 (unsigned long long)le64_to_cpu(u1->b), 453 (unsigned long long)buffer_info->dma, 454 buffer_info->skb, next_desc); 455 456 if (netif_msg_pktdata(adapter) && 457 buffer_info->skb) 458 print_hex_dump(KERN_INFO, "", 459 DUMP_PREFIX_ADDRESS, 16, 460 1, 461 buffer_info->skb->data, 462 adapter->rx_buffer_len, 463 true); 464 } 465 } 466 } 467 } 468 469 /** 470 * e1000_desc_unused - calculate if we have unused descriptors 471 **/ 472 static int e1000_desc_unused(struct e1000_ring *ring) 473 { 474 if (ring->next_to_clean > ring->next_to_use) 475 return ring->next_to_clean - ring->next_to_use - 1; 476 477 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 478 } 479 480 /** 481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 482 * @adapter: board private structure 483 * @hwtstamps: time stamp structure to update 484 * @systim: unsigned 64bit system time value. 485 * 486 * Convert the system time value stored in the RX/TXSTMP registers into a 487 * hwtstamp which can be used by the upper level time stamping functions. 488 * 489 * The 'systim_lock' spinlock is used to protect the consistency of the 490 * system time value. This is needed because reading the 64 bit time 491 * value involves reading two 32 bit registers. The first read latches the 492 * value. 493 **/ 494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 495 struct skb_shared_hwtstamps *hwtstamps, 496 u64 systim) 497 { 498 u64 ns; 499 unsigned long flags; 500 501 spin_lock_irqsave(&adapter->systim_lock, flags); 502 ns = timecounter_cyc2time(&adapter->tc, systim); 503 spin_unlock_irqrestore(&adapter->systim_lock, flags); 504 505 memset(hwtstamps, 0, sizeof(*hwtstamps)); 506 hwtstamps->hwtstamp = ns_to_ktime(ns); 507 } 508 509 /** 510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 511 * @adapter: board private structure 512 * @status: descriptor extended error and status field 513 * @skb: particular skb to include time stamp 514 * 515 * If the time stamp is valid, convert it into the timecounter ns value 516 * and store that result into the shhwtstamps structure which is passed 517 * up the network stack. 518 **/ 519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 520 struct sk_buff *skb) 521 { 522 struct e1000_hw *hw = &adapter->hw; 523 u64 rxstmp; 524 525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 526 !(status & E1000_RXDEXT_STATERR_TST) || 527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 528 return; 529 530 /* The Rx time stamp registers contain the time stamp. No other 531 * received packet will be time stamped until the Rx time stamp 532 * registers are read. Because only one packet can be time stamped 533 * at a time, the register values must belong to this packet and 534 * therefore none of the other additional attributes need to be 535 * compared. 536 */ 537 rxstmp = (u64)er32(RXSTMPL); 538 rxstmp |= (u64)er32(RXSTMPH) << 32; 539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 540 541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 542 } 543 544 /** 545 * e1000_receive_skb - helper function to handle Rx indications 546 * @adapter: board private structure 547 * @staterr: descriptor extended error and status field as written by hardware 548 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 549 * @skb: pointer to sk_buff to be indicated to stack 550 **/ 551 static void e1000_receive_skb(struct e1000_adapter *adapter, 552 struct net_device *netdev, struct sk_buff *skb, 553 u32 staterr, __le16 vlan) 554 { 555 u16 tag = le16_to_cpu(vlan); 556 557 e1000e_rx_hwtstamp(adapter, staterr, skb); 558 559 skb->protocol = eth_type_trans(skb, netdev); 560 561 if (staterr & E1000_RXD_STAT_VP) 562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 563 564 napi_gro_receive(&adapter->napi, skb); 565 } 566 567 /** 568 * e1000_rx_checksum - Receive Checksum Offload 569 * @adapter: board private structure 570 * @status_err: receive descriptor status and error fields 571 * @csum: receive descriptor csum field 572 * @sk_buff: socket buffer with received data 573 **/ 574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 575 struct sk_buff *skb) 576 { 577 u16 status = (u16)status_err; 578 u8 errors = (u8)(status_err >> 24); 579 580 skb_checksum_none_assert(skb); 581 582 /* Rx checksum disabled */ 583 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 584 return; 585 586 /* Ignore Checksum bit is set */ 587 if (status & E1000_RXD_STAT_IXSM) 588 return; 589 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 592 /* let the stack verify checksum errors */ 593 adapter->hw_csum_err++; 594 return; 595 } 596 597 /* TCP/UDP Checksum has not been calculated */ 598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 599 return; 600 601 /* It must be a TCP or UDP packet with a valid checksum */ 602 skb->ip_summed = CHECKSUM_UNNECESSARY; 603 adapter->hw_csum_good++; 604 } 605 606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 607 { 608 struct e1000_adapter *adapter = rx_ring->adapter; 609 struct e1000_hw *hw = &adapter->hw; 610 s32 ret_val = __ew32_prepare(hw); 611 612 writel(i, rx_ring->tail); 613 614 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 615 u32 rctl = er32(RCTL); 616 617 ew32(RCTL, rctl & ~E1000_RCTL_EN); 618 e_err("ME firmware caused invalid RDT - resetting\n"); 619 schedule_work(&adapter->reset_task); 620 } 621 } 622 623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = tx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 s32 ret_val = __ew32_prepare(hw); 628 629 writel(i, tx_ring->tail); 630 631 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 632 u32 tctl = er32(TCTL); 633 634 ew32(TCTL, tctl & ~E1000_TCTL_EN); 635 e_err("ME firmware caused invalid TDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 /** 641 * e1000_alloc_rx_buffers - Replace used receive buffers 642 * @rx_ring: Rx descriptor ring 643 **/ 644 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 645 int cleaned_count, gfp_t gfp) 646 { 647 struct e1000_adapter *adapter = rx_ring->adapter; 648 struct net_device *netdev = adapter->netdev; 649 struct pci_dev *pdev = adapter->pdev; 650 union e1000_rx_desc_extended *rx_desc; 651 struct e1000_buffer *buffer_info; 652 struct sk_buff *skb; 653 unsigned int i; 654 unsigned int bufsz = adapter->rx_buffer_len; 655 656 i = rx_ring->next_to_use; 657 buffer_info = &rx_ring->buffer_info[i]; 658 659 while (cleaned_count--) { 660 skb = buffer_info->skb; 661 if (skb) { 662 skb_trim(skb, 0); 663 goto map_skb; 664 } 665 666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 667 if (!skb) { 668 /* Better luck next round */ 669 adapter->alloc_rx_buff_failed++; 670 break; 671 } 672 673 buffer_info->skb = skb; 674 map_skb: 675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 676 adapter->rx_buffer_len, 677 DMA_FROM_DEVICE); 678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 679 dev_err(&pdev->dev, "Rx DMA map failed\n"); 680 adapter->rx_dma_failed++; 681 break; 682 } 683 684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 686 687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 688 /* Force memory writes to complete before letting h/w 689 * know there are new descriptors to fetch. (Only 690 * applicable for weak-ordered memory model archs, 691 * such as IA-64). 692 */ 693 wmb(); 694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 695 e1000e_update_rdt_wa(rx_ring, i); 696 else 697 writel(i, rx_ring->tail); 698 } 699 i++; 700 if (i == rx_ring->count) 701 i = 0; 702 buffer_info = &rx_ring->buffer_info[i]; 703 } 704 705 rx_ring->next_to_use = i; 706 } 707 708 /** 709 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 710 * @rx_ring: Rx descriptor ring 711 **/ 712 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 713 int cleaned_count, gfp_t gfp) 714 { 715 struct e1000_adapter *adapter = rx_ring->adapter; 716 struct net_device *netdev = adapter->netdev; 717 struct pci_dev *pdev = adapter->pdev; 718 union e1000_rx_desc_packet_split *rx_desc; 719 struct e1000_buffer *buffer_info; 720 struct e1000_ps_page *ps_page; 721 struct sk_buff *skb; 722 unsigned int i, j; 723 724 i = rx_ring->next_to_use; 725 buffer_info = &rx_ring->buffer_info[i]; 726 727 while (cleaned_count--) { 728 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 729 730 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 731 ps_page = &buffer_info->ps_pages[j]; 732 if (j >= adapter->rx_ps_pages) { 733 /* all unused desc entries get hw null ptr */ 734 rx_desc->read.buffer_addr[j + 1] = 735 ~cpu_to_le64(0); 736 continue; 737 } 738 if (!ps_page->page) { 739 ps_page->page = alloc_page(gfp); 740 if (!ps_page->page) { 741 adapter->alloc_rx_buff_failed++; 742 goto no_buffers; 743 } 744 ps_page->dma = dma_map_page(&pdev->dev, 745 ps_page->page, 746 0, PAGE_SIZE, 747 DMA_FROM_DEVICE); 748 if (dma_mapping_error(&pdev->dev, 749 ps_page->dma)) { 750 dev_err(&adapter->pdev->dev, 751 "Rx DMA page map failed\n"); 752 adapter->rx_dma_failed++; 753 goto no_buffers; 754 } 755 } 756 /* Refresh the desc even if buffer_addrs 757 * didn't change because each write-back 758 * erases this info. 759 */ 760 rx_desc->read.buffer_addr[j + 1] = 761 cpu_to_le64(ps_page->dma); 762 } 763 764 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 765 gfp); 766 767 if (!skb) { 768 adapter->alloc_rx_buff_failed++; 769 break; 770 } 771 772 buffer_info->skb = skb; 773 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 774 adapter->rx_ps_bsize0, 775 DMA_FROM_DEVICE); 776 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 777 dev_err(&pdev->dev, "Rx DMA map failed\n"); 778 adapter->rx_dma_failed++; 779 /* cleanup skb */ 780 dev_kfree_skb_any(skb); 781 buffer_info->skb = NULL; 782 break; 783 } 784 785 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 786 787 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 788 /* Force memory writes to complete before letting h/w 789 * know there are new descriptors to fetch. (Only 790 * applicable for weak-ordered memory model archs, 791 * such as IA-64). 792 */ 793 wmb(); 794 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 795 e1000e_update_rdt_wa(rx_ring, i << 1); 796 else 797 writel(i << 1, rx_ring->tail); 798 } 799 800 i++; 801 if (i == rx_ring->count) 802 i = 0; 803 buffer_info = &rx_ring->buffer_info[i]; 804 } 805 806 no_buffers: 807 rx_ring->next_to_use = i; 808 } 809 810 /** 811 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 812 * @rx_ring: Rx descriptor ring 813 * @cleaned_count: number of buffers to allocate this pass 814 **/ 815 816 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 817 int cleaned_count, gfp_t gfp) 818 { 819 struct e1000_adapter *adapter = rx_ring->adapter; 820 struct net_device *netdev = adapter->netdev; 821 struct pci_dev *pdev = adapter->pdev; 822 union e1000_rx_desc_extended *rx_desc; 823 struct e1000_buffer *buffer_info; 824 struct sk_buff *skb; 825 unsigned int i; 826 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 827 828 i = rx_ring->next_to_use; 829 buffer_info = &rx_ring->buffer_info[i]; 830 831 while (cleaned_count--) { 832 skb = buffer_info->skb; 833 if (skb) { 834 skb_trim(skb, 0); 835 goto check_page; 836 } 837 838 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 839 if (unlikely(!skb)) { 840 /* Better luck next round */ 841 adapter->alloc_rx_buff_failed++; 842 break; 843 } 844 845 buffer_info->skb = skb; 846 check_page: 847 /* allocate a new page if necessary */ 848 if (!buffer_info->page) { 849 buffer_info->page = alloc_page(gfp); 850 if (unlikely(!buffer_info->page)) { 851 adapter->alloc_rx_buff_failed++; 852 break; 853 } 854 } 855 856 if (!buffer_info->dma) { 857 buffer_info->dma = dma_map_page(&pdev->dev, 858 buffer_info->page, 0, 859 PAGE_SIZE, 860 DMA_FROM_DEVICE); 861 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 862 adapter->alloc_rx_buff_failed++; 863 break; 864 } 865 } 866 867 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 868 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 869 870 if (unlikely(++i == rx_ring->count)) 871 i = 0; 872 buffer_info = &rx_ring->buffer_info[i]; 873 } 874 875 if (likely(rx_ring->next_to_use != i)) { 876 rx_ring->next_to_use = i; 877 if (unlikely(i-- == 0)) 878 i = (rx_ring->count - 1); 879 880 /* Force memory writes to complete before letting h/w 881 * know there are new descriptors to fetch. (Only 882 * applicable for weak-ordered memory model archs, 883 * such as IA-64). 884 */ 885 wmb(); 886 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 887 e1000e_update_rdt_wa(rx_ring, i); 888 else 889 writel(i, rx_ring->tail); 890 } 891 } 892 893 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 894 struct sk_buff *skb) 895 { 896 if (netdev->features & NETIF_F_RXHASH) 897 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 898 } 899 900 /** 901 * e1000_clean_rx_irq - Send received data up the network stack 902 * @rx_ring: Rx descriptor ring 903 * 904 * the return value indicates whether actual cleaning was done, there 905 * is no guarantee that everything was cleaned 906 **/ 907 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 908 int work_to_do) 909 { 910 struct e1000_adapter *adapter = rx_ring->adapter; 911 struct net_device *netdev = adapter->netdev; 912 struct pci_dev *pdev = adapter->pdev; 913 struct e1000_hw *hw = &adapter->hw; 914 union e1000_rx_desc_extended *rx_desc, *next_rxd; 915 struct e1000_buffer *buffer_info, *next_buffer; 916 u32 length, staterr; 917 unsigned int i; 918 int cleaned_count = 0; 919 bool cleaned = false; 920 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 921 922 i = rx_ring->next_to_clean; 923 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 925 buffer_info = &rx_ring->buffer_info[i]; 926 927 while (staterr & E1000_RXD_STAT_DD) { 928 struct sk_buff *skb; 929 930 if (*work_done >= work_to_do) 931 break; 932 (*work_done)++; 933 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 934 935 skb = buffer_info->skb; 936 buffer_info->skb = NULL; 937 938 prefetch(skb->data - NET_IP_ALIGN); 939 940 i++; 941 if (i == rx_ring->count) 942 i = 0; 943 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 944 prefetch(next_rxd); 945 946 next_buffer = &rx_ring->buffer_info[i]; 947 948 cleaned = true; 949 cleaned_count++; 950 dma_unmap_single(&pdev->dev, buffer_info->dma, 951 adapter->rx_buffer_len, DMA_FROM_DEVICE); 952 buffer_info->dma = 0; 953 954 length = le16_to_cpu(rx_desc->wb.upper.length); 955 956 /* !EOP means multiple descriptors were used to store a single 957 * packet, if that's the case we need to toss it. In fact, we 958 * need to toss every packet with the EOP bit clear and the 959 * next frame that _does_ have the EOP bit set, as it is by 960 * definition only a frame fragment 961 */ 962 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 963 adapter->flags2 |= FLAG2_IS_DISCARDING; 964 965 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 966 /* All receives must fit into a single buffer */ 967 e_dbg("Receive packet consumed multiple buffers\n"); 968 /* recycle */ 969 buffer_info->skb = skb; 970 if (staterr & E1000_RXD_STAT_EOP) 971 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 972 goto next_desc; 973 } 974 975 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 976 !(netdev->features & NETIF_F_RXALL))) { 977 /* recycle */ 978 buffer_info->skb = skb; 979 goto next_desc; 980 } 981 982 /* adjust length to remove Ethernet CRC */ 983 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 984 /* If configured to store CRC, don't subtract FCS, 985 * but keep the FCS bytes out of the total_rx_bytes 986 * counter 987 */ 988 if (netdev->features & NETIF_F_RXFCS) 989 total_rx_bytes -= 4; 990 else 991 length -= 4; 992 } 993 994 total_rx_bytes += length; 995 total_rx_packets++; 996 997 /* code added for copybreak, this should improve 998 * performance for small packets with large amounts 999 * of reassembly being done in the stack 1000 */ 1001 if (length < copybreak) { 1002 struct sk_buff *new_skb = 1003 napi_alloc_skb(&adapter->napi, length); 1004 if (new_skb) { 1005 skb_copy_to_linear_data_offset(new_skb, 1006 -NET_IP_ALIGN, 1007 (skb->data - 1008 NET_IP_ALIGN), 1009 (length + 1010 NET_IP_ALIGN)); 1011 /* save the skb in buffer_info as good */ 1012 buffer_info->skb = skb; 1013 skb = new_skb; 1014 } 1015 /* else just continue with the old one */ 1016 } 1017 /* end copybreak code */ 1018 skb_put(skb, length); 1019 1020 /* Receive Checksum Offload */ 1021 e1000_rx_checksum(adapter, staterr, skb); 1022 1023 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1024 1025 e1000_receive_skb(adapter, netdev, skb, staterr, 1026 rx_desc->wb.upper.vlan); 1027 1028 next_desc: 1029 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1030 1031 /* return some buffers to hardware, one at a time is too slow */ 1032 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1033 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1034 GFP_ATOMIC); 1035 cleaned_count = 0; 1036 } 1037 1038 /* use prefetched values */ 1039 rx_desc = next_rxd; 1040 buffer_info = next_buffer; 1041 1042 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1043 } 1044 rx_ring->next_to_clean = i; 1045 1046 cleaned_count = e1000_desc_unused(rx_ring); 1047 if (cleaned_count) 1048 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1049 1050 adapter->total_rx_bytes += total_rx_bytes; 1051 adapter->total_rx_packets += total_rx_packets; 1052 return cleaned; 1053 } 1054 1055 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1056 struct e1000_buffer *buffer_info, 1057 bool drop) 1058 { 1059 struct e1000_adapter *adapter = tx_ring->adapter; 1060 1061 if (buffer_info->dma) { 1062 if (buffer_info->mapped_as_page) 1063 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1064 buffer_info->length, DMA_TO_DEVICE); 1065 else 1066 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1067 buffer_info->length, DMA_TO_DEVICE); 1068 buffer_info->dma = 0; 1069 } 1070 if (buffer_info->skb) { 1071 if (drop) 1072 dev_kfree_skb_any(buffer_info->skb); 1073 else 1074 dev_consume_skb_any(buffer_info->skb); 1075 buffer_info->skb = NULL; 1076 } 1077 buffer_info->time_stamp = 0; 1078 } 1079 1080 static void e1000_print_hw_hang(struct work_struct *work) 1081 { 1082 struct e1000_adapter *adapter = container_of(work, 1083 struct e1000_adapter, 1084 print_hang_task); 1085 struct net_device *netdev = adapter->netdev; 1086 struct e1000_ring *tx_ring = adapter->tx_ring; 1087 unsigned int i = tx_ring->next_to_clean; 1088 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1089 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1090 struct e1000_hw *hw = &adapter->hw; 1091 u16 phy_status, phy_1000t_status, phy_ext_status; 1092 u16 pci_status; 1093 1094 if (test_bit(__E1000_DOWN, &adapter->state)) 1095 return; 1096 1097 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1098 /* May be block on write-back, flush and detect again 1099 * flush pending descriptor writebacks to memory 1100 */ 1101 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1102 /* execute the writes immediately */ 1103 e1e_flush(); 1104 /* Due to rare timing issues, write to TIDV again to ensure 1105 * the write is successful 1106 */ 1107 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1108 /* execute the writes immediately */ 1109 e1e_flush(); 1110 adapter->tx_hang_recheck = true; 1111 return; 1112 } 1113 adapter->tx_hang_recheck = false; 1114 1115 if (er32(TDH(0)) == er32(TDT(0))) { 1116 e_dbg("false hang detected, ignoring\n"); 1117 return; 1118 } 1119 1120 /* Real hang detected */ 1121 netif_stop_queue(netdev); 1122 1123 e1e_rphy(hw, MII_BMSR, &phy_status); 1124 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1125 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1126 1127 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1128 1129 /* detected Hardware unit hang */ 1130 e_err("Detected Hardware Unit Hang:\n" 1131 " TDH <%x>\n" 1132 " TDT <%x>\n" 1133 " next_to_use <%x>\n" 1134 " next_to_clean <%x>\n" 1135 "buffer_info[next_to_clean]:\n" 1136 " time_stamp <%lx>\n" 1137 " next_to_watch <%x>\n" 1138 " jiffies <%lx>\n" 1139 " next_to_watch.status <%x>\n" 1140 "MAC Status <%x>\n" 1141 "PHY Status <%x>\n" 1142 "PHY 1000BASE-T Status <%x>\n" 1143 "PHY Extended Status <%x>\n" 1144 "PCI Status <%x>\n", 1145 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1146 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1147 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1148 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1149 1150 e1000e_dump(adapter); 1151 1152 /* Suggest workaround for known h/w issue */ 1153 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1154 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1155 } 1156 1157 /** 1158 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1159 * @work: pointer to work struct 1160 * 1161 * This work function polls the TSYNCTXCTL valid bit to determine when a 1162 * timestamp has been taken for the current stored skb. The timestamp must 1163 * be for this skb because only one such packet is allowed in the queue. 1164 */ 1165 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1166 { 1167 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1168 tx_hwtstamp_work); 1169 struct e1000_hw *hw = &adapter->hw; 1170 1171 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1172 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1173 struct skb_shared_hwtstamps shhwtstamps; 1174 u64 txstmp; 1175 1176 txstmp = er32(TXSTMPL); 1177 txstmp |= (u64)er32(TXSTMPH) << 32; 1178 1179 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1180 1181 /* Clear the global tx_hwtstamp_skb pointer and force writes 1182 * prior to notifying the stack of a Tx timestamp. 1183 */ 1184 adapter->tx_hwtstamp_skb = NULL; 1185 wmb(); /* force write prior to skb_tstamp_tx */ 1186 1187 skb_tstamp_tx(skb, &shhwtstamps); 1188 dev_consume_skb_any(skb); 1189 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1190 + adapter->tx_timeout_factor * HZ)) { 1191 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1192 adapter->tx_hwtstamp_skb = NULL; 1193 adapter->tx_hwtstamp_timeouts++; 1194 e_warn("clearing Tx timestamp hang\n"); 1195 } else { 1196 /* reschedule to check later */ 1197 schedule_work(&adapter->tx_hwtstamp_work); 1198 } 1199 } 1200 1201 /** 1202 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1203 * @tx_ring: Tx descriptor ring 1204 * 1205 * the return value indicates whether actual cleaning was done, there 1206 * is no guarantee that everything was cleaned 1207 **/ 1208 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1209 { 1210 struct e1000_adapter *adapter = tx_ring->adapter; 1211 struct net_device *netdev = adapter->netdev; 1212 struct e1000_hw *hw = &adapter->hw; 1213 struct e1000_tx_desc *tx_desc, *eop_desc; 1214 struct e1000_buffer *buffer_info; 1215 unsigned int i, eop; 1216 unsigned int count = 0; 1217 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1218 unsigned int bytes_compl = 0, pkts_compl = 0; 1219 1220 i = tx_ring->next_to_clean; 1221 eop = tx_ring->buffer_info[i].next_to_watch; 1222 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1223 1224 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1225 (count < tx_ring->count)) { 1226 bool cleaned = false; 1227 1228 dma_rmb(); /* read buffer_info after eop_desc */ 1229 for (; !cleaned; count++) { 1230 tx_desc = E1000_TX_DESC(*tx_ring, i); 1231 buffer_info = &tx_ring->buffer_info[i]; 1232 cleaned = (i == eop); 1233 1234 if (cleaned) { 1235 total_tx_packets += buffer_info->segs; 1236 total_tx_bytes += buffer_info->bytecount; 1237 if (buffer_info->skb) { 1238 bytes_compl += buffer_info->skb->len; 1239 pkts_compl++; 1240 } 1241 } 1242 1243 e1000_put_txbuf(tx_ring, buffer_info, false); 1244 tx_desc->upper.data = 0; 1245 1246 i++; 1247 if (i == tx_ring->count) 1248 i = 0; 1249 } 1250 1251 if (i == tx_ring->next_to_use) 1252 break; 1253 eop = tx_ring->buffer_info[i].next_to_watch; 1254 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1255 } 1256 1257 tx_ring->next_to_clean = i; 1258 1259 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1260 1261 #define TX_WAKE_THRESHOLD 32 1262 if (count && netif_carrier_ok(netdev) && 1263 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1264 /* Make sure that anybody stopping the queue after this 1265 * sees the new next_to_clean. 1266 */ 1267 smp_mb(); 1268 1269 if (netif_queue_stopped(netdev) && 1270 !(test_bit(__E1000_DOWN, &adapter->state))) { 1271 netif_wake_queue(netdev); 1272 ++adapter->restart_queue; 1273 } 1274 } 1275 1276 if (adapter->detect_tx_hung) { 1277 /* Detect a transmit hang in hardware, this serializes the 1278 * check with the clearing of time_stamp and movement of i 1279 */ 1280 adapter->detect_tx_hung = false; 1281 if (tx_ring->buffer_info[i].time_stamp && 1282 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1283 + (adapter->tx_timeout_factor * HZ)) && 1284 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1285 schedule_work(&adapter->print_hang_task); 1286 else 1287 adapter->tx_hang_recheck = false; 1288 } 1289 adapter->total_tx_bytes += total_tx_bytes; 1290 adapter->total_tx_packets += total_tx_packets; 1291 return count < tx_ring->count; 1292 } 1293 1294 /** 1295 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1296 * @rx_ring: Rx descriptor ring 1297 * 1298 * the return value indicates whether actual cleaning was done, there 1299 * is no guarantee that everything was cleaned 1300 **/ 1301 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1302 int work_to_do) 1303 { 1304 struct e1000_adapter *adapter = rx_ring->adapter; 1305 struct e1000_hw *hw = &adapter->hw; 1306 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1307 struct net_device *netdev = adapter->netdev; 1308 struct pci_dev *pdev = adapter->pdev; 1309 struct e1000_buffer *buffer_info, *next_buffer; 1310 struct e1000_ps_page *ps_page; 1311 struct sk_buff *skb; 1312 unsigned int i, j; 1313 u32 length, staterr; 1314 int cleaned_count = 0; 1315 bool cleaned = false; 1316 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1317 1318 i = rx_ring->next_to_clean; 1319 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1320 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1321 buffer_info = &rx_ring->buffer_info[i]; 1322 1323 while (staterr & E1000_RXD_STAT_DD) { 1324 if (*work_done >= work_to_do) 1325 break; 1326 (*work_done)++; 1327 skb = buffer_info->skb; 1328 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1329 1330 /* in the packet split case this is header only */ 1331 prefetch(skb->data - NET_IP_ALIGN); 1332 1333 i++; 1334 if (i == rx_ring->count) 1335 i = 0; 1336 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1337 prefetch(next_rxd); 1338 1339 next_buffer = &rx_ring->buffer_info[i]; 1340 1341 cleaned = true; 1342 cleaned_count++; 1343 dma_unmap_single(&pdev->dev, buffer_info->dma, 1344 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1345 buffer_info->dma = 0; 1346 1347 /* see !EOP comment in other Rx routine */ 1348 if (!(staterr & E1000_RXD_STAT_EOP)) 1349 adapter->flags2 |= FLAG2_IS_DISCARDING; 1350 1351 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1352 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1353 dev_kfree_skb_irq(skb); 1354 if (staterr & E1000_RXD_STAT_EOP) 1355 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1356 goto next_desc; 1357 } 1358 1359 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1360 !(netdev->features & NETIF_F_RXALL))) { 1361 dev_kfree_skb_irq(skb); 1362 goto next_desc; 1363 } 1364 1365 length = le16_to_cpu(rx_desc->wb.middle.length0); 1366 1367 if (!length) { 1368 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1369 dev_kfree_skb_irq(skb); 1370 goto next_desc; 1371 } 1372 1373 /* Good Receive */ 1374 skb_put(skb, length); 1375 1376 { 1377 /* this looks ugly, but it seems compiler issues make 1378 * it more efficient than reusing j 1379 */ 1380 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1381 1382 /* page alloc/put takes too long and effects small 1383 * packet throughput, so unsplit small packets and 1384 * save the alloc/put only valid in softirq (napi) 1385 * context to call kmap_* 1386 */ 1387 if (l1 && (l1 <= copybreak) && 1388 ((length + l1) <= adapter->rx_ps_bsize0)) { 1389 u8 *vaddr; 1390 1391 ps_page = &buffer_info->ps_pages[0]; 1392 1393 /* there is no documentation about how to call 1394 * kmap_atomic, so we can't hold the mapping 1395 * very long 1396 */ 1397 dma_sync_single_for_cpu(&pdev->dev, 1398 ps_page->dma, 1399 PAGE_SIZE, 1400 DMA_FROM_DEVICE); 1401 vaddr = kmap_atomic(ps_page->page); 1402 memcpy(skb_tail_pointer(skb), vaddr, l1); 1403 kunmap_atomic(vaddr); 1404 dma_sync_single_for_device(&pdev->dev, 1405 ps_page->dma, 1406 PAGE_SIZE, 1407 DMA_FROM_DEVICE); 1408 1409 /* remove the CRC */ 1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1411 if (!(netdev->features & NETIF_F_RXFCS)) 1412 l1 -= 4; 1413 } 1414 1415 skb_put(skb, l1); 1416 goto copydone; 1417 } /* if */ 1418 } 1419 1420 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1421 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1422 if (!length) 1423 break; 1424 1425 ps_page = &buffer_info->ps_pages[j]; 1426 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1427 DMA_FROM_DEVICE); 1428 ps_page->dma = 0; 1429 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1430 ps_page->page = NULL; 1431 skb->len += length; 1432 skb->data_len += length; 1433 skb->truesize += PAGE_SIZE; 1434 } 1435 1436 /* strip the ethernet crc, problem is we're using pages now so 1437 * this whole operation can get a little cpu intensive 1438 */ 1439 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1440 if (!(netdev->features & NETIF_F_RXFCS)) 1441 pskb_trim(skb, skb->len - 4); 1442 } 1443 1444 copydone: 1445 total_rx_bytes += skb->len; 1446 total_rx_packets++; 1447 1448 e1000_rx_checksum(adapter, staterr, skb); 1449 1450 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1451 1452 if (rx_desc->wb.upper.header_status & 1453 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1454 adapter->rx_hdr_split++; 1455 1456 e1000_receive_skb(adapter, netdev, skb, staterr, 1457 rx_desc->wb.middle.vlan); 1458 1459 next_desc: 1460 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1461 buffer_info->skb = NULL; 1462 1463 /* return some buffers to hardware, one at a time is too slow */ 1464 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1465 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1466 GFP_ATOMIC); 1467 cleaned_count = 0; 1468 } 1469 1470 /* use prefetched values */ 1471 rx_desc = next_rxd; 1472 buffer_info = next_buffer; 1473 1474 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1475 } 1476 rx_ring->next_to_clean = i; 1477 1478 cleaned_count = e1000_desc_unused(rx_ring); 1479 if (cleaned_count) 1480 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1481 1482 adapter->total_rx_bytes += total_rx_bytes; 1483 adapter->total_rx_packets += total_rx_packets; 1484 return cleaned; 1485 } 1486 1487 /** 1488 * e1000_consume_page - helper function 1489 **/ 1490 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1491 u16 length) 1492 { 1493 bi->page = NULL; 1494 skb->len += length; 1495 skb->data_len += length; 1496 skb->truesize += PAGE_SIZE; 1497 } 1498 1499 /** 1500 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1501 * @adapter: board private structure 1502 * 1503 * the return value indicates whether actual cleaning was done, there 1504 * is no guarantee that everything was cleaned 1505 **/ 1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1507 int work_to_do) 1508 { 1509 struct e1000_adapter *adapter = rx_ring->adapter; 1510 struct net_device *netdev = adapter->netdev; 1511 struct pci_dev *pdev = adapter->pdev; 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1513 struct e1000_buffer *buffer_info, *next_buffer; 1514 u32 length, staterr; 1515 unsigned int i; 1516 int cleaned_count = 0; 1517 bool cleaned = false; 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1519 struct skb_shared_info *shinfo; 1520 1521 i = rx_ring->next_to_clean; 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1524 buffer_info = &rx_ring->buffer_info[i]; 1525 1526 while (staterr & E1000_RXD_STAT_DD) { 1527 struct sk_buff *skb; 1528 1529 if (*work_done >= work_to_do) 1530 break; 1531 (*work_done)++; 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1533 1534 skb = buffer_info->skb; 1535 buffer_info->skb = NULL; 1536 1537 ++i; 1538 if (i == rx_ring->count) 1539 i = 0; 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1541 prefetch(next_rxd); 1542 1543 next_buffer = &rx_ring->buffer_info[i]; 1544 1545 cleaned = true; 1546 cleaned_count++; 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1548 DMA_FROM_DEVICE); 1549 buffer_info->dma = 0; 1550 1551 length = le16_to_cpu(rx_desc->wb.upper.length); 1552 1553 /* errors is only valid for DD + EOP descriptors */ 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1556 !(netdev->features & NETIF_F_RXALL)))) { 1557 /* recycle both page and skb */ 1558 buffer_info->skb = skb; 1559 /* an error means any chain goes out the window too */ 1560 if (rx_ring->rx_skb_top) 1561 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1562 rx_ring->rx_skb_top = NULL; 1563 goto next_desc; 1564 } 1565 #define rxtop (rx_ring->rx_skb_top) 1566 if (!(staterr & E1000_RXD_STAT_EOP)) { 1567 /* this descriptor is only the beginning (or middle) */ 1568 if (!rxtop) { 1569 /* this is the beginning of a chain */ 1570 rxtop = skb; 1571 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1572 0, length); 1573 } else { 1574 /* this is the middle of a chain */ 1575 shinfo = skb_shinfo(rxtop); 1576 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1577 buffer_info->page, 0, 1578 length); 1579 /* re-use the skb, only consumed the page */ 1580 buffer_info->skb = skb; 1581 } 1582 e1000_consume_page(buffer_info, rxtop, length); 1583 goto next_desc; 1584 } else { 1585 if (rxtop) { 1586 /* end of the chain */ 1587 shinfo = skb_shinfo(rxtop); 1588 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1589 buffer_info->page, 0, 1590 length); 1591 /* re-use the current skb, we only consumed the 1592 * page 1593 */ 1594 buffer_info->skb = skb; 1595 skb = rxtop; 1596 rxtop = NULL; 1597 e1000_consume_page(buffer_info, skb, length); 1598 } else { 1599 /* no chain, got EOP, this buf is the packet 1600 * copybreak to save the put_page/alloc_page 1601 */ 1602 if (length <= copybreak && 1603 skb_tailroom(skb) >= length) { 1604 u8 *vaddr; 1605 vaddr = kmap_atomic(buffer_info->page); 1606 memcpy(skb_tail_pointer(skb), vaddr, 1607 length); 1608 kunmap_atomic(vaddr); 1609 /* re-use the page, so don't erase 1610 * buffer_info->page 1611 */ 1612 skb_put(skb, length); 1613 } else { 1614 skb_fill_page_desc(skb, 0, 1615 buffer_info->page, 0, 1616 length); 1617 e1000_consume_page(buffer_info, skb, 1618 length); 1619 } 1620 } 1621 } 1622 1623 /* Receive Checksum Offload */ 1624 e1000_rx_checksum(adapter, staterr, skb); 1625 1626 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1627 1628 /* probably a little skewed due to removing CRC */ 1629 total_rx_bytes += skb->len; 1630 total_rx_packets++; 1631 1632 /* eth type trans needs skb->data to point to something */ 1633 if (!pskb_may_pull(skb, ETH_HLEN)) { 1634 e_err("pskb_may_pull failed.\n"); 1635 dev_kfree_skb_irq(skb); 1636 goto next_desc; 1637 } 1638 1639 e1000_receive_skb(adapter, netdev, skb, staterr, 1640 rx_desc->wb.upper.vlan); 1641 1642 next_desc: 1643 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1644 1645 /* return some buffers to hardware, one at a time is too slow */ 1646 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1647 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1648 GFP_ATOMIC); 1649 cleaned_count = 0; 1650 } 1651 1652 /* use prefetched values */ 1653 rx_desc = next_rxd; 1654 buffer_info = next_buffer; 1655 1656 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1657 } 1658 rx_ring->next_to_clean = i; 1659 1660 cleaned_count = e1000_desc_unused(rx_ring); 1661 if (cleaned_count) 1662 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1663 1664 adapter->total_rx_bytes += total_rx_bytes; 1665 adapter->total_rx_packets += total_rx_packets; 1666 return cleaned; 1667 } 1668 1669 /** 1670 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1671 * @rx_ring: Rx descriptor ring 1672 **/ 1673 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1674 { 1675 struct e1000_adapter *adapter = rx_ring->adapter; 1676 struct e1000_buffer *buffer_info; 1677 struct e1000_ps_page *ps_page; 1678 struct pci_dev *pdev = adapter->pdev; 1679 unsigned int i, j; 1680 1681 /* Free all the Rx ring sk_buffs */ 1682 for (i = 0; i < rx_ring->count; i++) { 1683 buffer_info = &rx_ring->buffer_info[i]; 1684 if (buffer_info->dma) { 1685 if (adapter->clean_rx == e1000_clean_rx_irq) 1686 dma_unmap_single(&pdev->dev, buffer_info->dma, 1687 adapter->rx_buffer_len, 1688 DMA_FROM_DEVICE); 1689 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1690 dma_unmap_page(&pdev->dev, buffer_info->dma, 1691 PAGE_SIZE, DMA_FROM_DEVICE); 1692 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1693 dma_unmap_single(&pdev->dev, buffer_info->dma, 1694 adapter->rx_ps_bsize0, 1695 DMA_FROM_DEVICE); 1696 buffer_info->dma = 0; 1697 } 1698 1699 if (buffer_info->page) { 1700 put_page(buffer_info->page); 1701 buffer_info->page = NULL; 1702 } 1703 1704 if (buffer_info->skb) { 1705 dev_kfree_skb(buffer_info->skb); 1706 buffer_info->skb = NULL; 1707 } 1708 1709 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1710 ps_page = &buffer_info->ps_pages[j]; 1711 if (!ps_page->page) 1712 break; 1713 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1714 DMA_FROM_DEVICE); 1715 ps_page->dma = 0; 1716 put_page(ps_page->page); 1717 ps_page->page = NULL; 1718 } 1719 } 1720 1721 /* there also may be some cached data from a chained receive */ 1722 if (rx_ring->rx_skb_top) { 1723 dev_kfree_skb(rx_ring->rx_skb_top); 1724 rx_ring->rx_skb_top = NULL; 1725 } 1726 1727 /* Zero out the descriptor ring */ 1728 memset(rx_ring->desc, 0, rx_ring->size); 1729 1730 rx_ring->next_to_clean = 0; 1731 rx_ring->next_to_use = 0; 1732 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1733 } 1734 1735 static void e1000e_downshift_workaround(struct work_struct *work) 1736 { 1737 struct e1000_adapter *adapter = container_of(work, 1738 struct e1000_adapter, 1739 downshift_task); 1740 1741 if (test_bit(__E1000_DOWN, &adapter->state)) 1742 return; 1743 1744 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1745 } 1746 1747 /** 1748 * e1000_intr_msi - Interrupt Handler 1749 * @irq: interrupt number 1750 * @data: pointer to a network interface device structure 1751 **/ 1752 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1753 { 1754 struct net_device *netdev = data; 1755 struct e1000_adapter *adapter = netdev_priv(netdev); 1756 struct e1000_hw *hw = &adapter->hw; 1757 u32 icr = er32(ICR); 1758 1759 /* read ICR disables interrupts using IAM */ 1760 if (icr & E1000_ICR_LSC) { 1761 hw->mac.get_link_status = true; 1762 /* ICH8 workaround-- Call gig speed drop workaround on cable 1763 * disconnect (LSC) before accessing any PHY registers 1764 */ 1765 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1766 (!(er32(STATUS) & E1000_STATUS_LU))) 1767 schedule_work(&adapter->downshift_task); 1768 1769 /* 80003ES2LAN workaround-- For packet buffer work-around on 1770 * link down event; disable receives here in the ISR and reset 1771 * adapter in watchdog 1772 */ 1773 if (netif_carrier_ok(netdev) && 1774 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1775 /* disable receives */ 1776 u32 rctl = er32(RCTL); 1777 1778 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1779 adapter->flags |= FLAG_RESTART_NOW; 1780 } 1781 /* guard against interrupt when we're going down */ 1782 if (!test_bit(__E1000_DOWN, &adapter->state)) 1783 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1784 } 1785 1786 /* Reset on uncorrectable ECC error */ 1787 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1788 u32 pbeccsts = er32(PBECCSTS); 1789 1790 adapter->corr_errors += 1791 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1792 adapter->uncorr_errors += 1793 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1794 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1795 1796 /* Do the reset outside of interrupt context */ 1797 schedule_work(&adapter->reset_task); 1798 1799 /* return immediately since reset is imminent */ 1800 return IRQ_HANDLED; 1801 } 1802 1803 if (napi_schedule_prep(&adapter->napi)) { 1804 adapter->total_tx_bytes = 0; 1805 adapter->total_tx_packets = 0; 1806 adapter->total_rx_bytes = 0; 1807 adapter->total_rx_packets = 0; 1808 __napi_schedule(&adapter->napi); 1809 } 1810 1811 return IRQ_HANDLED; 1812 } 1813 1814 /** 1815 * e1000_intr - Interrupt Handler 1816 * @irq: interrupt number 1817 * @data: pointer to a network interface device structure 1818 **/ 1819 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1820 { 1821 struct net_device *netdev = data; 1822 struct e1000_adapter *adapter = netdev_priv(netdev); 1823 struct e1000_hw *hw = &adapter->hw; 1824 u32 rctl, icr = er32(ICR); 1825 1826 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1827 return IRQ_NONE; /* Not our interrupt */ 1828 1829 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1830 * not set, then the adapter didn't send an interrupt 1831 */ 1832 if (!(icr & E1000_ICR_INT_ASSERTED)) 1833 return IRQ_NONE; 1834 1835 /* Interrupt Auto-Mask...upon reading ICR, 1836 * interrupts are masked. No need for the 1837 * IMC write 1838 */ 1839 1840 if (icr & E1000_ICR_LSC) { 1841 hw->mac.get_link_status = true; 1842 /* ICH8 workaround-- Call gig speed drop workaround on cable 1843 * disconnect (LSC) before accessing any PHY registers 1844 */ 1845 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1846 (!(er32(STATUS) & E1000_STATUS_LU))) 1847 schedule_work(&adapter->downshift_task); 1848 1849 /* 80003ES2LAN workaround-- 1850 * For packet buffer work-around on link down event; 1851 * disable receives here in the ISR and 1852 * reset adapter in watchdog 1853 */ 1854 if (netif_carrier_ok(netdev) && 1855 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1856 /* disable receives */ 1857 rctl = er32(RCTL); 1858 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1859 adapter->flags |= FLAG_RESTART_NOW; 1860 } 1861 /* guard against interrupt when we're going down */ 1862 if (!test_bit(__E1000_DOWN, &adapter->state)) 1863 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1864 } 1865 1866 /* Reset on uncorrectable ECC error */ 1867 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1868 u32 pbeccsts = er32(PBECCSTS); 1869 1870 adapter->corr_errors += 1871 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1872 adapter->uncorr_errors += 1873 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1874 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1875 1876 /* Do the reset outside of interrupt context */ 1877 schedule_work(&adapter->reset_task); 1878 1879 /* return immediately since reset is imminent */ 1880 return IRQ_HANDLED; 1881 } 1882 1883 if (napi_schedule_prep(&adapter->napi)) { 1884 adapter->total_tx_bytes = 0; 1885 adapter->total_tx_packets = 0; 1886 adapter->total_rx_bytes = 0; 1887 adapter->total_rx_packets = 0; 1888 __napi_schedule(&adapter->napi); 1889 } 1890 1891 return IRQ_HANDLED; 1892 } 1893 1894 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1895 { 1896 struct net_device *netdev = data; 1897 struct e1000_adapter *adapter = netdev_priv(netdev); 1898 struct e1000_hw *hw = &adapter->hw; 1899 u32 icr = er32(ICR); 1900 1901 if (icr & adapter->eiac_mask) 1902 ew32(ICS, (icr & adapter->eiac_mask)); 1903 1904 if (icr & E1000_ICR_LSC) { 1905 hw->mac.get_link_status = true; 1906 /* guard against interrupt when we're going down */ 1907 if (!test_bit(__E1000_DOWN, &adapter->state)) 1908 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1909 } 1910 1911 if (!test_bit(__E1000_DOWN, &adapter->state)) 1912 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1913 1914 return IRQ_HANDLED; 1915 } 1916 1917 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1918 { 1919 struct net_device *netdev = data; 1920 struct e1000_adapter *adapter = netdev_priv(netdev); 1921 struct e1000_hw *hw = &adapter->hw; 1922 struct e1000_ring *tx_ring = adapter->tx_ring; 1923 1924 adapter->total_tx_bytes = 0; 1925 adapter->total_tx_packets = 0; 1926 1927 if (!e1000_clean_tx_irq(tx_ring)) 1928 /* Ring was not completely cleaned, so fire another interrupt */ 1929 ew32(ICS, tx_ring->ims_val); 1930 1931 if (!test_bit(__E1000_DOWN, &adapter->state)) 1932 ew32(IMS, adapter->tx_ring->ims_val); 1933 1934 return IRQ_HANDLED; 1935 } 1936 1937 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1938 { 1939 struct net_device *netdev = data; 1940 struct e1000_adapter *adapter = netdev_priv(netdev); 1941 struct e1000_ring *rx_ring = adapter->rx_ring; 1942 1943 /* Write the ITR value calculated at the end of the 1944 * previous interrupt. 1945 */ 1946 if (rx_ring->set_itr) { 1947 u32 itr = rx_ring->itr_val ? 1948 1000000000 / (rx_ring->itr_val * 256) : 0; 1949 1950 writel(itr, rx_ring->itr_register); 1951 rx_ring->set_itr = 0; 1952 } 1953 1954 if (napi_schedule_prep(&adapter->napi)) { 1955 adapter->total_rx_bytes = 0; 1956 adapter->total_rx_packets = 0; 1957 __napi_schedule(&adapter->napi); 1958 } 1959 return IRQ_HANDLED; 1960 } 1961 1962 /** 1963 * e1000_configure_msix - Configure MSI-X hardware 1964 * 1965 * e1000_configure_msix sets up the hardware to properly 1966 * generate MSI-X interrupts. 1967 **/ 1968 static void e1000_configure_msix(struct e1000_adapter *adapter) 1969 { 1970 struct e1000_hw *hw = &adapter->hw; 1971 struct e1000_ring *rx_ring = adapter->rx_ring; 1972 struct e1000_ring *tx_ring = adapter->tx_ring; 1973 int vector = 0; 1974 u32 ctrl_ext, ivar = 0; 1975 1976 adapter->eiac_mask = 0; 1977 1978 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1979 if (hw->mac.type == e1000_82574) { 1980 u32 rfctl = er32(RFCTL); 1981 1982 rfctl |= E1000_RFCTL_ACK_DIS; 1983 ew32(RFCTL, rfctl); 1984 } 1985 1986 /* Configure Rx vector */ 1987 rx_ring->ims_val = E1000_IMS_RXQ0; 1988 adapter->eiac_mask |= rx_ring->ims_val; 1989 if (rx_ring->itr_val) 1990 writel(1000000000 / (rx_ring->itr_val * 256), 1991 rx_ring->itr_register); 1992 else 1993 writel(1, rx_ring->itr_register); 1994 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1995 1996 /* Configure Tx vector */ 1997 tx_ring->ims_val = E1000_IMS_TXQ0; 1998 vector++; 1999 if (tx_ring->itr_val) 2000 writel(1000000000 / (tx_ring->itr_val * 256), 2001 tx_ring->itr_register); 2002 else 2003 writel(1, tx_ring->itr_register); 2004 adapter->eiac_mask |= tx_ring->ims_val; 2005 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2006 2007 /* set vector for Other Causes, e.g. link changes */ 2008 vector++; 2009 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2010 if (rx_ring->itr_val) 2011 writel(1000000000 / (rx_ring->itr_val * 256), 2012 hw->hw_addr + E1000_EITR_82574(vector)); 2013 else 2014 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2015 2016 /* Cause Tx interrupts on every write back */ 2017 ivar |= BIT(31); 2018 2019 ew32(IVAR, ivar); 2020 2021 /* enable MSI-X PBA support */ 2022 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2023 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2024 ew32(CTRL_EXT, ctrl_ext); 2025 e1e_flush(); 2026 } 2027 2028 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2029 { 2030 if (adapter->msix_entries) { 2031 pci_disable_msix(adapter->pdev); 2032 kfree(adapter->msix_entries); 2033 adapter->msix_entries = NULL; 2034 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2035 pci_disable_msi(adapter->pdev); 2036 adapter->flags &= ~FLAG_MSI_ENABLED; 2037 } 2038 } 2039 2040 /** 2041 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2042 * 2043 * Attempt to configure interrupts using the best available 2044 * capabilities of the hardware and kernel. 2045 **/ 2046 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2047 { 2048 int err; 2049 int i; 2050 2051 switch (adapter->int_mode) { 2052 case E1000E_INT_MODE_MSIX: 2053 if (adapter->flags & FLAG_HAS_MSIX) { 2054 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2055 adapter->msix_entries = kcalloc(adapter->num_vectors, 2056 sizeof(struct 2057 msix_entry), 2058 GFP_KERNEL); 2059 if (adapter->msix_entries) { 2060 struct e1000_adapter *a = adapter; 2061 2062 for (i = 0; i < adapter->num_vectors; i++) 2063 adapter->msix_entries[i].entry = i; 2064 2065 err = pci_enable_msix_range(a->pdev, 2066 a->msix_entries, 2067 a->num_vectors, 2068 a->num_vectors); 2069 if (err > 0) 2070 return; 2071 } 2072 /* MSI-X failed, so fall through and try MSI */ 2073 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2074 e1000e_reset_interrupt_capability(adapter); 2075 } 2076 adapter->int_mode = E1000E_INT_MODE_MSI; 2077 /* Fall through */ 2078 case E1000E_INT_MODE_MSI: 2079 if (!pci_enable_msi(adapter->pdev)) { 2080 adapter->flags |= FLAG_MSI_ENABLED; 2081 } else { 2082 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2083 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2084 } 2085 /* Fall through */ 2086 case E1000E_INT_MODE_LEGACY: 2087 /* Don't do anything; this is the system default */ 2088 break; 2089 } 2090 2091 /* store the number of vectors being used */ 2092 adapter->num_vectors = 1; 2093 } 2094 2095 /** 2096 * e1000_request_msix - Initialize MSI-X interrupts 2097 * 2098 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2099 * kernel. 2100 **/ 2101 static int e1000_request_msix(struct e1000_adapter *adapter) 2102 { 2103 struct net_device *netdev = adapter->netdev; 2104 int err = 0, vector = 0; 2105 2106 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2107 snprintf(adapter->rx_ring->name, 2108 sizeof(adapter->rx_ring->name) - 1, 2109 "%.14s-rx-0", netdev->name); 2110 else 2111 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2112 err = request_irq(adapter->msix_entries[vector].vector, 2113 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2114 netdev); 2115 if (err) 2116 return err; 2117 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2118 E1000_EITR_82574(vector); 2119 adapter->rx_ring->itr_val = adapter->itr; 2120 vector++; 2121 2122 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2123 snprintf(adapter->tx_ring->name, 2124 sizeof(adapter->tx_ring->name) - 1, 2125 "%.14s-tx-0", netdev->name); 2126 else 2127 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2128 err = request_irq(adapter->msix_entries[vector].vector, 2129 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2130 netdev); 2131 if (err) 2132 return err; 2133 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2134 E1000_EITR_82574(vector); 2135 adapter->tx_ring->itr_val = adapter->itr; 2136 vector++; 2137 2138 err = request_irq(adapter->msix_entries[vector].vector, 2139 e1000_msix_other, 0, netdev->name, netdev); 2140 if (err) 2141 return err; 2142 2143 e1000_configure_msix(adapter); 2144 2145 return 0; 2146 } 2147 2148 /** 2149 * e1000_request_irq - initialize interrupts 2150 * 2151 * Attempts to configure interrupts using the best available 2152 * capabilities of the hardware and kernel. 2153 **/ 2154 static int e1000_request_irq(struct e1000_adapter *adapter) 2155 { 2156 struct net_device *netdev = adapter->netdev; 2157 int err; 2158 2159 if (adapter->msix_entries) { 2160 err = e1000_request_msix(adapter); 2161 if (!err) 2162 return err; 2163 /* fall back to MSI */ 2164 e1000e_reset_interrupt_capability(adapter); 2165 adapter->int_mode = E1000E_INT_MODE_MSI; 2166 e1000e_set_interrupt_capability(adapter); 2167 } 2168 if (adapter->flags & FLAG_MSI_ENABLED) { 2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2170 netdev->name, netdev); 2171 if (!err) 2172 return err; 2173 2174 /* fall back to legacy interrupt */ 2175 e1000e_reset_interrupt_capability(adapter); 2176 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2177 } 2178 2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2180 netdev->name, netdev); 2181 if (err) 2182 e_err("Unable to allocate interrupt, Error: %d\n", err); 2183 2184 return err; 2185 } 2186 2187 static void e1000_free_irq(struct e1000_adapter *adapter) 2188 { 2189 struct net_device *netdev = adapter->netdev; 2190 2191 if (adapter->msix_entries) { 2192 int vector = 0; 2193 2194 free_irq(adapter->msix_entries[vector].vector, netdev); 2195 vector++; 2196 2197 free_irq(adapter->msix_entries[vector].vector, netdev); 2198 vector++; 2199 2200 /* Other Causes interrupt vector */ 2201 free_irq(adapter->msix_entries[vector].vector, netdev); 2202 return; 2203 } 2204 2205 free_irq(adapter->pdev->irq, netdev); 2206 } 2207 2208 /** 2209 * e1000_irq_disable - Mask off interrupt generation on the NIC 2210 **/ 2211 static void e1000_irq_disable(struct e1000_adapter *adapter) 2212 { 2213 struct e1000_hw *hw = &adapter->hw; 2214 2215 ew32(IMC, ~0); 2216 if (adapter->msix_entries) 2217 ew32(EIAC_82574, 0); 2218 e1e_flush(); 2219 2220 if (adapter->msix_entries) { 2221 int i; 2222 2223 for (i = 0; i < adapter->num_vectors; i++) 2224 synchronize_irq(adapter->msix_entries[i].vector); 2225 } else { 2226 synchronize_irq(adapter->pdev->irq); 2227 } 2228 } 2229 2230 /** 2231 * e1000_irq_enable - Enable default interrupt generation settings 2232 **/ 2233 static void e1000_irq_enable(struct e1000_adapter *adapter) 2234 { 2235 struct e1000_hw *hw = &adapter->hw; 2236 2237 if (adapter->msix_entries) { 2238 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2239 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2240 IMS_OTHER_MASK); 2241 } else if (hw->mac.type >= e1000_pch_lpt) { 2242 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2243 } else { 2244 ew32(IMS, IMS_ENABLE_MASK); 2245 } 2246 e1e_flush(); 2247 } 2248 2249 /** 2250 * e1000e_get_hw_control - get control of the h/w from f/w 2251 * @adapter: address of board private structure 2252 * 2253 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2254 * For ASF and Pass Through versions of f/w this means that 2255 * the driver is loaded. For AMT version (only with 82573) 2256 * of the f/w this means that the network i/f is open. 2257 **/ 2258 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2259 { 2260 struct e1000_hw *hw = &adapter->hw; 2261 u32 ctrl_ext; 2262 u32 swsm; 2263 2264 /* Let firmware know the driver has taken over */ 2265 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2266 swsm = er32(SWSM); 2267 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2268 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2269 ctrl_ext = er32(CTRL_EXT); 2270 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2271 } 2272 } 2273 2274 /** 2275 * e1000e_release_hw_control - release control of the h/w to f/w 2276 * @adapter: address of board private structure 2277 * 2278 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2279 * For ASF and Pass Through versions of f/w this means that the 2280 * driver is no longer loaded. For AMT version (only with 82573) i 2281 * of the f/w this means that the network i/f is closed. 2282 * 2283 **/ 2284 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2285 { 2286 struct e1000_hw *hw = &adapter->hw; 2287 u32 ctrl_ext; 2288 u32 swsm; 2289 2290 /* Let firmware taken over control of h/w */ 2291 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2292 swsm = er32(SWSM); 2293 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2294 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2295 ctrl_ext = er32(CTRL_EXT); 2296 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2297 } 2298 } 2299 2300 /** 2301 * e1000_alloc_ring_dma - allocate memory for a ring structure 2302 **/ 2303 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2304 struct e1000_ring *ring) 2305 { 2306 struct pci_dev *pdev = adapter->pdev; 2307 2308 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2309 GFP_KERNEL); 2310 if (!ring->desc) 2311 return -ENOMEM; 2312 2313 return 0; 2314 } 2315 2316 /** 2317 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2318 * @tx_ring: Tx descriptor ring 2319 * 2320 * Return 0 on success, negative on failure 2321 **/ 2322 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2323 { 2324 struct e1000_adapter *adapter = tx_ring->adapter; 2325 int err = -ENOMEM, size; 2326 2327 size = sizeof(struct e1000_buffer) * tx_ring->count; 2328 tx_ring->buffer_info = vzalloc(size); 2329 if (!tx_ring->buffer_info) 2330 goto err; 2331 2332 /* round up to nearest 4K */ 2333 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2334 tx_ring->size = ALIGN(tx_ring->size, 4096); 2335 2336 err = e1000_alloc_ring_dma(adapter, tx_ring); 2337 if (err) 2338 goto err; 2339 2340 tx_ring->next_to_use = 0; 2341 tx_ring->next_to_clean = 0; 2342 2343 return 0; 2344 err: 2345 vfree(tx_ring->buffer_info); 2346 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2347 return err; 2348 } 2349 2350 /** 2351 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2352 * @rx_ring: Rx descriptor ring 2353 * 2354 * Returns 0 on success, negative on failure 2355 **/ 2356 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2357 { 2358 struct e1000_adapter *adapter = rx_ring->adapter; 2359 struct e1000_buffer *buffer_info; 2360 int i, size, desc_len, err = -ENOMEM; 2361 2362 size = sizeof(struct e1000_buffer) * rx_ring->count; 2363 rx_ring->buffer_info = vzalloc(size); 2364 if (!rx_ring->buffer_info) 2365 goto err; 2366 2367 for (i = 0; i < rx_ring->count; i++) { 2368 buffer_info = &rx_ring->buffer_info[i]; 2369 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2370 sizeof(struct e1000_ps_page), 2371 GFP_KERNEL); 2372 if (!buffer_info->ps_pages) 2373 goto err_pages; 2374 } 2375 2376 desc_len = sizeof(union e1000_rx_desc_packet_split); 2377 2378 /* Round up to nearest 4K */ 2379 rx_ring->size = rx_ring->count * desc_len; 2380 rx_ring->size = ALIGN(rx_ring->size, 4096); 2381 2382 err = e1000_alloc_ring_dma(adapter, rx_ring); 2383 if (err) 2384 goto err_pages; 2385 2386 rx_ring->next_to_clean = 0; 2387 rx_ring->next_to_use = 0; 2388 rx_ring->rx_skb_top = NULL; 2389 2390 return 0; 2391 2392 err_pages: 2393 for (i = 0; i < rx_ring->count; i++) { 2394 buffer_info = &rx_ring->buffer_info[i]; 2395 kfree(buffer_info->ps_pages); 2396 } 2397 err: 2398 vfree(rx_ring->buffer_info); 2399 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2400 return err; 2401 } 2402 2403 /** 2404 * e1000_clean_tx_ring - Free Tx Buffers 2405 * @tx_ring: Tx descriptor ring 2406 **/ 2407 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2408 { 2409 struct e1000_adapter *adapter = tx_ring->adapter; 2410 struct e1000_buffer *buffer_info; 2411 unsigned long size; 2412 unsigned int i; 2413 2414 for (i = 0; i < tx_ring->count; i++) { 2415 buffer_info = &tx_ring->buffer_info[i]; 2416 e1000_put_txbuf(tx_ring, buffer_info, false); 2417 } 2418 2419 netdev_reset_queue(adapter->netdev); 2420 size = sizeof(struct e1000_buffer) * tx_ring->count; 2421 memset(tx_ring->buffer_info, 0, size); 2422 2423 memset(tx_ring->desc, 0, tx_ring->size); 2424 2425 tx_ring->next_to_use = 0; 2426 tx_ring->next_to_clean = 0; 2427 } 2428 2429 /** 2430 * e1000e_free_tx_resources - Free Tx Resources per Queue 2431 * @tx_ring: Tx descriptor ring 2432 * 2433 * Free all transmit software resources 2434 **/ 2435 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2436 { 2437 struct e1000_adapter *adapter = tx_ring->adapter; 2438 struct pci_dev *pdev = adapter->pdev; 2439 2440 e1000_clean_tx_ring(tx_ring); 2441 2442 vfree(tx_ring->buffer_info); 2443 tx_ring->buffer_info = NULL; 2444 2445 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2446 tx_ring->dma); 2447 tx_ring->desc = NULL; 2448 } 2449 2450 /** 2451 * e1000e_free_rx_resources - Free Rx Resources 2452 * @rx_ring: Rx descriptor ring 2453 * 2454 * Free all receive software resources 2455 **/ 2456 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2457 { 2458 struct e1000_adapter *adapter = rx_ring->adapter; 2459 struct pci_dev *pdev = adapter->pdev; 2460 int i; 2461 2462 e1000_clean_rx_ring(rx_ring); 2463 2464 for (i = 0; i < rx_ring->count; i++) 2465 kfree(rx_ring->buffer_info[i].ps_pages); 2466 2467 vfree(rx_ring->buffer_info); 2468 rx_ring->buffer_info = NULL; 2469 2470 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2471 rx_ring->dma); 2472 rx_ring->desc = NULL; 2473 } 2474 2475 /** 2476 * e1000_update_itr - update the dynamic ITR value based on statistics 2477 * @adapter: pointer to adapter 2478 * @itr_setting: current adapter->itr 2479 * @packets: the number of packets during this measurement interval 2480 * @bytes: the number of bytes during this measurement interval 2481 * 2482 * Stores a new ITR value based on packets and byte 2483 * counts during the last interrupt. The advantage of per interrupt 2484 * computation is faster updates and more accurate ITR for the current 2485 * traffic pattern. Constants in this function were computed 2486 * based on theoretical maximum wire speed and thresholds were set based 2487 * on testing data as well as attempting to minimize response time 2488 * while increasing bulk throughput. This functionality is controlled 2489 * by the InterruptThrottleRate module parameter. 2490 **/ 2491 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2492 { 2493 unsigned int retval = itr_setting; 2494 2495 if (packets == 0) 2496 return itr_setting; 2497 2498 switch (itr_setting) { 2499 case lowest_latency: 2500 /* handle TSO and jumbo frames */ 2501 if (bytes / packets > 8000) 2502 retval = bulk_latency; 2503 else if ((packets < 5) && (bytes > 512)) 2504 retval = low_latency; 2505 break; 2506 case low_latency: /* 50 usec aka 20000 ints/s */ 2507 if (bytes > 10000) { 2508 /* this if handles the TSO accounting */ 2509 if (bytes / packets > 8000) 2510 retval = bulk_latency; 2511 else if ((packets < 10) || ((bytes / packets) > 1200)) 2512 retval = bulk_latency; 2513 else if ((packets > 35)) 2514 retval = lowest_latency; 2515 } else if (bytes / packets > 2000) { 2516 retval = bulk_latency; 2517 } else if (packets <= 2 && bytes < 512) { 2518 retval = lowest_latency; 2519 } 2520 break; 2521 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2522 if (bytes > 25000) { 2523 if (packets > 35) 2524 retval = low_latency; 2525 } else if (bytes < 6000) { 2526 retval = low_latency; 2527 } 2528 break; 2529 } 2530 2531 return retval; 2532 } 2533 2534 static void e1000_set_itr(struct e1000_adapter *adapter) 2535 { 2536 u16 current_itr; 2537 u32 new_itr = adapter->itr; 2538 2539 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2540 if (adapter->link_speed != SPEED_1000) { 2541 current_itr = 0; 2542 new_itr = 4000; 2543 goto set_itr_now; 2544 } 2545 2546 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2547 new_itr = 0; 2548 goto set_itr_now; 2549 } 2550 2551 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2552 adapter->total_tx_packets, 2553 adapter->total_tx_bytes); 2554 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2555 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2556 adapter->tx_itr = low_latency; 2557 2558 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2559 adapter->total_rx_packets, 2560 adapter->total_rx_bytes); 2561 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2562 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2563 adapter->rx_itr = low_latency; 2564 2565 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2566 2567 /* counts and packets in update_itr are dependent on these numbers */ 2568 switch (current_itr) { 2569 case lowest_latency: 2570 new_itr = 70000; 2571 break; 2572 case low_latency: 2573 new_itr = 20000; /* aka hwitr = ~200 */ 2574 break; 2575 case bulk_latency: 2576 new_itr = 4000; 2577 break; 2578 default: 2579 break; 2580 } 2581 2582 set_itr_now: 2583 if (new_itr != adapter->itr) { 2584 /* this attempts to bias the interrupt rate towards Bulk 2585 * by adding intermediate steps when interrupt rate is 2586 * increasing 2587 */ 2588 new_itr = new_itr > adapter->itr ? 2589 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2590 adapter->itr = new_itr; 2591 adapter->rx_ring->itr_val = new_itr; 2592 if (adapter->msix_entries) 2593 adapter->rx_ring->set_itr = 1; 2594 else 2595 e1000e_write_itr(adapter, new_itr); 2596 } 2597 } 2598 2599 /** 2600 * e1000e_write_itr - write the ITR value to the appropriate registers 2601 * @adapter: address of board private structure 2602 * @itr: new ITR value to program 2603 * 2604 * e1000e_write_itr determines if the adapter is in MSI-X mode 2605 * and, if so, writes the EITR registers with the ITR value. 2606 * Otherwise, it writes the ITR value into the ITR register. 2607 **/ 2608 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2609 { 2610 struct e1000_hw *hw = &adapter->hw; 2611 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2612 2613 if (adapter->msix_entries) { 2614 int vector; 2615 2616 for (vector = 0; vector < adapter->num_vectors; vector++) 2617 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2618 } else { 2619 ew32(ITR, new_itr); 2620 } 2621 } 2622 2623 /** 2624 * e1000_alloc_queues - Allocate memory for all rings 2625 * @adapter: board private structure to initialize 2626 **/ 2627 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2628 { 2629 int size = sizeof(struct e1000_ring); 2630 2631 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2632 if (!adapter->tx_ring) 2633 goto err; 2634 adapter->tx_ring->count = adapter->tx_ring_count; 2635 adapter->tx_ring->adapter = adapter; 2636 2637 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2638 if (!adapter->rx_ring) 2639 goto err; 2640 adapter->rx_ring->count = adapter->rx_ring_count; 2641 adapter->rx_ring->adapter = adapter; 2642 2643 return 0; 2644 err: 2645 e_err("Unable to allocate memory for queues\n"); 2646 kfree(adapter->rx_ring); 2647 kfree(adapter->tx_ring); 2648 return -ENOMEM; 2649 } 2650 2651 /** 2652 * e1000e_poll - NAPI Rx polling callback 2653 * @napi: struct associated with this polling callback 2654 * @budget: number of packets driver is allowed to process this poll 2655 **/ 2656 static int e1000e_poll(struct napi_struct *napi, int budget) 2657 { 2658 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2659 napi); 2660 struct e1000_hw *hw = &adapter->hw; 2661 struct net_device *poll_dev = adapter->netdev; 2662 int tx_cleaned = 1, work_done = 0; 2663 2664 adapter = netdev_priv(poll_dev); 2665 2666 if (!adapter->msix_entries || 2667 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2668 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2669 2670 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2671 2672 if (!tx_cleaned || work_done == budget) 2673 return budget; 2674 2675 /* Exit the polling mode, but don't re-enable interrupts if stack might 2676 * poll us due to busy-polling 2677 */ 2678 if (likely(napi_complete_done(napi, work_done))) { 2679 if (adapter->itr_setting & 3) 2680 e1000_set_itr(adapter); 2681 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2682 if (adapter->msix_entries) 2683 ew32(IMS, adapter->rx_ring->ims_val); 2684 else 2685 e1000_irq_enable(adapter); 2686 } 2687 } 2688 2689 return work_done; 2690 } 2691 2692 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2693 __always_unused __be16 proto, u16 vid) 2694 { 2695 struct e1000_adapter *adapter = netdev_priv(netdev); 2696 struct e1000_hw *hw = &adapter->hw; 2697 u32 vfta, index; 2698 2699 /* don't update vlan cookie if already programmed */ 2700 if ((adapter->hw.mng_cookie.status & 2701 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2702 (vid == adapter->mng_vlan_id)) 2703 return 0; 2704 2705 /* add VID to filter table */ 2706 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2707 index = (vid >> 5) & 0x7F; 2708 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2709 vfta |= BIT((vid & 0x1F)); 2710 hw->mac.ops.write_vfta(hw, index, vfta); 2711 } 2712 2713 set_bit(vid, adapter->active_vlans); 2714 2715 return 0; 2716 } 2717 2718 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2719 __always_unused __be16 proto, u16 vid) 2720 { 2721 struct e1000_adapter *adapter = netdev_priv(netdev); 2722 struct e1000_hw *hw = &adapter->hw; 2723 u32 vfta, index; 2724 2725 if ((adapter->hw.mng_cookie.status & 2726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2727 (vid == adapter->mng_vlan_id)) { 2728 /* release control to f/w */ 2729 e1000e_release_hw_control(adapter); 2730 return 0; 2731 } 2732 2733 /* remove VID from filter table */ 2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2735 index = (vid >> 5) & 0x7F; 2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2737 vfta &= ~BIT((vid & 0x1F)); 2738 hw->mac.ops.write_vfta(hw, index, vfta); 2739 } 2740 2741 clear_bit(vid, adapter->active_vlans); 2742 2743 return 0; 2744 } 2745 2746 /** 2747 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2748 * @adapter: board private structure to initialize 2749 **/ 2750 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2751 { 2752 struct net_device *netdev = adapter->netdev; 2753 struct e1000_hw *hw = &adapter->hw; 2754 u32 rctl; 2755 2756 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2757 /* disable VLAN receive filtering */ 2758 rctl = er32(RCTL); 2759 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2760 ew32(RCTL, rctl); 2761 2762 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2763 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2764 adapter->mng_vlan_id); 2765 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2766 } 2767 } 2768 } 2769 2770 /** 2771 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2772 * @adapter: board private structure to initialize 2773 **/ 2774 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2775 { 2776 struct e1000_hw *hw = &adapter->hw; 2777 u32 rctl; 2778 2779 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2780 /* enable VLAN receive filtering */ 2781 rctl = er32(RCTL); 2782 rctl |= E1000_RCTL_VFE; 2783 rctl &= ~E1000_RCTL_CFIEN; 2784 ew32(RCTL, rctl); 2785 } 2786 } 2787 2788 /** 2789 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2790 * @adapter: board private structure to initialize 2791 **/ 2792 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2793 { 2794 struct e1000_hw *hw = &adapter->hw; 2795 u32 ctrl; 2796 2797 /* disable VLAN tag insert/strip */ 2798 ctrl = er32(CTRL); 2799 ctrl &= ~E1000_CTRL_VME; 2800 ew32(CTRL, ctrl); 2801 } 2802 2803 /** 2804 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2805 * @adapter: board private structure to initialize 2806 **/ 2807 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2808 { 2809 struct e1000_hw *hw = &adapter->hw; 2810 u32 ctrl; 2811 2812 /* enable VLAN tag insert/strip */ 2813 ctrl = er32(CTRL); 2814 ctrl |= E1000_CTRL_VME; 2815 ew32(CTRL, ctrl); 2816 } 2817 2818 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2819 { 2820 struct net_device *netdev = adapter->netdev; 2821 u16 vid = adapter->hw.mng_cookie.vlan_id; 2822 u16 old_vid = adapter->mng_vlan_id; 2823 2824 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2825 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2826 adapter->mng_vlan_id = vid; 2827 } 2828 2829 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2830 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2831 } 2832 2833 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2834 { 2835 u16 vid; 2836 2837 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2838 2839 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2841 } 2842 2843 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2844 { 2845 struct e1000_hw *hw = &adapter->hw; 2846 u32 manc, manc2h, mdef, i, j; 2847 2848 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2849 return; 2850 2851 manc = er32(MANC); 2852 2853 /* enable receiving management packets to the host. this will probably 2854 * generate destination unreachable messages from the host OS, but 2855 * the packets will be handled on SMBUS 2856 */ 2857 manc |= E1000_MANC_EN_MNG2HOST; 2858 manc2h = er32(MANC2H); 2859 2860 switch (hw->mac.type) { 2861 default: 2862 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2863 break; 2864 case e1000_82574: 2865 case e1000_82583: 2866 /* Check if IPMI pass-through decision filter already exists; 2867 * if so, enable it. 2868 */ 2869 for (i = 0, j = 0; i < 8; i++) { 2870 mdef = er32(MDEF(i)); 2871 2872 /* Ignore filters with anything other than IPMI ports */ 2873 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2874 continue; 2875 2876 /* Enable this decision filter in MANC2H */ 2877 if (mdef) 2878 manc2h |= BIT(i); 2879 2880 j |= mdef; 2881 } 2882 2883 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2884 break; 2885 2886 /* Create new decision filter in an empty filter */ 2887 for (i = 0, j = 0; i < 8; i++) 2888 if (er32(MDEF(i)) == 0) { 2889 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2890 E1000_MDEF_PORT_664)); 2891 manc2h |= BIT(1); 2892 j++; 2893 break; 2894 } 2895 2896 if (!j) 2897 e_warn("Unable to create IPMI pass-through filter\n"); 2898 break; 2899 } 2900 2901 ew32(MANC2H, manc2h); 2902 ew32(MANC, manc); 2903 } 2904 2905 /** 2906 * e1000_configure_tx - Configure Transmit Unit after Reset 2907 * @adapter: board private structure 2908 * 2909 * Configure the Tx unit of the MAC after a reset. 2910 **/ 2911 static void e1000_configure_tx(struct e1000_adapter *adapter) 2912 { 2913 struct e1000_hw *hw = &adapter->hw; 2914 struct e1000_ring *tx_ring = adapter->tx_ring; 2915 u64 tdba; 2916 u32 tdlen, tctl, tarc; 2917 2918 /* Setup the HW Tx Head and Tail descriptor pointers */ 2919 tdba = tx_ring->dma; 2920 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2921 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2922 ew32(TDBAH(0), (tdba >> 32)); 2923 ew32(TDLEN(0), tdlen); 2924 ew32(TDH(0), 0); 2925 ew32(TDT(0), 0); 2926 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2927 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2928 2929 writel(0, tx_ring->head); 2930 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2931 e1000e_update_tdt_wa(tx_ring, 0); 2932 else 2933 writel(0, tx_ring->tail); 2934 2935 /* Set the Tx Interrupt Delay register */ 2936 ew32(TIDV, adapter->tx_int_delay); 2937 /* Tx irq moderation */ 2938 ew32(TADV, adapter->tx_abs_int_delay); 2939 2940 if (adapter->flags2 & FLAG2_DMA_BURST) { 2941 u32 txdctl = er32(TXDCTL(0)); 2942 2943 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2944 E1000_TXDCTL_WTHRESH); 2945 /* set up some performance related parameters to encourage the 2946 * hardware to use the bus more efficiently in bursts, depends 2947 * on the tx_int_delay to be enabled, 2948 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2949 * hthresh = 1 ==> prefetch when one or more available 2950 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2951 * BEWARE: this seems to work but should be considered first if 2952 * there are Tx hangs or other Tx related bugs 2953 */ 2954 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2955 ew32(TXDCTL(0), txdctl); 2956 } 2957 /* erratum work around: set txdctl the same for both queues */ 2958 ew32(TXDCTL(1), er32(TXDCTL(0))); 2959 2960 /* Program the Transmit Control Register */ 2961 tctl = er32(TCTL); 2962 tctl &= ~E1000_TCTL_CT; 2963 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2964 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2965 2966 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2967 tarc = er32(TARC(0)); 2968 /* set the speed mode bit, we'll clear it if we're not at 2969 * gigabit link later 2970 */ 2971 #define SPEED_MODE_BIT BIT(21) 2972 tarc |= SPEED_MODE_BIT; 2973 ew32(TARC(0), tarc); 2974 } 2975 2976 /* errata: program both queues to unweighted RR */ 2977 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2978 tarc = er32(TARC(0)); 2979 tarc |= 1; 2980 ew32(TARC(0), tarc); 2981 tarc = er32(TARC(1)); 2982 tarc |= 1; 2983 ew32(TARC(1), tarc); 2984 } 2985 2986 /* Setup Transmit Descriptor Settings for eop descriptor */ 2987 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2988 2989 /* only set IDE if we are delaying interrupts using the timers */ 2990 if (adapter->tx_int_delay) 2991 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2992 2993 /* enable Report Status bit */ 2994 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2995 2996 ew32(TCTL, tctl); 2997 2998 hw->mac.ops.config_collision_dist(hw); 2999 3000 /* SPT and KBL Si errata workaround to avoid data corruption */ 3001 if (hw->mac.type == e1000_pch_spt) { 3002 u32 reg_val; 3003 3004 reg_val = er32(IOSFPC); 3005 reg_val |= E1000_RCTL_RDMTS_HEX; 3006 ew32(IOSFPC, reg_val); 3007 3008 reg_val = er32(TARC(0)); 3009 /* SPT and KBL Si errata workaround to avoid Tx hang. 3010 * Dropping the number of outstanding requests from 3011 * 3 to 2 in order to avoid a buffer overrun. 3012 */ 3013 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3014 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3015 ew32(TARC(0), reg_val); 3016 } 3017 } 3018 3019 /** 3020 * e1000_setup_rctl - configure the receive control registers 3021 * @adapter: Board private structure 3022 **/ 3023 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3025 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3026 { 3027 struct e1000_hw *hw = &adapter->hw; 3028 u32 rctl, rfctl; 3029 u32 pages = 0; 3030 3031 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3032 * If jumbo frames not set, program related MAC/PHY registers 3033 * to h/w defaults 3034 */ 3035 if (hw->mac.type >= e1000_pch2lan) { 3036 s32 ret_val; 3037 3038 if (adapter->netdev->mtu > ETH_DATA_LEN) 3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3040 else 3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3042 3043 if (ret_val) 3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3045 } 3046 3047 /* Program MC offset vector base */ 3048 rctl = er32(RCTL); 3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3053 3054 /* Do not Store bad packets */ 3055 rctl &= ~E1000_RCTL_SBP; 3056 3057 /* Enable Long Packet receive */ 3058 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3059 rctl &= ~E1000_RCTL_LPE; 3060 else 3061 rctl |= E1000_RCTL_LPE; 3062 3063 /* Some systems expect that the CRC is included in SMBUS traffic. The 3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3065 * host memory when this is enabled 3066 */ 3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3068 rctl |= E1000_RCTL_SECRC; 3069 3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3072 u16 phy_data; 3073 3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3075 phy_data &= 0xfff8; 3076 phy_data |= BIT(2); 3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3078 3079 e1e_rphy(hw, 22, &phy_data); 3080 phy_data &= 0x0fff; 3081 phy_data |= BIT(14); 3082 e1e_wphy(hw, 0x10, 0x2823); 3083 e1e_wphy(hw, 0x11, 0x0003); 3084 e1e_wphy(hw, 22, phy_data); 3085 } 3086 3087 /* Setup buffer sizes */ 3088 rctl &= ~E1000_RCTL_SZ_4096; 3089 rctl |= E1000_RCTL_BSEX; 3090 switch (adapter->rx_buffer_len) { 3091 case 2048: 3092 default: 3093 rctl |= E1000_RCTL_SZ_2048; 3094 rctl &= ~E1000_RCTL_BSEX; 3095 break; 3096 case 4096: 3097 rctl |= E1000_RCTL_SZ_4096; 3098 break; 3099 case 8192: 3100 rctl |= E1000_RCTL_SZ_8192; 3101 break; 3102 case 16384: 3103 rctl |= E1000_RCTL_SZ_16384; 3104 break; 3105 } 3106 3107 /* Enable Extended Status in all Receive Descriptors */ 3108 rfctl = er32(RFCTL); 3109 rfctl |= E1000_RFCTL_EXTEN; 3110 ew32(RFCTL, rfctl); 3111 3112 /* 82571 and greater support packet-split where the protocol 3113 * header is placed in skb->data and the packet data is 3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3115 * In the case of a non-split, skb->data is linearly filled, 3116 * followed by the page buffers. Therefore, skb->data is 3117 * sized to hold the largest protocol header. 3118 * 3119 * allocations using alloc_page take too long for regular MTU 3120 * so only enable packet split for jumbo frames 3121 * 3122 * Using pages when the page size is greater than 16k wastes 3123 * a lot of memory, since we allocate 3 pages at all times 3124 * per packet. 3125 */ 3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3128 adapter->rx_ps_pages = pages; 3129 else 3130 adapter->rx_ps_pages = 0; 3131 3132 if (adapter->rx_ps_pages) { 3133 u32 psrctl = 0; 3134 3135 /* Enable Packet split descriptors */ 3136 rctl |= E1000_RCTL_DTYP_PS; 3137 3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3139 3140 switch (adapter->rx_ps_pages) { 3141 case 3: 3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3143 /* fall-through */ 3144 case 2: 3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3146 /* fall-through */ 3147 case 1: 3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3149 break; 3150 } 3151 3152 ew32(PSRCTL, psrctl); 3153 } 3154 3155 /* This is useful for sniffing bad packets. */ 3156 if (adapter->netdev->features & NETIF_F_RXALL) { 3157 /* UPE and MPE will be handled by normal PROMISC logic 3158 * in e1000e_set_rx_mode 3159 */ 3160 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3161 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3162 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3163 3164 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3165 E1000_RCTL_DPF | /* Allow filtered pause */ 3166 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3168 * and that breaks VLANs. 3169 */ 3170 } 3171 3172 ew32(RCTL, rctl); 3173 /* just started the receive unit, no need to restart */ 3174 adapter->flags &= ~FLAG_RESTART_NOW; 3175 } 3176 3177 /** 3178 * e1000_configure_rx - Configure Receive Unit after Reset 3179 * @adapter: board private structure 3180 * 3181 * Configure the Rx unit of the MAC after a reset. 3182 **/ 3183 static void e1000_configure_rx(struct e1000_adapter *adapter) 3184 { 3185 struct e1000_hw *hw = &adapter->hw; 3186 struct e1000_ring *rx_ring = adapter->rx_ring; 3187 u64 rdba; 3188 u32 rdlen, rctl, rxcsum, ctrl_ext; 3189 3190 if (adapter->rx_ps_pages) { 3191 /* this is a 32 byte descriptor */ 3192 rdlen = rx_ring->count * 3193 sizeof(union e1000_rx_desc_packet_split); 3194 adapter->clean_rx = e1000_clean_rx_irq_ps; 3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3200 } else { 3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3202 adapter->clean_rx = e1000_clean_rx_irq; 3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3204 } 3205 3206 /* disable receives while setting up the descriptors */ 3207 rctl = er32(RCTL); 3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3209 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3210 e1e_flush(); 3211 usleep_range(10000, 11000); 3212 3213 if (adapter->flags2 & FLAG2_DMA_BURST) { 3214 /* set the writeback threshold (only takes effect if the RDTR 3215 * is set). set GRAN=1 and write back up to 0x4 worth, and 3216 * enable prefetching of 0x20 Rx descriptors 3217 * granularity = 01 3218 * wthresh = 04, 3219 * hthresh = 04, 3220 * pthresh = 0x20 3221 */ 3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3224 } 3225 3226 /* set the Receive Delay Timer Register */ 3227 ew32(RDTR, adapter->rx_int_delay); 3228 3229 /* irq moderation */ 3230 ew32(RADV, adapter->rx_abs_int_delay); 3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3232 e1000e_write_itr(adapter, adapter->itr); 3233 3234 ctrl_ext = er32(CTRL_EXT); 3235 /* Auto-Mask interrupts upon ICR access */ 3236 ctrl_ext |= E1000_CTRL_EXT_IAME; 3237 ew32(IAM, 0xffffffff); 3238 ew32(CTRL_EXT, ctrl_ext); 3239 e1e_flush(); 3240 3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3242 * the Base and Length of the Rx Descriptor Ring 3243 */ 3244 rdba = rx_ring->dma; 3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3246 ew32(RDBAH(0), (rdba >> 32)); 3247 ew32(RDLEN(0), rdlen); 3248 ew32(RDH(0), 0); 3249 ew32(RDT(0), 0); 3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3252 3253 writel(0, rx_ring->head); 3254 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3255 e1000e_update_rdt_wa(rx_ring, 0); 3256 else 3257 writel(0, rx_ring->tail); 3258 3259 /* Enable Receive Checksum Offload for TCP and UDP */ 3260 rxcsum = er32(RXCSUM); 3261 if (adapter->netdev->features & NETIF_F_RXCSUM) 3262 rxcsum |= E1000_RXCSUM_TUOFL; 3263 else 3264 rxcsum &= ~E1000_RXCSUM_TUOFL; 3265 ew32(RXCSUM, rxcsum); 3266 3267 /* With jumbo frames, excessive C-state transition latencies result 3268 * in dropped transactions. 3269 */ 3270 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3271 u32 lat = 3272 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3273 adapter->max_frame_size) * 8 / 1000; 3274 3275 if (adapter->flags & FLAG_IS_ICH) { 3276 u32 rxdctl = er32(RXDCTL(0)); 3277 3278 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3279 } 3280 3281 dev_info(&adapter->pdev->dev, 3282 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3283 pm_qos_update_request(&adapter->pm_qos_req, lat); 3284 } else { 3285 pm_qos_update_request(&adapter->pm_qos_req, 3286 PM_QOS_DEFAULT_VALUE); 3287 } 3288 3289 /* Enable Receives */ 3290 ew32(RCTL, rctl); 3291 } 3292 3293 /** 3294 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3295 * @netdev: network interface device structure 3296 * 3297 * Writes multicast address list to the MTA hash table. 3298 * Returns: -ENOMEM on failure 3299 * 0 on no addresses written 3300 * X on writing X addresses to MTA 3301 */ 3302 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3303 { 3304 struct e1000_adapter *adapter = netdev_priv(netdev); 3305 struct e1000_hw *hw = &adapter->hw; 3306 struct netdev_hw_addr *ha; 3307 u8 *mta_list; 3308 int i; 3309 3310 if (netdev_mc_empty(netdev)) { 3311 /* nothing to program, so clear mc list */ 3312 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3313 return 0; 3314 } 3315 3316 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3317 if (!mta_list) 3318 return -ENOMEM; 3319 3320 /* update_mc_addr_list expects a packed array of only addresses. */ 3321 i = 0; 3322 netdev_for_each_mc_addr(ha, netdev) 3323 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3324 3325 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3326 kfree(mta_list); 3327 3328 return netdev_mc_count(netdev); 3329 } 3330 3331 /** 3332 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3333 * @netdev: network interface device structure 3334 * 3335 * Writes unicast address list to the RAR table. 3336 * Returns: -ENOMEM on failure/insufficient address space 3337 * 0 on no addresses written 3338 * X on writing X addresses to the RAR table 3339 **/ 3340 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3341 { 3342 struct e1000_adapter *adapter = netdev_priv(netdev); 3343 struct e1000_hw *hw = &adapter->hw; 3344 unsigned int rar_entries; 3345 int count = 0; 3346 3347 rar_entries = hw->mac.ops.rar_get_count(hw); 3348 3349 /* save a rar entry for our hardware address */ 3350 rar_entries--; 3351 3352 /* save a rar entry for the LAA workaround */ 3353 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3354 rar_entries--; 3355 3356 /* return ENOMEM indicating insufficient memory for addresses */ 3357 if (netdev_uc_count(netdev) > rar_entries) 3358 return -ENOMEM; 3359 3360 if (!netdev_uc_empty(netdev) && rar_entries) { 3361 struct netdev_hw_addr *ha; 3362 3363 /* write the addresses in reverse order to avoid write 3364 * combining 3365 */ 3366 netdev_for_each_uc_addr(ha, netdev) { 3367 int ret_val; 3368 3369 if (!rar_entries) 3370 break; 3371 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3372 if (ret_val < 0) 3373 return -ENOMEM; 3374 count++; 3375 } 3376 } 3377 3378 /* zero out the remaining RAR entries not used above */ 3379 for (; rar_entries > 0; rar_entries--) { 3380 ew32(RAH(rar_entries), 0); 3381 ew32(RAL(rar_entries), 0); 3382 } 3383 e1e_flush(); 3384 3385 return count; 3386 } 3387 3388 /** 3389 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3390 * @netdev: network interface device structure 3391 * 3392 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3393 * address list or the network interface flags are updated. This routine is 3394 * responsible for configuring the hardware for proper unicast, multicast, 3395 * promiscuous mode, and all-multi behavior. 3396 **/ 3397 static void e1000e_set_rx_mode(struct net_device *netdev) 3398 { 3399 struct e1000_adapter *adapter = netdev_priv(netdev); 3400 struct e1000_hw *hw = &adapter->hw; 3401 u32 rctl; 3402 3403 if (pm_runtime_suspended(netdev->dev.parent)) 3404 return; 3405 3406 /* Check for Promiscuous and All Multicast modes */ 3407 rctl = er32(RCTL); 3408 3409 /* clear the affected bits */ 3410 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3411 3412 if (netdev->flags & IFF_PROMISC) { 3413 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3414 /* Do not hardware filter VLANs in promisc mode */ 3415 e1000e_vlan_filter_disable(adapter); 3416 } else { 3417 int count; 3418 3419 if (netdev->flags & IFF_ALLMULTI) { 3420 rctl |= E1000_RCTL_MPE; 3421 } else { 3422 /* Write addresses to the MTA, if the attempt fails 3423 * then we should just turn on promiscuous mode so 3424 * that we can at least receive multicast traffic 3425 */ 3426 count = e1000e_write_mc_addr_list(netdev); 3427 if (count < 0) 3428 rctl |= E1000_RCTL_MPE; 3429 } 3430 e1000e_vlan_filter_enable(adapter); 3431 /* Write addresses to available RAR registers, if there is not 3432 * sufficient space to store all the addresses then enable 3433 * unicast promiscuous mode 3434 */ 3435 count = e1000e_write_uc_addr_list(netdev); 3436 if (count < 0) 3437 rctl |= E1000_RCTL_UPE; 3438 } 3439 3440 ew32(RCTL, rctl); 3441 3442 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3443 e1000e_vlan_strip_enable(adapter); 3444 else 3445 e1000e_vlan_strip_disable(adapter); 3446 } 3447 3448 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3449 { 3450 struct e1000_hw *hw = &adapter->hw; 3451 u32 mrqc, rxcsum; 3452 u32 rss_key[10]; 3453 int i; 3454 3455 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3456 for (i = 0; i < 10; i++) 3457 ew32(RSSRK(i), rss_key[i]); 3458 3459 /* Direct all traffic to queue 0 */ 3460 for (i = 0; i < 32; i++) 3461 ew32(RETA(i), 0); 3462 3463 /* Disable raw packet checksumming so that RSS hash is placed in 3464 * descriptor on writeback. 3465 */ 3466 rxcsum = er32(RXCSUM); 3467 rxcsum |= E1000_RXCSUM_PCSD; 3468 3469 ew32(RXCSUM, rxcsum); 3470 3471 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3472 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3473 E1000_MRQC_RSS_FIELD_IPV6 | 3474 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3475 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3476 3477 ew32(MRQC, mrqc); 3478 } 3479 3480 /** 3481 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3482 * @adapter: board private structure 3483 * @timinca: pointer to returned time increment attributes 3484 * 3485 * Get attributes for incrementing the System Time Register SYSTIML/H at 3486 * the default base frequency, and set the cyclecounter shift value. 3487 **/ 3488 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3489 { 3490 struct e1000_hw *hw = &adapter->hw; 3491 u32 incvalue, incperiod, shift; 3492 3493 /* Make sure clock is enabled on I217/I218/I219 before checking 3494 * the frequency 3495 */ 3496 if ((hw->mac.type >= e1000_pch_lpt) && 3497 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3498 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3499 u32 fextnvm7 = er32(FEXTNVM7); 3500 3501 if (!(fextnvm7 & BIT(0))) { 3502 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3503 e1e_flush(); 3504 } 3505 } 3506 3507 switch (hw->mac.type) { 3508 case e1000_pch2lan: 3509 /* Stable 96MHz frequency */ 3510 incperiod = INCPERIOD_96MHZ; 3511 incvalue = INCVALUE_96MHZ; 3512 shift = INCVALUE_SHIFT_96MHZ; 3513 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3514 break; 3515 case e1000_pch_lpt: 3516 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3517 /* Stable 96MHz frequency */ 3518 incperiod = INCPERIOD_96MHZ; 3519 incvalue = INCVALUE_96MHZ; 3520 shift = INCVALUE_SHIFT_96MHZ; 3521 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3522 } else { 3523 /* Stable 25MHz frequency */ 3524 incperiod = INCPERIOD_25MHZ; 3525 incvalue = INCVALUE_25MHZ; 3526 shift = INCVALUE_SHIFT_25MHZ; 3527 adapter->cc.shift = shift; 3528 } 3529 break; 3530 case e1000_pch_spt: 3531 /* Stable 24MHz frequency */ 3532 incperiod = INCPERIOD_24MHZ; 3533 incvalue = INCVALUE_24MHZ; 3534 shift = INCVALUE_SHIFT_24MHZ; 3535 adapter->cc.shift = shift; 3536 break; 3537 case e1000_pch_cnp: 3538 case e1000_pch_tgp: 3539 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3540 /* Stable 24MHz frequency */ 3541 incperiod = INCPERIOD_24MHZ; 3542 incvalue = INCVALUE_24MHZ; 3543 shift = INCVALUE_SHIFT_24MHZ; 3544 adapter->cc.shift = shift; 3545 } else { 3546 /* Stable 38400KHz frequency */ 3547 incperiod = INCPERIOD_38400KHZ; 3548 incvalue = INCVALUE_38400KHZ; 3549 shift = INCVALUE_SHIFT_38400KHZ; 3550 adapter->cc.shift = shift; 3551 } 3552 break; 3553 case e1000_82574: 3554 case e1000_82583: 3555 /* Stable 25MHz frequency */ 3556 incperiod = INCPERIOD_25MHZ; 3557 incvalue = INCVALUE_25MHZ; 3558 shift = INCVALUE_SHIFT_25MHZ; 3559 adapter->cc.shift = shift; 3560 break; 3561 default: 3562 return -EINVAL; 3563 } 3564 3565 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3566 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3567 3568 return 0; 3569 } 3570 3571 /** 3572 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3573 * @adapter: board private structure 3574 * 3575 * Outgoing time stamping can be enabled and disabled. Play nice and 3576 * disable it when requested, although it shouldn't cause any overhead 3577 * when no packet needs it. At most one packet in the queue may be 3578 * marked for time stamping, otherwise it would be impossible to tell 3579 * for sure to which packet the hardware time stamp belongs. 3580 * 3581 * Incoming time stamping has to be configured via the hardware filters. 3582 * Not all combinations are supported, in particular event type has to be 3583 * specified. Matching the kind of event packet is not supported, with the 3584 * exception of "all V2 events regardless of level 2 or 4". 3585 **/ 3586 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3587 struct hwtstamp_config *config) 3588 { 3589 struct e1000_hw *hw = &adapter->hw; 3590 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3591 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3592 u32 rxmtrl = 0; 3593 u16 rxudp = 0; 3594 bool is_l4 = false; 3595 bool is_l2 = false; 3596 u32 regval; 3597 3598 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3599 return -EINVAL; 3600 3601 /* flags reserved for future extensions - must be zero */ 3602 if (config->flags) 3603 return -EINVAL; 3604 3605 switch (config->tx_type) { 3606 case HWTSTAMP_TX_OFF: 3607 tsync_tx_ctl = 0; 3608 break; 3609 case HWTSTAMP_TX_ON: 3610 break; 3611 default: 3612 return -ERANGE; 3613 } 3614 3615 switch (config->rx_filter) { 3616 case HWTSTAMP_FILTER_NONE: 3617 tsync_rx_ctl = 0; 3618 break; 3619 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3620 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3621 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3622 is_l4 = true; 3623 break; 3624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3626 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3627 is_l4 = true; 3628 break; 3629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3630 /* Also time stamps V2 L2 Path Delay Request/Response */ 3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3632 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3633 is_l2 = true; 3634 break; 3635 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3636 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3638 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3639 is_l2 = true; 3640 break; 3641 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3642 /* Hardware cannot filter just V2 L4 Sync messages; 3643 * fall-through to V2 (both L2 and L4) Sync. 3644 */ 3645 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3646 /* Also time stamps V2 Path Delay Request/Response. */ 3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3649 is_l2 = true; 3650 is_l4 = true; 3651 break; 3652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3653 /* Hardware cannot filter just V2 L4 Delay Request messages; 3654 * fall-through to V2 (both L2 and L4) Delay Request. 3655 */ 3656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3657 /* Also time stamps V2 Path Delay Request/Response. */ 3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3659 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3660 is_l2 = true; 3661 is_l4 = true; 3662 break; 3663 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3665 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3666 * fall-through to all V2 (both L2 and L4) Events. 3667 */ 3668 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3670 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3671 is_l2 = true; 3672 is_l4 = true; 3673 break; 3674 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3675 /* For V1, the hardware can only filter Sync messages or 3676 * Delay Request messages but not both so fall-through to 3677 * time stamp all packets. 3678 */ 3679 case HWTSTAMP_FILTER_NTP_ALL: 3680 case HWTSTAMP_FILTER_ALL: 3681 is_l2 = true; 3682 is_l4 = true; 3683 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3684 config->rx_filter = HWTSTAMP_FILTER_ALL; 3685 break; 3686 default: 3687 return -ERANGE; 3688 } 3689 3690 adapter->hwtstamp_config = *config; 3691 3692 /* enable/disable Tx h/w time stamping */ 3693 regval = er32(TSYNCTXCTL); 3694 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3695 regval |= tsync_tx_ctl; 3696 ew32(TSYNCTXCTL, regval); 3697 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3698 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3699 e_err("Timesync Tx Control register not set as expected\n"); 3700 return -EAGAIN; 3701 } 3702 3703 /* enable/disable Rx h/w time stamping */ 3704 regval = er32(TSYNCRXCTL); 3705 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3706 regval |= tsync_rx_ctl; 3707 ew32(TSYNCRXCTL, regval); 3708 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3709 E1000_TSYNCRXCTL_TYPE_MASK)) != 3710 (regval & (E1000_TSYNCRXCTL_ENABLED | 3711 E1000_TSYNCRXCTL_TYPE_MASK))) { 3712 e_err("Timesync Rx Control register not set as expected\n"); 3713 return -EAGAIN; 3714 } 3715 3716 /* L2: define ethertype filter for time stamped packets */ 3717 if (is_l2) 3718 rxmtrl |= ETH_P_1588; 3719 3720 /* define which PTP packets get time stamped */ 3721 ew32(RXMTRL, rxmtrl); 3722 3723 /* Filter by destination port */ 3724 if (is_l4) { 3725 rxudp = PTP_EV_PORT; 3726 cpu_to_be16s(&rxudp); 3727 } 3728 ew32(RXUDP, rxudp); 3729 3730 e1e_flush(); 3731 3732 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3733 er32(RXSTMPH); 3734 er32(TXSTMPH); 3735 3736 return 0; 3737 } 3738 3739 /** 3740 * e1000_configure - configure the hardware for Rx and Tx 3741 * @adapter: private board structure 3742 **/ 3743 static void e1000_configure(struct e1000_adapter *adapter) 3744 { 3745 struct e1000_ring *rx_ring = adapter->rx_ring; 3746 3747 e1000e_set_rx_mode(adapter->netdev); 3748 3749 e1000_restore_vlan(adapter); 3750 e1000_init_manageability_pt(adapter); 3751 3752 e1000_configure_tx(adapter); 3753 3754 if (adapter->netdev->features & NETIF_F_RXHASH) 3755 e1000e_setup_rss_hash(adapter); 3756 e1000_setup_rctl(adapter); 3757 e1000_configure_rx(adapter); 3758 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3759 } 3760 3761 /** 3762 * e1000e_power_up_phy - restore link in case the phy was powered down 3763 * @adapter: address of board private structure 3764 * 3765 * The phy may be powered down to save power and turn off link when the 3766 * driver is unloaded and wake on lan is not enabled (among others) 3767 * *** this routine MUST be followed by a call to e1000e_reset *** 3768 **/ 3769 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3770 { 3771 if (adapter->hw.phy.ops.power_up) 3772 adapter->hw.phy.ops.power_up(&adapter->hw); 3773 3774 adapter->hw.mac.ops.setup_link(&adapter->hw); 3775 } 3776 3777 /** 3778 * e1000_power_down_phy - Power down the PHY 3779 * 3780 * Power down the PHY so no link is implied when interface is down. 3781 * The PHY cannot be powered down if management or WoL is active. 3782 */ 3783 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3784 { 3785 if (adapter->hw.phy.ops.power_down) 3786 adapter->hw.phy.ops.power_down(&adapter->hw); 3787 } 3788 3789 /** 3790 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3791 * 3792 * We want to clear all pending descriptors from the TX ring. 3793 * zeroing happens when the HW reads the regs. We assign the ring itself as 3794 * the data of the next descriptor. We don't care about the data we are about 3795 * to reset the HW. 3796 */ 3797 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3798 { 3799 struct e1000_hw *hw = &adapter->hw; 3800 struct e1000_ring *tx_ring = adapter->tx_ring; 3801 struct e1000_tx_desc *tx_desc = NULL; 3802 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3803 u16 size = 512; 3804 3805 tctl = er32(TCTL); 3806 ew32(TCTL, tctl | E1000_TCTL_EN); 3807 tdt = er32(TDT(0)); 3808 BUG_ON(tdt != tx_ring->next_to_use); 3809 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3810 tx_desc->buffer_addr = tx_ring->dma; 3811 3812 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3813 tx_desc->upper.data = 0; 3814 /* flush descriptors to memory before notifying the HW */ 3815 wmb(); 3816 tx_ring->next_to_use++; 3817 if (tx_ring->next_to_use == tx_ring->count) 3818 tx_ring->next_to_use = 0; 3819 ew32(TDT(0), tx_ring->next_to_use); 3820 usleep_range(200, 250); 3821 } 3822 3823 /** 3824 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3825 * 3826 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3827 */ 3828 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3829 { 3830 u32 rctl, rxdctl; 3831 struct e1000_hw *hw = &adapter->hw; 3832 3833 rctl = er32(RCTL); 3834 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3835 e1e_flush(); 3836 usleep_range(100, 150); 3837 3838 rxdctl = er32(RXDCTL(0)); 3839 /* zero the lower 14 bits (prefetch and host thresholds) */ 3840 rxdctl &= 0xffffc000; 3841 3842 /* update thresholds: prefetch threshold to 31, host threshold to 1 3843 * and make sure the granularity is "descriptors" and not "cache lines" 3844 */ 3845 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3846 3847 ew32(RXDCTL(0), rxdctl); 3848 /* momentarily enable the RX ring for the changes to take effect */ 3849 ew32(RCTL, rctl | E1000_RCTL_EN); 3850 e1e_flush(); 3851 usleep_range(100, 150); 3852 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3853 } 3854 3855 /** 3856 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3857 * 3858 * In i219, the descriptor rings must be emptied before resetting the HW 3859 * or before changing the device state to D3 during runtime (runtime PM). 3860 * 3861 * Failure to do this will cause the HW to enter a unit hang state which can 3862 * only be released by PCI reset on the device 3863 * 3864 */ 3865 3866 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3867 { 3868 u16 hang_state; 3869 u32 fext_nvm11, tdlen; 3870 struct e1000_hw *hw = &adapter->hw; 3871 3872 /* First, disable MULR fix in FEXTNVM11 */ 3873 fext_nvm11 = er32(FEXTNVM11); 3874 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3875 ew32(FEXTNVM11, fext_nvm11); 3876 /* do nothing if we're not in faulty state, or if the queue is empty */ 3877 tdlen = er32(TDLEN(0)); 3878 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3879 &hang_state); 3880 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3881 return; 3882 e1000_flush_tx_ring(adapter); 3883 /* recheck, maybe the fault is caused by the rx ring */ 3884 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3885 &hang_state); 3886 if (hang_state & FLUSH_DESC_REQUIRED) 3887 e1000_flush_rx_ring(adapter); 3888 } 3889 3890 /** 3891 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3892 * @adapter: board private structure 3893 * 3894 * When the MAC is reset, all hardware bits for timesync will be reset to the 3895 * default values. This function will restore the settings last in place. 3896 * Since the clock SYSTIME registers are reset, we will simply restore the 3897 * cyclecounter to the kernel real clock time. 3898 **/ 3899 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3900 { 3901 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3902 struct e1000_hw *hw = &adapter->hw; 3903 unsigned long flags; 3904 u32 timinca; 3905 s32 ret_val; 3906 3907 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3908 return; 3909 3910 if (info->adjfreq) { 3911 /* restore the previous ptp frequency delta */ 3912 ret_val = info->adjfreq(info, adapter->ptp_delta); 3913 } else { 3914 /* set the default base frequency if no adjustment possible */ 3915 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3916 if (!ret_val) 3917 ew32(TIMINCA, timinca); 3918 } 3919 3920 if (ret_val) { 3921 dev_warn(&adapter->pdev->dev, 3922 "Failed to restore TIMINCA clock rate delta: %d\n", 3923 ret_val); 3924 return; 3925 } 3926 3927 /* reset the systim ns time counter */ 3928 spin_lock_irqsave(&adapter->systim_lock, flags); 3929 timecounter_init(&adapter->tc, &adapter->cc, 3930 ktime_to_ns(ktime_get_real())); 3931 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3932 3933 /* restore the previous hwtstamp configuration settings */ 3934 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3935 } 3936 3937 /** 3938 * e1000e_reset - bring the hardware into a known good state 3939 * 3940 * This function boots the hardware and enables some settings that 3941 * require a configuration cycle of the hardware - those cannot be 3942 * set/changed during runtime. After reset the device needs to be 3943 * properly configured for Rx, Tx etc. 3944 */ 3945 void e1000e_reset(struct e1000_adapter *adapter) 3946 { 3947 struct e1000_mac_info *mac = &adapter->hw.mac; 3948 struct e1000_fc_info *fc = &adapter->hw.fc; 3949 struct e1000_hw *hw = &adapter->hw; 3950 u32 tx_space, min_tx_space, min_rx_space; 3951 u32 pba = adapter->pba; 3952 u16 hwm; 3953 3954 /* reset Packet Buffer Allocation to default */ 3955 ew32(PBA, pba); 3956 3957 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3958 /* To maintain wire speed transmits, the Tx FIFO should be 3959 * large enough to accommodate two full transmit packets, 3960 * rounded up to the next 1KB and expressed in KB. Likewise, 3961 * the Rx FIFO should be large enough to accommodate at least 3962 * one full receive packet and is similarly rounded up and 3963 * expressed in KB. 3964 */ 3965 pba = er32(PBA); 3966 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3967 tx_space = pba >> 16; 3968 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3969 pba &= 0xffff; 3970 /* the Tx fifo also stores 16 bytes of information about the Tx 3971 * but don't include ethernet FCS because hardware appends it 3972 */ 3973 min_tx_space = (adapter->max_frame_size + 3974 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3975 min_tx_space = ALIGN(min_tx_space, 1024); 3976 min_tx_space >>= 10; 3977 /* software strips receive CRC, so leave room for it */ 3978 min_rx_space = adapter->max_frame_size; 3979 min_rx_space = ALIGN(min_rx_space, 1024); 3980 min_rx_space >>= 10; 3981 3982 /* If current Tx allocation is less than the min Tx FIFO size, 3983 * and the min Tx FIFO size is less than the current Rx FIFO 3984 * allocation, take space away from current Rx allocation 3985 */ 3986 if ((tx_space < min_tx_space) && 3987 ((min_tx_space - tx_space) < pba)) { 3988 pba -= min_tx_space - tx_space; 3989 3990 /* if short on Rx space, Rx wins and must trump Tx 3991 * adjustment 3992 */ 3993 if (pba < min_rx_space) 3994 pba = min_rx_space; 3995 } 3996 3997 ew32(PBA, pba); 3998 } 3999 4000 /* flow control settings 4001 * 4002 * The high water mark must be low enough to fit one full frame 4003 * (or the size used for early receive) above it in the Rx FIFO. 4004 * Set it to the lower of: 4005 * - 90% of the Rx FIFO size, and 4006 * - the full Rx FIFO size minus one full frame 4007 */ 4008 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4009 fc->pause_time = 0xFFFF; 4010 else 4011 fc->pause_time = E1000_FC_PAUSE_TIME; 4012 fc->send_xon = true; 4013 fc->current_mode = fc->requested_mode; 4014 4015 switch (hw->mac.type) { 4016 case e1000_ich9lan: 4017 case e1000_ich10lan: 4018 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4019 pba = 14; 4020 ew32(PBA, pba); 4021 fc->high_water = 0x2800; 4022 fc->low_water = fc->high_water - 8; 4023 break; 4024 } 4025 /* fall-through */ 4026 default: 4027 hwm = min(((pba << 10) * 9 / 10), 4028 ((pba << 10) - adapter->max_frame_size)); 4029 4030 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4031 fc->low_water = fc->high_water - 8; 4032 break; 4033 case e1000_pchlan: 4034 /* Workaround PCH LOM adapter hangs with certain network 4035 * loads. If hangs persist, try disabling Tx flow control. 4036 */ 4037 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4038 fc->high_water = 0x3500; 4039 fc->low_water = 0x1500; 4040 } else { 4041 fc->high_water = 0x5000; 4042 fc->low_water = 0x3000; 4043 } 4044 fc->refresh_time = 0x1000; 4045 break; 4046 case e1000_pch2lan: 4047 case e1000_pch_lpt: 4048 case e1000_pch_spt: 4049 case e1000_pch_cnp: 4050 /* fall-through */ 4051 case e1000_pch_tgp: 4052 fc->refresh_time = 0xFFFF; 4053 fc->pause_time = 0xFFFF; 4054 4055 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4056 fc->high_water = 0x05C20; 4057 fc->low_water = 0x05048; 4058 break; 4059 } 4060 4061 pba = 14; 4062 ew32(PBA, pba); 4063 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4064 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4065 break; 4066 } 4067 4068 /* Alignment of Tx data is on an arbitrary byte boundary with the 4069 * maximum size per Tx descriptor limited only to the transmit 4070 * allocation of the packet buffer minus 96 bytes with an upper 4071 * limit of 24KB due to receive synchronization limitations. 4072 */ 4073 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4074 24 << 10); 4075 4076 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4077 * fit in receive buffer. 4078 */ 4079 if (adapter->itr_setting & 0x3) { 4080 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4081 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4082 dev_info(&adapter->pdev->dev, 4083 "Interrupt Throttle Rate off\n"); 4084 adapter->flags2 |= FLAG2_DISABLE_AIM; 4085 e1000e_write_itr(adapter, 0); 4086 } 4087 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4088 dev_info(&adapter->pdev->dev, 4089 "Interrupt Throttle Rate on\n"); 4090 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4091 adapter->itr = 20000; 4092 e1000e_write_itr(adapter, adapter->itr); 4093 } 4094 } 4095 4096 if (hw->mac.type >= e1000_pch_spt) 4097 e1000_flush_desc_rings(adapter); 4098 /* Allow time for pending master requests to run */ 4099 mac->ops.reset_hw(hw); 4100 4101 /* For parts with AMT enabled, let the firmware know 4102 * that the network interface is in control 4103 */ 4104 if (adapter->flags & FLAG_HAS_AMT) 4105 e1000e_get_hw_control(adapter); 4106 4107 ew32(WUC, 0); 4108 4109 if (mac->ops.init_hw(hw)) 4110 e_err("Hardware Error\n"); 4111 4112 e1000_update_mng_vlan(adapter); 4113 4114 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4115 ew32(VET, ETH_P_8021Q); 4116 4117 e1000e_reset_adaptive(hw); 4118 4119 /* restore systim and hwtstamp settings */ 4120 e1000e_systim_reset(adapter); 4121 4122 /* Set EEE advertisement as appropriate */ 4123 if (adapter->flags2 & FLAG2_HAS_EEE) { 4124 s32 ret_val; 4125 u16 adv_addr; 4126 4127 switch (hw->phy.type) { 4128 case e1000_phy_82579: 4129 adv_addr = I82579_EEE_ADVERTISEMENT; 4130 break; 4131 case e1000_phy_i217: 4132 adv_addr = I217_EEE_ADVERTISEMENT; 4133 break; 4134 default: 4135 dev_err(&adapter->pdev->dev, 4136 "Invalid PHY type setting EEE advertisement\n"); 4137 return; 4138 } 4139 4140 ret_val = hw->phy.ops.acquire(hw); 4141 if (ret_val) { 4142 dev_err(&adapter->pdev->dev, 4143 "EEE advertisement - unable to acquire PHY\n"); 4144 return; 4145 } 4146 4147 e1000_write_emi_reg_locked(hw, adv_addr, 4148 hw->dev_spec.ich8lan.eee_disable ? 4149 0 : adapter->eee_advert); 4150 4151 hw->phy.ops.release(hw); 4152 } 4153 4154 if (!netif_running(adapter->netdev) && 4155 !test_bit(__E1000_TESTING, &adapter->state)) 4156 e1000_power_down_phy(adapter); 4157 4158 e1000_get_phy_info(hw); 4159 4160 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4161 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4162 u16 phy_data = 0; 4163 /* speed up time to link by disabling smart power down, ignore 4164 * the return value of this function because there is nothing 4165 * different we would do if it failed 4166 */ 4167 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4168 phy_data &= ~IGP02E1000_PM_SPD; 4169 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4170 } 4171 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4172 u32 reg; 4173 4174 /* Fextnvm7 @ 0xe4[2] = 1 */ 4175 reg = er32(FEXTNVM7); 4176 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4177 ew32(FEXTNVM7, reg); 4178 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4179 reg = er32(FEXTNVM9); 4180 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4181 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4182 ew32(FEXTNVM9, reg); 4183 } 4184 4185 } 4186 4187 /** 4188 * e1000e_trigger_lsc - trigger an LSC interrupt 4189 * @adapter: 4190 * 4191 * Fire a link status change interrupt to start the watchdog. 4192 **/ 4193 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4194 { 4195 struct e1000_hw *hw = &adapter->hw; 4196 4197 if (adapter->msix_entries) 4198 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4199 else 4200 ew32(ICS, E1000_ICS_LSC); 4201 } 4202 4203 void e1000e_up(struct e1000_adapter *adapter) 4204 { 4205 /* hardware has been reset, we need to reload some things */ 4206 e1000_configure(adapter); 4207 4208 clear_bit(__E1000_DOWN, &adapter->state); 4209 4210 if (adapter->msix_entries) 4211 e1000_configure_msix(adapter); 4212 e1000_irq_enable(adapter); 4213 4214 /* Tx queue started by watchdog timer when link is up */ 4215 4216 e1000e_trigger_lsc(adapter); 4217 } 4218 4219 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4220 { 4221 struct e1000_hw *hw = &adapter->hw; 4222 4223 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4224 return; 4225 4226 /* flush pending descriptor writebacks to memory */ 4227 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4228 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4229 4230 /* execute the writes immediately */ 4231 e1e_flush(); 4232 4233 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4234 * write is successful 4235 */ 4236 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4237 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4238 4239 /* execute the writes immediately */ 4240 e1e_flush(); 4241 } 4242 4243 static void e1000e_update_stats(struct e1000_adapter *adapter); 4244 4245 /** 4246 * e1000e_down - quiesce the device and optionally reset the hardware 4247 * @adapter: board private structure 4248 * @reset: boolean flag to reset the hardware or not 4249 */ 4250 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4251 { 4252 struct net_device *netdev = adapter->netdev; 4253 struct e1000_hw *hw = &adapter->hw; 4254 u32 tctl, rctl; 4255 4256 /* signal that we're down so the interrupt handler does not 4257 * reschedule our watchdog timer 4258 */ 4259 set_bit(__E1000_DOWN, &adapter->state); 4260 4261 netif_carrier_off(netdev); 4262 4263 /* disable receives in the hardware */ 4264 rctl = er32(RCTL); 4265 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4266 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4267 /* flush and sleep below */ 4268 4269 netif_stop_queue(netdev); 4270 4271 /* disable transmits in the hardware */ 4272 tctl = er32(TCTL); 4273 tctl &= ~E1000_TCTL_EN; 4274 ew32(TCTL, tctl); 4275 4276 /* flush both disables and wait for them to finish */ 4277 e1e_flush(); 4278 usleep_range(10000, 11000); 4279 4280 e1000_irq_disable(adapter); 4281 4282 napi_synchronize(&adapter->napi); 4283 4284 del_timer_sync(&adapter->watchdog_timer); 4285 del_timer_sync(&adapter->phy_info_timer); 4286 4287 spin_lock(&adapter->stats64_lock); 4288 e1000e_update_stats(adapter); 4289 spin_unlock(&adapter->stats64_lock); 4290 4291 e1000e_flush_descriptors(adapter); 4292 4293 adapter->link_speed = 0; 4294 adapter->link_duplex = 0; 4295 4296 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4297 if ((hw->mac.type >= e1000_pch2lan) && 4298 (adapter->netdev->mtu > ETH_DATA_LEN) && 4299 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4300 e_dbg("failed to disable jumbo frame workaround mode\n"); 4301 4302 if (!pci_channel_offline(adapter->pdev)) { 4303 if (reset) 4304 e1000e_reset(adapter); 4305 else if (hw->mac.type >= e1000_pch_spt) 4306 e1000_flush_desc_rings(adapter); 4307 } 4308 e1000_clean_tx_ring(adapter->tx_ring); 4309 e1000_clean_rx_ring(adapter->rx_ring); 4310 } 4311 4312 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4313 { 4314 might_sleep(); 4315 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4316 usleep_range(1000, 1100); 4317 e1000e_down(adapter, true); 4318 e1000e_up(adapter); 4319 clear_bit(__E1000_RESETTING, &adapter->state); 4320 } 4321 4322 /** 4323 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4324 * @hw: pointer to the HW structure 4325 * @systim: PHC time value read, sanitized and returned 4326 * @sts: structure to hold system time before and after reading SYSTIML, 4327 * may be NULL 4328 * 4329 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4330 * check to see that the time is incrementing at a reasonable 4331 * rate and is a multiple of incvalue. 4332 **/ 4333 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4334 struct ptp_system_timestamp *sts) 4335 { 4336 u64 time_delta, rem, temp; 4337 u64 systim_next; 4338 u32 incvalue; 4339 int i; 4340 4341 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4342 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4343 /* latch SYSTIMH on read of SYSTIML */ 4344 ptp_read_system_prets(sts); 4345 systim_next = (u64)er32(SYSTIML); 4346 ptp_read_system_postts(sts); 4347 systim_next |= (u64)er32(SYSTIMH) << 32; 4348 4349 time_delta = systim_next - systim; 4350 temp = time_delta; 4351 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4352 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4353 4354 systim = systim_next; 4355 4356 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4357 break; 4358 } 4359 4360 return systim; 4361 } 4362 4363 /** 4364 * e1000e_read_systim - read SYSTIM register 4365 * @adapter: board private structure 4366 * @sts: structure which will contain system time before and after reading 4367 * SYSTIML, may be NULL 4368 **/ 4369 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4370 struct ptp_system_timestamp *sts) 4371 { 4372 struct e1000_hw *hw = &adapter->hw; 4373 u32 systimel, systimel_2, systimeh; 4374 u64 systim; 4375 /* SYSTIMH latching upon SYSTIML read does not work well. 4376 * This means that if SYSTIML overflows after we read it but before 4377 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4378 * will experience a huge non linear increment in the systime value 4379 * to fix that we test for overflow and if true, we re-read systime. 4380 */ 4381 ptp_read_system_prets(sts); 4382 systimel = er32(SYSTIML); 4383 ptp_read_system_postts(sts); 4384 systimeh = er32(SYSTIMH); 4385 /* Is systimel is so large that overflow is possible? */ 4386 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4387 ptp_read_system_prets(sts); 4388 systimel_2 = er32(SYSTIML); 4389 ptp_read_system_postts(sts); 4390 if (systimel > systimel_2) { 4391 /* There was an overflow, read again SYSTIMH, and use 4392 * systimel_2 4393 */ 4394 systimeh = er32(SYSTIMH); 4395 systimel = systimel_2; 4396 } 4397 } 4398 systim = (u64)systimel; 4399 systim |= (u64)systimeh << 32; 4400 4401 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4402 systim = e1000e_sanitize_systim(hw, systim, sts); 4403 4404 return systim; 4405 } 4406 4407 /** 4408 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4409 * @cc: cyclecounter structure 4410 **/ 4411 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4412 { 4413 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4414 cc); 4415 4416 return e1000e_read_systim(adapter, NULL); 4417 } 4418 4419 /** 4420 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4421 * @adapter: board private structure to initialize 4422 * 4423 * e1000_sw_init initializes the Adapter private data structure. 4424 * Fields are initialized based on PCI device information and 4425 * OS network device settings (MTU size). 4426 **/ 4427 static int e1000_sw_init(struct e1000_adapter *adapter) 4428 { 4429 struct net_device *netdev = adapter->netdev; 4430 4431 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4432 adapter->rx_ps_bsize0 = 128; 4433 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4434 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4435 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4436 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4437 4438 spin_lock_init(&adapter->stats64_lock); 4439 4440 e1000e_set_interrupt_capability(adapter); 4441 4442 if (e1000_alloc_queues(adapter)) 4443 return -ENOMEM; 4444 4445 /* Setup hardware time stamping cyclecounter */ 4446 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4447 adapter->cc.read = e1000e_cyclecounter_read; 4448 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4449 adapter->cc.mult = 1; 4450 /* cc.shift set in e1000e_get_base_tininca() */ 4451 4452 spin_lock_init(&adapter->systim_lock); 4453 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4454 } 4455 4456 /* Explicitly disable IRQ since the NIC can be in any state. */ 4457 e1000_irq_disable(adapter); 4458 4459 set_bit(__E1000_DOWN, &adapter->state); 4460 return 0; 4461 } 4462 4463 /** 4464 * e1000_intr_msi_test - Interrupt Handler 4465 * @irq: interrupt number 4466 * @data: pointer to a network interface device structure 4467 **/ 4468 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4469 { 4470 struct net_device *netdev = data; 4471 struct e1000_adapter *adapter = netdev_priv(netdev); 4472 struct e1000_hw *hw = &adapter->hw; 4473 u32 icr = er32(ICR); 4474 4475 e_dbg("icr is %08X\n", icr); 4476 if (icr & E1000_ICR_RXSEQ) { 4477 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4478 /* Force memory writes to complete before acknowledging the 4479 * interrupt is handled. 4480 */ 4481 wmb(); 4482 } 4483 4484 return IRQ_HANDLED; 4485 } 4486 4487 /** 4488 * e1000_test_msi_interrupt - Returns 0 for successful test 4489 * @adapter: board private struct 4490 * 4491 * code flow taken from tg3.c 4492 **/ 4493 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4494 { 4495 struct net_device *netdev = adapter->netdev; 4496 struct e1000_hw *hw = &adapter->hw; 4497 int err; 4498 4499 /* poll_enable hasn't been called yet, so don't need disable */ 4500 /* clear any pending events */ 4501 er32(ICR); 4502 4503 /* free the real vector and request a test handler */ 4504 e1000_free_irq(adapter); 4505 e1000e_reset_interrupt_capability(adapter); 4506 4507 /* Assume that the test fails, if it succeeds then the test 4508 * MSI irq handler will unset this flag 4509 */ 4510 adapter->flags |= FLAG_MSI_TEST_FAILED; 4511 4512 err = pci_enable_msi(adapter->pdev); 4513 if (err) 4514 goto msi_test_failed; 4515 4516 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4517 netdev->name, netdev); 4518 if (err) { 4519 pci_disable_msi(adapter->pdev); 4520 goto msi_test_failed; 4521 } 4522 4523 /* Force memory writes to complete before enabling and firing an 4524 * interrupt. 4525 */ 4526 wmb(); 4527 4528 e1000_irq_enable(adapter); 4529 4530 /* fire an unusual interrupt on the test handler */ 4531 ew32(ICS, E1000_ICS_RXSEQ); 4532 e1e_flush(); 4533 msleep(100); 4534 4535 e1000_irq_disable(adapter); 4536 4537 rmb(); /* read flags after interrupt has been fired */ 4538 4539 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4540 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4541 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4542 } else { 4543 e_dbg("MSI interrupt test succeeded!\n"); 4544 } 4545 4546 free_irq(adapter->pdev->irq, netdev); 4547 pci_disable_msi(adapter->pdev); 4548 4549 msi_test_failed: 4550 e1000e_set_interrupt_capability(adapter); 4551 return e1000_request_irq(adapter); 4552 } 4553 4554 /** 4555 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4556 * @adapter: board private struct 4557 * 4558 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4559 **/ 4560 static int e1000_test_msi(struct e1000_adapter *adapter) 4561 { 4562 int err; 4563 u16 pci_cmd; 4564 4565 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4566 return 0; 4567 4568 /* disable SERR in case the MSI write causes a master abort */ 4569 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4570 if (pci_cmd & PCI_COMMAND_SERR) 4571 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4572 pci_cmd & ~PCI_COMMAND_SERR); 4573 4574 err = e1000_test_msi_interrupt(adapter); 4575 4576 /* re-enable SERR */ 4577 if (pci_cmd & PCI_COMMAND_SERR) { 4578 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4579 pci_cmd |= PCI_COMMAND_SERR; 4580 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4581 } 4582 4583 return err; 4584 } 4585 4586 /** 4587 * e1000e_open - Called when a network interface is made active 4588 * @netdev: network interface device structure 4589 * 4590 * Returns 0 on success, negative value on failure 4591 * 4592 * The open entry point is called when a network interface is made 4593 * active by the system (IFF_UP). At this point all resources needed 4594 * for transmit and receive operations are allocated, the interrupt 4595 * handler is registered with the OS, the watchdog timer is started, 4596 * and the stack is notified that the interface is ready. 4597 **/ 4598 int e1000e_open(struct net_device *netdev) 4599 { 4600 struct e1000_adapter *adapter = netdev_priv(netdev); 4601 struct e1000_hw *hw = &adapter->hw; 4602 struct pci_dev *pdev = adapter->pdev; 4603 int err; 4604 4605 /* disallow open during test */ 4606 if (test_bit(__E1000_TESTING, &adapter->state)) 4607 return -EBUSY; 4608 4609 pm_runtime_get_sync(&pdev->dev); 4610 4611 netif_carrier_off(netdev); 4612 netif_stop_queue(netdev); 4613 4614 /* allocate transmit descriptors */ 4615 err = e1000e_setup_tx_resources(adapter->tx_ring); 4616 if (err) 4617 goto err_setup_tx; 4618 4619 /* allocate receive descriptors */ 4620 err = e1000e_setup_rx_resources(adapter->rx_ring); 4621 if (err) 4622 goto err_setup_rx; 4623 4624 /* If AMT is enabled, let the firmware know that the network 4625 * interface is now open and reset the part to a known state. 4626 */ 4627 if (adapter->flags & FLAG_HAS_AMT) { 4628 e1000e_get_hw_control(adapter); 4629 e1000e_reset(adapter); 4630 } 4631 4632 e1000e_power_up_phy(adapter); 4633 4634 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4635 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4636 e1000_update_mng_vlan(adapter); 4637 4638 /* DMA latency requirement to workaround jumbo issue */ 4639 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4640 PM_QOS_DEFAULT_VALUE); 4641 4642 /* before we allocate an interrupt, we must be ready to handle it. 4643 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4644 * as soon as we call pci_request_irq, so we have to setup our 4645 * clean_rx handler before we do so. 4646 */ 4647 e1000_configure(adapter); 4648 4649 err = e1000_request_irq(adapter); 4650 if (err) 4651 goto err_req_irq; 4652 4653 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4654 * ignore e1000e MSI messages, which means we need to test our MSI 4655 * interrupt now 4656 */ 4657 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4658 err = e1000_test_msi(adapter); 4659 if (err) { 4660 e_err("Interrupt allocation failed\n"); 4661 goto err_req_irq; 4662 } 4663 } 4664 4665 /* From here on the code is the same as e1000e_up() */ 4666 clear_bit(__E1000_DOWN, &adapter->state); 4667 4668 napi_enable(&adapter->napi); 4669 4670 e1000_irq_enable(adapter); 4671 4672 adapter->tx_hang_recheck = false; 4673 4674 hw->mac.get_link_status = true; 4675 pm_runtime_put(&pdev->dev); 4676 4677 e1000e_trigger_lsc(adapter); 4678 4679 return 0; 4680 4681 err_req_irq: 4682 pm_qos_remove_request(&adapter->pm_qos_req); 4683 e1000e_release_hw_control(adapter); 4684 e1000_power_down_phy(adapter); 4685 e1000e_free_rx_resources(adapter->rx_ring); 4686 err_setup_rx: 4687 e1000e_free_tx_resources(adapter->tx_ring); 4688 err_setup_tx: 4689 e1000e_reset(adapter); 4690 pm_runtime_put_sync(&pdev->dev); 4691 4692 return err; 4693 } 4694 4695 /** 4696 * e1000e_close - Disables a network interface 4697 * @netdev: network interface device structure 4698 * 4699 * Returns 0, this is not allowed to fail 4700 * 4701 * The close entry point is called when an interface is de-activated 4702 * by the OS. The hardware is still under the drivers control, but 4703 * needs to be disabled. A global MAC reset is issued to stop the 4704 * hardware, and all transmit and receive resources are freed. 4705 **/ 4706 int e1000e_close(struct net_device *netdev) 4707 { 4708 struct e1000_adapter *adapter = netdev_priv(netdev); 4709 struct pci_dev *pdev = adapter->pdev; 4710 int count = E1000_CHECK_RESET_COUNT; 4711 4712 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4713 usleep_range(10000, 11000); 4714 4715 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4716 4717 pm_runtime_get_sync(&pdev->dev); 4718 4719 if (netif_device_present(netdev)) { 4720 e1000e_down(adapter, true); 4721 e1000_free_irq(adapter); 4722 4723 /* Link status message must follow this format */ 4724 pr_info("%s NIC Link is Down\n", netdev->name); 4725 } 4726 4727 napi_disable(&adapter->napi); 4728 4729 e1000e_free_tx_resources(adapter->tx_ring); 4730 e1000e_free_rx_resources(adapter->rx_ring); 4731 4732 /* kill manageability vlan ID if supported, but not if a vlan with 4733 * the same ID is registered on the host OS (let 8021q kill it) 4734 */ 4735 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4736 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4737 adapter->mng_vlan_id); 4738 4739 /* If AMT is enabled, let the firmware know that the network 4740 * interface is now closed 4741 */ 4742 if ((adapter->flags & FLAG_HAS_AMT) && 4743 !test_bit(__E1000_TESTING, &adapter->state)) 4744 e1000e_release_hw_control(adapter); 4745 4746 pm_qos_remove_request(&adapter->pm_qos_req); 4747 4748 pm_runtime_put_sync(&pdev->dev); 4749 4750 return 0; 4751 } 4752 4753 /** 4754 * e1000_set_mac - Change the Ethernet Address of the NIC 4755 * @netdev: network interface device structure 4756 * @p: pointer to an address structure 4757 * 4758 * Returns 0 on success, negative on failure 4759 **/ 4760 static int e1000_set_mac(struct net_device *netdev, void *p) 4761 { 4762 struct e1000_adapter *adapter = netdev_priv(netdev); 4763 struct e1000_hw *hw = &adapter->hw; 4764 struct sockaddr *addr = p; 4765 4766 if (!is_valid_ether_addr(addr->sa_data)) 4767 return -EADDRNOTAVAIL; 4768 4769 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4770 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4771 4772 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4773 4774 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4775 /* activate the work around */ 4776 e1000e_set_laa_state_82571(&adapter->hw, 1); 4777 4778 /* Hold a copy of the LAA in RAR[14] This is done so that 4779 * between the time RAR[0] gets clobbered and the time it 4780 * gets fixed (in e1000_watchdog), the actual LAA is in one 4781 * of the RARs and no incoming packets directed to this port 4782 * are dropped. Eventually the LAA will be in RAR[0] and 4783 * RAR[14] 4784 */ 4785 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4786 adapter->hw.mac.rar_entry_count - 1); 4787 } 4788 4789 return 0; 4790 } 4791 4792 /** 4793 * e1000e_update_phy_task - work thread to update phy 4794 * @work: pointer to our work struct 4795 * 4796 * this worker thread exists because we must acquire a 4797 * semaphore to read the phy, which we could msleep while 4798 * waiting for it, and we can't msleep in a timer. 4799 **/ 4800 static void e1000e_update_phy_task(struct work_struct *work) 4801 { 4802 struct e1000_adapter *adapter = container_of(work, 4803 struct e1000_adapter, 4804 update_phy_task); 4805 struct e1000_hw *hw = &adapter->hw; 4806 4807 if (test_bit(__E1000_DOWN, &adapter->state)) 4808 return; 4809 4810 e1000_get_phy_info(hw); 4811 4812 /* Enable EEE on 82579 after link up */ 4813 if (hw->phy.type >= e1000_phy_82579) 4814 e1000_set_eee_pchlan(hw); 4815 } 4816 4817 /** 4818 * e1000_update_phy_info - timre call-back to update PHY info 4819 * @data: pointer to adapter cast into an unsigned long 4820 * 4821 * Need to wait a few seconds after link up to get diagnostic information from 4822 * the phy 4823 **/ 4824 static void e1000_update_phy_info(struct timer_list *t) 4825 { 4826 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4827 4828 if (test_bit(__E1000_DOWN, &adapter->state)) 4829 return; 4830 4831 schedule_work(&adapter->update_phy_task); 4832 } 4833 4834 /** 4835 * e1000e_update_phy_stats - Update the PHY statistics counters 4836 * @adapter: board private structure 4837 * 4838 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4839 **/ 4840 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4841 { 4842 struct e1000_hw *hw = &adapter->hw; 4843 s32 ret_val; 4844 u16 phy_data; 4845 4846 ret_val = hw->phy.ops.acquire(hw); 4847 if (ret_val) 4848 return; 4849 4850 /* A page set is expensive so check if already on desired page. 4851 * If not, set to the page with the PHY status registers. 4852 */ 4853 hw->phy.addr = 1; 4854 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4855 &phy_data); 4856 if (ret_val) 4857 goto release; 4858 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4859 ret_val = hw->phy.ops.set_page(hw, 4860 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4861 if (ret_val) 4862 goto release; 4863 } 4864 4865 /* Single Collision Count */ 4866 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4867 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4868 if (!ret_val) 4869 adapter->stats.scc += phy_data; 4870 4871 /* Excessive Collision Count */ 4872 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4873 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4874 if (!ret_val) 4875 adapter->stats.ecol += phy_data; 4876 4877 /* Multiple Collision Count */ 4878 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4879 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4880 if (!ret_val) 4881 adapter->stats.mcc += phy_data; 4882 4883 /* Late Collision Count */ 4884 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4885 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4886 if (!ret_val) 4887 adapter->stats.latecol += phy_data; 4888 4889 /* Collision Count - also used for adaptive IFS */ 4890 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4891 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4892 if (!ret_val) 4893 hw->mac.collision_delta = phy_data; 4894 4895 /* Defer Count */ 4896 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4897 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4898 if (!ret_val) 4899 adapter->stats.dc += phy_data; 4900 4901 /* Transmit with no CRS */ 4902 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4903 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4904 if (!ret_val) 4905 adapter->stats.tncrs += phy_data; 4906 4907 release: 4908 hw->phy.ops.release(hw); 4909 } 4910 4911 /** 4912 * e1000e_update_stats - Update the board statistics counters 4913 * @adapter: board private structure 4914 **/ 4915 static void e1000e_update_stats(struct e1000_adapter *adapter) 4916 { 4917 struct net_device *netdev = adapter->netdev; 4918 struct e1000_hw *hw = &adapter->hw; 4919 struct pci_dev *pdev = adapter->pdev; 4920 4921 /* Prevent stats update while adapter is being reset, or if the pci 4922 * connection is down. 4923 */ 4924 if (adapter->link_speed == 0) 4925 return; 4926 if (pci_channel_offline(pdev)) 4927 return; 4928 4929 adapter->stats.crcerrs += er32(CRCERRS); 4930 adapter->stats.gprc += er32(GPRC); 4931 adapter->stats.gorc += er32(GORCL); 4932 er32(GORCH); /* Clear gorc */ 4933 adapter->stats.bprc += er32(BPRC); 4934 adapter->stats.mprc += er32(MPRC); 4935 adapter->stats.roc += er32(ROC); 4936 4937 adapter->stats.mpc += er32(MPC); 4938 4939 /* Half-duplex statistics */ 4940 if (adapter->link_duplex == HALF_DUPLEX) { 4941 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4942 e1000e_update_phy_stats(adapter); 4943 } else { 4944 adapter->stats.scc += er32(SCC); 4945 adapter->stats.ecol += er32(ECOL); 4946 adapter->stats.mcc += er32(MCC); 4947 adapter->stats.latecol += er32(LATECOL); 4948 adapter->stats.dc += er32(DC); 4949 4950 hw->mac.collision_delta = er32(COLC); 4951 4952 if ((hw->mac.type != e1000_82574) && 4953 (hw->mac.type != e1000_82583)) 4954 adapter->stats.tncrs += er32(TNCRS); 4955 } 4956 adapter->stats.colc += hw->mac.collision_delta; 4957 } 4958 4959 adapter->stats.xonrxc += er32(XONRXC); 4960 adapter->stats.xontxc += er32(XONTXC); 4961 adapter->stats.xoffrxc += er32(XOFFRXC); 4962 adapter->stats.xofftxc += er32(XOFFTXC); 4963 adapter->stats.gptc += er32(GPTC); 4964 adapter->stats.gotc += er32(GOTCL); 4965 er32(GOTCH); /* Clear gotc */ 4966 adapter->stats.rnbc += er32(RNBC); 4967 adapter->stats.ruc += er32(RUC); 4968 4969 adapter->stats.mptc += er32(MPTC); 4970 adapter->stats.bptc += er32(BPTC); 4971 4972 /* used for adaptive IFS */ 4973 4974 hw->mac.tx_packet_delta = er32(TPT); 4975 adapter->stats.tpt += hw->mac.tx_packet_delta; 4976 4977 adapter->stats.algnerrc += er32(ALGNERRC); 4978 adapter->stats.rxerrc += er32(RXERRC); 4979 adapter->stats.cexterr += er32(CEXTERR); 4980 adapter->stats.tsctc += er32(TSCTC); 4981 adapter->stats.tsctfc += er32(TSCTFC); 4982 4983 /* Fill out the OS statistics structure */ 4984 netdev->stats.multicast = adapter->stats.mprc; 4985 netdev->stats.collisions = adapter->stats.colc; 4986 4987 /* Rx Errors */ 4988 4989 /* RLEC on some newer hardware can be incorrect so build 4990 * our own version based on RUC and ROC 4991 */ 4992 netdev->stats.rx_errors = adapter->stats.rxerrc + 4993 adapter->stats.crcerrs + adapter->stats.algnerrc + 4994 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4995 netdev->stats.rx_length_errors = adapter->stats.ruc + 4996 adapter->stats.roc; 4997 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 4998 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 4999 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5000 5001 /* Tx Errors */ 5002 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5003 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5004 netdev->stats.tx_window_errors = adapter->stats.latecol; 5005 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5006 5007 /* Tx Dropped needs to be maintained elsewhere */ 5008 5009 /* Management Stats */ 5010 adapter->stats.mgptc += er32(MGTPTC); 5011 adapter->stats.mgprc += er32(MGTPRC); 5012 adapter->stats.mgpdc += er32(MGTPDC); 5013 5014 /* Correctable ECC Errors */ 5015 if (hw->mac.type >= e1000_pch_lpt) { 5016 u32 pbeccsts = er32(PBECCSTS); 5017 5018 adapter->corr_errors += 5019 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5020 adapter->uncorr_errors += 5021 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5022 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5023 } 5024 } 5025 5026 /** 5027 * e1000_phy_read_status - Update the PHY register status snapshot 5028 * @adapter: board private structure 5029 **/ 5030 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5031 { 5032 struct e1000_hw *hw = &adapter->hw; 5033 struct e1000_phy_regs *phy = &adapter->phy_regs; 5034 5035 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5036 (er32(STATUS) & E1000_STATUS_LU) && 5037 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5038 int ret_val; 5039 5040 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5041 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5042 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5043 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5044 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5045 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5046 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5047 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5048 if (ret_val) 5049 e_warn("Error reading PHY register\n"); 5050 } else { 5051 /* Do not read PHY registers if link is not up 5052 * Set values to typical power-on defaults 5053 */ 5054 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5055 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5056 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5057 BMSR_ERCAP); 5058 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5059 ADVERTISE_ALL | ADVERTISE_CSMA); 5060 phy->lpa = 0; 5061 phy->expansion = EXPANSION_ENABLENPAGE; 5062 phy->ctrl1000 = ADVERTISE_1000FULL; 5063 phy->stat1000 = 0; 5064 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5065 } 5066 } 5067 5068 static void e1000_print_link_info(struct e1000_adapter *adapter) 5069 { 5070 struct e1000_hw *hw = &adapter->hw; 5071 u32 ctrl = er32(CTRL); 5072 5073 /* Link status message must follow this format for user tools */ 5074 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5075 adapter->netdev->name, adapter->link_speed, 5076 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5077 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5078 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5079 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5080 } 5081 5082 static bool e1000e_has_link(struct e1000_adapter *adapter) 5083 { 5084 struct e1000_hw *hw = &adapter->hw; 5085 bool link_active = false; 5086 s32 ret_val = 0; 5087 5088 /* get_link_status is set on LSC (link status) interrupt or 5089 * Rx sequence error interrupt. get_link_status will stay 5090 * true until the check_for_link establishes link 5091 * for copper adapters ONLY 5092 */ 5093 switch (hw->phy.media_type) { 5094 case e1000_media_type_copper: 5095 if (hw->mac.get_link_status) { 5096 ret_val = hw->mac.ops.check_for_link(hw); 5097 link_active = !hw->mac.get_link_status; 5098 } else { 5099 link_active = true; 5100 } 5101 break; 5102 case e1000_media_type_fiber: 5103 ret_val = hw->mac.ops.check_for_link(hw); 5104 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5105 break; 5106 case e1000_media_type_internal_serdes: 5107 ret_val = hw->mac.ops.check_for_link(hw); 5108 link_active = hw->mac.serdes_has_link; 5109 break; 5110 default: 5111 case e1000_media_type_unknown: 5112 break; 5113 } 5114 5115 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5116 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5117 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5118 e_info("Gigabit has been disabled, downgrading speed\n"); 5119 } 5120 5121 return link_active; 5122 } 5123 5124 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5125 { 5126 /* make sure the receive unit is started */ 5127 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5128 (adapter->flags & FLAG_RESTART_NOW)) { 5129 struct e1000_hw *hw = &adapter->hw; 5130 u32 rctl = er32(RCTL); 5131 5132 ew32(RCTL, rctl | E1000_RCTL_EN); 5133 adapter->flags &= ~FLAG_RESTART_NOW; 5134 } 5135 } 5136 5137 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5138 { 5139 struct e1000_hw *hw = &adapter->hw; 5140 5141 /* With 82574 controllers, PHY needs to be checked periodically 5142 * for hung state and reset, if two calls return true 5143 */ 5144 if (e1000_check_phy_82574(hw)) 5145 adapter->phy_hang_count++; 5146 else 5147 adapter->phy_hang_count = 0; 5148 5149 if (adapter->phy_hang_count > 1) { 5150 adapter->phy_hang_count = 0; 5151 e_dbg("PHY appears hung - resetting\n"); 5152 schedule_work(&adapter->reset_task); 5153 } 5154 } 5155 5156 /** 5157 * e1000_watchdog - Timer Call-back 5158 * @data: pointer to adapter cast into an unsigned long 5159 **/ 5160 static void e1000_watchdog(struct timer_list *t) 5161 { 5162 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5163 5164 /* Do the rest outside of interrupt context */ 5165 schedule_work(&adapter->watchdog_task); 5166 5167 /* TODO: make this use queue_delayed_work() */ 5168 } 5169 5170 static void e1000_watchdog_task(struct work_struct *work) 5171 { 5172 struct e1000_adapter *adapter = container_of(work, 5173 struct e1000_adapter, 5174 watchdog_task); 5175 struct net_device *netdev = adapter->netdev; 5176 struct e1000_mac_info *mac = &adapter->hw.mac; 5177 struct e1000_phy_info *phy = &adapter->hw.phy; 5178 struct e1000_ring *tx_ring = adapter->tx_ring; 5179 u32 dmoff_exit_timeout = 100, tries = 0; 5180 struct e1000_hw *hw = &adapter->hw; 5181 u32 link, tctl, pcim_state; 5182 5183 if (test_bit(__E1000_DOWN, &adapter->state)) 5184 return; 5185 5186 link = e1000e_has_link(adapter); 5187 if ((netif_carrier_ok(netdev)) && link) { 5188 /* Cancel scheduled suspend requests. */ 5189 pm_runtime_resume(netdev->dev.parent); 5190 5191 e1000e_enable_receives(adapter); 5192 goto link_up; 5193 } 5194 5195 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5196 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5197 e1000_update_mng_vlan(adapter); 5198 5199 if (link) { 5200 if (!netif_carrier_ok(netdev)) { 5201 bool txb2b = true; 5202 5203 /* Cancel scheduled suspend requests. */ 5204 pm_runtime_resume(netdev->dev.parent); 5205 5206 /* Checking if MAC is in DMoff state*/ 5207 pcim_state = er32(STATUS); 5208 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5209 if (tries++ == dmoff_exit_timeout) { 5210 e_dbg("Error in exiting dmoff\n"); 5211 break; 5212 } 5213 usleep_range(10000, 20000); 5214 pcim_state = er32(STATUS); 5215 5216 /* Checking if MAC exited DMoff state */ 5217 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5218 e1000_phy_hw_reset(&adapter->hw); 5219 } 5220 5221 /* update snapshot of PHY registers on LSC */ 5222 e1000_phy_read_status(adapter); 5223 mac->ops.get_link_up_info(&adapter->hw, 5224 &adapter->link_speed, 5225 &adapter->link_duplex); 5226 e1000_print_link_info(adapter); 5227 5228 /* check if SmartSpeed worked */ 5229 e1000e_check_downshift(hw); 5230 if (phy->speed_downgraded) 5231 netdev_warn(netdev, 5232 "Link Speed was downgraded by SmartSpeed\n"); 5233 5234 /* On supported PHYs, check for duplex mismatch only 5235 * if link has autonegotiated at 10/100 half 5236 */ 5237 if ((hw->phy.type == e1000_phy_igp_3 || 5238 hw->phy.type == e1000_phy_bm) && 5239 hw->mac.autoneg && 5240 (adapter->link_speed == SPEED_10 || 5241 adapter->link_speed == SPEED_100) && 5242 (adapter->link_duplex == HALF_DUPLEX)) { 5243 u16 autoneg_exp; 5244 5245 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5246 5247 if (!(autoneg_exp & EXPANSION_NWAY)) 5248 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5249 } 5250 5251 /* adjust timeout factor according to speed/duplex */ 5252 adapter->tx_timeout_factor = 1; 5253 switch (adapter->link_speed) { 5254 case SPEED_10: 5255 txb2b = false; 5256 adapter->tx_timeout_factor = 16; 5257 break; 5258 case SPEED_100: 5259 txb2b = false; 5260 adapter->tx_timeout_factor = 10; 5261 break; 5262 } 5263 5264 /* workaround: re-program speed mode bit after 5265 * link-up event 5266 */ 5267 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5268 !txb2b) { 5269 u32 tarc0; 5270 5271 tarc0 = er32(TARC(0)); 5272 tarc0 &= ~SPEED_MODE_BIT; 5273 ew32(TARC(0), tarc0); 5274 } 5275 5276 /* disable TSO for pcie and 10/100 speeds, to avoid 5277 * some hardware issues 5278 */ 5279 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5280 switch (adapter->link_speed) { 5281 case SPEED_10: 5282 case SPEED_100: 5283 e_info("10/100 speed: disabling TSO\n"); 5284 netdev->features &= ~NETIF_F_TSO; 5285 netdev->features &= ~NETIF_F_TSO6; 5286 break; 5287 case SPEED_1000: 5288 netdev->features |= NETIF_F_TSO; 5289 netdev->features |= NETIF_F_TSO6; 5290 break; 5291 default: 5292 /* oops */ 5293 break; 5294 } 5295 } 5296 5297 /* enable transmits in the hardware, need to do this 5298 * after setting TARC(0) 5299 */ 5300 tctl = er32(TCTL); 5301 tctl |= E1000_TCTL_EN; 5302 ew32(TCTL, tctl); 5303 5304 /* Perform any post-link-up configuration before 5305 * reporting link up. 5306 */ 5307 if (phy->ops.cfg_on_link_up) 5308 phy->ops.cfg_on_link_up(hw); 5309 5310 netif_wake_queue(netdev); 5311 netif_carrier_on(netdev); 5312 5313 if (!test_bit(__E1000_DOWN, &adapter->state)) 5314 mod_timer(&adapter->phy_info_timer, 5315 round_jiffies(jiffies + 2 * HZ)); 5316 } 5317 } else { 5318 if (netif_carrier_ok(netdev)) { 5319 adapter->link_speed = 0; 5320 adapter->link_duplex = 0; 5321 /* Link status message must follow this format */ 5322 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 5323 netif_carrier_off(netdev); 5324 netif_stop_queue(netdev); 5325 if (!test_bit(__E1000_DOWN, &adapter->state)) 5326 mod_timer(&adapter->phy_info_timer, 5327 round_jiffies(jiffies + 2 * HZ)); 5328 5329 /* 8000ES2LAN requires a Rx packet buffer work-around 5330 * on link down event; reset the controller to flush 5331 * the Rx packet buffer. 5332 */ 5333 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5334 adapter->flags |= FLAG_RESTART_NOW; 5335 else 5336 pm_schedule_suspend(netdev->dev.parent, 5337 LINK_TIMEOUT); 5338 } 5339 } 5340 5341 link_up: 5342 spin_lock(&adapter->stats64_lock); 5343 e1000e_update_stats(adapter); 5344 5345 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5346 adapter->tpt_old = adapter->stats.tpt; 5347 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5348 adapter->colc_old = adapter->stats.colc; 5349 5350 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5351 adapter->gorc_old = adapter->stats.gorc; 5352 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5353 adapter->gotc_old = adapter->stats.gotc; 5354 spin_unlock(&adapter->stats64_lock); 5355 5356 /* If the link is lost the controller stops DMA, but 5357 * if there is queued Tx work it cannot be done. So 5358 * reset the controller to flush the Tx packet buffers. 5359 */ 5360 if (!netif_carrier_ok(netdev) && 5361 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5362 adapter->flags |= FLAG_RESTART_NOW; 5363 5364 /* If reset is necessary, do it outside of interrupt context. */ 5365 if (adapter->flags & FLAG_RESTART_NOW) { 5366 schedule_work(&adapter->reset_task); 5367 /* return immediately since reset is imminent */ 5368 return; 5369 } 5370 5371 e1000e_update_adaptive(&adapter->hw); 5372 5373 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5374 if (adapter->itr_setting == 4) { 5375 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5376 * Total asymmetrical Tx or Rx gets ITR=8000; 5377 * everyone else is between 2000-8000. 5378 */ 5379 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5380 u32 dif = (adapter->gotc > adapter->gorc ? 5381 adapter->gotc - adapter->gorc : 5382 adapter->gorc - adapter->gotc) / 10000; 5383 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5384 5385 e1000e_write_itr(adapter, itr); 5386 } 5387 5388 /* Cause software interrupt to ensure Rx ring is cleaned */ 5389 if (adapter->msix_entries) 5390 ew32(ICS, adapter->rx_ring->ims_val); 5391 else 5392 ew32(ICS, E1000_ICS_RXDMT0); 5393 5394 /* flush pending descriptors to memory before detecting Tx hang */ 5395 e1000e_flush_descriptors(adapter); 5396 5397 /* Force detection of hung controller every watchdog period */ 5398 adapter->detect_tx_hung = true; 5399 5400 /* With 82571 controllers, LAA may be overwritten due to controller 5401 * reset from the other port. Set the appropriate LAA in RAR[0] 5402 */ 5403 if (e1000e_get_laa_state_82571(hw)) 5404 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5405 5406 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5407 e1000e_check_82574_phy_workaround(adapter); 5408 5409 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5410 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5411 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5412 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5413 er32(RXSTMPH); 5414 adapter->rx_hwtstamp_cleared++; 5415 } else { 5416 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5417 } 5418 } 5419 5420 /* Reset the timer */ 5421 if (!test_bit(__E1000_DOWN, &adapter->state)) 5422 mod_timer(&adapter->watchdog_timer, 5423 round_jiffies(jiffies + 2 * HZ)); 5424 } 5425 5426 #define E1000_TX_FLAGS_CSUM 0x00000001 5427 #define E1000_TX_FLAGS_VLAN 0x00000002 5428 #define E1000_TX_FLAGS_TSO 0x00000004 5429 #define E1000_TX_FLAGS_IPV4 0x00000008 5430 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5431 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5432 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5433 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5434 5435 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5436 __be16 protocol) 5437 { 5438 struct e1000_context_desc *context_desc; 5439 struct e1000_buffer *buffer_info; 5440 unsigned int i; 5441 u32 cmd_length = 0; 5442 u16 ipcse = 0, mss; 5443 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5444 int err; 5445 5446 if (!skb_is_gso(skb)) 5447 return 0; 5448 5449 err = skb_cow_head(skb, 0); 5450 if (err < 0) 5451 return err; 5452 5453 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5454 mss = skb_shinfo(skb)->gso_size; 5455 if (protocol == htons(ETH_P_IP)) { 5456 struct iphdr *iph = ip_hdr(skb); 5457 iph->tot_len = 0; 5458 iph->check = 0; 5459 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5460 0, IPPROTO_TCP, 0); 5461 cmd_length = E1000_TXD_CMD_IP; 5462 ipcse = skb_transport_offset(skb) - 1; 5463 } else if (skb_is_gso_v6(skb)) { 5464 ipv6_hdr(skb)->payload_len = 0; 5465 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5466 &ipv6_hdr(skb)->daddr, 5467 0, IPPROTO_TCP, 0); 5468 ipcse = 0; 5469 } 5470 ipcss = skb_network_offset(skb); 5471 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5472 tucss = skb_transport_offset(skb); 5473 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5474 5475 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5476 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5477 5478 i = tx_ring->next_to_use; 5479 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5480 buffer_info = &tx_ring->buffer_info[i]; 5481 5482 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5483 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5484 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5485 context_desc->upper_setup.tcp_fields.tucss = tucss; 5486 context_desc->upper_setup.tcp_fields.tucso = tucso; 5487 context_desc->upper_setup.tcp_fields.tucse = 0; 5488 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5489 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5490 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5491 5492 buffer_info->time_stamp = jiffies; 5493 buffer_info->next_to_watch = i; 5494 5495 i++; 5496 if (i == tx_ring->count) 5497 i = 0; 5498 tx_ring->next_to_use = i; 5499 5500 return 1; 5501 } 5502 5503 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5504 __be16 protocol) 5505 { 5506 struct e1000_adapter *adapter = tx_ring->adapter; 5507 struct e1000_context_desc *context_desc; 5508 struct e1000_buffer *buffer_info; 5509 unsigned int i; 5510 u8 css; 5511 u32 cmd_len = E1000_TXD_CMD_DEXT; 5512 5513 if (skb->ip_summed != CHECKSUM_PARTIAL) 5514 return false; 5515 5516 switch (protocol) { 5517 case cpu_to_be16(ETH_P_IP): 5518 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5519 cmd_len |= E1000_TXD_CMD_TCP; 5520 break; 5521 case cpu_to_be16(ETH_P_IPV6): 5522 /* XXX not handling all IPV6 headers */ 5523 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5524 cmd_len |= E1000_TXD_CMD_TCP; 5525 break; 5526 default: 5527 if (unlikely(net_ratelimit())) 5528 e_warn("checksum_partial proto=%x!\n", 5529 be16_to_cpu(protocol)); 5530 break; 5531 } 5532 5533 css = skb_checksum_start_offset(skb); 5534 5535 i = tx_ring->next_to_use; 5536 buffer_info = &tx_ring->buffer_info[i]; 5537 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5538 5539 context_desc->lower_setup.ip_config = 0; 5540 context_desc->upper_setup.tcp_fields.tucss = css; 5541 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5542 context_desc->upper_setup.tcp_fields.tucse = 0; 5543 context_desc->tcp_seg_setup.data = 0; 5544 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5545 5546 buffer_info->time_stamp = jiffies; 5547 buffer_info->next_to_watch = i; 5548 5549 i++; 5550 if (i == tx_ring->count) 5551 i = 0; 5552 tx_ring->next_to_use = i; 5553 5554 return true; 5555 } 5556 5557 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5558 unsigned int first, unsigned int max_per_txd, 5559 unsigned int nr_frags) 5560 { 5561 struct e1000_adapter *adapter = tx_ring->adapter; 5562 struct pci_dev *pdev = adapter->pdev; 5563 struct e1000_buffer *buffer_info; 5564 unsigned int len = skb_headlen(skb); 5565 unsigned int offset = 0, size, count = 0, i; 5566 unsigned int f, bytecount, segs; 5567 5568 i = tx_ring->next_to_use; 5569 5570 while (len) { 5571 buffer_info = &tx_ring->buffer_info[i]; 5572 size = min(len, max_per_txd); 5573 5574 buffer_info->length = size; 5575 buffer_info->time_stamp = jiffies; 5576 buffer_info->next_to_watch = i; 5577 buffer_info->dma = dma_map_single(&pdev->dev, 5578 skb->data + offset, 5579 size, DMA_TO_DEVICE); 5580 buffer_info->mapped_as_page = false; 5581 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5582 goto dma_error; 5583 5584 len -= size; 5585 offset += size; 5586 count++; 5587 5588 if (len) { 5589 i++; 5590 if (i == tx_ring->count) 5591 i = 0; 5592 } 5593 } 5594 5595 for (f = 0; f < nr_frags; f++) { 5596 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5597 5598 len = skb_frag_size(frag); 5599 offset = 0; 5600 5601 while (len) { 5602 i++; 5603 if (i == tx_ring->count) 5604 i = 0; 5605 5606 buffer_info = &tx_ring->buffer_info[i]; 5607 size = min(len, max_per_txd); 5608 5609 buffer_info->length = size; 5610 buffer_info->time_stamp = jiffies; 5611 buffer_info->next_to_watch = i; 5612 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5613 offset, size, 5614 DMA_TO_DEVICE); 5615 buffer_info->mapped_as_page = true; 5616 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5617 goto dma_error; 5618 5619 len -= size; 5620 offset += size; 5621 count++; 5622 } 5623 } 5624 5625 segs = skb_shinfo(skb)->gso_segs ? : 1; 5626 /* multiply data chunks by size of headers */ 5627 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5628 5629 tx_ring->buffer_info[i].skb = skb; 5630 tx_ring->buffer_info[i].segs = segs; 5631 tx_ring->buffer_info[i].bytecount = bytecount; 5632 tx_ring->buffer_info[first].next_to_watch = i; 5633 5634 return count; 5635 5636 dma_error: 5637 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5638 buffer_info->dma = 0; 5639 if (count) 5640 count--; 5641 5642 while (count--) { 5643 if (i == 0) 5644 i += tx_ring->count; 5645 i--; 5646 buffer_info = &tx_ring->buffer_info[i]; 5647 e1000_put_txbuf(tx_ring, buffer_info, true); 5648 } 5649 5650 return 0; 5651 } 5652 5653 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5654 { 5655 struct e1000_adapter *adapter = tx_ring->adapter; 5656 struct e1000_tx_desc *tx_desc = NULL; 5657 struct e1000_buffer *buffer_info; 5658 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5659 unsigned int i; 5660 5661 if (tx_flags & E1000_TX_FLAGS_TSO) { 5662 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5663 E1000_TXD_CMD_TSE; 5664 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5665 5666 if (tx_flags & E1000_TX_FLAGS_IPV4) 5667 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5668 } 5669 5670 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5671 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5672 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5673 } 5674 5675 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5676 txd_lower |= E1000_TXD_CMD_VLE; 5677 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5678 } 5679 5680 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5681 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5682 5683 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5684 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5685 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5686 } 5687 5688 i = tx_ring->next_to_use; 5689 5690 do { 5691 buffer_info = &tx_ring->buffer_info[i]; 5692 tx_desc = E1000_TX_DESC(*tx_ring, i); 5693 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5694 tx_desc->lower.data = cpu_to_le32(txd_lower | 5695 buffer_info->length); 5696 tx_desc->upper.data = cpu_to_le32(txd_upper); 5697 5698 i++; 5699 if (i == tx_ring->count) 5700 i = 0; 5701 } while (--count > 0); 5702 5703 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5704 5705 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5706 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5707 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5708 5709 /* Force memory writes to complete before letting h/w 5710 * know there are new descriptors to fetch. (Only 5711 * applicable for weak-ordered memory model archs, 5712 * such as IA-64). 5713 */ 5714 wmb(); 5715 5716 tx_ring->next_to_use = i; 5717 } 5718 5719 #define MINIMUM_DHCP_PACKET_SIZE 282 5720 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5721 struct sk_buff *skb) 5722 { 5723 struct e1000_hw *hw = &adapter->hw; 5724 u16 length, offset; 5725 5726 if (skb_vlan_tag_present(skb) && 5727 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5728 (adapter->hw.mng_cookie.status & 5729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5730 return 0; 5731 5732 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5733 return 0; 5734 5735 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5736 return 0; 5737 5738 { 5739 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5740 struct udphdr *udp; 5741 5742 if (ip->protocol != IPPROTO_UDP) 5743 return 0; 5744 5745 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5746 if (ntohs(udp->dest) != 67) 5747 return 0; 5748 5749 offset = (u8 *)udp + 8 - skb->data; 5750 length = skb->len - offset; 5751 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5752 } 5753 5754 return 0; 5755 } 5756 5757 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5758 { 5759 struct e1000_adapter *adapter = tx_ring->adapter; 5760 5761 netif_stop_queue(adapter->netdev); 5762 /* Herbert's original patch had: 5763 * smp_mb__after_netif_stop_queue(); 5764 * but since that doesn't exist yet, just open code it. 5765 */ 5766 smp_mb(); 5767 5768 /* We need to check again in a case another CPU has just 5769 * made room available. 5770 */ 5771 if (e1000_desc_unused(tx_ring) < size) 5772 return -EBUSY; 5773 5774 /* A reprieve! */ 5775 netif_start_queue(adapter->netdev); 5776 ++adapter->restart_queue; 5777 return 0; 5778 } 5779 5780 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5781 { 5782 BUG_ON(size > tx_ring->count); 5783 5784 if (e1000_desc_unused(tx_ring) >= size) 5785 return 0; 5786 return __e1000_maybe_stop_tx(tx_ring, size); 5787 } 5788 5789 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5790 struct net_device *netdev) 5791 { 5792 struct e1000_adapter *adapter = netdev_priv(netdev); 5793 struct e1000_ring *tx_ring = adapter->tx_ring; 5794 unsigned int first; 5795 unsigned int tx_flags = 0; 5796 unsigned int len = skb_headlen(skb); 5797 unsigned int nr_frags; 5798 unsigned int mss; 5799 int count = 0; 5800 int tso; 5801 unsigned int f; 5802 __be16 protocol = vlan_get_protocol(skb); 5803 5804 if (test_bit(__E1000_DOWN, &adapter->state)) { 5805 dev_kfree_skb_any(skb); 5806 return NETDEV_TX_OK; 5807 } 5808 5809 if (skb->len <= 0) { 5810 dev_kfree_skb_any(skb); 5811 return NETDEV_TX_OK; 5812 } 5813 5814 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5815 * pad skb in order to meet this minimum size requirement 5816 */ 5817 if (skb_put_padto(skb, 17)) 5818 return NETDEV_TX_OK; 5819 5820 mss = skb_shinfo(skb)->gso_size; 5821 if (mss) { 5822 u8 hdr_len; 5823 5824 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5825 * points to just header, pull a few bytes of payload from 5826 * frags into skb->data 5827 */ 5828 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5829 /* we do this workaround for ES2LAN, but it is un-necessary, 5830 * avoiding it could save a lot of cycles 5831 */ 5832 if (skb->data_len && (hdr_len == len)) { 5833 unsigned int pull_size; 5834 5835 pull_size = min_t(unsigned int, 4, skb->data_len); 5836 if (!__pskb_pull_tail(skb, pull_size)) { 5837 e_err("__pskb_pull_tail failed.\n"); 5838 dev_kfree_skb_any(skb); 5839 return NETDEV_TX_OK; 5840 } 5841 len = skb_headlen(skb); 5842 } 5843 } 5844 5845 /* reserve a descriptor for the offload context */ 5846 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5847 count++; 5848 count++; 5849 5850 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5851 5852 nr_frags = skb_shinfo(skb)->nr_frags; 5853 for (f = 0; f < nr_frags; f++) 5854 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5855 adapter->tx_fifo_limit); 5856 5857 if (adapter->hw.mac.tx_pkt_filtering) 5858 e1000_transfer_dhcp_info(adapter, skb); 5859 5860 /* need: count + 2 desc gap to keep tail from touching 5861 * head, otherwise try next time 5862 */ 5863 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5864 return NETDEV_TX_BUSY; 5865 5866 if (skb_vlan_tag_present(skb)) { 5867 tx_flags |= E1000_TX_FLAGS_VLAN; 5868 tx_flags |= (skb_vlan_tag_get(skb) << 5869 E1000_TX_FLAGS_VLAN_SHIFT); 5870 } 5871 5872 first = tx_ring->next_to_use; 5873 5874 tso = e1000_tso(tx_ring, skb, protocol); 5875 if (tso < 0) { 5876 dev_kfree_skb_any(skb); 5877 return NETDEV_TX_OK; 5878 } 5879 5880 if (tso) 5881 tx_flags |= E1000_TX_FLAGS_TSO; 5882 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5883 tx_flags |= E1000_TX_FLAGS_CSUM; 5884 5885 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5886 * 82571 hardware supports TSO capabilities for IPv6 as well... 5887 * no longer assume, we must. 5888 */ 5889 if (protocol == htons(ETH_P_IP)) 5890 tx_flags |= E1000_TX_FLAGS_IPV4; 5891 5892 if (unlikely(skb->no_fcs)) 5893 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5894 5895 /* if count is 0 then mapping error has occurred */ 5896 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5897 nr_frags); 5898 if (count) { 5899 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5900 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5901 if (!adapter->tx_hwtstamp_skb) { 5902 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5903 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5904 adapter->tx_hwtstamp_skb = skb_get(skb); 5905 adapter->tx_hwtstamp_start = jiffies; 5906 schedule_work(&adapter->tx_hwtstamp_work); 5907 } else { 5908 adapter->tx_hwtstamp_skipped++; 5909 } 5910 } 5911 5912 skb_tx_timestamp(skb); 5913 5914 netdev_sent_queue(netdev, skb->len); 5915 e1000_tx_queue(tx_ring, tx_flags, count); 5916 /* Make sure there is space in the ring for the next send. */ 5917 e1000_maybe_stop_tx(tx_ring, 5918 (MAX_SKB_FRAGS * 5919 DIV_ROUND_UP(PAGE_SIZE, 5920 adapter->tx_fifo_limit) + 2)); 5921 5922 if (!netdev_xmit_more() || 5923 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5924 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5925 e1000e_update_tdt_wa(tx_ring, 5926 tx_ring->next_to_use); 5927 else 5928 writel(tx_ring->next_to_use, tx_ring->tail); 5929 } 5930 } else { 5931 dev_kfree_skb_any(skb); 5932 tx_ring->buffer_info[first].time_stamp = 0; 5933 tx_ring->next_to_use = first; 5934 } 5935 5936 return NETDEV_TX_OK; 5937 } 5938 5939 /** 5940 * e1000_tx_timeout - Respond to a Tx Hang 5941 * @netdev: network interface device structure 5942 **/ 5943 static void e1000_tx_timeout(struct net_device *netdev) 5944 { 5945 struct e1000_adapter *adapter = netdev_priv(netdev); 5946 5947 /* Do the reset outside of interrupt context */ 5948 adapter->tx_timeout_count++; 5949 schedule_work(&adapter->reset_task); 5950 } 5951 5952 static void e1000_reset_task(struct work_struct *work) 5953 { 5954 struct e1000_adapter *adapter; 5955 adapter = container_of(work, struct e1000_adapter, reset_task); 5956 5957 /* don't run the task if already down */ 5958 if (test_bit(__E1000_DOWN, &adapter->state)) 5959 return; 5960 5961 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5962 e1000e_dump(adapter); 5963 e_err("Reset adapter unexpectedly\n"); 5964 } 5965 e1000e_reinit_locked(adapter); 5966 } 5967 5968 /** 5969 * e1000_get_stats64 - Get System Network Statistics 5970 * @netdev: network interface device structure 5971 * @stats: rtnl_link_stats64 pointer 5972 * 5973 * Returns the address of the device statistics structure. 5974 **/ 5975 void e1000e_get_stats64(struct net_device *netdev, 5976 struct rtnl_link_stats64 *stats) 5977 { 5978 struct e1000_adapter *adapter = netdev_priv(netdev); 5979 5980 spin_lock(&adapter->stats64_lock); 5981 e1000e_update_stats(adapter); 5982 /* Fill out the OS statistics structure */ 5983 stats->rx_bytes = adapter->stats.gorc; 5984 stats->rx_packets = adapter->stats.gprc; 5985 stats->tx_bytes = adapter->stats.gotc; 5986 stats->tx_packets = adapter->stats.gptc; 5987 stats->multicast = adapter->stats.mprc; 5988 stats->collisions = adapter->stats.colc; 5989 5990 /* Rx Errors */ 5991 5992 /* RLEC on some newer hardware can be incorrect so build 5993 * our own version based on RUC and ROC 5994 */ 5995 stats->rx_errors = adapter->stats.rxerrc + 5996 adapter->stats.crcerrs + adapter->stats.algnerrc + 5997 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5998 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5999 stats->rx_crc_errors = adapter->stats.crcerrs; 6000 stats->rx_frame_errors = adapter->stats.algnerrc; 6001 stats->rx_missed_errors = adapter->stats.mpc; 6002 6003 /* Tx Errors */ 6004 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6005 stats->tx_aborted_errors = adapter->stats.ecol; 6006 stats->tx_window_errors = adapter->stats.latecol; 6007 stats->tx_carrier_errors = adapter->stats.tncrs; 6008 6009 /* Tx Dropped needs to be maintained elsewhere */ 6010 6011 spin_unlock(&adapter->stats64_lock); 6012 } 6013 6014 /** 6015 * e1000_change_mtu - Change the Maximum Transfer Unit 6016 * @netdev: network interface device structure 6017 * @new_mtu: new value for maximum frame size 6018 * 6019 * Returns 0 on success, negative on failure 6020 **/ 6021 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6022 { 6023 struct e1000_adapter *adapter = netdev_priv(netdev); 6024 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6025 6026 /* Jumbo frame support */ 6027 if ((new_mtu > ETH_DATA_LEN) && 6028 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6029 e_err("Jumbo Frames not supported.\n"); 6030 return -EINVAL; 6031 } 6032 6033 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6034 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6035 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6036 (new_mtu > ETH_DATA_LEN)) { 6037 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6038 return -EINVAL; 6039 } 6040 6041 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6042 usleep_range(1000, 1100); 6043 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6044 adapter->max_frame_size = max_frame; 6045 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6046 netdev->mtu, new_mtu); 6047 netdev->mtu = new_mtu; 6048 6049 pm_runtime_get_sync(netdev->dev.parent); 6050 6051 if (netif_running(netdev)) 6052 e1000e_down(adapter, true); 6053 6054 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6055 * means we reserve 2 more, this pushes us to allocate from the next 6056 * larger slab size. 6057 * i.e. RXBUFFER_2048 --> size-4096 slab 6058 * However with the new *_jumbo_rx* routines, jumbo receives will use 6059 * fragmented skbs 6060 */ 6061 6062 if (max_frame <= 2048) 6063 adapter->rx_buffer_len = 2048; 6064 else 6065 adapter->rx_buffer_len = 4096; 6066 6067 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6068 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6069 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6070 6071 if (netif_running(netdev)) 6072 e1000e_up(adapter); 6073 else 6074 e1000e_reset(adapter); 6075 6076 pm_runtime_put_sync(netdev->dev.parent); 6077 6078 clear_bit(__E1000_RESETTING, &adapter->state); 6079 6080 return 0; 6081 } 6082 6083 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6084 int cmd) 6085 { 6086 struct e1000_adapter *adapter = netdev_priv(netdev); 6087 struct mii_ioctl_data *data = if_mii(ifr); 6088 6089 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6090 return -EOPNOTSUPP; 6091 6092 switch (cmd) { 6093 case SIOCGMIIPHY: 6094 data->phy_id = adapter->hw.phy.addr; 6095 break; 6096 case SIOCGMIIREG: 6097 e1000_phy_read_status(adapter); 6098 6099 switch (data->reg_num & 0x1F) { 6100 case MII_BMCR: 6101 data->val_out = adapter->phy_regs.bmcr; 6102 break; 6103 case MII_BMSR: 6104 data->val_out = adapter->phy_regs.bmsr; 6105 break; 6106 case MII_PHYSID1: 6107 data->val_out = (adapter->hw.phy.id >> 16); 6108 break; 6109 case MII_PHYSID2: 6110 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6111 break; 6112 case MII_ADVERTISE: 6113 data->val_out = adapter->phy_regs.advertise; 6114 break; 6115 case MII_LPA: 6116 data->val_out = adapter->phy_regs.lpa; 6117 break; 6118 case MII_EXPANSION: 6119 data->val_out = adapter->phy_regs.expansion; 6120 break; 6121 case MII_CTRL1000: 6122 data->val_out = adapter->phy_regs.ctrl1000; 6123 break; 6124 case MII_STAT1000: 6125 data->val_out = adapter->phy_regs.stat1000; 6126 break; 6127 case MII_ESTATUS: 6128 data->val_out = adapter->phy_regs.estatus; 6129 break; 6130 default: 6131 return -EIO; 6132 } 6133 break; 6134 case SIOCSMIIREG: 6135 default: 6136 return -EOPNOTSUPP; 6137 } 6138 return 0; 6139 } 6140 6141 /** 6142 * e1000e_hwtstamp_ioctl - control hardware time stamping 6143 * @netdev: network interface device structure 6144 * @ifreq: interface request 6145 * 6146 * Outgoing time stamping can be enabled and disabled. Play nice and 6147 * disable it when requested, although it shouldn't cause any overhead 6148 * when no packet needs it. At most one packet in the queue may be 6149 * marked for time stamping, otherwise it would be impossible to tell 6150 * for sure to which packet the hardware time stamp belongs. 6151 * 6152 * Incoming time stamping has to be configured via the hardware filters. 6153 * Not all combinations are supported, in particular event type has to be 6154 * specified. Matching the kind of event packet is not supported, with the 6155 * exception of "all V2 events regardless of level 2 or 4". 6156 **/ 6157 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6158 { 6159 struct e1000_adapter *adapter = netdev_priv(netdev); 6160 struct hwtstamp_config config; 6161 int ret_val; 6162 6163 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6164 return -EFAULT; 6165 6166 ret_val = e1000e_config_hwtstamp(adapter, &config); 6167 if (ret_val) 6168 return ret_val; 6169 6170 switch (config.rx_filter) { 6171 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6172 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6173 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6174 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6175 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6176 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6177 /* With V2 type filters which specify a Sync or Delay Request, 6178 * Path Delay Request/Response messages are also time stamped 6179 * by hardware so notify the caller the requested packets plus 6180 * some others are time stamped. 6181 */ 6182 config.rx_filter = HWTSTAMP_FILTER_SOME; 6183 break; 6184 default: 6185 break; 6186 } 6187 6188 return copy_to_user(ifr->ifr_data, &config, 6189 sizeof(config)) ? -EFAULT : 0; 6190 } 6191 6192 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6193 { 6194 struct e1000_adapter *adapter = netdev_priv(netdev); 6195 6196 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6197 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6198 } 6199 6200 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6201 { 6202 switch (cmd) { 6203 case SIOCGMIIPHY: 6204 case SIOCGMIIREG: 6205 case SIOCSMIIREG: 6206 return e1000_mii_ioctl(netdev, ifr, cmd); 6207 case SIOCSHWTSTAMP: 6208 return e1000e_hwtstamp_set(netdev, ifr); 6209 case SIOCGHWTSTAMP: 6210 return e1000e_hwtstamp_get(netdev, ifr); 6211 default: 6212 return -EOPNOTSUPP; 6213 } 6214 } 6215 6216 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6217 { 6218 struct e1000_hw *hw = &adapter->hw; 6219 u32 i, mac_reg, wuc; 6220 u16 phy_reg, wuc_enable; 6221 int retval; 6222 6223 /* copy MAC RARs to PHY RARs */ 6224 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6225 6226 retval = hw->phy.ops.acquire(hw); 6227 if (retval) { 6228 e_err("Could not acquire PHY\n"); 6229 return retval; 6230 } 6231 6232 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6233 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6234 if (retval) 6235 goto release; 6236 6237 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6238 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6239 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6240 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6241 (u16)(mac_reg & 0xFFFF)); 6242 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6243 (u16)((mac_reg >> 16) & 0xFFFF)); 6244 } 6245 6246 /* configure PHY Rx Control register */ 6247 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6248 mac_reg = er32(RCTL); 6249 if (mac_reg & E1000_RCTL_UPE) 6250 phy_reg |= BM_RCTL_UPE; 6251 if (mac_reg & E1000_RCTL_MPE) 6252 phy_reg |= BM_RCTL_MPE; 6253 phy_reg &= ~(BM_RCTL_MO_MASK); 6254 if (mac_reg & E1000_RCTL_MO_3) 6255 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6256 << BM_RCTL_MO_SHIFT); 6257 if (mac_reg & E1000_RCTL_BAM) 6258 phy_reg |= BM_RCTL_BAM; 6259 if (mac_reg & E1000_RCTL_PMCF) 6260 phy_reg |= BM_RCTL_PMCF; 6261 mac_reg = er32(CTRL); 6262 if (mac_reg & E1000_CTRL_RFCE) 6263 phy_reg |= BM_RCTL_RFCE; 6264 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6265 6266 wuc = E1000_WUC_PME_EN; 6267 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6268 wuc |= E1000_WUC_APME; 6269 6270 /* enable PHY wakeup in MAC register */ 6271 ew32(WUFC, wufc); 6272 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6273 E1000_WUC_PME_STATUS | wuc)); 6274 6275 /* configure and enable PHY wakeup in PHY registers */ 6276 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6277 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6278 6279 /* activate PHY wakeup */ 6280 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6281 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6282 if (retval) 6283 e_err("Could not set PHY Host Wakeup bit\n"); 6284 release: 6285 hw->phy.ops.release(hw); 6286 6287 return retval; 6288 } 6289 6290 static void e1000e_flush_lpic(struct pci_dev *pdev) 6291 { 6292 struct net_device *netdev = pci_get_drvdata(pdev); 6293 struct e1000_adapter *adapter = netdev_priv(netdev); 6294 struct e1000_hw *hw = &adapter->hw; 6295 u32 ret_val; 6296 6297 pm_runtime_get_sync(netdev->dev.parent); 6298 6299 ret_val = hw->phy.ops.acquire(hw); 6300 if (ret_val) 6301 goto fl_out; 6302 6303 pr_info("EEE TX LPI TIMER: %08X\n", 6304 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6305 6306 hw->phy.ops.release(hw); 6307 6308 fl_out: 6309 pm_runtime_put_sync(netdev->dev.parent); 6310 } 6311 6312 #ifdef CONFIG_PM_SLEEP 6313 /* S0ix implementation */ 6314 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6315 { 6316 struct e1000_hw *hw = &adapter->hw; 6317 u32 mac_data; 6318 u16 phy_data; 6319 6320 /* Disable the periodic inband message, 6321 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6322 */ 6323 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6324 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6325 phy_data |= BIT(10); 6326 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6327 6328 /* Make sure we don't exit K1 every time a new packet arrives 6329 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6330 */ 6331 e1e_rphy(hw, I217_CGFREG, &phy_data); 6332 phy_data |= BIT(5); 6333 e1e_wphy(hw, I217_CGFREG, phy_data); 6334 6335 /* Change the MAC/PHY interface to SMBus 6336 * Force the SMBus in PHY page769_23[0] = 1 6337 * Force the SMBus in MAC CTRL_EXT[11] = 1 6338 */ 6339 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6340 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6341 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6342 mac_data = er32(CTRL_EXT); 6343 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6344 ew32(CTRL_EXT, mac_data); 6345 6346 /* DFT control: PHY bit: page769_20[0] = 1 6347 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6348 */ 6349 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6350 phy_data |= BIT(0); 6351 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6352 6353 mac_data = er32(EXTCNF_CTRL); 6354 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6355 ew32(EXTCNF_CTRL, mac_data); 6356 6357 /* Check MAC Tx/Rx packet buffer pointers. 6358 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6359 * pending traffic indication that would prevent power gating. 6360 */ 6361 mac_data = er32(TDFH); 6362 if (mac_data) 6363 ew32(TDFH, 0); 6364 mac_data = er32(TDFT); 6365 if (mac_data) 6366 ew32(TDFT, 0); 6367 mac_data = er32(TDFHS); 6368 if (mac_data) 6369 ew32(TDFHS, 0); 6370 mac_data = er32(TDFTS); 6371 if (mac_data) 6372 ew32(TDFTS, 0); 6373 mac_data = er32(TDFPC); 6374 if (mac_data) 6375 ew32(TDFPC, 0); 6376 mac_data = er32(RDFH); 6377 if (mac_data) 6378 ew32(RDFH, 0); 6379 mac_data = er32(RDFT); 6380 if (mac_data) 6381 ew32(RDFT, 0); 6382 mac_data = er32(RDFHS); 6383 if (mac_data) 6384 ew32(RDFHS, 0); 6385 mac_data = er32(RDFTS); 6386 if (mac_data) 6387 ew32(RDFTS, 0); 6388 mac_data = er32(RDFPC); 6389 if (mac_data) 6390 ew32(RDFPC, 0); 6391 6392 /* Enable the Dynamic Power Gating in the MAC */ 6393 mac_data = er32(FEXTNVM7); 6394 mac_data |= BIT(22); 6395 ew32(FEXTNVM7, mac_data); 6396 6397 /* Disable the time synchronization clock */ 6398 mac_data = er32(FEXTNVM7); 6399 mac_data |= BIT(31); 6400 mac_data &= ~BIT(0); 6401 ew32(FEXTNVM7, mac_data); 6402 6403 /* Dynamic Power Gating Enable */ 6404 mac_data = er32(CTRL_EXT); 6405 mac_data |= BIT(3); 6406 ew32(CTRL_EXT, mac_data); 6407 6408 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6409 mac_data = er32(CTRL_EXT); 6410 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6411 ew32(CTRL_EXT, mac_data); 6412 6413 /* No MAC DPG gating SLP_S0 in modern standby 6414 * Switch the logic of the lanphypc to use PMC counter 6415 */ 6416 mac_data = er32(FEXTNVM5); 6417 mac_data |= BIT(7); 6418 ew32(FEXTNVM5, mac_data); 6419 } 6420 6421 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6422 { 6423 struct e1000_hw *hw = &adapter->hw; 6424 u32 mac_data; 6425 u16 phy_data; 6426 6427 /* Disable the Dynamic Power Gating in the MAC */ 6428 mac_data = er32(FEXTNVM7); 6429 mac_data &= 0xFFBFFFFF; 6430 ew32(FEXTNVM7, mac_data); 6431 6432 /* Enable the time synchronization clock */ 6433 mac_data = er32(FEXTNVM7); 6434 mac_data |= BIT(0); 6435 ew32(FEXTNVM7, mac_data); 6436 6437 /* Disable Dynamic Power Gating */ 6438 mac_data = er32(CTRL_EXT); 6439 mac_data &= 0xFFFFFFF7; 6440 ew32(CTRL_EXT, mac_data); 6441 6442 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6443 mac_data = er32(CTRL_EXT); 6444 mac_data &= 0xFFF7FFFF; 6445 ew32(CTRL_EXT, mac_data); 6446 6447 /* Revert the lanphypc logic to use the internal Gbe counter 6448 * and not the PMC counter 6449 */ 6450 mac_data = er32(FEXTNVM5); 6451 mac_data &= 0xFFFFFF7F; 6452 ew32(FEXTNVM5, mac_data); 6453 6454 /* Enable the periodic inband message, 6455 * Request PCIe clock in K1 page770_17[10:9] =01b 6456 */ 6457 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6458 phy_data &= 0xFBFF; 6459 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6460 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6461 6462 /* Return back configuration 6463 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6464 */ 6465 e1e_rphy(hw, I217_CGFREG, &phy_data); 6466 phy_data &= 0xFFDF; 6467 e1e_wphy(hw, I217_CGFREG, phy_data); 6468 6469 /* Change the MAC/PHY interface to Kumeran 6470 * Unforce the SMBus in PHY page769_23[0] = 0 6471 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6472 */ 6473 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6474 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6475 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6476 mac_data = er32(CTRL_EXT); 6477 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6478 ew32(CTRL_EXT, mac_data); 6479 } 6480 #endif /* CONFIG_PM_SLEEP */ 6481 6482 static int e1000e_pm_freeze(struct device *dev) 6483 { 6484 struct net_device *netdev = dev_get_drvdata(dev); 6485 struct e1000_adapter *adapter = netdev_priv(netdev); 6486 bool present; 6487 6488 rtnl_lock(); 6489 6490 present = netif_device_present(netdev); 6491 netif_device_detach(netdev); 6492 6493 if (present && netif_running(netdev)) { 6494 int count = E1000_CHECK_RESET_COUNT; 6495 6496 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6497 usleep_range(10000, 11000); 6498 6499 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6500 6501 /* Quiesce the device without resetting the hardware */ 6502 e1000e_down(adapter, false); 6503 e1000_free_irq(adapter); 6504 } 6505 rtnl_unlock(); 6506 6507 e1000e_reset_interrupt_capability(adapter); 6508 6509 /* Allow time for pending master requests to run */ 6510 e1000e_disable_pcie_master(&adapter->hw); 6511 6512 return 0; 6513 } 6514 6515 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6516 { 6517 struct net_device *netdev = pci_get_drvdata(pdev); 6518 struct e1000_adapter *adapter = netdev_priv(netdev); 6519 struct e1000_hw *hw = &adapter->hw; 6520 u32 ctrl, ctrl_ext, rctl, status; 6521 /* Runtime suspend should only enable wakeup for link changes */ 6522 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6523 int retval = 0; 6524 6525 status = er32(STATUS); 6526 if (status & E1000_STATUS_LU) 6527 wufc &= ~E1000_WUFC_LNKC; 6528 6529 if (wufc) { 6530 e1000_setup_rctl(adapter); 6531 e1000e_set_rx_mode(netdev); 6532 6533 /* turn on all-multi mode if wake on multicast is enabled */ 6534 if (wufc & E1000_WUFC_MC) { 6535 rctl = er32(RCTL); 6536 rctl |= E1000_RCTL_MPE; 6537 ew32(RCTL, rctl); 6538 } 6539 6540 ctrl = er32(CTRL); 6541 ctrl |= E1000_CTRL_ADVD3WUC; 6542 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6543 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6544 ew32(CTRL, ctrl); 6545 6546 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6547 adapter->hw.phy.media_type == 6548 e1000_media_type_internal_serdes) { 6549 /* keep the laser running in D3 */ 6550 ctrl_ext = er32(CTRL_EXT); 6551 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6552 ew32(CTRL_EXT, ctrl_ext); 6553 } 6554 6555 if (!runtime) 6556 e1000e_power_up_phy(adapter); 6557 6558 if (adapter->flags & FLAG_IS_ICH) 6559 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6560 6561 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6562 /* enable wakeup by the PHY */ 6563 retval = e1000_init_phy_wakeup(adapter, wufc); 6564 if (retval) 6565 return retval; 6566 } else { 6567 /* enable wakeup by the MAC */ 6568 ew32(WUFC, wufc); 6569 ew32(WUC, E1000_WUC_PME_EN); 6570 } 6571 } else { 6572 ew32(WUC, 0); 6573 ew32(WUFC, 0); 6574 6575 e1000_power_down_phy(adapter); 6576 } 6577 6578 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6579 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6580 } else if (hw->mac.type >= e1000_pch_lpt) { 6581 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6582 /* ULP does not support wake from unicast, multicast 6583 * or broadcast. 6584 */ 6585 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6586 6587 if (retval) 6588 return retval; 6589 } 6590 6591 /* Ensure that the appropriate bits are set in LPI_CTRL 6592 * for EEE in Sx 6593 */ 6594 if ((hw->phy.type >= e1000_phy_i217) && 6595 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6596 u16 lpi_ctrl = 0; 6597 6598 retval = hw->phy.ops.acquire(hw); 6599 if (!retval) { 6600 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6601 &lpi_ctrl); 6602 if (!retval) { 6603 if (adapter->eee_advert & 6604 hw->dev_spec.ich8lan.eee_lp_ability & 6605 I82579_EEE_100_SUPPORTED) 6606 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6607 if (adapter->eee_advert & 6608 hw->dev_spec.ich8lan.eee_lp_ability & 6609 I82579_EEE_1000_SUPPORTED) 6610 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6611 6612 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6613 lpi_ctrl); 6614 } 6615 } 6616 hw->phy.ops.release(hw); 6617 } 6618 6619 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6620 * would have already happened in close and is redundant. 6621 */ 6622 e1000e_release_hw_control(adapter); 6623 6624 pci_clear_master(pdev); 6625 6626 /* The pci-e switch on some quad port adapters will report a 6627 * correctable error when the MAC transitions from D0 to D3. To 6628 * prevent this we need to mask off the correctable errors on the 6629 * downstream port of the pci-e switch. 6630 * 6631 * We don't have the associated upstream bridge while assigning 6632 * the PCI device into guest. For example, the KVM on power is 6633 * one of the cases. 6634 */ 6635 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6636 struct pci_dev *us_dev = pdev->bus->self; 6637 u16 devctl; 6638 6639 if (!us_dev) 6640 return 0; 6641 6642 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6643 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6644 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6645 6646 pci_save_state(pdev); 6647 pci_prepare_to_sleep(pdev); 6648 6649 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6650 } 6651 6652 return 0; 6653 } 6654 6655 /** 6656 * __e1000e_disable_aspm - Disable ASPM states 6657 * @pdev: pointer to PCI device struct 6658 * @state: bit-mask of ASPM states to disable 6659 * @locked: indication if this context holds pci_bus_sem locked. 6660 * 6661 * Some devices *must* have certain ASPM states disabled per hardware errata. 6662 **/ 6663 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6664 { 6665 struct pci_dev *parent = pdev->bus->self; 6666 u16 aspm_dis_mask = 0; 6667 u16 pdev_aspmc, parent_aspmc; 6668 6669 switch (state) { 6670 case PCIE_LINK_STATE_L0S: 6671 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6672 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6673 /* fall-through - can't have L1 without L0s */ 6674 case PCIE_LINK_STATE_L1: 6675 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6676 break; 6677 default: 6678 return; 6679 } 6680 6681 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6682 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6683 6684 if (parent) { 6685 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6686 &parent_aspmc); 6687 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6688 } 6689 6690 /* Nothing to do if the ASPM states to be disabled already are */ 6691 if (!(pdev_aspmc & aspm_dis_mask) && 6692 (!parent || !(parent_aspmc & aspm_dis_mask))) 6693 return; 6694 6695 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6696 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6697 "L0s" : "", 6698 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6699 "L1" : ""); 6700 6701 #ifdef CONFIG_PCIEASPM 6702 if (locked) 6703 pci_disable_link_state_locked(pdev, state); 6704 else 6705 pci_disable_link_state(pdev, state); 6706 6707 /* Double-check ASPM control. If not disabled by the above, the 6708 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6709 * not enabled); override by writing PCI config space directly. 6710 */ 6711 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6712 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6713 6714 if (!(aspm_dis_mask & pdev_aspmc)) 6715 return; 6716 #endif 6717 6718 /* Both device and parent should have the same ASPM setting. 6719 * Disable ASPM in downstream component first and then upstream. 6720 */ 6721 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6722 6723 if (parent) 6724 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6725 aspm_dis_mask); 6726 } 6727 6728 /** 6729 * e1000e_disable_aspm - Disable ASPM states. 6730 * @pdev: pointer to PCI device struct 6731 * @state: bit-mask of ASPM states to disable 6732 * 6733 * This function acquires the pci_bus_sem! 6734 * Some devices *must* have certain ASPM states disabled per hardware errata. 6735 **/ 6736 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6737 { 6738 __e1000e_disable_aspm(pdev, state, 0); 6739 } 6740 6741 /** 6742 * e1000e_disable_aspm_locked Disable ASPM states. 6743 * @pdev: pointer to PCI device struct 6744 * @state: bit-mask of ASPM states to disable 6745 * 6746 * This function must be called with pci_bus_sem acquired! 6747 * Some devices *must* have certain ASPM states disabled per hardware errata. 6748 **/ 6749 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6750 { 6751 __e1000e_disable_aspm(pdev, state, 1); 6752 } 6753 6754 static int e1000e_pm_thaw(struct device *dev) 6755 { 6756 struct net_device *netdev = dev_get_drvdata(dev); 6757 struct e1000_adapter *adapter = netdev_priv(netdev); 6758 int rc = 0; 6759 6760 e1000e_set_interrupt_capability(adapter); 6761 6762 rtnl_lock(); 6763 if (netif_running(netdev)) { 6764 rc = e1000_request_irq(adapter); 6765 if (rc) 6766 goto err_irq; 6767 6768 e1000e_up(adapter); 6769 } 6770 6771 netif_device_attach(netdev); 6772 err_irq: 6773 rtnl_unlock(); 6774 6775 return rc; 6776 } 6777 6778 #ifdef CONFIG_PM 6779 static int __e1000_resume(struct pci_dev *pdev) 6780 { 6781 struct net_device *netdev = pci_get_drvdata(pdev); 6782 struct e1000_adapter *adapter = netdev_priv(netdev); 6783 struct e1000_hw *hw = &adapter->hw; 6784 u16 aspm_disable_flag = 0; 6785 6786 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6787 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6788 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6789 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6790 if (aspm_disable_flag) 6791 e1000e_disable_aspm(pdev, aspm_disable_flag); 6792 6793 pci_set_master(pdev); 6794 6795 if (hw->mac.type >= e1000_pch2lan) 6796 e1000_resume_workarounds_pchlan(&adapter->hw); 6797 6798 e1000e_power_up_phy(adapter); 6799 6800 /* report the system wakeup cause from S3/S4 */ 6801 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6802 u16 phy_data; 6803 6804 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6805 if (phy_data) { 6806 e_info("PHY Wakeup cause - %s\n", 6807 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6808 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6809 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6810 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6811 phy_data & E1000_WUS_LNKC ? 6812 "Link Status Change" : "other"); 6813 } 6814 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6815 } else { 6816 u32 wus = er32(WUS); 6817 6818 if (wus) { 6819 e_info("MAC Wakeup cause - %s\n", 6820 wus & E1000_WUS_EX ? "Unicast Packet" : 6821 wus & E1000_WUS_MC ? "Multicast Packet" : 6822 wus & E1000_WUS_BC ? "Broadcast Packet" : 6823 wus & E1000_WUS_MAG ? "Magic Packet" : 6824 wus & E1000_WUS_LNKC ? "Link Status Change" : 6825 "other"); 6826 } 6827 ew32(WUS, ~0); 6828 } 6829 6830 e1000e_reset(adapter); 6831 6832 e1000_init_manageability_pt(adapter); 6833 6834 /* If the controller has AMT, do not set DRV_LOAD until the interface 6835 * is up. For all other cases, let the f/w know that the h/w is now 6836 * under the control of the driver. 6837 */ 6838 if (!(adapter->flags & FLAG_HAS_AMT)) 6839 e1000e_get_hw_control(adapter); 6840 6841 return 0; 6842 } 6843 6844 #ifdef CONFIG_PM_SLEEP 6845 static int e1000e_pm_suspend(struct device *dev) 6846 { 6847 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6848 struct e1000_adapter *adapter = netdev_priv(netdev); 6849 struct pci_dev *pdev = to_pci_dev(dev); 6850 struct e1000_hw *hw = &adapter->hw; 6851 int rc; 6852 6853 e1000e_flush_lpic(pdev); 6854 6855 e1000e_pm_freeze(dev); 6856 6857 rc = __e1000_shutdown(pdev, false); 6858 if (rc) 6859 e1000e_pm_thaw(dev); 6860 6861 /* Introduce S0ix implementation */ 6862 if (hw->mac.type >= e1000_pch_cnp) 6863 e1000e_s0ix_entry_flow(adapter); 6864 6865 return rc; 6866 } 6867 6868 static int e1000e_pm_resume(struct device *dev) 6869 { 6870 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6871 struct e1000_adapter *adapter = netdev_priv(netdev); 6872 struct pci_dev *pdev = to_pci_dev(dev); 6873 struct e1000_hw *hw = &adapter->hw; 6874 int rc; 6875 6876 /* Introduce S0ix implementation */ 6877 if (hw->mac.type >= e1000_pch_cnp) 6878 e1000e_s0ix_exit_flow(adapter); 6879 6880 rc = __e1000_resume(pdev); 6881 if (rc) 6882 return rc; 6883 6884 return e1000e_pm_thaw(dev); 6885 } 6886 #endif /* CONFIG_PM_SLEEP */ 6887 6888 static int e1000e_pm_runtime_idle(struct device *dev) 6889 { 6890 struct net_device *netdev = dev_get_drvdata(dev); 6891 struct e1000_adapter *adapter = netdev_priv(netdev); 6892 u16 eee_lp; 6893 6894 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6895 6896 if (!e1000e_has_link(adapter)) { 6897 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6898 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6899 } 6900 6901 return -EBUSY; 6902 } 6903 6904 static int e1000e_pm_runtime_resume(struct device *dev) 6905 { 6906 struct pci_dev *pdev = to_pci_dev(dev); 6907 struct net_device *netdev = pci_get_drvdata(pdev); 6908 struct e1000_adapter *adapter = netdev_priv(netdev); 6909 int rc; 6910 6911 rc = __e1000_resume(pdev); 6912 if (rc) 6913 return rc; 6914 6915 if (netdev->flags & IFF_UP) 6916 e1000e_up(adapter); 6917 6918 return rc; 6919 } 6920 6921 static int e1000e_pm_runtime_suspend(struct device *dev) 6922 { 6923 struct pci_dev *pdev = to_pci_dev(dev); 6924 struct net_device *netdev = pci_get_drvdata(pdev); 6925 struct e1000_adapter *adapter = netdev_priv(netdev); 6926 6927 if (netdev->flags & IFF_UP) { 6928 int count = E1000_CHECK_RESET_COUNT; 6929 6930 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6931 usleep_range(10000, 11000); 6932 6933 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6934 6935 /* Down the device without resetting the hardware */ 6936 e1000e_down(adapter, false); 6937 } 6938 6939 if (__e1000_shutdown(pdev, true)) { 6940 e1000e_pm_runtime_resume(dev); 6941 return -EBUSY; 6942 } 6943 6944 return 0; 6945 } 6946 #endif /* CONFIG_PM */ 6947 6948 static void e1000_shutdown(struct pci_dev *pdev) 6949 { 6950 e1000e_flush_lpic(pdev); 6951 6952 e1000e_pm_freeze(&pdev->dev); 6953 6954 __e1000_shutdown(pdev, false); 6955 } 6956 6957 #ifdef CONFIG_NET_POLL_CONTROLLER 6958 6959 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6960 { 6961 struct net_device *netdev = data; 6962 struct e1000_adapter *adapter = netdev_priv(netdev); 6963 6964 if (adapter->msix_entries) { 6965 int vector, msix_irq; 6966 6967 vector = 0; 6968 msix_irq = adapter->msix_entries[vector].vector; 6969 if (disable_hardirq(msix_irq)) 6970 e1000_intr_msix_rx(msix_irq, netdev); 6971 enable_irq(msix_irq); 6972 6973 vector++; 6974 msix_irq = adapter->msix_entries[vector].vector; 6975 if (disable_hardirq(msix_irq)) 6976 e1000_intr_msix_tx(msix_irq, netdev); 6977 enable_irq(msix_irq); 6978 6979 vector++; 6980 msix_irq = adapter->msix_entries[vector].vector; 6981 if (disable_hardirq(msix_irq)) 6982 e1000_msix_other(msix_irq, netdev); 6983 enable_irq(msix_irq); 6984 } 6985 6986 return IRQ_HANDLED; 6987 } 6988 6989 /** 6990 * e1000_netpoll 6991 * @netdev: network interface device structure 6992 * 6993 * Polling 'interrupt' - used by things like netconsole to send skbs 6994 * without having to re-enable interrupts. It's not called while 6995 * the interrupt routine is executing. 6996 */ 6997 static void e1000_netpoll(struct net_device *netdev) 6998 { 6999 struct e1000_adapter *adapter = netdev_priv(netdev); 7000 7001 switch (adapter->int_mode) { 7002 case E1000E_INT_MODE_MSIX: 7003 e1000_intr_msix(adapter->pdev->irq, netdev); 7004 break; 7005 case E1000E_INT_MODE_MSI: 7006 if (disable_hardirq(adapter->pdev->irq)) 7007 e1000_intr_msi(adapter->pdev->irq, netdev); 7008 enable_irq(adapter->pdev->irq); 7009 break; 7010 default: /* E1000E_INT_MODE_LEGACY */ 7011 if (disable_hardirq(adapter->pdev->irq)) 7012 e1000_intr(adapter->pdev->irq, netdev); 7013 enable_irq(adapter->pdev->irq); 7014 break; 7015 } 7016 } 7017 #endif 7018 7019 /** 7020 * e1000_io_error_detected - called when PCI error is detected 7021 * @pdev: Pointer to PCI device 7022 * @state: The current pci connection state 7023 * 7024 * This function is called after a PCI bus error affecting 7025 * this device has been detected. 7026 */ 7027 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7028 pci_channel_state_t state) 7029 { 7030 e1000e_pm_freeze(&pdev->dev); 7031 7032 if (state == pci_channel_io_perm_failure) 7033 return PCI_ERS_RESULT_DISCONNECT; 7034 7035 pci_disable_device(pdev); 7036 7037 /* Request a slot slot reset. */ 7038 return PCI_ERS_RESULT_NEED_RESET; 7039 } 7040 7041 /** 7042 * e1000_io_slot_reset - called after the pci bus has been reset. 7043 * @pdev: Pointer to PCI device 7044 * 7045 * Restart the card from scratch, as if from a cold-boot. Implementation 7046 * resembles the first-half of the e1000e_pm_resume routine. 7047 */ 7048 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7049 { 7050 struct net_device *netdev = pci_get_drvdata(pdev); 7051 struct e1000_adapter *adapter = netdev_priv(netdev); 7052 struct e1000_hw *hw = &adapter->hw; 7053 u16 aspm_disable_flag = 0; 7054 int err; 7055 pci_ers_result_t result; 7056 7057 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7058 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7059 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7060 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7061 if (aspm_disable_flag) 7062 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7063 7064 err = pci_enable_device_mem(pdev); 7065 if (err) { 7066 dev_err(&pdev->dev, 7067 "Cannot re-enable PCI device after reset.\n"); 7068 result = PCI_ERS_RESULT_DISCONNECT; 7069 } else { 7070 pdev->state_saved = true; 7071 pci_restore_state(pdev); 7072 pci_set_master(pdev); 7073 7074 pci_enable_wake(pdev, PCI_D3hot, 0); 7075 pci_enable_wake(pdev, PCI_D3cold, 0); 7076 7077 e1000e_reset(adapter); 7078 ew32(WUS, ~0); 7079 result = PCI_ERS_RESULT_RECOVERED; 7080 } 7081 7082 return result; 7083 } 7084 7085 /** 7086 * e1000_io_resume - called when traffic can start flowing again. 7087 * @pdev: Pointer to PCI device 7088 * 7089 * This callback is called when the error recovery driver tells us that 7090 * its OK to resume normal operation. Implementation resembles the 7091 * second-half of the e1000e_pm_resume routine. 7092 */ 7093 static void e1000_io_resume(struct pci_dev *pdev) 7094 { 7095 struct net_device *netdev = pci_get_drvdata(pdev); 7096 struct e1000_adapter *adapter = netdev_priv(netdev); 7097 7098 e1000_init_manageability_pt(adapter); 7099 7100 e1000e_pm_thaw(&pdev->dev); 7101 7102 /* If the controller has AMT, do not set DRV_LOAD until the interface 7103 * is up. For all other cases, let the f/w know that the h/w is now 7104 * under the control of the driver. 7105 */ 7106 if (!(adapter->flags & FLAG_HAS_AMT)) 7107 e1000e_get_hw_control(adapter); 7108 } 7109 7110 static void e1000_print_device_info(struct e1000_adapter *adapter) 7111 { 7112 struct e1000_hw *hw = &adapter->hw; 7113 struct net_device *netdev = adapter->netdev; 7114 u32 ret_val; 7115 u8 pba_str[E1000_PBANUM_LENGTH]; 7116 7117 /* print bus type/speed/width info */ 7118 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7119 /* bus width */ 7120 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7121 "Width x1"), 7122 /* MAC address */ 7123 netdev->dev_addr); 7124 e_info("Intel(R) PRO/%s Network Connection\n", 7125 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7126 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7127 E1000_PBANUM_LENGTH); 7128 if (ret_val) 7129 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7130 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7131 hw->mac.type, hw->phy.type, pba_str); 7132 } 7133 7134 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7135 { 7136 struct e1000_hw *hw = &adapter->hw; 7137 int ret_val; 7138 u16 buf = 0; 7139 7140 if (hw->mac.type != e1000_82573) 7141 return; 7142 7143 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7144 le16_to_cpus(&buf); 7145 if (!ret_val && (!(buf & BIT(0)))) { 7146 /* Deep Smart Power Down (DSPD) */ 7147 dev_warn(&adapter->pdev->dev, 7148 "Warning: detected DSPD enabled in EEPROM\n"); 7149 } 7150 } 7151 7152 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7153 netdev_features_t features) 7154 { 7155 struct e1000_adapter *adapter = netdev_priv(netdev); 7156 struct e1000_hw *hw = &adapter->hw; 7157 7158 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7159 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7160 features &= ~NETIF_F_RXFCS; 7161 7162 /* Since there is no support for separate Rx/Tx vlan accel 7163 * enable/disable make sure Tx flag is always in same state as Rx. 7164 */ 7165 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7166 features |= NETIF_F_HW_VLAN_CTAG_TX; 7167 else 7168 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7169 7170 return features; 7171 } 7172 7173 static int e1000_set_features(struct net_device *netdev, 7174 netdev_features_t features) 7175 { 7176 struct e1000_adapter *adapter = netdev_priv(netdev); 7177 netdev_features_t changed = features ^ netdev->features; 7178 7179 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7180 adapter->flags |= FLAG_TSO_FORCE; 7181 7182 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7183 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7184 NETIF_F_RXALL))) 7185 return 0; 7186 7187 if (changed & NETIF_F_RXFCS) { 7188 if (features & NETIF_F_RXFCS) { 7189 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7190 } else { 7191 /* We need to take it back to defaults, which might mean 7192 * stripping is still disabled at the adapter level. 7193 */ 7194 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7195 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7196 else 7197 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7198 } 7199 } 7200 7201 netdev->features = features; 7202 7203 if (netif_running(netdev)) 7204 e1000e_reinit_locked(adapter); 7205 else 7206 e1000e_reset(adapter); 7207 7208 return 1; 7209 } 7210 7211 static const struct net_device_ops e1000e_netdev_ops = { 7212 .ndo_open = e1000e_open, 7213 .ndo_stop = e1000e_close, 7214 .ndo_start_xmit = e1000_xmit_frame, 7215 .ndo_get_stats64 = e1000e_get_stats64, 7216 .ndo_set_rx_mode = e1000e_set_rx_mode, 7217 .ndo_set_mac_address = e1000_set_mac, 7218 .ndo_change_mtu = e1000_change_mtu, 7219 .ndo_do_ioctl = e1000_ioctl, 7220 .ndo_tx_timeout = e1000_tx_timeout, 7221 .ndo_validate_addr = eth_validate_addr, 7222 7223 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7224 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7225 #ifdef CONFIG_NET_POLL_CONTROLLER 7226 .ndo_poll_controller = e1000_netpoll, 7227 #endif 7228 .ndo_set_features = e1000_set_features, 7229 .ndo_fix_features = e1000_fix_features, 7230 .ndo_features_check = passthru_features_check, 7231 }; 7232 7233 /** 7234 * e1000_probe - Device Initialization Routine 7235 * @pdev: PCI device information struct 7236 * @ent: entry in e1000_pci_tbl 7237 * 7238 * Returns 0 on success, negative on failure 7239 * 7240 * e1000_probe initializes an adapter identified by a pci_dev structure. 7241 * The OS initialization, configuring of the adapter private structure, 7242 * and a hardware reset occur. 7243 **/ 7244 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7245 { 7246 struct net_device *netdev; 7247 struct e1000_adapter *adapter; 7248 struct e1000_hw *hw; 7249 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7250 resource_size_t mmio_start, mmio_len; 7251 resource_size_t flash_start, flash_len; 7252 static int cards_found; 7253 u16 aspm_disable_flag = 0; 7254 int bars, i, err, pci_using_dac; 7255 u16 eeprom_data = 0; 7256 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7257 s32 ret_val = 0; 7258 7259 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7260 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7261 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7262 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7263 if (aspm_disable_flag) 7264 e1000e_disable_aspm(pdev, aspm_disable_flag); 7265 7266 err = pci_enable_device_mem(pdev); 7267 if (err) 7268 return err; 7269 7270 pci_using_dac = 0; 7271 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7272 if (!err) { 7273 pci_using_dac = 1; 7274 } else { 7275 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7276 if (err) { 7277 dev_err(&pdev->dev, 7278 "No usable DMA configuration, aborting\n"); 7279 goto err_dma; 7280 } 7281 } 7282 7283 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7284 err = pci_request_selected_regions_exclusive(pdev, bars, 7285 e1000e_driver_name); 7286 if (err) 7287 goto err_pci_reg; 7288 7289 /* AER (Advanced Error Reporting) hooks */ 7290 pci_enable_pcie_error_reporting(pdev); 7291 7292 pci_set_master(pdev); 7293 /* PCI config space info */ 7294 err = pci_save_state(pdev); 7295 if (err) 7296 goto err_alloc_etherdev; 7297 7298 err = -ENOMEM; 7299 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7300 if (!netdev) 7301 goto err_alloc_etherdev; 7302 7303 SET_NETDEV_DEV(netdev, &pdev->dev); 7304 7305 netdev->irq = pdev->irq; 7306 7307 pci_set_drvdata(pdev, netdev); 7308 adapter = netdev_priv(netdev); 7309 hw = &adapter->hw; 7310 adapter->netdev = netdev; 7311 adapter->pdev = pdev; 7312 adapter->ei = ei; 7313 adapter->pba = ei->pba; 7314 adapter->flags = ei->flags; 7315 adapter->flags2 = ei->flags2; 7316 adapter->hw.adapter = adapter; 7317 adapter->hw.mac.type = ei->mac; 7318 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7319 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7320 7321 mmio_start = pci_resource_start(pdev, 0); 7322 mmio_len = pci_resource_len(pdev, 0); 7323 7324 err = -EIO; 7325 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7326 if (!adapter->hw.hw_addr) 7327 goto err_ioremap; 7328 7329 if ((adapter->flags & FLAG_HAS_FLASH) && 7330 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7331 (hw->mac.type < e1000_pch_spt)) { 7332 flash_start = pci_resource_start(pdev, 1); 7333 flash_len = pci_resource_len(pdev, 1); 7334 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7335 if (!adapter->hw.flash_address) 7336 goto err_flashmap; 7337 } 7338 7339 /* Set default EEE advertisement */ 7340 if (adapter->flags2 & FLAG2_HAS_EEE) 7341 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7342 7343 /* construct the net_device struct */ 7344 netdev->netdev_ops = &e1000e_netdev_ops; 7345 e1000e_set_ethtool_ops(netdev); 7346 netdev->watchdog_timeo = 5 * HZ; 7347 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7348 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7349 7350 netdev->mem_start = mmio_start; 7351 netdev->mem_end = mmio_start + mmio_len; 7352 7353 adapter->bd_number = cards_found++; 7354 7355 e1000e_check_options(adapter); 7356 7357 /* setup adapter struct */ 7358 err = e1000_sw_init(adapter); 7359 if (err) 7360 goto err_sw_init; 7361 7362 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7363 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7364 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7365 7366 err = ei->get_variants(adapter); 7367 if (err) 7368 goto err_hw_init; 7369 7370 if ((adapter->flags & FLAG_IS_ICH) && 7371 (adapter->flags & FLAG_READ_ONLY_NVM) && 7372 (hw->mac.type < e1000_pch_spt)) 7373 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7374 7375 hw->mac.ops.get_bus_info(&adapter->hw); 7376 7377 adapter->hw.phy.autoneg_wait_to_complete = 0; 7378 7379 /* Copper options */ 7380 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7381 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7382 adapter->hw.phy.disable_polarity_correction = 0; 7383 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7384 } 7385 7386 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7387 dev_info(&pdev->dev, 7388 "PHY reset is blocked due to SOL/IDER session.\n"); 7389 7390 /* Set initial default active device features */ 7391 netdev->features = (NETIF_F_SG | 7392 NETIF_F_HW_VLAN_CTAG_RX | 7393 NETIF_F_HW_VLAN_CTAG_TX | 7394 NETIF_F_TSO | 7395 NETIF_F_TSO6 | 7396 NETIF_F_RXHASH | 7397 NETIF_F_RXCSUM | 7398 NETIF_F_HW_CSUM); 7399 7400 /* Set user-changeable features (subset of all device features) */ 7401 netdev->hw_features = netdev->features; 7402 netdev->hw_features |= NETIF_F_RXFCS; 7403 netdev->priv_flags |= IFF_SUPP_NOFCS; 7404 netdev->hw_features |= NETIF_F_RXALL; 7405 7406 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7407 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7408 7409 netdev->vlan_features |= (NETIF_F_SG | 7410 NETIF_F_TSO | 7411 NETIF_F_TSO6 | 7412 NETIF_F_HW_CSUM); 7413 7414 netdev->priv_flags |= IFF_UNICAST_FLT; 7415 7416 if (pci_using_dac) { 7417 netdev->features |= NETIF_F_HIGHDMA; 7418 netdev->vlan_features |= NETIF_F_HIGHDMA; 7419 } 7420 7421 /* MTU range: 68 - max_hw_frame_size */ 7422 netdev->min_mtu = ETH_MIN_MTU; 7423 netdev->max_mtu = adapter->max_hw_frame_size - 7424 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7425 7426 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7427 adapter->flags |= FLAG_MNG_PT_ENABLED; 7428 7429 /* before reading the NVM, reset the controller to 7430 * put the device in a known good starting state 7431 */ 7432 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7433 7434 /* systems with ASPM and others may see the checksum fail on the first 7435 * attempt. Let's give it a few tries 7436 */ 7437 for (i = 0;; i++) { 7438 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7439 break; 7440 if (i == 2) { 7441 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7442 err = -EIO; 7443 goto err_eeprom; 7444 } 7445 } 7446 7447 e1000_eeprom_checks(adapter); 7448 7449 /* copy the MAC address */ 7450 if (e1000e_read_mac_addr(&adapter->hw)) 7451 dev_err(&pdev->dev, 7452 "NVM Read Error while reading MAC address\n"); 7453 7454 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7455 7456 if (!is_valid_ether_addr(netdev->dev_addr)) { 7457 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7458 netdev->dev_addr); 7459 err = -EIO; 7460 goto err_eeprom; 7461 } 7462 7463 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7464 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7465 7466 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7467 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7468 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7469 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7470 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7471 7472 /* Initialize link parameters. User can change them with ethtool */ 7473 adapter->hw.mac.autoneg = 1; 7474 adapter->fc_autoneg = true; 7475 adapter->hw.fc.requested_mode = e1000_fc_default; 7476 adapter->hw.fc.current_mode = e1000_fc_default; 7477 adapter->hw.phy.autoneg_advertised = 0x2f; 7478 7479 /* Initial Wake on LAN setting - If APM wake is enabled in 7480 * the EEPROM, enable the ACPI Magic Packet filter 7481 */ 7482 if (adapter->flags & FLAG_APME_IN_WUC) { 7483 /* APME bit in EEPROM is mapped to WUC.APME */ 7484 eeprom_data = er32(WUC); 7485 eeprom_apme_mask = E1000_WUC_APME; 7486 if ((hw->mac.type > e1000_ich10lan) && 7487 (eeprom_data & E1000_WUC_PHY_WAKE)) 7488 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7489 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7490 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7491 (adapter->hw.bus.func == 1)) 7492 ret_val = e1000_read_nvm(&adapter->hw, 7493 NVM_INIT_CONTROL3_PORT_B, 7494 1, &eeprom_data); 7495 else 7496 ret_val = e1000_read_nvm(&adapter->hw, 7497 NVM_INIT_CONTROL3_PORT_A, 7498 1, &eeprom_data); 7499 } 7500 7501 /* fetch WoL from EEPROM */ 7502 if (ret_val) 7503 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7504 else if (eeprom_data & eeprom_apme_mask) 7505 adapter->eeprom_wol |= E1000_WUFC_MAG; 7506 7507 /* now that we have the eeprom settings, apply the special cases 7508 * where the eeprom may be wrong or the board simply won't support 7509 * wake on lan on a particular port 7510 */ 7511 if (!(adapter->flags & FLAG_HAS_WOL)) 7512 adapter->eeprom_wol = 0; 7513 7514 /* initialize the wol settings based on the eeprom settings */ 7515 adapter->wol = adapter->eeprom_wol; 7516 7517 /* make sure adapter isn't asleep if manageability is enabled */ 7518 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7519 (hw->mac.ops.check_mng_mode(hw))) 7520 device_wakeup_enable(&pdev->dev); 7521 7522 /* save off EEPROM version number */ 7523 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7524 7525 if (ret_val) { 7526 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7527 adapter->eeprom_vers = 0; 7528 } 7529 7530 /* init PTP hardware clock */ 7531 e1000e_ptp_init(adapter); 7532 7533 /* reset the hardware with the new settings */ 7534 e1000e_reset(adapter); 7535 7536 /* If the controller has AMT, do not set DRV_LOAD until the interface 7537 * is up. For all other cases, let the f/w know that the h/w is now 7538 * under the control of the driver. 7539 */ 7540 if (!(adapter->flags & FLAG_HAS_AMT)) 7541 e1000e_get_hw_control(adapter); 7542 7543 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7544 err = register_netdev(netdev); 7545 if (err) 7546 goto err_register; 7547 7548 /* carrier off reporting is important to ethtool even BEFORE open */ 7549 netif_carrier_off(netdev); 7550 7551 e1000_print_device_info(adapter); 7552 7553 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP); 7554 7555 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp) 7556 pm_runtime_put_noidle(&pdev->dev); 7557 7558 return 0; 7559 7560 err_register: 7561 if (!(adapter->flags & FLAG_HAS_AMT)) 7562 e1000e_release_hw_control(adapter); 7563 err_eeprom: 7564 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7565 e1000_phy_hw_reset(&adapter->hw); 7566 err_hw_init: 7567 kfree(adapter->tx_ring); 7568 kfree(adapter->rx_ring); 7569 err_sw_init: 7570 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7571 iounmap(adapter->hw.flash_address); 7572 e1000e_reset_interrupt_capability(adapter); 7573 err_flashmap: 7574 iounmap(adapter->hw.hw_addr); 7575 err_ioremap: 7576 free_netdev(netdev); 7577 err_alloc_etherdev: 7578 pci_release_mem_regions(pdev); 7579 err_pci_reg: 7580 err_dma: 7581 pci_disable_device(pdev); 7582 return err; 7583 } 7584 7585 /** 7586 * e1000_remove - Device Removal Routine 7587 * @pdev: PCI device information struct 7588 * 7589 * e1000_remove is called by the PCI subsystem to alert the driver 7590 * that it should release a PCI device. The could be caused by a 7591 * Hot-Plug event, or because the driver is going to be removed from 7592 * memory. 7593 **/ 7594 static void e1000_remove(struct pci_dev *pdev) 7595 { 7596 struct net_device *netdev = pci_get_drvdata(pdev); 7597 struct e1000_adapter *adapter = netdev_priv(netdev); 7598 7599 e1000e_ptp_remove(adapter); 7600 7601 /* The timers may be rescheduled, so explicitly disable them 7602 * from being rescheduled. 7603 */ 7604 set_bit(__E1000_DOWN, &adapter->state); 7605 del_timer_sync(&adapter->watchdog_timer); 7606 del_timer_sync(&adapter->phy_info_timer); 7607 7608 cancel_work_sync(&adapter->reset_task); 7609 cancel_work_sync(&adapter->watchdog_task); 7610 cancel_work_sync(&adapter->downshift_task); 7611 cancel_work_sync(&adapter->update_phy_task); 7612 cancel_work_sync(&adapter->print_hang_task); 7613 7614 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7615 cancel_work_sync(&adapter->tx_hwtstamp_work); 7616 if (adapter->tx_hwtstamp_skb) { 7617 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7618 adapter->tx_hwtstamp_skb = NULL; 7619 } 7620 } 7621 7622 unregister_netdev(netdev); 7623 7624 if (pci_dev_run_wake(pdev)) 7625 pm_runtime_get_noresume(&pdev->dev); 7626 7627 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7628 * would have already happened in close and is redundant. 7629 */ 7630 e1000e_release_hw_control(adapter); 7631 7632 e1000e_reset_interrupt_capability(adapter); 7633 kfree(adapter->tx_ring); 7634 kfree(adapter->rx_ring); 7635 7636 iounmap(adapter->hw.hw_addr); 7637 if ((adapter->hw.flash_address) && 7638 (adapter->hw.mac.type < e1000_pch_spt)) 7639 iounmap(adapter->hw.flash_address); 7640 pci_release_mem_regions(pdev); 7641 7642 free_netdev(netdev); 7643 7644 /* AER disable */ 7645 pci_disable_pcie_error_reporting(pdev); 7646 7647 pci_disable_device(pdev); 7648 } 7649 7650 /* PCI Error Recovery (ERS) */ 7651 static const struct pci_error_handlers e1000_err_handler = { 7652 .error_detected = e1000_io_error_detected, 7653 .slot_reset = e1000_io_slot_reset, 7654 .resume = e1000_io_resume, 7655 }; 7656 7657 static const struct pci_device_id e1000_pci_tbl[] = { 7658 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7659 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7660 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7661 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7662 board_82571 }, 7663 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7664 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7665 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7666 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7667 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7668 7669 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7670 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7671 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7672 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7673 7674 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7675 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7676 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7677 7678 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7679 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7680 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7681 7682 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7683 board_80003es2lan }, 7684 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7685 board_80003es2lan }, 7686 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7687 board_80003es2lan }, 7688 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7689 board_80003es2lan }, 7690 7691 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7692 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7693 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7694 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7695 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7696 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7697 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7698 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7699 7700 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7701 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7702 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7703 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7704 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7705 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7706 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7707 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7708 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7709 7710 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7711 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7712 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7713 7714 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7715 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7716 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7717 7718 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7719 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7720 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7721 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7722 7723 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7724 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7725 7726 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7727 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7728 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7729 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7730 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7731 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7732 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7733 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7734 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7735 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7736 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7737 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7738 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7739 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7740 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7741 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7742 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7743 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7744 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7745 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7746 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7747 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7748 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7749 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7750 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7751 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7752 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7753 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, 7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, 7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, 7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, 7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, 7762 7763 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7764 }; 7765 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7766 7767 static const struct dev_pm_ops e1000_pm_ops = { 7768 #ifdef CONFIG_PM_SLEEP 7769 .suspend = e1000e_pm_suspend, 7770 .resume = e1000e_pm_resume, 7771 .freeze = e1000e_pm_freeze, 7772 .thaw = e1000e_pm_thaw, 7773 .poweroff = e1000e_pm_suspend, 7774 .restore = e1000e_pm_resume, 7775 #endif 7776 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7777 e1000e_pm_runtime_idle) 7778 }; 7779 7780 /* PCI Device API Driver */ 7781 static struct pci_driver e1000_driver = { 7782 .name = e1000e_driver_name, 7783 .id_table = e1000_pci_tbl, 7784 .probe = e1000_probe, 7785 .remove = e1000_remove, 7786 .driver = { 7787 .pm = &e1000_pm_ops, 7788 }, 7789 .shutdown = e1000_shutdown, 7790 .err_handler = &e1000_err_handler 7791 }; 7792 7793 /** 7794 * e1000_init_module - Driver Registration Routine 7795 * 7796 * e1000_init_module is the first routine called when the driver is 7797 * loaded. All it does is register with the PCI subsystem. 7798 **/ 7799 static int __init e1000_init_module(void) 7800 { 7801 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7802 e1000e_driver_version); 7803 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7804 7805 return pci_register_driver(&e1000_driver); 7806 } 7807 module_init(e1000_init_module); 7808 7809 /** 7810 * e1000_exit_module - Driver Exit Cleanup Routine 7811 * 7812 * e1000_exit_module is called just before the driver is removed 7813 * from memory. 7814 **/ 7815 static void __exit e1000_exit_module(void) 7816 { 7817 pci_unregister_driver(&e1000_driver); 7818 } 7819 module_exit(e1000_exit_module); 7820 7821 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7822 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7823 MODULE_LICENSE("GPL v2"); 7824 MODULE_VERSION(DRV_VERSION); 7825 7826 /* netdev.c */ 7827