1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/module.h> 25 #include <linux/types.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/vmalloc.h> 29 #include <linux/pagemap.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/interrupt.h> 33 #include <linux/tcp.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/cpu.h> 41 #include <linux/smp.h> 42 #include <linux/pm_qos.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/aer.h> 45 #include <linux/prefetch.h> 46 47 #include "e1000.h" 48 49 #define DRV_EXTRAVERSION "-k" 50 51 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 52 char e1000e_driver_name[] = "e1000e"; 53 const char e1000e_driver_version[] = DRV_VERSION; 54 55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 56 static int debug = -1; 57 module_param(debug, int, 0); 58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 59 60 static const struct e1000_info *e1000_info_tbl[] = { 61 [board_82571] = &e1000_82571_info, 62 [board_82572] = &e1000_82572_info, 63 [board_82573] = &e1000_82573_info, 64 [board_82574] = &e1000_82574_info, 65 [board_82583] = &e1000_82583_info, 66 [board_80003es2lan] = &e1000_es2_info, 67 [board_ich8lan] = &e1000_ich8_info, 68 [board_ich9lan] = &e1000_ich9_info, 69 [board_ich10lan] = &e1000_ich10_info, 70 [board_pchlan] = &e1000_pch_info, 71 [board_pch2lan] = &e1000_pch2_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info, 73 [board_pch_spt] = &e1000_pch_spt_info, 74 [board_pch_cnp] = &e1000_pch_cnp_info, 75 }; 76 77 struct e1000_reg_info { 78 u32 ofs; 79 char *name; 80 }; 81 82 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 83 /* General Registers */ 84 {E1000_CTRL, "CTRL"}, 85 {E1000_STATUS, "STATUS"}, 86 {E1000_CTRL_EXT, "CTRL_EXT"}, 87 88 /* Interrupt Registers */ 89 {E1000_ICR, "ICR"}, 90 91 /* Rx Registers */ 92 {E1000_RCTL, "RCTL"}, 93 {E1000_RDLEN(0), "RDLEN"}, 94 {E1000_RDH(0), "RDH"}, 95 {E1000_RDT(0), "RDT"}, 96 {E1000_RDTR, "RDTR"}, 97 {E1000_RXDCTL(0), "RXDCTL"}, 98 {E1000_ERT, "ERT"}, 99 {E1000_RDBAL(0), "RDBAL"}, 100 {E1000_RDBAH(0), "RDBAH"}, 101 {E1000_RDFH, "RDFH"}, 102 {E1000_RDFT, "RDFT"}, 103 {E1000_RDFHS, "RDFHS"}, 104 {E1000_RDFTS, "RDFTS"}, 105 {E1000_RDFPC, "RDFPC"}, 106 107 /* Tx Registers */ 108 {E1000_TCTL, "TCTL"}, 109 {E1000_TDBAL(0), "TDBAL"}, 110 {E1000_TDBAH(0), "TDBAH"}, 111 {E1000_TDLEN(0), "TDLEN"}, 112 {E1000_TDH(0), "TDH"}, 113 {E1000_TDT(0), "TDT"}, 114 {E1000_TIDV, "TIDV"}, 115 {E1000_TXDCTL(0), "TXDCTL"}, 116 {E1000_TADV, "TADV"}, 117 {E1000_TARC(0), "TARC"}, 118 {E1000_TDFH, "TDFH"}, 119 {E1000_TDFT, "TDFT"}, 120 {E1000_TDFHS, "TDFHS"}, 121 {E1000_TDFTS, "TDFTS"}, 122 {E1000_TDFPC, "TDFPC"}, 123 124 /* List Terminator */ 125 {0, NULL} 126 }; 127 128 /** 129 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 130 * @hw: pointer to the HW structure 131 * 132 * When updating the MAC CSR registers, the Manageability Engine (ME) could 133 * be accessing the registers at the same time. Normally, this is handled in 134 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 135 * accesses later than it should which could result in the register to have 136 * an incorrect value. Workaround this by checking the FWSM register which 137 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 138 * and try again a number of times. 139 **/ 140 s32 __ew32_prepare(struct e1000_hw *hw) 141 { 142 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 143 144 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 145 udelay(50); 146 147 return i; 148 } 149 150 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 151 { 152 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 153 __ew32_prepare(hw); 154 155 writel(val, hw->hw_addr + reg); 156 } 157 158 /** 159 * e1000_regdump - register printout routine 160 * @hw: pointer to the HW structure 161 * @reginfo: pointer to the register info table 162 **/ 163 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 164 { 165 int n = 0; 166 char rname[16]; 167 u32 regs[8]; 168 169 switch (reginfo->ofs) { 170 case E1000_RXDCTL(0): 171 for (n = 0; n < 2; n++) 172 regs[n] = __er32(hw, E1000_RXDCTL(n)); 173 break; 174 case E1000_TXDCTL(0): 175 for (n = 0; n < 2; n++) 176 regs[n] = __er32(hw, E1000_TXDCTL(n)); 177 break; 178 case E1000_TARC(0): 179 for (n = 0; n < 2; n++) 180 regs[n] = __er32(hw, E1000_TARC(n)); 181 break; 182 default: 183 pr_info("%-15s %08x\n", 184 reginfo->name, __er32(hw, reginfo->ofs)); 185 return; 186 } 187 188 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 189 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 190 } 191 192 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 193 struct e1000_buffer *bi) 194 { 195 int i; 196 struct e1000_ps_page *ps_page; 197 198 for (i = 0; i < adapter->rx_ps_pages; i++) { 199 ps_page = &bi->ps_pages[i]; 200 201 if (ps_page->page) { 202 pr_info("packet dump for ps_page %d:\n", i); 203 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 204 16, 1, page_address(ps_page->page), 205 PAGE_SIZE, true); 206 } 207 } 208 } 209 210 /** 211 * e1000e_dump - Print registers, Tx-ring and Rx-ring 212 * @adapter: board private structure 213 **/ 214 static void e1000e_dump(struct e1000_adapter *adapter) 215 { 216 struct net_device *netdev = adapter->netdev; 217 struct e1000_hw *hw = &adapter->hw; 218 struct e1000_reg_info *reginfo; 219 struct e1000_ring *tx_ring = adapter->tx_ring; 220 struct e1000_tx_desc *tx_desc; 221 struct my_u0 { 222 __le64 a; 223 __le64 b; 224 } *u0; 225 struct e1000_buffer *buffer_info; 226 struct e1000_ring *rx_ring = adapter->rx_ring; 227 union e1000_rx_desc_packet_split *rx_desc_ps; 228 union e1000_rx_desc_extended *rx_desc; 229 struct my_u1 { 230 __le64 a; 231 __le64 b; 232 __le64 c; 233 __le64 d; 234 } *u1; 235 u32 staterr; 236 int i = 0; 237 238 if (!netif_msg_hw(adapter)) 239 return; 240 241 /* Print netdevice Info */ 242 if (netdev) { 243 dev_info(&adapter->pdev->dev, "Net device Info\n"); 244 pr_info("Device Name state trans_start\n"); 245 pr_info("%-15s %016lX %016lX\n", netdev->name, 246 netdev->state, dev_trans_start(netdev)); 247 } 248 249 /* Print Registers */ 250 dev_info(&adapter->pdev->dev, "Register Dump\n"); 251 pr_info(" Register Name Value\n"); 252 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 253 reginfo->name; reginfo++) { 254 e1000_regdump(hw, reginfo); 255 } 256 257 /* Print Tx Ring Summary */ 258 if (!netdev || !netif_running(netdev)) 259 return; 260 261 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 262 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 263 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 264 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 265 0, tx_ring->next_to_use, tx_ring->next_to_clean, 266 (unsigned long long)buffer_info->dma, 267 buffer_info->length, 268 buffer_info->next_to_watch, 269 (unsigned long long)buffer_info->time_stamp); 270 271 /* Print Tx Ring */ 272 if (!netif_msg_tx_done(adapter)) 273 goto rx_ring_summary; 274 275 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 276 277 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 278 * 279 * Legacy Transmit Descriptor 280 * +--------------------------------------------------------------+ 281 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 282 * +--------------------------------------------------------------+ 283 * 8 | Special | CSS | Status | CMD | CSO | Length | 284 * +--------------------------------------------------------------+ 285 * 63 48 47 36 35 32 31 24 23 16 15 0 286 * 287 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 288 * 63 48 47 40 39 32 31 16 15 8 7 0 289 * +----------------------------------------------------------------+ 290 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 291 * +----------------------------------------------------------------+ 292 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 293 * +----------------------------------------------------------------+ 294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 295 * 296 * Extended Data Descriptor (DTYP=0x1) 297 * +----------------------------------------------------------------+ 298 * 0 | Buffer Address [63:0] | 299 * +----------------------------------------------------------------+ 300 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 301 * +----------------------------------------------------------------+ 302 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 303 */ 304 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 305 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 306 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 307 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 308 const char *next_desc; 309 tx_desc = E1000_TX_DESC(*tx_ring, i); 310 buffer_info = &tx_ring->buffer_info[i]; 311 u0 = (struct my_u0 *)tx_desc; 312 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 313 next_desc = " NTC/U"; 314 else if (i == tx_ring->next_to_use) 315 next_desc = " NTU"; 316 else if (i == tx_ring->next_to_clean) 317 next_desc = " NTC"; 318 else 319 next_desc = ""; 320 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 321 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 322 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 323 i, 324 (unsigned long long)le64_to_cpu(u0->a), 325 (unsigned long long)le64_to_cpu(u0->b), 326 (unsigned long long)buffer_info->dma, 327 buffer_info->length, buffer_info->next_to_watch, 328 (unsigned long long)buffer_info->time_stamp, 329 buffer_info->skb, next_desc); 330 331 if (netif_msg_pktdata(adapter) && buffer_info->skb) 332 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 333 16, 1, buffer_info->skb->data, 334 buffer_info->skb->len, true); 335 } 336 337 /* Print Rx Ring Summary */ 338 rx_ring_summary: 339 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 340 pr_info("Queue [NTU] [NTC]\n"); 341 pr_info(" %5d %5X %5X\n", 342 0, rx_ring->next_to_use, rx_ring->next_to_clean); 343 344 /* Print Rx Ring */ 345 if (!netif_msg_rx_status(adapter)) 346 return; 347 348 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 349 switch (adapter->rx_ps_pages) { 350 case 1: 351 case 2: 352 case 3: 353 /* [Extended] Packet Split Receive Descriptor Format 354 * 355 * +-----------------------------------------------------+ 356 * 0 | Buffer Address 0 [63:0] | 357 * +-----------------------------------------------------+ 358 * 8 | Buffer Address 1 [63:0] | 359 * +-----------------------------------------------------+ 360 * 16 | Buffer Address 2 [63:0] | 361 * +-----------------------------------------------------+ 362 * 24 | Buffer Address 3 [63:0] | 363 * +-----------------------------------------------------+ 364 */ 365 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 366 /* [Extended] Receive Descriptor (Write-Back) Format 367 * 368 * 63 48 47 32 31 13 12 8 7 4 3 0 369 * +------------------------------------------------------+ 370 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 371 * | Checksum | Ident | | Queue | | Type | 372 * +------------------------------------------------------+ 373 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 374 * +------------------------------------------------------+ 375 * 63 48 47 32 31 20 19 0 376 */ 377 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 378 for (i = 0; i < rx_ring->count; i++) { 379 const char *next_desc; 380 buffer_info = &rx_ring->buffer_info[i]; 381 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 382 u1 = (struct my_u1 *)rx_desc_ps; 383 staterr = 384 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 385 386 if (i == rx_ring->next_to_use) 387 next_desc = " NTU"; 388 else if (i == rx_ring->next_to_clean) 389 next_desc = " NTC"; 390 else 391 next_desc = ""; 392 393 if (staterr & E1000_RXD_STAT_DD) { 394 /* Descriptor Done */ 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 396 "RWB", i, 397 (unsigned long long)le64_to_cpu(u1->a), 398 (unsigned long long)le64_to_cpu(u1->b), 399 (unsigned long long)le64_to_cpu(u1->c), 400 (unsigned long long)le64_to_cpu(u1->d), 401 buffer_info->skb, next_desc); 402 } else { 403 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 404 "R ", i, 405 (unsigned long long)le64_to_cpu(u1->a), 406 (unsigned long long)le64_to_cpu(u1->b), 407 (unsigned long long)le64_to_cpu(u1->c), 408 (unsigned long long)le64_to_cpu(u1->d), 409 (unsigned long long)buffer_info->dma, 410 buffer_info->skb, next_desc); 411 412 if (netif_msg_pktdata(adapter)) 413 e1000e_dump_ps_pages(adapter, 414 buffer_info); 415 } 416 } 417 break; 418 default: 419 case 0: 420 /* Extended Receive Descriptor (Read) Format 421 * 422 * +-----------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +-----------------------------------------------------+ 425 * 8 | Reserved | 426 * +-----------------------------------------------------+ 427 */ 428 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 429 /* Extended Receive Descriptor (Write-Back) Format 430 * 431 * 63 48 47 32 31 24 23 4 3 0 432 * +------------------------------------------------------+ 433 * | RSS Hash | | | | 434 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 435 * | Packet | IP | | | Type | 436 * | Checksum | Ident | | | | 437 * +------------------------------------------------------+ 438 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 439 * +------------------------------------------------------+ 440 * 63 48 47 32 31 20 19 0 441 */ 442 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 443 444 for (i = 0; i < rx_ring->count; i++) { 445 const char *next_desc; 446 447 buffer_info = &rx_ring->buffer_info[i]; 448 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 449 u1 = (struct my_u1 *)rx_desc; 450 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 451 452 if (i == rx_ring->next_to_use) 453 next_desc = " NTU"; 454 else if (i == rx_ring->next_to_clean) 455 next_desc = " NTC"; 456 else 457 next_desc = ""; 458 459 if (staterr & E1000_RXD_STAT_DD) { 460 /* Descriptor Done */ 461 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 462 "RWB", i, 463 (unsigned long long)le64_to_cpu(u1->a), 464 (unsigned long long)le64_to_cpu(u1->b), 465 buffer_info->skb, next_desc); 466 } else { 467 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 468 "R ", i, 469 (unsigned long long)le64_to_cpu(u1->a), 470 (unsigned long long)le64_to_cpu(u1->b), 471 (unsigned long long)buffer_info->dma, 472 buffer_info->skb, next_desc); 473 474 if (netif_msg_pktdata(adapter) && 475 buffer_info->skb) 476 print_hex_dump(KERN_INFO, "", 477 DUMP_PREFIX_ADDRESS, 16, 478 1, 479 buffer_info->skb->data, 480 adapter->rx_buffer_len, 481 true); 482 } 483 } 484 } 485 } 486 487 /** 488 * e1000_desc_unused - calculate if we have unused descriptors 489 **/ 490 static int e1000_desc_unused(struct e1000_ring *ring) 491 { 492 if (ring->next_to_clean > ring->next_to_use) 493 return ring->next_to_clean - ring->next_to_use - 1; 494 495 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 496 } 497 498 /** 499 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 500 * @adapter: board private structure 501 * @hwtstamps: time stamp structure to update 502 * @systim: unsigned 64bit system time value. 503 * 504 * Convert the system time value stored in the RX/TXSTMP registers into a 505 * hwtstamp which can be used by the upper level time stamping functions. 506 * 507 * The 'systim_lock' spinlock is used to protect the consistency of the 508 * system time value. This is needed because reading the 64 bit time 509 * value involves reading two 32 bit registers. The first read latches the 510 * value. 511 **/ 512 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 513 struct skb_shared_hwtstamps *hwtstamps, 514 u64 systim) 515 { 516 u64 ns; 517 unsigned long flags; 518 519 spin_lock_irqsave(&adapter->systim_lock, flags); 520 ns = timecounter_cyc2time(&adapter->tc, systim); 521 spin_unlock_irqrestore(&adapter->systim_lock, flags); 522 523 memset(hwtstamps, 0, sizeof(*hwtstamps)); 524 hwtstamps->hwtstamp = ns_to_ktime(ns); 525 } 526 527 /** 528 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 529 * @adapter: board private structure 530 * @status: descriptor extended error and status field 531 * @skb: particular skb to include time stamp 532 * 533 * If the time stamp is valid, convert it into the timecounter ns value 534 * and store that result into the shhwtstamps structure which is passed 535 * up the network stack. 536 **/ 537 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 538 struct sk_buff *skb) 539 { 540 struct e1000_hw *hw = &adapter->hw; 541 u64 rxstmp; 542 543 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 544 !(status & E1000_RXDEXT_STATERR_TST) || 545 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 546 return; 547 548 /* The Rx time stamp registers contain the time stamp. No other 549 * received packet will be time stamped until the Rx time stamp 550 * registers are read. Because only one packet can be time stamped 551 * at a time, the register values must belong to this packet and 552 * therefore none of the other additional attributes need to be 553 * compared. 554 */ 555 rxstmp = (u64)er32(RXSTMPL); 556 rxstmp |= (u64)er32(RXSTMPH) << 32; 557 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 558 559 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 560 } 561 562 /** 563 * e1000_receive_skb - helper function to handle Rx indications 564 * @adapter: board private structure 565 * @staterr: descriptor extended error and status field as written by hardware 566 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 567 * @skb: pointer to sk_buff to be indicated to stack 568 **/ 569 static void e1000_receive_skb(struct e1000_adapter *adapter, 570 struct net_device *netdev, struct sk_buff *skb, 571 u32 staterr, __le16 vlan) 572 { 573 u16 tag = le16_to_cpu(vlan); 574 575 e1000e_rx_hwtstamp(adapter, staterr, skb); 576 577 skb->protocol = eth_type_trans(skb, netdev); 578 579 if (staterr & E1000_RXD_STAT_VP) 580 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 581 582 napi_gro_receive(&adapter->napi, skb); 583 } 584 585 /** 586 * e1000_rx_checksum - Receive Checksum Offload 587 * @adapter: board private structure 588 * @status_err: receive descriptor status and error fields 589 * @csum: receive descriptor csum field 590 * @sk_buff: socket buffer with received data 591 **/ 592 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 593 struct sk_buff *skb) 594 { 595 u16 status = (u16)status_err; 596 u8 errors = (u8)(status_err >> 24); 597 598 skb_checksum_none_assert(skb); 599 600 /* Rx checksum disabled */ 601 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 602 return; 603 604 /* Ignore Checksum bit is set */ 605 if (status & E1000_RXD_STAT_IXSM) 606 return; 607 608 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 609 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 610 /* let the stack verify checksum errors */ 611 adapter->hw_csum_err++; 612 return; 613 } 614 615 /* TCP/UDP Checksum has not been calculated */ 616 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 617 return; 618 619 /* It must be a TCP or UDP packet with a valid checksum */ 620 skb->ip_summed = CHECKSUM_UNNECESSARY; 621 adapter->hw_csum_good++; 622 } 623 624 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 625 { 626 struct e1000_adapter *adapter = rx_ring->adapter; 627 struct e1000_hw *hw = &adapter->hw; 628 s32 ret_val = __ew32_prepare(hw); 629 630 writel(i, rx_ring->tail); 631 632 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 633 u32 rctl = er32(RCTL); 634 635 ew32(RCTL, rctl & ~E1000_RCTL_EN); 636 e_err("ME firmware caused invalid RDT - resetting\n"); 637 schedule_work(&adapter->reset_task); 638 } 639 } 640 641 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 642 { 643 struct e1000_adapter *adapter = tx_ring->adapter; 644 struct e1000_hw *hw = &adapter->hw; 645 s32 ret_val = __ew32_prepare(hw); 646 647 writel(i, tx_ring->tail); 648 649 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 650 u32 tctl = er32(TCTL); 651 652 ew32(TCTL, tctl & ~E1000_TCTL_EN); 653 e_err("ME firmware caused invalid TDT - resetting\n"); 654 schedule_work(&adapter->reset_task); 655 } 656 } 657 658 /** 659 * e1000_alloc_rx_buffers - Replace used receive buffers 660 * @rx_ring: Rx descriptor ring 661 **/ 662 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 663 int cleaned_count, gfp_t gfp) 664 { 665 struct e1000_adapter *adapter = rx_ring->adapter; 666 struct net_device *netdev = adapter->netdev; 667 struct pci_dev *pdev = adapter->pdev; 668 union e1000_rx_desc_extended *rx_desc; 669 struct e1000_buffer *buffer_info; 670 struct sk_buff *skb; 671 unsigned int i; 672 unsigned int bufsz = adapter->rx_buffer_len; 673 674 i = rx_ring->next_to_use; 675 buffer_info = &rx_ring->buffer_info[i]; 676 677 while (cleaned_count--) { 678 skb = buffer_info->skb; 679 if (skb) { 680 skb_trim(skb, 0); 681 goto map_skb; 682 } 683 684 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 685 if (!skb) { 686 /* Better luck next round */ 687 adapter->alloc_rx_buff_failed++; 688 break; 689 } 690 691 buffer_info->skb = skb; 692 map_skb: 693 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 694 adapter->rx_buffer_len, 695 DMA_FROM_DEVICE); 696 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 697 dev_err(&pdev->dev, "Rx DMA map failed\n"); 698 adapter->rx_dma_failed++; 699 break; 700 } 701 702 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 703 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 704 705 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 706 /* Force memory writes to complete before letting h/w 707 * know there are new descriptors to fetch. (Only 708 * applicable for weak-ordered memory model archs, 709 * such as IA-64). 710 */ 711 wmb(); 712 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 713 e1000e_update_rdt_wa(rx_ring, i); 714 else 715 writel(i, rx_ring->tail); 716 } 717 i++; 718 if (i == rx_ring->count) 719 i = 0; 720 buffer_info = &rx_ring->buffer_info[i]; 721 } 722 723 rx_ring->next_to_use = i; 724 } 725 726 /** 727 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 728 * @rx_ring: Rx descriptor ring 729 **/ 730 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 731 int cleaned_count, gfp_t gfp) 732 { 733 struct e1000_adapter *adapter = rx_ring->adapter; 734 struct net_device *netdev = adapter->netdev; 735 struct pci_dev *pdev = adapter->pdev; 736 union e1000_rx_desc_packet_split *rx_desc; 737 struct e1000_buffer *buffer_info; 738 struct e1000_ps_page *ps_page; 739 struct sk_buff *skb; 740 unsigned int i, j; 741 742 i = rx_ring->next_to_use; 743 buffer_info = &rx_ring->buffer_info[i]; 744 745 while (cleaned_count--) { 746 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 747 748 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 749 ps_page = &buffer_info->ps_pages[j]; 750 if (j >= adapter->rx_ps_pages) { 751 /* all unused desc entries get hw null ptr */ 752 rx_desc->read.buffer_addr[j + 1] = 753 ~cpu_to_le64(0); 754 continue; 755 } 756 if (!ps_page->page) { 757 ps_page->page = alloc_page(gfp); 758 if (!ps_page->page) { 759 adapter->alloc_rx_buff_failed++; 760 goto no_buffers; 761 } 762 ps_page->dma = dma_map_page(&pdev->dev, 763 ps_page->page, 764 0, PAGE_SIZE, 765 DMA_FROM_DEVICE); 766 if (dma_mapping_error(&pdev->dev, 767 ps_page->dma)) { 768 dev_err(&adapter->pdev->dev, 769 "Rx DMA page map failed\n"); 770 adapter->rx_dma_failed++; 771 goto no_buffers; 772 } 773 } 774 /* Refresh the desc even if buffer_addrs 775 * didn't change because each write-back 776 * erases this info. 777 */ 778 rx_desc->read.buffer_addr[j + 1] = 779 cpu_to_le64(ps_page->dma); 780 } 781 782 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 783 gfp); 784 785 if (!skb) { 786 adapter->alloc_rx_buff_failed++; 787 break; 788 } 789 790 buffer_info->skb = skb; 791 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 792 adapter->rx_ps_bsize0, 793 DMA_FROM_DEVICE); 794 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 795 dev_err(&pdev->dev, "Rx DMA map failed\n"); 796 adapter->rx_dma_failed++; 797 /* cleanup skb */ 798 dev_kfree_skb_any(skb); 799 buffer_info->skb = NULL; 800 break; 801 } 802 803 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 804 805 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 806 /* Force memory writes to complete before letting h/w 807 * know there are new descriptors to fetch. (Only 808 * applicable for weak-ordered memory model archs, 809 * such as IA-64). 810 */ 811 wmb(); 812 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 813 e1000e_update_rdt_wa(rx_ring, i << 1); 814 else 815 writel(i << 1, rx_ring->tail); 816 } 817 818 i++; 819 if (i == rx_ring->count) 820 i = 0; 821 buffer_info = &rx_ring->buffer_info[i]; 822 } 823 824 no_buffers: 825 rx_ring->next_to_use = i; 826 } 827 828 /** 829 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 830 * @rx_ring: Rx descriptor ring 831 * @cleaned_count: number of buffers to allocate this pass 832 **/ 833 834 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 835 int cleaned_count, gfp_t gfp) 836 { 837 struct e1000_adapter *adapter = rx_ring->adapter; 838 struct net_device *netdev = adapter->netdev; 839 struct pci_dev *pdev = adapter->pdev; 840 union e1000_rx_desc_extended *rx_desc; 841 struct e1000_buffer *buffer_info; 842 struct sk_buff *skb; 843 unsigned int i; 844 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 845 846 i = rx_ring->next_to_use; 847 buffer_info = &rx_ring->buffer_info[i]; 848 849 while (cleaned_count--) { 850 skb = buffer_info->skb; 851 if (skb) { 852 skb_trim(skb, 0); 853 goto check_page; 854 } 855 856 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 857 if (unlikely(!skb)) { 858 /* Better luck next round */ 859 adapter->alloc_rx_buff_failed++; 860 break; 861 } 862 863 buffer_info->skb = skb; 864 check_page: 865 /* allocate a new page if necessary */ 866 if (!buffer_info->page) { 867 buffer_info->page = alloc_page(gfp); 868 if (unlikely(!buffer_info->page)) { 869 adapter->alloc_rx_buff_failed++; 870 break; 871 } 872 } 873 874 if (!buffer_info->dma) { 875 buffer_info->dma = dma_map_page(&pdev->dev, 876 buffer_info->page, 0, 877 PAGE_SIZE, 878 DMA_FROM_DEVICE); 879 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 880 adapter->alloc_rx_buff_failed++; 881 break; 882 } 883 } 884 885 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 886 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 887 888 if (unlikely(++i == rx_ring->count)) 889 i = 0; 890 buffer_info = &rx_ring->buffer_info[i]; 891 } 892 893 if (likely(rx_ring->next_to_use != i)) { 894 rx_ring->next_to_use = i; 895 if (unlikely(i-- == 0)) 896 i = (rx_ring->count - 1); 897 898 /* Force memory writes to complete before letting h/w 899 * know there are new descriptors to fetch. (Only 900 * applicable for weak-ordered memory model archs, 901 * such as IA-64). 902 */ 903 wmb(); 904 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 905 e1000e_update_rdt_wa(rx_ring, i); 906 else 907 writel(i, rx_ring->tail); 908 } 909 } 910 911 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 912 struct sk_buff *skb) 913 { 914 if (netdev->features & NETIF_F_RXHASH) 915 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 916 } 917 918 /** 919 * e1000_clean_rx_irq - Send received data up the network stack 920 * @rx_ring: Rx descriptor ring 921 * 922 * the return value indicates whether actual cleaning was done, there 923 * is no guarantee that everything was cleaned 924 **/ 925 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 926 int work_to_do) 927 { 928 struct e1000_adapter *adapter = rx_ring->adapter; 929 struct net_device *netdev = adapter->netdev; 930 struct pci_dev *pdev = adapter->pdev; 931 struct e1000_hw *hw = &adapter->hw; 932 union e1000_rx_desc_extended *rx_desc, *next_rxd; 933 struct e1000_buffer *buffer_info, *next_buffer; 934 u32 length, staterr; 935 unsigned int i; 936 int cleaned_count = 0; 937 bool cleaned = false; 938 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 939 940 i = rx_ring->next_to_clean; 941 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 942 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 943 buffer_info = &rx_ring->buffer_info[i]; 944 945 while (staterr & E1000_RXD_STAT_DD) { 946 struct sk_buff *skb; 947 948 if (*work_done >= work_to_do) 949 break; 950 (*work_done)++; 951 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 952 953 skb = buffer_info->skb; 954 buffer_info->skb = NULL; 955 956 prefetch(skb->data - NET_IP_ALIGN); 957 958 i++; 959 if (i == rx_ring->count) 960 i = 0; 961 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 962 prefetch(next_rxd); 963 964 next_buffer = &rx_ring->buffer_info[i]; 965 966 cleaned = true; 967 cleaned_count++; 968 dma_unmap_single(&pdev->dev, buffer_info->dma, 969 adapter->rx_buffer_len, DMA_FROM_DEVICE); 970 buffer_info->dma = 0; 971 972 length = le16_to_cpu(rx_desc->wb.upper.length); 973 974 /* !EOP means multiple descriptors were used to store a single 975 * packet, if that's the case we need to toss it. In fact, we 976 * need to toss every packet with the EOP bit clear and the 977 * next frame that _does_ have the EOP bit set, as it is by 978 * definition only a frame fragment 979 */ 980 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 981 adapter->flags2 |= FLAG2_IS_DISCARDING; 982 983 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 984 /* All receives must fit into a single buffer */ 985 e_dbg("Receive packet consumed multiple buffers\n"); 986 /* recycle */ 987 buffer_info->skb = skb; 988 if (staterr & E1000_RXD_STAT_EOP) 989 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 990 goto next_desc; 991 } 992 993 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 994 !(netdev->features & NETIF_F_RXALL))) { 995 /* recycle */ 996 buffer_info->skb = skb; 997 goto next_desc; 998 } 999 1000 /* adjust length to remove Ethernet CRC */ 1001 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1002 /* If configured to store CRC, don't subtract FCS, 1003 * but keep the FCS bytes out of the total_rx_bytes 1004 * counter 1005 */ 1006 if (netdev->features & NETIF_F_RXFCS) 1007 total_rx_bytes -= 4; 1008 else 1009 length -= 4; 1010 } 1011 1012 total_rx_bytes += length; 1013 total_rx_packets++; 1014 1015 /* code added for copybreak, this should improve 1016 * performance for small packets with large amounts 1017 * of reassembly being done in the stack 1018 */ 1019 if (length < copybreak) { 1020 struct sk_buff *new_skb = 1021 napi_alloc_skb(&adapter->napi, length); 1022 if (new_skb) { 1023 skb_copy_to_linear_data_offset(new_skb, 1024 -NET_IP_ALIGN, 1025 (skb->data - 1026 NET_IP_ALIGN), 1027 (length + 1028 NET_IP_ALIGN)); 1029 /* save the skb in buffer_info as good */ 1030 buffer_info->skb = skb; 1031 skb = new_skb; 1032 } 1033 /* else just continue with the old one */ 1034 } 1035 /* end copybreak code */ 1036 skb_put(skb, length); 1037 1038 /* Receive Checksum Offload */ 1039 e1000_rx_checksum(adapter, staterr, skb); 1040 1041 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1042 1043 e1000_receive_skb(adapter, netdev, skb, staterr, 1044 rx_desc->wb.upper.vlan); 1045 1046 next_desc: 1047 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1048 1049 /* return some buffers to hardware, one at a time is too slow */ 1050 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1051 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1052 GFP_ATOMIC); 1053 cleaned_count = 0; 1054 } 1055 1056 /* use prefetched values */ 1057 rx_desc = next_rxd; 1058 buffer_info = next_buffer; 1059 1060 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1061 } 1062 rx_ring->next_to_clean = i; 1063 1064 cleaned_count = e1000_desc_unused(rx_ring); 1065 if (cleaned_count) 1066 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1067 1068 adapter->total_rx_bytes += total_rx_bytes; 1069 adapter->total_rx_packets += total_rx_packets; 1070 return cleaned; 1071 } 1072 1073 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1074 struct e1000_buffer *buffer_info) 1075 { 1076 struct e1000_adapter *adapter = tx_ring->adapter; 1077 1078 if (buffer_info->dma) { 1079 if (buffer_info->mapped_as_page) 1080 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1081 buffer_info->length, DMA_TO_DEVICE); 1082 else 1083 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1084 buffer_info->length, DMA_TO_DEVICE); 1085 buffer_info->dma = 0; 1086 } 1087 if (buffer_info->skb) { 1088 dev_kfree_skb_any(buffer_info->skb); 1089 buffer_info->skb = NULL; 1090 } 1091 buffer_info->time_stamp = 0; 1092 } 1093 1094 static void e1000_print_hw_hang(struct work_struct *work) 1095 { 1096 struct e1000_adapter *adapter = container_of(work, 1097 struct e1000_adapter, 1098 print_hang_task); 1099 struct net_device *netdev = adapter->netdev; 1100 struct e1000_ring *tx_ring = adapter->tx_ring; 1101 unsigned int i = tx_ring->next_to_clean; 1102 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1103 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1104 struct e1000_hw *hw = &adapter->hw; 1105 u16 phy_status, phy_1000t_status, phy_ext_status; 1106 u16 pci_status; 1107 1108 if (test_bit(__E1000_DOWN, &adapter->state)) 1109 return; 1110 1111 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1112 /* May be block on write-back, flush and detect again 1113 * flush pending descriptor writebacks to memory 1114 */ 1115 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1116 /* execute the writes immediately */ 1117 e1e_flush(); 1118 /* Due to rare timing issues, write to TIDV again to ensure 1119 * the write is successful 1120 */ 1121 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1122 /* execute the writes immediately */ 1123 e1e_flush(); 1124 adapter->tx_hang_recheck = true; 1125 return; 1126 } 1127 adapter->tx_hang_recheck = false; 1128 1129 if (er32(TDH(0)) == er32(TDT(0))) { 1130 e_dbg("false hang detected, ignoring\n"); 1131 return; 1132 } 1133 1134 /* Real hang detected */ 1135 netif_stop_queue(netdev); 1136 1137 e1e_rphy(hw, MII_BMSR, &phy_status); 1138 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1139 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1140 1141 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1142 1143 /* detected Hardware unit hang */ 1144 e_err("Detected Hardware Unit Hang:\n" 1145 " TDH <%x>\n" 1146 " TDT <%x>\n" 1147 " next_to_use <%x>\n" 1148 " next_to_clean <%x>\n" 1149 "buffer_info[next_to_clean]:\n" 1150 " time_stamp <%lx>\n" 1151 " next_to_watch <%x>\n" 1152 " jiffies <%lx>\n" 1153 " next_to_watch.status <%x>\n" 1154 "MAC Status <%x>\n" 1155 "PHY Status <%x>\n" 1156 "PHY 1000BASE-T Status <%x>\n" 1157 "PHY Extended Status <%x>\n" 1158 "PCI Status <%x>\n", 1159 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1160 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1161 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1162 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1163 1164 e1000e_dump(adapter); 1165 1166 /* Suggest workaround for known h/w issue */ 1167 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1168 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1169 } 1170 1171 /** 1172 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1173 * @work: pointer to work struct 1174 * 1175 * This work function polls the TSYNCTXCTL valid bit to determine when a 1176 * timestamp has been taken for the current stored skb. The timestamp must 1177 * be for this skb because only one such packet is allowed in the queue. 1178 */ 1179 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1180 { 1181 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1182 tx_hwtstamp_work); 1183 struct e1000_hw *hw = &adapter->hw; 1184 1185 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1186 struct skb_shared_hwtstamps shhwtstamps; 1187 u64 txstmp; 1188 1189 txstmp = er32(TXSTMPL); 1190 txstmp |= (u64)er32(TXSTMPH) << 32; 1191 1192 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1193 1194 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps); 1195 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1196 adapter->tx_hwtstamp_skb = NULL; 1197 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1198 + adapter->tx_timeout_factor * HZ)) { 1199 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1200 adapter->tx_hwtstamp_skb = NULL; 1201 adapter->tx_hwtstamp_timeouts++; 1202 e_warn("clearing Tx timestamp hang\n"); 1203 } else { 1204 /* reschedule to check later */ 1205 schedule_work(&adapter->tx_hwtstamp_work); 1206 } 1207 } 1208 1209 /** 1210 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1211 * @tx_ring: Tx descriptor ring 1212 * 1213 * the return value indicates whether actual cleaning was done, there 1214 * is no guarantee that everything was cleaned 1215 **/ 1216 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1217 { 1218 struct e1000_adapter *adapter = tx_ring->adapter; 1219 struct net_device *netdev = adapter->netdev; 1220 struct e1000_hw *hw = &adapter->hw; 1221 struct e1000_tx_desc *tx_desc, *eop_desc; 1222 struct e1000_buffer *buffer_info; 1223 unsigned int i, eop; 1224 unsigned int count = 0; 1225 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1226 unsigned int bytes_compl = 0, pkts_compl = 0; 1227 1228 i = tx_ring->next_to_clean; 1229 eop = tx_ring->buffer_info[i].next_to_watch; 1230 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1231 1232 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1233 (count < tx_ring->count)) { 1234 bool cleaned = false; 1235 1236 dma_rmb(); /* read buffer_info after eop_desc */ 1237 for (; !cleaned; count++) { 1238 tx_desc = E1000_TX_DESC(*tx_ring, i); 1239 buffer_info = &tx_ring->buffer_info[i]; 1240 cleaned = (i == eop); 1241 1242 if (cleaned) { 1243 total_tx_packets += buffer_info->segs; 1244 total_tx_bytes += buffer_info->bytecount; 1245 if (buffer_info->skb) { 1246 bytes_compl += buffer_info->skb->len; 1247 pkts_compl++; 1248 } 1249 } 1250 1251 e1000_put_txbuf(tx_ring, buffer_info); 1252 tx_desc->upper.data = 0; 1253 1254 i++; 1255 if (i == tx_ring->count) 1256 i = 0; 1257 } 1258 1259 if (i == tx_ring->next_to_use) 1260 break; 1261 eop = tx_ring->buffer_info[i].next_to_watch; 1262 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1263 } 1264 1265 tx_ring->next_to_clean = i; 1266 1267 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1268 1269 #define TX_WAKE_THRESHOLD 32 1270 if (count && netif_carrier_ok(netdev) && 1271 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1272 /* Make sure that anybody stopping the queue after this 1273 * sees the new next_to_clean. 1274 */ 1275 smp_mb(); 1276 1277 if (netif_queue_stopped(netdev) && 1278 !(test_bit(__E1000_DOWN, &adapter->state))) { 1279 netif_wake_queue(netdev); 1280 ++adapter->restart_queue; 1281 } 1282 } 1283 1284 if (adapter->detect_tx_hung) { 1285 /* Detect a transmit hang in hardware, this serializes the 1286 * check with the clearing of time_stamp and movement of i 1287 */ 1288 adapter->detect_tx_hung = false; 1289 if (tx_ring->buffer_info[i].time_stamp && 1290 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1291 + (adapter->tx_timeout_factor * HZ)) && 1292 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1293 schedule_work(&adapter->print_hang_task); 1294 else 1295 adapter->tx_hang_recheck = false; 1296 } 1297 adapter->total_tx_bytes += total_tx_bytes; 1298 adapter->total_tx_packets += total_tx_packets; 1299 return count < tx_ring->count; 1300 } 1301 1302 /** 1303 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1304 * @rx_ring: Rx descriptor ring 1305 * 1306 * the return value indicates whether actual cleaning was done, there 1307 * is no guarantee that everything was cleaned 1308 **/ 1309 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1310 int work_to_do) 1311 { 1312 struct e1000_adapter *adapter = rx_ring->adapter; 1313 struct e1000_hw *hw = &adapter->hw; 1314 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1315 struct net_device *netdev = adapter->netdev; 1316 struct pci_dev *pdev = adapter->pdev; 1317 struct e1000_buffer *buffer_info, *next_buffer; 1318 struct e1000_ps_page *ps_page; 1319 struct sk_buff *skb; 1320 unsigned int i, j; 1321 u32 length, staterr; 1322 int cleaned_count = 0; 1323 bool cleaned = false; 1324 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1325 1326 i = rx_ring->next_to_clean; 1327 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1328 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1329 buffer_info = &rx_ring->buffer_info[i]; 1330 1331 while (staterr & E1000_RXD_STAT_DD) { 1332 if (*work_done >= work_to_do) 1333 break; 1334 (*work_done)++; 1335 skb = buffer_info->skb; 1336 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1337 1338 /* in the packet split case this is header only */ 1339 prefetch(skb->data - NET_IP_ALIGN); 1340 1341 i++; 1342 if (i == rx_ring->count) 1343 i = 0; 1344 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1345 prefetch(next_rxd); 1346 1347 next_buffer = &rx_ring->buffer_info[i]; 1348 1349 cleaned = true; 1350 cleaned_count++; 1351 dma_unmap_single(&pdev->dev, buffer_info->dma, 1352 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1353 buffer_info->dma = 0; 1354 1355 /* see !EOP comment in other Rx routine */ 1356 if (!(staterr & E1000_RXD_STAT_EOP)) 1357 adapter->flags2 |= FLAG2_IS_DISCARDING; 1358 1359 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1360 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1361 dev_kfree_skb_irq(skb); 1362 if (staterr & E1000_RXD_STAT_EOP) 1363 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1364 goto next_desc; 1365 } 1366 1367 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1368 !(netdev->features & NETIF_F_RXALL))) { 1369 dev_kfree_skb_irq(skb); 1370 goto next_desc; 1371 } 1372 1373 length = le16_to_cpu(rx_desc->wb.middle.length0); 1374 1375 if (!length) { 1376 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1377 dev_kfree_skb_irq(skb); 1378 goto next_desc; 1379 } 1380 1381 /* Good Receive */ 1382 skb_put(skb, length); 1383 1384 { 1385 /* this looks ugly, but it seems compiler issues make 1386 * it more efficient than reusing j 1387 */ 1388 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1389 1390 /* page alloc/put takes too long and effects small 1391 * packet throughput, so unsplit small packets and 1392 * save the alloc/put only valid in softirq (napi) 1393 * context to call kmap_* 1394 */ 1395 if (l1 && (l1 <= copybreak) && 1396 ((length + l1) <= adapter->rx_ps_bsize0)) { 1397 u8 *vaddr; 1398 1399 ps_page = &buffer_info->ps_pages[0]; 1400 1401 /* there is no documentation about how to call 1402 * kmap_atomic, so we can't hold the mapping 1403 * very long 1404 */ 1405 dma_sync_single_for_cpu(&pdev->dev, 1406 ps_page->dma, 1407 PAGE_SIZE, 1408 DMA_FROM_DEVICE); 1409 vaddr = kmap_atomic(ps_page->page); 1410 memcpy(skb_tail_pointer(skb), vaddr, l1); 1411 kunmap_atomic(vaddr); 1412 dma_sync_single_for_device(&pdev->dev, 1413 ps_page->dma, 1414 PAGE_SIZE, 1415 DMA_FROM_DEVICE); 1416 1417 /* remove the CRC */ 1418 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1419 if (!(netdev->features & NETIF_F_RXFCS)) 1420 l1 -= 4; 1421 } 1422 1423 skb_put(skb, l1); 1424 goto copydone; 1425 } /* if */ 1426 } 1427 1428 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1429 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1430 if (!length) 1431 break; 1432 1433 ps_page = &buffer_info->ps_pages[j]; 1434 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1435 DMA_FROM_DEVICE); 1436 ps_page->dma = 0; 1437 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1438 ps_page->page = NULL; 1439 skb->len += length; 1440 skb->data_len += length; 1441 skb->truesize += PAGE_SIZE; 1442 } 1443 1444 /* strip the ethernet crc, problem is we're using pages now so 1445 * this whole operation can get a little cpu intensive 1446 */ 1447 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1448 if (!(netdev->features & NETIF_F_RXFCS)) 1449 pskb_trim(skb, skb->len - 4); 1450 } 1451 1452 copydone: 1453 total_rx_bytes += skb->len; 1454 total_rx_packets++; 1455 1456 e1000_rx_checksum(adapter, staterr, skb); 1457 1458 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1459 1460 if (rx_desc->wb.upper.header_status & 1461 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1462 adapter->rx_hdr_split++; 1463 1464 e1000_receive_skb(adapter, netdev, skb, staterr, 1465 rx_desc->wb.middle.vlan); 1466 1467 next_desc: 1468 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1469 buffer_info->skb = NULL; 1470 1471 /* return some buffers to hardware, one at a time is too slow */ 1472 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1473 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1474 GFP_ATOMIC); 1475 cleaned_count = 0; 1476 } 1477 1478 /* use prefetched values */ 1479 rx_desc = next_rxd; 1480 buffer_info = next_buffer; 1481 1482 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1483 } 1484 rx_ring->next_to_clean = i; 1485 1486 cleaned_count = e1000_desc_unused(rx_ring); 1487 if (cleaned_count) 1488 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1489 1490 adapter->total_rx_bytes += total_rx_bytes; 1491 adapter->total_rx_packets += total_rx_packets; 1492 return cleaned; 1493 } 1494 1495 /** 1496 * e1000_consume_page - helper function 1497 **/ 1498 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1499 u16 length) 1500 { 1501 bi->page = NULL; 1502 skb->len += length; 1503 skb->data_len += length; 1504 skb->truesize += PAGE_SIZE; 1505 } 1506 1507 /** 1508 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1509 * @adapter: board private structure 1510 * 1511 * the return value indicates whether actual cleaning was done, there 1512 * is no guarantee that everything was cleaned 1513 **/ 1514 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1515 int work_to_do) 1516 { 1517 struct e1000_adapter *adapter = rx_ring->adapter; 1518 struct net_device *netdev = adapter->netdev; 1519 struct pci_dev *pdev = adapter->pdev; 1520 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1521 struct e1000_buffer *buffer_info, *next_buffer; 1522 u32 length, staterr; 1523 unsigned int i; 1524 int cleaned_count = 0; 1525 bool cleaned = false; 1526 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1527 struct skb_shared_info *shinfo; 1528 1529 i = rx_ring->next_to_clean; 1530 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1532 buffer_info = &rx_ring->buffer_info[i]; 1533 1534 while (staterr & E1000_RXD_STAT_DD) { 1535 struct sk_buff *skb; 1536 1537 if (*work_done >= work_to_do) 1538 break; 1539 (*work_done)++; 1540 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1541 1542 skb = buffer_info->skb; 1543 buffer_info->skb = NULL; 1544 1545 ++i; 1546 if (i == rx_ring->count) 1547 i = 0; 1548 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1549 prefetch(next_rxd); 1550 1551 next_buffer = &rx_ring->buffer_info[i]; 1552 1553 cleaned = true; 1554 cleaned_count++; 1555 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1556 DMA_FROM_DEVICE); 1557 buffer_info->dma = 0; 1558 1559 length = le16_to_cpu(rx_desc->wb.upper.length); 1560 1561 /* errors is only valid for DD + EOP descriptors */ 1562 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1563 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1564 !(netdev->features & NETIF_F_RXALL)))) { 1565 /* recycle both page and skb */ 1566 buffer_info->skb = skb; 1567 /* an error means any chain goes out the window too */ 1568 if (rx_ring->rx_skb_top) 1569 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1570 rx_ring->rx_skb_top = NULL; 1571 goto next_desc; 1572 } 1573 #define rxtop (rx_ring->rx_skb_top) 1574 if (!(staterr & E1000_RXD_STAT_EOP)) { 1575 /* this descriptor is only the beginning (or middle) */ 1576 if (!rxtop) { 1577 /* this is the beginning of a chain */ 1578 rxtop = skb; 1579 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1580 0, length); 1581 } else { 1582 /* this is the middle of a chain */ 1583 shinfo = skb_shinfo(rxtop); 1584 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1585 buffer_info->page, 0, 1586 length); 1587 /* re-use the skb, only consumed the page */ 1588 buffer_info->skb = skb; 1589 } 1590 e1000_consume_page(buffer_info, rxtop, length); 1591 goto next_desc; 1592 } else { 1593 if (rxtop) { 1594 /* end of the chain */ 1595 shinfo = skb_shinfo(rxtop); 1596 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1597 buffer_info->page, 0, 1598 length); 1599 /* re-use the current skb, we only consumed the 1600 * page 1601 */ 1602 buffer_info->skb = skb; 1603 skb = rxtop; 1604 rxtop = NULL; 1605 e1000_consume_page(buffer_info, skb, length); 1606 } else { 1607 /* no chain, got EOP, this buf is the packet 1608 * copybreak to save the put_page/alloc_page 1609 */ 1610 if (length <= copybreak && 1611 skb_tailroom(skb) >= length) { 1612 u8 *vaddr; 1613 vaddr = kmap_atomic(buffer_info->page); 1614 memcpy(skb_tail_pointer(skb), vaddr, 1615 length); 1616 kunmap_atomic(vaddr); 1617 /* re-use the page, so don't erase 1618 * buffer_info->page 1619 */ 1620 skb_put(skb, length); 1621 } else { 1622 skb_fill_page_desc(skb, 0, 1623 buffer_info->page, 0, 1624 length); 1625 e1000_consume_page(buffer_info, skb, 1626 length); 1627 } 1628 } 1629 } 1630 1631 /* Receive Checksum Offload */ 1632 e1000_rx_checksum(adapter, staterr, skb); 1633 1634 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1635 1636 /* probably a little skewed due to removing CRC */ 1637 total_rx_bytes += skb->len; 1638 total_rx_packets++; 1639 1640 /* eth type trans needs skb->data to point to something */ 1641 if (!pskb_may_pull(skb, ETH_HLEN)) { 1642 e_err("pskb_may_pull failed.\n"); 1643 dev_kfree_skb_irq(skb); 1644 goto next_desc; 1645 } 1646 1647 e1000_receive_skb(adapter, netdev, skb, staterr, 1648 rx_desc->wb.upper.vlan); 1649 1650 next_desc: 1651 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1652 1653 /* return some buffers to hardware, one at a time is too slow */ 1654 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1655 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1656 GFP_ATOMIC); 1657 cleaned_count = 0; 1658 } 1659 1660 /* use prefetched values */ 1661 rx_desc = next_rxd; 1662 buffer_info = next_buffer; 1663 1664 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1665 } 1666 rx_ring->next_to_clean = i; 1667 1668 cleaned_count = e1000_desc_unused(rx_ring); 1669 if (cleaned_count) 1670 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1671 1672 adapter->total_rx_bytes += total_rx_bytes; 1673 adapter->total_rx_packets += total_rx_packets; 1674 return cleaned; 1675 } 1676 1677 /** 1678 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1679 * @rx_ring: Rx descriptor ring 1680 **/ 1681 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1682 { 1683 struct e1000_adapter *adapter = rx_ring->adapter; 1684 struct e1000_buffer *buffer_info; 1685 struct e1000_ps_page *ps_page; 1686 struct pci_dev *pdev = adapter->pdev; 1687 unsigned int i, j; 1688 1689 /* Free all the Rx ring sk_buffs */ 1690 for (i = 0; i < rx_ring->count; i++) { 1691 buffer_info = &rx_ring->buffer_info[i]; 1692 if (buffer_info->dma) { 1693 if (adapter->clean_rx == e1000_clean_rx_irq) 1694 dma_unmap_single(&pdev->dev, buffer_info->dma, 1695 adapter->rx_buffer_len, 1696 DMA_FROM_DEVICE); 1697 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1698 dma_unmap_page(&pdev->dev, buffer_info->dma, 1699 PAGE_SIZE, DMA_FROM_DEVICE); 1700 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1701 dma_unmap_single(&pdev->dev, buffer_info->dma, 1702 adapter->rx_ps_bsize0, 1703 DMA_FROM_DEVICE); 1704 buffer_info->dma = 0; 1705 } 1706 1707 if (buffer_info->page) { 1708 put_page(buffer_info->page); 1709 buffer_info->page = NULL; 1710 } 1711 1712 if (buffer_info->skb) { 1713 dev_kfree_skb(buffer_info->skb); 1714 buffer_info->skb = NULL; 1715 } 1716 1717 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1718 ps_page = &buffer_info->ps_pages[j]; 1719 if (!ps_page->page) 1720 break; 1721 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1722 DMA_FROM_DEVICE); 1723 ps_page->dma = 0; 1724 put_page(ps_page->page); 1725 ps_page->page = NULL; 1726 } 1727 } 1728 1729 /* there also may be some cached data from a chained receive */ 1730 if (rx_ring->rx_skb_top) { 1731 dev_kfree_skb(rx_ring->rx_skb_top); 1732 rx_ring->rx_skb_top = NULL; 1733 } 1734 1735 /* Zero out the descriptor ring */ 1736 memset(rx_ring->desc, 0, rx_ring->size); 1737 1738 rx_ring->next_to_clean = 0; 1739 rx_ring->next_to_use = 0; 1740 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1741 } 1742 1743 static void e1000e_downshift_workaround(struct work_struct *work) 1744 { 1745 struct e1000_adapter *adapter = container_of(work, 1746 struct e1000_adapter, 1747 downshift_task); 1748 1749 if (test_bit(__E1000_DOWN, &adapter->state)) 1750 return; 1751 1752 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1753 } 1754 1755 /** 1756 * e1000_intr_msi - Interrupt Handler 1757 * @irq: interrupt number 1758 * @data: pointer to a network interface device structure 1759 **/ 1760 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1761 { 1762 struct net_device *netdev = data; 1763 struct e1000_adapter *adapter = netdev_priv(netdev); 1764 struct e1000_hw *hw = &adapter->hw; 1765 u32 icr = er32(ICR); 1766 1767 /* read ICR disables interrupts using IAM */ 1768 if (icr & E1000_ICR_LSC) { 1769 hw->mac.get_link_status = true; 1770 /* ICH8 workaround-- Call gig speed drop workaround on cable 1771 * disconnect (LSC) before accessing any PHY registers 1772 */ 1773 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1774 (!(er32(STATUS) & E1000_STATUS_LU))) 1775 schedule_work(&adapter->downshift_task); 1776 1777 /* 80003ES2LAN workaround-- For packet buffer work-around on 1778 * link down event; disable receives here in the ISR and reset 1779 * adapter in watchdog 1780 */ 1781 if (netif_carrier_ok(netdev) && 1782 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1783 /* disable receives */ 1784 u32 rctl = er32(RCTL); 1785 1786 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1787 adapter->flags |= FLAG_RESTART_NOW; 1788 } 1789 /* guard against interrupt when we're going down */ 1790 if (!test_bit(__E1000_DOWN, &adapter->state)) 1791 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1792 } 1793 1794 /* Reset on uncorrectable ECC error */ 1795 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1796 u32 pbeccsts = er32(PBECCSTS); 1797 1798 adapter->corr_errors += 1799 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1800 adapter->uncorr_errors += 1801 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1803 1804 /* Do the reset outside of interrupt context */ 1805 schedule_work(&adapter->reset_task); 1806 1807 /* return immediately since reset is imminent */ 1808 return IRQ_HANDLED; 1809 } 1810 1811 if (napi_schedule_prep(&adapter->napi)) { 1812 adapter->total_tx_bytes = 0; 1813 adapter->total_tx_packets = 0; 1814 adapter->total_rx_bytes = 0; 1815 adapter->total_rx_packets = 0; 1816 __napi_schedule(&adapter->napi); 1817 } 1818 1819 return IRQ_HANDLED; 1820 } 1821 1822 /** 1823 * e1000_intr - Interrupt Handler 1824 * @irq: interrupt number 1825 * @data: pointer to a network interface device structure 1826 **/ 1827 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1828 { 1829 struct net_device *netdev = data; 1830 struct e1000_adapter *adapter = netdev_priv(netdev); 1831 struct e1000_hw *hw = &adapter->hw; 1832 u32 rctl, icr = er32(ICR); 1833 1834 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1835 return IRQ_NONE; /* Not our interrupt */ 1836 1837 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1838 * not set, then the adapter didn't send an interrupt 1839 */ 1840 if (!(icr & E1000_ICR_INT_ASSERTED)) 1841 return IRQ_NONE; 1842 1843 /* Interrupt Auto-Mask...upon reading ICR, 1844 * interrupts are masked. No need for the 1845 * IMC write 1846 */ 1847 1848 if (icr & E1000_ICR_LSC) { 1849 hw->mac.get_link_status = true; 1850 /* ICH8 workaround-- Call gig speed drop workaround on cable 1851 * disconnect (LSC) before accessing any PHY registers 1852 */ 1853 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1854 (!(er32(STATUS) & E1000_STATUS_LU))) 1855 schedule_work(&adapter->downshift_task); 1856 1857 /* 80003ES2LAN workaround-- 1858 * For packet buffer work-around on link down event; 1859 * disable receives here in the ISR and 1860 * reset adapter in watchdog 1861 */ 1862 if (netif_carrier_ok(netdev) && 1863 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1864 /* disable receives */ 1865 rctl = er32(RCTL); 1866 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1867 adapter->flags |= FLAG_RESTART_NOW; 1868 } 1869 /* guard against interrupt when we're going down */ 1870 if (!test_bit(__E1000_DOWN, &adapter->state)) 1871 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1872 } 1873 1874 /* Reset on uncorrectable ECC error */ 1875 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1876 u32 pbeccsts = er32(PBECCSTS); 1877 1878 adapter->corr_errors += 1879 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1880 adapter->uncorr_errors += 1881 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1882 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1883 1884 /* Do the reset outside of interrupt context */ 1885 schedule_work(&adapter->reset_task); 1886 1887 /* return immediately since reset is imminent */ 1888 return IRQ_HANDLED; 1889 } 1890 1891 if (napi_schedule_prep(&adapter->napi)) { 1892 adapter->total_tx_bytes = 0; 1893 adapter->total_tx_packets = 0; 1894 adapter->total_rx_bytes = 0; 1895 adapter->total_rx_packets = 0; 1896 __napi_schedule(&adapter->napi); 1897 } 1898 1899 return IRQ_HANDLED; 1900 } 1901 1902 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1903 { 1904 struct net_device *netdev = data; 1905 struct e1000_adapter *adapter = netdev_priv(netdev); 1906 struct e1000_hw *hw = &adapter->hw; 1907 1908 hw->mac.get_link_status = true; 1909 1910 /* guard against interrupt when we're going down */ 1911 if (!test_bit(__E1000_DOWN, &adapter->state)) { 1912 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1913 ew32(IMS, E1000_IMS_OTHER); 1914 } 1915 1916 return IRQ_HANDLED; 1917 } 1918 1919 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1920 { 1921 struct net_device *netdev = data; 1922 struct e1000_adapter *adapter = netdev_priv(netdev); 1923 struct e1000_hw *hw = &adapter->hw; 1924 struct e1000_ring *tx_ring = adapter->tx_ring; 1925 1926 adapter->total_tx_bytes = 0; 1927 adapter->total_tx_packets = 0; 1928 1929 if (!e1000_clean_tx_irq(tx_ring)) 1930 /* Ring was not completely cleaned, so fire another interrupt */ 1931 ew32(ICS, tx_ring->ims_val); 1932 1933 if (!test_bit(__E1000_DOWN, &adapter->state)) 1934 ew32(IMS, adapter->tx_ring->ims_val); 1935 1936 return IRQ_HANDLED; 1937 } 1938 1939 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1940 { 1941 struct net_device *netdev = data; 1942 struct e1000_adapter *adapter = netdev_priv(netdev); 1943 struct e1000_ring *rx_ring = adapter->rx_ring; 1944 1945 /* Write the ITR value calculated at the end of the 1946 * previous interrupt. 1947 */ 1948 if (rx_ring->set_itr) { 1949 u32 itr = rx_ring->itr_val ? 1950 1000000000 / (rx_ring->itr_val * 256) : 0; 1951 1952 writel(itr, rx_ring->itr_register); 1953 rx_ring->set_itr = 0; 1954 } 1955 1956 if (napi_schedule_prep(&adapter->napi)) { 1957 adapter->total_rx_bytes = 0; 1958 adapter->total_rx_packets = 0; 1959 __napi_schedule(&adapter->napi); 1960 } 1961 return IRQ_HANDLED; 1962 } 1963 1964 /** 1965 * e1000_configure_msix - Configure MSI-X hardware 1966 * 1967 * e1000_configure_msix sets up the hardware to properly 1968 * generate MSI-X interrupts. 1969 **/ 1970 static void e1000_configure_msix(struct e1000_adapter *adapter) 1971 { 1972 struct e1000_hw *hw = &adapter->hw; 1973 struct e1000_ring *rx_ring = adapter->rx_ring; 1974 struct e1000_ring *tx_ring = adapter->tx_ring; 1975 int vector = 0; 1976 u32 ctrl_ext, ivar = 0; 1977 1978 adapter->eiac_mask = 0; 1979 1980 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1981 if (hw->mac.type == e1000_82574) { 1982 u32 rfctl = er32(RFCTL); 1983 1984 rfctl |= E1000_RFCTL_ACK_DIS; 1985 ew32(RFCTL, rfctl); 1986 } 1987 1988 /* Configure Rx vector */ 1989 rx_ring->ims_val = E1000_IMS_RXQ0; 1990 adapter->eiac_mask |= rx_ring->ims_val; 1991 if (rx_ring->itr_val) 1992 writel(1000000000 / (rx_ring->itr_val * 256), 1993 rx_ring->itr_register); 1994 else 1995 writel(1, rx_ring->itr_register); 1996 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1997 1998 /* Configure Tx vector */ 1999 tx_ring->ims_val = E1000_IMS_TXQ0; 2000 vector++; 2001 if (tx_ring->itr_val) 2002 writel(1000000000 / (tx_ring->itr_val * 256), 2003 tx_ring->itr_register); 2004 else 2005 writel(1, tx_ring->itr_register); 2006 adapter->eiac_mask |= tx_ring->ims_val; 2007 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2008 2009 /* set vector for Other Causes, e.g. link changes */ 2010 vector++; 2011 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2012 if (rx_ring->itr_val) 2013 writel(1000000000 / (rx_ring->itr_val * 256), 2014 hw->hw_addr + E1000_EITR_82574(vector)); 2015 else 2016 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2017 adapter->eiac_mask |= E1000_IMS_OTHER; 2018 2019 /* Cause Tx interrupts on every write back */ 2020 ivar |= BIT(31); 2021 2022 ew32(IVAR, ivar); 2023 2024 /* enable MSI-X PBA support */ 2025 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2026 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2027 ew32(CTRL_EXT, ctrl_ext); 2028 e1e_flush(); 2029 } 2030 2031 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2032 { 2033 if (adapter->msix_entries) { 2034 pci_disable_msix(adapter->pdev); 2035 kfree(adapter->msix_entries); 2036 adapter->msix_entries = NULL; 2037 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2038 pci_disable_msi(adapter->pdev); 2039 adapter->flags &= ~FLAG_MSI_ENABLED; 2040 } 2041 } 2042 2043 /** 2044 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2045 * 2046 * Attempt to configure interrupts using the best available 2047 * capabilities of the hardware and kernel. 2048 **/ 2049 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2050 { 2051 int err; 2052 int i; 2053 2054 switch (adapter->int_mode) { 2055 case E1000E_INT_MODE_MSIX: 2056 if (adapter->flags & FLAG_HAS_MSIX) { 2057 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2058 adapter->msix_entries = kcalloc(adapter->num_vectors, 2059 sizeof(struct 2060 msix_entry), 2061 GFP_KERNEL); 2062 if (adapter->msix_entries) { 2063 struct e1000_adapter *a = adapter; 2064 2065 for (i = 0; i < adapter->num_vectors; i++) 2066 adapter->msix_entries[i].entry = i; 2067 2068 err = pci_enable_msix_range(a->pdev, 2069 a->msix_entries, 2070 a->num_vectors, 2071 a->num_vectors); 2072 if (err > 0) 2073 return; 2074 } 2075 /* MSI-X failed, so fall through and try MSI */ 2076 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2077 e1000e_reset_interrupt_capability(adapter); 2078 } 2079 adapter->int_mode = E1000E_INT_MODE_MSI; 2080 /* Fall through */ 2081 case E1000E_INT_MODE_MSI: 2082 if (!pci_enable_msi(adapter->pdev)) { 2083 adapter->flags |= FLAG_MSI_ENABLED; 2084 } else { 2085 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2086 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2087 } 2088 /* Fall through */ 2089 case E1000E_INT_MODE_LEGACY: 2090 /* Don't do anything; this is the system default */ 2091 break; 2092 } 2093 2094 /* store the number of vectors being used */ 2095 adapter->num_vectors = 1; 2096 } 2097 2098 /** 2099 * e1000_request_msix - Initialize MSI-X interrupts 2100 * 2101 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2102 * kernel. 2103 **/ 2104 static int e1000_request_msix(struct e1000_adapter *adapter) 2105 { 2106 struct net_device *netdev = adapter->netdev; 2107 int err = 0, vector = 0; 2108 2109 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2110 snprintf(adapter->rx_ring->name, 2111 sizeof(adapter->rx_ring->name) - 1, 2112 "%s-rx-0", netdev->name); 2113 else 2114 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2115 err = request_irq(adapter->msix_entries[vector].vector, 2116 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2117 netdev); 2118 if (err) 2119 return err; 2120 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2121 E1000_EITR_82574(vector); 2122 adapter->rx_ring->itr_val = adapter->itr; 2123 vector++; 2124 2125 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2126 snprintf(adapter->tx_ring->name, 2127 sizeof(adapter->tx_ring->name) - 1, 2128 "%s-tx-0", netdev->name); 2129 else 2130 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2131 err = request_irq(adapter->msix_entries[vector].vector, 2132 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2133 netdev); 2134 if (err) 2135 return err; 2136 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2137 E1000_EITR_82574(vector); 2138 adapter->tx_ring->itr_val = adapter->itr; 2139 vector++; 2140 2141 err = request_irq(adapter->msix_entries[vector].vector, 2142 e1000_msix_other, 0, netdev->name, netdev); 2143 if (err) 2144 return err; 2145 2146 e1000_configure_msix(adapter); 2147 2148 return 0; 2149 } 2150 2151 /** 2152 * e1000_request_irq - initialize interrupts 2153 * 2154 * Attempts to configure interrupts using the best available 2155 * capabilities of the hardware and kernel. 2156 **/ 2157 static int e1000_request_irq(struct e1000_adapter *adapter) 2158 { 2159 struct net_device *netdev = adapter->netdev; 2160 int err; 2161 2162 if (adapter->msix_entries) { 2163 err = e1000_request_msix(adapter); 2164 if (!err) 2165 return err; 2166 /* fall back to MSI */ 2167 e1000e_reset_interrupt_capability(adapter); 2168 adapter->int_mode = E1000E_INT_MODE_MSI; 2169 e1000e_set_interrupt_capability(adapter); 2170 } 2171 if (adapter->flags & FLAG_MSI_ENABLED) { 2172 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2173 netdev->name, netdev); 2174 if (!err) 2175 return err; 2176 2177 /* fall back to legacy interrupt */ 2178 e1000e_reset_interrupt_capability(adapter); 2179 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2180 } 2181 2182 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2183 netdev->name, netdev); 2184 if (err) 2185 e_err("Unable to allocate interrupt, Error: %d\n", err); 2186 2187 return err; 2188 } 2189 2190 static void e1000_free_irq(struct e1000_adapter *adapter) 2191 { 2192 struct net_device *netdev = adapter->netdev; 2193 2194 if (adapter->msix_entries) { 2195 int vector = 0; 2196 2197 free_irq(adapter->msix_entries[vector].vector, netdev); 2198 vector++; 2199 2200 free_irq(adapter->msix_entries[vector].vector, netdev); 2201 vector++; 2202 2203 /* Other Causes interrupt vector */ 2204 free_irq(adapter->msix_entries[vector].vector, netdev); 2205 return; 2206 } 2207 2208 free_irq(adapter->pdev->irq, netdev); 2209 } 2210 2211 /** 2212 * e1000_irq_disable - Mask off interrupt generation on the NIC 2213 **/ 2214 static void e1000_irq_disable(struct e1000_adapter *adapter) 2215 { 2216 struct e1000_hw *hw = &adapter->hw; 2217 2218 ew32(IMC, ~0); 2219 if (adapter->msix_entries) 2220 ew32(EIAC_82574, 0); 2221 e1e_flush(); 2222 2223 if (adapter->msix_entries) { 2224 int i; 2225 2226 for (i = 0; i < adapter->num_vectors; i++) 2227 synchronize_irq(adapter->msix_entries[i].vector); 2228 } else { 2229 synchronize_irq(adapter->pdev->irq); 2230 } 2231 } 2232 2233 /** 2234 * e1000_irq_enable - Enable default interrupt generation settings 2235 **/ 2236 static void e1000_irq_enable(struct e1000_adapter *adapter) 2237 { 2238 struct e1000_hw *hw = &adapter->hw; 2239 2240 if (adapter->msix_entries) { 2241 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2242 ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC); 2243 } else if (hw->mac.type >= e1000_pch_lpt) { 2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2245 } else { 2246 ew32(IMS, IMS_ENABLE_MASK); 2247 } 2248 e1e_flush(); 2249 } 2250 2251 /** 2252 * e1000e_get_hw_control - get control of the h/w from f/w 2253 * @adapter: address of board private structure 2254 * 2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2256 * For ASF and Pass Through versions of f/w this means that 2257 * the driver is loaded. For AMT version (only with 82573) 2258 * of the f/w this means that the network i/f is open. 2259 **/ 2260 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2261 { 2262 struct e1000_hw *hw = &adapter->hw; 2263 u32 ctrl_ext; 2264 u32 swsm; 2265 2266 /* Let firmware know the driver has taken over */ 2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2268 swsm = er32(SWSM); 2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2271 ctrl_ext = er32(CTRL_EXT); 2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2273 } 2274 } 2275 2276 /** 2277 * e1000e_release_hw_control - release control of the h/w to f/w 2278 * @adapter: address of board private structure 2279 * 2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2281 * For ASF and Pass Through versions of f/w this means that the 2282 * driver is no longer loaded. For AMT version (only with 82573) i 2283 * of the f/w this means that the network i/f is closed. 2284 * 2285 **/ 2286 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2287 { 2288 struct e1000_hw *hw = &adapter->hw; 2289 u32 ctrl_ext; 2290 u32 swsm; 2291 2292 /* Let firmware taken over control of h/w */ 2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2294 swsm = er32(SWSM); 2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2297 ctrl_ext = er32(CTRL_EXT); 2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2299 } 2300 } 2301 2302 /** 2303 * e1000_alloc_ring_dma - allocate memory for a ring structure 2304 **/ 2305 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2306 struct e1000_ring *ring) 2307 { 2308 struct pci_dev *pdev = adapter->pdev; 2309 2310 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2311 GFP_KERNEL); 2312 if (!ring->desc) 2313 return -ENOMEM; 2314 2315 return 0; 2316 } 2317 2318 /** 2319 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2320 * @tx_ring: Tx descriptor ring 2321 * 2322 * Return 0 on success, negative on failure 2323 **/ 2324 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2325 { 2326 struct e1000_adapter *adapter = tx_ring->adapter; 2327 int err = -ENOMEM, size; 2328 2329 size = sizeof(struct e1000_buffer) * tx_ring->count; 2330 tx_ring->buffer_info = vzalloc(size); 2331 if (!tx_ring->buffer_info) 2332 goto err; 2333 2334 /* round up to nearest 4K */ 2335 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2336 tx_ring->size = ALIGN(tx_ring->size, 4096); 2337 2338 err = e1000_alloc_ring_dma(adapter, tx_ring); 2339 if (err) 2340 goto err; 2341 2342 tx_ring->next_to_use = 0; 2343 tx_ring->next_to_clean = 0; 2344 2345 return 0; 2346 err: 2347 vfree(tx_ring->buffer_info); 2348 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2349 return err; 2350 } 2351 2352 /** 2353 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2354 * @rx_ring: Rx descriptor ring 2355 * 2356 * Returns 0 on success, negative on failure 2357 **/ 2358 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2359 { 2360 struct e1000_adapter *adapter = rx_ring->adapter; 2361 struct e1000_buffer *buffer_info; 2362 int i, size, desc_len, err = -ENOMEM; 2363 2364 size = sizeof(struct e1000_buffer) * rx_ring->count; 2365 rx_ring->buffer_info = vzalloc(size); 2366 if (!rx_ring->buffer_info) 2367 goto err; 2368 2369 for (i = 0; i < rx_ring->count; i++) { 2370 buffer_info = &rx_ring->buffer_info[i]; 2371 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2372 sizeof(struct e1000_ps_page), 2373 GFP_KERNEL); 2374 if (!buffer_info->ps_pages) 2375 goto err_pages; 2376 } 2377 2378 desc_len = sizeof(union e1000_rx_desc_packet_split); 2379 2380 /* Round up to nearest 4K */ 2381 rx_ring->size = rx_ring->count * desc_len; 2382 rx_ring->size = ALIGN(rx_ring->size, 4096); 2383 2384 err = e1000_alloc_ring_dma(adapter, rx_ring); 2385 if (err) 2386 goto err_pages; 2387 2388 rx_ring->next_to_clean = 0; 2389 rx_ring->next_to_use = 0; 2390 rx_ring->rx_skb_top = NULL; 2391 2392 return 0; 2393 2394 err_pages: 2395 for (i = 0; i < rx_ring->count; i++) { 2396 buffer_info = &rx_ring->buffer_info[i]; 2397 kfree(buffer_info->ps_pages); 2398 } 2399 err: 2400 vfree(rx_ring->buffer_info); 2401 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2402 return err; 2403 } 2404 2405 /** 2406 * e1000_clean_tx_ring - Free Tx Buffers 2407 * @tx_ring: Tx descriptor ring 2408 **/ 2409 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2410 { 2411 struct e1000_adapter *adapter = tx_ring->adapter; 2412 struct e1000_buffer *buffer_info; 2413 unsigned long size; 2414 unsigned int i; 2415 2416 for (i = 0; i < tx_ring->count; i++) { 2417 buffer_info = &tx_ring->buffer_info[i]; 2418 e1000_put_txbuf(tx_ring, buffer_info); 2419 } 2420 2421 netdev_reset_queue(adapter->netdev); 2422 size = sizeof(struct e1000_buffer) * tx_ring->count; 2423 memset(tx_ring->buffer_info, 0, size); 2424 2425 memset(tx_ring->desc, 0, tx_ring->size); 2426 2427 tx_ring->next_to_use = 0; 2428 tx_ring->next_to_clean = 0; 2429 } 2430 2431 /** 2432 * e1000e_free_tx_resources - Free Tx Resources per Queue 2433 * @tx_ring: Tx descriptor ring 2434 * 2435 * Free all transmit software resources 2436 **/ 2437 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2438 { 2439 struct e1000_adapter *adapter = tx_ring->adapter; 2440 struct pci_dev *pdev = adapter->pdev; 2441 2442 e1000_clean_tx_ring(tx_ring); 2443 2444 vfree(tx_ring->buffer_info); 2445 tx_ring->buffer_info = NULL; 2446 2447 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2448 tx_ring->dma); 2449 tx_ring->desc = NULL; 2450 } 2451 2452 /** 2453 * e1000e_free_rx_resources - Free Rx Resources 2454 * @rx_ring: Rx descriptor ring 2455 * 2456 * Free all receive software resources 2457 **/ 2458 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2459 { 2460 struct e1000_adapter *adapter = rx_ring->adapter; 2461 struct pci_dev *pdev = adapter->pdev; 2462 int i; 2463 2464 e1000_clean_rx_ring(rx_ring); 2465 2466 for (i = 0; i < rx_ring->count; i++) 2467 kfree(rx_ring->buffer_info[i].ps_pages); 2468 2469 vfree(rx_ring->buffer_info); 2470 rx_ring->buffer_info = NULL; 2471 2472 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2473 rx_ring->dma); 2474 rx_ring->desc = NULL; 2475 } 2476 2477 /** 2478 * e1000_update_itr - update the dynamic ITR value based on statistics 2479 * @adapter: pointer to adapter 2480 * @itr_setting: current adapter->itr 2481 * @packets: the number of packets during this measurement interval 2482 * @bytes: the number of bytes during this measurement interval 2483 * 2484 * Stores a new ITR value based on packets and byte 2485 * counts during the last interrupt. The advantage of per interrupt 2486 * computation is faster updates and more accurate ITR for the current 2487 * traffic pattern. Constants in this function were computed 2488 * based on theoretical maximum wire speed and thresholds were set based 2489 * on testing data as well as attempting to minimize response time 2490 * while increasing bulk throughput. This functionality is controlled 2491 * by the InterruptThrottleRate module parameter. 2492 **/ 2493 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2494 { 2495 unsigned int retval = itr_setting; 2496 2497 if (packets == 0) 2498 return itr_setting; 2499 2500 switch (itr_setting) { 2501 case lowest_latency: 2502 /* handle TSO and jumbo frames */ 2503 if (bytes / packets > 8000) 2504 retval = bulk_latency; 2505 else if ((packets < 5) && (bytes > 512)) 2506 retval = low_latency; 2507 break; 2508 case low_latency: /* 50 usec aka 20000 ints/s */ 2509 if (bytes > 10000) { 2510 /* this if handles the TSO accounting */ 2511 if (bytes / packets > 8000) 2512 retval = bulk_latency; 2513 else if ((packets < 10) || ((bytes / packets) > 1200)) 2514 retval = bulk_latency; 2515 else if ((packets > 35)) 2516 retval = lowest_latency; 2517 } else if (bytes / packets > 2000) { 2518 retval = bulk_latency; 2519 } else if (packets <= 2 && bytes < 512) { 2520 retval = lowest_latency; 2521 } 2522 break; 2523 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2524 if (bytes > 25000) { 2525 if (packets > 35) 2526 retval = low_latency; 2527 } else if (bytes < 6000) { 2528 retval = low_latency; 2529 } 2530 break; 2531 } 2532 2533 return retval; 2534 } 2535 2536 static void e1000_set_itr(struct e1000_adapter *adapter) 2537 { 2538 u16 current_itr; 2539 u32 new_itr = adapter->itr; 2540 2541 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2542 if (adapter->link_speed != SPEED_1000) { 2543 current_itr = 0; 2544 new_itr = 4000; 2545 goto set_itr_now; 2546 } 2547 2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2549 new_itr = 0; 2550 goto set_itr_now; 2551 } 2552 2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2554 adapter->total_tx_packets, 2555 adapter->total_tx_bytes); 2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2558 adapter->tx_itr = low_latency; 2559 2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2561 adapter->total_rx_packets, 2562 adapter->total_rx_bytes); 2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2565 adapter->rx_itr = low_latency; 2566 2567 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2568 2569 /* counts and packets in update_itr are dependent on these numbers */ 2570 switch (current_itr) { 2571 case lowest_latency: 2572 new_itr = 70000; 2573 break; 2574 case low_latency: 2575 new_itr = 20000; /* aka hwitr = ~200 */ 2576 break; 2577 case bulk_latency: 2578 new_itr = 4000; 2579 break; 2580 default: 2581 break; 2582 } 2583 2584 set_itr_now: 2585 if (new_itr != adapter->itr) { 2586 /* this attempts to bias the interrupt rate towards Bulk 2587 * by adding intermediate steps when interrupt rate is 2588 * increasing 2589 */ 2590 new_itr = new_itr > adapter->itr ? 2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2592 adapter->itr = new_itr; 2593 adapter->rx_ring->itr_val = new_itr; 2594 if (adapter->msix_entries) 2595 adapter->rx_ring->set_itr = 1; 2596 else 2597 e1000e_write_itr(adapter, new_itr); 2598 } 2599 } 2600 2601 /** 2602 * e1000e_write_itr - write the ITR value to the appropriate registers 2603 * @adapter: address of board private structure 2604 * @itr: new ITR value to program 2605 * 2606 * e1000e_write_itr determines if the adapter is in MSI-X mode 2607 * and, if so, writes the EITR registers with the ITR value. 2608 * Otherwise, it writes the ITR value into the ITR register. 2609 **/ 2610 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2611 { 2612 struct e1000_hw *hw = &adapter->hw; 2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2614 2615 if (adapter->msix_entries) { 2616 int vector; 2617 2618 for (vector = 0; vector < adapter->num_vectors; vector++) 2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2620 } else { 2621 ew32(ITR, new_itr); 2622 } 2623 } 2624 2625 /** 2626 * e1000_alloc_queues - Allocate memory for all rings 2627 * @adapter: board private structure to initialize 2628 **/ 2629 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2630 { 2631 int size = sizeof(struct e1000_ring); 2632 2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2634 if (!adapter->tx_ring) 2635 goto err; 2636 adapter->tx_ring->count = adapter->tx_ring_count; 2637 adapter->tx_ring->adapter = adapter; 2638 2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2640 if (!adapter->rx_ring) 2641 goto err; 2642 adapter->rx_ring->count = adapter->rx_ring_count; 2643 adapter->rx_ring->adapter = adapter; 2644 2645 return 0; 2646 err: 2647 e_err("Unable to allocate memory for queues\n"); 2648 kfree(adapter->rx_ring); 2649 kfree(adapter->tx_ring); 2650 return -ENOMEM; 2651 } 2652 2653 /** 2654 * e1000e_poll - NAPI Rx polling callback 2655 * @napi: struct associated with this polling callback 2656 * @weight: number of packets driver is allowed to process this poll 2657 **/ 2658 static int e1000e_poll(struct napi_struct *napi, int weight) 2659 { 2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2661 napi); 2662 struct e1000_hw *hw = &adapter->hw; 2663 struct net_device *poll_dev = adapter->netdev; 2664 int tx_cleaned = 1, work_done = 0; 2665 2666 adapter = netdev_priv(poll_dev); 2667 2668 if (!adapter->msix_entries || 2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2671 2672 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2673 2674 if (!tx_cleaned) 2675 work_done = weight; 2676 2677 /* If weight not fully consumed, exit the polling mode */ 2678 if (work_done < weight) { 2679 if (adapter->itr_setting & 3) 2680 e1000_set_itr(adapter); 2681 napi_complete_done(napi, work_done); 2682 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2683 if (adapter->msix_entries) 2684 ew32(IMS, adapter->rx_ring->ims_val); 2685 else 2686 e1000_irq_enable(adapter); 2687 } 2688 } 2689 2690 return work_done; 2691 } 2692 2693 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2694 __always_unused __be16 proto, u16 vid) 2695 { 2696 struct e1000_adapter *adapter = netdev_priv(netdev); 2697 struct e1000_hw *hw = &adapter->hw; 2698 u32 vfta, index; 2699 2700 /* don't update vlan cookie if already programmed */ 2701 if ((adapter->hw.mng_cookie.status & 2702 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2703 (vid == adapter->mng_vlan_id)) 2704 return 0; 2705 2706 /* add VID to filter table */ 2707 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2708 index = (vid >> 5) & 0x7F; 2709 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2710 vfta |= BIT((vid & 0x1F)); 2711 hw->mac.ops.write_vfta(hw, index, vfta); 2712 } 2713 2714 set_bit(vid, adapter->active_vlans); 2715 2716 return 0; 2717 } 2718 2719 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2720 __always_unused __be16 proto, u16 vid) 2721 { 2722 struct e1000_adapter *adapter = netdev_priv(netdev); 2723 struct e1000_hw *hw = &adapter->hw; 2724 u32 vfta, index; 2725 2726 if ((adapter->hw.mng_cookie.status & 2727 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2728 (vid == adapter->mng_vlan_id)) { 2729 /* release control to f/w */ 2730 e1000e_release_hw_control(adapter); 2731 return 0; 2732 } 2733 2734 /* remove VID from filter table */ 2735 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2736 index = (vid >> 5) & 0x7F; 2737 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2738 vfta &= ~BIT((vid & 0x1F)); 2739 hw->mac.ops.write_vfta(hw, index, vfta); 2740 } 2741 2742 clear_bit(vid, adapter->active_vlans); 2743 2744 return 0; 2745 } 2746 2747 /** 2748 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2749 * @adapter: board private structure to initialize 2750 **/ 2751 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2752 { 2753 struct net_device *netdev = adapter->netdev; 2754 struct e1000_hw *hw = &adapter->hw; 2755 u32 rctl; 2756 2757 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2758 /* disable VLAN receive filtering */ 2759 rctl = er32(RCTL); 2760 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2761 ew32(RCTL, rctl); 2762 2763 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2764 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2765 adapter->mng_vlan_id); 2766 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2767 } 2768 } 2769 } 2770 2771 /** 2772 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2773 * @adapter: board private structure to initialize 2774 **/ 2775 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2776 { 2777 struct e1000_hw *hw = &adapter->hw; 2778 u32 rctl; 2779 2780 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2781 /* enable VLAN receive filtering */ 2782 rctl = er32(RCTL); 2783 rctl |= E1000_RCTL_VFE; 2784 rctl &= ~E1000_RCTL_CFIEN; 2785 ew32(RCTL, rctl); 2786 } 2787 } 2788 2789 /** 2790 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2791 * @adapter: board private structure to initialize 2792 **/ 2793 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2794 { 2795 struct e1000_hw *hw = &adapter->hw; 2796 u32 ctrl; 2797 2798 /* disable VLAN tag insert/strip */ 2799 ctrl = er32(CTRL); 2800 ctrl &= ~E1000_CTRL_VME; 2801 ew32(CTRL, ctrl); 2802 } 2803 2804 /** 2805 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2806 * @adapter: board private structure to initialize 2807 **/ 2808 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2809 { 2810 struct e1000_hw *hw = &adapter->hw; 2811 u32 ctrl; 2812 2813 /* enable VLAN tag insert/strip */ 2814 ctrl = er32(CTRL); 2815 ctrl |= E1000_CTRL_VME; 2816 ew32(CTRL, ctrl); 2817 } 2818 2819 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2820 { 2821 struct net_device *netdev = adapter->netdev; 2822 u16 vid = adapter->hw.mng_cookie.vlan_id; 2823 u16 old_vid = adapter->mng_vlan_id; 2824 2825 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2826 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2827 adapter->mng_vlan_id = vid; 2828 } 2829 2830 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2831 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2832 } 2833 2834 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2835 { 2836 u16 vid; 2837 2838 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2839 2840 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2841 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2842 } 2843 2844 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2845 { 2846 struct e1000_hw *hw = &adapter->hw; 2847 u32 manc, manc2h, mdef, i, j; 2848 2849 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2850 return; 2851 2852 manc = er32(MANC); 2853 2854 /* enable receiving management packets to the host. this will probably 2855 * generate destination unreachable messages from the host OS, but 2856 * the packets will be handled on SMBUS 2857 */ 2858 manc |= E1000_MANC_EN_MNG2HOST; 2859 manc2h = er32(MANC2H); 2860 2861 switch (hw->mac.type) { 2862 default: 2863 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2864 break; 2865 case e1000_82574: 2866 case e1000_82583: 2867 /* Check if IPMI pass-through decision filter already exists; 2868 * if so, enable it. 2869 */ 2870 for (i = 0, j = 0; i < 8; i++) { 2871 mdef = er32(MDEF(i)); 2872 2873 /* Ignore filters with anything other than IPMI ports */ 2874 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2875 continue; 2876 2877 /* Enable this decision filter in MANC2H */ 2878 if (mdef) 2879 manc2h |= BIT(i); 2880 2881 j |= mdef; 2882 } 2883 2884 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2885 break; 2886 2887 /* Create new decision filter in an empty filter */ 2888 for (i = 0, j = 0; i < 8; i++) 2889 if (er32(MDEF(i)) == 0) { 2890 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2891 E1000_MDEF_PORT_664)); 2892 manc2h |= BIT(1); 2893 j++; 2894 break; 2895 } 2896 2897 if (!j) 2898 e_warn("Unable to create IPMI pass-through filter\n"); 2899 break; 2900 } 2901 2902 ew32(MANC2H, manc2h); 2903 ew32(MANC, manc); 2904 } 2905 2906 /** 2907 * e1000_configure_tx - Configure Transmit Unit after Reset 2908 * @adapter: board private structure 2909 * 2910 * Configure the Tx unit of the MAC after a reset. 2911 **/ 2912 static void e1000_configure_tx(struct e1000_adapter *adapter) 2913 { 2914 struct e1000_hw *hw = &adapter->hw; 2915 struct e1000_ring *tx_ring = adapter->tx_ring; 2916 u64 tdba; 2917 u32 tdlen, tctl, tarc; 2918 2919 /* Setup the HW Tx Head and Tail descriptor pointers */ 2920 tdba = tx_ring->dma; 2921 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2922 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2923 ew32(TDBAH(0), (tdba >> 32)); 2924 ew32(TDLEN(0), tdlen); 2925 ew32(TDH(0), 0); 2926 ew32(TDT(0), 0); 2927 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2928 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2929 2930 writel(0, tx_ring->head); 2931 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2932 e1000e_update_tdt_wa(tx_ring, 0); 2933 else 2934 writel(0, tx_ring->tail); 2935 2936 /* Set the Tx Interrupt Delay register */ 2937 ew32(TIDV, adapter->tx_int_delay); 2938 /* Tx irq moderation */ 2939 ew32(TADV, adapter->tx_abs_int_delay); 2940 2941 if (adapter->flags2 & FLAG2_DMA_BURST) { 2942 u32 txdctl = er32(TXDCTL(0)); 2943 2944 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2945 E1000_TXDCTL_WTHRESH); 2946 /* set up some performance related parameters to encourage the 2947 * hardware to use the bus more efficiently in bursts, depends 2948 * on the tx_int_delay to be enabled, 2949 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2950 * hthresh = 1 ==> prefetch when one or more available 2951 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2952 * BEWARE: this seems to work but should be considered first if 2953 * there are Tx hangs or other Tx related bugs 2954 */ 2955 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2956 ew32(TXDCTL(0), txdctl); 2957 } 2958 /* erratum work around: set txdctl the same for both queues */ 2959 ew32(TXDCTL(1), er32(TXDCTL(0))); 2960 2961 /* Program the Transmit Control Register */ 2962 tctl = er32(TCTL); 2963 tctl &= ~E1000_TCTL_CT; 2964 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2965 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2966 2967 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2968 tarc = er32(TARC(0)); 2969 /* set the speed mode bit, we'll clear it if we're not at 2970 * gigabit link later 2971 */ 2972 #define SPEED_MODE_BIT BIT(21) 2973 tarc |= SPEED_MODE_BIT; 2974 ew32(TARC(0), tarc); 2975 } 2976 2977 /* errata: program both queues to unweighted RR */ 2978 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2979 tarc = er32(TARC(0)); 2980 tarc |= 1; 2981 ew32(TARC(0), tarc); 2982 tarc = er32(TARC(1)); 2983 tarc |= 1; 2984 ew32(TARC(1), tarc); 2985 } 2986 2987 /* Setup Transmit Descriptor Settings for eop descriptor */ 2988 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2989 2990 /* only set IDE if we are delaying interrupts using the timers */ 2991 if (adapter->tx_int_delay) 2992 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2993 2994 /* enable Report Status bit */ 2995 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2996 2997 ew32(TCTL, tctl); 2998 2999 hw->mac.ops.config_collision_dist(hw); 3000 3001 /* SPT and CNP Si errata workaround to avoid data corruption */ 3002 if (hw->mac.type >= e1000_pch_spt) { 3003 u32 reg_val; 3004 3005 reg_val = er32(IOSFPC); 3006 reg_val |= E1000_RCTL_RDMTS_HEX; 3007 ew32(IOSFPC, reg_val); 3008 3009 reg_val = er32(TARC(0)); 3010 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 3011 ew32(TARC(0), reg_val); 3012 } 3013 } 3014 3015 /** 3016 * e1000_setup_rctl - configure the receive control registers 3017 * @adapter: Board private structure 3018 **/ 3019 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3020 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3021 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3022 { 3023 struct e1000_hw *hw = &adapter->hw; 3024 u32 rctl, rfctl; 3025 u32 pages = 0; 3026 3027 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3028 * If jumbo frames not set, program related MAC/PHY registers 3029 * to h/w defaults 3030 */ 3031 if (hw->mac.type >= e1000_pch2lan) { 3032 s32 ret_val; 3033 3034 if (adapter->netdev->mtu > ETH_DATA_LEN) 3035 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3036 else 3037 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3038 3039 if (ret_val) 3040 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3041 } 3042 3043 /* Program MC offset vector base */ 3044 rctl = er32(RCTL); 3045 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3046 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3047 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3048 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3049 3050 /* Do not Store bad packets */ 3051 rctl &= ~E1000_RCTL_SBP; 3052 3053 /* Enable Long Packet receive */ 3054 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3055 rctl &= ~E1000_RCTL_LPE; 3056 else 3057 rctl |= E1000_RCTL_LPE; 3058 3059 /* Some systems expect that the CRC is included in SMBUS traffic. The 3060 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3061 * host memory when this is enabled 3062 */ 3063 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3064 rctl |= E1000_RCTL_SECRC; 3065 3066 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3067 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3068 u16 phy_data; 3069 3070 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3071 phy_data &= 0xfff8; 3072 phy_data |= BIT(2); 3073 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3074 3075 e1e_rphy(hw, 22, &phy_data); 3076 phy_data &= 0x0fff; 3077 phy_data |= BIT(14); 3078 e1e_wphy(hw, 0x10, 0x2823); 3079 e1e_wphy(hw, 0x11, 0x0003); 3080 e1e_wphy(hw, 22, phy_data); 3081 } 3082 3083 /* Setup buffer sizes */ 3084 rctl &= ~E1000_RCTL_SZ_4096; 3085 rctl |= E1000_RCTL_BSEX; 3086 switch (adapter->rx_buffer_len) { 3087 case 2048: 3088 default: 3089 rctl |= E1000_RCTL_SZ_2048; 3090 rctl &= ~E1000_RCTL_BSEX; 3091 break; 3092 case 4096: 3093 rctl |= E1000_RCTL_SZ_4096; 3094 break; 3095 case 8192: 3096 rctl |= E1000_RCTL_SZ_8192; 3097 break; 3098 case 16384: 3099 rctl |= E1000_RCTL_SZ_16384; 3100 break; 3101 } 3102 3103 /* Enable Extended Status in all Receive Descriptors */ 3104 rfctl = er32(RFCTL); 3105 rfctl |= E1000_RFCTL_EXTEN; 3106 ew32(RFCTL, rfctl); 3107 3108 /* 82571 and greater support packet-split where the protocol 3109 * header is placed in skb->data and the packet data is 3110 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3111 * In the case of a non-split, skb->data is linearly filled, 3112 * followed by the page buffers. Therefore, skb->data is 3113 * sized to hold the largest protocol header. 3114 * 3115 * allocations using alloc_page take too long for regular MTU 3116 * so only enable packet split for jumbo frames 3117 * 3118 * Using pages when the page size is greater than 16k wastes 3119 * a lot of memory, since we allocate 3 pages at all times 3120 * per packet. 3121 */ 3122 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3123 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3124 adapter->rx_ps_pages = pages; 3125 else 3126 adapter->rx_ps_pages = 0; 3127 3128 if (adapter->rx_ps_pages) { 3129 u32 psrctl = 0; 3130 3131 /* Enable Packet split descriptors */ 3132 rctl |= E1000_RCTL_DTYP_PS; 3133 3134 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3135 3136 switch (adapter->rx_ps_pages) { 3137 case 3: 3138 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3139 /* fall-through */ 3140 case 2: 3141 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3142 /* fall-through */ 3143 case 1: 3144 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3145 break; 3146 } 3147 3148 ew32(PSRCTL, psrctl); 3149 } 3150 3151 /* This is useful for sniffing bad packets. */ 3152 if (adapter->netdev->features & NETIF_F_RXALL) { 3153 /* UPE and MPE will be handled by normal PROMISC logic 3154 * in e1000e_set_rx_mode 3155 */ 3156 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3157 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3158 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3159 3160 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3161 E1000_RCTL_DPF | /* Allow filtered pause */ 3162 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3163 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3164 * and that breaks VLANs. 3165 */ 3166 } 3167 3168 ew32(RCTL, rctl); 3169 /* just started the receive unit, no need to restart */ 3170 adapter->flags &= ~FLAG_RESTART_NOW; 3171 } 3172 3173 /** 3174 * e1000_configure_rx - Configure Receive Unit after Reset 3175 * @adapter: board private structure 3176 * 3177 * Configure the Rx unit of the MAC after a reset. 3178 **/ 3179 static void e1000_configure_rx(struct e1000_adapter *adapter) 3180 { 3181 struct e1000_hw *hw = &adapter->hw; 3182 struct e1000_ring *rx_ring = adapter->rx_ring; 3183 u64 rdba; 3184 u32 rdlen, rctl, rxcsum, ctrl_ext; 3185 3186 if (adapter->rx_ps_pages) { 3187 /* this is a 32 byte descriptor */ 3188 rdlen = rx_ring->count * 3189 sizeof(union e1000_rx_desc_packet_split); 3190 adapter->clean_rx = e1000_clean_rx_irq_ps; 3191 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3192 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3193 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3194 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3195 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3196 } else { 3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3198 adapter->clean_rx = e1000_clean_rx_irq; 3199 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3200 } 3201 3202 /* disable receives while setting up the descriptors */ 3203 rctl = er32(RCTL); 3204 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3205 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3206 e1e_flush(); 3207 usleep_range(10000, 20000); 3208 3209 if (adapter->flags2 & FLAG2_DMA_BURST) { 3210 /* set the writeback threshold (only takes effect if the RDTR 3211 * is set). set GRAN=1 and write back up to 0x4 worth, and 3212 * enable prefetching of 0x20 Rx descriptors 3213 * granularity = 01 3214 * wthresh = 04, 3215 * hthresh = 04, 3216 * pthresh = 0x20 3217 */ 3218 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3219 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3220 3221 /* override the delay timers for enabling bursting, only if 3222 * the value was not set by the user via module options 3223 */ 3224 if (adapter->rx_int_delay == DEFAULT_RDTR) 3225 adapter->rx_int_delay = BURST_RDTR; 3226 if (adapter->rx_abs_int_delay == DEFAULT_RADV) 3227 adapter->rx_abs_int_delay = BURST_RADV; 3228 } 3229 3230 /* set the Receive Delay Timer Register */ 3231 ew32(RDTR, adapter->rx_int_delay); 3232 3233 /* irq moderation */ 3234 ew32(RADV, adapter->rx_abs_int_delay); 3235 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3236 e1000e_write_itr(adapter, adapter->itr); 3237 3238 ctrl_ext = er32(CTRL_EXT); 3239 /* Auto-Mask interrupts upon ICR access */ 3240 ctrl_ext |= E1000_CTRL_EXT_IAME; 3241 ew32(IAM, 0xffffffff); 3242 ew32(CTRL_EXT, ctrl_ext); 3243 e1e_flush(); 3244 3245 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3246 * the Base and Length of the Rx Descriptor Ring 3247 */ 3248 rdba = rx_ring->dma; 3249 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3250 ew32(RDBAH(0), (rdba >> 32)); 3251 ew32(RDLEN(0), rdlen); 3252 ew32(RDH(0), 0); 3253 ew32(RDT(0), 0); 3254 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3255 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3256 3257 writel(0, rx_ring->head); 3258 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3259 e1000e_update_rdt_wa(rx_ring, 0); 3260 else 3261 writel(0, rx_ring->tail); 3262 3263 /* Enable Receive Checksum Offload for TCP and UDP */ 3264 rxcsum = er32(RXCSUM); 3265 if (adapter->netdev->features & NETIF_F_RXCSUM) 3266 rxcsum |= E1000_RXCSUM_TUOFL; 3267 else 3268 rxcsum &= ~E1000_RXCSUM_TUOFL; 3269 ew32(RXCSUM, rxcsum); 3270 3271 /* With jumbo frames, excessive C-state transition latencies result 3272 * in dropped transactions. 3273 */ 3274 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3275 u32 lat = 3276 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3277 adapter->max_frame_size) * 8 / 1000; 3278 3279 if (adapter->flags & FLAG_IS_ICH) { 3280 u32 rxdctl = er32(RXDCTL(0)); 3281 3282 ew32(RXDCTL(0), rxdctl | 0x3); 3283 } 3284 3285 pm_qos_update_request(&adapter->pm_qos_req, lat); 3286 } else { 3287 pm_qos_update_request(&adapter->pm_qos_req, 3288 PM_QOS_DEFAULT_VALUE); 3289 } 3290 3291 /* Enable Receives */ 3292 ew32(RCTL, rctl); 3293 } 3294 3295 /** 3296 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3297 * @netdev: network interface device structure 3298 * 3299 * Writes multicast address list to the MTA hash table. 3300 * Returns: -ENOMEM on failure 3301 * 0 on no addresses written 3302 * X on writing X addresses to MTA 3303 */ 3304 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3305 { 3306 struct e1000_adapter *adapter = netdev_priv(netdev); 3307 struct e1000_hw *hw = &adapter->hw; 3308 struct netdev_hw_addr *ha; 3309 u8 *mta_list; 3310 int i; 3311 3312 if (netdev_mc_empty(netdev)) { 3313 /* nothing to program, so clear mc list */ 3314 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3315 return 0; 3316 } 3317 3318 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3319 if (!mta_list) 3320 return -ENOMEM; 3321 3322 /* update_mc_addr_list expects a packed array of only addresses. */ 3323 i = 0; 3324 netdev_for_each_mc_addr(ha, netdev) 3325 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3326 3327 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3328 kfree(mta_list); 3329 3330 return netdev_mc_count(netdev); 3331 } 3332 3333 /** 3334 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3335 * @netdev: network interface device structure 3336 * 3337 * Writes unicast address list to the RAR table. 3338 * Returns: -ENOMEM on failure/insufficient address space 3339 * 0 on no addresses written 3340 * X on writing X addresses to the RAR table 3341 **/ 3342 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3343 { 3344 struct e1000_adapter *adapter = netdev_priv(netdev); 3345 struct e1000_hw *hw = &adapter->hw; 3346 unsigned int rar_entries; 3347 int count = 0; 3348 3349 rar_entries = hw->mac.ops.rar_get_count(hw); 3350 3351 /* save a rar entry for our hardware address */ 3352 rar_entries--; 3353 3354 /* save a rar entry for the LAA workaround */ 3355 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3356 rar_entries--; 3357 3358 /* return ENOMEM indicating insufficient memory for addresses */ 3359 if (netdev_uc_count(netdev) > rar_entries) 3360 return -ENOMEM; 3361 3362 if (!netdev_uc_empty(netdev) && rar_entries) { 3363 struct netdev_hw_addr *ha; 3364 3365 /* write the addresses in reverse order to avoid write 3366 * combining 3367 */ 3368 netdev_for_each_uc_addr(ha, netdev) { 3369 int ret_val; 3370 3371 if (!rar_entries) 3372 break; 3373 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3374 if (ret_val < 0) 3375 return -ENOMEM; 3376 count++; 3377 } 3378 } 3379 3380 /* zero out the remaining RAR entries not used above */ 3381 for (; rar_entries > 0; rar_entries--) { 3382 ew32(RAH(rar_entries), 0); 3383 ew32(RAL(rar_entries), 0); 3384 } 3385 e1e_flush(); 3386 3387 return count; 3388 } 3389 3390 /** 3391 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3392 * @netdev: network interface device structure 3393 * 3394 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3395 * address list or the network interface flags are updated. This routine is 3396 * responsible for configuring the hardware for proper unicast, multicast, 3397 * promiscuous mode, and all-multi behavior. 3398 **/ 3399 static void e1000e_set_rx_mode(struct net_device *netdev) 3400 { 3401 struct e1000_adapter *adapter = netdev_priv(netdev); 3402 struct e1000_hw *hw = &adapter->hw; 3403 u32 rctl; 3404 3405 if (pm_runtime_suspended(netdev->dev.parent)) 3406 return; 3407 3408 /* Check for Promiscuous and All Multicast modes */ 3409 rctl = er32(RCTL); 3410 3411 /* clear the affected bits */ 3412 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3413 3414 if (netdev->flags & IFF_PROMISC) { 3415 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3416 /* Do not hardware filter VLANs in promisc mode */ 3417 e1000e_vlan_filter_disable(adapter); 3418 } else { 3419 int count; 3420 3421 if (netdev->flags & IFF_ALLMULTI) { 3422 rctl |= E1000_RCTL_MPE; 3423 } else { 3424 /* Write addresses to the MTA, if the attempt fails 3425 * then we should just turn on promiscuous mode so 3426 * that we can at least receive multicast traffic 3427 */ 3428 count = e1000e_write_mc_addr_list(netdev); 3429 if (count < 0) 3430 rctl |= E1000_RCTL_MPE; 3431 } 3432 e1000e_vlan_filter_enable(adapter); 3433 /* Write addresses to available RAR registers, if there is not 3434 * sufficient space to store all the addresses then enable 3435 * unicast promiscuous mode 3436 */ 3437 count = e1000e_write_uc_addr_list(netdev); 3438 if (count < 0) 3439 rctl |= E1000_RCTL_UPE; 3440 } 3441 3442 ew32(RCTL, rctl); 3443 3444 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3445 e1000e_vlan_strip_enable(adapter); 3446 else 3447 e1000e_vlan_strip_disable(adapter); 3448 } 3449 3450 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3451 { 3452 struct e1000_hw *hw = &adapter->hw; 3453 u32 mrqc, rxcsum; 3454 u32 rss_key[10]; 3455 int i; 3456 3457 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3458 for (i = 0; i < 10; i++) 3459 ew32(RSSRK(i), rss_key[i]); 3460 3461 /* Direct all traffic to queue 0 */ 3462 for (i = 0; i < 32; i++) 3463 ew32(RETA(i), 0); 3464 3465 /* Disable raw packet checksumming so that RSS hash is placed in 3466 * descriptor on writeback. 3467 */ 3468 rxcsum = er32(RXCSUM); 3469 rxcsum |= E1000_RXCSUM_PCSD; 3470 3471 ew32(RXCSUM, rxcsum); 3472 3473 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3474 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3475 E1000_MRQC_RSS_FIELD_IPV6 | 3476 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3477 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3478 3479 ew32(MRQC, mrqc); 3480 } 3481 3482 /** 3483 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3484 * @adapter: board private structure 3485 * @timinca: pointer to returned time increment attributes 3486 * 3487 * Get attributes for incrementing the System Time Register SYSTIML/H at 3488 * the default base frequency, and set the cyclecounter shift value. 3489 **/ 3490 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3491 { 3492 struct e1000_hw *hw = &adapter->hw; 3493 u32 incvalue, incperiod, shift; 3494 3495 /* Make sure clock is enabled on I217/I218/I219 before checking 3496 * the frequency 3497 */ 3498 if ((hw->mac.type >= e1000_pch_lpt) && 3499 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3500 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3501 u32 fextnvm7 = er32(FEXTNVM7); 3502 3503 if (!(fextnvm7 & BIT(0))) { 3504 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3505 e1e_flush(); 3506 } 3507 } 3508 3509 switch (hw->mac.type) { 3510 case e1000_pch2lan: 3511 /* Stable 96MHz frequency */ 3512 incperiod = INCPERIOD_96MHZ; 3513 incvalue = INCVALUE_96MHZ; 3514 shift = INCVALUE_SHIFT_96MHZ; 3515 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3516 break; 3517 case e1000_pch_lpt: 3518 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3519 /* Stable 96MHz frequency */ 3520 incperiod = INCPERIOD_96MHZ; 3521 incvalue = INCVALUE_96MHZ; 3522 shift = INCVALUE_SHIFT_96MHZ; 3523 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3524 } else { 3525 /* Stable 25MHz frequency */ 3526 incperiod = INCPERIOD_25MHZ; 3527 incvalue = INCVALUE_25MHZ; 3528 shift = INCVALUE_SHIFT_25MHZ; 3529 adapter->cc.shift = shift; 3530 } 3531 break; 3532 case e1000_pch_spt: 3533 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3534 /* Stable 24MHz frequency */ 3535 incperiod = INCPERIOD_24MHZ; 3536 incvalue = INCVALUE_24MHZ; 3537 shift = INCVALUE_SHIFT_24MHZ; 3538 adapter->cc.shift = shift; 3539 break; 3540 } 3541 return -EINVAL; 3542 case e1000_pch_cnp: 3543 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3544 /* Stable 24MHz frequency */ 3545 incperiod = INCPERIOD_24MHZ; 3546 incvalue = INCVALUE_24MHZ; 3547 shift = INCVALUE_SHIFT_24MHZ; 3548 adapter->cc.shift = shift; 3549 } else { 3550 /* Stable 38400KHz frequency */ 3551 incperiod = INCPERIOD_38400KHZ; 3552 incvalue = INCVALUE_38400KHZ; 3553 shift = INCVALUE_SHIFT_38400KHZ; 3554 adapter->cc.shift = shift; 3555 } 3556 break; 3557 case e1000_82574: 3558 case e1000_82583: 3559 /* Stable 25MHz frequency */ 3560 incperiod = INCPERIOD_25MHZ; 3561 incvalue = INCVALUE_25MHZ; 3562 shift = INCVALUE_SHIFT_25MHZ; 3563 adapter->cc.shift = shift; 3564 break; 3565 default: 3566 return -EINVAL; 3567 } 3568 3569 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3570 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3571 3572 return 0; 3573 } 3574 3575 /** 3576 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3577 * @adapter: board private structure 3578 * 3579 * Outgoing time stamping can be enabled and disabled. Play nice and 3580 * disable it when requested, although it shouldn't cause any overhead 3581 * when no packet needs it. At most one packet in the queue may be 3582 * marked for time stamping, otherwise it would be impossible to tell 3583 * for sure to which packet the hardware time stamp belongs. 3584 * 3585 * Incoming time stamping has to be configured via the hardware filters. 3586 * Not all combinations are supported, in particular event type has to be 3587 * specified. Matching the kind of event packet is not supported, with the 3588 * exception of "all V2 events regardless of level 2 or 4". 3589 **/ 3590 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3591 struct hwtstamp_config *config) 3592 { 3593 struct e1000_hw *hw = &adapter->hw; 3594 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3595 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3596 u32 rxmtrl = 0; 3597 u16 rxudp = 0; 3598 bool is_l4 = false; 3599 bool is_l2 = false; 3600 u32 regval; 3601 3602 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3603 return -EINVAL; 3604 3605 /* flags reserved for future extensions - must be zero */ 3606 if (config->flags) 3607 return -EINVAL; 3608 3609 switch (config->tx_type) { 3610 case HWTSTAMP_TX_OFF: 3611 tsync_tx_ctl = 0; 3612 break; 3613 case HWTSTAMP_TX_ON: 3614 break; 3615 default: 3616 return -ERANGE; 3617 } 3618 3619 switch (config->rx_filter) { 3620 case HWTSTAMP_FILTER_NONE: 3621 tsync_rx_ctl = 0; 3622 break; 3623 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3625 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3626 is_l4 = true; 3627 break; 3628 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3629 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3630 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3631 is_l4 = true; 3632 break; 3633 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3634 /* Also time stamps V2 L2 Path Delay Request/Response */ 3635 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3636 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3637 is_l2 = true; 3638 break; 3639 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3640 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3641 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3642 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3643 is_l2 = true; 3644 break; 3645 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3646 /* Hardware cannot filter just V2 L4 Sync messages; 3647 * fall-through to V2 (both L2 and L4) Sync. 3648 */ 3649 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3650 /* Also time stamps V2 Path Delay Request/Response. */ 3651 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3652 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3653 is_l2 = true; 3654 is_l4 = true; 3655 break; 3656 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3657 /* Hardware cannot filter just V2 L4 Delay Request messages; 3658 * fall-through to V2 (both L2 and L4) Delay Request. 3659 */ 3660 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3661 /* Also time stamps V2 Path Delay Request/Response. */ 3662 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3663 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3664 is_l2 = true; 3665 is_l4 = true; 3666 break; 3667 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3668 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3669 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3670 * fall-through to all V2 (both L2 and L4) Events. 3671 */ 3672 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3673 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3674 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3675 is_l2 = true; 3676 is_l4 = true; 3677 break; 3678 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3679 /* For V1, the hardware can only filter Sync messages or 3680 * Delay Request messages but not both so fall-through to 3681 * time stamp all packets. 3682 */ 3683 case HWTSTAMP_FILTER_ALL: 3684 is_l2 = true; 3685 is_l4 = true; 3686 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3687 config->rx_filter = HWTSTAMP_FILTER_ALL; 3688 break; 3689 default: 3690 return -ERANGE; 3691 } 3692 3693 adapter->hwtstamp_config = *config; 3694 3695 /* enable/disable Tx h/w time stamping */ 3696 regval = er32(TSYNCTXCTL); 3697 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3698 regval |= tsync_tx_ctl; 3699 ew32(TSYNCTXCTL, regval); 3700 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3701 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3702 e_err("Timesync Tx Control register not set as expected\n"); 3703 return -EAGAIN; 3704 } 3705 3706 /* enable/disable Rx h/w time stamping */ 3707 regval = er32(TSYNCRXCTL); 3708 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3709 regval |= tsync_rx_ctl; 3710 ew32(TSYNCRXCTL, regval); 3711 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3712 E1000_TSYNCRXCTL_TYPE_MASK)) != 3713 (regval & (E1000_TSYNCRXCTL_ENABLED | 3714 E1000_TSYNCRXCTL_TYPE_MASK))) { 3715 e_err("Timesync Rx Control register not set as expected\n"); 3716 return -EAGAIN; 3717 } 3718 3719 /* L2: define ethertype filter for time stamped packets */ 3720 if (is_l2) 3721 rxmtrl |= ETH_P_1588; 3722 3723 /* define which PTP packets get time stamped */ 3724 ew32(RXMTRL, rxmtrl); 3725 3726 /* Filter by destination port */ 3727 if (is_l4) { 3728 rxudp = PTP_EV_PORT; 3729 cpu_to_be16s(&rxudp); 3730 } 3731 ew32(RXUDP, rxudp); 3732 3733 e1e_flush(); 3734 3735 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3736 er32(RXSTMPH); 3737 er32(TXSTMPH); 3738 3739 return 0; 3740 } 3741 3742 /** 3743 * e1000_configure - configure the hardware for Rx and Tx 3744 * @adapter: private board structure 3745 **/ 3746 static void e1000_configure(struct e1000_adapter *adapter) 3747 { 3748 struct e1000_ring *rx_ring = adapter->rx_ring; 3749 3750 e1000e_set_rx_mode(adapter->netdev); 3751 3752 e1000_restore_vlan(adapter); 3753 e1000_init_manageability_pt(adapter); 3754 3755 e1000_configure_tx(adapter); 3756 3757 if (adapter->netdev->features & NETIF_F_RXHASH) 3758 e1000e_setup_rss_hash(adapter); 3759 e1000_setup_rctl(adapter); 3760 e1000_configure_rx(adapter); 3761 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3762 } 3763 3764 /** 3765 * e1000e_power_up_phy - restore link in case the phy was powered down 3766 * @adapter: address of board private structure 3767 * 3768 * The phy may be powered down to save power and turn off link when the 3769 * driver is unloaded and wake on lan is not enabled (among others) 3770 * *** this routine MUST be followed by a call to e1000e_reset *** 3771 **/ 3772 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3773 { 3774 if (adapter->hw.phy.ops.power_up) 3775 adapter->hw.phy.ops.power_up(&adapter->hw); 3776 3777 adapter->hw.mac.ops.setup_link(&adapter->hw); 3778 } 3779 3780 /** 3781 * e1000_power_down_phy - Power down the PHY 3782 * 3783 * Power down the PHY so no link is implied when interface is down. 3784 * The PHY cannot be powered down if management or WoL is active. 3785 */ 3786 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3787 { 3788 if (adapter->hw.phy.ops.power_down) 3789 adapter->hw.phy.ops.power_down(&adapter->hw); 3790 } 3791 3792 /** 3793 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3794 * 3795 * We want to clear all pending descriptors from the TX ring. 3796 * zeroing happens when the HW reads the regs. We assign the ring itself as 3797 * the data of the next descriptor. We don't care about the data we are about 3798 * to reset the HW. 3799 */ 3800 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3801 { 3802 struct e1000_hw *hw = &adapter->hw; 3803 struct e1000_ring *tx_ring = adapter->tx_ring; 3804 struct e1000_tx_desc *tx_desc = NULL; 3805 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3806 u16 size = 512; 3807 3808 tctl = er32(TCTL); 3809 ew32(TCTL, tctl | E1000_TCTL_EN); 3810 tdt = er32(TDT(0)); 3811 BUG_ON(tdt != tx_ring->next_to_use); 3812 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3813 tx_desc->buffer_addr = tx_ring->dma; 3814 3815 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3816 tx_desc->upper.data = 0; 3817 /* flush descriptors to memory before notifying the HW */ 3818 wmb(); 3819 tx_ring->next_to_use++; 3820 if (tx_ring->next_to_use == tx_ring->count) 3821 tx_ring->next_to_use = 0; 3822 ew32(TDT(0), tx_ring->next_to_use); 3823 mmiowb(); 3824 usleep_range(200, 250); 3825 } 3826 3827 /** 3828 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3829 * 3830 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3831 */ 3832 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3833 { 3834 u32 rctl, rxdctl; 3835 struct e1000_hw *hw = &adapter->hw; 3836 3837 rctl = er32(RCTL); 3838 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3839 e1e_flush(); 3840 usleep_range(100, 150); 3841 3842 rxdctl = er32(RXDCTL(0)); 3843 /* zero the lower 14 bits (prefetch and host thresholds) */ 3844 rxdctl &= 0xffffc000; 3845 3846 /* update thresholds: prefetch threshold to 31, host threshold to 1 3847 * and make sure the granularity is "descriptors" and not "cache lines" 3848 */ 3849 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3850 3851 ew32(RXDCTL(0), rxdctl); 3852 /* momentarily enable the RX ring for the changes to take effect */ 3853 ew32(RCTL, rctl | E1000_RCTL_EN); 3854 e1e_flush(); 3855 usleep_range(100, 150); 3856 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3857 } 3858 3859 /** 3860 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3861 * 3862 * In i219, the descriptor rings must be emptied before resetting the HW 3863 * or before changing the device state to D3 during runtime (runtime PM). 3864 * 3865 * Failure to do this will cause the HW to enter a unit hang state which can 3866 * only be released by PCI reset on the device 3867 * 3868 */ 3869 3870 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3871 { 3872 u16 hang_state; 3873 u32 fext_nvm11, tdlen; 3874 struct e1000_hw *hw = &adapter->hw; 3875 3876 /* First, disable MULR fix in FEXTNVM11 */ 3877 fext_nvm11 = er32(FEXTNVM11); 3878 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3879 ew32(FEXTNVM11, fext_nvm11); 3880 /* do nothing if we're not in faulty state, or if the queue is empty */ 3881 tdlen = er32(TDLEN(0)); 3882 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3883 &hang_state); 3884 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3885 return; 3886 e1000_flush_tx_ring(adapter); 3887 /* recheck, maybe the fault is caused by the rx ring */ 3888 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3889 &hang_state); 3890 if (hang_state & FLUSH_DESC_REQUIRED) 3891 e1000_flush_rx_ring(adapter); 3892 } 3893 3894 /** 3895 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3896 * @adapter: board private structure 3897 * 3898 * When the MAC is reset, all hardware bits for timesync will be reset to the 3899 * default values. This function will restore the settings last in place. 3900 * Since the clock SYSTIME registers are reset, we will simply restore the 3901 * cyclecounter to the kernel real clock time. 3902 **/ 3903 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3904 { 3905 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3906 struct e1000_hw *hw = &adapter->hw; 3907 unsigned long flags; 3908 u32 timinca; 3909 s32 ret_val; 3910 3911 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3912 return; 3913 3914 if (info->adjfreq) { 3915 /* restore the previous ptp frequency delta */ 3916 ret_val = info->adjfreq(info, adapter->ptp_delta); 3917 } else { 3918 /* set the default base frequency if no adjustment possible */ 3919 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3920 if (!ret_val) 3921 ew32(TIMINCA, timinca); 3922 } 3923 3924 if (ret_val) { 3925 dev_warn(&adapter->pdev->dev, 3926 "Failed to restore TIMINCA clock rate delta: %d\n", 3927 ret_val); 3928 return; 3929 } 3930 3931 /* reset the systim ns time counter */ 3932 spin_lock_irqsave(&adapter->systim_lock, flags); 3933 timecounter_init(&adapter->tc, &adapter->cc, 3934 ktime_to_ns(ktime_get_real())); 3935 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3936 3937 /* restore the previous hwtstamp configuration settings */ 3938 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3939 } 3940 3941 /** 3942 * e1000e_reset - bring the hardware into a known good state 3943 * 3944 * This function boots the hardware and enables some settings that 3945 * require a configuration cycle of the hardware - those cannot be 3946 * set/changed during runtime. After reset the device needs to be 3947 * properly configured for Rx, Tx etc. 3948 */ 3949 void e1000e_reset(struct e1000_adapter *adapter) 3950 { 3951 struct e1000_mac_info *mac = &adapter->hw.mac; 3952 struct e1000_fc_info *fc = &adapter->hw.fc; 3953 struct e1000_hw *hw = &adapter->hw; 3954 u32 tx_space, min_tx_space, min_rx_space; 3955 u32 pba = adapter->pba; 3956 u16 hwm; 3957 3958 /* reset Packet Buffer Allocation to default */ 3959 ew32(PBA, pba); 3960 3961 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3962 /* To maintain wire speed transmits, the Tx FIFO should be 3963 * large enough to accommodate two full transmit packets, 3964 * rounded up to the next 1KB and expressed in KB. Likewise, 3965 * the Rx FIFO should be large enough to accommodate at least 3966 * one full receive packet and is similarly rounded up and 3967 * expressed in KB. 3968 */ 3969 pba = er32(PBA); 3970 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3971 tx_space = pba >> 16; 3972 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3973 pba &= 0xffff; 3974 /* the Tx fifo also stores 16 bytes of information about the Tx 3975 * but don't include ethernet FCS because hardware appends it 3976 */ 3977 min_tx_space = (adapter->max_frame_size + 3978 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3979 min_tx_space = ALIGN(min_tx_space, 1024); 3980 min_tx_space >>= 10; 3981 /* software strips receive CRC, so leave room for it */ 3982 min_rx_space = adapter->max_frame_size; 3983 min_rx_space = ALIGN(min_rx_space, 1024); 3984 min_rx_space >>= 10; 3985 3986 /* If current Tx allocation is less than the min Tx FIFO size, 3987 * and the min Tx FIFO size is less than the current Rx FIFO 3988 * allocation, take space away from current Rx allocation 3989 */ 3990 if ((tx_space < min_tx_space) && 3991 ((min_tx_space - tx_space) < pba)) { 3992 pba -= min_tx_space - tx_space; 3993 3994 /* if short on Rx space, Rx wins and must trump Tx 3995 * adjustment 3996 */ 3997 if (pba < min_rx_space) 3998 pba = min_rx_space; 3999 } 4000 4001 ew32(PBA, pba); 4002 } 4003 4004 /* flow control settings 4005 * 4006 * The high water mark must be low enough to fit one full frame 4007 * (or the size used for early receive) above it in the Rx FIFO. 4008 * Set it to the lower of: 4009 * - 90% of the Rx FIFO size, and 4010 * - the full Rx FIFO size minus one full frame 4011 */ 4012 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4013 fc->pause_time = 0xFFFF; 4014 else 4015 fc->pause_time = E1000_FC_PAUSE_TIME; 4016 fc->send_xon = true; 4017 fc->current_mode = fc->requested_mode; 4018 4019 switch (hw->mac.type) { 4020 case e1000_ich9lan: 4021 case e1000_ich10lan: 4022 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4023 pba = 14; 4024 ew32(PBA, pba); 4025 fc->high_water = 0x2800; 4026 fc->low_water = fc->high_water - 8; 4027 break; 4028 } 4029 /* fall-through */ 4030 default: 4031 hwm = min(((pba << 10) * 9 / 10), 4032 ((pba << 10) - adapter->max_frame_size)); 4033 4034 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4035 fc->low_water = fc->high_water - 8; 4036 break; 4037 case e1000_pchlan: 4038 /* Workaround PCH LOM adapter hangs with certain network 4039 * loads. If hangs persist, try disabling Tx flow control. 4040 */ 4041 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4042 fc->high_water = 0x3500; 4043 fc->low_water = 0x1500; 4044 } else { 4045 fc->high_water = 0x5000; 4046 fc->low_water = 0x3000; 4047 } 4048 fc->refresh_time = 0x1000; 4049 break; 4050 case e1000_pch2lan: 4051 case e1000_pch_lpt: 4052 case e1000_pch_spt: 4053 case e1000_pch_cnp: 4054 fc->refresh_time = 0x0400; 4055 4056 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4057 fc->high_water = 0x05C20; 4058 fc->low_water = 0x05048; 4059 fc->pause_time = 0x0650; 4060 break; 4061 } 4062 4063 pba = 14; 4064 ew32(PBA, pba); 4065 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4066 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4067 break; 4068 } 4069 4070 /* Alignment of Tx data is on an arbitrary byte boundary with the 4071 * maximum size per Tx descriptor limited only to the transmit 4072 * allocation of the packet buffer minus 96 bytes with an upper 4073 * limit of 24KB due to receive synchronization limitations. 4074 */ 4075 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4076 24 << 10); 4077 4078 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4079 * fit in receive buffer. 4080 */ 4081 if (adapter->itr_setting & 0x3) { 4082 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4083 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4084 dev_info(&adapter->pdev->dev, 4085 "Interrupt Throttle Rate off\n"); 4086 adapter->flags2 |= FLAG2_DISABLE_AIM; 4087 e1000e_write_itr(adapter, 0); 4088 } 4089 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4090 dev_info(&adapter->pdev->dev, 4091 "Interrupt Throttle Rate on\n"); 4092 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4093 adapter->itr = 20000; 4094 e1000e_write_itr(adapter, adapter->itr); 4095 } 4096 } 4097 4098 if (hw->mac.type >= e1000_pch_spt) 4099 e1000_flush_desc_rings(adapter); 4100 /* Allow time for pending master requests to run */ 4101 mac->ops.reset_hw(hw); 4102 4103 /* For parts with AMT enabled, let the firmware know 4104 * that the network interface is in control 4105 */ 4106 if (adapter->flags & FLAG_HAS_AMT) 4107 e1000e_get_hw_control(adapter); 4108 4109 ew32(WUC, 0); 4110 4111 if (mac->ops.init_hw(hw)) 4112 e_err("Hardware Error\n"); 4113 4114 e1000_update_mng_vlan(adapter); 4115 4116 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4117 ew32(VET, ETH_P_8021Q); 4118 4119 e1000e_reset_adaptive(hw); 4120 4121 /* restore systim and hwtstamp settings */ 4122 e1000e_systim_reset(adapter); 4123 4124 /* Set EEE advertisement as appropriate */ 4125 if (adapter->flags2 & FLAG2_HAS_EEE) { 4126 s32 ret_val; 4127 u16 adv_addr; 4128 4129 switch (hw->phy.type) { 4130 case e1000_phy_82579: 4131 adv_addr = I82579_EEE_ADVERTISEMENT; 4132 break; 4133 case e1000_phy_i217: 4134 adv_addr = I217_EEE_ADVERTISEMENT; 4135 break; 4136 default: 4137 dev_err(&adapter->pdev->dev, 4138 "Invalid PHY type setting EEE advertisement\n"); 4139 return; 4140 } 4141 4142 ret_val = hw->phy.ops.acquire(hw); 4143 if (ret_val) { 4144 dev_err(&adapter->pdev->dev, 4145 "EEE advertisement - unable to acquire PHY\n"); 4146 return; 4147 } 4148 4149 e1000_write_emi_reg_locked(hw, adv_addr, 4150 hw->dev_spec.ich8lan.eee_disable ? 4151 0 : adapter->eee_advert); 4152 4153 hw->phy.ops.release(hw); 4154 } 4155 4156 if (!netif_running(adapter->netdev) && 4157 !test_bit(__E1000_TESTING, &adapter->state)) 4158 e1000_power_down_phy(adapter); 4159 4160 e1000_get_phy_info(hw); 4161 4162 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4163 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4164 u16 phy_data = 0; 4165 /* speed up time to link by disabling smart power down, ignore 4166 * the return value of this function because there is nothing 4167 * different we would do if it failed 4168 */ 4169 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4170 phy_data &= ~IGP02E1000_PM_SPD; 4171 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4172 } 4173 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4174 u32 reg; 4175 4176 /* Fextnvm7 @ 0xe4[2] = 1 */ 4177 reg = er32(FEXTNVM7); 4178 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4179 ew32(FEXTNVM7, reg); 4180 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4181 reg = er32(FEXTNVM9); 4182 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4183 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4184 ew32(FEXTNVM9, reg); 4185 } 4186 4187 } 4188 4189 /** 4190 * e1000e_trigger_lsc - trigger an LSC interrupt 4191 * @adapter: 4192 * 4193 * Fire a link status change interrupt to start the watchdog. 4194 **/ 4195 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4196 { 4197 struct e1000_hw *hw = &adapter->hw; 4198 4199 if (adapter->msix_entries) 4200 ew32(ICS, E1000_ICS_OTHER); 4201 else 4202 ew32(ICS, E1000_ICS_LSC); 4203 } 4204 4205 void e1000e_up(struct e1000_adapter *adapter) 4206 { 4207 /* hardware has been reset, we need to reload some things */ 4208 e1000_configure(adapter); 4209 4210 clear_bit(__E1000_DOWN, &adapter->state); 4211 4212 if (adapter->msix_entries) 4213 e1000_configure_msix(adapter); 4214 e1000_irq_enable(adapter); 4215 4216 netif_start_queue(adapter->netdev); 4217 4218 e1000e_trigger_lsc(adapter); 4219 } 4220 4221 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4222 { 4223 struct e1000_hw *hw = &adapter->hw; 4224 4225 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4226 return; 4227 4228 /* flush pending descriptor writebacks to memory */ 4229 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4230 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4231 4232 /* execute the writes immediately */ 4233 e1e_flush(); 4234 4235 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4236 * write is successful 4237 */ 4238 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4239 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4240 4241 /* execute the writes immediately */ 4242 e1e_flush(); 4243 } 4244 4245 static void e1000e_update_stats(struct e1000_adapter *adapter); 4246 4247 /** 4248 * e1000e_down - quiesce the device and optionally reset the hardware 4249 * @adapter: board private structure 4250 * @reset: boolean flag to reset the hardware or not 4251 */ 4252 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4253 { 4254 struct net_device *netdev = adapter->netdev; 4255 struct e1000_hw *hw = &adapter->hw; 4256 u32 tctl, rctl; 4257 4258 /* signal that we're down so the interrupt handler does not 4259 * reschedule our watchdog timer 4260 */ 4261 set_bit(__E1000_DOWN, &adapter->state); 4262 4263 netif_carrier_off(netdev); 4264 4265 /* disable receives in the hardware */ 4266 rctl = er32(RCTL); 4267 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4268 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4269 /* flush and sleep below */ 4270 4271 netif_stop_queue(netdev); 4272 4273 /* disable transmits in the hardware */ 4274 tctl = er32(TCTL); 4275 tctl &= ~E1000_TCTL_EN; 4276 ew32(TCTL, tctl); 4277 4278 /* flush both disables and wait for them to finish */ 4279 e1e_flush(); 4280 usleep_range(10000, 20000); 4281 4282 e1000_irq_disable(adapter); 4283 4284 napi_synchronize(&adapter->napi); 4285 4286 del_timer_sync(&adapter->watchdog_timer); 4287 del_timer_sync(&adapter->phy_info_timer); 4288 4289 spin_lock(&adapter->stats64_lock); 4290 e1000e_update_stats(adapter); 4291 spin_unlock(&adapter->stats64_lock); 4292 4293 e1000e_flush_descriptors(adapter); 4294 4295 adapter->link_speed = 0; 4296 adapter->link_duplex = 0; 4297 4298 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4299 if ((hw->mac.type >= e1000_pch2lan) && 4300 (adapter->netdev->mtu > ETH_DATA_LEN) && 4301 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4302 e_dbg("failed to disable jumbo frame workaround mode\n"); 4303 4304 if (!pci_channel_offline(adapter->pdev)) { 4305 if (reset) 4306 e1000e_reset(adapter); 4307 else if (hw->mac.type >= e1000_pch_spt) 4308 e1000_flush_desc_rings(adapter); 4309 } 4310 e1000_clean_tx_ring(adapter->tx_ring); 4311 e1000_clean_rx_ring(adapter->rx_ring); 4312 } 4313 4314 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4315 { 4316 might_sleep(); 4317 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4318 usleep_range(1000, 2000); 4319 e1000e_down(adapter, true); 4320 e1000e_up(adapter); 4321 clear_bit(__E1000_RESETTING, &adapter->state); 4322 } 4323 4324 /** 4325 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4326 * @hw: pointer to the HW structure 4327 * @systim: time value read, sanitized and returned 4328 * 4329 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4330 * check to see that the time is incrementing at a reasonable 4331 * rate and is a multiple of incvalue. 4332 **/ 4333 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim) 4334 { 4335 u64 time_delta, rem, temp; 4336 u64 systim_next; 4337 u32 incvalue; 4338 int i; 4339 4340 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4341 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4342 /* latch SYSTIMH on read of SYSTIML */ 4343 systim_next = (u64)er32(SYSTIML); 4344 systim_next |= (u64)er32(SYSTIMH) << 32; 4345 4346 time_delta = systim_next - systim; 4347 temp = time_delta; 4348 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4349 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4350 4351 systim = systim_next; 4352 4353 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4354 break; 4355 } 4356 4357 return systim; 4358 } 4359 4360 /** 4361 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4362 * @cc: cyclecounter structure 4363 **/ 4364 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4365 { 4366 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4367 cc); 4368 struct e1000_hw *hw = &adapter->hw; 4369 u32 systimel, systimeh; 4370 u64 systim; 4371 /* SYSTIMH latching upon SYSTIML read does not work well. 4372 * This means that if SYSTIML overflows after we read it but before 4373 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4374 * will experience a huge non linear increment in the systime value 4375 * to fix that we test for overflow and if true, we re-read systime. 4376 */ 4377 systimel = er32(SYSTIML); 4378 systimeh = er32(SYSTIMH); 4379 /* Is systimel is so large that overflow is possible? */ 4380 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4381 u32 systimel_2 = er32(SYSTIML); 4382 if (systimel > systimel_2) { 4383 /* There was an overflow, read again SYSTIMH, and use 4384 * systimel_2 4385 */ 4386 systimeh = er32(SYSTIMH); 4387 systimel = systimel_2; 4388 } 4389 } 4390 systim = (u64)systimel; 4391 systim |= (u64)systimeh << 32; 4392 4393 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4394 systim = e1000e_sanitize_systim(hw, systim); 4395 4396 return systim; 4397 } 4398 4399 /** 4400 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4401 * @adapter: board private structure to initialize 4402 * 4403 * e1000_sw_init initializes the Adapter private data structure. 4404 * Fields are initialized based on PCI device information and 4405 * OS network device settings (MTU size). 4406 **/ 4407 static int e1000_sw_init(struct e1000_adapter *adapter) 4408 { 4409 struct net_device *netdev = adapter->netdev; 4410 4411 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4412 adapter->rx_ps_bsize0 = 128; 4413 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4414 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4415 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4416 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4417 4418 spin_lock_init(&adapter->stats64_lock); 4419 4420 e1000e_set_interrupt_capability(adapter); 4421 4422 if (e1000_alloc_queues(adapter)) 4423 return -ENOMEM; 4424 4425 /* Setup hardware time stamping cyclecounter */ 4426 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4427 adapter->cc.read = e1000e_cyclecounter_read; 4428 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4429 adapter->cc.mult = 1; 4430 /* cc.shift set in e1000e_get_base_tininca() */ 4431 4432 spin_lock_init(&adapter->systim_lock); 4433 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4434 } 4435 4436 /* Explicitly disable IRQ since the NIC can be in any state. */ 4437 e1000_irq_disable(adapter); 4438 4439 set_bit(__E1000_DOWN, &adapter->state); 4440 return 0; 4441 } 4442 4443 /** 4444 * e1000_intr_msi_test - Interrupt Handler 4445 * @irq: interrupt number 4446 * @data: pointer to a network interface device structure 4447 **/ 4448 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4449 { 4450 struct net_device *netdev = data; 4451 struct e1000_adapter *adapter = netdev_priv(netdev); 4452 struct e1000_hw *hw = &adapter->hw; 4453 u32 icr = er32(ICR); 4454 4455 e_dbg("icr is %08X\n", icr); 4456 if (icr & E1000_ICR_RXSEQ) { 4457 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4458 /* Force memory writes to complete before acknowledging the 4459 * interrupt is handled. 4460 */ 4461 wmb(); 4462 } 4463 4464 return IRQ_HANDLED; 4465 } 4466 4467 /** 4468 * e1000_test_msi_interrupt - Returns 0 for successful test 4469 * @adapter: board private struct 4470 * 4471 * code flow taken from tg3.c 4472 **/ 4473 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4474 { 4475 struct net_device *netdev = adapter->netdev; 4476 struct e1000_hw *hw = &adapter->hw; 4477 int err; 4478 4479 /* poll_enable hasn't been called yet, so don't need disable */ 4480 /* clear any pending events */ 4481 er32(ICR); 4482 4483 /* free the real vector and request a test handler */ 4484 e1000_free_irq(adapter); 4485 e1000e_reset_interrupt_capability(adapter); 4486 4487 /* Assume that the test fails, if it succeeds then the test 4488 * MSI irq handler will unset this flag 4489 */ 4490 adapter->flags |= FLAG_MSI_TEST_FAILED; 4491 4492 err = pci_enable_msi(adapter->pdev); 4493 if (err) 4494 goto msi_test_failed; 4495 4496 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4497 netdev->name, netdev); 4498 if (err) { 4499 pci_disable_msi(adapter->pdev); 4500 goto msi_test_failed; 4501 } 4502 4503 /* Force memory writes to complete before enabling and firing an 4504 * interrupt. 4505 */ 4506 wmb(); 4507 4508 e1000_irq_enable(adapter); 4509 4510 /* fire an unusual interrupt on the test handler */ 4511 ew32(ICS, E1000_ICS_RXSEQ); 4512 e1e_flush(); 4513 msleep(100); 4514 4515 e1000_irq_disable(adapter); 4516 4517 rmb(); /* read flags after interrupt has been fired */ 4518 4519 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4520 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4521 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4522 } else { 4523 e_dbg("MSI interrupt test succeeded!\n"); 4524 } 4525 4526 free_irq(adapter->pdev->irq, netdev); 4527 pci_disable_msi(adapter->pdev); 4528 4529 msi_test_failed: 4530 e1000e_set_interrupt_capability(adapter); 4531 return e1000_request_irq(adapter); 4532 } 4533 4534 /** 4535 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4536 * @adapter: board private struct 4537 * 4538 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4539 **/ 4540 static int e1000_test_msi(struct e1000_adapter *adapter) 4541 { 4542 int err; 4543 u16 pci_cmd; 4544 4545 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4546 return 0; 4547 4548 /* disable SERR in case the MSI write causes a master abort */ 4549 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4550 if (pci_cmd & PCI_COMMAND_SERR) 4551 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4552 pci_cmd & ~PCI_COMMAND_SERR); 4553 4554 err = e1000_test_msi_interrupt(adapter); 4555 4556 /* re-enable SERR */ 4557 if (pci_cmd & PCI_COMMAND_SERR) { 4558 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4559 pci_cmd |= PCI_COMMAND_SERR; 4560 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4561 } 4562 4563 return err; 4564 } 4565 4566 /** 4567 * e1000e_open - Called when a network interface is made active 4568 * @netdev: network interface device structure 4569 * 4570 * Returns 0 on success, negative value on failure 4571 * 4572 * The open entry point is called when a network interface is made 4573 * active by the system (IFF_UP). At this point all resources needed 4574 * for transmit and receive operations are allocated, the interrupt 4575 * handler is registered with the OS, the watchdog timer is started, 4576 * and the stack is notified that the interface is ready. 4577 **/ 4578 int e1000e_open(struct net_device *netdev) 4579 { 4580 struct e1000_adapter *adapter = netdev_priv(netdev); 4581 struct e1000_hw *hw = &adapter->hw; 4582 struct pci_dev *pdev = adapter->pdev; 4583 int err; 4584 4585 /* disallow open during test */ 4586 if (test_bit(__E1000_TESTING, &adapter->state)) 4587 return -EBUSY; 4588 4589 pm_runtime_get_sync(&pdev->dev); 4590 4591 netif_carrier_off(netdev); 4592 4593 /* allocate transmit descriptors */ 4594 err = e1000e_setup_tx_resources(adapter->tx_ring); 4595 if (err) 4596 goto err_setup_tx; 4597 4598 /* allocate receive descriptors */ 4599 err = e1000e_setup_rx_resources(adapter->rx_ring); 4600 if (err) 4601 goto err_setup_rx; 4602 4603 /* If AMT is enabled, let the firmware know that the network 4604 * interface is now open and reset the part to a known state. 4605 */ 4606 if (adapter->flags & FLAG_HAS_AMT) { 4607 e1000e_get_hw_control(adapter); 4608 e1000e_reset(adapter); 4609 } 4610 4611 e1000e_power_up_phy(adapter); 4612 4613 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4614 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4615 e1000_update_mng_vlan(adapter); 4616 4617 /* DMA latency requirement to workaround jumbo issue */ 4618 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4619 PM_QOS_DEFAULT_VALUE); 4620 4621 /* before we allocate an interrupt, we must be ready to handle it. 4622 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4623 * as soon as we call pci_request_irq, so we have to setup our 4624 * clean_rx handler before we do so. 4625 */ 4626 e1000_configure(adapter); 4627 4628 err = e1000_request_irq(adapter); 4629 if (err) 4630 goto err_req_irq; 4631 4632 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4633 * ignore e1000e MSI messages, which means we need to test our MSI 4634 * interrupt now 4635 */ 4636 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4637 err = e1000_test_msi(adapter); 4638 if (err) { 4639 e_err("Interrupt allocation failed\n"); 4640 goto err_req_irq; 4641 } 4642 } 4643 4644 /* From here on the code is the same as e1000e_up() */ 4645 clear_bit(__E1000_DOWN, &adapter->state); 4646 4647 napi_enable(&adapter->napi); 4648 4649 e1000_irq_enable(adapter); 4650 4651 adapter->tx_hang_recheck = false; 4652 netif_start_queue(netdev); 4653 4654 hw->mac.get_link_status = true; 4655 pm_runtime_put(&pdev->dev); 4656 4657 e1000e_trigger_lsc(adapter); 4658 4659 return 0; 4660 4661 err_req_irq: 4662 pm_qos_remove_request(&adapter->pm_qos_req); 4663 e1000e_release_hw_control(adapter); 4664 e1000_power_down_phy(adapter); 4665 e1000e_free_rx_resources(adapter->rx_ring); 4666 err_setup_rx: 4667 e1000e_free_tx_resources(adapter->tx_ring); 4668 err_setup_tx: 4669 e1000e_reset(adapter); 4670 pm_runtime_put_sync(&pdev->dev); 4671 4672 return err; 4673 } 4674 4675 /** 4676 * e1000e_close - Disables a network interface 4677 * @netdev: network interface device structure 4678 * 4679 * Returns 0, this is not allowed to fail 4680 * 4681 * The close entry point is called when an interface is de-activated 4682 * by the OS. The hardware is still under the drivers control, but 4683 * needs to be disabled. A global MAC reset is issued to stop the 4684 * hardware, and all transmit and receive resources are freed. 4685 **/ 4686 int e1000e_close(struct net_device *netdev) 4687 { 4688 struct e1000_adapter *adapter = netdev_priv(netdev); 4689 struct pci_dev *pdev = adapter->pdev; 4690 int count = E1000_CHECK_RESET_COUNT; 4691 4692 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4693 usleep_range(10000, 20000); 4694 4695 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4696 4697 pm_runtime_get_sync(&pdev->dev); 4698 4699 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4700 e1000e_down(adapter, true); 4701 e1000_free_irq(adapter); 4702 4703 /* Link status message must follow this format */ 4704 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4705 } 4706 4707 napi_disable(&adapter->napi); 4708 4709 e1000e_free_tx_resources(adapter->tx_ring); 4710 e1000e_free_rx_resources(adapter->rx_ring); 4711 4712 /* kill manageability vlan ID if supported, but not if a vlan with 4713 * the same ID is registered on the host OS (let 8021q kill it) 4714 */ 4715 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4716 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4717 adapter->mng_vlan_id); 4718 4719 /* If AMT is enabled, let the firmware know that the network 4720 * interface is now closed 4721 */ 4722 if ((adapter->flags & FLAG_HAS_AMT) && 4723 !test_bit(__E1000_TESTING, &adapter->state)) 4724 e1000e_release_hw_control(adapter); 4725 4726 pm_qos_remove_request(&adapter->pm_qos_req); 4727 4728 pm_runtime_put_sync(&pdev->dev); 4729 4730 return 0; 4731 } 4732 4733 /** 4734 * e1000_set_mac - Change the Ethernet Address of the NIC 4735 * @netdev: network interface device structure 4736 * @p: pointer to an address structure 4737 * 4738 * Returns 0 on success, negative on failure 4739 **/ 4740 static int e1000_set_mac(struct net_device *netdev, void *p) 4741 { 4742 struct e1000_adapter *adapter = netdev_priv(netdev); 4743 struct e1000_hw *hw = &adapter->hw; 4744 struct sockaddr *addr = p; 4745 4746 if (!is_valid_ether_addr(addr->sa_data)) 4747 return -EADDRNOTAVAIL; 4748 4749 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4750 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4751 4752 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4753 4754 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4755 /* activate the work around */ 4756 e1000e_set_laa_state_82571(&adapter->hw, 1); 4757 4758 /* Hold a copy of the LAA in RAR[14] This is done so that 4759 * between the time RAR[0] gets clobbered and the time it 4760 * gets fixed (in e1000_watchdog), the actual LAA is in one 4761 * of the RARs and no incoming packets directed to this port 4762 * are dropped. Eventually the LAA will be in RAR[0] and 4763 * RAR[14] 4764 */ 4765 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4766 adapter->hw.mac.rar_entry_count - 1); 4767 } 4768 4769 return 0; 4770 } 4771 4772 /** 4773 * e1000e_update_phy_task - work thread to update phy 4774 * @work: pointer to our work struct 4775 * 4776 * this worker thread exists because we must acquire a 4777 * semaphore to read the phy, which we could msleep while 4778 * waiting for it, and we can't msleep in a timer. 4779 **/ 4780 static void e1000e_update_phy_task(struct work_struct *work) 4781 { 4782 struct e1000_adapter *adapter = container_of(work, 4783 struct e1000_adapter, 4784 update_phy_task); 4785 struct e1000_hw *hw = &adapter->hw; 4786 4787 if (test_bit(__E1000_DOWN, &adapter->state)) 4788 return; 4789 4790 e1000_get_phy_info(hw); 4791 4792 /* Enable EEE on 82579 after link up */ 4793 if (hw->phy.type >= e1000_phy_82579) 4794 e1000_set_eee_pchlan(hw); 4795 } 4796 4797 /** 4798 * e1000_update_phy_info - timre call-back to update PHY info 4799 * @data: pointer to adapter cast into an unsigned long 4800 * 4801 * Need to wait a few seconds after link up to get diagnostic information from 4802 * the phy 4803 **/ 4804 static void e1000_update_phy_info(unsigned long data) 4805 { 4806 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 4807 4808 if (test_bit(__E1000_DOWN, &adapter->state)) 4809 return; 4810 4811 schedule_work(&adapter->update_phy_task); 4812 } 4813 4814 /** 4815 * e1000e_update_phy_stats - Update the PHY statistics counters 4816 * @adapter: board private structure 4817 * 4818 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4819 **/ 4820 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4821 { 4822 struct e1000_hw *hw = &adapter->hw; 4823 s32 ret_val; 4824 u16 phy_data; 4825 4826 ret_val = hw->phy.ops.acquire(hw); 4827 if (ret_val) 4828 return; 4829 4830 /* A page set is expensive so check if already on desired page. 4831 * If not, set to the page with the PHY status registers. 4832 */ 4833 hw->phy.addr = 1; 4834 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4835 &phy_data); 4836 if (ret_val) 4837 goto release; 4838 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4839 ret_val = hw->phy.ops.set_page(hw, 4840 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4841 if (ret_val) 4842 goto release; 4843 } 4844 4845 /* Single Collision Count */ 4846 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4847 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4848 if (!ret_val) 4849 adapter->stats.scc += phy_data; 4850 4851 /* Excessive Collision Count */ 4852 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4853 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4854 if (!ret_val) 4855 adapter->stats.ecol += phy_data; 4856 4857 /* Multiple Collision Count */ 4858 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4859 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4860 if (!ret_val) 4861 adapter->stats.mcc += phy_data; 4862 4863 /* Late Collision Count */ 4864 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4865 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4866 if (!ret_val) 4867 adapter->stats.latecol += phy_data; 4868 4869 /* Collision Count - also used for adaptive IFS */ 4870 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4871 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4872 if (!ret_val) 4873 hw->mac.collision_delta = phy_data; 4874 4875 /* Defer Count */ 4876 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4877 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4878 if (!ret_val) 4879 adapter->stats.dc += phy_data; 4880 4881 /* Transmit with no CRS */ 4882 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4883 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4884 if (!ret_val) 4885 adapter->stats.tncrs += phy_data; 4886 4887 release: 4888 hw->phy.ops.release(hw); 4889 } 4890 4891 /** 4892 * e1000e_update_stats - Update the board statistics counters 4893 * @adapter: board private structure 4894 **/ 4895 static void e1000e_update_stats(struct e1000_adapter *adapter) 4896 { 4897 struct net_device *netdev = adapter->netdev; 4898 struct e1000_hw *hw = &adapter->hw; 4899 struct pci_dev *pdev = adapter->pdev; 4900 4901 /* Prevent stats update while adapter is being reset, or if the pci 4902 * connection is down. 4903 */ 4904 if (adapter->link_speed == 0) 4905 return; 4906 if (pci_channel_offline(pdev)) 4907 return; 4908 4909 adapter->stats.crcerrs += er32(CRCERRS); 4910 adapter->stats.gprc += er32(GPRC); 4911 adapter->stats.gorc += er32(GORCL); 4912 er32(GORCH); /* Clear gorc */ 4913 adapter->stats.bprc += er32(BPRC); 4914 adapter->stats.mprc += er32(MPRC); 4915 adapter->stats.roc += er32(ROC); 4916 4917 adapter->stats.mpc += er32(MPC); 4918 4919 /* Half-duplex statistics */ 4920 if (adapter->link_duplex == HALF_DUPLEX) { 4921 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4922 e1000e_update_phy_stats(adapter); 4923 } else { 4924 adapter->stats.scc += er32(SCC); 4925 adapter->stats.ecol += er32(ECOL); 4926 adapter->stats.mcc += er32(MCC); 4927 adapter->stats.latecol += er32(LATECOL); 4928 adapter->stats.dc += er32(DC); 4929 4930 hw->mac.collision_delta = er32(COLC); 4931 4932 if ((hw->mac.type != e1000_82574) && 4933 (hw->mac.type != e1000_82583)) 4934 adapter->stats.tncrs += er32(TNCRS); 4935 } 4936 adapter->stats.colc += hw->mac.collision_delta; 4937 } 4938 4939 adapter->stats.xonrxc += er32(XONRXC); 4940 adapter->stats.xontxc += er32(XONTXC); 4941 adapter->stats.xoffrxc += er32(XOFFRXC); 4942 adapter->stats.xofftxc += er32(XOFFTXC); 4943 adapter->stats.gptc += er32(GPTC); 4944 adapter->stats.gotc += er32(GOTCL); 4945 er32(GOTCH); /* Clear gotc */ 4946 adapter->stats.rnbc += er32(RNBC); 4947 adapter->stats.ruc += er32(RUC); 4948 4949 adapter->stats.mptc += er32(MPTC); 4950 adapter->stats.bptc += er32(BPTC); 4951 4952 /* used for adaptive IFS */ 4953 4954 hw->mac.tx_packet_delta = er32(TPT); 4955 adapter->stats.tpt += hw->mac.tx_packet_delta; 4956 4957 adapter->stats.algnerrc += er32(ALGNERRC); 4958 adapter->stats.rxerrc += er32(RXERRC); 4959 adapter->stats.cexterr += er32(CEXTERR); 4960 adapter->stats.tsctc += er32(TSCTC); 4961 adapter->stats.tsctfc += er32(TSCTFC); 4962 4963 /* Fill out the OS statistics structure */ 4964 netdev->stats.multicast = adapter->stats.mprc; 4965 netdev->stats.collisions = adapter->stats.colc; 4966 4967 /* Rx Errors */ 4968 4969 /* RLEC on some newer hardware can be incorrect so build 4970 * our own version based on RUC and ROC 4971 */ 4972 netdev->stats.rx_errors = adapter->stats.rxerrc + 4973 adapter->stats.crcerrs + adapter->stats.algnerrc + 4974 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4975 netdev->stats.rx_length_errors = adapter->stats.ruc + 4976 adapter->stats.roc; 4977 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 4978 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 4979 netdev->stats.rx_missed_errors = adapter->stats.mpc; 4980 4981 /* Tx Errors */ 4982 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 4983 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 4984 netdev->stats.tx_window_errors = adapter->stats.latecol; 4985 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 4986 4987 /* Tx Dropped needs to be maintained elsewhere */ 4988 4989 /* Management Stats */ 4990 adapter->stats.mgptc += er32(MGTPTC); 4991 adapter->stats.mgprc += er32(MGTPRC); 4992 adapter->stats.mgpdc += er32(MGTPDC); 4993 4994 /* Correctable ECC Errors */ 4995 if (hw->mac.type >= e1000_pch_lpt) { 4996 u32 pbeccsts = er32(PBECCSTS); 4997 4998 adapter->corr_errors += 4999 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5000 adapter->uncorr_errors += 5001 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5002 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5003 } 5004 } 5005 5006 /** 5007 * e1000_phy_read_status - Update the PHY register status snapshot 5008 * @adapter: board private structure 5009 **/ 5010 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5011 { 5012 struct e1000_hw *hw = &adapter->hw; 5013 struct e1000_phy_regs *phy = &adapter->phy_regs; 5014 5015 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5016 (er32(STATUS) & E1000_STATUS_LU) && 5017 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5018 int ret_val; 5019 5020 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5021 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5022 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5023 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5024 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5025 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5026 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5027 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5028 if (ret_val) 5029 e_warn("Error reading PHY register\n"); 5030 } else { 5031 /* Do not read PHY registers if link is not up 5032 * Set values to typical power-on defaults 5033 */ 5034 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5035 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5036 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5037 BMSR_ERCAP); 5038 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5039 ADVERTISE_ALL | ADVERTISE_CSMA); 5040 phy->lpa = 0; 5041 phy->expansion = EXPANSION_ENABLENPAGE; 5042 phy->ctrl1000 = ADVERTISE_1000FULL; 5043 phy->stat1000 = 0; 5044 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5045 } 5046 } 5047 5048 static void e1000_print_link_info(struct e1000_adapter *adapter) 5049 { 5050 struct e1000_hw *hw = &adapter->hw; 5051 u32 ctrl = er32(CTRL); 5052 5053 /* Link status message must follow this format for user tools */ 5054 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5055 adapter->netdev->name, adapter->link_speed, 5056 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5057 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5058 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5059 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5060 } 5061 5062 static bool e1000e_has_link(struct e1000_adapter *adapter) 5063 { 5064 struct e1000_hw *hw = &adapter->hw; 5065 bool link_active = false; 5066 s32 ret_val = 0; 5067 5068 /* get_link_status is set on LSC (link status) interrupt or 5069 * Rx sequence error interrupt. get_link_status will stay 5070 * false until the check_for_link establishes link 5071 * for copper adapters ONLY 5072 */ 5073 switch (hw->phy.media_type) { 5074 case e1000_media_type_copper: 5075 if (hw->mac.get_link_status) { 5076 ret_val = hw->mac.ops.check_for_link(hw); 5077 link_active = !hw->mac.get_link_status; 5078 } else { 5079 link_active = true; 5080 } 5081 break; 5082 case e1000_media_type_fiber: 5083 ret_val = hw->mac.ops.check_for_link(hw); 5084 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5085 break; 5086 case e1000_media_type_internal_serdes: 5087 ret_val = hw->mac.ops.check_for_link(hw); 5088 link_active = adapter->hw.mac.serdes_has_link; 5089 break; 5090 default: 5091 case e1000_media_type_unknown: 5092 break; 5093 } 5094 5095 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5096 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5097 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5098 e_info("Gigabit has been disabled, downgrading speed\n"); 5099 } 5100 5101 return link_active; 5102 } 5103 5104 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5105 { 5106 /* make sure the receive unit is started */ 5107 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5108 (adapter->flags & FLAG_RESTART_NOW)) { 5109 struct e1000_hw *hw = &adapter->hw; 5110 u32 rctl = er32(RCTL); 5111 5112 ew32(RCTL, rctl | E1000_RCTL_EN); 5113 adapter->flags &= ~FLAG_RESTART_NOW; 5114 } 5115 } 5116 5117 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5118 { 5119 struct e1000_hw *hw = &adapter->hw; 5120 5121 /* With 82574 controllers, PHY needs to be checked periodically 5122 * for hung state and reset, if two calls return true 5123 */ 5124 if (e1000_check_phy_82574(hw)) 5125 adapter->phy_hang_count++; 5126 else 5127 adapter->phy_hang_count = 0; 5128 5129 if (adapter->phy_hang_count > 1) { 5130 adapter->phy_hang_count = 0; 5131 e_dbg("PHY appears hung - resetting\n"); 5132 schedule_work(&adapter->reset_task); 5133 } 5134 } 5135 5136 /** 5137 * e1000_watchdog - Timer Call-back 5138 * @data: pointer to adapter cast into an unsigned long 5139 **/ 5140 static void e1000_watchdog(unsigned long data) 5141 { 5142 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 5143 5144 /* Do the rest outside of interrupt context */ 5145 schedule_work(&adapter->watchdog_task); 5146 5147 /* TODO: make this use queue_delayed_work() */ 5148 } 5149 5150 static void e1000_watchdog_task(struct work_struct *work) 5151 { 5152 struct e1000_adapter *adapter = container_of(work, 5153 struct e1000_adapter, 5154 watchdog_task); 5155 struct net_device *netdev = adapter->netdev; 5156 struct e1000_mac_info *mac = &adapter->hw.mac; 5157 struct e1000_phy_info *phy = &adapter->hw.phy; 5158 struct e1000_ring *tx_ring = adapter->tx_ring; 5159 struct e1000_hw *hw = &adapter->hw; 5160 u32 link, tctl; 5161 5162 if (test_bit(__E1000_DOWN, &adapter->state)) 5163 return; 5164 5165 link = e1000e_has_link(adapter); 5166 if ((netif_carrier_ok(netdev)) && link) { 5167 /* Cancel scheduled suspend requests. */ 5168 pm_runtime_resume(netdev->dev.parent); 5169 5170 e1000e_enable_receives(adapter); 5171 goto link_up; 5172 } 5173 5174 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5175 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5176 e1000_update_mng_vlan(adapter); 5177 5178 if (link) { 5179 if (!netif_carrier_ok(netdev)) { 5180 bool txb2b = true; 5181 5182 /* Cancel scheduled suspend requests. */ 5183 pm_runtime_resume(netdev->dev.parent); 5184 5185 /* update snapshot of PHY registers on LSC */ 5186 e1000_phy_read_status(adapter); 5187 mac->ops.get_link_up_info(&adapter->hw, 5188 &adapter->link_speed, 5189 &adapter->link_duplex); 5190 e1000_print_link_info(adapter); 5191 5192 /* check if SmartSpeed worked */ 5193 e1000e_check_downshift(hw); 5194 if (phy->speed_downgraded) 5195 netdev_warn(netdev, 5196 "Link Speed was downgraded by SmartSpeed\n"); 5197 5198 /* On supported PHYs, check for duplex mismatch only 5199 * if link has autonegotiated at 10/100 half 5200 */ 5201 if ((hw->phy.type == e1000_phy_igp_3 || 5202 hw->phy.type == e1000_phy_bm) && 5203 hw->mac.autoneg && 5204 (adapter->link_speed == SPEED_10 || 5205 adapter->link_speed == SPEED_100) && 5206 (adapter->link_duplex == HALF_DUPLEX)) { 5207 u16 autoneg_exp; 5208 5209 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5210 5211 if (!(autoneg_exp & EXPANSION_NWAY)) 5212 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5213 } 5214 5215 /* adjust timeout factor according to speed/duplex */ 5216 adapter->tx_timeout_factor = 1; 5217 switch (adapter->link_speed) { 5218 case SPEED_10: 5219 txb2b = false; 5220 adapter->tx_timeout_factor = 16; 5221 break; 5222 case SPEED_100: 5223 txb2b = false; 5224 adapter->tx_timeout_factor = 10; 5225 break; 5226 } 5227 5228 /* workaround: re-program speed mode bit after 5229 * link-up event 5230 */ 5231 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5232 !txb2b) { 5233 u32 tarc0; 5234 5235 tarc0 = er32(TARC(0)); 5236 tarc0 &= ~SPEED_MODE_BIT; 5237 ew32(TARC(0), tarc0); 5238 } 5239 5240 /* disable TSO for pcie and 10/100 speeds, to avoid 5241 * some hardware issues 5242 */ 5243 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5244 switch (adapter->link_speed) { 5245 case SPEED_10: 5246 case SPEED_100: 5247 e_info("10/100 speed: disabling TSO\n"); 5248 netdev->features &= ~NETIF_F_TSO; 5249 netdev->features &= ~NETIF_F_TSO6; 5250 break; 5251 case SPEED_1000: 5252 netdev->features |= NETIF_F_TSO; 5253 netdev->features |= NETIF_F_TSO6; 5254 break; 5255 default: 5256 /* oops */ 5257 break; 5258 } 5259 } 5260 5261 /* enable transmits in the hardware, need to do this 5262 * after setting TARC(0) 5263 */ 5264 tctl = er32(TCTL); 5265 tctl |= E1000_TCTL_EN; 5266 ew32(TCTL, tctl); 5267 5268 /* Perform any post-link-up configuration before 5269 * reporting link up. 5270 */ 5271 if (phy->ops.cfg_on_link_up) 5272 phy->ops.cfg_on_link_up(hw); 5273 5274 netif_carrier_on(netdev); 5275 5276 if (!test_bit(__E1000_DOWN, &adapter->state)) 5277 mod_timer(&adapter->phy_info_timer, 5278 round_jiffies(jiffies + 2 * HZ)); 5279 } 5280 } else { 5281 if (netif_carrier_ok(netdev)) { 5282 adapter->link_speed = 0; 5283 adapter->link_duplex = 0; 5284 /* Link status message must follow this format */ 5285 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 5286 netif_carrier_off(netdev); 5287 if (!test_bit(__E1000_DOWN, &adapter->state)) 5288 mod_timer(&adapter->phy_info_timer, 5289 round_jiffies(jiffies + 2 * HZ)); 5290 5291 /* 8000ES2LAN requires a Rx packet buffer work-around 5292 * on link down event; reset the controller to flush 5293 * the Rx packet buffer. 5294 */ 5295 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5296 adapter->flags |= FLAG_RESTART_NOW; 5297 else 5298 pm_schedule_suspend(netdev->dev.parent, 5299 LINK_TIMEOUT); 5300 } 5301 } 5302 5303 link_up: 5304 spin_lock(&adapter->stats64_lock); 5305 e1000e_update_stats(adapter); 5306 5307 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5308 adapter->tpt_old = adapter->stats.tpt; 5309 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5310 adapter->colc_old = adapter->stats.colc; 5311 5312 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5313 adapter->gorc_old = adapter->stats.gorc; 5314 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5315 adapter->gotc_old = adapter->stats.gotc; 5316 spin_unlock(&adapter->stats64_lock); 5317 5318 /* If the link is lost the controller stops DMA, but 5319 * if there is queued Tx work it cannot be done. So 5320 * reset the controller to flush the Tx packet buffers. 5321 */ 5322 if (!netif_carrier_ok(netdev) && 5323 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5324 adapter->flags |= FLAG_RESTART_NOW; 5325 5326 /* If reset is necessary, do it outside of interrupt context. */ 5327 if (adapter->flags & FLAG_RESTART_NOW) { 5328 schedule_work(&adapter->reset_task); 5329 /* return immediately since reset is imminent */ 5330 return; 5331 } 5332 5333 e1000e_update_adaptive(&adapter->hw); 5334 5335 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5336 if (adapter->itr_setting == 4) { 5337 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5338 * Total asymmetrical Tx or Rx gets ITR=8000; 5339 * everyone else is between 2000-8000. 5340 */ 5341 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5342 u32 dif = (adapter->gotc > adapter->gorc ? 5343 adapter->gotc - adapter->gorc : 5344 adapter->gorc - adapter->gotc) / 10000; 5345 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5346 5347 e1000e_write_itr(adapter, itr); 5348 } 5349 5350 /* Cause software interrupt to ensure Rx ring is cleaned */ 5351 if (adapter->msix_entries) 5352 ew32(ICS, adapter->rx_ring->ims_val); 5353 else 5354 ew32(ICS, E1000_ICS_RXDMT0); 5355 5356 /* flush pending descriptors to memory before detecting Tx hang */ 5357 e1000e_flush_descriptors(adapter); 5358 5359 /* Force detection of hung controller every watchdog period */ 5360 adapter->detect_tx_hung = true; 5361 5362 /* With 82571 controllers, LAA may be overwritten due to controller 5363 * reset from the other port. Set the appropriate LAA in RAR[0] 5364 */ 5365 if (e1000e_get_laa_state_82571(hw)) 5366 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5367 5368 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5369 e1000e_check_82574_phy_workaround(adapter); 5370 5371 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5372 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5373 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5374 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5375 er32(RXSTMPH); 5376 adapter->rx_hwtstamp_cleared++; 5377 } else { 5378 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5379 } 5380 } 5381 5382 /* Reset the timer */ 5383 if (!test_bit(__E1000_DOWN, &adapter->state)) 5384 mod_timer(&adapter->watchdog_timer, 5385 round_jiffies(jiffies + 2 * HZ)); 5386 } 5387 5388 #define E1000_TX_FLAGS_CSUM 0x00000001 5389 #define E1000_TX_FLAGS_VLAN 0x00000002 5390 #define E1000_TX_FLAGS_TSO 0x00000004 5391 #define E1000_TX_FLAGS_IPV4 0x00000008 5392 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5393 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5394 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5395 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5396 5397 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5398 __be16 protocol) 5399 { 5400 struct e1000_context_desc *context_desc; 5401 struct e1000_buffer *buffer_info; 5402 unsigned int i; 5403 u32 cmd_length = 0; 5404 u16 ipcse = 0, mss; 5405 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5406 int err; 5407 5408 if (!skb_is_gso(skb)) 5409 return 0; 5410 5411 err = skb_cow_head(skb, 0); 5412 if (err < 0) 5413 return err; 5414 5415 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5416 mss = skb_shinfo(skb)->gso_size; 5417 if (protocol == htons(ETH_P_IP)) { 5418 struct iphdr *iph = ip_hdr(skb); 5419 iph->tot_len = 0; 5420 iph->check = 0; 5421 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5422 0, IPPROTO_TCP, 0); 5423 cmd_length = E1000_TXD_CMD_IP; 5424 ipcse = skb_transport_offset(skb) - 1; 5425 } else if (skb_is_gso_v6(skb)) { 5426 ipv6_hdr(skb)->payload_len = 0; 5427 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5428 &ipv6_hdr(skb)->daddr, 5429 0, IPPROTO_TCP, 0); 5430 ipcse = 0; 5431 } 5432 ipcss = skb_network_offset(skb); 5433 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5434 tucss = skb_transport_offset(skb); 5435 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5436 5437 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5438 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5439 5440 i = tx_ring->next_to_use; 5441 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5442 buffer_info = &tx_ring->buffer_info[i]; 5443 5444 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5445 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5446 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5447 context_desc->upper_setup.tcp_fields.tucss = tucss; 5448 context_desc->upper_setup.tcp_fields.tucso = tucso; 5449 context_desc->upper_setup.tcp_fields.tucse = 0; 5450 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5451 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5452 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5453 5454 buffer_info->time_stamp = jiffies; 5455 buffer_info->next_to_watch = i; 5456 5457 i++; 5458 if (i == tx_ring->count) 5459 i = 0; 5460 tx_ring->next_to_use = i; 5461 5462 return 1; 5463 } 5464 5465 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5466 __be16 protocol) 5467 { 5468 struct e1000_adapter *adapter = tx_ring->adapter; 5469 struct e1000_context_desc *context_desc; 5470 struct e1000_buffer *buffer_info; 5471 unsigned int i; 5472 u8 css; 5473 u32 cmd_len = E1000_TXD_CMD_DEXT; 5474 5475 if (skb->ip_summed != CHECKSUM_PARTIAL) 5476 return false; 5477 5478 switch (protocol) { 5479 case cpu_to_be16(ETH_P_IP): 5480 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5481 cmd_len |= E1000_TXD_CMD_TCP; 5482 break; 5483 case cpu_to_be16(ETH_P_IPV6): 5484 /* XXX not handling all IPV6 headers */ 5485 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5486 cmd_len |= E1000_TXD_CMD_TCP; 5487 break; 5488 default: 5489 if (unlikely(net_ratelimit())) 5490 e_warn("checksum_partial proto=%x!\n", 5491 be16_to_cpu(protocol)); 5492 break; 5493 } 5494 5495 css = skb_checksum_start_offset(skb); 5496 5497 i = tx_ring->next_to_use; 5498 buffer_info = &tx_ring->buffer_info[i]; 5499 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5500 5501 context_desc->lower_setup.ip_config = 0; 5502 context_desc->upper_setup.tcp_fields.tucss = css; 5503 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5504 context_desc->upper_setup.tcp_fields.tucse = 0; 5505 context_desc->tcp_seg_setup.data = 0; 5506 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5507 5508 buffer_info->time_stamp = jiffies; 5509 buffer_info->next_to_watch = i; 5510 5511 i++; 5512 if (i == tx_ring->count) 5513 i = 0; 5514 tx_ring->next_to_use = i; 5515 5516 return true; 5517 } 5518 5519 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5520 unsigned int first, unsigned int max_per_txd, 5521 unsigned int nr_frags) 5522 { 5523 struct e1000_adapter *adapter = tx_ring->adapter; 5524 struct pci_dev *pdev = adapter->pdev; 5525 struct e1000_buffer *buffer_info; 5526 unsigned int len = skb_headlen(skb); 5527 unsigned int offset = 0, size, count = 0, i; 5528 unsigned int f, bytecount, segs; 5529 5530 i = tx_ring->next_to_use; 5531 5532 while (len) { 5533 buffer_info = &tx_ring->buffer_info[i]; 5534 size = min(len, max_per_txd); 5535 5536 buffer_info->length = size; 5537 buffer_info->time_stamp = jiffies; 5538 buffer_info->next_to_watch = i; 5539 buffer_info->dma = dma_map_single(&pdev->dev, 5540 skb->data + offset, 5541 size, DMA_TO_DEVICE); 5542 buffer_info->mapped_as_page = false; 5543 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5544 goto dma_error; 5545 5546 len -= size; 5547 offset += size; 5548 count++; 5549 5550 if (len) { 5551 i++; 5552 if (i == tx_ring->count) 5553 i = 0; 5554 } 5555 } 5556 5557 for (f = 0; f < nr_frags; f++) { 5558 const struct skb_frag_struct *frag; 5559 5560 frag = &skb_shinfo(skb)->frags[f]; 5561 len = skb_frag_size(frag); 5562 offset = 0; 5563 5564 while (len) { 5565 i++; 5566 if (i == tx_ring->count) 5567 i = 0; 5568 5569 buffer_info = &tx_ring->buffer_info[i]; 5570 size = min(len, max_per_txd); 5571 5572 buffer_info->length = size; 5573 buffer_info->time_stamp = jiffies; 5574 buffer_info->next_to_watch = i; 5575 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5576 offset, size, 5577 DMA_TO_DEVICE); 5578 buffer_info->mapped_as_page = true; 5579 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5580 goto dma_error; 5581 5582 len -= size; 5583 offset += size; 5584 count++; 5585 } 5586 } 5587 5588 segs = skb_shinfo(skb)->gso_segs ? : 1; 5589 /* multiply data chunks by size of headers */ 5590 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5591 5592 tx_ring->buffer_info[i].skb = skb; 5593 tx_ring->buffer_info[i].segs = segs; 5594 tx_ring->buffer_info[i].bytecount = bytecount; 5595 tx_ring->buffer_info[first].next_to_watch = i; 5596 5597 return count; 5598 5599 dma_error: 5600 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5601 buffer_info->dma = 0; 5602 if (count) 5603 count--; 5604 5605 while (count--) { 5606 if (i == 0) 5607 i += tx_ring->count; 5608 i--; 5609 buffer_info = &tx_ring->buffer_info[i]; 5610 e1000_put_txbuf(tx_ring, buffer_info); 5611 } 5612 5613 return 0; 5614 } 5615 5616 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5617 { 5618 struct e1000_adapter *adapter = tx_ring->adapter; 5619 struct e1000_tx_desc *tx_desc = NULL; 5620 struct e1000_buffer *buffer_info; 5621 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5622 unsigned int i; 5623 5624 if (tx_flags & E1000_TX_FLAGS_TSO) { 5625 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5626 E1000_TXD_CMD_TSE; 5627 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5628 5629 if (tx_flags & E1000_TX_FLAGS_IPV4) 5630 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5631 } 5632 5633 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5634 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5635 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5636 } 5637 5638 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5639 txd_lower |= E1000_TXD_CMD_VLE; 5640 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5641 } 5642 5643 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5644 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5645 5646 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5647 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5648 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5649 } 5650 5651 i = tx_ring->next_to_use; 5652 5653 do { 5654 buffer_info = &tx_ring->buffer_info[i]; 5655 tx_desc = E1000_TX_DESC(*tx_ring, i); 5656 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5657 tx_desc->lower.data = cpu_to_le32(txd_lower | 5658 buffer_info->length); 5659 tx_desc->upper.data = cpu_to_le32(txd_upper); 5660 5661 i++; 5662 if (i == tx_ring->count) 5663 i = 0; 5664 } while (--count > 0); 5665 5666 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5667 5668 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5669 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5670 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5671 5672 /* Force memory writes to complete before letting h/w 5673 * know there are new descriptors to fetch. (Only 5674 * applicable for weak-ordered memory model archs, 5675 * such as IA-64). 5676 */ 5677 wmb(); 5678 5679 tx_ring->next_to_use = i; 5680 } 5681 5682 #define MINIMUM_DHCP_PACKET_SIZE 282 5683 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5684 struct sk_buff *skb) 5685 { 5686 struct e1000_hw *hw = &adapter->hw; 5687 u16 length, offset; 5688 5689 if (skb_vlan_tag_present(skb) && 5690 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5691 (adapter->hw.mng_cookie.status & 5692 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5693 return 0; 5694 5695 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5696 return 0; 5697 5698 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5699 return 0; 5700 5701 { 5702 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5703 struct udphdr *udp; 5704 5705 if (ip->protocol != IPPROTO_UDP) 5706 return 0; 5707 5708 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5709 if (ntohs(udp->dest) != 67) 5710 return 0; 5711 5712 offset = (u8 *)udp + 8 - skb->data; 5713 length = skb->len - offset; 5714 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5715 } 5716 5717 return 0; 5718 } 5719 5720 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5721 { 5722 struct e1000_adapter *adapter = tx_ring->adapter; 5723 5724 netif_stop_queue(adapter->netdev); 5725 /* Herbert's original patch had: 5726 * smp_mb__after_netif_stop_queue(); 5727 * but since that doesn't exist yet, just open code it. 5728 */ 5729 smp_mb(); 5730 5731 /* We need to check again in a case another CPU has just 5732 * made room available. 5733 */ 5734 if (e1000_desc_unused(tx_ring) < size) 5735 return -EBUSY; 5736 5737 /* A reprieve! */ 5738 netif_start_queue(adapter->netdev); 5739 ++adapter->restart_queue; 5740 return 0; 5741 } 5742 5743 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5744 { 5745 BUG_ON(size > tx_ring->count); 5746 5747 if (e1000_desc_unused(tx_ring) >= size) 5748 return 0; 5749 return __e1000_maybe_stop_tx(tx_ring, size); 5750 } 5751 5752 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5753 struct net_device *netdev) 5754 { 5755 struct e1000_adapter *adapter = netdev_priv(netdev); 5756 struct e1000_ring *tx_ring = adapter->tx_ring; 5757 unsigned int first; 5758 unsigned int tx_flags = 0; 5759 unsigned int len = skb_headlen(skb); 5760 unsigned int nr_frags; 5761 unsigned int mss; 5762 int count = 0; 5763 int tso; 5764 unsigned int f; 5765 __be16 protocol = vlan_get_protocol(skb); 5766 5767 if (test_bit(__E1000_DOWN, &adapter->state)) { 5768 dev_kfree_skb_any(skb); 5769 return NETDEV_TX_OK; 5770 } 5771 5772 if (skb->len <= 0) { 5773 dev_kfree_skb_any(skb); 5774 return NETDEV_TX_OK; 5775 } 5776 5777 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5778 * pad skb in order to meet this minimum size requirement 5779 */ 5780 if (skb_put_padto(skb, 17)) 5781 return NETDEV_TX_OK; 5782 5783 mss = skb_shinfo(skb)->gso_size; 5784 if (mss) { 5785 u8 hdr_len; 5786 5787 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5788 * points to just header, pull a few bytes of payload from 5789 * frags into skb->data 5790 */ 5791 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5792 /* we do this workaround for ES2LAN, but it is un-necessary, 5793 * avoiding it could save a lot of cycles 5794 */ 5795 if (skb->data_len && (hdr_len == len)) { 5796 unsigned int pull_size; 5797 5798 pull_size = min_t(unsigned int, 4, skb->data_len); 5799 if (!__pskb_pull_tail(skb, pull_size)) { 5800 e_err("__pskb_pull_tail failed.\n"); 5801 dev_kfree_skb_any(skb); 5802 return NETDEV_TX_OK; 5803 } 5804 len = skb_headlen(skb); 5805 } 5806 } 5807 5808 /* reserve a descriptor for the offload context */ 5809 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5810 count++; 5811 count++; 5812 5813 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5814 5815 nr_frags = skb_shinfo(skb)->nr_frags; 5816 for (f = 0; f < nr_frags; f++) 5817 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5818 adapter->tx_fifo_limit); 5819 5820 if (adapter->hw.mac.tx_pkt_filtering) 5821 e1000_transfer_dhcp_info(adapter, skb); 5822 5823 /* need: count + 2 desc gap to keep tail from touching 5824 * head, otherwise try next time 5825 */ 5826 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5827 return NETDEV_TX_BUSY; 5828 5829 if (skb_vlan_tag_present(skb)) { 5830 tx_flags |= E1000_TX_FLAGS_VLAN; 5831 tx_flags |= (skb_vlan_tag_get(skb) << 5832 E1000_TX_FLAGS_VLAN_SHIFT); 5833 } 5834 5835 first = tx_ring->next_to_use; 5836 5837 tso = e1000_tso(tx_ring, skb, protocol); 5838 if (tso < 0) { 5839 dev_kfree_skb_any(skb); 5840 return NETDEV_TX_OK; 5841 } 5842 5843 if (tso) 5844 tx_flags |= E1000_TX_FLAGS_TSO; 5845 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5846 tx_flags |= E1000_TX_FLAGS_CSUM; 5847 5848 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5849 * 82571 hardware supports TSO capabilities for IPv6 as well... 5850 * no longer assume, we must. 5851 */ 5852 if (protocol == htons(ETH_P_IP)) 5853 tx_flags |= E1000_TX_FLAGS_IPV4; 5854 5855 if (unlikely(skb->no_fcs)) 5856 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5857 5858 /* if count is 0 then mapping error has occurred */ 5859 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5860 nr_frags); 5861 if (count) { 5862 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5863 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) && 5864 !adapter->tx_hwtstamp_skb) { 5865 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5866 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5867 adapter->tx_hwtstamp_skb = skb_get(skb); 5868 adapter->tx_hwtstamp_start = jiffies; 5869 schedule_work(&adapter->tx_hwtstamp_work); 5870 } else { 5871 skb_tx_timestamp(skb); 5872 } 5873 5874 netdev_sent_queue(netdev, skb->len); 5875 e1000_tx_queue(tx_ring, tx_flags, count); 5876 /* Make sure there is space in the ring for the next send. */ 5877 e1000_maybe_stop_tx(tx_ring, 5878 (MAX_SKB_FRAGS * 5879 DIV_ROUND_UP(PAGE_SIZE, 5880 adapter->tx_fifo_limit) + 2)); 5881 5882 if (!skb->xmit_more || 5883 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5884 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5885 e1000e_update_tdt_wa(tx_ring, 5886 tx_ring->next_to_use); 5887 else 5888 writel(tx_ring->next_to_use, tx_ring->tail); 5889 5890 /* we need this if more than one processor can write 5891 * to our tail at a time, it synchronizes IO on 5892 *IA64/Altix systems 5893 */ 5894 mmiowb(); 5895 } 5896 } else { 5897 dev_kfree_skb_any(skb); 5898 tx_ring->buffer_info[first].time_stamp = 0; 5899 tx_ring->next_to_use = first; 5900 } 5901 5902 return NETDEV_TX_OK; 5903 } 5904 5905 /** 5906 * e1000_tx_timeout - Respond to a Tx Hang 5907 * @netdev: network interface device structure 5908 **/ 5909 static void e1000_tx_timeout(struct net_device *netdev) 5910 { 5911 struct e1000_adapter *adapter = netdev_priv(netdev); 5912 5913 /* Do the reset outside of interrupt context */ 5914 adapter->tx_timeout_count++; 5915 schedule_work(&adapter->reset_task); 5916 } 5917 5918 static void e1000_reset_task(struct work_struct *work) 5919 { 5920 struct e1000_adapter *adapter; 5921 adapter = container_of(work, struct e1000_adapter, reset_task); 5922 5923 /* don't run the task if already down */ 5924 if (test_bit(__E1000_DOWN, &adapter->state)) 5925 return; 5926 5927 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5928 e1000e_dump(adapter); 5929 e_err("Reset adapter unexpectedly\n"); 5930 } 5931 e1000e_reinit_locked(adapter); 5932 } 5933 5934 /** 5935 * e1000_get_stats64 - Get System Network Statistics 5936 * @netdev: network interface device structure 5937 * @stats: rtnl_link_stats64 pointer 5938 * 5939 * Returns the address of the device statistics structure. 5940 **/ 5941 void e1000e_get_stats64(struct net_device *netdev, 5942 struct rtnl_link_stats64 *stats) 5943 { 5944 struct e1000_adapter *adapter = netdev_priv(netdev); 5945 5946 spin_lock(&adapter->stats64_lock); 5947 e1000e_update_stats(adapter); 5948 /* Fill out the OS statistics structure */ 5949 stats->rx_bytes = adapter->stats.gorc; 5950 stats->rx_packets = adapter->stats.gprc; 5951 stats->tx_bytes = adapter->stats.gotc; 5952 stats->tx_packets = adapter->stats.gptc; 5953 stats->multicast = adapter->stats.mprc; 5954 stats->collisions = adapter->stats.colc; 5955 5956 /* Rx Errors */ 5957 5958 /* RLEC on some newer hardware can be incorrect so build 5959 * our own version based on RUC and ROC 5960 */ 5961 stats->rx_errors = adapter->stats.rxerrc + 5962 adapter->stats.crcerrs + adapter->stats.algnerrc + 5963 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5964 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5965 stats->rx_crc_errors = adapter->stats.crcerrs; 5966 stats->rx_frame_errors = adapter->stats.algnerrc; 5967 stats->rx_missed_errors = adapter->stats.mpc; 5968 5969 /* Tx Errors */ 5970 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5971 stats->tx_aborted_errors = adapter->stats.ecol; 5972 stats->tx_window_errors = adapter->stats.latecol; 5973 stats->tx_carrier_errors = adapter->stats.tncrs; 5974 5975 /* Tx Dropped needs to be maintained elsewhere */ 5976 5977 spin_unlock(&adapter->stats64_lock); 5978 } 5979 5980 /** 5981 * e1000_change_mtu - Change the Maximum Transfer Unit 5982 * @netdev: network interface device structure 5983 * @new_mtu: new value for maximum frame size 5984 * 5985 * Returns 0 on success, negative on failure 5986 **/ 5987 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 5988 { 5989 struct e1000_adapter *adapter = netdev_priv(netdev); 5990 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 5991 5992 /* Jumbo frame support */ 5993 if ((new_mtu > ETH_DATA_LEN) && 5994 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 5995 e_err("Jumbo Frames not supported.\n"); 5996 return -EINVAL; 5997 } 5998 5999 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6000 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6001 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6002 (new_mtu > ETH_DATA_LEN)) { 6003 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6004 return -EINVAL; 6005 } 6006 6007 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6008 usleep_range(1000, 2000); 6009 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6010 adapter->max_frame_size = max_frame; 6011 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6012 netdev->mtu = new_mtu; 6013 6014 pm_runtime_get_sync(netdev->dev.parent); 6015 6016 if (netif_running(netdev)) 6017 e1000e_down(adapter, true); 6018 6019 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6020 * means we reserve 2 more, this pushes us to allocate from the next 6021 * larger slab size. 6022 * i.e. RXBUFFER_2048 --> size-4096 slab 6023 * However with the new *_jumbo_rx* routines, jumbo receives will use 6024 * fragmented skbs 6025 */ 6026 6027 if (max_frame <= 2048) 6028 adapter->rx_buffer_len = 2048; 6029 else 6030 adapter->rx_buffer_len = 4096; 6031 6032 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6033 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6034 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6035 6036 if (netif_running(netdev)) 6037 e1000e_up(adapter); 6038 else 6039 e1000e_reset(adapter); 6040 6041 pm_runtime_put_sync(netdev->dev.parent); 6042 6043 clear_bit(__E1000_RESETTING, &adapter->state); 6044 6045 return 0; 6046 } 6047 6048 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6049 int cmd) 6050 { 6051 struct e1000_adapter *adapter = netdev_priv(netdev); 6052 struct mii_ioctl_data *data = if_mii(ifr); 6053 6054 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6055 return -EOPNOTSUPP; 6056 6057 switch (cmd) { 6058 case SIOCGMIIPHY: 6059 data->phy_id = adapter->hw.phy.addr; 6060 break; 6061 case SIOCGMIIREG: 6062 e1000_phy_read_status(adapter); 6063 6064 switch (data->reg_num & 0x1F) { 6065 case MII_BMCR: 6066 data->val_out = adapter->phy_regs.bmcr; 6067 break; 6068 case MII_BMSR: 6069 data->val_out = adapter->phy_regs.bmsr; 6070 break; 6071 case MII_PHYSID1: 6072 data->val_out = (adapter->hw.phy.id >> 16); 6073 break; 6074 case MII_PHYSID2: 6075 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6076 break; 6077 case MII_ADVERTISE: 6078 data->val_out = adapter->phy_regs.advertise; 6079 break; 6080 case MII_LPA: 6081 data->val_out = adapter->phy_regs.lpa; 6082 break; 6083 case MII_EXPANSION: 6084 data->val_out = adapter->phy_regs.expansion; 6085 break; 6086 case MII_CTRL1000: 6087 data->val_out = adapter->phy_regs.ctrl1000; 6088 break; 6089 case MII_STAT1000: 6090 data->val_out = adapter->phy_regs.stat1000; 6091 break; 6092 case MII_ESTATUS: 6093 data->val_out = adapter->phy_regs.estatus; 6094 break; 6095 default: 6096 return -EIO; 6097 } 6098 break; 6099 case SIOCSMIIREG: 6100 default: 6101 return -EOPNOTSUPP; 6102 } 6103 return 0; 6104 } 6105 6106 /** 6107 * e1000e_hwtstamp_ioctl - control hardware time stamping 6108 * @netdev: network interface device structure 6109 * @ifreq: interface request 6110 * 6111 * Outgoing time stamping can be enabled and disabled. Play nice and 6112 * disable it when requested, although it shouldn't cause any overhead 6113 * when no packet needs it. At most one packet in the queue may be 6114 * marked for time stamping, otherwise it would be impossible to tell 6115 * for sure to which packet the hardware time stamp belongs. 6116 * 6117 * Incoming time stamping has to be configured via the hardware filters. 6118 * Not all combinations are supported, in particular event type has to be 6119 * specified. Matching the kind of event packet is not supported, with the 6120 * exception of "all V2 events regardless of level 2 or 4". 6121 **/ 6122 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6123 { 6124 struct e1000_adapter *adapter = netdev_priv(netdev); 6125 struct hwtstamp_config config; 6126 int ret_val; 6127 6128 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6129 return -EFAULT; 6130 6131 ret_val = e1000e_config_hwtstamp(adapter, &config); 6132 if (ret_val) 6133 return ret_val; 6134 6135 switch (config.rx_filter) { 6136 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6137 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6138 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6139 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6140 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6141 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6142 /* With V2 type filters which specify a Sync or Delay Request, 6143 * Path Delay Request/Response messages are also time stamped 6144 * by hardware so notify the caller the requested packets plus 6145 * some others are time stamped. 6146 */ 6147 config.rx_filter = HWTSTAMP_FILTER_SOME; 6148 break; 6149 default: 6150 break; 6151 } 6152 6153 return copy_to_user(ifr->ifr_data, &config, 6154 sizeof(config)) ? -EFAULT : 0; 6155 } 6156 6157 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6158 { 6159 struct e1000_adapter *adapter = netdev_priv(netdev); 6160 6161 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6162 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6163 } 6164 6165 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6166 { 6167 switch (cmd) { 6168 case SIOCGMIIPHY: 6169 case SIOCGMIIREG: 6170 case SIOCSMIIREG: 6171 return e1000_mii_ioctl(netdev, ifr, cmd); 6172 case SIOCSHWTSTAMP: 6173 return e1000e_hwtstamp_set(netdev, ifr); 6174 case SIOCGHWTSTAMP: 6175 return e1000e_hwtstamp_get(netdev, ifr); 6176 default: 6177 return -EOPNOTSUPP; 6178 } 6179 } 6180 6181 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6182 { 6183 struct e1000_hw *hw = &adapter->hw; 6184 u32 i, mac_reg, wuc; 6185 u16 phy_reg, wuc_enable; 6186 int retval; 6187 6188 /* copy MAC RARs to PHY RARs */ 6189 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6190 6191 retval = hw->phy.ops.acquire(hw); 6192 if (retval) { 6193 e_err("Could not acquire PHY\n"); 6194 return retval; 6195 } 6196 6197 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6198 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6199 if (retval) 6200 goto release; 6201 6202 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6203 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6204 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6205 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6206 (u16)(mac_reg & 0xFFFF)); 6207 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6208 (u16)((mac_reg >> 16) & 0xFFFF)); 6209 } 6210 6211 /* configure PHY Rx Control register */ 6212 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6213 mac_reg = er32(RCTL); 6214 if (mac_reg & E1000_RCTL_UPE) 6215 phy_reg |= BM_RCTL_UPE; 6216 if (mac_reg & E1000_RCTL_MPE) 6217 phy_reg |= BM_RCTL_MPE; 6218 phy_reg &= ~(BM_RCTL_MO_MASK); 6219 if (mac_reg & E1000_RCTL_MO_3) 6220 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6221 << BM_RCTL_MO_SHIFT); 6222 if (mac_reg & E1000_RCTL_BAM) 6223 phy_reg |= BM_RCTL_BAM; 6224 if (mac_reg & E1000_RCTL_PMCF) 6225 phy_reg |= BM_RCTL_PMCF; 6226 mac_reg = er32(CTRL); 6227 if (mac_reg & E1000_CTRL_RFCE) 6228 phy_reg |= BM_RCTL_RFCE; 6229 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6230 6231 wuc = E1000_WUC_PME_EN; 6232 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6233 wuc |= E1000_WUC_APME; 6234 6235 /* enable PHY wakeup in MAC register */ 6236 ew32(WUFC, wufc); 6237 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6238 E1000_WUC_PME_STATUS | wuc)); 6239 6240 /* configure and enable PHY wakeup in PHY registers */ 6241 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6242 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6243 6244 /* activate PHY wakeup */ 6245 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6246 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6247 if (retval) 6248 e_err("Could not set PHY Host Wakeup bit\n"); 6249 release: 6250 hw->phy.ops.release(hw); 6251 6252 return retval; 6253 } 6254 6255 static void e1000e_flush_lpic(struct pci_dev *pdev) 6256 { 6257 struct net_device *netdev = pci_get_drvdata(pdev); 6258 struct e1000_adapter *adapter = netdev_priv(netdev); 6259 struct e1000_hw *hw = &adapter->hw; 6260 u32 ret_val; 6261 6262 pm_runtime_get_sync(netdev->dev.parent); 6263 6264 ret_val = hw->phy.ops.acquire(hw); 6265 if (ret_val) 6266 goto fl_out; 6267 6268 pr_info("EEE TX LPI TIMER: %08X\n", 6269 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6270 6271 hw->phy.ops.release(hw); 6272 6273 fl_out: 6274 pm_runtime_put_sync(netdev->dev.parent); 6275 } 6276 6277 static int e1000e_pm_freeze(struct device *dev) 6278 { 6279 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6280 struct e1000_adapter *adapter = netdev_priv(netdev); 6281 6282 netif_device_detach(netdev); 6283 6284 if (netif_running(netdev)) { 6285 int count = E1000_CHECK_RESET_COUNT; 6286 6287 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6288 usleep_range(10000, 20000); 6289 6290 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6291 6292 /* Quiesce the device without resetting the hardware */ 6293 e1000e_down(adapter, false); 6294 e1000_free_irq(adapter); 6295 } 6296 e1000e_reset_interrupt_capability(adapter); 6297 6298 /* Allow time for pending master requests to run */ 6299 e1000e_disable_pcie_master(&adapter->hw); 6300 6301 return 0; 6302 } 6303 6304 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6305 { 6306 struct net_device *netdev = pci_get_drvdata(pdev); 6307 struct e1000_adapter *adapter = netdev_priv(netdev); 6308 struct e1000_hw *hw = &adapter->hw; 6309 u32 ctrl, ctrl_ext, rctl, status; 6310 /* Runtime suspend should only enable wakeup for link changes */ 6311 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6312 int retval = 0; 6313 6314 status = er32(STATUS); 6315 if (status & E1000_STATUS_LU) 6316 wufc &= ~E1000_WUFC_LNKC; 6317 6318 if (wufc) { 6319 e1000_setup_rctl(adapter); 6320 e1000e_set_rx_mode(netdev); 6321 6322 /* turn on all-multi mode if wake on multicast is enabled */ 6323 if (wufc & E1000_WUFC_MC) { 6324 rctl = er32(RCTL); 6325 rctl |= E1000_RCTL_MPE; 6326 ew32(RCTL, rctl); 6327 } 6328 6329 ctrl = er32(CTRL); 6330 ctrl |= E1000_CTRL_ADVD3WUC; 6331 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6332 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6333 ew32(CTRL, ctrl); 6334 6335 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6336 adapter->hw.phy.media_type == 6337 e1000_media_type_internal_serdes) { 6338 /* keep the laser running in D3 */ 6339 ctrl_ext = er32(CTRL_EXT); 6340 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6341 ew32(CTRL_EXT, ctrl_ext); 6342 } 6343 6344 if (!runtime) 6345 e1000e_power_up_phy(adapter); 6346 6347 if (adapter->flags & FLAG_IS_ICH) 6348 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6349 6350 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6351 /* enable wakeup by the PHY */ 6352 retval = e1000_init_phy_wakeup(adapter, wufc); 6353 if (retval) 6354 return retval; 6355 } else { 6356 /* enable wakeup by the MAC */ 6357 ew32(WUFC, wufc); 6358 ew32(WUC, E1000_WUC_PME_EN); 6359 } 6360 } else { 6361 ew32(WUC, 0); 6362 ew32(WUFC, 0); 6363 6364 e1000_power_down_phy(adapter); 6365 } 6366 6367 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6368 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6369 } else if (hw->mac.type >= e1000_pch_lpt) { 6370 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6371 /* ULP does not support wake from unicast, multicast 6372 * or broadcast. 6373 */ 6374 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6375 6376 if (retval) 6377 return retval; 6378 } 6379 6380 /* Ensure that the appropriate bits are set in LPI_CTRL 6381 * for EEE in Sx 6382 */ 6383 if ((hw->phy.type >= e1000_phy_i217) && 6384 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6385 u16 lpi_ctrl = 0; 6386 6387 retval = hw->phy.ops.acquire(hw); 6388 if (!retval) { 6389 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6390 &lpi_ctrl); 6391 if (!retval) { 6392 if (adapter->eee_advert & 6393 hw->dev_spec.ich8lan.eee_lp_ability & 6394 I82579_EEE_100_SUPPORTED) 6395 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6396 if (adapter->eee_advert & 6397 hw->dev_spec.ich8lan.eee_lp_ability & 6398 I82579_EEE_1000_SUPPORTED) 6399 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6400 6401 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6402 lpi_ctrl); 6403 } 6404 } 6405 hw->phy.ops.release(hw); 6406 } 6407 6408 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6409 * would have already happened in close and is redundant. 6410 */ 6411 e1000e_release_hw_control(adapter); 6412 6413 pci_clear_master(pdev); 6414 6415 /* The pci-e switch on some quad port adapters will report a 6416 * correctable error when the MAC transitions from D0 to D3. To 6417 * prevent this we need to mask off the correctable errors on the 6418 * downstream port of the pci-e switch. 6419 * 6420 * We don't have the associated upstream bridge while assigning 6421 * the PCI device into guest. For example, the KVM on power is 6422 * one of the cases. 6423 */ 6424 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6425 struct pci_dev *us_dev = pdev->bus->self; 6426 u16 devctl; 6427 6428 if (!us_dev) 6429 return 0; 6430 6431 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6432 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6433 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6434 6435 pci_save_state(pdev); 6436 pci_prepare_to_sleep(pdev); 6437 6438 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6439 } 6440 6441 return 0; 6442 } 6443 6444 /** 6445 * __e1000e_disable_aspm - Disable ASPM states 6446 * @pdev: pointer to PCI device struct 6447 * @state: bit-mask of ASPM states to disable 6448 * @locked: indication if this context holds pci_bus_sem locked. 6449 * 6450 * Some devices *must* have certain ASPM states disabled per hardware errata. 6451 **/ 6452 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6453 { 6454 struct pci_dev *parent = pdev->bus->self; 6455 u16 aspm_dis_mask = 0; 6456 u16 pdev_aspmc, parent_aspmc; 6457 6458 switch (state) { 6459 case PCIE_LINK_STATE_L0S: 6460 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6461 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6462 /* fall-through - can't have L1 without L0s */ 6463 case PCIE_LINK_STATE_L1: 6464 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6465 break; 6466 default: 6467 return; 6468 } 6469 6470 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6471 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6472 6473 if (parent) { 6474 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6475 &parent_aspmc); 6476 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6477 } 6478 6479 /* Nothing to do if the ASPM states to be disabled already are */ 6480 if (!(pdev_aspmc & aspm_dis_mask) && 6481 (!parent || !(parent_aspmc & aspm_dis_mask))) 6482 return; 6483 6484 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6485 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6486 "L0s" : "", 6487 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6488 "L1" : ""); 6489 6490 #ifdef CONFIG_PCIEASPM 6491 if (locked) 6492 pci_disable_link_state_locked(pdev, state); 6493 else 6494 pci_disable_link_state(pdev, state); 6495 6496 /* Double-check ASPM control. If not disabled by the above, the 6497 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6498 * not enabled); override by writing PCI config space directly. 6499 */ 6500 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6501 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6502 6503 if (!(aspm_dis_mask & pdev_aspmc)) 6504 return; 6505 #endif 6506 6507 /* Both device and parent should have the same ASPM setting. 6508 * Disable ASPM in downstream component first and then upstream. 6509 */ 6510 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6511 6512 if (parent) 6513 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6514 aspm_dis_mask); 6515 } 6516 6517 /** 6518 * e1000e_disable_aspm - Disable ASPM states. 6519 * @pdev: pointer to PCI device struct 6520 * @state: bit-mask of ASPM states to disable 6521 * 6522 * This function acquires the pci_bus_sem! 6523 * Some devices *must* have certain ASPM states disabled per hardware errata. 6524 **/ 6525 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6526 { 6527 __e1000e_disable_aspm(pdev, state, 0); 6528 } 6529 6530 /** 6531 * e1000e_disable_aspm_locked Disable ASPM states. 6532 * @pdev: pointer to PCI device struct 6533 * @state: bit-mask of ASPM states to disable 6534 * 6535 * This function must be called with pci_bus_sem acquired! 6536 * Some devices *must* have certain ASPM states disabled per hardware errata. 6537 **/ 6538 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6539 { 6540 __e1000e_disable_aspm(pdev, state, 1); 6541 } 6542 6543 #ifdef CONFIG_PM 6544 static int __e1000_resume(struct pci_dev *pdev) 6545 { 6546 struct net_device *netdev = pci_get_drvdata(pdev); 6547 struct e1000_adapter *adapter = netdev_priv(netdev); 6548 struct e1000_hw *hw = &adapter->hw; 6549 u16 aspm_disable_flag = 0; 6550 6551 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6552 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6553 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6554 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6555 if (aspm_disable_flag) 6556 e1000e_disable_aspm(pdev, aspm_disable_flag); 6557 6558 pci_set_master(pdev); 6559 6560 if (hw->mac.type >= e1000_pch2lan) 6561 e1000_resume_workarounds_pchlan(&adapter->hw); 6562 6563 e1000e_power_up_phy(adapter); 6564 6565 /* report the system wakeup cause from S3/S4 */ 6566 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6567 u16 phy_data; 6568 6569 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6570 if (phy_data) { 6571 e_info("PHY Wakeup cause - %s\n", 6572 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6573 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6574 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6575 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6576 phy_data & E1000_WUS_LNKC ? 6577 "Link Status Change" : "other"); 6578 } 6579 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6580 } else { 6581 u32 wus = er32(WUS); 6582 6583 if (wus) { 6584 e_info("MAC Wakeup cause - %s\n", 6585 wus & E1000_WUS_EX ? "Unicast Packet" : 6586 wus & E1000_WUS_MC ? "Multicast Packet" : 6587 wus & E1000_WUS_BC ? "Broadcast Packet" : 6588 wus & E1000_WUS_MAG ? "Magic Packet" : 6589 wus & E1000_WUS_LNKC ? "Link Status Change" : 6590 "other"); 6591 } 6592 ew32(WUS, ~0); 6593 } 6594 6595 e1000e_reset(adapter); 6596 6597 e1000_init_manageability_pt(adapter); 6598 6599 /* If the controller has AMT, do not set DRV_LOAD until the interface 6600 * is up. For all other cases, let the f/w know that the h/w is now 6601 * under the control of the driver. 6602 */ 6603 if (!(adapter->flags & FLAG_HAS_AMT)) 6604 e1000e_get_hw_control(adapter); 6605 6606 return 0; 6607 } 6608 6609 #ifdef CONFIG_PM_SLEEP 6610 static int e1000e_pm_thaw(struct device *dev) 6611 { 6612 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6613 struct e1000_adapter *adapter = netdev_priv(netdev); 6614 6615 e1000e_set_interrupt_capability(adapter); 6616 if (netif_running(netdev)) { 6617 u32 err = e1000_request_irq(adapter); 6618 6619 if (err) 6620 return err; 6621 6622 e1000e_up(adapter); 6623 } 6624 6625 netif_device_attach(netdev); 6626 6627 return 0; 6628 } 6629 6630 static int e1000e_pm_suspend(struct device *dev) 6631 { 6632 struct pci_dev *pdev = to_pci_dev(dev); 6633 6634 e1000e_flush_lpic(pdev); 6635 6636 e1000e_pm_freeze(dev); 6637 6638 return __e1000_shutdown(pdev, false); 6639 } 6640 6641 static int e1000e_pm_resume(struct device *dev) 6642 { 6643 struct pci_dev *pdev = to_pci_dev(dev); 6644 int rc; 6645 6646 rc = __e1000_resume(pdev); 6647 if (rc) 6648 return rc; 6649 6650 return e1000e_pm_thaw(dev); 6651 } 6652 #endif /* CONFIG_PM_SLEEP */ 6653 6654 static int e1000e_pm_runtime_idle(struct device *dev) 6655 { 6656 struct pci_dev *pdev = to_pci_dev(dev); 6657 struct net_device *netdev = pci_get_drvdata(pdev); 6658 struct e1000_adapter *adapter = netdev_priv(netdev); 6659 u16 eee_lp; 6660 6661 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6662 6663 if (!e1000e_has_link(adapter)) { 6664 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6665 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6666 } 6667 6668 return -EBUSY; 6669 } 6670 6671 static int e1000e_pm_runtime_resume(struct device *dev) 6672 { 6673 struct pci_dev *pdev = to_pci_dev(dev); 6674 struct net_device *netdev = pci_get_drvdata(pdev); 6675 struct e1000_adapter *adapter = netdev_priv(netdev); 6676 int rc; 6677 6678 rc = __e1000_resume(pdev); 6679 if (rc) 6680 return rc; 6681 6682 if (netdev->flags & IFF_UP) 6683 e1000e_up(adapter); 6684 6685 return rc; 6686 } 6687 6688 static int e1000e_pm_runtime_suspend(struct device *dev) 6689 { 6690 struct pci_dev *pdev = to_pci_dev(dev); 6691 struct net_device *netdev = pci_get_drvdata(pdev); 6692 struct e1000_adapter *adapter = netdev_priv(netdev); 6693 6694 if (netdev->flags & IFF_UP) { 6695 int count = E1000_CHECK_RESET_COUNT; 6696 6697 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6698 usleep_range(10000, 20000); 6699 6700 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6701 6702 /* Down the device without resetting the hardware */ 6703 e1000e_down(adapter, false); 6704 } 6705 6706 if (__e1000_shutdown(pdev, true)) { 6707 e1000e_pm_runtime_resume(dev); 6708 return -EBUSY; 6709 } 6710 6711 return 0; 6712 } 6713 #endif /* CONFIG_PM */ 6714 6715 static void e1000_shutdown(struct pci_dev *pdev) 6716 { 6717 e1000e_flush_lpic(pdev); 6718 6719 e1000e_pm_freeze(&pdev->dev); 6720 6721 __e1000_shutdown(pdev, false); 6722 } 6723 6724 #ifdef CONFIG_NET_POLL_CONTROLLER 6725 6726 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6727 { 6728 struct net_device *netdev = data; 6729 struct e1000_adapter *adapter = netdev_priv(netdev); 6730 6731 if (adapter->msix_entries) { 6732 int vector, msix_irq; 6733 6734 vector = 0; 6735 msix_irq = adapter->msix_entries[vector].vector; 6736 disable_irq(msix_irq); 6737 e1000_intr_msix_rx(msix_irq, netdev); 6738 enable_irq(msix_irq); 6739 6740 vector++; 6741 msix_irq = adapter->msix_entries[vector].vector; 6742 disable_irq(msix_irq); 6743 e1000_intr_msix_tx(msix_irq, netdev); 6744 enable_irq(msix_irq); 6745 6746 vector++; 6747 msix_irq = adapter->msix_entries[vector].vector; 6748 disable_irq(msix_irq); 6749 e1000_msix_other(msix_irq, netdev); 6750 enable_irq(msix_irq); 6751 } 6752 6753 return IRQ_HANDLED; 6754 } 6755 6756 /** 6757 * e1000_netpoll 6758 * @netdev: network interface device structure 6759 * 6760 * Polling 'interrupt' - used by things like netconsole to send skbs 6761 * without having to re-enable interrupts. It's not called while 6762 * the interrupt routine is executing. 6763 */ 6764 static void e1000_netpoll(struct net_device *netdev) 6765 { 6766 struct e1000_adapter *adapter = netdev_priv(netdev); 6767 6768 switch (adapter->int_mode) { 6769 case E1000E_INT_MODE_MSIX: 6770 e1000_intr_msix(adapter->pdev->irq, netdev); 6771 break; 6772 case E1000E_INT_MODE_MSI: 6773 if (disable_hardirq(adapter->pdev->irq)) 6774 e1000_intr_msi(adapter->pdev->irq, netdev); 6775 enable_irq(adapter->pdev->irq); 6776 break; 6777 default: /* E1000E_INT_MODE_LEGACY */ 6778 if (disable_hardirq(adapter->pdev->irq)) 6779 e1000_intr(adapter->pdev->irq, netdev); 6780 enable_irq(adapter->pdev->irq); 6781 break; 6782 } 6783 } 6784 #endif 6785 6786 /** 6787 * e1000_io_error_detected - called when PCI error is detected 6788 * @pdev: Pointer to PCI device 6789 * @state: The current pci connection state 6790 * 6791 * This function is called after a PCI bus error affecting 6792 * this device has been detected. 6793 */ 6794 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6795 pci_channel_state_t state) 6796 { 6797 struct net_device *netdev = pci_get_drvdata(pdev); 6798 struct e1000_adapter *adapter = netdev_priv(netdev); 6799 6800 netif_device_detach(netdev); 6801 6802 if (state == pci_channel_io_perm_failure) 6803 return PCI_ERS_RESULT_DISCONNECT; 6804 6805 if (netif_running(netdev)) 6806 e1000e_down(adapter, true); 6807 pci_disable_device(pdev); 6808 6809 /* Request a slot slot reset. */ 6810 return PCI_ERS_RESULT_NEED_RESET; 6811 } 6812 6813 /** 6814 * e1000_io_slot_reset - called after the pci bus has been reset. 6815 * @pdev: Pointer to PCI device 6816 * 6817 * Restart the card from scratch, as if from a cold-boot. Implementation 6818 * resembles the first-half of the e1000e_pm_resume routine. 6819 */ 6820 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6821 { 6822 struct net_device *netdev = pci_get_drvdata(pdev); 6823 struct e1000_adapter *adapter = netdev_priv(netdev); 6824 struct e1000_hw *hw = &adapter->hw; 6825 u16 aspm_disable_flag = 0; 6826 int err; 6827 pci_ers_result_t result; 6828 6829 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6830 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6831 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6832 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6833 if (aspm_disable_flag) 6834 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 6835 6836 err = pci_enable_device_mem(pdev); 6837 if (err) { 6838 dev_err(&pdev->dev, 6839 "Cannot re-enable PCI device after reset.\n"); 6840 result = PCI_ERS_RESULT_DISCONNECT; 6841 } else { 6842 pdev->state_saved = true; 6843 pci_restore_state(pdev); 6844 pci_set_master(pdev); 6845 6846 pci_enable_wake(pdev, PCI_D3hot, 0); 6847 pci_enable_wake(pdev, PCI_D3cold, 0); 6848 6849 e1000e_reset(adapter); 6850 ew32(WUS, ~0); 6851 result = PCI_ERS_RESULT_RECOVERED; 6852 } 6853 6854 pci_cleanup_aer_uncorrect_error_status(pdev); 6855 6856 return result; 6857 } 6858 6859 /** 6860 * e1000_io_resume - called when traffic can start flowing again. 6861 * @pdev: Pointer to PCI device 6862 * 6863 * This callback is called when the error recovery driver tells us that 6864 * its OK to resume normal operation. Implementation resembles the 6865 * second-half of the e1000e_pm_resume routine. 6866 */ 6867 static void e1000_io_resume(struct pci_dev *pdev) 6868 { 6869 struct net_device *netdev = pci_get_drvdata(pdev); 6870 struct e1000_adapter *adapter = netdev_priv(netdev); 6871 6872 e1000_init_manageability_pt(adapter); 6873 6874 if (netif_running(netdev)) 6875 e1000e_up(adapter); 6876 6877 netif_device_attach(netdev); 6878 6879 /* If the controller has AMT, do not set DRV_LOAD until the interface 6880 * is up. For all other cases, let the f/w know that the h/w is now 6881 * under the control of the driver. 6882 */ 6883 if (!(adapter->flags & FLAG_HAS_AMT)) 6884 e1000e_get_hw_control(adapter); 6885 } 6886 6887 static void e1000_print_device_info(struct e1000_adapter *adapter) 6888 { 6889 struct e1000_hw *hw = &adapter->hw; 6890 struct net_device *netdev = adapter->netdev; 6891 u32 ret_val; 6892 u8 pba_str[E1000_PBANUM_LENGTH]; 6893 6894 /* print bus type/speed/width info */ 6895 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6896 /* bus width */ 6897 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6898 "Width x1"), 6899 /* MAC address */ 6900 netdev->dev_addr); 6901 e_info("Intel(R) PRO/%s Network Connection\n", 6902 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6903 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6904 E1000_PBANUM_LENGTH); 6905 if (ret_val) 6906 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6907 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6908 hw->mac.type, hw->phy.type, pba_str); 6909 } 6910 6911 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6912 { 6913 struct e1000_hw *hw = &adapter->hw; 6914 int ret_val; 6915 u16 buf = 0; 6916 6917 if (hw->mac.type != e1000_82573) 6918 return; 6919 6920 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6921 le16_to_cpus(&buf); 6922 if (!ret_val && (!(buf & BIT(0)))) { 6923 /* Deep Smart Power Down (DSPD) */ 6924 dev_warn(&adapter->pdev->dev, 6925 "Warning: detected DSPD enabled in EEPROM\n"); 6926 } 6927 } 6928 6929 static netdev_features_t e1000_fix_features(struct net_device *netdev, 6930 netdev_features_t features) 6931 { 6932 struct e1000_adapter *adapter = netdev_priv(netdev); 6933 struct e1000_hw *hw = &adapter->hw; 6934 6935 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6936 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 6937 features &= ~NETIF_F_RXFCS; 6938 6939 /* Since there is no support for separate Rx/Tx vlan accel 6940 * enable/disable make sure Tx flag is always in same state as Rx. 6941 */ 6942 if (features & NETIF_F_HW_VLAN_CTAG_RX) 6943 features |= NETIF_F_HW_VLAN_CTAG_TX; 6944 else 6945 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 6946 6947 return features; 6948 } 6949 6950 static int e1000_set_features(struct net_device *netdev, 6951 netdev_features_t features) 6952 { 6953 struct e1000_adapter *adapter = netdev_priv(netdev); 6954 netdev_features_t changed = features ^ netdev->features; 6955 6956 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6957 adapter->flags |= FLAG_TSO_FORCE; 6958 6959 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6960 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6961 NETIF_F_RXALL))) 6962 return 0; 6963 6964 if (changed & NETIF_F_RXFCS) { 6965 if (features & NETIF_F_RXFCS) { 6966 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6967 } else { 6968 /* We need to take it back to defaults, which might mean 6969 * stripping is still disabled at the adapter level. 6970 */ 6971 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 6972 adapter->flags2 |= FLAG2_CRC_STRIPPING; 6973 else 6974 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6975 } 6976 } 6977 6978 netdev->features = features; 6979 6980 if (netif_running(netdev)) 6981 e1000e_reinit_locked(adapter); 6982 else 6983 e1000e_reset(adapter); 6984 6985 return 0; 6986 } 6987 6988 static const struct net_device_ops e1000e_netdev_ops = { 6989 .ndo_open = e1000e_open, 6990 .ndo_stop = e1000e_close, 6991 .ndo_start_xmit = e1000_xmit_frame, 6992 .ndo_get_stats64 = e1000e_get_stats64, 6993 .ndo_set_rx_mode = e1000e_set_rx_mode, 6994 .ndo_set_mac_address = e1000_set_mac, 6995 .ndo_change_mtu = e1000_change_mtu, 6996 .ndo_do_ioctl = e1000_ioctl, 6997 .ndo_tx_timeout = e1000_tx_timeout, 6998 .ndo_validate_addr = eth_validate_addr, 6999 7000 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7001 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7002 #ifdef CONFIG_NET_POLL_CONTROLLER 7003 .ndo_poll_controller = e1000_netpoll, 7004 #endif 7005 .ndo_set_features = e1000_set_features, 7006 .ndo_fix_features = e1000_fix_features, 7007 .ndo_features_check = passthru_features_check, 7008 }; 7009 7010 /** 7011 * e1000_probe - Device Initialization Routine 7012 * @pdev: PCI device information struct 7013 * @ent: entry in e1000_pci_tbl 7014 * 7015 * Returns 0 on success, negative on failure 7016 * 7017 * e1000_probe initializes an adapter identified by a pci_dev structure. 7018 * The OS initialization, configuring of the adapter private structure, 7019 * and a hardware reset occur. 7020 **/ 7021 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7022 { 7023 struct net_device *netdev; 7024 struct e1000_adapter *adapter; 7025 struct e1000_hw *hw; 7026 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7027 resource_size_t mmio_start, mmio_len; 7028 resource_size_t flash_start, flash_len; 7029 static int cards_found; 7030 u16 aspm_disable_flag = 0; 7031 int bars, i, err, pci_using_dac; 7032 u16 eeprom_data = 0; 7033 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7034 s32 ret_val = 0; 7035 7036 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7037 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7038 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7039 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7040 if (aspm_disable_flag) 7041 e1000e_disable_aspm(pdev, aspm_disable_flag); 7042 7043 err = pci_enable_device_mem(pdev); 7044 if (err) 7045 return err; 7046 7047 pci_using_dac = 0; 7048 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7049 if (!err) { 7050 pci_using_dac = 1; 7051 } else { 7052 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7053 if (err) { 7054 dev_err(&pdev->dev, 7055 "No usable DMA configuration, aborting\n"); 7056 goto err_dma; 7057 } 7058 } 7059 7060 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7061 err = pci_request_selected_regions_exclusive(pdev, bars, 7062 e1000e_driver_name); 7063 if (err) 7064 goto err_pci_reg; 7065 7066 /* AER (Advanced Error Reporting) hooks */ 7067 pci_enable_pcie_error_reporting(pdev); 7068 7069 pci_set_master(pdev); 7070 /* PCI config space info */ 7071 err = pci_save_state(pdev); 7072 if (err) 7073 goto err_alloc_etherdev; 7074 7075 err = -ENOMEM; 7076 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7077 if (!netdev) 7078 goto err_alloc_etherdev; 7079 7080 SET_NETDEV_DEV(netdev, &pdev->dev); 7081 7082 netdev->irq = pdev->irq; 7083 7084 pci_set_drvdata(pdev, netdev); 7085 adapter = netdev_priv(netdev); 7086 hw = &adapter->hw; 7087 adapter->netdev = netdev; 7088 adapter->pdev = pdev; 7089 adapter->ei = ei; 7090 adapter->pba = ei->pba; 7091 adapter->flags = ei->flags; 7092 adapter->flags2 = ei->flags2; 7093 adapter->hw.adapter = adapter; 7094 adapter->hw.mac.type = ei->mac; 7095 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7096 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7097 7098 mmio_start = pci_resource_start(pdev, 0); 7099 mmio_len = pci_resource_len(pdev, 0); 7100 7101 err = -EIO; 7102 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7103 if (!adapter->hw.hw_addr) 7104 goto err_ioremap; 7105 7106 if ((adapter->flags & FLAG_HAS_FLASH) && 7107 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7108 (hw->mac.type < e1000_pch_spt)) { 7109 flash_start = pci_resource_start(pdev, 1); 7110 flash_len = pci_resource_len(pdev, 1); 7111 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7112 if (!adapter->hw.flash_address) 7113 goto err_flashmap; 7114 } 7115 7116 /* Set default EEE advertisement */ 7117 if (adapter->flags2 & FLAG2_HAS_EEE) 7118 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7119 7120 /* construct the net_device struct */ 7121 netdev->netdev_ops = &e1000e_netdev_ops; 7122 e1000e_set_ethtool_ops(netdev); 7123 netdev->watchdog_timeo = 5 * HZ; 7124 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7125 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7126 7127 netdev->mem_start = mmio_start; 7128 netdev->mem_end = mmio_start + mmio_len; 7129 7130 adapter->bd_number = cards_found++; 7131 7132 e1000e_check_options(adapter); 7133 7134 /* setup adapter struct */ 7135 err = e1000_sw_init(adapter); 7136 if (err) 7137 goto err_sw_init; 7138 7139 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7140 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7141 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7142 7143 err = ei->get_variants(adapter); 7144 if (err) 7145 goto err_hw_init; 7146 7147 if ((adapter->flags & FLAG_IS_ICH) && 7148 (adapter->flags & FLAG_READ_ONLY_NVM) && 7149 (hw->mac.type < e1000_pch_spt)) 7150 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7151 7152 hw->mac.ops.get_bus_info(&adapter->hw); 7153 7154 adapter->hw.phy.autoneg_wait_to_complete = 0; 7155 7156 /* Copper options */ 7157 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7158 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7159 adapter->hw.phy.disable_polarity_correction = 0; 7160 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7161 } 7162 7163 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7164 dev_info(&pdev->dev, 7165 "PHY reset is blocked due to SOL/IDER session.\n"); 7166 7167 /* Set initial default active device features */ 7168 netdev->features = (NETIF_F_SG | 7169 NETIF_F_HW_VLAN_CTAG_RX | 7170 NETIF_F_HW_VLAN_CTAG_TX | 7171 NETIF_F_TSO | 7172 NETIF_F_TSO6 | 7173 NETIF_F_RXHASH | 7174 NETIF_F_RXCSUM | 7175 NETIF_F_HW_CSUM); 7176 7177 /* Set user-changeable features (subset of all device features) */ 7178 netdev->hw_features = netdev->features; 7179 netdev->hw_features |= NETIF_F_RXFCS; 7180 netdev->priv_flags |= IFF_SUPP_NOFCS; 7181 netdev->hw_features |= NETIF_F_RXALL; 7182 7183 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7184 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7185 7186 netdev->vlan_features |= (NETIF_F_SG | 7187 NETIF_F_TSO | 7188 NETIF_F_TSO6 | 7189 NETIF_F_HW_CSUM); 7190 7191 netdev->priv_flags |= IFF_UNICAST_FLT; 7192 7193 if (pci_using_dac) { 7194 netdev->features |= NETIF_F_HIGHDMA; 7195 netdev->vlan_features |= NETIF_F_HIGHDMA; 7196 } 7197 7198 /* MTU range: 68 - max_hw_frame_size */ 7199 netdev->min_mtu = ETH_MIN_MTU; 7200 netdev->max_mtu = adapter->max_hw_frame_size - 7201 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7202 7203 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7204 adapter->flags |= FLAG_MNG_PT_ENABLED; 7205 7206 /* before reading the NVM, reset the controller to 7207 * put the device in a known good starting state 7208 */ 7209 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7210 7211 /* systems with ASPM and others may see the checksum fail on the first 7212 * attempt. Let's give it a few tries 7213 */ 7214 for (i = 0;; i++) { 7215 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7216 break; 7217 if (i == 2) { 7218 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7219 err = -EIO; 7220 goto err_eeprom; 7221 } 7222 } 7223 7224 e1000_eeprom_checks(adapter); 7225 7226 /* copy the MAC address */ 7227 if (e1000e_read_mac_addr(&adapter->hw)) 7228 dev_err(&pdev->dev, 7229 "NVM Read Error while reading MAC address\n"); 7230 7231 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7232 7233 if (!is_valid_ether_addr(netdev->dev_addr)) { 7234 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7235 netdev->dev_addr); 7236 err = -EIO; 7237 goto err_eeprom; 7238 } 7239 7240 init_timer(&adapter->watchdog_timer); 7241 adapter->watchdog_timer.function = e1000_watchdog; 7242 adapter->watchdog_timer.data = (unsigned long)adapter; 7243 7244 init_timer(&adapter->phy_info_timer); 7245 adapter->phy_info_timer.function = e1000_update_phy_info; 7246 adapter->phy_info_timer.data = (unsigned long)adapter; 7247 7248 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7249 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7250 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7251 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7252 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7253 7254 /* Initialize link parameters. User can change them with ethtool */ 7255 adapter->hw.mac.autoneg = 1; 7256 adapter->fc_autoneg = true; 7257 adapter->hw.fc.requested_mode = e1000_fc_default; 7258 adapter->hw.fc.current_mode = e1000_fc_default; 7259 adapter->hw.phy.autoneg_advertised = 0x2f; 7260 7261 /* Initial Wake on LAN setting - If APM wake is enabled in 7262 * the EEPROM, enable the ACPI Magic Packet filter 7263 */ 7264 if (adapter->flags & FLAG_APME_IN_WUC) { 7265 /* APME bit in EEPROM is mapped to WUC.APME */ 7266 eeprom_data = er32(WUC); 7267 eeprom_apme_mask = E1000_WUC_APME; 7268 if ((hw->mac.type > e1000_ich10lan) && 7269 (eeprom_data & E1000_WUC_PHY_WAKE)) 7270 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7271 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7272 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7273 (adapter->hw.bus.func == 1)) 7274 ret_val = e1000_read_nvm(&adapter->hw, 7275 NVM_INIT_CONTROL3_PORT_B, 7276 1, &eeprom_data); 7277 else 7278 ret_val = e1000_read_nvm(&adapter->hw, 7279 NVM_INIT_CONTROL3_PORT_A, 7280 1, &eeprom_data); 7281 } 7282 7283 /* fetch WoL from EEPROM */ 7284 if (ret_val) 7285 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7286 else if (eeprom_data & eeprom_apme_mask) 7287 adapter->eeprom_wol |= E1000_WUFC_MAG; 7288 7289 /* now that we have the eeprom settings, apply the special cases 7290 * where the eeprom may be wrong or the board simply won't support 7291 * wake on lan on a particular port 7292 */ 7293 if (!(adapter->flags & FLAG_HAS_WOL)) 7294 adapter->eeprom_wol = 0; 7295 7296 /* initialize the wol settings based on the eeprom settings */ 7297 adapter->wol = adapter->eeprom_wol; 7298 7299 /* make sure adapter isn't asleep if manageability is enabled */ 7300 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7301 (hw->mac.ops.check_mng_mode(hw))) 7302 device_wakeup_enable(&pdev->dev); 7303 7304 /* save off EEPROM version number */ 7305 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7306 7307 if (ret_val) { 7308 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7309 adapter->eeprom_vers = 0; 7310 } 7311 7312 /* init PTP hardware clock */ 7313 e1000e_ptp_init(adapter); 7314 7315 /* reset the hardware with the new settings */ 7316 e1000e_reset(adapter); 7317 7318 /* If the controller has AMT, do not set DRV_LOAD until the interface 7319 * is up. For all other cases, let the f/w know that the h/w is now 7320 * under the control of the driver. 7321 */ 7322 if (!(adapter->flags & FLAG_HAS_AMT)) 7323 e1000e_get_hw_control(adapter); 7324 7325 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7326 err = register_netdev(netdev); 7327 if (err) 7328 goto err_register; 7329 7330 /* carrier off reporting is important to ethtool even BEFORE open */ 7331 netif_carrier_off(netdev); 7332 7333 e1000_print_device_info(adapter); 7334 7335 if (pci_dev_run_wake(pdev)) 7336 pm_runtime_put_noidle(&pdev->dev); 7337 7338 return 0; 7339 7340 err_register: 7341 if (!(adapter->flags & FLAG_HAS_AMT)) 7342 e1000e_release_hw_control(adapter); 7343 err_eeprom: 7344 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7345 e1000_phy_hw_reset(&adapter->hw); 7346 err_hw_init: 7347 kfree(adapter->tx_ring); 7348 kfree(adapter->rx_ring); 7349 err_sw_init: 7350 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7351 iounmap(adapter->hw.flash_address); 7352 e1000e_reset_interrupt_capability(adapter); 7353 err_flashmap: 7354 iounmap(adapter->hw.hw_addr); 7355 err_ioremap: 7356 free_netdev(netdev); 7357 err_alloc_etherdev: 7358 pci_release_mem_regions(pdev); 7359 err_pci_reg: 7360 err_dma: 7361 pci_disable_device(pdev); 7362 return err; 7363 } 7364 7365 /** 7366 * e1000_remove - Device Removal Routine 7367 * @pdev: PCI device information struct 7368 * 7369 * e1000_remove is called by the PCI subsystem to alert the driver 7370 * that it should release a PCI device. The could be caused by a 7371 * Hot-Plug event, or because the driver is going to be removed from 7372 * memory. 7373 **/ 7374 static void e1000_remove(struct pci_dev *pdev) 7375 { 7376 struct net_device *netdev = pci_get_drvdata(pdev); 7377 struct e1000_adapter *adapter = netdev_priv(netdev); 7378 bool down = test_bit(__E1000_DOWN, &adapter->state); 7379 7380 e1000e_ptp_remove(adapter); 7381 7382 /* The timers may be rescheduled, so explicitly disable them 7383 * from being rescheduled. 7384 */ 7385 if (!down) 7386 set_bit(__E1000_DOWN, &adapter->state); 7387 del_timer_sync(&adapter->watchdog_timer); 7388 del_timer_sync(&adapter->phy_info_timer); 7389 7390 cancel_work_sync(&adapter->reset_task); 7391 cancel_work_sync(&adapter->watchdog_task); 7392 cancel_work_sync(&adapter->downshift_task); 7393 cancel_work_sync(&adapter->update_phy_task); 7394 cancel_work_sync(&adapter->print_hang_task); 7395 7396 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7397 cancel_work_sync(&adapter->tx_hwtstamp_work); 7398 if (adapter->tx_hwtstamp_skb) { 7399 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 7400 adapter->tx_hwtstamp_skb = NULL; 7401 } 7402 } 7403 7404 /* Don't lie to e1000_close() down the road. */ 7405 if (!down) 7406 clear_bit(__E1000_DOWN, &adapter->state); 7407 unregister_netdev(netdev); 7408 7409 if (pci_dev_run_wake(pdev)) 7410 pm_runtime_get_noresume(&pdev->dev); 7411 7412 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7413 * would have already happened in close and is redundant. 7414 */ 7415 e1000e_release_hw_control(adapter); 7416 7417 e1000e_reset_interrupt_capability(adapter); 7418 kfree(adapter->tx_ring); 7419 kfree(adapter->rx_ring); 7420 7421 iounmap(adapter->hw.hw_addr); 7422 if ((adapter->hw.flash_address) && 7423 (adapter->hw.mac.type < e1000_pch_spt)) 7424 iounmap(adapter->hw.flash_address); 7425 pci_release_mem_regions(pdev); 7426 7427 free_netdev(netdev); 7428 7429 /* AER disable */ 7430 pci_disable_pcie_error_reporting(pdev); 7431 7432 pci_disable_device(pdev); 7433 } 7434 7435 /* PCI Error Recovery (ERS) */ 7436 static const struct pci_error_handlers e1000_err_handler = { 7437 .error_detected = e1000_io_error_detected, 7438 .slot_reset = e1000_io_slot_reset, 7439 .resume = e1000_io_resume, 7440 }; 7441 7442 static const struct pci_device_id e1000_pci_tbl[] = { 7443 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7447 board_82571 }, 7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7449 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7453 7454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7458 7459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7462 7463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7466 7467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7468 board_80003es2lan }, 7469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7470 board_80003es2lan }, 7471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7472 board_80003es2lan }, 7473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7474 board_80003es2lan }, 7475 7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7484 7485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7494 7495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7498 7499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7502 7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7507 7508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7510 7511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7532 7533 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7534 }; 7535 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7536 7537 static const struct dev_pm_ops e1000_pm_ops = { 7538 #ifdef CONFIG_PM_SLEEP 7539 .suspend = e1000e_pm_suspend, 7540 .resume = e1000e_pm_resume, 7541 .freeze = e1000e_pm_freeze, 7542 .thaw = e1000e_pm_thaw, 7543 .poweroff = e1000e_pm_suspend, 7544 .restore = e1000e_pm_resume, 7545 #endif 7546 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7547 e1000e_pm_runtime_idle) 7548 }; 7549 7550 /* PCI Device API Driver */ 7551 static struct pci_driver e1000_driver = { 7552 .name = e1000e_driver_name, 7553 .id_table = e1000_pci_tbl, 7554 .probe = e1000_probe, 7555 .remove = e1000_remove, 7556 .driver = { 7557 .pm = &e1000_pm_ops, 7558 }, 7559 .shutdown = e1000_shutdown, 7560 .err_handler = &e1000_err_handler 7561 }; 7562 7563 /** 7564 * e1000_init_module - Driver Registration Routine 7565 * 7566 * e1000_init_module is the first routine called when the driver is 7567 * loaded. All it does is register with the PCI subsystem. 7568 **/ 7569 static int __init e1000_init_module(void) 7570 { 7571 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7572 e1000e_driver_version); 7573 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7574 7575 return pci_register_driver(&e1000_driver); 7576 } 7577 module_init(e1000_init_module); 7578 7579 /** 7580 * e1000_exit_module - Driver Exit Cleanup Routine 7581 * 7582 * e1000_exit_module is called just before the driver is removed 7583 * from memory. 7584 **/ 7585 static void __exit e1000_exit_module(void) 7586 { 7587 pci_unregister_driver(&e1000_driver); 7588 } 7589 module_exit(e1000_exit_module); 7590 7591 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7592 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7593 MODULE_LICENSE("GPL"); 7594 MODULE_VERSION(DRV_VERSION); 7595 7596 /* netdev.c */ 7597