1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/delay.h> 13 #include <linux/netdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/tcp.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/cpu.h> 23 #include <linux/smp.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/aer.h> 27 #include <linux/prefetch.h> 28 29 #include "e1000.h" 30 31 char e1000e_driver_name[] = "e1000e"; 32 33 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 34 static int debug = -1; 35 module_param(debug, int, 0); 36 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 37 38 static const struct e1000_info *e1000_info_tbl[] = { 39 [board_82571] = &e1000_82571_info, 40 [board_82572] = &e1000_82572_info, 41 [board_82573] = &e1000_82573_info, 42 [board_82574] = &e1000_82574_info, 43 [board_82583] = &e1000_82583_info, 44 [board_80003es2lan] = &e1000_es2_info, 45 [board_ich8lan] = &e1000_ich8_info, 46 [board_ich9lan] = &e1000_ich9_info, 47 [board_ich10lan] = &e1000_ich10_info, 48 [board_pchlan] = &e1000_pch_info, 49 [board_pch2lan] = &e1000_pch2_info, 50 [board_pch_lpt] = &e1000_pch_lpt_info, 51 [board_pch_spt] = &e1000_pch_spt_info, 52 [board_pch_cnp] = &e1000_pch_cnp_info, 53 }; 54 55 struct e1000_reg_info { 56 u32 ofs; 57 char *name; 58 }; 59 60 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 61 /* General Registers */ 62 {E1000_CTRL, "CTRL"}, 63 {E1000_STATUS, "STATUS"}, 64 {E1000_CTRL_EXT, "CTRL_EXT"}, 65 66 /* Interrupt Registers */ 67 {E1000_ICR, "ICR"}, 68 69 /* Rx Registers */ 70 {E1000_RCTL, "RCTL"}, 71 {E1000_RDLEN(0), "RDLEN"}, 72 {E1000_RDH(0), "RDH"}, 73 {E1000_RDT(0), "RDT"}, 74 {E1000_RDTR, "RDTR"}, 75 {E1000_RXDCTL(0), "RXDCTL"}, 76 {E1000_ERT, "ERT"}, 77 {E1000_RDBAL(0), "RDBAL"}, 78 {E1000_RDBAH(0), "RDBAH"}, 79 {E1000_RDFH, "RDFH"}, 80 {E1000_RDFT, "RDFT"}, 81 {E1000_RDFHS, "RDFHS"}, 82 {E1000_RDFTS, "RDFTS"}, 83 {E1000_RDFPC, "RDFPC"}, 84 85 /* Tx Registers */ 86 {E1000_TCTL, "TCTL"}, 87 {E1000_TDBAL(0), "TDBAL"}, 88 {E1000_TDBAH(0), "TDBAH"}, 89 {E1000_TDLEN(0), "TDLEN"}, 90 {E1000_TDH(0), "TDH"}, 91 {E1000_TDT(0), "TDT"}, 92 {E1000_TIDV, "TIDV"}, 93 {E1000_TXDCTL(0), "TXDCTL"}, 94 {E1000_TADV, "TADV"}, 95 {E1000_TARC(0), "TARC"}, 96 {E1000_TDFH, "TDFH"}, 97 {E1000_TDFT, "TDFT"}, 98 {E1000_TDFHS, "TDFHS"}, 99 {E1000_TDFTS, "TDFTS"}, 100 {E1000_TDFPC, "TDFPC"}, 101 102 /* List Terminator */ 103 {0, NULL} 104 }; 105 106 struct e1000e_me_supported { 107 u16 device_id; /* supported device ID */ 108 }; 109 110 static const struct e1000e_me_supported me_supported[] = { 111 {E1000_DEV_ID_PCH_LPT_I217_LM}, 112 {E1000_DEV_ID_PCH_LPTLP_I218_LM}, 113 {E1000_DEV_ID_PCH_I218_LM2}, 114 {E1000_DEV_ID_PCH_I218_LM3}, 115 {E1000_DEV_ID_PCH_SPT_I219_LM}, 116 {E1000_DEV_ID_PCH_SPT_I219_LM2}, 117 {E1000_DEV_ID_PCH_LBG_I219_LM3}, 118 {E1000_DEV_ID_PCH_SPT_I219_LM4}, 119 {E1000_DEV_ID_PCH_SPT_I219_LM5}, 120 {E1000_DEV_ID_PCH_CNP_I219_LM6}, 121 {E1000_DEV_ID_PCH_CNP_I219_LM7}, 122 {E1000_DEV_ID_PCH_ICP_I219_LM8}, 123 {E1000_DEV_ID_PCH_ICP_I219_LM9}, 124 {E1000_DEV_ID_PCH_CMP_I219_LM10}, 125 {E1000_DEV_ID_PCH_CMP_I219_LM11}, 126 {E1000_DEV_ID_PCH_CMP_I219_LM12}, 127 {E1000_DEV_ID_PCH_TGP_I219_LM13}, 128 {E1000_DEV_ID_PCH_TGP_I219_LM14}, 129 {E1000_DEV_ID_PCH_TGP_I219_LM15}, 130 {0} 131 }; 132 133 static bool e1000e_check_me(u16 device_id) 134 { 135 struct e1000e_me_supported *id; 136 137 for (id = (struct e1000e_me_supported *)me_supported; 138 id->device_id; id++) 139 if (device_id == id->device_id) 140 return true; 141 142 return false; 143 } 144 145 /** 146 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 147 * @hw: pointer to the HW structure 148 * 149 * When updating the MAC CSR registers, the Manageability Engine (ME) could 150 * be accessing the registers at the same time. Normally, this is handled in 151 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 152 * accesses later than it should which could result in the register to have 153 * an incorrect value. Workaround this by checking the FWSM register which 154 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 155 * and try again a number of times. 156 **/ 157 static void __ew32_prepare(struct e1000_hw *hw) 158 { 159 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 160 161 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 162 udelay(50); 163 } 164 165 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 166 { 167 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 168 __ew32_prepare(hw); 169 170 writel(val, hw->hw_addr + reg); 171 } 172 173 /** 174 * e1000_regdump - register printout routine 175 * @hw: pointer to the HW structure 176 * @reginfo: pointer to the register info table 177 **/ 178 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 179 { 180 int n = 0; 181 char rname[16]; 182 u32 regs[8]; 183 184 switch (reginfo->ofs) { 185 case E1000_RXDCTL(0): 186 for (n = 0; n < 2; n++) 187 regs[n] = __er32(hw, E1000_RXDCTL(n)); 188 break; 189 case E1000_TXDCTL(0): 190 for (n = 0; n < 2; n++) 191 regs[n] = __er32(hw, E1000_TXDCTL(n)); 192 break; 193 case E1000_TARC(0): 194 for (n = 0; n < 2; n++) 195 regs[n] = __er32(hw, E1000_TARC(n)); 196 break; 197 default: 198 pr_info("%-15s %08x\n", 199 reginfo->name, __er32(hw, reginfo->ofs)); 200 return; 201 } 202 203 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 204 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 205 } 206 207 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 208 struct e1000_buffer *bi) 209 { 210 int i; 211 struct e1000_ps_page *ps_page; 212 213 for (i = 0; i < adapter->rx_ps_pages; i++) { 214 ps_page = &bi->ps_pages[i]; 215 216 if (ps_page->page) { 217 pr_info("packet dump for ps_page %d:\n", i); 218 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 219 16, 1, page_address(ps_page->page), 220 PAGE_SIZE, true); 221 } 222 } 223 } 224 225 /** 226 * e1000e_dump - Print registers, Tx-ring and Rx-ring 227 * @adapter: board private structure 228 **/ 229 static void e1000e_dump(struct e1000_adapter *adapter) 230 { 231 struct net_device *netdev = adapter->netdev; 232 struct e1000_hw *hw = &adapter->hw; 233 struct e1000_reg_info *reginfo; 234 struct e1000_ring *tx_ring = adapter->tx_ring; 235 struct e1000_tx_desc *tx_desc; 236 struct my_u0 { 237 __le64 a; 238 __le64 b; 239 } *u0; 240 struct e1000_buffer *buffer_info; 241 struct e1000_ring *rx_ring = adapter->rx_ring; 242 union e1000_rx_desc_packet_split *rx_desc_ps; 243 union e1000_rx_desc_extended *rx_desc; 244 struct my_u1 { 245 __le64 a; 246 __le64 b; 247 __le64 c; 248 __le64 d; 249 } *u1; 250 u32 staterr; 251 int i = 0; 252 253 if (!netif_msg_hw(adapter)) 254 return; 255 256 /* Print netdevice Info */ 257 if (netdev) { 258 dev_info(&adapter->pdev->dev, "Net device Info\n"); 259 pr_info("Device Name state trans_start\n"); 260 pr_info("%-15s %016lX %016lX\n", netdev->name, 261 netdev->state, dev_trans_start(netdev)); 262 } 263 264 /* Print Registers */ 265 dev_info(&adapter->pdev->dev, "Register Dump\n"); 266 pr_info(" Register Name Value\n"); 267 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 268 reginfo->name; reginfo++) { 269 e1000_regdump(hw, reginfo); 270 } 271 272 /* Print Tx Ring Summary */ 273 if (!netdev || !netif_running(netdev)) 274 return; 275 276 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 277 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 278 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 279 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 280 0, tx_ring->next_to_use, tx_ring->next_to_clean, 281 (unsigned long long)buffer_info->dma, 282 buffer_info->length, 283 buffer_info->next_to_watch, 284 (unsigned long long)buffer_info->time_stamp); 285 286 /* Print Tx Ring */ 287 if (!netif_msg_tx_done(adapter)) 288 goto rx_ring_summary; 289 290 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 291 292 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 293 * 294 * Legacy Transmit Descriptor 295 * +--------------------------------------------------------------+ 296 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 297 * +--------------------------------------------------------------+ 298 * 8 | Special | CSS | Status | CMD | CSO | Length | 299 * +--------------------------------------------------------------+ 300 * 63 48 47 36 35 32 31 24 23 16 15 0 301 * 302 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 303 * 63 48 47 40 39 32 31 16 15 8 7 0 304 * +----------------------------------------------------------------+ 305 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 306 * +----------------------------------------------------------------+ 307 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 308 * +----------------------------------------------------------------+ 309 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 310 * 311 * Extended Data Descriptor (DTYP=0x1) 312 * +----------------------------------------------------------------+ 313 * 0 | Buffer Address [63:0] | 314 * +----------------------------------------------------------------+ 315 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 316 * +----------------------------------------------------------------+ 317 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 318 */ 319 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 320 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 321 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 322 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 323 const char *next_desc; 324 tx_desc = E1000_TX_DESC(*tx_ring, i); 325 buffer_info = &tx_ring->buffer_info[i]; 326 u0 = (struct my_u0 *)tx_desc; 327 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 328 next_desc = " NTC/U"; 329 else if (i == tx_ring->next_to_use) 330 next_desc = " NTU"; 331 else if (i == tx_ring->next_to_clean) 332 next_desc = " NTC"; 333 else 334 next_desc = ""; 335 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 336 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 337 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 338 i, 339 (unsigned long long)le64_to_cpu(u0->a), 340 (unsigned long long)le64_to_cpu(u0->b), 341 (unsigned long long)buffer_info->dma, 342 buffer_info->length, buffer_info->next_to_watch, 343 (unsigned long long)buffer_info->time_stamp, 344 buffer_info->skb, next_desc); 345 346 if (netif_msg_pktdata(adapter) && buffer_info->skb) 347 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 348 16, 1, buffer_info->skb->data, 349 buffer_info->skb->len, true); 350 } 351 352 /* Print Rx Ring Summary */ 353 rx_ring_summary: 354 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 355 pr_info("Queue [NTU] [NTC]\n"); 356 pr_info(" %5d %5X %5X\n", 357 0, rx_ring->next_to_use, rx_ring->next_to_clean); 358 359 /* Print Rx Ring */ 360 if (!netif_msg_rx_status(adapter)) 361 return; 362 363 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 364 switch (adapter->rx_ps_pages) { 365 case 1: 366 case 2: 367 case 3: 368 /* [Extended] Packet Split Receive Descriptor Format 369 * 370 * +-----------------------------------------------------+ 371 * 0 | Buffer Address 0 [63:0] | 372 * +-----------------------------------------------------+ 373 * 8 | Buffer Address 1 [63:0] | 374 * +-----------------------------------------------------+ 375 * 16 | Buffer Address 2 [63:0] | 376 * +-----------------------------------------------------+ 377 * 24 | Buffer Address 3 [63:0] | 378 * +-----------------------------------------------------+ 379 */ 380 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 381 /* [Extended] Receive Descriptor (Write-Back) Format 382 * 383 * 63 48 47 32 31 13 12 8 7 4 3 0 384 * +------------------------------------------------------+ 385 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 386 * | Checksum | Ident | | Queue | | Type | 387 * +------------------------------------------------------+ 388 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 389 * +------------------------------------------------------+ 390 * 63 48 47 32 31 20 19 0 391 */ 392 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 393 for (i = 0; i < rx_ring->count; i++) { 394 const char *next_desc; 395 buffer_info = &rx_ring->buffer_info[i]; 396 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 397 u1 = (struct my_u1 *)rx_desc_ps; 398 staterr = 399 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 400 401 if (i == rx_ring->next_to_use) 402 next_desc = " NTU"; 403 else if (i == rx_ring->next_to_clean) 404 next_desc = " NTC"; 405 else 406 next_desc = ""; 407 408 if (staterr & E1000_RXD_STAT_DD) { 409 /* Descriptor Done */ 410 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 411 "RWB", i, 412 (unsigned long long)le64_to_cpu(u1->a), 413 (unsigned long long)le64_to_cpu(u1->b), 414 (unsigned long long)le64_to_cpu(u1->c), 415 (unsigned long long)le64_to_cpu(u1->d), 416 buffer_info->skb, next_desc); 417 } else { 418 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 419 "R ", i, 420 (unsigned long long)le64_to_cpu(u1->a), 421 (unsigned long long)le64_to_cpu(u1->b), 422 (unsigned long long)le64_to_cpu(u1->c), 423 (unsigned long long)le64_to_cpu(u1->d), 424 (unsigned long long)buffer_info->dma, 425 buffer_info->skb, next_desc); 426 427 if (netif_msg_pktdata(adapter)) 428 e1000e_dump_ps_pages(adapter, 429 buffer_info); 430 } 431 } 432 break; 433 default: 434 case 0: 435 /* Extended Receive Descriptor (Read) Format 436 * 437 * +-----------------------------------------------------+ 438 * 0 | Buffer Address [63:0] | 439 * +-----------------------------------------------------+ 440 * 8 | Reserved | 441 * +-----------------------------------------------------+ 442 */ 443 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 444 /* Extended Receive Descriptor (Write-Back) Format 445 * 446 * 63 48 47 32 31 24 23 4 3 0 447 * +------------------------------------------------------+ 448 * | RSS Hash | | | | 449 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 450 * | Packet | IP | | | Type | 451 * | Checksum | Ident | | | | 452 * +------------------------------------------------------+ 453 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 454 * +------------------------------------------------------+ 455 * 63 48 47 32 31 20 19 0 456 */ 457 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 458 459 for (i = 0; i < rx_ring->count; i++) { 460 const char *next_desc; 461 462 buffer_info = &rx_ring->buffer_info[i]; 463 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 464 u1 = (struct my_u1 *)rx_desc; 465 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 466 467 if (i == rx_ring->next_to_use) 468 next_desc = " NTU"; 469 else if (i == rx_ring->next_to_clean) 470 next_desc = " NTC"; 471 else 472 next_desc = ""; 473 474 if (staterr & E1000_RXD_STAT_DD) { 475 /* Descriptor Done */ 476 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 477 "RWB", i, 478 (unsigned long long)le64_to_cpu(u1->a), 479 (unsigned long long)le64_to_cpu(u1->b), 480 buffer_info->skb, next_desc); 481 } else { 482 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 483 "R ", i, 484 (unsigned long long)le64_to_cpu(u1->a), 485 (unsigned long long)le64_to_cpu(u1->b), 486 (unsigned long long)buffer_info->dma, 487 buffer_info->skb, next_desc); 488 489 if (netif_msg_pktdata(adapter) && 490 buffer_info->skb) 491 print_hex_dump(KERN_INFO, "", 492 DUMP_PREFIX_ADDRESS, 16, 493 1, 494 buffer_info->skb->data, 495 adapter->rx_buffer_len, 496 true); 497 } 498 } 499 } 500 } 501 502 /** 503 * e1000_desc_unused - calculate if we have unused descriptors 504 **/ 505 static int e1000_desc_unused(struct e1000_ring *ring) 506 { 507 if (ring->next_to_clean > ring->next_to_use) 508 return ring->next_to_clean - ring->next_to_use - 1; 509 510 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 511 } 512 513 /** 514 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 515 * @adapter: board private structure 516 * @hwtstamps: time stamp structure to update 517 * @systim: unsigned 64bit system time value. 518 * 519 * Convert the system time value stored in the RX/TXSTMP registers into a 520 * hwtstamp which can be used by the upper level time stamping functions. 521 * 522 * The 'systim_lock' spinlock is used to protect the consistency of the 523 * system time value. This is needed because reading the 64 bit time 524 * value involves reading two 32 bit registers. The first read latches the 525 * value. 526 **/ 527 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 528 struct skb_shared_hwtstamps *hwtstamps, 529 u64 systim) 530 { 531 u64 ns; 532 unsigned long flags; 533 534 spin_lock_irqsave(&adapter->systim_lock, flags); 535 ns = timecounter_cyc2time(&adapter->tc, systim); 536 spin_unlock_irqrestore(&adapter->systim_lock, flags); 537 538 memset(hwtstamps, 0, sizeof(*hwtstamps)); 539 hwtstamps->hwtstamp = ns_to_ktime(ns); 540 } 541 542 /** 543 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 544 * @adapter: board private structure 545 * @status: descriptor extended error and status field 546 * @skb: particular skb to include time stamp 547 * 548 * If the time stamp is valid, convert it into the timecounter ns value 549 * and store that result into the shhwtstamps structure which is passed 550 * up the network stack. 551 **/ 552 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 553 struct sk_buff *skb) 554 { 555 struct e1000_hw *hw = &adapter->hw; 556 u64 rxstmp; 557 558 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 559 !(status & E1000_RXDEXT_STATERR_TST) || 560 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 561 return; 562 563 /* The Rx time stamp registers contain the time stamp. No other 564 * received packet will be time stamped until the Rx time stamp 565 * registers are read. Because only one packet can be time stamped 566 * at a time, the register values must belong to this packet and 567 * therefore none of the other additional attributes need to be 568 * compared. 569 */ 570 rxstmp = (u64)er32(RXSTMPL); 571 rxstmp |= (u64)er32(RXSTMPH) << 32; 572 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 573 574 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 575 } 576 577 /** 578 * e1000_receive_skb - helper function to handle Rx indications 579 * @adapter: board private structure 580 * @staterr: descriptor extended error and status field as written by hardware 581 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 582 * @skb: pointer to sk_buff to be indicated to stack 583 **/ 584 static void e1000_receive_skb(struct e1000_adapter *adapter, 585 struct net_device *netdev, struct sk_buff *skb, 586 u32 staterr, __le16 vlan) 587 { 588 u16 tag = le16_to_cpu(vlan); 589 590 e1000e_rx_hwtstamp(adapter, staterr, skb); 591 592 skb->protocol = eth_type_trans(skb, netdev); 593 594 if (staterr & E1000_RXD_STAT_VP) 595 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 596 597 napi_gro_receive(&adapter->napi, skb); 598 } 599 600 /** 601 * e1000_rx_checksum - Receive Checksum Offload 602 * @adapter: board private structure 603 * @status_err: receive descriptor status and error fields 604 * @csum: receive descriptor csum field 605 * @sk_buff: socket buffer with received data 606 **/ 607 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 608 struct sk_buff *skb) 609 { 610 u16 status = (u16)status_err; 611 u8 errors = (u8)(status_err >> 24); 612 613 skb_checksum_none_assert(skb); 614 615 /* Rx checksum disabled */ 616 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 617 return; 618 619 /* Ignore Checksum bit is set */ 620 if (status & E1000_RXD_STAT_IXSM) 621 return; 622 623 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 624 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 625 /* let the stack verify checksum errors */ 626 adapter->hw_csum_err++; 627 return; 628 } 629 630 /* TCP/UDP Checksum has not been calculated */ 631 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 632 return; 633 634 /* It must be a TCP or UDP packet with a valid checksum */ 635 skb->ip_summed = CHECKSUM_UNNECESSARY; 636 adapter->hw_csum_good++; 637 } 638 639 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 640 { 641 struct e1000_adapter *adapter = rx_ring->adapter; 642 struct e1000_hw *hw = &adapter->hw; 643 644 __ew32_prepare(hw); 645 writel(i, rx_ring->tail); 646 647 if (unlikely(i != readl(rx_ring->tail))) { 648 u32 rctl = er32(RCTL); 649 650 ew32(RCTL, rctl & ~E1000_RCTL_EN); 651 e_err("ME firmware caused invalid RDT - resetting\n"); 652 schedule_work(&adapter->reset_task); 653 } 654 } 655 656 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 657 { 658 struct e1000_adapter *adapter = tx_ring->adapter; 659 struct e1000_hw *hw = &adapter->hw; 660 661 __ew32_prepare(hw); 662 writel(i, tx_ring->tail); 663 664 if (unlikely(i != readl(tx_ring->tail))) { 665 u32 tctl = er32(TCTL); 666 667 ew32(TCTL, tctl & ~E1000_TCTL_EN); 668 e_err("ME firmware caused invalid TDT - resetting\n"); 669 schedule_work(&adapter->reset_task); 670 } 671 } 672 673 /** 674 * e1000_alloc_rx_buffers - Replace used receive buffers 675 * @rx_ring: Rx descriptor ring 676 **/ 677 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 678 int cleaned_count, gfp_t gfp) 679 { 680 struct e1000_adapter *adapter = rx_ring->adapter; 681 struct net_device *netdev = adapter->netdev; 682 struct pci_dev *pdev = adapter->pdev; 683 union e1000_rx_desc_extended *rx_desc; 684 struct e1000_buffer *buffer_info; 685 struct sk_buff *skb; 686 unsigned int i; 687 unsigned int bufsz = adapter->rx_buffer_len; 688 689 i = rx_ring->next_to_use; 690 buffer_info = &rx_ring->buffer_info[i]; 691 692 while (cleaned_count--) { 693 skb = buffer_info->skb; 694 if (skb) { 695 skb_trim(skb, 0); 696 goto map_skb; 697 } 698 699 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 700 if (!skb) { 701 /* Better luck next round */ 702 adapter->alloc_rx_buff_failed++; 703 break; 704 } 705 706 buffer_info->skb = skb; 707 map_skb: 708 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 709 adapter->rx_buffer_len, 710 DMA_FROM_DEVICE); 711 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 712 dev_err(&pdev->dev, "Rx DMA map failed\n"); 713 adapter->rx_dma_failed++; 714 break; 715 } 716 717 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 718 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 719 720 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 721 /* Force memory writes to complete before letting h/w 722 * know there are new descriptors to fetch. (Only 723 * applicable for weak-ordered memory model archs, 724 * such as IA-64). 725 */ 726 wmb(); 727 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 728 e1000e_update_rdt_wa(rx_ring, i); 729 else 730 writel(i, rx_ring->tail); 731 } 732 i++; 733 if (i == rx_ring->count) 734 i = 0; 735 buffer_info = &rx_ring->buffer_info[i]; 736 } 737 738 rx_ring->next_to_use = i; 739 } 740 741 /** 742 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 743 * @rx_ring: Rx descriptor ring 744 **/ 745 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 746 int cleaned_count, gfp_t gfp) 747 { 748 struct e1000_adapter *adapter = rx_ring->adapter; 749 struct net_device *netdev = adapter->netdev; 750 struct pci_dev *pdev = adapter->pdev; 751 union e1000_rx_desc_packet_split *rx_desc; 752 struct e1000_buffer *buffer_info; 753 struct e1000_ps_page *ps_page; 754 struct sk_buff *skb; 755 unsigned int i, j; 756 757 i = rx_ring->next_to_use; 758 buffer_info = &rx_ring->buffer_info[i]; 759 760 while (cleaned_count--) { 761 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 762 763 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 764 ps_page = &buffer_info->ps_pages[j]; 765 if (j >= adapter->rx_ps_pages) { 766 /* all unused desc entries get hw null ptr */ 767 rx_desc->read.buffer_addr[j + 1] = 768 ~cpu_to_le64(0); 769 continue; 770 } 771 if (!ps_page->page) { 772 ps_page->page = alloc_page(gfp); 773 if (!ps_page->page) { 774 adapter->alloc_rx_buff_failed++; 775 goto no_buffers; 776 } 777 ps_page->dma = dma_map_page(&pdev->dev, 778 ps_page->page, 779 0, PAGE_SIZE, 780 DMA_FROM_DEVICE); 781 if (dma_mapping_error(&pdev->dev, 782 ps_page->dma)) { 783 dev_err(&adapter->pdev->dev, 784 "Rx DMA page map failed\n"); 785 adapter->rx_dma_failed++; 786 goto no_buffers; 787 } 788 } 789 /* Refresh the desc even if buffer_addrs 790 * didn't change because each write-back 791 * erases this info. 792 */ 793 rx_desc->read.buffer_addr[j + 1] = 794 cpu_to_le64(ps_page->dma); 795 } 796 797 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 798 gfp); 799 800 if (!skb) { 801 adapter->alloc_rx_buff_failed++; 802 break; 803 } 804 805 buffer_info->skb = skb; 806 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 807 adapter->rx_ps_bsize0, 808 DMA_FROM_DEVICE); 809 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 810 dev_err(&pdev->dev, "Rx DMA map failed\n"); 811 adapter->rx_dma_failed++; 812 /* cleanup skb */ 813 dev_kfree_skb_any(skb); 814 buffer_info->skb = NULL; 815 break; 816 } 817 818 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 819 820 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 821 /* Force memory writes to complete before letting h/w 822 * know there are new descriptors to fetch. (Only 823 * applicable for weak-ordered memory model archs, 824 * such as IA-64). 825 */ 826 wmb(); 827 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 828 e1000e_update_rdt_wa(rx_ring, i << 1); 829 else 830 writel(i << 1, rx_ring->tail); 831 } 832 833 i++; 834 if (i == rx_ring->count) 835 i = 0; 836 buffer_info = &rx_ring->buffer_info[i]; 837 } 838 839 no_buffers: 840 rx_ring->next_to_use = i; 841 } 842 843 /** 844 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 845 * @rx_ring: Rx descriptor ring 846 * @cleaned_count: number of buffers to allocate this pass 847 **/ 848 849 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 850 int cleaned_count, gfp_t gfp) 851 { 852 struct e1000_adapter *adapter = rx_ring->adapter; 853 struct net_device *netdev = adapter->netdev; 854 struct pci_dev *pdev = adapter->pdev; 855 union e1000_rx_desc_extended *rx_desc; 856 struct e1000_buffer *buffer_info; 857 struct sk_buff *skb; 858 unsigned int i; 859 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 860 861 i = rx_ring->next_to_use; 862 buffer_info = &rx_ring->buffer_info[i]; 863 864 while (cleaned_count--) { 865 skb = buffer_info->skb; 866 if (skb) { 867 skb_trim(skb, 0); 868 goto check_page; 869 } 870 871 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 872 if (unlikely(!skb)) { 873 /* Better luck next round */ 874 adapter->alloc_rx_buff_failed++; 875 break; 876 } 877 878 buffer_info->skb = skb; 879 check_page: 880 /* allocate a new page if necessary */ 881 if (!buffer_info->page) { 882 buffer_info->page = alloc_page(gfp); 883 if (unlikely(!buffer_info->page)) { 884 adapter->alloc_rx_buff_failed++; 885 break; 886 } 887 } 888 889 if (!buffer_info->dma) { 890 buffer_info->dma = dma_map_page(&pdev->dev, 891 buffer_info->page, 0, 892 PAGE_SIZE, 893 DMA_FROM_DEVICE); 894 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 895 adapter->alloc_rx_buff_failed++; 896 break; 897 } 898 } 899 900 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 901 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 902 903 if (unlikely(++i == rx_ring->count)) 904 i = 0; 905 buffer_info = &rx_ring->buffer_info[i]; 906 } 907 908 if (likely(rx_ring->next_to_use != i)) { 909 rx_ring->next_to_use = i; 910 if (unlikely(i-- == 0)) 911 i = (rx_ring->count - 1); 912 913 /* Force memory writes to complete before letting h/w 914 * know there are new descriptors to fetch. (Only 915 * applicable for weak-ordered memory model archs, 916 * such as IA-64). 917 */ 918 wmb(); 919 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 920 e1000e_update_rdt_wa(rx_ring, i); 921 else 922 writel(i, rx_ring->tail); 923 } 924 } 925 926 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 927 struct sk_buff *skb) 928 { 929 if (netdev->features & NETIF_F_RXHASH) 930 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 931 } 932 933 /** 934 * e1000_clean_rx_irq - Send received data up the network stack 935 * @rx_ring: Rx descriptor ring 936 * 937 * the return value indicates whether actual cleaning was done, there 938 * is no guarantee that everything was cleaned 939 **/ 940 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 941 int work_to_do) 942 { 943 struct e1000_adapter *adapter = rx_ring->adapter; 944 struct net_device *netdev = adapter->netdev; 945 struct pci_dev *pdev = adapter->pdev; 946 struct e1000_hw *hw = &adapter->hw; 947 union e1000_rx_desc_extended *rx_desc, *next_rxd; 948 struct e1000_buffer *buffer_info, *next_buffer; 949 u32 length, staterr; 950 unsigned int i; 951 int cleaned_count = 0; 952 bool cleaned = false; 953 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 954 955 i = rx_ring->next_to_clean; 956 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 957 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 958 buffer_info = &rx_ring->buffer_info[i]; 959 960 while (staterr & E1000_RXD_STAT_DD) { 961 struct sk_buff *skb; 962 963 if (*work_done >= work_to_do) 964 break; 965 (*work_done)++; 966 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 967 968 skb = buffer_info->skb; 969 buffer_info->skb = NULL; 970 971 prefetch(skb->data - NET_IP_ALIGN); 972 973 i++; 974 if (i == rx_ring->count) 975 i = 0; 976 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 977 prefetch(next_rxd); 978 979 next_buffer = &rx_ring->buffer_info[i]; 980 981 cleaned = true; 982 cleaned_count++; 983 dma_unmap_single(&pdev->dev, buffer_info->dma, 984 adapter->rx_buffer_len, DMA_FROM_DEVICE); 985 buffer_info->dma = 0; 986 987 length = le16_to_cpu(rx_desc->wb.upper.length); 988 989 /* !EOP means multiple descriptors were used to store a single 990 * packet, if that's the case we need to toss it. In fact, we 991 * need to toss every packet with the EOP bit clear and the 992 * next frame that _does_ have the EOP bit set, as it is by 993 * definition only a frame fragment 994 */ 995 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 996 adapter->flags2 |= FLAG2_IS_DISCARDING; 997 998 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 999 /* All receives must fit into a single buffer */ 1000 e_dbg("Receive packet consumed multiple buffers\n"); 1001 /* recycle */ 1002 buffer_info->skb = skb; 1003 if (staterr & E1000_RXD_STAT_EOP) 1004 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1005 goto next_desc; 1006 } 1007 1008 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1009 !(netdev->features & NETIF_F_RXALL))) { 1010 /* recycle */ 1011 buffer_info->skb = skb; 1012 goto next_desc; 1013 } 1014 1015 /* adjust length to remove Ethernet CRC */ 1016 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1017 /* If configured to store CRC, don't subtract FCS, 1018 * but keep the FCS bytes out of the total_rx_bytes 1019 * counter 1020 */ 1021 if (netdev->features & NETIF_F_RXFCS) 1022 total_rx_bytes -= 4; 1023 else 1024 length -= 4; 1025 } 1026 1027 total_rx_bytes += length; 1028 total_rx_packets++; 1029 1030 /* code added for copybreak, this should improve 1031 * performance for small packets with large amounts 1032 * of reassembly being done in the stack 1033 */ 1034 if (length < copybreak) { 1035 struct sk_buff *new_skb = 1036 napi_alloc_skb(&adapter->napi, length); 1037 if (new_skb) { 1038 skb_copy_to_linear_data_offset(new_skb, 1039 -NET_IP_ALIGN, 1040 (skb->data - 1041 NET_IP_ALIGN), 1042 (length + 1043 NET_IP_ALIGN)); 1044 /* save the skb in buffer_info as good */ 1045 buffer_info->skb = skb; 1046 skb = new_skb; 1047 } 1048 /* else just continue with the old one */ 1049 } 1050 /* end copybreak code */ 1051 skb_put(skb, length); 1052 1053 /* Receive Checksum Offload */ 1054 e1000_rx_checksum(adapter, staterr, skb); 1055 1056 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1057 1058 e1000_receive_skb(adapter, netdev, skb, staterr, 1059 rx_desc->wb.upper.vlan); 1060 1061 next_desc: 1062 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1063 1064 /* return some buffers to hardware, one at a time is too slow */ 1065 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1066 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1067 GFP_ATOMIC); 1068 cleaned_count = 0; 1069 } 1070 1071 /* use prefetched values */ 1072 rx_desc = next_rxd; 1073 buffer_info = next_buffer; 1074 1075 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1076 } 1077 rx_ring->next_to_clean = i; 1078 1079 cleaned_count = e1000_desc_unused(rx_ring); 1080 if (cleaned_count) 1081 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1082 1083 adapter->total_rx_bytes += total_rx_bytes; 1084 adapter->total_rx_packets += total_rx_packets; 1085 return cleaned; 1086 } 1087 1088 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1089 struct e1000_buffer *buffer_info, 1090 bool drop) 1091 { 1092 struct e1000_adapter *adapter = tx_ring->adapter; 1093 1094 if (buffer_info->dma) { 1095 if (buffer_info->mapped_as_page) 1096 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1097 buffer_info->length, DMA_TO_DEVICE); 1098 else 1099 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1100 buffer_info->length, DMA_TO_DEVICE); 1101 buffer_info->dma = 0; 1102 } 1103 if (buffer_info->skb) { 1104 if (drop) 1105 dev_kfree_skb_any(buffer_info->skb); 1106 else 1107 dev_consume_skb_any(buffer_info->skb); 1108 buffer_info->skb = NULL; 1109 } 1110 buffer_info->time_stamp = 0; 1111 } 1112 1113 static void e1000_print_hw_hang(struct work_struct *work) 1114 { 1115 struct e1000_adapter *adapter = container_of(work, 1116 struct e1000_adapter, 1117 print_hang_task); 1118 struct net_device *netdev = adapter->netdev; 1119 struct e1000_ring *tx_ring = adapter->tx_ring; 1120 unsigned int i = tx_ring->next_to_clean; 1121 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1122 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1123 struct e1000_hw *hw = &adapter->hw; 1124 u16 phy_status, phy_1000t_status, phy_ext_status; 1125 u16 pci_status; 1126 1127 if (test_bit(__E1000_DOWN, &adapter->state)) 1128 return; 1129 1130 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1131 /* May be block on write-back, flush and detect again 1132 * flush pending descriptor writebacks to memory 1133 */ 1134 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1135 /* execute the writes immediately */ 1136 e1e_flush(); 1137 /* Due to rare timing issues, write to TIDV again to ensure 1138 * the write is successful 1139 */ 1140 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1141 /* execute the writes immediately */ 1142 e1e_flush(); 1143 adapter->tx_hang_recheck = true; 1144 return; 1145 } 1146 adapter->tx_hang_recheck = false; 1147 1148 if (er32(TDH(0)) == er32(TDT(0))) { 1149 e_dbg("false hang detected, ignoring\n"); 1150 return; 1151 } 1152 1153 /* Real hang detected */ 1154 netif_stop_queue(netdev); 1155 1156 e1e_rphy(hw, MII_BMSR, &phy_status); 1157 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1158 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1159 1160 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1161 1162 /* detected Hardware unit hang */ 1163 e_err("Detected Hardware Unit Hang:\n" 1164 " TDH <%x>\n" 1165 " TDT <%x>\n" 1166 " next_to_use <%x>\n" 1167 " next_to_clean <%x>\n" 1168 "buffer_info[next_to_clean]:\n" 1169 " time_stamp <%lx>\n" 1170 " next_to_watch <%x>\n" 1171 " jiffies <%lx>\n" 1172 " next_to_watch.status <%x>\n" 1173 "MAC Status <%x>\n" 1174 "PHY Status <%x>\n" 1175 "PHY 1000BASE-T Status <%x>\n" 1176 "PHY Extended Status <%x>\n" 1177 "PCI Status <%x>\n", 1178 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1179 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1180 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1181 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1182 1183 e1000e_dump(adapter); 1184 1185 /* Suggest workaround for known h/w issue */ 1186 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1187 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1188 } 1189 1190 /** 1191 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1192 * @work: pointer to work struct 1193 * 1194 * This work function polls the TSYNCTXCTL valid bit to determine when a 1195 * timestamp has been taken for the current stored skb. The timestamp must 1196 * be for this skb because only one such packet is allowed in the queue. 1197 */ 1198 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1199 { 1200 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1201 tx_hwtstamp_work); 1202 struct e1000_hw *hw = &adapter->hw; 1203 1204 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1205 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1206 struct skb_shared_hwtstamps shhwtstamps; 1207 u64 txstmp; 1208 1209 txstmp = er32(TXSTMPL); 1210 txstmp |= (u64)er32(TXSTMPH) << 32; 1211 1212 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1213 1214 /* Clear the global tx_hwtstamp_skb pointer and force writes 1215 * prior to notifying the stack of a Tx timestamp. 1216 */ 1217 adapter->tx_hwtstamp_skb = NULL; 1218 wmb(); /* force write prior to skb_tstamp_tx */ 1219 1220 skb_tstamp_tx(skb, &shhwtstamps); 1221 dev_consume_skb_any(skb); 1222 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1223 + adapter->tx_timeout_factor * HZ)) { 1224 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1225 adapter->tx_hwtstamp_skb = NULL; 1226 adapter->tx_hwtstamp_timeouts++; 1227 e_warn("clearing Tx timestamp hang\n"); 1228 } else { 1229 /* reschedule to check later */ 1230 schedule_work(&adapter->tx_hwtstamp_work); 1231 } 1232 } 1233 1234 /** 1235 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1236 * @tx_ring: Tx descriptor ring 1237 * 1238 * the return value indicates whether actual cleaning was done, there 1239 * is no guarantee that everything was cleaned 1240 **/ 1241 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1242 { 1243 struct e1000_adapter *adapter = tx_ring->adapter; 1244 struct net_device *netdev = adapter->netdev; 1245 struct e1000_hw *hw = &adapter->hw; 1246 struct e1000_tx_desc *tx_desc, *eop_desc; 1247 struct e1000_buffer *buffer_info; 1248 unsigned int i, eop; 1249 unsigned int count = 0; 1250 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1251 unsigned int bytes_compl = 0, pkts_compl = 0; 1252 1253 i = tx_ring->next_to_clean; 1254 eop = tx_ring->buffer_info[i].next_to_watch; 1255 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1256 1257 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1258 (count < tx_ring->count)) { 1259 bool cleaned = false; 1260 1261 dma_rmb(); /* read buffer_info after eop_desc */ 1262 for (; !cleaned; count++) { 1263 tx_desc = E1000_TX_DESC(*tx_ring, i); 1264 buffer_info = &tx_ring->buffer_info[i]; 1265 cleaned = (i == eop); 1266 1267 if (cleaned) { 1268 total_tx_packets += buffer_info->segs; 1269 total_tx_bytes += buffer_info->bytecount; 1270 if (buffer_info->skb) { 1271 bytes_compl += buffer_info->skb->len; 1272 pkts_compl++; 1273 } 1274 } 1275 1276 e1000_put_txbuf(tx_ring, buffer_info, false); 1277 tx_desc->upper.data = 0; 1278 1279 i++; 1280 if (i == tx_ring->count) 1281 i = 0; 1282 } 1283 1284 if (i == tx_ring->next_to_use) 1285 break; 1286 eop = tx_ring->buffer_info[i].next_to_watch; 1287 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1288 } 1289 1290 tx_ring->next_to_clean = i; 1291 1292 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1293 1294 #define TX_WAKE_THRESHOLD 32 1295 if (count && netif_carrier_ok(netdev) && 1296 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1297 /* Make sure that anybody stopping the queue after this 1298 * sees the new next_to_clean. 1299 */ 1300 smp_mb(); 1301 1302 if (netif_queue_stopped(netdev) && 1303 !(test_bit(__E1000_DOWN, &adapter->state))) { 1304 netif_wake_queue(netdev); 1305 ++adapter->restart_queue; 1306 } 1307 } 1308 1309 if (adapter->detect_tx_hung) { 1310 /* Detect a transmit hang in hardware, this serializes the 1311 * check with the clearing of time_stamp and movement of i 1312 */ 1313 adapter->detect_tx_hung = false; 1314 if (tx_ring->buffer_info[i].time_stamp && 1315 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1316 + (adapter->tx_timeout_factor * HZ)) && 1317 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1318 schedule_work(&adapter->print_hang_task); 1319 else 1320 adapter->tx_hang_recheck = false; 1321 } 1322 adapter->total_tx_bytes += total_tx_bytes; 1323 adapter->total_tx_packets += total_tx_packets; 1324 return count < tx_ring->count; 1325 } 1326 1327 /** 1328 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1329 * @rx_ring: Rx descriptor ring 1330 * 1331 * the return value indicates whether actual cleaning was done, there 1332 * is no guarantee that everything was cleaned 1333 **/ 1334 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1335 int work_to_do) 1336 { 1337 struct e1000_adapter *adapter = rx_ring->adapter; 1338 struct e1000_hw *hw = &adapter->hw; 1339 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1340 struct net_device *netdev = adapter->netdev; 1341 struct pci_dev *pdev = adapter->pdev; 1342 struct e1000_buffer *buffer_info, *next_buffer; 1343 struct e1000_ps_page *ps_page; 1344 struct sk_buff *skb; 1345 unsigned int i, j; 1346 u32 length, staterr; 1347 int cleaned_count = 0; 1348 bool cleaned = false; 1349 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1350 1351 i = rx_ring->next_to_clean; 1352 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1353 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1354 buffer_info = &rx_ring->buffer_info[i]; 1355 1356 while (staterr & E1000_RXD_STAT_DD) { 1357 if (*work_done >= work_to_do) 1358 break; 1359 (*work_done)++; 1360 skb = buffer_info->skb; 1361 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1362 1363 /* in the packet split case this is header only */ 1364 prefetch(skb->data - NET_IP_ALIGN); 1365 1366 i++; 1367 if (i == rx_ring->count) 1368 i = 0; 1369 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1370 prefetch(next_rxd); 1371 1372 next_buffer = &rx_ring->buffer_info[i]; 1373 1374 cleaned = true; 1375 cleaned_count++; 1376 dma_unmap_single(&pdev->dev, buffer_info->dma, 1377 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1378 buffer_info->dma = 0; 1379 1380 /* see !EOP comment in other Rx routine */ 1381 if (!(staterr & E1000_RXD_STAT_EOP)) 1382 adapter->flags2 |= FLAG2_IS_DISCARDING; 1383 1384 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1385 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1386 dev_kfree_skb_irq(skb); 1387 if (staterr & E1000_RXD_STAT_EOP) 1388 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1389 goto next_desc; 1390 } 1391 1392 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1393 !(netdev->features & NETIF_F_RXALL))) { 1394 dev_kfree_skb_irq(skb); 1395 goto next_desc; 1396 } 1397 1398 length = le16_to_cpu(rx_desc->wb.middle.length0); 1399 1400 if (!length) { 1401 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1402 dev_kfree_skb_irq(skb); 1403 goto next_desc; 1404 } 1405 1406 /* Good Receive */ 1407 skb_put(skb, length); 1408 1409 { 1410 /* this looks ugly, but it seems compiler issues make 1411 * it more efficient than reusing j 1412 */ 1413 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1414 1415 /* page alloc/put takes too long and effects small 1416 * packet throughput, so unsplit small packets and 1417 * save the alloc/put only valid in softirq (napi) 1418 * context to call kmap_* 1419 */ 1420 if (l1 && (l1 <= copybreak) && 1421 ((length + l1) <= adapter->rx_ps_bsize0)) { 1422 u8 *vaddr; 1423 1424 ps_page = &buffer_info->ps_pages[0]; 1425 1426 /* there is no documentation about how to call 1427 * kmap_atomic, so we can't hold the mapping 1428 * very long 1429 */ 1430 dma_sync_single_for_cpu(&pdev->dev, 1431 ps_page->dma, 1432 PAGE_SIZE, 1433 DMA_FROM_DEVICE); 1434 vaddr = kmap_atomic(ps_page->page); 1435 memcpy(skb_tail_pointer(skb), vaddr, l1); 1436 kunmap_atomic(vaddr); 1437 dma_sync_single_for_device(&pdev->dev, 1438 ps_page->dma, 1439 PAGE_SIZE, 1440 DMA_FROM_DEVICE); 1441 1442 /* remove the CRC */ 1443 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1444 if (!(netdev->features & NETIF_F_RXFCS)) 1445 l1 -= 4; 1446 } 1447 1448 skb_put(skb, l1); 1449 goto copydone; 1450 } /* if */ 1451 } 1452 1453 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1454 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1455 if (!length) 1456 break; 1457 1458 ps_page = &buffer_info->ps_pages[j]; 1459 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1460 DMA_FROM_DEVICE); 1461 ps_page->dma = 0; 1462 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1463 ps_page->page = NULL; 1464 skb->len += length; 1465 skb->data_len += length; 1466 skb->truesize += PAGE_SIZE; 1467 } 1468 1469 /* strip the ethernet crc, problem is we're using pages now so 1470 * this whole operation can get a little cpu intensive 1471 */ 1472 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1473 if (!(netdev->features & NETIF_F_RXFCS)) 1474 pskb_trim(skb, skb->len - 4); 1475 } 1476 1477 copydone: 1478 total_rx_bytes += skb->len; 1479 total_rx_packets++; 1480 1481 e1000_rx_checksum(adapter, staterr, skb); 1482 1483 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1484 1485 if (rx_desc->wb.upper.header_status & 1486 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1487 adapter->rx_hdr_split++; 1488 1489 e1000_receive_skb(adapter, netdev, skb, staterr, 1490 rx_desc->wb.middle.vlan); 1491 1492 next_desc: 1493 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1494 buffer_info->skb = NULL; 1495 1496 /* return some buffers to hardware, one at a time is too slow */ 1497 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1498 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1499 GFP_ATOMIC); 1500 cleaned_count = 0; 1501 } 1502 1503 /* use prefetched values */ 1504 rx_desc = next_rxd; 1505 buffer_info = next_buffer; 1506 1507 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1508 } 1509 rx_ring->next_to_clean = i; 1510 1511 cleaned_count = e1000_desc_unused(rx_ring); 1512 if (cleaned_count) 1513 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1514 1515 adapter->total_rx_bytes += total_rx_bytes; 1516 adapter->total_rx_packets += total_rx_packets; 1517 return cleaned; 1518 } 1519 1520 /** 1521 * e1000_consume_page - helper function 1522 **/ 1523 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1524 u16 length) 1525 { 1526 bi->page = NULL; 1527 skb->len += length; 1528 skb->data_len += length; 1529 skb->truesize += PAGE_SIZE; 1530 } 1531 1532 /** 1533 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1534 * @adapter: board private structure 1535 * 1536 * the return value indicates whether actual cleaning was done, there 1537 * is no guarantee that everything was cleaned 1538 **/ 1539 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1540 int work_to_do) 1541 { 1542 struct e1000_adapter *adapter = rx_ring->adapter; 1543 struct net_device *netdev = adapter->netdev; 1544 struct pci_dev *pdev = adapter->pdev; 1545 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1546 struct e1000_buffer *buffer_info, *next_buffer; 1547 u32 length, staterr; 1548 unsigned int i; 1549 int cleaned_count = 0; 1550 bool cleaned = false; 1551 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1552 struct skb_shared_info *shinfo; 1553 1554 i = rx_ring->next_to_clean; 1555 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1556 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1557 buffer_info = &rx_ring->buffer_info[i]; 1558 1559 while (staterr & E1000_RXD_STAT_DD) { 1560 struct sk_buff *skb; 1561 1562 if (*work_done >= work_to_do) 1563 break; 1564 (*work_done)++; 1565 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1566 1567 skb = buffer_info->skb; 1568 buffer_info->skb = NULL; 1569 1570 ++i; 1571 if (i == rx_ring->count) 1572 i = 0; 1573 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1574 prefetch(next_rxd); 1575 1576 next_buffer = &rx_ring->buffer_info[i]; 1577 1578 cleaned = true; 1579 cleaned_count++; 1580 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1581 DMA_FROM_DEVICE); 1582 buffer_info->dma = 0; 1583 1584 length = le16_to_cpu(rx_desc->wb.upper.length); 1585 1586 /* errors is only valid for DD + EOP descriptors */ 1587 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1588 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1589 !(netdev->features & NETIF_F_RXALL)))) { 1590 /* recycle both page and skb */ 1591 buffer_info->skb = skb; 1592 /* an error means any chain goes out the window too */ 1593 if (rx_ring->rx_skb_top) 1594 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1595 rx_ring->rx_skb_top = NULL; 1596 goto next_desc; 1597 } 1598 #define rxtop (rx_ring->rx_skb_top) 1599 if (!(staterr & E1000_RXD_STAT_EOP)) { 1600 /* this descriptor is only the beginning (or middle) */ 1601 if (!rxtop) { 1602 /* this is the beginning of a chain */ 1603 rxtop = skb; 1604 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1605 0, length); 1606 } else { 1607 /* this is the middle of a chain */ 1608 shinfo = skb_shinfo(rxtop); 1609 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1610 buffer_info->page, 0, 1611 length); 1612 /* re-use the skb, only consumed the page */ 1613 buffer_info->skb = skb; 1614 } 1615 e1000_consume_page(buffer_info, rxtop, length); 1616 goto next_desc; 1617 } else { 1618 if (rxtop) { 1619 /* end of the chain */ 1620 shinfo = skb_shinfo(rxtop); 1621 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1622 buffer_info->page, 0, 1623 length); 1624 /* re-use the current skb, we only consumed the 1625 * page 1626 */ 1627 buffer_info->skb = skb; 1628 skb = rxtop; 1629 rxtop = NULL; 1630 e1000_consume_page(buffer_info, skb, length); 1631 } else { 1632 /* no chain, got EOP, this buf is the packet 1633 * copybreak to save the put_page/alloc_page 1634 */ 1635 if (length <= copybreak && 1636 skb_tailroom(skb) >= length) { 1637 u8 *vaddr; 1638 vaddr = kmap_atomic(buffer_info->page); 1639 memcpy(skb_tail_pointer(skb), vaddr, 1640 length); 1641 kunmap_atomic(vaddr); 1642 /* re-use the page, so don't erase 1643 * buffer_info->page 1644 */ 1645 skb_put(skb, length); 1646 } else { 1647 skb_fill_page_desc(skb, 0, 1648 buffer_info->page, 0, 1649 length); 1650 e1000_consume_page(buffer_info, skb, 1651 length); 1652 } 1653 } 1654 } 1655 1656 /* Receive Checksum Offload */ 1657 e1000_rx_checksum(adapter, staterr, skb); 1658 1659 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1660 1661 /* probably a little skewed due to removing CRC */ 1662 total_rx_bytes += skb->len; 1663 total_rx_packets++; 1664 1665 /* eth type trans needs skb->data to point to something */ 1666 if (!pskb_may_pull(skb, ETH_HLEN)) { 1667 e_err("pskb_may_pull failed.\n"); 1668 dev_kfree_skb_irq(skb); 1669 goto next_desc; 1670 } 1671 1672 e1000_receive_skb(adapter, netdev, skb, staterr, 1673 rx_desc->wb.upper.vlan); 1674 1675 next_desc: 1676 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1677 1678 /* return some buffers to hardware, one at a time is too slow */ 1679 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1680 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1681 GFP_ATOMIC); 1682 cleaned_count = 0; 1683 } 1684 1685 /* use prefetched values */ 1686 rx_desc = next_rxd; 1687 buffer_info = next_buffer; 1688 1689 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1690 } 1691 rx_ring->next_to_clean = i; 1692 1693 cleaned_count = e1000_desc_unused(rx_ring); 1694 if (cleaned_count) 1695 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1696 1697 adapter->total_rx_bytes += total_rx_bytes; 1698 adapter->total_rx_packets += total_rx_packets; 1699 return cleaned; 1700 } 1701 1702 /** 1703 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1704 * @rx_ring: Rx descriptor ring 1705 **/ 1706 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1707 { 1708 struct e1000_adapter *adapter = rx_ring->adapter; 1709 struct e1000_buffer *buffer_info; 1710 struct e1000_ps_page *ps_page; 1711 struct pci_dev *pdev = adapter->pdev; 1712 unsigned int i, j; 1713 1714 /* Free all the Rx ring sk_buffs */ 1715 for (i = 0; i < rx_ring->count; i++) { 1716 buffer_info = &rx_ring->buffer_info[i]; 1717 if (buffer_info->dma) { 1718 if (adapter->clean_rx == e1000_clean_rx_irq) 1719 dma_unmap_single(&pdev->dev, buffer_info->dma, 1720 adapter->rx_buffer_len, 1721 DMA_FROM_DEVICE); 1722 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1723 dma_unmap_page(&pdev->dev, buffer_info->dma, 1724 PAGE_SIZE, DMA_FROM_DEVICE); 1725 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1726 dma_unmap_single(&pdev->dev, buffer_info->dma, 1727 adapter->rx_ps_bsize0, 1728 DMA_FROM_DEVICE); 1729 buffer_info->dma = 0; 1730 } 1731 1732 if (buffer_info->page) { 1733 put_page(buffer_info->page); 1734 buffer_info->page = NULL; 1735 } 1736 1737 if (buffer_info->skb) { 1738 dev_kfree_skb(buffer_info->skb); 1739 buffer_info->skb = NULL; 1740 } 1741 1742 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1743 ps_page = &buffer_info->ps_pages[j]; 1744 if (!ps_page->page) 1745 break; 1746 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1747 DMA_FROM_DEVICE); 1748 ps_page->dma = 0; 1749 put_page(ps_page->page); 1750 ps_page->page = NULL; 1751 } 1752 } 1753 1754 /* there also may be some cached data from a chained receive */ 1755 if (rx_ring->rx_skb_top) { 1756 dev_kfree_skb(rx_ring->rx_skb_top); 1757 rx_ring->rx_skb_top = NULL; 1758 } 1759 1760 /* Zero out the descriptor ring */ 1761 memset(rx_ring->desc, 0, rx_ring->size); 1762 1763 rx_ring->next_to_clean = 0; 1764 rx_ring->next_to_use = 0; 1765 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1766 } 1767 1768 static void e1000e_downshift_workaround(struct work_struct *work) 1769 { 1770 struct e1000_adapter *adapter = container_of(work, 1771 struct e1000_adapter, 1772 downshift_task); 1773 1774 if (test_bit(__E1000_DOWN, &adapter->state)) 1775 return; 1776 1777 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1778 } 1779 1780 /** 1781 * e1000_intr_msi - Interrupt Handler 1782 * @irq: interrupt number 1783 * @data: pointer to a network interface device structure 1784 **/ 1785 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1786 { 1787 struct net_device *netdev = data; 1788 struct e1000_adapter *adapter = netdev_priv(netdev); 1789 struct e1000_hw *hw = &adapter->hw; 1790 u32 icr = er32(ICR); 1791 1792 /* read ICR disables interrupts using IAM */ 1793 if (icr & E1000_ICR_LSC) { 1794 hw->mac.get_link_status = true; 1795 /* ICH8 workaround-- Call gig speed drop workaround on cable 1796 * disconnect (LSC) before accessing any PHY registers 1797 */ 1798 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1799 (!(er32(STATUS) & E1000_STATUS_LU))) 1800 schedule_work(&adapter->downshift_task); 1801 1802 /* 80003ES2LAN workaround-- For packet buffer work-around on 1803 * link down event; disable receives here in the ISR and reset 1804 * adapter in watchdog 1805 */ 1806 if (netif_carrier_ok(netdev) && 1807 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1808 /* disable receives */ 1809 u32 rctl = er32(RCTL); 1810 1811 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1812 adapter->flags |= FLAG_RESTART_NOW; 1813 } 1814 /* guard against interrupt when we're going down */ 1815 if (!test_bit(__E1000_DOWN, &adapter->state)) 1816 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1817 } 1818 1819 /* Reset on uncorrectable ECC error */ 1820 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1821 u32 pbeccsts = er32(PBECCSTS); 1822 1823 adapter->corr_errors += 1824 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1825 adapter->uncorr_errors += 1826 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1827 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1828 1829 /* Do the reset outside of interrupt context */ 1830 schedule_work(&adapter->reset_task); 1831 1832 /* return immediately since reset is imminent */ 1833 return IRQ_HANDLED; 1834 } 1835 1836 if (napi_schedule_prep(&adapter->napi)) { 1837 adapter->total_tx_bytes = 0; 1838 adapter->total_tx_packets = 0; 1839 adapter->total_rx_bytes = 0; 1840 adapter->total_rx_packets = 0; 1841 __napi_schedule(&adapter->napi); 1842 } 1843 1844 return IRQ_HANDLED; 1845 } 1846 1847 /** 1848 * e1000_intr - Interrupt Handler 1849 * @irq: interrupt number 1850 * @data: pointer to a network interface device structure 1851 **/ 1852 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1853 { 1854 struct net_device *netdev = data; 1855 struct e1000_adapter *adapter = netdev_priv(netdev); 1856 struct e1000_hw *hw = &adapter->hw; 1857 u32 rctl, icr = er32(ICR); 1858 1859 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1860 return IRQ_NONE; /* Not our interrupt */ 1861 1862 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1863 * not set, then the adapter didn't send an interrupt 1864 */ 1865 if (!(icr & E1000_ICR_INT_ASSERTED)) 1866 return IRQ_NONE; 1867 1868 /* Interrupt Auto-Mask...upon reading ICR, 1869 * interrupts are masked. No need for the 1870 * IMC write 1871 */ 1872 1873 if (icr & E1000_ICR_LSC) { 1874 hw->mac.get_link_status = true; 1875 /* ICH8 workaround-- Call gig speed drop workaround on cable 1876 * disconnect (LSC) before accessing any PHY registers 1877 */ 1878 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1879 (!(er32(STATUS) & E1000_STATUS_LU))) 1880 schedule_work(&adapter->downshift_task); 1881 1882 /* 80003ES2LAN workaround-- 1883 * For packet buffer work-around on link down event; 1884 * disable receives here in the ISR and 1885 * reset adapter in watchdog 1886 */ 1887 if (netif_carrier_ok(netdev) && 1888 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1889 /* disable receives */ 1890 rctl = er32(RCTL); 1891 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1892 adapter->flags |= FLAG_RESTART_NOW; 1893 } 1894 /* guard against interrupt when we're going down */ 1895 if (!test_bit(__E1000_DOWN, &adapter->state)) 1896 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1897 } 1898 1899 /* Reset on uncorrectable ECC error */ 1900 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1901 u32 pbeccsts = er32(PBECCSTS); 1902 1903 adapter->corr_errors += 1904 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1905 adapter->uncorr_errors += 1906 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1907 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1908 1909 /* Do the reset outside of interrupt context */ 1910 schedule_work(&adapter->reset_task); 1911 1912 /* return immediately since reset is imminent */ 1913 return IRQ_HANDLED; 1914 } 1915 1916 if (napi_schedule_prep(&adapter->napi)) { 1917 adapter->total_tx_bytes = 0; 1918 adapter->total_tx_packets = 0; 1919 adapter->total_rx_bytes = 0; 1920 adapter->total_rx_packets = 0; 1921 __napi_schedule(&adapter->napi); 1922 } 1923 1924 return IRQ_HANDLED; 1925 } 1926 1927 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1928 { 1929 struct net_device *netdev = data; 1930 struct e1000_adapter *adapter = netdev_priv(netdev); 1931 struct e1000_hw *hw = &adapter->hw; 1932 u32 icr = er32(ICR); 1933 1934 if (icr & adapter->eiac_mask) 1935 ew32(ICS, (icr & adapter->eiac_mask)); 1936 1937 if (icr & E1000_ICR_LSC) { 1938 hw->mac.get_link_status = true; 1939 /* guard against interrupt when we're going down */ 1940 if (!test_bit(__E1000_DOWN, &adapter->state)) 1941 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1942 } 1943 1944 if (!test_bit(__E1000_DOWN, &adapter->state)) 1945 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); 1946 1947 return IRQ_HANDLED; 1948 } 1949 1950 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1951 { 1952 struct net_device *netdev = data; 1953 struct e1000_adapter *adapter = netdev_priv(netdev); 1954 struct e1000_hw *hw = &adapter->hw; 1955 struct e1000_ring *tx_ring = adapter->tx_ring; 1956 1957 adapter->total_tx_bytes = 0; 1958 adapter->total_tx_packets = 0; 1959 1960 if (!e1000_clean_tx_irq(tx_ring)) 1961 /* Ring was not completely cleaned, so fire another interrupt */ 1962 ew32(ICS, tx_ring->ims_val); 1963 1964 if (!test_bit(__E1000_DOWN, &adapter->state)) 1965 ew32(IMS, adapter->tx_ring->ims_val); 1966 1967 return IRQ_HANDLED; 1968 } 1969 1970 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1971 { 1972 struct net_device *netdev = data; 1973 struct e1000_adapter *adapter = netdev_priv(netdev); 1974 struct e1000_ring *rx_ring = adapter->rx_ring; 1975 1976 /* Write the ITR value calculated at the end of the 1977 * previous interrupt. 1978 */ 1979 if (rx_ring->set_itr) { 1980 u32 itr = rx_ring->itr_val ? 1981 1000000000 / (rx_ring->itr_val * 256) : 0; 1982 1983 writel(itr, rx_ring->itr_register); 1984 rx_ring->set_itr = 0; 1985 } 1986 1987 if (napi_schedule_prep(&adapter->napi)) { 1988 adapter->total_rx_bytes = 0; 1989 adapter->total_rx_packets = 0; 1990 __napi_schedule(&adapter->napi); 1991 } 1992 return IRQ_HANDLED; 1993 } 1994 1995 /** 1996 * e1000_configure_msix - Configure MSI-X hardware 1997 * 1998 * e1000_configure_msix sets up the hardware to properly 1999 * generate MSI-X interrupts. 2000 **/ 2001 static void e1000_configure_msix(struct e1000_adapter *adapter) 2002 { 2003 struct e1000_hw *hw = &adapter->hw; 2004 struct e1000_ring *rx_ring = adapter->rx_ring; 2005 struct e1000_ring *tx_ring = adapter->tx_ring; 2006 int vector = 0; 2007 u32 ctrl_ext, ivar = 0; 2008 2009 adapter->eiac_mask = 0; 2010 2011 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 2012 if (hw->mac.type == e1000_82574) { 2013 u32 rfctl = er32(RFCTL); 2014 2015 rfctl |= E1000_RFCTL_ACK_DIS; 2016 ew32(RFCTL, rfctl); 2017 } 2018 2019 /* Configure Rx vector */ 2020 rx_ring->ims_val = E1000_IMS_RXQ0; 2021 adapter->eiac_mask |= rx_ring->ims_val; 2022 if (rx_ring->itr_val) 2023 writel(1000000000 / (rx_ring->itr_val * 256), 2024 rx_ring->itr_register); 2025 else 2026 writel(1, rx_ring->itr_register); 2027 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2028 2029 /* Configure Tx vector */ 2030 tx_ring->ims_val = E1000_IMS_TXQ0; 2031 vector++; 2032 if (tx_ring->itr_val) 2033 writel(1000000000 / (tx_ring->itr_val * 256), 2034 tx_ring->itr_register); 2035 else 2036 writel(1, tx_ring->itr_register); 2037 adapter->eiac_mask |= tx_ring->ims_val; 2038 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2039 2040 /* set vector for Other Causes, e.g. link changes */ 2041 vector++; 2042 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2043 if (rx_ring->itr_val) 2044 writel(1000000000 / (rx_ring->itr_val * 256), 2045 hw->hw_addr + E1000_EITR_82574(vector)); 2046 else 2047 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2048 2049 /* Cause Tx interrupts on every write back */ 2050 ivar |= BIT(31); 2051 2052 ew32(IVAR, ivar); 2053 2054 /* enable MSI-X PBA support */ 2055 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2056 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2057 ew32(CTRL_EXT, ctrl_ext); 2058 e1e_flush(); 2059 } 2060 2061 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2062 { 2063 if (adapter->msix_entries) { 2064 pci_disable_msix(adapter->pdev); 2065 kfree(adapter->msix_entries); 2066 adapter->msix_entries = NULL; 2067 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2068 pci_disable_msi(adapter->pdev); 2069 adapter->flags &= ~FLAG_MSI_ENABLED; 2070 } 2071 } 2072 2073 /** 2074 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2075 * 2076 * Attempt to configure interrupts using the best available 2077 * capabilities of the hardware and kernel. 2078 **/ 2079 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2080 { 2081 int err; 2082 int i; 2083 2084 switch (adapter->int_mode) { 2085 case E1000E_INT_MODE_MSIX: 2086 if (adapter->flags & FLAG_HAS_MSIX) { 2087 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2088 adapter->msix_entries = kcalloc(adapter->num_vectors, 2089 sizeof(struct 2090 msix_entry), 2091 GFP_KERNEL); 2092 if (adapter->msix_entries) { 2093 struct e1000_adapter *a = adapter; 2094 2095 for (i = 0; i < adapter->num_vectors; i++) 2096 adapter->msix_entries[i].entry = i; 2097 2098 err = pci_enable_msix_range(a->pdev, 2099 a->msix_entries, 2100 a->num_vectors, 2101 a->num_vectors); 2102 if (err > 0) 2103 return; 2104 } 2105 /* MSI-X failed, so fall through and try MSI */ 2106 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2107 e1000e_reset_interrupt_capability(adapter); 2108 } 2109 adapter->int_mode = E1000E_INT_MODE_MSI; 2110 fallthrough; 2111 case E1000E_INT_MODE_MSI: 2112 if (!pci_enable_msi(adapter->pdev)) { 2113 adapter->flags |= FLAG_MSI_ENABLED; 2114 } else { 2115 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2116 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2117 } 2118 fallthrough; 2119 case E1000E_INT_MODE_LEGACY: 2120 /* Don't do anything; this is the system default */ 2121 break; 2122 } 2123 2124 /* store the number of vectors being used */ 2125 adapter->num_vectors = 1; 2126 } 2127 2128 /** 2129 * e1000_request_msix - Initialize MSI-X interrupts 2130 * 2131 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2132 * kernel. 2133 **/ 2134 static int e1000_request_msix(struct e1000_adapter *adapter) 2135 { 2136 struct net_device *netdev = adapter->netdev; 2137 int err = 0, vector = 0; 2138 2139 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2140 snprintf(adapter->rx_ring->name, 2141 sizeof(adapter->rx_ring->name) - 1, 2142 "%.14s-rx-0", netdev->name); 2143 else 2144 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2145 err = request_irq(adapter->msix_entries[vector].vector, 2146 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2147 netdev); 2148 if (err) 2149 return err; 2150 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2151 E1000_EITR_82574(vector); 2152 adapter->rx_ring->itr_val = adapter->itr; 2153 vector++; 2154 2155 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2156 snprintf(adapter->tx_ring->name, 2157 sizeof(adapter->tx_ring->name) - 1, 2158 "%.14s-tx-0", netdev->name); 2159 else 2160 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2161 err = request_irq(adapter->msix_entries[vector].vector, 2162 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2163 netdev); 2164 if (err) 2165 return err; 2166 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2167 E1000_EITR_82574(vector); 2168 adapter->tx_ring->itr_val = adapter->itr; 2169 vector++; 2170 2171 err = request_irq(adapter->msix_entries[vector].vector, 2172 e1000_msix_other, 0, netdev->name, netdev); 2173 if (err) 2174 return err; 2175 2176 e1000_configure_msix(adapter); 2177 2178 return 0; 2179 } 2180 2181 /** 2182 * e1000_request_irq - initialize interrupts 2183 * 2184 * Attempts to configure interrupts using the best available 2185 * capabilities of the hardware and kernel. 2186 **/ 2187 static int e1000_request_irq(struct e1000_adapter *adapter) 2188 { 2189 struct net_device *netdev = adapter->netdev; 2190 int err; 2191 2192 if (adapter->msix_entries) { 2193 err = e1000_request_msix(adapter); 2194 if (!err) 2195 return err; 2196 /* fall back to MSI */ 2197 e1000e_reset_interrupt_capability(adapter); 2198 adapter->int_mode = E1000E_INT_MODE_MSI; 2199 e1000e_set_interrupt_capability(adapter); 2200 } 2201 if (adapter->flags & FLAG_MSI_ENABLED) { 2202 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2203 netdev->name, netdev); 2204 if (!err) 2205 return err; 2206 2207 /* fall back to legacy interrupt */ 2208 e1000e_reset_interrupt_capability(adapter); 2209 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2210 } 2211 2212 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2213 netdev->name, netdev); 2214 if (err) 2215 e_err("Unable to allocate interrupt, Error: %d\n", err); 2216 2217 return err; 2218 } 2219 2220 static void e1000_free_irq(struct e1000_adapter *adapter) 2221 { 2222 struct net_device *netdev = adapter->netdev; 2223 2224 if (adapter->msix_entries) { 2225 int vector = 0; 2226 2227 free_irq(adapter->msix_entries[vector].vector, netdev); 2228 vector++; 2229 2230 free_irq(adapter->msix_entries[vector].vector, netdev); 2231 vector++; 2232 2233 /* Other Causes interrupt vector */ 2234 free_irq(adapter->msix_entries[vector].vector, netdev); 2235 return; 2236 } 2237 2238 free_irq(adapter->pdev->irq, netdev); 2239 } 2240 2241 /** 2242 * e1000_irq_disable - Mask off interrupt generation on the NIC 2243 **/ 2244 static void e1000_irq_disable(struct e1000_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 2248 ew32(IMC, ~0); 2249 if (adapter->msix_entries) 2250 ew32(EIAC_82574, 0); 2251 e1e_flush(); 2252 2253 if (adapter->msix_entries) { 2254 int i; 2255 2256 for (i = 0; i < adapter->num_vectors; i++) 2257 synchronize_irq(adapter->msix_entries[i].vector); 2258 } else { 2259 synchronize_irq(adapter->pdev->irq); 2260 } 2261 } 2262 2263 /** 2264 * e1000_irq_enable - Enable default interrupt generation settings 2265 **/ 2266 static void e1000_irq_enable(struct e1000_adapter *adapter) 2267 { 2268 struct e1000_hw *hw = &adapter->hw; 2269 2270 if (adapter->msix_entries) { 2271 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2272 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | 2273 IMS_OTHER_MASK); 2274 } else if (hw->mac.type >= e1000_pch_lpt) { 2275 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2276 } else { 2277 ew32(IMS, IMS_ENABLE_MASK); 2278 } 2279 e1e_flush(); 2280 } 2281 2282 /** 2283 * e1000e_get_hw_control - get control of the h/w from f/w 2284 * @adapter: address of board private structure 2285 * 2286 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2287 * For ASF and Pass Through versions of f/w this means that 2288 * the driver is loaded. For AMT version (only with 82573) 2289 * of the f/w this means that the network i/f is open. 2290 **/ 2291 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2292 { 2293 struct e1000_hw *hw = &adapter->hw; 2294 u32 ctrl_ext; 2295 u32 swsm; 2296 2297 /* Let firmware know the driver has taken over */ 2298 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2299 swsm = er32(SWSM); 2300 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2301 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2302 ctrl_ext = er32(CTRL_EXT); 2303 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2304 } 2305 } 2306 2307 /** 2308 * e1000e_release_hw_control - release control of the h/w to f/w 2309 * @adapter: address of board private structure 2310 * 2311 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2312 * For ASF and Pass Through versions of f/w this means that the 2313 * driver is no longer loaded. For AMT version (only with 82573) i 2314 * of the f/w this means that the network i/f is closed. 2315 * 2316 **/ 2317 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2318 { 2319 struct e1000_hw *hw = &adapter->hw; 2320 u32 ctrl_ext; 2321 u32 swsm; 2322 2323 /* Let firmware taken over control of h/w */ 2324 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2325 swsm = er32(SWSM); 2326 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2327 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2328 ctrl_ext = er32(CTRL_EXT); 2329 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2330 } 2331 } 2332 2333 /** 2334 * e1000_alloc_ring_dma - allocate memory for a ring structure 2335 **/ 2336 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2337 struct e1000_ring *ring) 2338 { 2339 struct pci_dev *pdev = adapter->pdev; 2340 2341 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2342 GFP_KERNEL); 2343 if (!ring->desc) 2344 return -ENOMEM; 2345 2346 return 0; 2347 } 2348 2349 /** 2350 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2351 * @tx_ring: Tx descriptor ring 2352 * 2353 * Return 0 on success, negative on failure 2354 **/ 2355 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2356 { 2357 struct e1000_adapter *adapter = tx_ring->adapter; 2358 int err = -ENOMEM, size; 2359 2360 size = sizeof(struct e1000_buffer) * tx_ring->count; 2361 tx_ring->buffer_info = vzalloc(size); 2362 if (!tx_ring->buffer_info) 2363 goto err; 2364 2365 /* round up to nearest 4K */ 2366 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2367 tx_ring->size = ALIGN(tx_ring->size, 4096); 2368 2369 err = e1000_alloc_ring_dma(adapter, tx_ring); 2370 if (err) 2371 goto err; 2372 2373 tx_ring->next_to_use = 0; 2374 tx_ring->next_to_clean = 0; 2375 2376 return 0; 2377 err: 2378 vfree(tx_ring->buffer_info); 2379 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2380 return err; 2381 } 2382 2383 /** 2384 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2385 * @rx_ring: Rx descriptor ring 2386 * 2387 * Returns 0 on success, negative on failure 2388 **/ 2389 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2390 { 2391 struct e1000_adapter *adapter = rx_ring->adapter; 2392 struct e1000_buffer *buffer_info; 2393 int i, size, desc_len, err = -ENOMEM; 2394 2395 size = sizeof(struct e1000_buffer) * rx_ring->count; 2396 rx_ring->buffer_info = vzalloc(size); 2397 if (!rx_ring->buffer_info) 2398 goto err; 2399 2400 for (i = 0; i < rx_ring->count; i++) { 2401 buffer_info = &rx_ring->buffer_info[i]; 2402 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2403 sizeof(struct e1000_ps_page), 2404 GFP_KERNEL); 2405 if (!buffer_info->ps_pages) 2406 goto err_pages; 2407 } 2408 2409 desc_len = sizeof(union e1000_rx_desc_packet_split); 2410 2411 /* Round up to nearest 4K */ 2412 rx_ring->size = rx_ring->count * desc_len; 2413 rx_ring->size = ALIGN(rx_ring->size, 4096); 2414 2415 err = e1000_alloc_ring_dma(adapter, rx_ring); 2416 if (err) 2417 goto err_pages; 2418 2419 rx_ring->next_to_clean = 0; 2420 rx_ring->next_to_use = 0; 2421 rx_ring->rx_skb_top = NULL; 2422 2423 return 0; 2424 2425 err_pages: 2426 for (i = 0; i < rx_ring->count; i++) { 2427 buffer_info = &rx_ring->buffer_info[i]; 2428 kfree(buffer_info->ps_pages); 2429 } 2430 err: 2431 vfree(rx_ring->buffer_info); 2432 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2433 return err; 2434 } 2435 2436 /** 2437 * e1000_clean_tx_ring - Free Tx Buffers 2438 * @tx_ring: Tx descriptor ring 2439 **/ 2440 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2441 { 2442 struct e1000_adapter *adapter = tx_ring->adapter; 2443 struct e1000_buffer *buffer_info; 2444 unsigned long size; 2445 unsigned int i; 2446 2447 for (i = 0; i < tx_ring->count; i++) { 2448 buffer_info = &tx_ring->buffer_info[i]; 2449 e1000_put_txbuf(tx_ring, buffer_info, false); 2450 } 2451 2452 netdev_reset_queue(adapter->netdev); 2453 size = sizeof(struct e1000_buffer) * tx_ring->count; 2454 memset(tx_ring->buffer_info, 0, size); 2455 2456 memset(tx_ring->desc, 0, tx_ring->size); 2457 2458 tx_ring->next_to_use = 0; 2459 tx_ring->next_to_clean = 0; 2460 } 2461 2462 /** 2463 * e1000e_free_tx_resources - Free Tx Resources per Queue 2464 * @tx_ring: Tx descriptor ring 2465 * 2466 * Free all transmit software resources 2467 **/ 2468 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2469 { 2470 struct e1000_adapter *adapter = tx_ring->adapter; 2471 struct pci_dev *pdev = adapter->pdev; 2472 2473 e1000_clean_tx_ring(tx_ring); 2474 2475 vfree(tx_ring->buffer_info); 2476 tx_ring->buffer_info = NULL; 2477 2478 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2479 tx_ring->dma); 2480 tx_ring->desc = NULL; 2481 } 2482 2483 /** 2484 * e1000e_free_rx_resources - Free Rx Resources 2485 * @rx_ring: Rx descriptor ring 2486 * 2487 * Free all receive software resources 2488 **/ 2489 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2490 { 2491 struct e1000_adapter *adapter = rx_ring->adapter; 2492 struct pci_dev *pdev = adapter->pdev; 2493 int i; 2494 2495 e1000_clean_rx_ring(rx_ring); 2496 2497 for (i = 0; i < rx_ring->count; i++) 2498 kfree(rx_ring->buffer_info[i].ps_pages); 2499 2500 vfree(rx_ring->buffer_info); 2501 rx_ring->buffer_info = NULL; 2502 2503 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2504 rx_ring->dma); 2505 rx_ring->desc = NULL; 2506 } 2507 2508 /** 2509 * e1000_update_itr - update the dynamic ITR value based on statistics 2510 * @adapter: pointer to adapter 2511 * @itr_setting: current adapter->itr 2512 * @packets: the number of packets during this measurement interval 2513 * @bytes: the number of bytes during this measurement interval 2514 * 2515 * Stores a new ITR value based on packets and byte 2516 * counts during the last interrupt. The advantage of per interrupt 2517 * computation is faster updates and more accurate ITR for the current 2518 * traffic pattern. Constants in this function were computed 2519 * based on theoretical maximum wire speed and thresholds were set based 2520 * on testing data as well as attempting to minimize response time 2521 * while increasing bulk throughput. This functionality is controlled 2522 * by the InterruptThrottleRate module parameter. 2523 **/ 2524 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2525 { 2526 unsigned int retval = itr_setting; 2527 2528 if (packets == 0) 2529 return itr_setting; 2530 2531 switch (itr_setting) { 2532 case lowest_latency: 2533 /* handle TSO and jumbo frames */ 2534 if (bytes / packets > 8000) 2535 retval = bulk_latency; 2536 else if ((packets < 5) && (bytes > 512)) 2537 retval = low_latency; 2538 break; 2539 case low_latency: /* 50 usec aka 20000 ints/s */ 2540 if (bytes > 10000) { 2541 /* this if handles the TSO accounting */ 2542 if (bytes / packets > 8000) 2543 retval = bulk_latency; 2544 else if ((packets < 10) || ((bytes / packets) > 1200)) 2545 retval = bulk_latency; 2546 else if ((packets > 35)) 2547 retval = lowest_latency; 2548 } else if (bytes / packets > 2000) { 2549 retval = bulk_latency; 2550 } else if (packets <= 2 && bytes < 512) { 2551 retval = lowest_latency; 2552 } 2553 break; 2554 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2555 if (bytes > 25000) { 2556 if (packets > 35) 2557 retval = low_latency; 2558 } else if (bytes < 6000) { 2559 retval = low_latency; 2560 } 2561 break; 2562 } 2563 2564 return retval; 2565 } 2566 2567 static void e1000_set_itr(struct e1000_adapter *adapter) 2568 { 2569 u16 current_itr; 2570 u32 new_itr = adapter->itr; 2571 2572 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2573 if (adapter->link_speed != SPEED_1000) { 2574 current_itr = 0; 2575 new_itr = 4000; 2576 goto set_itr_now; 2577 } 2578 2579 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2580 new_itr = 0; 2581 goto set_itr_now; 2582 } 2583 2584 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2585 adapter->total_tx_packets, 2586 adapter->total_tx_bytes); 2587 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2588 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2589 adapter->tx_itr = low_latency; 2590 2591 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2592 adapter->total_rx_packets, 2593 adapter->total_rx_bytes); 2594 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2595 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2596 adapter->rx_itr = low_latency; 2597 2598 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2599 2600 /* counts and packets in update_itr are dependent on these numbers */ 2601 switch (current_itr) { 2602 case lowest_latency: 2603 new_itr = 70000; 2604 break; 2605 case low_latency: 2606 new_itr = 20000; /* aka hwitr = ~200 */ 2607 break; 2608 case bulk_latency: 2609 new_itr = 4000; 2610 break; 2611 default: 2612 break; 2613 } 2614 2615 set_itr_now: 2616 if (new_itr != adapter->itr) { 2617 /* this attempts to bias the interrupt rate towards Bulk 2618 * by adding intermediate steps when interrupt rate is 2619 * increasing 2620 */ 2621 new_itr = new_itr > adapter->itr ? 2622 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2623 adapter->itr = new_itr; 2624 adapter->rx_ring->itr_val = new_itr; 2625 if (adapter->msix_entries) 2626 adapter->rx_ring->set_itr = 1; 2627 else 2628 e1000e_write_itr(adapter, new_itr); 2629 } 2630 } 2631 2632 /** 2633 * e1000e_write_itr - write the ITR value to the appropriate registers 2634 * @adapter: address of board private structure 2635 * @itr: new ITR value to program 2636 * 2637 * e1000e_write_itr determines if the adapter is in MSI-X mode 2638 * and, if so, writes the EITR registers with the ITR value. 2639 * Otherwise, it writes the ITR value into the ITR register. 2640 **/ 2641 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2642 { 2643 struct e1000_hw *hw = &adapter->hw; 2644 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2645 2646 if (adapter->msix_entries) { 2647 int vector; 2648 2649 for (vector = 0; vector < adapter->num_vectors; vector++) 2650 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2651 } else { 2652 ew32(ITR, new_itr); 2653 } 2654 } 2655 2656 /** 2657 * e1000_alloc_queues - Allocate memory for all rings 2658 * @adapter: board private structure to initialize 2659 **/ 2660 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2661 { 2662 int size = sizeof(struct e1000_ring); 2663 2664 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2665 if (!adapter->tx_ring) 2666 goto err; 2667 adapter->tx_ring->count = adapter->tx_ring_count; 2668 adapter->tx_ring->adapter = adapter; 2669 2670 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2671 if (!adapter->rx_ring) 2672 goto err; 2673 adapter->rx_ring->count = adapter->rx_ring_count; 2674 adapter->rx_ring->adapter = adapter; 2675 2676 return 0; 2677 err: 2678 e_err("Unable to allocate memory for queues\n"); 2679 kfree(adapter->rx_ring); 2680 kfree(adapter->tx_ring); 2681 return -ENOMEM; 2682 } 2683 2684 /** 2685 * e1000e_poll - NAPI Rx polling callback 2686 * @napi: struct associated with this polling callback 2687 * @budget: number of packets driver is allowed to process this poll 2688 **/ 2689 static int e1000e_poll(struct napi_struct *napi, int budget) 2690 { 2691 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2692 napi); 2693 struct e1000_hw *hw = &adapter->hw; 2694 struct net_device *poll_dev = adapter->netdev; 2695 int tx_cleaned = 1, work_done = 0; 2696 2697 adapter = netdev_priv(poll_dev); 2698 2699 if (!adapter->msix_entries || 2700 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2701 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2702 2703 adapter->clean_rx(adapter->rx_ring, &work_done, budget); 2704 2705 if (!tx_cleaned || work_done == budget) 2706 return budget; 2707 2708 /* Exit the polling mode, but don't re-enable interrupts if stack might 2709 * poll us due to busy-polling 2710 */ 2711 if (likely(napi_complete_done(napi, work_done))) { 2712 if (adapter->itr_setting & 3) 2713 e1000_set_itr(adapter); 2714 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2715 if (adapter->msix_entries) 2716 ew32(IMS, adapter->rx_ring->ims_val); 2717 else 2718 e1000_irq_enable(adapter); 2719 } 2720 } 2721 2722 return work_done; 2723 } 2724 2725 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2726 __always_unused __be16 proto, u16 vid) 2727 { 2728 struct e1000_adapter *adapter = netdev_priv(netdev); 2729 struct e1000_hw *hw = &adapter->hw; 2730 u32 vfta, index; 2731 2732 /* don't update vlan cookie if already programmed */ 2733 if ((adapter->hw.mng_cookie.status & 2734 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2735 (vid == adapter->mng_vlan_id)) 2736 return 0; 2737 2738 /* add VID to filter table */ 2739 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2740 index = (vid >> 5) & 0x7F; 2741 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2742 vfta |= BIT((vid & 0x1F)); 2743 hw->mac.ops.write_vfta(hw, index, vfta); 2744 } 2745 2746 set_bit(vid, adapter->active_vlans); 2747 2748 return 0; 2749 } 2750 2751 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2752 __always_unused __be16 proto, u16 vid) 2753 { 2754 struct e1000_adapter *adapter = netdev_priv(netdev); 2755 struct e1000_hw *hw = &adapter->hw; 2756 u32 vfta, index; 2757 2758 if ((adapter->hw.mng_cookie.status & 2759 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2760 (vid == adapter->mng_vlan_id)) { 2761 /* release control to f/w */ 2762 e1000e_release_hw_control(adapter); 2763 return 0; 2764 } 2765 2766 /* remove VID from filter table */ 2767 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2768 index = (vid >> 5) & 0x7F; 2769 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2770 vfta &= ~BIT((vid & 0x1F)); 2771 hw->mac.ops.write_vfta(hw, index, vfta); 2772 } 2773 2774 clear_bit(vid, adapter->active_vlans); 2775 2776 return 0; 2777 } 2778 2779 /** 2780 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2781 * @adapter: board private structure to initialize 2782 **/ 2783 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2784 { 2785 struct net_device *netdev = adapter->netdev; 2786 struct e1000_hw *hw = &adapter->hw; 2787 u32 rctl; 2788 2789 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2790 /* disable VLAN receive filtering */ 2791 rctl = er32(RCTL); 2792 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2793 ew32(RCTL, rctl); 2794 2795 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2796 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2797 adapter->mng_vlan_id); 2798 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2799 } 2800 } 2801 } 2802 2803 /** 2804 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2805 * @adapter: board private structure to initialize 2806 **/ 2807 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2808 { 2809 struct e1000_hw *hw = &adapter->hw; 2810 u32 rctl; 2811 2812 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2813 /* enable VLAN receive filtering */ 2814 rctl = er32(RCTL); 2815 rctl |= E1000_RCTL_VFE; 2816 rctl &= ~E1000_RCTL_CFIEN; 2817 ew32(RCTL, rctl); 2818 } 2819 } 2820 2821 /** 2822 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2823 * @adapter: board private structure to initialize 2824 **/ 2825 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2826 { 2827 struct e1000_hw *hw = &adapter->hw; 2828 u32 ctrl; 2829 2830 /* disable VLAN tag insert/strip */ 2831 ctrl = er32(CTRL); 2832 ctrl &= ~E1000_CTRL_VME; 2833 ew32(CTRL, ctrl); 2834 } 2835 2836 /** 2837 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2838 * @adapter: board private structure to initialize 2839 **/ 2840 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2841 { 2842 struct e1000_hw *hw = &adapter->hw; 2843 u32 ctrl; 2844 2845 /* enable VLAN tag insert/strip */ 2846 ctrl = er32(CTRL); 2847 ctrl |= E1000_CTRL_VME; 2848 ew32(CTRL, ctrl); 2849 } 2850 2851 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2852 { 2853 struct net_device *netdev = adapter->netdev; 2854 u16 vid = adapter->hw.mng_cookie.vlan_id; 2855 u16 old_vid = adapter->mng_vlan_id; 2856 2857 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2858 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2859 adapter->mng_vlan_id = vid; 2860 } 2861 2862 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2863 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2864 } 2865 2866 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2867 { 2868 u16 vid; 2869 2870 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2871 2872 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2873 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2874 } 2875 2876 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2877 { 2878 struct e1000_hw *hw = &adapter->hw; 2879 u32 manc, manc2h, mdef, i, j; 2880 2881 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2882 return; 2883 2884 manc = er32(MANC); 2885 2886 /* enable receiving management packets to the host. this will probably 2887 * generate destination unreachable messages from the host OS, but 2888 * the packets will be handled on SMBUS 2889 */ 2890 manc |= E1000_MANC_EN_MNG2HOST; 2891 manc2h = er32(MANC2H); 2892 2893 switch (hw->mac.type) { 2894 default: 2895 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2896 break; 2897 case e1000_82574: 2898 case e1000_82583: 2899 /* Check if IPMI pass-through decision filter already exists; 2900 * if so, enable it. 2901 */ 2902 for (i = 0, j = 0; i < 8; i++) { 2903 mdef = er32(MDEF(i)); 2904 2905 /* Ignore filters with anything other than IPMI ports */ 2906 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2907 continue; 2908 2909 /* Enable this decision filter in MANC2H */ 2910 if (mdef) 2911 manc2h |= BIT(i); 2912 2913 j |= mdef; 2914 } 2915 2916 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2917 break; 2918 2919 /* Create new decision filter in an empty filter */ 2920 for (i = 0, j = 0; i < 8; i++) 2921 if (er32(MDEF(i)) == 0) { 2922 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2923 E1000_MDEF_PORT_664)); 2924 manc2h |= BIT(1); 2925 j++; 2926 break; 2927 } 2928 2929 if (!j) 2930 e_warn("Unable to create IPMI pass-through filter\n"); 2931 break; 2932 } 2933 2934 ew32(MANC2H, manc2h); 2935 ew32(MANC, manc); 2936 } 2937 2938 /** 2939 * e1000_configure_tx - Configure Transmit Unit after Reset 2940 * @adapter: board private structure 2941 * 2942 * Configure the Tx unit of the MAC after a reset. 2943 **/ 2944 static void e1000_configure_tx(struct e1000_adapter *adapter) 2945 { 2946 struct e1000_hw *hw = &adapter->hw; 2947 struct e1000_ring *tx_ring = adapter->tx_ring; 2948 u64 tdba; 2949 u32 tdlen, tctl, tarc; 2950 2951 /* Setup the HW Tx Head and Tail descriptor pointers */ 2952 tdba = tx_ring->dma; 2953 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2954 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2955 ew32(TDBAH(0), (tdba >> 32)); 2956 ew32(TDLEN(0), tdlen); 2957 ew32(TDH(0), 0); 2958 ew32(TDT(0), 0); 2959 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2960 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2961 2962 writel(0, tx_ring->head); 2963 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2964 e1000e_update_tdt_wa(tx_ring, 0); 2965 else 2966 writel(0, tx_ring->tail); 2967 2968 /* Set the Tx Interrupt Delay register */ 2969 ew32(TIDV, adapter->tx_int_delay); 2970 /* Tx irq moderation */ 2971 ew32(TADV, adapter->tx_abs_int_delay); 2972 2973 if (adapter->flags2 & FLAG2_DMA_BURST) { 2974 u32 txdctl = er32(TXDCTL(0)); 2975 2976 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2977 E1000_TXDCTL_WTHRESH); 2978 /* set up some performance related parameters to encourage the 2979 * hardware to use the bus more efficiently in bursts, depends 2980 * on the tx_int_delay to be enabled, 2981 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2982 * hthresh = 1 ==> prefetch when one or more available 2983 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2984 * BEWARE: this seems to work but should be considered first if 2985 * there are Tx hangs or other Tx related bugs 2986 */ 2987 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2988 ew32(TXDCTL(0), txdctl); 2989 } 2990 /* erratum work around: set txdctl the same for both queues */ 2991 ew32(TXDCTL(1), er32(TXDCTL(0))); 2992 2993 /* Program the Transmit Control Register */ 2994 tctl = er32(TCTL); 2995 tctl &= ~E1000_TCTL_CT; 2996 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2997 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2998 2999 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 3000 tarc = er32(TARC(0)); 3001 /* set the speed mode bit, we'll clear it if we're not at 3002 * gigabit link later 3003 */ 3004 #define SPEED_MODE_BIT BIT(21) 3005 tarc |= SPEED_MODE_BIT; 3006 ew32(TARC(0), tarc); 3007 } 3008 3009 /* errata: program both queues to unweighted RR */ 3010 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3011 tarc = er32(TARC(0)); 3012 tarc |= 1; 3013 ew32(TARC(0), tarc); 3014 tarc = er32(TARC(1)); 3015 tarc |= 1; 3016 ew32(TARC(1), tarc); 3017 } 3018 3019 /* Setup Transmit Descriptor Settings for eop descriptor */ 3020 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3021 3022 /* only set IDE if we are delaying interrupts using the timers */ 3023 if (adapter->tx_int_delay) 3024 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3025 3026 /* enable Report Status bit */ 3027 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3028 3029 ew32(TCTL, tctl); 3030 3031 hw->mac.ops.config_collision_dist(hw); 3032 3033 /* SPT and KBL Si errata workaround to avoid data corruption */ 3034 if (hw->mac.type == e1000_pch_spt) { 3035 u32 reg_val; 3036 3037 reg_val = er32(IOSFPC); 3038 reg_val |= E1000_RCTL_RDMTS_HEX; 3039 ew32(IOSFPC, reg_val); 3040 3041 reg_val = er32(TARC(0)); 3042 /* SPT and KBL Si errata workaround to avoid Tx hang. 3043 * Dropping the number of outstanding requests from 3044 * 3 to 2 in order to avoid a buffer overrun. 3045 */ 3046 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3047 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3048 ew32(TARC(0), reg_val); 3049 } 3050 } 3051 3052 /** 3053 * e1000_setup_rctl - configure the receive control registers 3054 * @adapter: Board private structure 3055 **/ 3056 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3057 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3058 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3059 { 3060 struct e1000_hw *hw = &adapter->hw; 3061 u32 rctl, rfctl; 3062 u32 pages = 0; 3063 3064 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3065 * If jumbo frames not set, program related MAC/PHY registers 3066 * to h/w defaults 3067 */ 3068 if (hw->mac.type >= e1000_pch2lan) { 3069 s32 ret_val; 3070 3071 if (adapter->netdev->mtu > ETH_DATA_LEN) 3072 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3073 else 3074 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3075 3076 if (ret_val) 3077 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3078 } 3079 3080 /* Program MC offset vector base */ 3081 rctl = er32(RCTL); 3082 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3083 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3084 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3085 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3086 3087 /* Do not Store bad packets */ 3088 rctl &= ~E1000_RCTL_SBP; 3089 3090 /* Enable Long Packet receive */ 3091 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3092 rctl &= ~E1000_RCTL_LPE; 3093 else 3094 rctl |= E1000_RCTL_LPE; 3095 3096 /* Some systems expect that the CRC is included in SMBUS traffic. The 3097 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3098 * host memory when this is enabled 3099 */ 3100 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3101 rctl |= E1000_RCTL_SECRC; 3102 3103 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3104 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3105 u16 phy_data; 3106 3107 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3108 phy_data &= 0xfff8; 3109 phy_data |= BIT(2); 3110 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3111 3112 e1e_rphy(hw, 22, &phy_data); 3113 phy_data &= 0x0fff; 3114 phy_data |= BIT(14); 3115 e1e_wphy(hw, 0x10, 0x2823); 3116 e1e_wphy(hw, 0x11, 0x0003); 3117 e1e_wphy(hw, 22, phy_data); 3118 } 3119 3120 /* Setup buffer sizes */ 3121 rctl &= ~E1000_RCTL_SZ_4096; 3122 rctl |= E1000_RCTL_BSEX; 3123 switch (adapter->rx_buffer_len) { 3124 case 2048: 3125 default: 3126 rctl |= E1000_RCTL_SZ_2048; 3127 rctl &= ~E1000_RCTL_BSEX; 3128 break; 3129 case 4096: 3130 rctl |= E1000_RCTL_SZ_4096; 3131 break; 3132 case 8192: 3133 rctl |= E1000_RCTL_SZ_8192; 3134 break; 3135 case 16384: 3136 rctl |= E1000_RCTL_SZ_16384; 3137 break; 3138 } 3139 3140 /* Enable Extended Status in all Receive Descriptors */ 3141 rfctl = er32(RFCTL); 3142 rfctl |= E1000_RFCTL_EXTEN; 3143 ew32(RFCTL, rfctl); 3144 3145 /* 82571 and greater support packet-split where the protocol 3146 * header is placed in skb->data and the packet data is 3147 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3148 * In the case of a non-split, skb->data is linearly filled, 3149 * followed by the page buffers. Therefore, skb->data is 3150 * sized to hold the largest protocol header. 3151 * 3152 * allocations using alloc_page take too long for regular MTU 3153 * so only enable packet split for jumbo frames 3154 * 3155 * Using pages when the page size is greater than 16k wastes 3156 * a lot of memory, since we allocate 3 pages at all times 3157 * per packet. 3158 */ 3159 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3160 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3161 adapter->rx_ps_pages = pages; 3162 else 3163 adapter->rx_ps_pages = 0; 3164 3165 if (adapter->rx_ps_pages) { 3166 u32 psrctl = 0; 3167 3168 /* Enable Packet split descriptors */ 3169 rctl |= E1000_RCTL_DTYP_PS; 3170 3171 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3172 3173 switch (adapter->rx_ps_pages) { 3174 case 3: 3175 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3176 fallthrough; 3177 case 2: 3178 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3179 fallthrough; 3180 case 1: 3181 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3182 break; 3183 } 3184 3185 ew32(PSRCTL, psrctl); 3186 } 3187 3188 /* This is useful for sniffing bad packets. */ 3189 if (adapter->netdev->features & NETIF_F_RXALL) { 3190 /* UPE and MPE will be handled by normal PROMISC logic 3191 * in e1000e_set_rx_mode 3192 */ 3193 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3194 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3195 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3196 3197 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3198 E1000_RCTL_DPF | /* Allow filtered pause */ 3199 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3200 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3201 * and that breaks VLANs. 3202 */ 3203 } 3204 3205 ew32(RCTL, rctl); 3206 /* just started the receive unit, no need to restart */ 3207 adapter->flags &= ~FLAG_RESTART_NOW; 3208 } 3209 3210 /** 3211 * e1000_configure_rx - Configure Receive Unit after Reset 3212 * @adapter: board private structure 3213 * 3214 * Configure the Rx unit of the MAC after a reset. 3215 **/ 3216 static void e1000_configure_rx(struct e1000_adapter *adapter) 3217 { 3218 struct e1000_hw *hw = &adapter->hw; 3219 struct e1000_ring *rx_ring = adapter->rx_ring; 3220 u64 rdba; 3221 u32 rdlen, rctl, rxcsum, ctrl_ext; 3222 3223 if (adapter->rx_ps_pages) { 3224 /* this is a 32 byte descriptor */ 3225 rdlen = rx_ring->count * 3226 sizeof(union e1000_rx_desc_packet_split); 3227 adapter->clean_rx = e1000_clean_rx_irq_ps; 3228 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3229 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3230 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3231 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3232 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3233 } else { 3234 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3235 adapter->clean_rx = e1000_clean_rx_irq; 3236 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3237 } 3238 3239 /* disable receives while setting up the descriptors */ 3240 rctl = er32(RCTL); 3241 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3242 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3243 e1e_flush(); 3244 usleep_range(10000, 11000); 3245 3246 if (adapter->flags2 & FLAG2_DMA_BURST) { 3247 /* set the writeback threshold (only takes effect if the RDTR 3248 * is set). set GRAN=1 and write back up to 0x4 worth, and 3249 * enable prefetching of 0x20 Rx descriptors 3250 * granularity = 01 3251 * wthresh = 04, 3252 * hthresh = 04, 3253 * pthresh = 0x20 3254 */ 3255 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3256 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3257 } 3258 3259 /* set the Receive Delay Timer Register */ 3260 ew32(RDTR, adapter->rx_int_delay); 3261 3262 /* irq moderation */ 3263 ew32(RADV, adapter->rx_abs_int_delay); 3264 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3265 e1000e_write_itr(adapter, adapter->itr); 3266 3267 ctrl_ext = er32(CTRL_EXT); 3268 /* Auto-Mask interrupts upon ICR access */ 3269 ctrl_ext |= E1000_CTRL_EXT_IAME; 3270 ew32(IAM, 0xffffffff); 3271 ew32(CTRL_EXT, ctrl_ext); 3272 e1e_flush(); 3273 3274 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3275 * the Base and Length of the Rx Descriptor Ring 3276 */ 3277 rdba = rx_ring->dma; 3278 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3279 ew32(RDBAH(0), (rdba >> 32)); 3280 ew32(RDLEN(0), rdlen); 3281 ew32(RDH(0), 0); 3282 ew32(RDT(0), 0); 3283 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3284 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3285 3286 writel(0, rx_ring->head); 3287 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3288 e1000e_update_rdt_wa(rx_ring, 0); 3289 else 3290 writel(0, rx_ring->tail); 3291 3292 /* Enable Receive Checksum Offload for TCP and UDP */ 3293 rxcsum = er32(RXCSUM); 3294 if (adapter->netdev->features & NETIF_F_RXCSUM) 3295 rxcsum |= E1000_RXCSUM_TUOFL; 3296 else 3297 rxcsum &= ~E1000_RXCSUM_TUOFL; 3298 ew32(RXCSUM, rxcsum); 3299 3300 /* With jumbo frames, excessive C-state transition latencies result 3301 * in dropped transactions. 3302 */ 3303 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3304 u32 lat = 3305 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3306 adapter->max_frame_size) * 8 / 1000; 3307 3308 if (adapter->flags & FLAG_IS_ICH) { 3309 u32 rxdctl = er32(RXDCTL(0)); 3310 3311 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3312 } 3313 3314 dev_info(&adapter->pdev->dev, 3315 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3316 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat); 3317 } else { 3318 cpu_latency_qos_update_request(&adapter->pm_qos_req, 3319 PM_QOS_DEFAULT_VALUE); 3320 } 3321 3322 /* Enable Receives */ 3323 ew32(RCTL, rctl); 3324 } 3325 3326 /** 3327 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3328 * @netdev: network interface device structure 3329 * 3330 * Writes multicast address list to the MTA hash table. 3331 * Returns: -ENOMEM on failure 3332 * 0 on no addresses written 3333 * X on writing X addresses to MTA 3334 */ 3335 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3336 { 3337 struct e1000_adapter *adapter = netdev_priv(netdev); 3338 struct e1000_hw *hw = &adapter->hw; 3339 struct netdev_hw_addr *ha; 3340 u8 *mta_list; 3341 int i; 3342 3343 if (netdev_mc_empty(netdev)) { 3344 /* nothing to program, so clear mc list */ 3345 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3346 return 0; 3347 } 3348 3349 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); 3350 if (!mta_list) 3351 return -ENOMEM; 3352 3353 /* update_mc_addr_list expects a packed array of only addresses. */ 3354 i = 0; 3355 netdev_for_each_mc_addr(ha, netdev) 3356 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3357 3358 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3359 kfree(mta_list); 3360 3361 return netdev_mc_count(netdev); 3362 } 3363 3364 /** 3365 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3366 * @netdev: network interface device structure 3367 * 3368 * Writes unicast address list to the RAR table. 3369 * Returns: -ENOMEM on failure/insufficient address space 3370 * 0 on no addresses written 3371 * X on writing X addresses to the RAR table 3372 **/ 3373 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3374 { 3375 struct e1000_adapter *adapter = netdev_priv(netdev); 3376 struct e1000_hw *hw = &adapter->hw; 3377 unsigned int rar_entries; 3378 int count = 0; 3379 3380 rar_entries = hw->mac.ops.rar_get_count(hw); 3381 3382 /* save a rar entry for our hardware address */ 3383 rar_entries--; 3384 3385 /* save a rar entry for the LAA workaround */ 3386 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3387 rar_entries--; 3388 3389 /* return ENOMEM indicating insufficient memory for addresses */ 3390 if (netdev_uc_count(netdev) > rar_entries) 3391 return -ENOMEM; 3392 3393 if (!netdev_uc_empty(netdev) && rar_entries) { 3394 struct netdev_hw_addr *ha; 3395 3396 /* write the addresses in reverse order to avoid write 3397 * combining 3398 */ 3399 netdev_for_each_uc_addr(ha, netdev) { 3400 int ret_val; 3401 3402 if (!rar_entries) 3403 break; 3404 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3405 if (ret_val < 0) 3406 return -ENOMEM; 3407 count++; 3408 } 3409 } 3410 3411 /* zero out the remaining RAR entries not used above */ 3412 for (; rar_entries > 0; rar_entries--) { 3413 ew32(RAH(rar_entries), 0); 3414 ew32(RAL(rar_entries), 0); 3415 } 3416 e1e_flush(); 3417 3418 return count; 3419 } 3420 3421 /** 3422 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3423 * @netdev: network interface device structure 3424 * 3425 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3426 * address list or the network interface flags are updated. This routine is 3427 * responsible for configuring the hardware for proper unicast, multicast, 3428 * promiscuous mode, and all-multi behavior. 3429 **/ 3430 static void e1000e_set_rx_mode(struct net_device *netdev) 3431 { 3432 struct e1000_adapter *adapter = netdev_priv(netdev); 3433 struct e1000_hw *hw = &adapter->hw; 3434 u32 rctl; 3435 3436 if (pm_runtime_suspended(netdev->dev.parent)) 3437 return; 3438 3439 /* Check for Promiscuous and All Multicast modes */ 3440 rctl = er32(RCTL); 3441 3442 /* clear the affected bits */ 3443 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3444 3445 if (netdev->flags & IFF_PROMISC) { 3446 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3447 /* Do not hardware filter VLANs in promisc mode */ 3448 e1000e_vlan_filter_disable(adapter); 3449 } else { 3450 int count; 3451 3452 if (netdev->flags & IFF_ALLMULTI) { 3453 rctl |= E1000_RCTL_MPE; 3454 } else { 3455 /* Write addresses to the MTA, if the attempt fails 3456 * then we should just turn on promiscuous mode so 3457 * that we can at least receive multicast traffic 3458 */ 3459 count = e1000e_write_mc_addr_list(netdev); 3460 if (count < 0) 3461 rctl |= E1000_RCTL_MPE; 3462 } 3463 e1000e_vlan_filter_enable(adapter); 3464 /* Write addresses to available RAR registers, if there is not 3465 * sufficient space to store all the addresses then enable 3466 * unicast promiscuous mode 3467 */ 3468 count = e1000e_write_uc_addr_list(netdev); 3469 if (count < 0) 3470 rctl |= E1000_RCTL_UPE; 3471 } 3472 3473 ew32(RCTL, rctl); 3474 3475 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3476 e1000e_vlan_strip_enable(adapter); 3477 else 3478 e1000e_vlan_strip_disable(adapter); 3479 } 3480 3481 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3482 { 3483 struct e1000_hw *hw = &adapter->hw; 3484 u32 mrqc, rxcsum; 3485 u32 rss_key[10]; 3486 int i; 3487 3488 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3489 for (i = 0; i < 10; i++) 3490 ew32(RSSRK(i), rss_key[i]); 3491 3492 /* Direct all traffic to queue 0 */ 3493 for (i = 0; i < 32; i++) 3494 ew32(RETA(i), 0); 3495 3496 /* Disable raw packet checksumming so that RSS hash is placed in 3497 * descriptor on writeback. 3498 */ 3499 rxcsum = er32(RXCSUM); 3500 rxcsum |= E1000_RXCSUM_PCSD; 3501 3502 ew32(RXCSUM, rxcsum); 3503 3504 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3505 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3506 E1000_MRQC_RSS_FIELD_IPV6 | 3507 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3508 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3509 3510 ew32(MRQC, mrqc); 3511 } 3512 3513 /** 3514 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3515 * @adapter: board private structure 3516 * @timinca: pointer to returned time increment attributes 3517 * 3518 * Get attributes for incrementing the System Time Register SYSTIML/H at 3519 * the default base frequency, and set the cyclecounter shift value. 3520 **/ 3521 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3522 { 3523 struct e1000_hw *hw = &adapter->hw; 3524 u32 incvalue, incperiod, shift; 3525 3526 /* Make sure clock is enabled on I217/I218/I219 before checking 3527 * the frequency 3528 */ 3529 if ((hw->mac.type >= e1000_pch_lpt) && 3530 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3531 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3532 u32 fextnvm7 = er32(FEXTNVM7); 3533 3534 if (!(fextnvm7 & BIT(0))) { 3535 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3536 e1e_flush(); 3537 } 3538 } 3539 3540 switch (hw->mac.type) { 3541 case e1000_pch2lan: 3542 /* Stable 96MHz frequency */ 3543 incperiod = INCPERIOD_96MHZ; 3544 incvalue = INCVALUE_96MHZ; 3545 shift = INCVALUE_SHIFT_96MHZ; 3546 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3547 break; 3548 case e1000_pch_lpt: 3549 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3550 /* Stable 96MHz frequency */ 3551 incperiod = INCPERIOD_96MHZ; 3552 incvalue = INCVALUE_96MHZ; 3553 shift = INCVALUE_SHIFT_96MHZ; 3554 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3555 } else { 3556 /* Stable 25MHz frequency */ 3557 incperiod = INCPERIOD_25MHZ; 3558 incvalue = INCVALUE_25MHZ; 3559 shift = INCVALUE_SHIFT_25MHZ; 3560 adapter->cc.shift = shift; 3561 } 3562 break; 3563 case e1000_pch_spt: 3564 /* Stable 24MHz frequency */ 3565 incperiod = INCPERIOD_24MHZ; 3566 incvalue = INCVALUE_24MHZ; 3567 shift = INCVALUE_SHIFT_24MHZ; 3568 adapter->cc.shift = shift; 3569 break; 3570 case e1000_pch_cnp: 3571 case e1000_pch_tgp: 3572 case e1000_pch_adp: 3573 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3574 /* Stable 24MHz frequency */ 3575 incperiod = INCPERIOD_24MHZ; 3576 incvalue = INCVALUE_24MHZ; 3577 shift = INCVALUE_SHIFT_24MHZ; 3578 adapter->cc.shift = shift; 3579 } else { 3580 /* Stable 38400KHz frequency */ 3581 incperiod = INCPERIOD_38400KHZ; 3582 incvalue = INCVALUE_38400KHZ; 3583 shift = INCVALUE_SHIFT_38400KHZ; 3584 adapter->cc.shift = shift; 3585 } 3586 break; 3587 case e1000_82574: 3588 case e1000_82583: 3589 /* Stable 25MHz frequency */ 3590 incperiod = INCPERIOD_25MHZ; 3591 incvalue = INCVALUE_25MHZ; 3592 shift = INCVALUE_SHIFT_25MHZ; 3593 adapter->cc.shift = shift; 3594 break; 3595 default: 3596 return -EINVAL; 3597 } 3598 3599 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3600 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3601 3602 return 0; 3603 } 3604 3605 /** 3606 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3607 * @adapter: board private structure 3608 * 3609 * Outgoing time stamping can be enabled and disabled. Play nice and 3610 * disable it when requested, although it shouldn't cause any overhead 3611 * when no packet needs it. At most one packet in the queue may be 3612 * marked for time stamping, otherwise it would be impossible to tell 3613 * for sure to which packet the hardware time stamp belongs. 3614 * 3615 * Incoming time stamping has to be configured via the hardware filters. 3616 * Not all combinations are supported, in particular event type has to be 3617 * specified. Matching the kind of event packet is not supported, with the 3618 * exception of "all V2 events regardless of level 2 or 4". 3619 **/ 3620 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3621 struct hwtstamp_config *config) 3622 { 3623 struct e1000_hw *hw = &adapter->hw; 3624 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3625 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3626 u32 rxmtrl = 0; 3627 u16 rxudp = 0; 3628 bool is_l4 = false; 3629 bool is_l2 = false; 3630 u32 regval; 3631 3632 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3633 return -EINVAL; 3634 3635 /* flags reserved for future extensions - must be zero */ 3636 if (config->flags) 3637 return -EINVAL; 3638 3639 switch (config->tx_type) { 3640 case HWTSTAMP_TX_OFF: 3641 tsync_tx_ctl = 0; 3642 break; 3643 case HWTSTAMP_TX_ON: 3644 break; 3645 default: 3646 return -ERANGE; 3647 } 3648 3649 switch (config->rx_filter) { 3650 case HWTSTAMP_FILTER_NONE: 3651 tsync_rx_ctl = 0; 3652 break; 3653 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3654 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3655 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3656 is_l4 = true; 3657 break; 3658 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3659 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3660 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3661 is_l4 = true; 3662 break; 3663 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3664 /* Also time stamps V2 L2 Path Delay Request/Response */ 3665 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3666 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3667 is_l2 = true; 3668 break; 3669 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3670 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3671 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3672 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3673 is_l2 = true; 3674 break; 3675 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3676 /* Hardware cannot filter just V2 L4 Sync messages */ 3677 fallthrough; 3678 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3679 /* Also time stamps V2 Path Delay Request/Response. */ 3680 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3681 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3682 is_l2 = true; 3683 is_l4 = true; 3684 break; 3685 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3686 /* Hardware cannot filter just V2 L4 Delay Request messages */ 3687 fallthrough; 3688 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3689 /* Also time stamps V2 Path Delay Request/Response. */ 3690 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3691 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3692 is_l2 = true; 3693 is_l4 = true; 3694 break; 3695 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3696 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3697 /* Hardware cannot filter just V2 L4 or L2 Event messages */ 3698 fallthrough; 3699 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3700 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3701 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3702 is_l2 = true; 3703 is_l4 = true; 3704 break; 3705 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3706 /* For V1, the hardware can only filter Sync messages or 3707 * Delay Request messages but not both so fall-through to 3708 * time stamp all packets. 3709 */ 3710 fallthrough; 3711 case HWTSTAMP_FILTER_NTP_ALL: 3712 case HWTSTAMP_FILTER_ALL: 3713 is_l2 = true; 3714 is_l4 = true; 3715 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3716 config->rx_filter = HWTSTAMP_FILTER_ALL; 3717 break; 3718 default: 3719 return -ERANGE; 3720 } 3721 3722 adapter->hwtstamp_config = *config; 3723 3724 /* enable/disable Tx h/w time stamping */ 3725 regval = er32(TSYNCTXCTL); 3726 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3727 regval |= tsync_tx_ctl; 3728 ew32(TSYNCTXCTL, regval); 3729 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3730 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3731 e_err("Timesync Tx Control register not set as expected\n"); 3732 return -EAGAIN; 3733 } 3734 3735 /* enable/disable Rx h/w time stamping */ 3736 regval = er32(TSYNCRXCTL); 3737 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3738 regval |= tsync_rx_ctl; 3739 ew32(TSYNCRXCTL, regval); 3740 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3741 E1000_TSYNCRXCTL_TYPE_MASK)) != 3742 (regval & (E1000_TSYNCRXCTL_ENABLED | 3743 E1000_TSYNCRXCTL_TYPE_MASK))) { 3744 e_err("Timesync Rx Control register not set as expected\n"); 3745 return -EAGAIN; 3746 } 3747 3748 /* L2: define ethertype filter for time stamped packets */ 3749 if (is_l2) 3750 rxmtrl |= ETH_P_1588; 3751 3752 /* define which PTP packets get time stamped */ 3753 ew32(RXMTRL, rxmtrl); 3754 3755 /* Filter by destination port */ 3756 if (is_l4) { 3757 rxudp = PTP_EV_PORT; 3758 cpu_to_be16s(&rxudp); 3759 } 3760 ew32(RXUDP, rxudp); 3761 3762 e1e_flush(); 3763 3764 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3765 er32(RXSTMPH); 3766 er32(TXSTMPH); 3767 3768 return 0; 3769 } 3770 3771 /** 3772 * e1000_configure - configure the hardware for Rx and Tx 3773 * @adapter: private board structure 3774 **/ 3775 static void e1000_configure(struct e1000_adapter *adapter) 3776 { 3777 struct e1000_ring *rx_ring = adapter->rx_ring; 3778 3779 e1000e_set_rx_mode(adapter->netdev); 3780 3781 e1000_restore_vlan(adapter); 3782 e1000_init_manageability_pt(adapter); 3783 3784 e1000_configure_tx(adapter); 3785 3786 if (adapter->netdev->features & NETIF_F_RXHASH) 3787 e1000e_setup_rss_hash(adapter); 3788 e1000_setup_rctl(adapter); 3789 e1000_configure_rx(adapter); 3790 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3791 } 3792 3793 /** 3794 * e1000e_power_up_phy - restore link in case the phy was powered down 3795 * @adapter: address of board private structure 3796 * 3797 * The phy may be powered down to save power and turn off link when the 3798 * driver is unloaded and wake on lan is not enabled (among others) 3799 * *** this routine MUST be followed by a call to e1000e_reset *** 3800 **/ 3801 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3802 { 3803 if (adapter->hw.phy.ops.power_up) 3804 adapter->hw.phy.ops.power_up(&adapter->hw); 3805 3806 adapter->hw.mac.ops.setup_link(&adapter->hw); 3807 } 3808 3809 /** 3810 * e1000_power_down_phy - Power down the PHY 3811 * 3812 * Power down the PHY so no link is implied when interface is down. 3813 * The PHY cannot be powered down if management or WoL is active. 3814 */ 3815 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3816 { 3817 if (adapter->hw.phy.ops.power_down) 3818 adapter->hw.phy.ops.power_down(&adapter->hw); 3819 } 3820 3821 /** 3822 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3823 * 3824 * We want to clear all pending descriptors from the TX ring. 3825 * zeroing happens when the HW reads the regs. We assign the ring itself as 3826 * the data of the next descriptor. We don't care about the data we are about 3827 * to reset the HW. 3828 */ 3829 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3830 { 3831 struct e1000_hw *hw = &adapter->hw; 3832 struct e1000_ring *tx_ring = adapter->tx_ring; 3833 struct e1000_tx_desc *tx_desc = NULL; 3834 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3835 u16 size = 512; 3836 3837 tctl = er32(TCTL); 3838 ew32(TCTL, tctl | E1000_TCTL_EN); 3839 tdt = er32(TDT(0)); 3840 BUG_ON(tdt != tx_ring->next_to_use); 3841 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3842 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma); 3843 3844 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3845 tx_desc->upper.data = 0; 3846 /* flush descriptors to memory before notifying the HW */ 3847 wmb(); 3848 tx_ring->next_to_use++; 3849 if (tx_ring->next_to_use == tx_ring->count) 3850 tx_ring->next_to_use = 0; 3851 ew32(TDT(0), tx_ring->next_to_use); 3852 usleep_range(200, 250); 3853 } 3854 3855 /** 3856 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3857 * 3858 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3859 */ 3860 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3861 { 3862 u32 rctl, rxdctl; 3863 struct e1000_hw *hw = &adapter->hw; 3864 3865 rctl = er32(RCTL); 3866 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3867 e1e_flush(); 3868 usleep_range(100, 150); 3869 3870 rxdctl = er32(RXDCTL(0)); 3871 /* zero the lower 14 bits (prefetch and host thresholds) */ 3872 rxdctl &= 0xffffc000; 3873 3874 /* update thresholds: prefetch threshold to 31, host threshold to 1 3875 * and make sure the granularity is "descriptors" and not "cache lines" 3876 */ 3877 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3878 3879 ew32(RXDCTL(0), rxdctl); 3880 /* momentarily enable the RX ring for the changes to take effect */ 3881 ew32(RCTL, rctl | E1000_RCTL_EN); 3882 e1e_flush(); 3883 usleep_range(100, 150); 3884 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3885 } 3886 3887 /** 3888 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3889 * 3890 * In i219, the descriptor rings must be emptied before resetting the HW 3891 * or before changing the device state to D3 during runtime (runtime PM). 3892 * 3893 * Failure to do this will cause the HW to enter a unit hang state which can 3894 * only be released by PCI reset on the device 3895 * 3896 */ 3897 3898 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3899 { 3900 u16 hang_state; 3901 u32 fext_nvm11, tdlen; 3902 struct e1000_hw *hw = &adapter->hw; 3903 3904 /* First, disable MULR fix in FEXTNVM11 */ 3905 fext_nvm11 = er32(FEXTNVM11); 3906 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3907 ew32(FEXTNVM11, fext_nvm11); 3908 /* do nothing if we're not in faulty state, or if the queue is empty */ 3909 tdlen = er32(TDLEN(0)); 3910 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3911 &hang_state); 3912 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3913 return; 3914 e1000_flush_tx_ring(adapter); 3915 /* recheck, maybe the fault is caused by the rx ring */ 3916 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3917 &hang_state); 3918 if (hang_state & FLUSH_DESC_REQUIRED) 3919 e1000_flush_rx_ring(adapter); 3920 } 3921 3922 /** 3923 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3924 * @adapter: board private structure 3925 * 3926 * When the MAC is reset, all hardware bits for timesync will be reset to the 3927 * default values. This function will restore the settings last in place. 3928 * Since the clock SYSTIME registers are reset, we will simply restore the 3929 * cyclecounter to the kernel real clock time. 3930 **/ 3931 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3932 { 3933 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3934 struct e1000_hw *hw = &adapter->hw; 3935 unsigned long flags; 3936 u32 timinca; 3937 s32 ret_val; 3938 3939 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3940 return; 3941 3942 if (info->adjfreq) { 3943 /* restore the previous ptp frequency delta */ 3944 ret_val = info->adjfreq(info, adapter->ptp_delta); 3945 } else { 3946 /* set the default base frequency if no adjustment possible */ 3947 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3948 if (!ret_val) 3949 ew32(TIMINCA, timinca); 3950 } 3951 3952 if (ret_val) { 3953 dev_warn(&adapter->pdev->dev, 3954 "Failed to restore TIMINCA clock rate delta: %d\n", 3955 ret_val); 3956 return; 3957 } 3958 3959 /* reset the systim ns time counter */ 3960 spin_lock_irqsave(&adapter->systim_lock, flags); 3961 timecounter_init(&adapter->tc, &adapter->cc, 3962 ktime_to_ns(ktime_get_real())); 3963 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3964 3965 /* restore the previous hwtstamp configuration settings */ 3966 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3967 } 3968 3969 /** 3970 * e1000e_reset - bring the hardware into a known good state 3971 * 3972 * This function boots the hardware and enables some settings that 3973 * require a configuration cycle of the hardware - those cannot be 3974 * set/changed during runtime. After reset the device needs to be 3975 * properly configured for Rx, Tx etc. 3976 */ 3977 void e1000e_reset(struct e1000_adapter *adapter) 3978 { 3979 struct e1000_mac_info *mac = &adapter->hw.mac; 3980 struct e1000_fc_info *fc = &adapter->hw.fc; 3981 struct e1000_hw *hw = &adapter->hw; 3982 u32 tx_space, min_tx_space, min_rx_space; 3983 u32 pba = adapter->pba; 3984 u16 hwm; 3985 3986 /* reset Packet Buffer Allocation to default */ 3987 ew32(PBA, pba); 3988 3989 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3990 /* To maintain wire speed transmits, the Tx FIFO should be 3991 * large enough to accommodate two full transmit packets, 3992 * rounded up to the next 1KB and expressed in KB. Likewise, 3993 * the Rx FIFO should be large enough to accommodate at least 3994 * one full receive packet and is similarly rounded up and 3995 * expressed in KB. 3996 */ 3997 pba = er32(PBA); 3998 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3999 tx_space = pba >> 16; 4000 /* lower 16 bits has Rx packet buffer allocation size in KB */ 4001 pba &= 0xffff; 4002 /* the Tx fifo also stores 16 bytes of information about the Tx 4003 * but don't include ethernet FCS because hardware appends it 4004 */ 4005 min_tx_space = (adapter->max_frame_size + 4006 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4007 min_tx_space = ALIGN(min_tx_space, 1024); 4008 min_tx_space >>= 10; 4009 /* software strips receive CRC, so leave room for it */ 4010 min_rx_space = adapter->max_frame_size; 4011 min_rx_space = ALIGN(min_rx_space, 1024); 4012 min_rx_space >>= 10; 4013 4014 /* If current Tx allocation is less than the min Tx FIFO size, 4015 * and the min Tx FIFO size is less than the current Rx FIFO 4016 * allocation, take space away from current Rx allocation 4017 */ 4018 if ((tx_space < min_tx_space) && 4019 ((min_tx_space - tx_space) < pba)) { 4020 pba -= min_tx_space - tx_space; 4021 4022 /* if short on Rx space, Rx wins and must trump Tx 4023 * adjustment 4024 */ 4025 if (pba < min_rx_space) 4026 pba = min_rx_space; 4027 } 4028 4029 ew32(PBA, pba); 4030 } 4031 4032 /* flow control settings 4033 * 4034 * The high water mark must be low enough to fit one full frame 4035 * (or the size used for early receive) above it in the Rx FIFO. 4036 * Set it to the lower of: 4037 * - 90% of the Rx FIFO size, and 4038 * - the full Rx FIFO size minus one full frame 4039 */ 4040 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4041 fc->pause_time = 0xFFFF; 4042 else 4043 fc->pause_time = E1000_FC_PAUSE_TIME; 4044 fc->send_xon = true; 4045 fc->current_mode = fc->requested_mode; 4046 4047 switch (hw->mac.type) { 4048 case e1000_ich9lan: 4049 case e1000_ich10lan: 4050 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4051 pba = 14; 4052 ew32(PBA, pba); 4053 fc->high_water = 0x2800; 4054 fc->low_water = fc->high_water - 8; 4055 break; 4056 } 4057 fallthrough; 4058 default: 4059 hwm = min(((pba << 10) * 9 / 10), 4060 ((pba << 10) - adapter->max_frame_size)); 4061 4062 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4063 fc->low_water = fc->high_water - 8; 4064 break; 4065 case e1000_pchlan: 4066 /* Workaround PCH LOM adapter hangs with certain network 4067 * loads. If hangs persist, try disabling Tx flow control. 4068 */ 4069 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4070 fc->high_water = 0x3500; 4071 fc->low_water = 0x1500; 4072 } else { 4073 fc->high_water = 0x5000; 4074 fc->low_water = 0x3000; 4075 } 4076 fc->refresh_time = 0x1000; 4077 break; 4078 case e1000_pch2lan: 4079 case e1000_pch_lpt: 4080 case e1000_pch_spt: 4081 case e1000_pch_cnp: 4082 case e1000_pch_tgp: 4083 case e1000_pch_adp: 4084 fc->refresh_time = 0xFFFF; 4085 fc->pause_time = 0xFFFF; 4086 4087 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4088 fc->high_water = 0x05C20; 4089 fc->low_water = 0x05048; 4090 break; 4091 } 4092 4093 pba = 14; 4094 ew32(PBA, pba); 4095 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4096 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4097 break; 4098 } 4099 4100 /* Alignment of Tx data is on an arbitrary byte boundary with the 4101 * maximum size per Tx descriptor limited only to the transmit 4102 * allocation of the packet buffer minus 96 bytes with an upper 4103 * limit of 24KB due to receive synchronization limitations. 4104 */ 4105 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4106 24 << 10); 4107 4108 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4109 * fit in receive buffer. 4110 */ 4111 if (adapter->itr_setting & 0x3) { 4112 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4113 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4114 dev_info(&adapter->pdev->dev, 4115 "Interrupt Throttle Rate off\n"); 4116 adapter->flags2 |= FLAG2_DISABLE_AIM; 4117 e1000e_write_itr(adapter, 0); 4118 } 4119 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4120 dev_info(&adapter->pdev->dev, 4121 "Interrupt Throttle Rate on\n"); 4122 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4123 adapter->itr = 20000; 4124 e1000e_write_itr(adapter, adapter->itr); 4125 } 4126 } 4127 4128 if (hw->mac.type >= e1000_pch_spt) 4129 e1000_flush_desc_rings(adapter); 4130 /* Allow time for pending master requests to run */ 4131 mac->ops.reset_hw(hw); 4132 4133 /* For parts with AMT enabled, let the firmware know 4134 * that the network interface is in control 4135 */ 4136 if (adapter->flags & FLAG_HAS_AMT) 4137 e1000e_get_hw_control(adapter); 4138 4139 ew32(WUC, 0); 4140 4141 if (mac->ops.init_hw(hw)) 4142 e_err("Hardware Error\n"); 4143 4144 e1000_update_mng_vlan(adapter); 4145 4146 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4147 ew32(VET, ETH_P_8021Q); 4148 4149 e1000e_reset_adaptive(hw); 4150 4151 /* restore systim and hwtstamp settings */ 4152 e1000e_systim_reset(adapter); 4153 4154 /* Set EEE advertisement as appropriate */ 4155 if (adapter->flags2 & FLAG2_HAS_EEE) { 4156 s32 ret_val; 4157 u16 adv_addr; 4158 4159 switch (hw->phy.type) { 4160 case e1000_phy_82579: 4161 adv_addr = I82579_EEE_ADVERTISEMENT; 4162 break; 4163 case e1000_phy_i217: 4164 adv_addr = I217_EEE_ADVERTISEMENT; 4165 break; 4166 default: 4167 dev_err(&adapter->pdev->dev, 4168 "Invalid PHY type setting EEE advertisement\n"); 4169 return; 4170 } 4171 4172 ret_val = hw->phy.ops.acquire(hw); 4173 if (ret_val) { 4174 dev_err(&adapter->pdev->dev, 4175 "EEE advertisement - unable to acquire PHY\n"); 4176 return; 4177 } 4178 4179 e1000_write_emi_reg_locked(hw, adv_addr, 4180 hw->dev_spec.ich8lan.eee_disable ? 4181 0 : adapter->eee_advert); 4182 4183 hw->phy.ops.release(hw); 4184 } 4185 4186 if (!netif_running(adapter->netdev) && 4187 !test_bit(__E1000_TESTING, &adapter->state)) 4188 e1000_power_down_phy(adapter); 4189 4190 e1000_get_phy_info(hw); 4191 4192 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4193 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4194 u16 phy_data = 0; 4195 /* speed up time to link by disabling smart power down, ignore 4196 * the return value of this function because there is nothing 4197 * different we would do if it failed 4198 */ 4199 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4200 phy_data &= ~IGP02E1000_PM_SPD; 4201 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4202 } 4203 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4204 u32 reg; 4205 4206 /* Fextnvm7 @ 0xe4[2] = 1 */ 4207 reg = er32(FEXTNVM7); 4208 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4209 ew32(FEXTNVM7, reg); 4210 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4211 reg = er32(FEXTNVM9); 4212 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4213 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4214 ew32(FEXTNVM9, reg); 4215 } 4216 4217 } 4218 4219 /** 4220 * e1000e_trigger_lsc - trigger an LSC interrupt 4221 * @adapter: 4222 * 4223 * Fire a link status change interrupt to start the watchdog. 4224 **/ 4225 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4226 { 4227 struct e1000_hw *hw = &adapter->hw; 4228 4229 if (adapter->msix_entries) 4230 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4231 else 4232 ew32(ICS, E1000_ICS_LSC); 4233 } 4234 4235 void e1000e_up(struct e1000_adapter *adapter) 4236 { 4237 /* hardware has been reset, we need to reload some things */ 4238 e1000_configure(adapter); 4239 4240 clear_bit(__E1000_DOWN, &adapter->state); 4241 4242 if (adapter->msix_entries) 4243 e1000_configure_msix(adapter); 4244 e1000_irq_enable(adapter); 4245 4246 /* Tx queue started by watchdog timer when link is up */ 4247 4248 e1000e_trigger_lsc(adapter); 4249 } 4250 4251 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4252 { 4253 struct e1000_hw *hw = &adapter->hw; 4254 4255 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4256 return; 4257 4258 /* flush pending descriptor writebacks to memory */ 4259 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4260 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4261 4262 /* execute the writes immediately */ 4263 e1e_flush(); 4264 4265 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4266 * write is successful 4267 */ 4268 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4269 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4270 4271 /* execute the writes immediately */ 4272 e1e_flush(); 4273 } 4274 4275 static void e1000e_update_stats(struct e1000_adapter *adapter); 4276 4277 /** 4278 * e1000e_down - quiesce the device and optionally reset the hardware 4279 * @adapter: board private structure 4280 * @reset: boolean flag to reset the hardware or not 4281 */ 4282 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4283 { 4284 struct net_device *netdev = adapter->netdev; 4285 struct e1000_hw *hw = &adapter->hw; 4286 u32 tctl, rctl; 4287 4288 /* signal that we're down so the interrupt handler does not 4289 * reschedule our watchdog timer 4290 */ 4291 set_bit(__E1000_DOWN, &adapter->state); 4292 4293 netif_carrier_off(netdev); 4294 4295 /* disable receives in the hardware */ 4296 rctl = er32(RCTL); 4297 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4298 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4299 /* flush and sleep below */ 4300 4301 netif_stop_queue(netdev); 4302 4303 /* disable transmits in the hardware */ 4304 tctl = er32(TCTL); 4305 tctl &= ~E1000_TCTL_EN; 4306 ew32(TCTL, tctl); 4307 4308 /* flush both disables and wait for them to finish */ 4309 e1e_flush(); 4310 usleep_range(10000, 11000); 4311 4312 e1000_irq_disable(adapter); 4313 4314 napi_synchronize(&adapter->napi); 4315 4316 del_timer_sync(&adapter->watchdog_timer); 4317 del_timer_sync(&adapter->phy_info_timer); 4318 4319 spin_lock(&adapter->stats64_lock); 4320 e1000e_update_stats(adapter); 4321 spin_unlock(&adapter->stats64_lock); 4322 4323 e1000e_flush_descriptors(adapter); 4324 4325 adapter->link_speed = 0; 4326 adapter->link_duplex = 0; 4327 4328 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4329 if ((hw->mac.type >= e1000_pch2lan) && 4330 (adapter->netdev->mtu > ETH_DATA_LEN) && 4331 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4332 e_dbg("failed to disable jumbo frame workaround mode\n"); 4333 4334 if (!pci_channel_offline(adapter->pdev)) { 4335 if (reset) 4336 e1000e_reset(adapter); 4337 else if (hw->mac.type >= e1000_pch_spt) 4338 e1000_flush_desc_rings(adapter); 4339 } 4340 e1000_clean_tx_ring(adapter->tx_ring); 4341 e1000_clean_rx_ring(adapter->rx_ring); 4342 } 4343 4344 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4345 { 4346 might_sleep(); 4347 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4348 usleep_range(1000, 1100); 4349 e1000e_down(adapter, true); 4350 e1000e_up(adapter); 4351 clear_bit(__E1000_RESETTING, &adapter->state); 4352 } 4353 4354 /** 4355 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4356 * @hw: pointer to the HW structure 4357 * @systim: PHC time value read, sanitized and returned 4358 * @sts: structure to hold system time before and after reading SYSTIML, 4359 * may be NULL 4360 * 4361 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4362 * check to see that the time is incrementing at a reasonable 4363 * rate and is a multiple of incvalue. 4364 **/ 4365 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, 4366 struct ptp_system_timestamp *sts) 4367 { 4368 u64 time_delta, rem, temp; 4369 u64 systim_next; 4370 u32 incvalue; 4371 int i; 4372 4373 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4374 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4375 /* latch SYSTIMH on read of SYSTIML */ 4376 ptp_read_system_prets(sts); 4377 systim_next = (u64)er32(SYSTIML); 4378 ptp_read_system_postts(sts); 4379 systim_next |= (u64)er32(SYSTIMH) << 32; 4380 4381 time_delta = systim_next - systim; 4382 temp = time_delta; 4383 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4384 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4385 4386 systim = systim_next; 4387 4388 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4389 break; 4390 } 4391 4392 return systim; 4393 } 4394 4395 /** 4396 * e1000e_read_systim - read SYSTIM register 4397 * @adapter: board private structure 4398 * @sts: structure which will contain system time before and after reading 4399 * SYSTIML, may be NULL 4400 **/ 4401 u64 e1000e_read_systim(struct e1000_adapter *adapter, 4402 struct ptp_system_timestamp *sts) 4403 { 4404 struct e1000_hw *hw = &adapter->hw; 4405 u32 systimel, systimel_2, systimeh; 4406 u64 systim; 4407 /* SYSTIMH latching upon SYSTIML read does not work well. 4408 * This means that if SYSTIML overflows after we read it but before 4409 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4410 * will experience a huge non linear increment in the systime value 4411 * to fix that we test for overflow and if true, we re-read systime. 4412 */ 4413 ptp_read_system_prets(sts); 4414 systimel = er32(SYSTIML); 4415 ptp_read_system_postts(sts); 4416 systimeh = er32(SYSTIMH); 4417 /* Is systimel is so large that overflow is possible? */ 4418 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4419 ptp_read_system_prets(sts); 4420 systimel_2 = er32(SYSTIML); 4421 ptp_read_system_postts(sts); 4422 if (systimel > systimel_2) { 4423 /* There was an overflow, read again SYSTIMH, and use 4424 * systimel_2 4425 */ 4426 systimeh = er32(SYSTIMH); 4427 systimel = systimel_2; 4428 } 4429 } 4430 systim = (u64)systimel; 4431 systim |= (u64)systimeh << 32; 4432 4433 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4434 systim = e1000e_sanitize_systim(hw, systim, sts); 4435 4436 return systim; 4437 } 4438 4439 /** 4440 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4441 * @cc: cyclecounter structure 4442 **/ 4443 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4444 { 4445 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4446 cc); 4447 4448 return e1000e_read_systim(adapter, NULL); 4449 } 4450 4451 /** 4452 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4453 * @adapter: board private structure to initialize 4454 * 4455 * e1000_sw_init initializes the Adapter private data structure. 4456 * Fields are initialized based on PCI device information and 4457 * OS network device settings (MTU size). 4458 **/ 4459 static int e1000_sw_init(struct e1000_adapter *adapter) 4460 { 4461 struct net_device *netdev = adapter->netdev; 4462 4463 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4464 adapter->rx_ps_bsize0 = 128; 4465 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4466 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4467 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4468 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4469 4470 spin_lock_init(&adapter->stats64_lock); 4471 4472 e1000e_set_interrupt_capability(adapter); 4473 4474 if (e1000_alloc_queues(adapter)) 4475 return -ENOMEM; 4476 4477 /* Setup hardware time stamping cyclecounter */ 4478 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4479 adapter->cc.read = e1000e_cyclecounter_read; 4480 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4481 adapter->cc.mult = 1; 4482 /* cc.shift set in e1000e_get_base_tininca() */ 4483 4484 spin_lock_init(&adapter->systim_lock); 4485 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4486 } 4487 4488 /* Explicitly disable IRQ since the NIC can be in any state. */ 4489 e1000_irq_disable(adapter); 4490 4491 set_bit(__E1000_DOWN, &adapter->state); 4492 return 0; 4493 } 4494 4495 /** 4496 * e1000_intr_msi_test - Interrupt Handler 4497 * @irq: interrupt number 4498 * @data: pointer to a network interface device structure 4499 **/ 4500 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4501 { 4502 struct net_device *netdev = data; 4503 struct e1000_adapter *adapter = netdev_priv(netdev); 4504 struct e1000_hw *hw = &adapter->hw; 4505 u32 icr = er32(ICR); 4506 4507 e_dbg("icr is %08X\n", icr); 4508 if (icr & E1000_ICR_RXSEQ) { 4509 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4510 /* Force memory writes to complete before acknowledging the 4511 * interrupt is handled. 4512 */ 4513 wmb(); 4514 } 4515 4516 return IRQ_HANDLED; 4517 } 4518 4519 /** 4520 * e1000_test_msi_interrupt - Returns 0 for successful test 4521 * @adapter: board private struct 4522 * 4523 * code flow taken from tg3.c 4524 **/ 4525 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4526 { 4527 struct net_device *netdev = adapter->netdev; 4528 struct e1000_hw *hw = &adapter->hw; 4529 int err; 4530 4531 /* poll_enable hasn't been called yet, so don't need disable */ 4532 /* clear any pending events */ 4533 er32(ICR); 4534 4535 /* free the real vector and request a test handler */ 4536 e1000_free_irq(adapter); 4537 e1000e_reset_interrupt_capability(adapter); 4538 4539 /* Assume that the test fails, if it succeeds then the test 4540 * MSI irq handler will unset this flag 4541 */ 4542 adapter->flags |= FLAG_MSI_TEST_FAILED; 4543 4544 err = pci_enable_msi(adapter->pdev); 4545 if (err) 4546 goto msi_test_failed; 4547 4548 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4549 netdev->name, netdev); 4550 if (err) { 4551 pci_disable_msi(adapter->pdev); 4552 goto msi_test_failed; 4553 } 4554 4555 /* Force memory writes to complete before enabling and firing an 4556 * interrupt. 4557 */ 4558 wmb(); 4559 4560 e1000_irq_enable(adapter); 4561 4562 /* fire an unusual interrupt on the test handler */ 4563 ew32(ICS, E1000_ICS_RXSEQ); 4564 e1e_flush(); 4565 msleep(100); 4566 4567 e1000_irq_disable(adapter); 4568 4569 rmb(); /* read flags after interrupt has been fired */ 4570 4571 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4572 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4573 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4574 } else { 4575 e_dbg("MSI interrupt test succeeded!\n"); 4576 } 4577 4578 free_irq(adapter->pdev->irq, netdev); 4579 pci_disable_msi(adapter->pdev); 4580 4581 msi_test_failed: 4582 e1000e_set_interrupt_capability(adapter); 4583 return e1000_request_irq(adapter); 4584 } 4585 4586 /** 4587 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4588 * @adapter: board private struct 4589 * 4590 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4591 **/ 4592 static int e1000_test_msi(struct e1000_adapter *adapter) 4593 { 4594 int err; 4595 u16 pci_cmd; 4596 4597 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4598 return 0; 4599 4600 /* disable SERR in case the MSI write causes a master abort */ 4601 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4602 if (pci_cmd & PCI_COMMAND_SERR) 4603 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4604 pci_cmd & ~PCI_COMMAND_SERR); 4605 4606 err = e1000_test_msi_interrupt(adapter); 4607 4608 /* re-enable SERR */ 4609 if (pci_cmd & PCI_COMMAND_SERR) { 4610 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4611 pci_cmd |= PCI_COMMAND_SERR; 4612 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4613 } 4614 4615 return err; 4616 } 4617 4618 /** 4619 * e1000e_open - Called when a network interface is made active 4620 * @netdev: network interface device structure 4621 * 4622 * Returns 0 on success, negative value on failure 4623 * 4624 * The open entry point is called when a network interface is made 4625 * active by the system (IFF_UP). At this point all resources needed 4626 * for transmit and receive operations are allocated, the interrupt 4627 * handler is registered with the OS, the watchdog timer is started, 4628 * and the stack is notified that the interface is ready. 4629 **/ 4630 int e1000e_open(struct net_device *netdev) 4631 { 4632 struct e1000_adapter *adapter = netdev_priv(netdev); 4633 struct e1000_hw *hw = &adapter->hw; 4634 struct pci_dev *pdev = adapter->pdev; 4635 int err; 4636 4637 /* disallow open during test */ 4638 if (test_bit(__E1000_TESTING, &adapter->state)) 4639 return -EBUSY; 4640 4641 pm_runtime_get_sync(&pdev->dev); 4642 4643 netif_carrier_off(netdev); 4644 netif_stop_queue(netdev); 4645 4646 /* allocate transmit descriptors */ 4647 err = e1000e_setup_tx_resources(adapter->tx_ring); 4648 if (err) 4649 goto err_setup_tx; 4650 4651 /* allocate receive descriptors */ 4652 err = e1000e_setup_rx_resources(adapter->rx_ring); 4653 if (err) 4654 goto err_setup_rx; 4655 4656 /* If AMT is enabled, let the firmware know that the network 4657 * interface is now open and reset the part to a known state. 4658 */ 4659 if (adapter->flags & FLAG_HAS_AMT) { 4660 e1000e_get_hw_control(adapter); 4661 e1000e_reset(adapter); 4662 } 4663 4664 e1000e_power_up_phy(adapter); 4665 4666 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4667 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4668 e1000_update_mng_vlan(adapter); 4669 4670 /* DMA latency requirement to workaround jumbo issue */ 4671 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE); 4672 4673 /* before we allocate an interrupt, we must be ready to handle it. 4674 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4675 * as soon as we call pci_request_irq, so we have to setup our 4676 * clean_rx handler before we do so. 4677 */ 4678 e1000_configure(adapter); 4679 4680 err = e1000_request_irq(adapter); 4681 if (err) 4682 goto err_req_irq; 4683 4684 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4685 * ignore e1000e MSI messages, which means we need to test our MSI 4686 * interrupt now 4687 */ 4688 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4689 err = e1000_test_msi(adapter); 4690 if (err) { 4691 e_err("Interrupt allocation failed\n"); 4692 goto err_req_irq; 4693 } 4694 } 4695 4696 /* From here on the code is the same as e1000e_up() */ 4697 clear_bit(__E1000_DOWN, &adapter->state); 4698 4699 napi_enable(&adapter->napi); 4700 4701 e1000_irq_enable(adapter); 4702 4703 adapter->tx_hang_recheck = false; 4704 4705 hw->mac.get_link_status = true; 4706 pm_runtime_put(&pdev->dev); 4707 4708 e1000e_trigger_lsc(adapter); 4709 4710 return 0; 4711 4712 err_req_irq: 4713 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4714 e1000e_release_hw_control(adapter); 4715 e1000_power_down_phy(adapter); 4716 e1000e_free_rx_resources(adapter->rx_ring); 4717 err_setup_rx: 4718 e1000e_free_tx_resources(adapter->tx_ring); 4719 err_setup_tx: 4720 e1000e_reset(adapter); 4721 pm_runtime_put_sync(&pdev->dev); 4722 4723 return err; 4724 } 4725 4726 /** 4727 * e1000e_close - Disables a network interface 4728 * @netdev: network interface device structure 4729 * 4730 * Returns 0, this is not allowed to fail 4731 * 4732 * The close entry point is called when an interface is de-activated 4733 * by the OS. The hardware is still under the drivers control, but 4734 * needs to be disabled. A global MAC reset is issued to stop the 4735 * hardware, and all transmit and receive resources are freed. 4736 **/ 4737 int e1000e_close(struct net_device *netdev) 4738 { 4739 struct e1000_adapter *adapter = netdev_priv(netdev); 4740 struct pci_dev *pdev = adapter->pdev; 4741 int count = E1000_CHECK_RESET_COUNT; 4742 4743 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4744 usleep_range(10000, 11000); 4745 4746 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4747 4748 pm_runtime_get_sync(&pdev->dev); 4749 4750 if (netif_device_present(netdev)) { 4751 e1000e_down(adapter, true); 4752 e1000_free_irq(adapter); 4753 4754 /* Link status message must follow this format */ 4755 netdev_info(netdev, "NIC Link is Down\n"); 4756 } 4757 4758 napi_disable(&adapter->napi); 4759 4760 e1000e_free_tx_resources(adapter->tx_ring); 4761 e1000e_free_rx_resources(adapter->rx_ring); 4762 4763 /* kill manageability vlan ID if supported, but not if a vlan with 4764 * the same ID is registered on the host OS (let 8021q kill it) 4765 */ 4766 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4767 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4768 adapter->mng_vlan_id); 4769 4770 /* If AMT is enabled, let the firmware know that the network 4771 * interface is now closed 4772 */ 4773 if ((adapter->flags & FLAG_HAS_AMT) && 4774 !test_bit(__E1000_TESTING, &adapter->state)) 4775 e1000e_release_hw_control(adapter); 4776 4777 cpu_latency_qos_remove_request(&adapter->pm_qos_req); 4778 4779 pm_runtime_put_sync(&pdev->dev); 4780 4781 return 0; 4782 } 4783 4784 /** 4785 * e1000_set_mac - Change the Ethernet Address of the NIC 4786 * @netdev: network interface device structure 4787 * @p: pointer to an address structure 4788 * 4789 * Returns 0 on success, negative on failure 4790 **/ 4791 static int e1000_set_mac(struct net_device *netdev, void *p) 4792 { 4793 struct e1000_adapter *adapter = netdev_priv(netdev); 4794 struct e1000_hw *hw = &adapter->hw; 4795 struct sockaddr *addr = p; 4796 4797 if (!is_valid_ether_addr(addr->sa_data)) 4798 return -EADDRNOTAVAIL; 4799 4800 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4801 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4802 4803 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4804 4805 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4806 /* activate the work around */ 4807 e1000e_set_laa_state_82571(&adapter->hw, 1); 4808 4809 /* Hold a copy of the LAA in RAR[14] This is done so that 4810 * between the time RAR[0] gets clobbered and the time it 4811 * gets fixed (in e1000_watchdog), the actual LAA is in one 4812 * of the RARs and no incoming packets directed to this port 4813 * are dropped. Eventually the LAA will be in RAR[0] and 4814 * RAR[14] 4815 */ 4816 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4817 adapter->hw.mac.rar_entry_count - 1); 4818 } 4819 4820 return 0; 4821 } 4822 4823 /** 4824 * e1000e_update_phy_task - work thread to update phy 4825 * @work: pointer to our work struct 4826 * 4827 * this worker thread exists because we must acquire a 4828 * semaphore to read the phy, which we could msleep while 4829 * waiting for it, and we can't msleep in a timer. 4830 **/ 4831 static void e1000e_update_phy_task(struct work_struct *work) 4832 { 4833 struct e1000_adapter *adapter = container_of(work, 4834 struct e1000_adapter, 4835 update_phy_task); 4836 struct e1000_hw *hw = &adapter->hw; 4837 4838 if (test_bit(__E1000_DOWN, &adapter->state)) 4839 return; 4840 4841 e1000_get_phy_info(hw); 4842 4843 /* Enable EEE on 82579 after link up */ 4844 if (hw->phy.type >= e1000_phy_82579) 4845 e1000_set_eee_pchlan(hw); 4846 } 4847 4848 /** 4849 * e1000_update_phy_info - timre call-back to update PHY info 4850 * @data: pointer to adapter cast into an unsigned long 4851 * 4852 * Need to wait a few seconds after link up to get diagnostic information from 4853 * the phy 4854 **/ 4855 static void e1000_update_phy_info(struct timer_list *t) 4856 { 4857 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4858 4859 if (test_bit(__E1000_DOWN, &adapter->state)) 4860 return; 4861 4862 schedule_work(&adapter->update_phy_task); 4863 } 4864 4865 /** 4866 * e1000e_update_phy_stats - Update the PHY statistics counters 4867 * @adapter: board private structure 4868 * 4869 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4870 **/ 4871 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4872 { 4873 struct e1000_hw *hw = &adapter->hw; 4874 s32 ret_val; 4875 u16 phy_data; 4876 4877 ret_val = hw->phy.ops.acquire(hw); 4878 if (ret_val) 4879 return; 4880 4881 /* A page set is expensive so check if already on desired page. 4882 * If not, set to the page with the PHY status registers. 4883 */ 4884 hw->phy.addr = 1; 4885 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4886 &phy_data); 4887 if (ret_val) 4888 goto release; 4889 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4890 ret_val = hw->phy.ops.set_page(hw, 4891 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4892 if (ret_val) 4893 goto release; 4894 } 4895 4896 /* Single Collision Count */ 4897 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4899 if (!ret_val) 4900 adapter->stats.scc += phy_data; 4901 4902 /* Excessive Collision Count */ 4903 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4905 if (!ret_val) 4906 adapter->stats.ecol += phy_data; 4907 4908 /* Multiple Collision Count */ 4909 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4911 if (!ret_val) 4912 adapter->stats.mcc += phy_data; 4913 4914 /* Late Collision Count */ 4915 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4917 if (!ret_val) 4918 adapter->stats.latecol += phy_data; 4919 4920 /* Collision Count - also used for adaptive IFS */ 4921 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4922 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4923 if (!ret_val) 4924 hw->mac.collision_delta = phy_data; 4925 4926 /* Defer Count */ 4927 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4928 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4929 if (!ret_val) 4930 adapter->stats.dc += phy_data; 4931 4932 /* Transmit with no CRS */ 4933 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4934 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4935 if (!ret_val) 4936 adapter->stats.tncrs += phy_data; 4937 4938 release: 4939 hw->phy.ops.release(hw); 4940 } 4941 4942 /** 4943 * e1000e_update_stats - Update the board statistics counters 4944 * @adapter: board private structure 4945 **/ 4946 static void e1000e_update_stats(struct e1000_adapter *adapter) 4947 { 4948 struct net_device *netdev = adapter->netdev; 4949 struct e1000_hw *hw = &adapter->hw; 4950 struct pci_dev *pdev = adapter->pdev; 4951 4952 /* Prevent stats update while adapter is being reset, or if the pci 4953 * connection is down. 4954 */ 4955 if (adapter->link_speed == 0) 4956 return; 4957 if (pci_channel_offline(pdev)) 4958 return; 4959 4960 adapter->stats.crcerrs += er32(CRCERRS); 4961 adapter->stats.gprc += er32(GPRC); 4962 adapter->stats.gorc += er32(GORCL); 4963 er32(GORCH); /* Clear gorc */ 4964 adapter->stats.bprc += er32(BPRC); 4965 adapter->stats.mprc += er32(MPRC); 4966 adapter->stats.roc += er32(ROC); 4967 4968 adapter->stats.mpc += er32(MPC); 4969 4970 /* Half-duplex statistics */ 4971 if (adapter->link_duplex == HALF_DUPLEX) { 4972 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4973 e1000e_update_phy_stats(adapter); 4974 } else { 4975 adapter->stats.scc += er32(SCC); 4976 adapter->stats.ecol += er32(ECOL); 4977 adapter->stats.mcc += er32(MCC); 4978 adapter->stats.latecol += er32(LATECOL); 4979 adapter->stats.dc += er32(DC); 4980 4981 hw->mac.collision_delta = er32(COLC); 4982 4983 if ((hw->mac.type != e1000_82574) && 4984 (hw->mac.type != e1000_82583)) 4985 adapter->stats.tncrs += er32(TNCRS); 4986 } 4987 adapter->stats.colc += hw->mac.collision_delta; 4988 } 4989 4990 adapter->stats.xonrxc += er32(XONRXC); 4991 adapter->stats.xontxc += er32(XONTXC); 4992 adapter->stats.xoffrxc += er32(XOFFRXC); 4993 adapter->stats.xofftxc += er32(XOFFTXC); 4994 adapter->stats.gptc += er32(GPTC); 4995 adapter->stats.gotc += er32(GOTCL); 4996 er32(GOTCH); /* Clear gotc */ 4997 adapter->stats.rnbc += er32(RNBC); 4998 adapter->stats.ruc += er32(RUC); 4999 5000 adapter->stats.mptc += er32(MPTC); 5001 adapter->stats.bptc += er32(BPTC); 5002 5003 /* used for adaptive IFS */ 5004 5005 hw->mac.tx_packet_delta = er32(TPT); 5006 adapter->stats.tpt += hw->mac.tx_packet_delta; 5007 5008 adapter->stats.algnerrc += er32(ALGNERRC); 5009 adapter->stats.rxerrc += er32(RXERRC); 5010 adapter->stats.cexterr += er32(CEXTERR); 5011 adapter->stats.tsctc += er32(TSCTC); 5012 adapter->stats.tsctfc += er32(TSCTFC); 5013 5014 /* Fill out the OS statistics structure */ 5015 netdev->stats.multicast = adapter->stats.mprc; 5016 netdev->stats.collisions = adapter->stats.colc; 5017 5018 /* Rx Errors */ 5019 5020 /* RLEC on some newer hardware can be incorrect so build 5021 * our own version based on RUC and ROC 5022 */ 5023 netdev->stats.rx_errors = adapter->stats.rxerrc + 5024 adapter->stats.crcerrs + adapter->stats.algnerrc + 5025 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5026 netdev->stats.rx_length_errors = adapter->stats.ruc + 5027 adapter->stats.roc; 5028 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5029 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5030 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5031 5032 /* Tx Errors */ 5033 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5034 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5035 netdev->stats.tx_window_errors = adapter->stats.latecol; 5036 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5037 5038 /* Tx Dropped needs to be maintained elsewhere */ 5039 5040 /* Management Stats */ 5041 adapter->stats.mgptc += er32(MGTPTC); 5042 adapter->stats.mgprc += er32(MGTPRC); 5043 adapter->stats.mgpdc += er32(MGTPDC); 5044 5045 /* Correctable ECC Errors */ 5046 if (hw->mac.type >= e1000_pch_lpt) { 5047 u32 pbeccsts = er32(PBECCSTS); 5048 5049 adapter->corr_errors += 5050 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5051 adapter->uncorr_errors += 5052 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5053 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5054 } 5055 } 5056 5057 /** 5058 * e1000_phy_read_status - Update the PHY register status snapshot 5059 * @adapter: board private structure 5060 **/ 5061 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5062 { 5063 struct e1000_hw *hw = &adapter->hw; 5064 struct e1000_phy_regs *phy = &adapter->phy_regs; 5065 5066 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5067 (er32(STATUS) & E1000_STATUS_LU) && 5068 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5069 int ret_val; 5070 5071 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5072 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5073 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5074 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5075 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5076 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5077 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5078 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5079 if (ret_val) 5080 e_warn("Error reading PHY register\n"); 5081 } else { 5082 /* Do not read PHY registers if link is not up 5083 * Set values to typical power-on defaults 5084 */ 5085 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5086 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5087 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5088 BMSR_ERCAP); 5089 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5090 ADVERTISE_ALL | ADVERTISE_CSMA); 5091 phy->lpa = 0; 5092 phy->expansion = EXPANSION_ENABLENPAGE; 5093 phy->ctrl1000 = ADVERTISE_1000FULL; 5094 phy->stat1000 = 0; 5095 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5096 } 5097 } 5098 5099 static void e1000_print_link_info(struct e1000_adapter *adapter) 5100 { 5101 struct e1000_hw *hw = &adapter->hw; 5102 u32 ctrl = er32(CTRL); 5103 5104 /* Link status message must follow this format for user tools */ 5105 netdev_info(adapter->netdev, 5106 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5107 adapter->link_speed, 5108 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5109 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5110 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5111 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5112 } 5113 5114 static bool e1000e_has_link(struct e1000_adapter *adapter) 5115 { 5116 struct e1000_hw *hw = &adapter->hw; 5117 bool link_active = false; 5118 s32 ret_val = 0; 5119 5120 /* get_link_status is set on LSC (link status) interrupt or 5121 * Rx sequence error interrupt. get_link_status will stay 5122 * true until the check_for_link establishes link 5123 * for copper adapters ONLY 5124 */ 5125 switch (hw->phy.media_type) { 5126 case e1000_media_type_copper: 5127 if (hw->mac.get_link_status) { 5128 ret_val = hw->mac.ops.check_for_link(hw); 5129 link_active = !hw->mac.get_link_status; 5130 } else { 5131 link_active = true; 5132 } 5133 break; 5134 case e1000_media_type_fiber: 5135 ret_val = hw->mac.ops.check_for_link(hw); 5136 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5137 break; 5138 case e1000_media_type_internal_serdes: 5139 ret_val = hw->mac.ops.check_for_link(hw); 5140 link_active = hw->mac.serdes_has_link; 5141 break; 5142 default: 5143 case e1000_media_type_unknown: 5144 break; 5145 } 5146 5147 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5148 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5149 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5150 e_info("Gigabit has been disabled, downgrading speed\n"); 5151 } 5152 5153 return link_active; 5154 } 5155 5156 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5157 { 5158 /* make sure the receive unit is started */ 5159 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5160 (adapter->flags & FLAG_RESTART_NOW)) { 5161 struct e1000_hw *hw = &adapter->hw; 5162 u32 rctl = er32(RCTL); 5163 5164 ew32(RCTL, rctl | E1000_RCTL_EN); 5165 adapter->flags &= ~FLAG_RESTART_NOW; 5166 } 5167 } 5168 5169 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5170 { 5171 struct e1000_hw *hw = &adapter->hw; 5172 5173 /* With 82574 controllers, PHY needs to be checked periodically 5174 * for hung state and reset, if two calls return true 5175 */ 5176 if (e1000_check_phy_82574(hw)) 5177 adapter->phy_hang_count++; 5178 else 5179 adapter->phy_hang_count = 0; 5180 5181 if (adapter->phy_hang_count > 1) { 5182 adapter->phy_hang_count = 0; 5183 e_dbg("PHY appears hung - resetting\n"); 5184 schedule_work(&adapter->reset_task); 5185 } 5186 } 5187 5188 /** 5189 * e1000_watchdog - Timer Call-back 5190 * @data: pointer to adapter cast into an unsigned long 5191 **/ 5192 static void e1000_watchdog(struct timer_list *t) 5193 { 5194 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5195 5196 /* Do the rest outside of interrupt context */ 5197 schedule_work(&adapter->watchdog_task); 5198 5199 /* TODO: make this use queue_delayed_work() */ 5200 } 5201 5202 static void e1000_watchdog_task(struct work_struct *work) 5203 { 5204 struct e1000_adapter *adapter = container_of(work, 5205 struct e1000_adapter, 5206 watchdog_task); 5207 struct net_device *netdev = adapter->netdev; 5208 struct e1000_mac_info *mac = &adapter->hw.mac; 5209 struct e1000_phy_info *phy = &adapter->hw.phy; 5210 struct e1000_ring *tx_ring = adapter->tx_ring; 5211 u32 dmoff_exit_timeout = 100, tries = 0; 5212 struct e1000_hw *hw = &adapter->hw; 5213 u32 link, tctl, pcim_state; 5214 5215 if (test_bit(__E1000_DOWN, &adapter->state)) 5216 return; 5217 5218 link = e1000e_has_link(adapter); 5219 if ((netif_carrier_ok(netdev)) && link) { 5220 /* Cancel scheduled suspend requests. */ 5221 pm_runtime_resume(netdev->dev.parent); 5222 5223 e1000e_enable_receives(adapter); 5224 goto link_up; 5225 } 5226 5227 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5228 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5229 e1000_update_mng_vlan(adapter); 5230 5231 if (link) { 5232 if (!netif_carrier_ok(netdev)) { 5233 bool txb2b = true; 5234 5235 /* Cancel scheduled suspend requests. */ 5236 pm_runtime_resume(netdev->dev.parent); 5237 5238 /* Checking if MAC is in DMoff state*/ 5239 pcim_state = er32(STATUS); 5240 while (pcim_state & E1000_STATUS_PCIM_STATE) { 5241 if (tries++ == dmoff_exit_timeout) { 5242 e_dbg("Error in exiting dmoff\n"); 5243 break; 5244 } 5245 usleep_range(10000, 20000); 5246 pcim_state = er32(STATUS); 5247 5248 /* Checking if MAC exited DMoff state */ 5249 if (!(pcim_state & E1000_STATUS_PCIM_STATE)) 5250 e1000_phy_hw_reset(&adapter->hw); 5251 } 5252 5253 /* update snapshot of PHY registers on LSC */ 5254 e1000_phy_read_status(adapter); 5255 mac->ops.get_link_up_info(&adapter->hw, 5256 &adapter->link_speed, 5257 &adapter->link_duplex); 5258 e1000_print_link_info(adapter); 5259 5260 /* check if SmartSpeed worked */ 5261 e1000e_check_downshift(hw); 5262 if (phy->speed_downgraded) 5263 netdev_warn(netdev, 5264 "Link Speed was downgraded by SmartSpeed\n"); 5265 5266 /* On supported PHYs, check for duplex mismatch only 5267 * if link has autonegotiated at 10/100 half 5268 */ 5269 if ((hw->phy.type == e1000_phy_igp_3 || 5270 hw->phy.type == e1000_phy_bm) && 5271 hw->mac.autoneg && 5272 (adapter->link_speed == SPEED_10 || 5273 adapter->link_speed == SPEED_100) && 5274 (adapter->link_duplex == HALF_DUPLEX)) { 5275 u16 autoneg_exp; 5276 5277 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5278 5279 if (!(autoneg_exp & EXPANSION_NWAY)) 5280 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5281 } 5282 5283 /* adjust timeout factor according to speed/duplex */ 5284 adapter->tx_timeout_factor = 1; 5285 switch (adapter->link_speed) { 5286 case SPEED_10: 5287 txb2b = false; 5288 adapter->tx_timeout_factor = 16; 5289 break; 5290 case SPEED_100: 5291 txb2b = false; 5292 adapter->tx_timeout_factor = 10; 5293 break; 5294 } 5295 5296 /* workaround: re-program speed mode bit after 5297 * link-up event 5298 */ 5299 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5300 !txb2b) { 5301 u32 tarc0; 5302 5303 tarc0 = er32(TARC(0)); 5304 tarc0 &= ~SPEED_MODE_BIT; 5305 ew32(TARC(0), tarc0); 5306 } 5307 5308 /* disable TSO for pcie and 10/100 speeds, to avoid 5309 * some hardware issues 5310 */ 5311 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5312 switch (adapter->link_speed) { 5313 case SPEED_10: 5314 case SPEED_100: 5315 e_info("10/100 speed: disabling TSO\n"); 5316 netdev->features &= ~NETIF_F_TSO; 5317 netdev->features &= ~NETIF_F_TSO6; 5318 break; 5319 case SPEED_1000: 5320 netdev->features |= NETIF_F_TSO; 5321 netdev->features |= NETIF_F_TSO6; 5322 break; 5323 default: 5324 /* oops */ 5325 break; 5326 } 5327 if (hw->mac.type == e1000_pch_spt) { 5328 netdev->features &= ~NETIF_F_TSO; 5329 netdev->features &= ~NETIF_F_TSO6; 5330 } 5331 } 5332 5333 /* enable transmits in the hardware, need to do this 5334 * after setting TARC(0) 5335 */ 5336 tctl = er32(TCTL); 5337 tctl |= E1000_TCTL_EN; 5338 ew32(TCTL, tctl); 5339 5340 /* Perform any post-link-up configuration before 5341 * reporting link up. 5342 */ 5343 if (phy->ops.cfg_on_link_up) 5344 phy->ops.cfg_on_link_up(hw); 5345 5346 netif_wake_queue(netdev); 5347 netif_carrier_on(netdev); 5348 5349 if (!test_bit(__E1000_DOWN, &adapter->state)) 5350 mod_timer(&adapter->phy_info_timer, 5351 round_jiffies(jiffies + 2 * HZ)); 5352 } 5353 } else { 5354 if (netif_carrier_ok(netdev)) { 5355 adapter->link_speed = 0; 5356 adapter->link_duplex = 0; 5357 /* Link status message must follow this format */ 5358 netdev_info(netdev, "NIC Link is Down\n"); 5359 netif_carrier_off(netdev); 5360 netif_stop_queue(netdev); 5361 if (!test_bit(__E1000_DOWN, &adapter->state)) 5362 mod_timer(&adapter->phy_info_timer, 5363 round_jiffies(jiffies + 2 * HZ)); 5364 5365 /* 8000ES2LAN requires a Rx packet buffer work-around 5366 * on link down event; reset the controller to flush 5367 * the Rx packet buffer. 5368 */ 5369 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5370 adapter->flags |= FLAG_RESTART_NOW; 5371 else 5372 pm_schedule_suspend(netdev->dev.parent, 5373 LINK_TIMEOUT); 5374 } 5375 } 5376 5377 link_up: 5378 spin_lock(&adapter->stats64_lock); 5379 e1000e_update_stats(adapter); 5380 5381 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5382 adapter->tpt_old = adapter->stats.tpt; 5383 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5384 adapter->colc_old = adapter->stats.colc; 5385 5386 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5387 adapter->gorc_old = adapter->stats.gorc; 5388 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5389 adapter->gotc_old = adapter->stats.gotc; 5390 spin_unlock(&adapter->stats64_lock); 5391 5392 /* If the link is lost the controller stops DMA, but 5393 * if there is queued Tx work it cannot be done. So 5394 * reset the controller to flush the Tx packet buffers. 5395 */ 5396 if (!netif_carrier_ok(netdev) && 5397 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5398 adapter->flags |= FLAG_RESTART_NOW; 5399 5400 /* If reset is necessary, do it outside of interrupt context. */ 5401 if (adapter->flags & FLAG_RESTART_NOW) { 5402 schedule_work(&adapter->reset_task); 5403 /* return immediately since reset is imminent */ 5404 return; 5405 } 5406 5407 e1000e_update_adaptive(&adapter->hw); 5408 5409 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5410 if (adapter->itr_setting == 4) { 5411 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5412 * Total asymmetrical Tx or Rx gets ITR=8000; 5413 * everyone else is between 2000-8000. 5414 */ 5415 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5416 u32 dif = (adapter->gotc > adapter->gorc ? 5417 adapter->gotc - adapter->gorc : 5418 adapter->gorc - adapter->gotc) / 10000; 5419 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5420 5421 e1000e_write_itr(adapter, itr); 5422 } 5423 5424 /* Cause software interrupt to ensure Rx ring is cleaned */ 5425 if (adapter->msix_entries) 5426 ew32(ICS, adapter->rx_ring->ims_val); 5427 else 5428 ew32(ICS, E1000_ICS_RXDMT0); 5429 5430 /* flush pending descriptors to memory before detecting Tx hang */ 5431 e1000e_flush_descriptors(adapter); 5432 5433 /* Force detection of hung controller every watchdog period */ 5434 adapter->detect_tx_hung = true; 5435 5436 /* With 82571 controllers, LAA may be overwritten due to controller 5437 * reset from the other port. Set the appropriate LAA in RAR[0] 5438 */ 5439 if (e1000e_get_laa_state_82571(hw)) 5440 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5441 5442 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5443 e1000e_check_82574_phy_workaround(adapter); 5444 5445 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5446 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5447 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5448 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5449 er32(RXSTMPH); 5450 adapter->rx_hwtstamp_cleared++; 5451 } else { 5452 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5453 } 5454 } 5455 5456 /* Reset the timer */ 5457 if (!test_bit(__E1000_DOWN, &adapter->state)) 5458 mod_timer(&adapter->watchdog_timer, 5459 round_jiffies(jiffies + 2 * HZ)); 5460 } 5461 5462 #define E1000_TX_FLAGS_CSUM 0x00000001 5463 #define E1000_TX_FLAGS_VLAN 0x00000002 5464 #define E1000_TX_FLAGS_TSO 0x00000004 5465 #define E1000_TX_FLAGS_IPV4 0x00000008 5466 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5467 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5468 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5469 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5470 5471 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5472 __be16 protocol) 5473 { 5474 struct e1000_context_desc *context_desc; 5475 struct e1000_buffer *buffer_info; 5476 unsigned int i; 5477 u32 cmd_length = 0; 5478 u16 ipcse = 0, mss; 5479 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5480 int err; 5481 5482 if (!skb_is_gso(skb)) 5483 return 0; 5484 5485 err = skb_cow_head(skb, 0); 5486 if (err < 0) 5487 return err; 5488 5489 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5490 mss = skb_shinfo(skb)->gso_size; 5491 if (protocol == htons(ETH_P_IP)) { 5492 struct iphdr *iph = ip_hdr(skb); 5493 iph->tot_len = 0; 5494 iph->check = 0; 5495 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5496 0, IPPROTO_TCP, 0); 5497 cmd_length = E1000_TXD_CMD_IP; 5498 ipcse = skb_transport_offset(skb) - 1; 5499 } else if (skb_is_gso_v6(skb)) { 5500 tcp_v6_gso_csum_prep(skb); 5501 ipcse = 0; 5502 } 5503 ipcss = skb_network_offset(skb); 5504 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5505 tucss = skb_transport_offset(skb); 5506 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5507 5508 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5509 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5510 5511 i = tx_ring->next_to_use; 5512 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5513 buffer_info = &tx_ring->buffer_info[i]; 5514 5515 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5516 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5517 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5518 context_desc->upper_setup.tcp_fields.tucss = tucss; 5519 context_desc->upper_setup.tcp_fields.tucso = tucso; 5520 context_desc->upper_setup.tcp_fields.tucse = 0; 5521 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5522 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5523 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5524 5525 buffer_info->time_stamp = jiffies; 5526 buffer_info->next_to_watch = i; 5527 5528 i++; 5529 if (i == tx_ring->count) 5530 i = 0; 5531 tx_ring->next_to_use = i; 5532 5533 return 1; 5534 } 5535 5536 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5537 __be16 protocol) 5538 { 5539 struct e1000_adapter *adapter = tx_ring->adapter; 5540 struct e1000_context_desc *context_desc; 5541 struct e1000_buffer *buffer_info; 5542 unsigned int i; 5543 u8 css; 5544 u32 cmd_len = E1000_TXD_CMD_DEXT; 5545 5546 if (skb->ip_summed != CHECKSUM_PARTIAL) 5547 return false; 5548 5549 switch (protocol) { 5550 case cpu_to_be16(ETH_P_IP): 5551 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5552 cmd_len |= E1000_TXD_CMD_TCP; 5553 break; 5554 case cpu_to_be16(ETH_P_IPV6): 5555 /* XXX not handling all IPV6 headers */ 5556 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5557 cmd_len |= E1000_TXD_CMD_TCP; 5558 break; 5559 default: 5560 if (unlikely(net_ratelimit())) 5561 e_warn("checksum_partial proto=%x!\n", 5562 be16_to_cpu(protocol)); 5563 break; 5564 } 5565 5566 css = skb_checksum_start_offset(skb); 5567 5568 i = tx_ring->next_to_use; 5569 buffer_info = &tx_ring->buffer_info[i]; 5570 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5571 5572 context_desc->lower_setup.ip_config = 0; 5573 context_desc->upper_setup.tcp_fields.tucss = css; 5574 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5575 context_desc->upper_setup.tcp_fields.tucse = 0; 5576 context_desc->tcp_seg_setup.data = 0; 5577 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5578 5579 buffer_info->time_stamp = jiffies; 5580 buffer_info->next_to_watch = i; 5581 5582 i++; 5583 if (i == tx_ring->count) 5584 i = 0; 5585 tx_ring->next_to_use = i; 5586 5587 return true; 5588 } 5589 5590 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5591 unsigned int first, unsigned int max_per_txd, 5592 unsigned int nr_frags) 5593 { 5594 struct e1000_adapter *adapter = tx_ring->adapter; 5595 struct pci_dev *pdev = adapter->pdev; 5596 struct e1000_buffer *buffer_info; 5597 unsigned int len = skb_headlen(skb); 5598 unsigned int offset = 0, size, count = 0, i; 5599 unsigned int f, bytecount, segs; 5600 5601 i = tx_ring->next_to_use; 5602 5603 while (len) { 5604 buffer_info = &tx_ring->buffer_info[i]; 5605 size = min(len, max_per_txd); 5606 5607 buffer_info->length = size; 5608 buffer_info->time_stamp = jiffies; 5609 buffer_info->next_to_watch = i; 5610 buffer_info->dma = dma_map_single(&pdev->dev, 5611 skb->data + offset, 5612 size, DMA_TO_DEVICE); 5613 buffer_info->mapped_as_page = false; 5614 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5615 goto dma_error; 5616 5617 len -= size; 5618 offset += size; 5619 count++; 5620 5621 if (len) { 5622 i++; 5623 if (i == tx_ring->count) 5624 i = 0; 5625 } 5626 } 5627 5628 for (f = 0; f < nr_frags; f++) { 5629 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 5630 5631 len = skb_frag_size(frag); 5632 offset = 0; 5633 5634 while (len) { 5635 i++; 5636 if (i == tx_ring->count) 5637 i = 0; 5638 5639 buffer_info = &tx_ring->buffer_info[i]; 5640 size = min(len, max_per_txd); 5641 5642 buffer_info->length = size; 5643 buffer_info->time_stamp = jiffies; 5644 buffer_info->next_to_watch = i; 5645 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5646 offset, size, 5647 DMA_TO_DEVICE); 5648 buffer_info->mapped_as_page = true; 5649 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5650 goto dma_error; 5651 5652 len -= size; 5653 offset += size; 5654 count++; 5655 } 5656 } 5657 5658 segs = skb_shinfo(skb)->gso_segs ? : 1; 5659 /* multiply data chunks by size of headers */ 5660 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5661 5662 tx_ring->buffer_info[i].skb = skb; 5663 tx_ring->buffer_info[i].segs = segs; 5664 tx_ring->buffer_info[i].bytecount = bytecount; 5665 tx_ring->buffer_info[first].next_to_watch = i; 5666 5667 return count; 5668 5669 dma_error: 5670 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5671 buffer_info->dma = 0; 5672 if (count) 5673 count--; 5674 5675 while (count--) { 5676 if (i == 0) 5677 i += tx_ring->count; 5678 i--; 5679 buffer_info = &tx_ring->buffer_info[i]; 5680 e1000_put_txbuf(tx_ring, buffer_info, true); 5681 } 5682 5683 return 0; 5684 } 5685 5686 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5687 { 5688 struct e1000_adapter *adapter = tx_ring->adapter; 5689 struct e1000_tx_desc *tx_desc = NULL; 5690 struct e1000_buffer *buffer_info; 5691 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5692 unsigned int i; 5693 5694 if (tx_flags & E1000_TX_FLAGS_TSO) { 5695 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5696 E1000_TXD_CMD_TSE; 5697 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5698 5699 if (tx_flags & E1000_TX_FLAGS_IPV4) 5700 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5701 } 5702 5703 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5704 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5705 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5706 } 5707 5708 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5709 txd_lower |= E1000_TXD_CMD_VLE; 5710 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5711 } 5712 5713 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5714 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5715 5716 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5717 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5718 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5719 } 5720 5721 i = tx_ring->next_to_use; 5722 5723 do { 5724 buffer_info = &tx_ring->buffer_info[i]; 5725 tx_desc = E1000_TX_DESC(*tx_ring, i); 5726 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5727 tx_desc->lower.data = cpu_to_le32(txd_lower | 5728 buffer_info->length); 5729 tx_desc->upper.data = cpu_to_le32(txd_upper); 5730 5731 i++; 5732 if (i == tx_ring->count) 5733 i = 0; 5734 } while (--count > 0); 5735 5736 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5737 5738 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5739 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5740 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5741 5742 /* Force memory writes to complete before letting h/w 5743 * know there are new descriptors to fetch. (Only 5744 * applicable for weak-ordered memory model archs, 5745 * such as IA-64). 5746 */ 5747 wmb(); 5748 5749 tx_ring->next_to_use = i; 5750 } 5751 5752 #define MINIMUM_DHCP_PACKET_SIZE 282 5753 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5754 struct sk_buff *skb) 5755 { 5756 struct e1000_hw *hw = &adapter->hw; 5757 u16 length, offset; 5758 5759 if (skb_vlan_tag_present(skb) && 5760 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5761 (adapter->hw.mng_cookie.status & 5762 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5763 return 0; 5764 5765 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5766 return 0; 5767 5768 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5769 return 0; 5770 5771 { 5772 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5773 struct udphdr *udp; 5774 5775 if (ip->protocol != IPPROTO_UDP) 5776 return 0; 5777 5778 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5779 if (ntohs(udp->dest) != 67) 5780 return 0; 5781 5782 offset = (u8 *)udp + 8 - skb->data; 5783 length = skb->len - offset; 5784 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5785 } 5786 5787 return 0; 5788 } 5789 5790 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5791 { 5792 struct e1000_adapter *adapter = tx_ring->adapter; 5793 5794 netif_stop_queue(adapter->netdev); 5795 /* Herbert's original patch had: 5796 * smp_mb__after_netif_stop_queue(); 5797 * but since that doesn't exist yet, just open code it. 5798 */ 5799 smp_mb(); 5800 5801 /* We need to check again in a case another CPU has just 5802 * made room available. 5803 */ 5804 if (e1000_desc_unused(tx_ring) < size) 5805 return -EBUSY; 5806 5807 /* A reprieve! */ 5808 netif_start_queue(adapter->netdev); 5809 ++adapter->restart_queue; 5810 return 0; 5811 } 5812 5813 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5814 { 5815 BUG_ON(size > tx_ring->count); 5816 5817 if (e1000_desc_unused(tx_ring) >= size) 5818 return 0; 5819 return __e1000_maybe_stop_tx(tx_ring, size); 5820 } 5821 5822 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5823 struct net_device *netdev) 5824 { 5825 struct e1000_adapter *adapter = netdev_priv(netdev); 5826 struct e1000_ring *tx_ring = adapter->tx_ring; 5827 unsigned int first; 5828 unsigned int tx_flags = 0; 5829 unsigned int len = skb_headlen(skb); 5830 unsigned int nr_frags; 5831 unsigned int mss; 5832 int count = 0; 5833 int tso; 5834 unsigned int f; 5835 __be16 protocol = vlan_get_protocol(skb); 5836 5837 if (test_bit(__E1000_DOWN, &adapter->state)) { 5838 dev_kfree_skb_any(skb); 5839 return NETDEV_TX_OK; 5840 } 5841 5842 if (skb->len <= 0) { 5843 dev_kfree_skb_any(skb); 5844 return NETDEV_TX_OK; 5845 } 5846 5847 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5848 * pad skb in order to meet this minimum size requirement 5849 */ 5850 if (skb_put_padto(skb, 17)) 5851 return NETDEV_TX_OK; 5852 5853 mss = skb_shinfo(skb)->gso_size; 5854 if (mss) { 5855 u8 hdr_len; 5856 5857 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5858 * points to just header, pull a few bytes of payload from 5859 * frags into skb->data 5860 */ 5861 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5862 /* we do this workaround for ES2LAN, but it is un-necessary, 5863 * avoiding it could save a lot of cycles 5864 */ 5865 if (skb->data_len && (hdr_len == len)) { 5866 unsigned int pull_size; 5867 5868 pull_size = min_t(unsigned int, 4, skb->data_len); 5869 if (!__pskb_pull_tail(skb, pull_size)) { 5870 e_err("__pskb_pull_tail failed.\n"); 5871 dev_kfree_skb_any(skb); 5872 return NETDEV_TX_OK; 5873 } 5874 len = skb_headlen(skb); 5875 } 5876 } 5877 5878 /* reserve a descriptor for the offload context */ 5879 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5880 count++; 5881 count++; 5882 5883 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5884 5885 nr_frags = skb_shinfo(skb)->nr_frags; 5886 for (f = 0; f < nr_frags; f++) 5887 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5888 adapter->tx_fifo_limit); 5889 5890 if (adapter->hw.mac.tx_pkt_filtering) 5891 e1000_transfer_dhcp_info(adapter, skb); 5892 5893 /* need: count + 2 desc gap to keep tail from touching 5894 * head, otherwise try next time 5895 */ 5896 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5897 return NETDEV_TX_BUSY; 5898 5899 if (skb_vlan_tag_present(skb)) { 5900 tx_flags |= E1000_TX_FLAGS_VLAN; 5901 tx_flags |= (skb_vlan_tag_get(skb) << 5902 E1000_TX_FLAGS_VLAN_SHIFT); 5903 } 5904 5905 first = tx_ring->next_to_use; 5906 5907 tso = e1000_tso(tx_ring, skb, protocol); 5908 if (tso < 0) { 5909 dev_kfree_skb_any(skb); 5910 return NETDEV_TX_OK; 5911 } 5912 5913 if (tso) 5914 tx_flags |= E1000_TX_FLAGS_TSO; 5915 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5916 tx_flags |= E1000_TX_FLAGS_CSUM; 5917 5918 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5919 * 82571 hardware supports TSO capabilities for IPv6 as well... 5920 * no longer assume, we must. 5921 */ 5922 if (protocol == htons(ETH_P_IP)) 5923 tx_flags |= E1000_TX_FLAGS_IPV4; 5924 5925 if (unlikely(skb->no_fcs)) 5926 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5927 5928 /* if count is 0 then mapping error has occurred */ 5929 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5930 nr_frags); 5931 if (count) { 5932 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5933 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5934 if (!adapter->tx_hwtstamp_skb) { 5935 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5936 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5937 adapter->tx_hwtstamp_skb = skb_get(skb); 5938 adapter->tx_hwtstamp_start = jiffies; 5939 schedule_work(&adapter->tx_hwtstamp_work); 5940 } else { 5941 adapter->tx_hwtstamp_skipped++; 5942 } 5943 } 5944 5945 skb_tx_timestamp(skb); 5946 5947 netdev_sent_queue(netdev, skb->len); 5948 e1000_tx_queue(tx_ring, tx_flags, count); 5949 /* Make sure there is space in the ring for the next send. */ 5950 e1000_maybe_stop_tx(tx_ring, 5951 (MAX_SKB_FRAGS * 5952 DIV_ROUND_UP(PAGE_SIZE, 5953 adapter->tx_fifo_limit) + 2)); 5954 5955 if (!netdev_xmit_more() || 5956 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5957 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5958 e1000e_update_tdt_wa(tx_ring, 5959 tx_ring->next_to_use); 5960 else 5961 writel(tx_ring->next_to_use, tx_ring->tail); 5962 } 5963 } else { 5964 dev_kfree_skb_any(skb); 5965 tx_ring->buffer_info[first].time_stamp = 0; 5966 tx_ring->next_to_use = first; 5967 } 5968 5969 return NETDEV_TX_OK; 5970 } 5971 5972 /** 5973 * e1000_tx_timeout - Respond to a Tx Hang 5974 * @netdev: network interface device structure 5975 **/ 5976 static void e1000_tx_timeout(struct net_device *netdev, unsigned int txqueue) 5977 { 5978 struct e1000_adapter *adapter = netdev_priv(netdev); 5979 5980 /* Do the reset outside of interrupt context */ 5981 adapter->tx_timeout_count++; 5982 schedule_work(&adapter->reset_task); 5983 } 5984 5985 static void e1000_reset_task(struct work_struct *work) 5986 { 5987 struct e1000_adapter *adapter; 5988 adapter = container_of(work, struct e1000_adapter, reset_task); 5989 5990 /* don't run the task if already down */ 5991 if (test_bit(__E1000_DOWN, &adapter->state)) 5992 return; 5993 5994 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5995 e1000e_dump(adapter); 5996 e_err("Reset adapter unexpectedly\n"); 5997 } 5998 e1000e_reinit_locked(adapter); 5999 } 6000 6001 /** 6002 * e1000_get_stats64 - Get System Network Statistics 6003 * @netdev: network interface device structure 6004 * @stats: rtnl_link_stats64 pointer 6005 * 6006 * Returns the address of the device statistics structure. 6007 **/ 6008 void e1000e_get_stats64(struct net_device *netdev, 6009 struct rtnl_link_stats64 *stats) 6010 { 6011 struct e1000_adapter *adapter = netdev_priv(netdev); 6012 6013 spin_lock(&adapter->stats64_lock); 6014 e1000e_update_stats(adapter); 6015 /* Fill out the OS statistics structure */ 6016 stats->rx_bytes = adapter->stats.gorc; 6017 stats->rx_packets = adapter->stats.gprc; 6018 stats->tx_bytes = adapter->stats.gotc; 6019 stats->tx_packets = adapter->stats.gptc; 6020 stats->multicast = adapter->stats.mprc; 6021 stats->collisions = adapter->stats.colc; 6022 6023 /* Rx Errors */ 6024 6025 /* RLEC on some newer hardware can be incorrect so build 6026 * our own version based on RUC and ROC 6027 */ 6028 stats->rx_errors = adapter->stats.rxerrc + 6029 adapter->stats.crcerrs + adapter->stats.algnerrc + 6030 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 6031 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 6032 stats->rx_crc_errors = adapter->stats.crcerrs; 6033 stats->rx_frame_errors = adapter->stats.algnerrc; 6034 stats->rx_missed_errors = adapter->stats.mpc; 6035 6036 /* Tx Errors */ 6037 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6038 stats->tx_aborted_errors = adapter->stats.ecol; 6039 stats->tx_window_errors = adapter->stats.latecol; 6040 stats->tx_carrier_errors = adapter->stats.tncrs; 6041 6042 /* Tx Dropped needs to be maintained elsewhere */ 6043 6044 spin_unlock(&adapter->stats64_lock); 6045 } 6046 6047 /** 6048 * e1000_change_mtu - Change the Maximum Transfer Unit 6049 * @netdev: network interface device structure 6050 * @new_mtu: new value for maximum frame size 6051 * 6052 * Returns 0 on success, negative on failure 6053 **/ 6054 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6055 { 6056 struct e1000_adapter *adapter = netdev_priv(netdev); 6057 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6058 6059 /* Jumbo frame support */ 6060 if ((new_mtu > ETH_DATA_LEN) && 6061 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6062 e_err("Jumbo Frames not supported.\n"); 6063 return -EINVAL; 6064 } 6065 6066 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6067 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6068 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6069 (new_mtu > ETH_DATA_LEN)) { 6070 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6071 return -EINVAL; 6072 } 6073 6074 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6075 usleep_range(1000, 1100); 6076 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6077 adapter->max_frame_size = max_frame; 6078 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6079 netdev->mtu, new_mtu); 6080 netdev->mtu = new_mtu; 6081 6082 pm_runtime_get_sync(netdev->dev.parent); 6083 6084 if (netif_running(netdev)) 6085 e1000e_down(adapter, true); 6086 6087 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6088 * means we reserve 2 more, this pushes us to allocate from the next 6089 * larger slab size. 6090 * i.e. RXBUFFER_2048 --> size-4096 slab 6091 * However with the new *_jumbo_rx* routines, jumbo receives will use 6092 * fragmented skbs 6093 */ 6094 6095 if (max_frame <= 2048) 6096 adapter->rx_buffer_len = 2048; 6097 else 6098 adapter->rx_buffer_len = 4096; 6099 6100 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6101 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6102 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6103 6104 if (netif_running(netdev)) 6105 e1000e_up(adapter); 6106 else 6107 e1000e_reset(adapter); 6108 6109 pm_runtime_put_sync(netdev->dev.parent); 6110 6111 clear_bit(__E1000_RESETTING, &adapter->state); 6112 6113 return 0; 6114 } 6115 6116 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6117 int cmd) 6118 { 6119 struct e1000_adapter *adapter = netdev_priv(netdev); 6120 struct mii_ioctl_data *data = if_mii(ifr); 6121 6122 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6123 return -EOPNOTSUPP; 6124 6125 switch (cmd) { 6126 case SIOCGMIIPHY: 6127 data->phy_id = adapter->hw.phy.addr; 6128 break; 6129 case SIOCGMIIREG: 6130 e1000_phy_read_status(adapter); 6131 6132 switch (data->reg_num & 0x1F) { 6133 case MII_BMCR: 6134 data->val_out = adapter->phy_regs.bmcr; 6135 break; 6136 case MII_BMSR: 6137 data->val_out = adapter->phy_regs.bmsr; 6138 break; 6139 case MII_PHYSID1: 6140 data->val_out = (adapter->hw.phy.id >> 16); 6141 break; 6142 case MII_PHYSID2: 6143 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6144 break; 6145 case MII_ADVERTISE: 6146 data->val_out = adapter->phy_regs.advertise; 6147 break; 6148 case MII_LPA: 6149 data->val_out = adapter->phy_regs.lpa; 6150 break; 6151 case MII_EXPANSION: 6152 data->val_out = adapter->phy_regs.expansion; 6153 break; 6154 case MII_CTRL1000: 6155 data->val_out = adapter->phy_regs.ctrl1000; 6156 break; 6157 case MII_STAT1000: 6158 data->val_out = adapter->phy_regs.stat1000; 6159 break; 6160 case MII_ESTATUS: 6161 data->val_out = adapter->phy_regs.estatus; 6162 break; 6163 default: 6164 return -EIO; 6165 } 6166 break; 6167 case SIOCSMIIREG: 6168 default: 6169 return -EOPNOTSUPP; 6170 } 6171 return 0; 6172 } 6173 6174 /** 6175 * e1000e_hwtstamp_ioctl - control hardware time stamping 6176 * @netdev: network interface device structure 6177 * @ifreq: interface request 6178 * 6179 * Outgoing time stamping can be enabled and disabled. Play nice and 6180 * disable it when requested, although it shouldn't cause any overhead 6181 * when no packet needs it. At most one packet in the queue may be 6182 * marked for time stamping, otherwise it would be impossible to tell 6183 * for sure to which packet the hardware time stamp belongs. 6184 * 6185 * Incoming time stamping has to be configured via the hardware filters. 6186 * Not all combinations are supported, in particular event type has to be 6187 * specified. Matching the kind of event packet is not supported, with the 6188 * exception of "all V2 events regardless of level 2 or 4". 6189 **/ 6190 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6191 { 6192 struct e1000_adapter *adapter = netdev_priv(netdev); 6193 struct hwtstamp_config config; 6194 int ret_val; 6195 6196 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6197 return -EFAULT; 6198 6199 ret_val = e1000e_config_hwtstamp(adapter, &config); 6200 if (ret_val) 6201 return ret_val; 6202 6203 switch (config.rx_filter) { 6204 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6205 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6206 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6207 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6208 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6209 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6210 /* With V2 type filters which specify a Sync or Delay Request, 6211 * Path Delay Request/Response messages are also time stamped 6212 * by hardware so notify the caller the requested packets plus 6213 * some others are time stamped. 6214 */ 6215 config.rx_filter = HWTSTAMP_FILTER_SOME; 6216 break; 6217 default: 6218 break; 6219 } 6220 6221 return copy_to_user(ifr->ifr_data, &config, 6222 sizeof(config)) ? -EFAULT : 0; 6223 } 6224 6225 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6226 { 6227 struct e1000_adapter *adapter = netdev_priv(netdev); 6228 6229 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6230 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6231 } 6232 6233 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6234 { 6235 switch (cmd) { 6236 case SIOCGMIIPHY: 6237 case SIOCGMIIREG: 6238 case SIOCSMIIREG: 6239 return e1000_mii_ioctl(netdev, ifr, cmd); 6240 case SIOCSHWTSTAMP: 6241 return e1000e_hwtstamp_set(netdev, ifr); 6242 case SIOCGHWTSTAMP: 6243 return e1000e_hwtstamp_get(netdev, ifr); 6244 default: 6245 return -EOPNOTSUPP; 6246 } 6247 } 6248 6249 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6250 { 6251 struct e1000_hw *hw = &adapter->hw; 6252 u32 i, mac_reg, wuc; 6253 u16 phy_reg, wuc_enable; 6254 int retval; 6255 6256 /* copy MAC RARs to PHY RARs */ 6257 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6258 6259 retval = hw->phy.ops.acquire(hw); 6260 if (retval) { 6261 e_err("Could not acquire PHY\n"); 6262 return retval; 6263 } 6264 6265 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6266 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6267 if (retval) 6268 goto release; 6269 6270 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6271 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6272 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6273 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6274 (u16)(mac_reg & 0xFFFF)); 6275 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6276 (u16)((mac_reg >> 16) & 0xFFFF)); 6277 } 6278 6279 /* configure PHY Rx Control register */ 6280 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6281 mac_reg = er32(RCTL); 6282 if (mac_reg & E1000_RCTL_UPE) 6283 phy_reg |= BM_RCTL_UPE; 6284 if (mac_reg & E1000_RCTL_MPE) 6285 phy_reg |= BM_RCTL_MPE; 6286 phy_reg &= ~(BM_RCTL_MO_MASK); 6287 if (mac_reg & E1000_RCTL_MO_3) 6288 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6289 << BM_RCTL_MO_SHIFT); 6290 if (mac_reg & E1000_RCTL_BAM) 6291 phy_reg |= BM_RCTL_BAM; 6292 if (mac_reg & E1000_RCTL_PMCF) 6293 phy_reg |= BM_RCTL_PMCF; 6294 mac_reg = er32(CTRL); 6295 if (mac_reg & E1000_CTRL_RFCE) 6296 phy_reg |= BM_RCTL_RFCE; 6297 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6298 6299 wuc = E1000_WUC_PME_EN; 6300 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6301 wuc |= E1000_WUC_APME; 6302 6303 /* enable PHY wakeup in MAC register */ 6304 ew32(WUFC, wufc); 6305 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6306 E1000_WUC_PME_STATUS | wuc)); 6307 6308 /* configure and enable PHY wakeup in PHY registers */ 6309 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6310 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6311 6312 /* activate PHY wakeup */ 6313 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6314 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6315 if (retval) 6316 e_err("Could not set PHY Host Wakeup bit\n"); 6317 release: 6318 hw->phy.ops.release(hw); 6319 6320 return retval; 6321 } 6322 6323 static void e1000e_flush_lpic(struct pci_dev *pdev) 6324 { 6325 struct net_device *netdev = pci_get_drvdata(pdev); 6326 struct e1000_adapter *adapter = netdev_priv(netdev); 6327 struct e1000_hw *hw = &adapter->hw; 6328 u32 ret_val; 6329 6330 pm_runtime_get_sync(netdev->dev.parent); 6331 6332 ret_val = hw->phy.ops.acquire(hw); 6333 if (ret_val) 6334 goto fl_out; 6335 6336 pr_info("EEE TX LPI TIMER: %08X\n", 6337 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6338 6339 hw->phy.ops.release(hw); 6340 6341 fl_out: 6342 pm_runtime_put_sync(netdev->dev.parent); 6343 } 6344 6345 /* S0ix implementation */ 6346 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter) 6347 { 6348 struct e1000_hw *hw = &adapter->hw; 6349 u32 mac_data; 6350 u16 phy_data; 6351 6352 /* Disable the periodic inband message, 6353 * don't request PCIe clock in K1 page770_17[10:9] = 10b 6354 */ 6355 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6356 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ; 6357 phy_data |= BIT(10); 6358 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6359 6360 /* Make sure we don't exit K1 every time a new packet arrives 6361 * 772_29[5] = 1 CS_Mode_Stay_In_K1 6362 */ 6363 e1e_rphy(hw, I217_CGFREG, &phy_data); 6364 phy_data |= BIT(5); 6365 e1e_wphy(hw, I217_CGFREG, phy_data); 6366 6367 /* Change the MAC/PHY interface to SMBus 6368 * Force the SMBus in PHY page769_23[0] = 1 6369 * Force the SMBus in MAC CTRL_EXT[11] = 1 6370 */ 6371 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6372 phy_data |= CV_SMB_CTRL_FORCE_SMBUS; 6373 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6374 mac_data = er32(CTRL_EXT); 6375 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS; 6376 ew32(CTRL_EXT, mac_data); 6377 6378 /* DFT control: PHY bit: page769_20[0] = 1 6379 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 6380 */ 6381 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data); 6382 phy_data |= BIT(0); 6383 e1e_wphy(hw, I82579_DFT_CTRL, phy_data); 6384 6385 mac_data = er32(EXTCNF_CTRL); 6386 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 6387 ew32(EXTCNF_CTRL, mac_data); 6388 6389 /* Check MAC Tx/Rx packet buffer pointers. 6390 * Reset MAC Tx/Rx packet buffer pointers to suppress any 6391 * pending traffic indication that would prevent power gating. 6392 */ 6393 mac_data = er32(TDFH); 6394 if (mac_data) 6395 ew32(TDFH, 0); 6396 mac_data = er32(TDFT); 6397 if (mac_data) 6398 ew32(TDFT, 0); 6399 mac_data = er32(TDFHS); 6400 if (mac_data) 6401 ew32(TDFHS, 0); 6402 mac_data = er32(TDFTS); 6403 if (mac_data) 6404 ew32(TDFTS, 0); 6405 mac_data = er32(TDFPC); 6406 if (mac_data) 6407 ew32(TDFPC, 0); 6408 mac_data = er32(RDFH); 6409 if (mac_data) 6410 ew32(RDFH, 0); 6411 mac_data = er32(RDFT); 6412 if (mac_data) 6413 ew32(RDFT, 0); 6414 mac_data = er32(RDFHS); 6415 if (mac_data) 6416 ew32(RDFHS, 0); 6417 mac_data = er32(RDFTS); 6418 if (mac_data) 6419 ew32(RDFTS, 0); 6420 mac_data = er32(RDFPC); 6421 if (mac_data) 6422 ew32(RDFPC, 0); 6423 6424 /* Enable the Dynamic Power Gating in the MAC */ 6425 mac_data = er32(FEXTNVM7); 6426 mac_data |= BIT(22); 6427 ew32(FEXTNVM7, mac_data); 6428 6429 /* Disable the time synchronization clock */ 6430 mac_data = er32(FEXTNVM7); 6431 mac_data |= BIT(31); 6432 mac_data &= ~BIT(0); 6433 ew32(FEXTNVM7, mac_data); 6434 6435 /* Dynamic Power Gating Enable */ 6436 mac_data = er32(CTRL_EXT); 6437 mac_data |= BIT(3); 6438 ew32(CTRL_EXT, mac_data); 6439 6440 /* Disable disconnected cable conditioning for Power Gating */ 6441 mac_data = er32(DPGFR); 6442 mac_data |= BIT(2); 6443 ew32(DPGFR, mac_data); 6444 6445 /* Don't wake from dynamic Power Gating with clock request */ 6446 mac_data = er32(FEXTNVM12); 6447 mac_data |= BIT(12); 6448 ew32(FEXTNVM12, mac_data); 6449 6450 /* Ungate PGCB clock */ 6451 mac_data = er32(FEXTNVM9); 6452 mac_data |= BIT(28); 6453 ew32(FEXTNVM9, mac_data); 6454 6455 /* Enable K1 off to enable mPHY Power Gating */ 6456 mac_data = er32(FEXTNVM6); 6457 mac_data |= BIT(31); 6458 ew32(FEXTNVM12, mac_data); 6459 6460 /* Enable mPHY power gating for any link and speed */ 6461 mac_data = er32(FEXTNVM8); 6462 mac_data |= BIT(9); 6463 ew32(FEXTNVM8, mac_data); 6464 6465 /* Enable the Dynamic Clock Gating in the DMA and MAC */ 6466 mac_data = er32(CTRL_EXT); 6467 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN; 6468 ew32(CTRL_EXT, mac_data); 6469 6470 /* No MAC DPG gating SLP_S0 in modern standby 6471 * Switch the logic of the lanphypc to use PMC counter 6472 */ 6473 mac_data = er32(FEXTNVM5); 6474 mac_data |= BIT(7); 6475 ew32(FEXTNVM5, mac_data); 6476 } 6477 6478 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter) 6479 { 6480 struct e1000_hw *hw = &adapter->hw; 6481 u32 mac_data; 6482 u16 phy_data; 6483 6484 /* Disable the Dynamic Power Gating in the MAC */ 6485 mac_data = er32(FEXTNVM7); 6486 mac_data &= 0xFFBFFFFF; 6487 ew32(FEXTNVM7, mac_data); 6488 6489 /* Enable the time synchronization clock */ 6490 mac_data = er32(FEXTNVM7); 6491 mac_data |= BIT(0); 6492 ew32(FEXTNVM7, mac_data); 6493 6494 /* Disable mPHY power gating for any link and speed */ 6495 mac_data = er32(FEXTNVM8); 6496 mac_data &= ~BIT(9); 6497 ew32(FEXTNVM8, mac_data); 6498 6499 /* Disable K1 off */ 6500 mac_data = er32(FEXTNVM6); 6501 mac_data &= ~BIT(31); 6502 ew32(FEXTNVM12, mac_data); 6503 6504 /* Disable Ungate PGCB clock */ 6505 mac_data = er32(FEXTNVM9); 6506 mac_data &= ~BIT(28); 6507 ew32(FEXTNVM9, mac_data); 6508 6509 /* Cancel not waking from dynamic 6510 * Power Gating with clock request 6511 */ 6512 mac_data = er32(FEXTNVM12); 6513 mac_data &= ~BIT(12); 6514 ew32(FEXTNVM12, mac_data); 6515 6516 /* Cancel disable disconnected cable conditioning 6517 * for Power Gating 6518 */ 6519 mac_data = er32(DPGFR); 6520 mac_data &= ~BIT(2); 6521 ew32(DPGFR, mac_data); 6522 6523 /* Disable Dynamic Power Gating */ 6524 mac_data = er32(CTRL_EXT); 6525 mac_data &= 0xFFFFFFF7; 6526 ew32(CTRL_EXT, mac_data); 6527 6528 /* Disable the Dynamic Clock Gating in the DMA and MAC */ 6529 mac_data = er32(CTRL_EXT); 6530 mac_data &= 0xFFF7FFFF; 6531 ew32(CTRL_EXT, mac_data); 6532 6533 /* Revert the lanphypc logic to use the internal Gbe counter 6534 * and not the PMC counter 6535 */ 6536 mac_data = er32(FEXTNVM5); 6537 mac_data &= 0xFFFFFF7F; 6538 ew32(FEXTNVM5, mac_data); 6539 6540 /* Enable the periodic inband message, 6541 * Request PCIe clock in K1 page770_17[10:9] =01b 6542 */ 6543 e1e_rphy(hw, HV_PM_CTRL, &phy_data); 6544 phy_data &= 0xFBFF; 6545 phy_data |= HV_PM_CTRL_K1_CLK_REQ; 6546 e1e_wphy(hw, HV_PM_CTRL, phy_data); 6547 6548 /* Return back configuration 6549 * 772_29[5] = 0 CS_Mode_Stay_In_K1 6550 */ 6551 e1e_rphy(hw, I217_CGFREG, &phy_data); 6552 phy_data &= 0xFFDF; 6553 e1e_wphy(hw, I217_CGFREG, phy_data); 6554 6555 /* Change the MAC/PHY interface to Kumeran 6556 * Unforce the SMBus in PHY page769_23[0] = 0 6557 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 6558 */ 6559 e1e_rphy(hw, CV_SMB_CTRL, &phy_data); 6560 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS; 6561 e1e_wphy(hw, CV_SMB_CTRL, phy_data); 6562 mac_data = er32(CTRL_EXT); 6563 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS; 6564 ew32(CTRL_EXT, mac_data); 6565 } 6566 6567 static int e1000e_pm_freeze(struct device *dev) 6568 { 6569 struct net_device *netdev = dev_get_drvdata(dev); 6570 struct e1000_adapter *adapter = netdev_priv(netdev); 6571 bool present; 6572 6573 rtnl_lock(); 6574 6575 present = netif_device_present(netdev); 6576 netif_device_detach(netdev); 6577 6578 if (present && netif_running(netdev)) { 6579 int count = E1000_CHECK_RESET_COUNT; 6580 6581 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6582 usleep_range(10000, 11000); 6583 6584 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6585 6586 /* Quiesce the device without resetting the hardware */ 6587 e1000e_down(adapter, false); 6588 e1000_free_irq(adapter); 6589 } 6590 rtnl_unlock(); 6591 6592 e1000e_reset_interrupt_capability(adapter); 6593 6594 /* Allow time for pending master requests to run */ 6595 e1000e_disable_pcie_master(&adapter->hw); 6596 6597 return 0; 6598 } 6599 6600 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6601 { 6602 struct net_device *netdev = pci_get_drvdata(pdev); 6603 struct e1000_adapter *adapter = netdev_priv(netdev); 6604 struct e1000_hw *hw = &adapter->hw; 6605 u32 ctrl, ctrl_ext, rctl, status, wufc; 6606 int retval = 0; 6607 6608 /* Runtime suspend should only enable wakeup for link changes */ 6609 if (runtime) 6610 wufc = E1000_WUFC_LNKC; 6611 else if (device_may_wakeup(&pdev->dev)) 6612 wufc = adapter->wol; 6613 else 6614 wufc = 0; 6615 6616 status = er32(STATUS); 6617 if (status & E1000_STATUS_LU) 6618 wufc &= ~E1000_WUFC_LNKC; 6619 6620 if (wufc) { 6621 e1000_setup_rctl(adapter); 6622 e1000e_set_rx_mode(netdev); 6623 6624 /* turn on all-multi mode if wake on multicast is enabled */ 6625 if (wufc & E1000_WUFC_MC) { 6626 rctl = er32(RCTL); 6627 rctl |= E1000_RCTL_MPE; 6628 ew32(RCTL, rctl); 6629 } 6630 6631 ctrl = er32(CTRL); 6632 ctrl |= E1000_CTRL_ADVD3WUC; 6633 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6634 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6635 ew32(CTRL, ctrl); 6636 6637 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6638 adapter->hw.phy.media_type == 6639 e1000_media_type_internal_serdes) { 6640 /* keep the laser running in D3 */ 6641 ctrl_ext = er32(CTRL_EXT); 6642 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6643 ew32(CTRL_EXT, ctrl_ext); 6644 } 6645 6646 if (!runtime) 6647 e1000e_power_up_phy(adapter); 6648 6649 if (adapter->flags & FLAG_IS_ICH) 6650 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6651 6652 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6653 /* enable wakeup by the PHY */ 6654 retval = e1000_init_phy_wakeup(adapter, wufc); 6655 if (retval) 6656 return retval; 6657 } else { 6658 /* enable wakeup by the MAC */ 6659 ew32(WUFC, wufc); 6660 ew32(WUC, E1000_WUC_PME_EN); 6661 } 6662 } else { 6663 ew32(WUC, 0); 6664 ew32(WUFC, 0); 6665 6666 e1000_power_down_phy(adapter); 6667 } 6668 6669 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6670 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6671 } else if (hw->mac.type >= e1000_pch_lpt) { 6672 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6673 /* ULP does not support wake from unicast, multicast 6674 * or broadcast. 6675 */ 6676 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6677 6678 if (retval) 6679 return retval; 6680 } 6681 6682 /* Ensure that the appropriate bits are set in LPI_CTRL 6683 * for EEE in Sx 6684 */ 6685 if ((hw->phy.type >= e1000_phy_i217) && 6686 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6687 u16 lpi_ctrl = 0; 6688 6689 retval = hw->phy.ops.acquire(hw); 6690 if (!retval) { 6691 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6692 &lpi_ctrl); 6693 if (!retval) { 6694 if (adapter->eee_advert & 6695 hw->dev_spec.ich8lan.eee_lp_ability & 6696 I82579_EEE_100_SUPPORTED) 6697 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6698 if (adapter->eee_advert & 6699 hw->dev_spec.ich8lan.eee_lp_ability & 6700 I82579_EEE_1000_SUPPORTED) 6701 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6702 6703 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6704 lpi_ctrl); 6705 } 6706 } 6707 hw->phy.ops.release(hw); 6708 } 6709 6710 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6711 * would have already happened in close and is redundant. 6712 */ 6713 e1000e_release_hw_control(adapter); 6714 6715 pci_clear_master(pdev); 6716 6717 /* The pci-e switch on some quad port adapters will report a 6718 * correctable error when the MAC transitions from D0 to D3. To 6719 * prevent this we need to mask off the correctable errors on the 6720 * downstream port of the pci-e switch. 6721 * 6722 * We don't have the associated upstream bridge while assigning 6723 * the PCI device into guest. For example, the KVM on power is 6724 * one of the cases. 6725 */ 6726 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6727 struct pci_dev *us_dev = pdev->bus->self; 6728 u16 devctl; 6729 6730 if (!us_dev) 6731 return 0; 6732 6733 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6734 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6735 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6736 6737 pci_save_state(pdev); 6738 pci_prepare_to_sleep(pdev); 6739 6740 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6741 } 6742 6743 return 0; 6744 } 6745 6746 /** 6747 * __e1000e_disable_aspm - Disable ASPM states 6748 * @pdev: pointer to PCI device struct 6749 * @state: bit-mask of ASPM states to disable 6750 * @locked: indication if this context holds pci_bus_sem locked. 6751 * 6752 * Some devices *must* have certain ASPM states disabled per hardware errata. 6753 **/ 6754 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6755 { 6756 struct pci_dev *parent = pdev->bus->self; 6757 u16 aspm_dis_mask = 0; 6758 u16 pdev_aspmc, parent_aspmc; 6759 6760 switch (state) { 6761 case PCIE_LINK_STATE_L0S: 6762 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6763 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6764 fallthrough; /* can't have L1 without L0s */ 6765 case PCIE_LINK_STATE_L1: 6766 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6767 break; 6768 default: 6769 return; 6770 } 6771 6772 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6773 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6774 6775 if (parent) { 6776 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6777 &parent_aspmc); 6778 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6779 } 6780 6781 /* Nothing to do if the ASPM states to be disabled already are */ 6782 if (!(pdev_aspmc & aspm_dis_mask) && 6783 (!parent || !(parent_aspmc & aspm_dis_mask))) 6784 return; 6785 6786 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6787 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6788 "L0s" : "", 6789 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6790 "L1" : ""); 6791 6792 #ifdef CONFIG_PCIEASPM 6793 if (locked) 6794 pci_disable_link_state_locked(pdev, state); 6795 else 6796 pci_disable_link_state(pdev, state); 6797 6798 /* Double-check ASPM control. If not disabled by the above, the 6799 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6800 * not enabled); override by writing PCI config space directly. 6801 */ 6802 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6803 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6804 6805 if (!(aspm_dis_mask & pdev_aspmc)) 6806 return; 6807 #endif 6808 6809 /* Both device and parent should have the same ASPM setting. 6810 * Disable ASPM in downstream component first and then upstream. 6811 */ 6812 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6813 6814 if (parent) 6815 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6816 aspm_dis_mask); 6817 } 6818 6819 /** 6820 * e1000e_disable_aspm - Disable ASPM states. 6821 * @pdev: pointer to PCI device struct 6822 * @state: bit-mask of ASPM states to disable 6823 * 6824 * This function acquires the pci_bus_sem! 6825 * Some devices *must* have certain ASPM states disabled per hardware errata. 6826 **/ 6827 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6828 { 6829 __e1000e_disable_aspm(pdev, state, 0); 6830 } 6831 6832 /** 6833 * e1000e_disable_aspm_locked Disable ASPM states. 6834 * @pdev: pointer to PCI device struct 6835 * @state: bit-mask of ASPM states to disable 6836 * 6837 * This function must be called with pci_bus_sem acquired! 6838 * Some devices *must* have certain ASPM states disabled per hardware errata. 6839 **/ 6840 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6841 { 6842 __e1000e_disable_aspm(pdev, state, 1); 6843 } 6844 6845 static int e1000e_pm_thaw(struct device *dev) 6846 { 6847 struct net_device *netdev = dev_get_drvdata(dev); 6848 struct e1000_adapter *adapter = netdev_priv(netdev); 6849 int rc = 0; 6850 6851 e1000e_set_interrupt_capability(adapter); 6852 6853 rtnl_lock(); 6854 if (netif_running(netdev)) { 6855 rc = e1000_request_irq(adapter); 6856 if (rc) 6857 goto err_irq; 6858 6859 e1000e_up(adapter); 6860 } 6861 6862 netif_device_attach(netdev); 6863 err_irq: 6864 rtnl_unlock(); 6865 6866 return rc; 6867 } 6868 6869 static int __e1000_resume(struct pci_dev *pdev) 6870 { 6871 struct net_device *netdev = pci_get_drvdata(pdev); 6872 struct e1000_adapter *adapter = netdev_priv(netdev); 6873 struct e1000_hw *hw = &adapter->hw; 6874 u16 aspm_disable_flag = 0; 6875 6876 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6877 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6878 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6879 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6880 if (aspm_disable_flag) 6881 e1000e_disable_aspm(pdev, aspm_disable_flag); 6882 6883 pci_set_master(pdev); 6884 6885 if (hw->mac.type >= e1000_pch2lan) 6886 e1000_resume_workarounds_pchlan(&adapter->hw); 6887 6888 e1000e_power_up_phy(adapter); 6889 6890 /* report the system wakeup cause from S3/S4 */ 6891 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6892 u16 phy_data; 6893 6894 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6895 if (phy_data) { 6896 e_info("PHY Wakeup cause - %s\n", 6897 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6898 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6899 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6900 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6901 phy_data & E1000_WUS_LNKC ? 6902 "Link Status Change" : "other"); 6903 } 6904 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6905 } else { 6906 u32 wus = er32(WUS); 6907 6908 if (wus) { 6909 e_info("MAC Wakeup cause - %s\n", 6910 wus & E1000_WUS_EX ? "Unicast Packet" : 6911 wus & E1000_WUS_MC ? "Multicast Packet" : 6912 wus & E1000_WUS_BC ? "Broadcast Packet" : 6913 wus & E1000_WUS_MAG ? "Magic Packet" : 6914 wus & E1000_WUS_LNKC ? "Link Status Change" : 6915 "other"); 6916 } 6917 ew32(WUS, ~0); 6918 } 6919 6920 e1000e_reset(adapter); 6921 6922 e1000_init_manageability_pt(adapter); 6923 6924 /* If the controller has AMT, do not set DRV_LOAD until the interface 6925 * is up. For all other cases, let the f/w know that the h/w is now 6926 * under the control of the driver. 6927 */ 6928 if (!(adapter->flags & FLAG_HAS_AMT)) 6929 e1000e_get_hw_control(adapter); 6930 6931 return 0; 6932 } 6933 6934 static __maybe_unused int e1000e_pm_suspend(struct device *dev) 6935 { 6936 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6937 struct e1000_adapter *adapter = netdev_priv(netdev); 6938 struct pci_dev *pdev = to_pci_dev(dev); 6939 struct e1000_hw *hw = &adapter->hw; 6940 int rc; 6941 6942 e1000e_flush_lpic(pdev); 6943 6944 e1000e_pm_freeze(dev); 6945 6946 rc = __e1000_shutdown(pdev, false); 6947 if (rc) 6948 e1000e_pm_thaw(dev); 6949 6950 /* Introduce S0ix implementation */ 6951 if (hw->mac.type >= e1000_pch_cnp && 6952 !e1000e_check_me(hw->adapter->pdev->device)) 6953 e1000e_s0ix_entry_flow(adapter); 6954 6955 return rc; 6956 } 6957 6958 static __maybe_unused int e1000e_pm_resume(struct device *dev) 6959 { 6960 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6961 struct e1000_adapter *adapter = netdev_priv(netdev); 6962 struct pci_dev *pdev = to_pci_dev(dev); 6963 struct e1000_hw *hw = &adapter->hw; 6964 int rc; 6965 6966 /* Introduce S0ix implementation */ 6967 if (hw->mac.type >= e1000_pch_cnp && 6968 !e1000e_check_me(hw->adapter->pdev->device)) 6969 e1000e_s0ix_exit_flow(adapter); 6970 6971 rc = __e1000_resume(pdev); 6972 if (rc) 6973 return rc; 6974 6975 return e1000e_pm_thaw(dev); 6976 } 6977 6978 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev) 6979 { 6980 struct net_device *netdev = dev_get_drvdata(dev); 6981 struct e1000_adapter *adapter = netdev_priv(netdev); 6982 u16 eee_lp; 6983 6984 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6985 6986 if (!e1000e_has_link(adapter)) { 6987 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6988 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6989 } 6990 6991 return -EBUSY; 6992 } 6993 6994 static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev) 6995 { 6996 struct pci_dev *pdev = to_pci_dev(dev); 6997 struct net_device *netdev = pci_get_drvdata(pdev); 6998 struct e1000_adapter *adapter = netdev_priv(netdev); 6999 int rc; 7000 7001 rc = __e1000_resume(pdev); 7002 if (rc) 7003 return rc; 7004 7005 if (netdev->flags & IFF_UP) 7006 e1000e_up(adapter); 7007 7008 return rc; 7009 } 7010 7011 static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev) 7012 { 7013 struct pci_dev *pdev = to_pci_dev(dev); 7014 struct net_device *netdev = pci_get_drvdata(pdev); 7015 struct e1000_adapter *adapter = netdev_priv(netdev); 7016 7017 if (netdev->flags & IFF_UP) { 7018 int count = E1000_CHECK_RESET_COUNT; 7019 7020 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 7021 usleep_range(10000, 11000); 7022 7023 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 7024 7025 /* Down the device without resetting the hardware */ 7026 e1000e_down(adapter, false); 7027 } 7028 7029 if (__e1000_shutdown(pdev, true)) { 7030 e1000e_pm_runtime_resume(dev); 7031 return -EBUSY; 7032 } 7033 7034 return 0; 7035 } 7036 7037 static void e1000_shutdown(struct pci_dev *pdev) 7038 { 7039 e1000e_flush_lpic(pdev); 7040 7041 e1000e_pm_freeze(&pdev->dev); 7042 7043 __e1000_shutdown(pdev, false); 7044 } 7045 7046 #ifdef CONFIG_NET_POLL_CONTROLLER 7047 7048 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 7049 { 7050 struct net_device *netdev = data; 7051 struct e1000_adapter *adapter = netdev_priv(netdev); 7052 7053 if (adapter->msix_entries) { 7054 int vector, msix_irq; 7055 7056 vector = 0; 7057 msix_irq = adapter->msix_entries[vector].vector; 7058 if (disable_hardirq(msix_irq)) 7059 e1000_intr_msix_rx(msix_irq, netdev); 7060 enable_irq(msix_irq); 7061 7062 vector++; 7063 msix_irq = adapter->msix_entries[vector].vector; 7064 if (disable_hardirq(msix_irq)) 7065 e1000_intr_msix_tx(msix_irq, netdev); 7066 enable_irq(msix_irq); 7067 7068 vector++; 7069 msix_irq = adapter->msix_entries[vector].vector; 7070 if (disable_hardirq(msix_irq)) 7071 e1000_msix_other(msix_irq, netdev); 7072 enable_irq(msix_irq); 7073 } 7074 7075 return IRQ_HANDLED; 7076 } 7077 7078 /** 7079 * e1000_netpoll 7080 * @netdev: network interface device structure 7081 * 7082 * Polling 'interrupt' - used by things like netconsole to send skbs 7083 * without having to re-enable interrupts. It's not called while 7084 * the interrupt routine is executing. 7085 */ 7086 static void e1000_netpoll(struct net_device *netdev) 7087 { 7088 struct e1000_adapter *adapter = netdev_priv(netdev); 7089 7090 switch (adapter->int_mode) { 7091 case E1000E_INT_MODE_MSIX: 7092 e1000_intr_msix(adapter->pdev->irq, netdev); 7093 break; 7094 case E1000E_INT_MODE_MSI: 7095 if (disable_hardirq(adapter->pdev->irq)) 7096 e1000_intr_msi(adapter->pdev->irq, netdev); 7097 enable_irq(adapter->pdev->irq); 7098 break; 7099 default: /* E1000E_INT_MODE_LEGACY */ 7100 if (disable_hardirq(adapter->pdev->irq)) 7101 e1000_intr(adapter->pdev->irq, netdev); 7102 enable_irq(adapter->pdev->irq); 7103 break; 7104 } 7105 } 7106 #endif 7107 7108 /** 7109 * e1000_io_error_detected - called when PCI error is detected 7110 * @pdev: Pointer to PCI device 7111 * @state: The current pci connection state 7112 * 7113 * This function is called after a PCI bus error affecting 7114 * this device has been detected. 7115 */ 7116 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 7117 pci_channel_state_t state) 7118 { 7119 e1000e_pm_freeze(&pdev->dev); 7120 7121 if (state == pci_channel_io_perm_failure) 7122 return PCI_ERS_RESULT_DISCONNECT; 7123 7124 pci_disable_device(pdev); 7125 7126 /* Request a slot slot reset. */ 7127 return PCI_ERS_RESULT_NEED_RESET; 7128 } 7129 7130 /** 7131 * e1000_io_slot_reset - called after the pci bus has been reset. 7132 * @pdev: Pointer to PCI device 7133 * 7134 * Restart the card from scratch, as if from a cold-boot. Implementation 7135 * resembles the first-half of the e1000e_pm_resume routine. 7136 */ 7137 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 7138 { 7139 struct net_device *netdev = pci_get_drvdata(pdev); 7140 struct e1000_adapter *adapter = netdev_priv(netdev); 7141 struct e1000_hw *hw = &adapter->hw; 7142 u16 aspm_disable_flag = 0; 7143 int err; 7144 pci_ers_result_t result; 7145 7146 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 7147 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7148 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 7149 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7150 if (aspm_disable_flag) 7151 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 7152 7153 err = pci_enable_device_mem(pdev); 7154 if (err) { 7155 dev_err(&pdev->dev, 7156 "Cannot re-enable PCI device after reset.\n"); 7157 result = PCI_ERS_RESULT_DISCONNECT; 7158 } else { 7159 pdev->state_saved = true; 7160 pci_restore_state(pdev); 7161 pci_set_master(pdev); 7162 7163 pci_enable_wake(pdev, PCI_D3hot, 0); 7164 pci_enable_wake(pdev, PCI_D3cold, 0); 7165 7166 e1000e_reset(adapter); 7167 ew32(WUS, ~0); 7168 result = PCI_ERS_RESULT_RECOVERED; 7169 } 7170 7171 return result; 7172 } 7173 7174 /** 7175 * e1000_io_resume - called when traffic can start flowing again. 7176 * @pdev: Pointer to PCI device 7177 * 7178 * This callback is called when the error recovery driver tells us that 7179 * its OK to resume normal operation. Implementation resembles the 7180 * second-half of the e1000e_pm_resume routine. 7181 */ 7182 static void e1000_io_resume(struct pci_dev *pdev) 7183 { 7184 struct net_device *netdev = pci_get_drvdata(pdev); 7185 struct e1000_adapter *adapter = netdev_priv(netdev); 7186 7187 e1000_init_manageability_pt(adapter); 7188 7189 e1000e_pm_thaw(&pdev->dev); 7190 7191 /* If the controller has AMT, do not set DRV_LOAD until the interface 7192 * is up. For all other cases, let the f/w know that the h/w is now 7193 * under the control of the driver. 7194 */ 7195 if (!(adapter->flags & FLAG_HAS_AMT)) 7196 e1000e_get_hw_control(adapter); 7197 } 7198 7199 static void e1000_print_device_info(struct e1000_adapter *adapter) 7200 { 7201 struct e1000_hw *hw = &adapter->hw; 7202 struct net_device *netdev = adapter->netdev; 7203 u32 ret_val; 7204 u8 pba_str[E1000_PBANUM_LENGTH]; 7205 7206 /* print bus type/speed/width info */ 7207 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 7208 /* bus width */ 7209 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 7210 "Width x1"), 7211 /* MAC address */ 7212 netdev->dev_addr); 7213 e_info("Intel(R) PRO/%s Network Connection\n", 7214 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 7215 ret_val = e1000_read_pba_string_generic(hw, pba_str, 7216 E1000_PBANUM_LENGTH); 7217 if (ret_val) 7218 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 7219 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 7220 hw->mac.type, hw->phy.type, pba_str); 7221 } 7222 7223 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 7224 { 7225 struct e1000_hw *hw = &adapter->hw; 7226 int ret_val; 7227 u16 buf = 0; 7228 7229 if (hw->mac.type != e1000_82573) 7230 return; 7231 7232 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 7233 le16_to_cpus(&buf); 7234 if (!ret_val && (!(buf & BIT(0)))) { 7235 /* Deep Smart Power Down (DSPD) */ 7236 dev_warn(&adapter->pdev->dev, 7237 "Warning: detected DSPD enabled in EEPROM\n"); 7238 } 7239 } 7240 7241 static netdev_features_t e1000_fix_features(struct net_device *netdev, 7242 netdev_features_t features) 7243 { 7244 struct e1000_adapter *adapter = netdev_priv(netdev); 7245 struct e1000_hw *hw = &adapter->hw; 7246 7247 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 7248 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 7249 features &= ~NETIF_F_RXFCS; 7250 7251 /* Since there is no support for separate Rx/Tx vlan accel 7252 * enable/disable make sure Tx flag is always in same state as Rx. 7253 */ 7254 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7255 features |= NETIF_F_HW_VLAN_CTAG_TX; 7256 else 7257 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 7258 7259 return features; 7260 } 7261 7262 static int e1000_set_features(struct net_device *netdev, 7263 netdev_features_t features) 7264 { 7265 struct e1000_adapter *adapter = netdev_priv(netdev); 7266 netdev_features_t changed = features ^ netdev->features; 7267 7268 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 7269 adapter->flags |= FLAG_TSO_FORCE; 7270 7271 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 7272 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 7273 NETIF_F_RXALL))) 7274 return 0; 7275 7276 if (changed & NETIF_F_RXFCS) { 7277 if (features & NETIF_F_RXFCS) { 7278 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7279 } else { 7280 /* We need to take it back to defaults, which might mean 7281 * stripping is still disabled at the adapter level. 7282 */ 7283 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7284 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7285 else 7286 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7287 } 7288 } 7289 7290 netdev->features = features; 7291 7292 if (netif_running(netdev)) 7293 e1000e_reinit_locked(adapter); 7294 else 7295 e1000e_reset(adapter); 7296 7297 return 1; 7298 } 7299 7300 static const struct net_device_ops e1000e_netdev_ops = { 7301 .ndo_open = e1000e_open, 7302 .ndo_stop = e1000e_close, 7303 .ndo_start_xmit = e1000_xmit_frame, 7304 .ndo_get_stats64 = e1000e_get_stats64, 7305 .ndo_set_rx_mode = e1000e_set_rx_mode, 7306 .ndo_set_mac_address = e1000_set_mac, 7307 .ndo_change_mtu = e1000_change_mtu, 7308 .ndo_do_ioctl = e1000_ioctl, 7309 .ndo_tx_timeout = e1000_tx_timeout, 7310 .ndo_validate_addr = eth_validate_addr, 7311 7312 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7313 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7314 #ifdef CONFIG_NET_POLL_CONTROLLER 7315 .ndo_poll_controller = e1000_netpoll, 7316 #endif 7317 .ndo_set_features = e1000_set_features, 7318 .ndo_fix_features = e1000_fix_features, 7319 .ndo_features_check = passthru_features_check, 7320 }; 7321 7322 /** 7323 * e1000_probe - Device Initialization Routine 7324 * @pdev: PCI device information struct 7325 * @ent: entry in e1000_pci_tbl 7326 * 7327 * Returns 0 on success, negative on failure 7328 * 7329 * e1000_probe initializes an adapter identified by a pci_dev structure. 7330 * The OS initialization, configuring of the adapter private structure, 7331 * and a hardware reset occur. 7332 **/ 7333 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7334 { 7335 struct net_device *netdev; 7336 struct e1000_adapter *adapter; 7337 struct e1000_hw *hw; 7338 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7339 resource_size_t mmio_start, mmio_len; 7340 resource_size_t flash_start, flash_len; 7341 static int cards_found; 7342 u16 aspm_disable_flag = 0; 7343 int bars, i, err, pci_using_dac; 7344 u16 eeprom_data = 0; 7345 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7346 s32 ret_val = 0; 7347 7348 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7349 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7350 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7351 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7352 if (aspm_disable_flag) 7353 e1000e_disable_aspm(pdev, aspm_disable_flag); 7354 7355 err = pci_enable_device_mem(pdev); 7356 if (err) 7357 return err; 7358 7359 pci_using_dac = 0; 7360 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7361 if (!err) { 7362 pci_using_dac = 1; 7363 } else { 7364 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7365 if (err) { 7366 dev_err(&pdev->dev, 7367 "No usable DMA configuration, aborting\n"); 7368 goto err_dma; 7369 } 7370 } 7371 7372 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7373 err = pci_request_selected_regions_exclusive(pdev, bars, 7374 e1000e_driver_name); 7375 if (err) 7376 goto err_pci_reg; 7377 7378 /* AER (Advanced Error Reporting) hooks */ 7379 pci_enable_pcie_error_reporting(pdev); 7380 7381 pci_set_master(pdev); 7382 /* PCI config space info */ 7383 err = pci_save_state(pdev); 7384 if (err) 7385 goto err_alloc_etherdev; 7386 7387 err = -ENOMEM; 7388 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7389 if (!netdev) 7390 goto err_alloc_etherdev; 7391 7392 SET_NETDEV_DEV(netdev, &pdev->dev); 7393 7394 netdev->irq = pdev->irq; 7395 7396 pci_set_drvdata(pdev, netdev); 7397 adapter = netdev_priv(netdev); 7398 hw = &adapter->hw; 7399 adapter->netdev = netdev; 7400 adapter->pdev = pdev; 7401 adapter->ei = ei; 7402 adapter->pba = ei->pba; 7403 adapter->flags = ei->flags; 7404 adapter->flags2 = ei->flags2; 7405 adapter->hw.adapter = adapter; 7406 adapter->hw.mac.type = ei->mac; 7407 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7408 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7409 7410 mmio_start = pci_resource_start(pdev, 0); 7411 mmio_len = pci_resource_len(pdev, 0); 7412 7413 err = -EIO; 7414 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7415 if (!adapter->hw.hw_addr) 7416 goto err_ioremap; 7417 7418 if ((adapter->flags & FLAG_HAS_FLASH) && 7419 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7420 (hw->mac.type < e1000_pch_spt)) { 7421 flash_start = pci_resource_start(pdev, 1); 7422 flash_len = pci_resource_len(pdev, 1); 7423 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7424 if (!adapter->hw.flash_address) 7425 goto err_flashmap; 7426 } 7427 7428 /* Set default EEE advertisement */ 7429 if (adapter->flags2 & FLAG2_HAS_EEE) 7430 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7431 7432 /* construct the net_device struct */ 7433 netdev->netdev_ops = &e1000e_netdev_ops; 7434 e1000e_set_ethtool_ops(netdev); 7435 netdev->watchdog_timeo = 5 * HZ; 7436 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7437 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7438 7439 netdev->mem_start = mmio_start; 7440 netdev->mem_end = mmio_start + mmio_len; 7441 7442 adapter->bd_number = cards_found++; 7443 7444 e1000e_check_options(adapter); 7445 7446 /* setup adapter struct */ 7447 err = e1000_sw_init(adapter); 7448 if (err) 7449 goto err_sw_init; 7450 7451 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7452 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7453 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7454 7455 err = ei->get_variants(adapter); 7456 if (err) 7457 goto err_hw_init; 7458 7459 if ((adapter->flags & FLAG_IS_ICH) && 7460 (adapter->flags & FLAG_READ_ONLY_NVM) && 7461 (hw->mac.type < e1000_pch_spt)) 7462 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7463 7464 hw->mac.ops.get_bus_info(&adapter->hw); 7465 7466 adapter->hw.phy.autoneg_wait_to_complete = 0; 7467 7468 /* Copper options */ 7469 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7470 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7471 adapter->hw.phy.disable_polarity_correction = 0; 7472 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7473 } 7474 7475 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7476 dev_info(&pdev->dev, 7477 "PHY reset is blocked due to SOL/IDER session.\n"); 7478 7479 /* Set initial default active device features */ 7480 netdev->features = (NETIF_F_SG | 7481 NETIF_F_HW_VLAN_CTAG_RX | 7482 NETIF_F_HW_VLAN_CTAG_TX | 7483 NETIF_F_TSO | 7484 NETIF_F_TSO6 | 7485 NETIF_F_RXHASH | 7486 NETIF_F_RXCSUM | 7487 NETIF_F_HW_CSUM); 7488 7489 /* Set user-changeable features (subset of all device features) */ 7490 netdev->hw_features = netdev->features; 7491 netdev->hw_features |= NETIF_F_RXFCS; 7492 netdev->priv_flags |= IFF_SUPP_NOFCS; 7493 netdev->hw_features |= NETIF_F_RXALL; 7494 7495 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7496 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7497 7498 netdev->vlan_features |= (NETIF_F_SG | 7499 NETIF_F_TSO | 7500 NETIF_F_TSO6 | 7501 NETIF_F_HW_CSUM); 7502 7503 netdev->priv_flags |= IFF_UNICAST_FLT; 7504 7505 if (pci_using_dac) { 7506 netdev->features |= NETIF_F_HIGHDMA; 7507 netdev->vlan_features |= NETIF_F_HIGHDMA; 7508 } 7509 7510 /* MTU range: 68 - max_hw_frame_size */ 7511 netdev->min_mtu = ETH_MIN_MTU; 7512 netdev->max_mtu = adapter->max_hw_frame_size - 7513 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7514 7515 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7516 adapter->flags |= FLAG_MNG_PT_ENABLED; 7517 7518 /* before reading the NVM, reset the controller to 7519 * put the device in a known good starting state 7520 */ 7521 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7522 7523 /* systems with ASPM and others may see the checksum fail on the first 7524 * attempt. Let's give it a few tries 7525 */ 7526 for (i = 0;; i++) { 7527 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7528 break; 7529 if (i == 2) { 7530 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7531 err = -EIO; 7532 goto err_eeprom; 7533 } 7534 } 7535 7536 e1000_eeprom_checks(adapter); 7537 7538 /* copy the MAC address */ 7539 if (e1000e_read_mac_addr(&adapter->hw)) 7540 dev_err(&pdev->dev, 7541 "NVM Read Error while reading MAC address\n"); 7542 7543 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7544 7545 if (!is_valid_ether_addr(netdev->dev_addr)) { 7546 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7547 netdev->dev_addr); 7548 err = -EIO; 7549 goto err_eeprom; 7550 } 7551 7552 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7553 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7554 7555 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7556 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7557 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7558 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7559 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7560 7561 /* Initialize link parameters. User can change them with ethtool */ 7562 adapter->hw.mac.autoneg = 1; 7563 adapter->fc_autoneg = true; 7564 adapter->hw.fc.requested_mode = e1000_fc_default; 7565 adapter->hw.fc.current_mode = e1000_fc_default; 7566 adapter->hw.phy.autoneg_advertised = 0x2f; 7567 7568 /* Initial Wake on LAN setting - If APM wake is enabled in 7569 * the EEPROM, enable the ACPI Magic Packet filter 7570 */ 7571 if (adapter->flags & FLAG_APME_IN_WUC) { 7572 /* APME bit in EEPROM is mapped to WUC.APME */ 7573 eeprom_data = er32(WUC); 7574 eeprom_apme_mask = E1000_WUC_APME; 7575 if ((hw->mac.type > e1000_ich10lan) && 7576 (eeprom_data & E1000_WUC_PHY_WAKE)) 7577 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7578 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7579 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7580 (adapter->hw.bus.func == 1)) 7581 ret_val = e1000_read_nvm(&adapter->hw, 7582 NVM_INIT_CONTROL3_PORT_B, 7583 1, &eeprom_data); 7584 else 7585 ret_val = e1000_read_nvm(&adapter->hw, 7586 NVM_INIT_CONTROL3_PORT_A, 7587 1, &eeprom_data); 7588 } 7589 7590 /* fetch WoL from EEPROM */ 7591 if (ret_val) 7592 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7593 else if (eeprom_data & eeprom_apme_mask) 7594 adapter->eeprom_wol |= E1000_WUFC_MAG; 7595 7596 /* now that we have the eeprom settings, apply the special cases 7597 * where the eeprom may be wrong or the board simply won't support 7598 * wake on lan on a particular port 7599 */ 7600 if (!(adapter->flags & FLAG_HAS_WOL)) 7601 adapter->eeprom_wol = 0; 7602 7603 /* initialize the wol settings based on the eeprom settings */ 7604 adapter->wol = adapter->eeprom_wol; 7605 7606 /* make sure adapter isn't asleep if manageability is enabled */ 7607 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7608 (hw->mac.ops.check_mng_mode(hw))) 7609 device_wakeup_enable(&pdev->dev); 7610 7611 /* save off EEPROM version number */ 7612 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7613 7614 if (ret_val) { 7615 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7616 adapter->eeprom_vers = 0; 7617 } 7618 7619 /* init PTP hardware clock */ 7620 e1000e_ptp_init(adapter); 7621 7622 /* reset the hardware with the new settings */ 7623 e1000e_reset(adapter); 7624 7625 /* If the controller has AMT, do not set DRV_LOAD until the interface 7626 * is up. For all other cases, let the f/w know that the h/w is now 7627 * under the control of the driver. 7628 */ 7629 if (!(adapter->flags & FLAG_HAS_AMT)) 7630 e1000e_get_hw_control(adapter); 7631 7632 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7633 err = register_netdev(netdev); 7634 if (err) 7635 goto err_register; 7636 7637 /* carrier off reporting is important to ethtool even BEFORE open */ 7638 netif_carrier_off(netdev); 7639 7640 e1000_print_device_info(adapter); 7641 7642 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 7643 7644 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp) 7645 pm_runtime_put_noidle(&pdev->dev); 7646 7647 return 0; 7648 7649 err_register: 7650 if (!(adapter->flags & FLAG_HAS_AMT)) 7651 e1000e_release_hw_control(adapter); 7652 err_eeprom: 7653 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7654 e1000_phy_hw_reset(&adapter->hw); 7655 err_hw_init: 7656 kfree(adapter->tx_ring); 7657 kfree(adapter->rx_ring); 7658 err_sw_init: 7659 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7660 iounmap(adapter->hw.flash_address); 7661 e1000e_reset_interrupt_capability(adapter); 7662 err_flashmap: 7663 iounmap(adapter->hw.hw_addr); 7664 err_ioremap: 7665 free_netdev(netdev); 7666 err_alloc_etherdev: 7667 pci_release_mem_regions(pdev); 7668 err_pci_reg: 7669 err_dma: 7670 pci_disable_device(pdev); 7671 return err; 7672 } 7673 7674 /** 7675 * e1000_remove - Device Removal Routine 7676 * @pdev: PCI device information struct 7677 * 7678 * e1000_remove is called by the PCI subsystem to alert the driver 7679 * that it should release a PCI device. The could be caused by a 7680 * Hot-Plug event, or because the driver is going to be removed from 7681 * memory. 7682 **/ 7683 static void e1000_remove(struct pci_dev *pdev) 7684 { 7685 struct net_device *netdev = pci_get_drvdata(pdev); 7686 struct e1000_adapter *adapter = netdev_priv(netdev); 7687 7688 e1000e_ptp_remove(adapter); 7689 7690 /* The timers may be rescheduled, so explicitly disable them 7691 * from being rescheduled. 7692 */ 7693 set_bit(__E1000_DOWN, &adapter->state); 7694 del_timer_sync(&adapter->watchdog_timer); 7695 del_timer_sync(&adapter->phy_info_timer); 7696 7697 cancel_work_sync(&adapter->reset_task); 7698 cancel_work_sync(&adapter->watchdog_task); 7699 cancel_work_sync(&adapter->downshift_task); 7700 cancel_work_sync(&adapter->update_phy_task); 7701 cancel_work_sync(&adapter->print_hang_task); 7702 7703 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7704 cancel_work_sync(&adapter->tx_hwtstamp_work); 7705 if (adapter->tx_hwtstamp_skb) { 7706 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7707 adapter->tx_hwtstamp_skb = NULL; 7708 } 7709 } 7710 7711 unregister_netdev(netdev); 7712 7713 if (pci_dev_run_wake(pdev)) 7714 pm_runtime_get_noresume(&pdev->dev); 7715 7716 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7717 * would have already happened in close and is redundant. 7718 */ 7719 e1000e_release_hw_control(adapter); 7720 7721 e1000e_reset_interrupt_capability(adapter); 7722 kfree(adapter->tx_ring); 7723 kfree(adapter->rx_ring); 7724 7725 iounmap(adapter->hw.hw_addr); 7726 if ((adapter->hw.flash_address) && 7727 (adapter->hw.mac.type < e1000_pch_spt)) 7728 iounmap(adapter->hw.flash_address); 7729 pci_release_mem_regions(pdev); 7730 7731 free_netdev(netdev); 7732 7733 /* AER disable */ 7734 pci_disable_pcie_error_reporting(pdev); 7735 7736 pci_disable_device(pdev); 7737 } 7738 7739 /* PCI Error Recovery (ERS) */ 7740 static const struct pci_error_handlers e1000_err_handler = { 7741 .error_detected = e1000_io_error_detected, 7742 .slot_reset = e1000_io_slot_reset, 7743 .resume = e1000_io_resume, 7744 }; 7745 7746 static const struct pci_device_id e1000_pci_tbl[] = { 7747 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7748 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7749 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7750 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7751 board_82571 }, 7752 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7753 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7757 7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7762 7763 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7764 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7765 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7766 7767 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7768 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7769 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7770 7771 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7772 board_80003es2lan }, 7773 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7774 board_80003es2lan }, 7775 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7776 board_80003es2lan }, 7777 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7778 board_80003es2lan }, 7779 7780 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7781 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7782 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7783 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7785 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7788 7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7798 7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7802 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7806 7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7811 7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7814 7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp }, 7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp }, 7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp }, 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, 7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, 7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, 7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, 7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, 7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp }, 7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp }, 7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp }, 7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp }, 7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp }, 7856 7857 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7858 }; 7859 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7860 7861 static const struct dev_pm_ops e1000_pm_ops = { 7862 #ifdef CONFIG_PM_SLEEP 7863 .suspend = e1000e_pm_suspend, 7864 .resume = e1000e_pm_resume, 7865 .freeze = e1000e_pm_freeze, 7866 .thaw = e1000e_pm_thaw, 7867 .poweroff = e1000e_pm_suspend, 7868 .restore = e1000e_pm_resume, 7869 #endif 7870 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7871 e1000e_pm_runtime_idle) 7872 }; 7873 7874 /* PCI Device API Driver */ 7875 static struct pci_driver e1000_driver = { 7876 .name = e1000e_driver_name, 7877 .id_table = e1000_pci_tbl, 7878 .probe = e1000_probe, 7879 .remove = e1000_remove, 7880 .driver = { 7881 .pm = &e1000_pm_ops, 7882 }, 7883 .shutdown = e1000_shutdown, 7884 .err_handler = &e1000_err_handler 7885 }; 7886 7887 /** 7888 * e1000_init_module - Driver Registration Routine 7889 * 7890 * e1000_init_module is the first routine called when the driver is 7891 * loaded. All it does is register with the PCI subsystem. 7892 **/ 7893 static int __init e1000_init_module(void) 7894 { 7895 pr_info("Intel(R) PRO/1000 Network Driver\n"); 7896 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7897 7898 return pci_register_driver(&e1000_driver); 7899 } 7900 module_init(e1000_init_module); 7901 7902 /** 7903 * e1000_exit_module - Driver Exit Cleanup Routine 7904 * 7905 * e1000_exit_module is called just before the driver is removed 7906 * from memory. 7907 **/ 7908 static void __exit e1000_exit_module(void) 7909 { 7910 pci_unregister_driver(&e1000_driver); 7911 } 7912 module_exit(e1000_exit_module); 7913 7914 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7915 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7916 MODULE_LICENSE("GPL v2"); 7917 7918 /* netdev.c */ 7919