1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/pci.h> 35 #include <linux/vmalloc.h> 36 #include <linux/pagemap.h> 37 #include <linux/delay.h> 38 #include <linux/netdevice.h> 39 #include <linux/interrupt.h> 40 #include <linux/tcp.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/ethtool.h> 46 #include <linux/if_vlan.h> 47 #include <linux/cpu.h> 48 #include <linux/smp.h> 49 #include <linux/pm_qos.h> 50 #include <linux/pm_runtime.h> 51 #include <linux/aer.h> 52 #include <linux/prefetch.h> 53 54 #include "e1000.h" 55 56 #define DRV_EXTRAVERSION "-k" 57 58 #define DRV_VERSION "2.2.14" DRV_EXTRAVERSION 59 char e1000e_driver_name[] = "e1000e"; 60 const char e1000e_driver_version[] = DRV_VERSION; 61 62 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 63 static int debug = -1; 64 module_param(debug, int, 0); 65 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 66 67 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state); 68 69 static const struct e1000_info *e1000_info_tbl[] = { 70 [board_82571] = &e1000_82571_info, 71 [board_82572] = &e1000_82572_info, 72 [board_82573] = &e1000_82573_info, 73 [board_82574] = &e1000_82574_info, 74 [board_82583] = &e1000_82583_info, 75 [board_80003es2lan] = &e1000_es2_info, 76 [board_ich8lan] = &e1000_ich8_info, 77 [board_ich9lan] = &e1000_ich9_info, 78 [board_ich10lan] = &e1000_ich10_info, 79 [board_pchlan] = &e1000_pch_info, 80 [board_pch2lan] = &e1000_pch2_info, 81 [board_pch_lpt] = &e1000_pch_lpt_info, 82 }; 83 84 struct e1000_reg_info { 85 u32 ofs; 86 char *name; 87 }; 88 89 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 90 /* General Registers */ 91 {E1000_CTRL, "CTRL"}, 92 {E1000_STATUS, "STATUS"}, 93 {E1000_CTRL_EXT, "CTRL_EXT"}, 94 95 /* Interrupt Registers */ 96 {E1000_ICR, "ICR"}, 97 98 /* Rx Registers */ 99 {E1000_RCTL, "RCTL"}, 100 {E1000_RDLEN(0), "RDLEN"}, 101 {E1000_RDH(0), "RDH"}, 102 {E1000_RDT(0), "RDT"}, 103 {E1000_RDTR, "RDTR"}, 104 {E1000_RXDCTL(0), "RXDCTL"}, 105 {E1000_ERT, "ERT"}, 106 {E1000_RDBAL(0), "RDBAL"}, 107 {E1000_RDBAH(0), "RDBAH"}, 108 {E1000_RDFH, "RDFH"}, 109 {E1000_RDFT, "RDFT"}, 110 {E1000_RDFHS, "RDFHS"}, 111 {E1000_RDFTS, "RDFTS"}, 112 {E1000_RDFPC, "RDFPC"}, 113 114 /* Tx Registers */ 115 {E1000_TCTL, "TCTL"}, 116 {E1000_TDBAL(0), "TDBAL"}, 117 {E1000_TDBAH(0), "TDBAH"}, 118 {E1000_TDLEN(0), "TDLEN"}, 119 {E1000_TDH(0), "TDH"}, 120 {E1000_TDT(0), "TDT"}, 121 {E1000_TIDV, "TIDV"}, 122 {E1000_TXDCTL(0), "TXDCTL"}, 123 {E1000_TADV, "TADV"}, 124 {E1000_TARC(0), "TARC"}, 125 {E1000_TDFH, "TDFH"}, 126 {E1000_TDFT, "TDFT"}, 127 {E1000_TDFHS, "TDFHS"}, 128 {E1000_TDFTS, "TDFTS"}, 129 {E1000_TDFPC, "TDFPC"}, 130 131 /* List Terminator */ 132 {0, NULL} 133 }; 134 135 /** 136 * e1000_regdump - register printout routine 137 * @hw: pointer to the HW structure 138 * @reginfo: pointer to the register info table 139 **/ 140 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 141 { 142 int n = 0; 143 char rname[16]; 144 u32 regs[8]; 145 146 switch (reginfo->ofs) { 147 case E1000_RXDCTL(0): 148 for (n = 0; n < 2; n++) 149 regs[n] = __er32(hw, E1000_RXDCTL(n)); 150 break; 151 case E1000_TXDCTL(0): 152 for (n = 0; n < 2; n++) 153 regs[n] = __er32(hw, E1000_TXDCTL(n)); 154 break; 155 case E1000_TARC(0): 156 for (n = 0; n < 2; n++) 157 regs[n] = __er32(hw, E1000_TARC(n)); 158 break; 159 default: 160 pr_info("%-15s %08x\n", 161 reginfo->name, __er32(hw, reginfo->ofs)); 162 return; 163 } 164 165 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 166 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 167 } 168 169 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 170 struct e1000_buffer *bi) 171 { 172 int i; 173 struct e1000_ps_page *ps_page; 174 175 for (i = 0; i < adapter->rx_ps_pages; i++) { 176 ps_page = &bi->ps_pages[i]; 177 178 if (ps_page->page) { 179 pr_info("packet dump for ps_page %d:\n", i); 180 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 181 16, 1, page_address(ps_page->page), 182 PAGE_SIZE, true); 183 } 184 } 185 } 186 187 /** 188 * e1000e_dump - Print registers, Tx-ring and Rx-ring 189 * @adapter: board private structure 190 **/ 191 static void e1000e_dump(struct e1000_adapter *adapter) 192 { 193 struct net_device *netdev = adapter->netdev; 194 struct e1000_hw *hw = &adapter->hw; 195 struct e1000_reg_info *reginfo; 196 struct e1000_ring *tx_ring = adapter->tx_ring; 197 struct e1000_tx_desc *tx_desc; 198 struct my_u0 { 199 __le64 a; 200 __le64 b; 201 } *u0; 202 struct e1000_buffer *buffer_info; 203 struct e1000_ring *rx_ring = adapter->rx_ring; 204 union e1000_rx_desc_packet_split *rx_desc_ps; 205 union e1000_rx_desc_extended *rx_desc; 206 struct my_u1 { 207 __le64 a; 208 __le64 b; 209 __le64 c; 210 __le64 d; 211 } *u1; 212 u32 staterr; 213 int i = 0; 214 215 if (!netif_msg_hw(adapter)) 216 return; 217 218 /* Print netdevice Info */ 219 if (netdev) { 220 dev_info(&adapter->pdev->dev, "Net device Info\n"); 221 pr_info("Device Name state trans_start last_rx\n"); 222 pr_info("%-15s %016lX %016lX %016lX\n", 223 netdev->name, netdev->state, netdev->trans_start, 224 netdev->last_rx); 225 } 226 227 /* Print Registers */ 228 dev_info(&adapter->pdev->dev, "Register Dump\n"); 229 pr_info(" Register Name Value\n"); 230 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 231 reginfo->name; reginfo++) { 232 e1000_regdump(hw, reginfo); 233 } 234 235 /* Print Tx Ring Summary */ 236 if (!netdev || !netif_running(netdev)) 237 return; 238 239 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 240 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 241 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 242 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 243 0, tx_ring->next_to_use, tx_ring->next_to_clean, 244 (unsigned long long)buffer_info->dma, 245 buffer_info->length, 246 buffer_info->next_to_watch, 247 (unsigned long long)buffer_info->time_stamp); 248 249 /* Print Tx Ring */ 250 if (!netif_msg_tx_done(adapter)) 251 goto rx_ring_summary; 252 253 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 254 255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 256 * 257 * Legacy Transmit Descriptor 258 * +--------------------------------------------------------------+ 259 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 260 * +--------------------------------------------------------------+ 261 * 8 | Special | CSS | Status | CMD | CSO | Length | 262 * +--------------------------------------------------------------+ 263 * 63 48 47 36 35 32 31 24 23 16 15 0 264 * 265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 266 * 63 48 47 40 39 32 31 16 15 8 7 0 267 * +----------------------------------------------------------------+ 268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 269 * +----------------------------------------------------------------+ 270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 271 * +----------------------------------------------------------------+ 272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 273 * 274 * Extended Data Descriptor (DTYP=0x1) 275 * +----------------------------------------------------------------+ 276 * 0 | Buffer Address [63:0] | 277 * +----------------------------------------------------------------+ 278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 279 * +----------------------------------------------------------------+ 280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 281 */ 282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 286 const char *next_desc; 287 tx_desc = E1000_TX_DESC(*tx_ring, i); 288 buffer_info = &tx_ring->buffer_info[i]; 289 u0 = (struct my_u0 *)tx_desc; 290 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 291 next_desc = " NTC/U"; 292 else if (i == tx_ring->next_to_use) 293 next_desc = " NTU"; 294 else if (i == tx_ring->next_to_clean) 295 next_desc = " NTC"; 296 else 297 next_desc = ""; 298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 299 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' : 300 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')), 301 i, 302 (unsigned long long)le64_to_cpu(u0->a), 303 (unsigned long long)le64_to_cpu(u0->b), 304 (unsigned long long)buffer_info->dma, 305 buffer_info->length, buffer_info->next_to_watch, 306 (unsigned long long)buffer_info->time_stamp, 307 buffer_info->skb, next_desc); 308 309 if (netif_msg_pktdata(adapter) && buffer_info->skb) 310 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 311 16, 1, buffer_info->skb->data, 312 buffer_info->skb->len, true); 313 } 314 315 /* Print Rx Ring Summary */ 316 rx_ring_summary: 317 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 318 pr_info("Queue [NTU] [NTC]\n"); 319 pr_info(" %5d %5X %5X\n", 320 0, rx_ring->next_to_use, rx_ring->next_to_clean); 321 322 /* Print Rx Ring */ 323 if (!netif_msg_rx_status(adapter)) 324 return; 325 326 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 327 switch (adapter->rx_ps_pages) { 328 case 1: 329 case 2: 330 case 3: 331 /* [Extended] Packet Split Receive Descriptor Format 332 * 333 * +-----------------------------------------------------+ 334 * 0 | Buffer Address 0 [63:0] | 335 * +-----------------------------------------------------+ 336 * 8 | Buffer Address 1 [63:0] | 337 * +-----------------------------------------------------+ 338 * 16 | Buffer Address 2 [63:0] | 339 * +-----------------------------------------------------+ 340 * 24 | Buffer Address 3 [63:0] | 341 * +-----------------------------------------------------+ 342 */ 343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 344 /* [Extended] Receive Descriptor (Write-Back) Format 345 * 346 * 63 48 47 32 31 13 12 8 7 4 3 0 347 * +------------------------------------------------------+ 348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 349 * | Checksum | Ident | | Queue | | Type | 350 * +------------------------------------------------------+ 351 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 352 * +------------------------------------------------------+ 353 * 63 48 47 32 31 20 19 0 354 */ 355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 356 for (i = 0; i < rx_ring->count; i++) { 357 const char *next_desc; 358 buffer_info = &rx_ring->buffer_info[i]; 359 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 360 u1 = (struct my_u1 *)rx_desc_ps; 361 staterr = 362 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 363 364 if (i == rx_ring->next_to_use) 365 next_desc = " NTU"; 366 else if (i == rx_ring->next_to_clean) 367 next_desc = " NTC"; 368 else 369 next_desc = ""; 370 371 if (staterr & E1000_RXD_STAT_DD) { 372 /* Descriptor Done */ 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 374 "RWB", i, 375 (unsigned long long)le64_to_cpu(u1->a), 376 (unsigned long long)le64_to_cpu(u1->b), 377 (unsigned long long)le64_to_cpu(u1->c), 378 (unsigned long long)le64_to_cpu(u1->d), 379 buffer_info->skb, next_desc); 380 } else { 381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 382 "R ", i, 383 (unsigned long long)le64_to_cpu(u1->a), 384 (unsigned long long)le64_to_cpu(u1->b), 385 (unsigned long long)le64_to_cpu(u1->c), 386 (unsigned long long)le64_to_cpu(u1->d), 387 (unsigned long long)buffer_info->dma, 388 buffer_info->skb, next_desc); 389 390 if (netif_msg_pktdata(adapter)) 391 e1000e_dump_ps_pages(adapter, 392 buffer_info); 393 } 394 } 395 break; 396 default: 397 case 0: 398 /* Extended Receive Descriptor (Read) Format 399 * 400 * +-----------------------------------------------------+ 401 * 0 | Buffer Address [63:0] | 402 * +-----------------------------------------------------+ 403 * 8 | Reserved | 404 * +-----------------------------------------------------+ 405 */ 406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 407 /* Extended Receive Descriptor (Write-Back) Format 408 * 409 * 63 48 47 32 31 24 23 4 3 0 410 * +------------------------------------------------------+ 411 * | RSS Hash | | | | 412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 413 * | Packet | IP | | | Type | 414 * | Checksum | Ident | | | | 415 * +------------------------------------------------------+ 416 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 417 * +------------------------------------------------------+ 418 * 63 48 47 32 31 20 19 0 419 */ 420 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 421 422 for (i = 0; i < rx_ring->count; i++) { 423 const char *next_desc; 424 425 buffer_info = &rx_ring->buffer_info[i]; 426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 427 u1 = (struct my_u1 *)rx_desc; 428 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 429 430 if (i == rx_ring->next_to_use) 431 next_desc = " NTU"; 432 else if (i == rx_ring->next_to_clean) 433 next_desc = " NTC"; 434 else 435 next_desc = ""; 436 437 if (staterr & E1000_RXD_STAT_DD) { 438 /* Descriptor Done */ 439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 440 "RWB", i, 441 (unsigned long long)le64_to_cpu(u1->a), 442 (unsigned long long)le64_to_cpu(u1->b), 443 buffer_info->skb, next_desc); 444 } else { 445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 446 "R ", i, 447 (unsigned long long)le64_to_cpu(u1->a), 448 (unsigned long long)le64_to_cpu(u1->b), 449 (unsigned long long)buffer_info->dma, 450 buffer_info->skb, next_desc); 451 452 if (netif_msg_pktdata(adapter) && 453 buffer_info->skb) 454 print_hex_dump(KERN_INFO, "", 455 DUMP_PREFIX_ADDRESS, 16, 456 1, 457 buffer_info->skb->data, 458 adapter->rx_buffer_len, 459 true); 460 } 461 } 462 } 463 } 464 465 /** 466 * e1000_desc_unused - calculate if we have unused descriptors 467 **/ 468 static int e1000_desc_unused(struct e1000_ring *ring) 469 { 470 if (ring->next_to_clean > ring->next_to_use) 471 return ring->next_to_clean - ring->next_to_use - 1; 472 473 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 474 } 475 476 /** 477 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 478 * @adapter: board private structure 479 * @hwtstamps: time stamp structure to update 480 * @systim: unsigned 64bit system time value. 481 * 482 * Convert the system time value stored in the RX/TXSTMP registers into a 483 * hwtstamp which can be used by the upper level time stamping functions. 484 * 485 * The 'systim_lock' spinlock is used to protect the consistency of the 486 * system time value. This is needed because reading the 64 bit time 487 * value involves reading two 32 bit registers. The first read latches the 488 * value. 489 **/ 490 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 491 struct skb_shared_hwtstamps *hwtstamps, 492 u64 systim) 493 { 494 u64 ns; 495 unsigned long flags; 496 497 spin_lock_irqsave(&adapter->systim_lock, flags); 498 ns = timecounter_cyc2time(&adapter->tc, systim); 499 spin_unlock_irqrestore(&adapter->systim_lock, flags); 500 501 memset(hwtstamps, 0, sizeof(*hwtstamps)); 502 hwtstamps->hwtstamp = ns_to_ktime(ns); 503 } 504 505 /** 506 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 507 * @adapter: board private structure 508 * @status: descriptor extended error and status field 509 * @skb: particular skb to include time stamp 510 * 511 * If the time stamp is valid, convert it into the timecounter ns value 512 * and store that result into the shhwtstamps structure which is passed 513 * up the network stack. 514 **/ 515 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 516 struct sk_buff *skb) 517 { 518 struct e1000_hw *hw = &adapter->hw; 519 u64 rxstmp; 520 521 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 522 !(status & E1000_RXDEXT_STATERR_TST) || 523 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 524 return; 525 526 /* The Rx time stamp registers contain the time stamp. No other 527 * received packet will be time stamped until the Rx time stamp 528 * registers are read. Because only one packet can be time stamped 529 * at a time, the register values must belong to this packet and 530 * therefore none of the other additional attributes need to be 531 * compared. 532 */ 533 rxstmp = (u64)er32(RXSTMPL); 534 rxstmp |= (u64)er32(RXSTMPH) << 32; 535 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 536 537 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 538 } 539 540 /** 541 * e1000_receive_skb - helper function to handle Rx indications 542 * @adapter: board private structure 543 * @staterr: descriptor extended error and status field as written by hardware 544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 545 * @skb: pointer to sk_buff to be indicated to stack 546 **/ 547 static void e1000_receive_skb(struct e1000_adapter *adapter, 548 struct net_device *netdev, struct sk_buff *skb, 549 u32 staterr, __le16 vlan) 550 { 551 u16 tag = le16_to_cpu(vlan); 552 553 e1000e_rx_hwtstamp(adapter, staterr, skb); 554 555 skb->protocol = eth_type_trans(skb, netdev); 556 557 if (staterr & E1000_RXD_STAT_VP) 558 __vlan_hwaccel_put_tag(skb, tag); 559 560 napi_gro_receive(&adapter->napi, skb); 561 } 562 563 /** 564 * e1000_rx_checksum - Receive Checksum Offload 565 * @adapter: board private structure 566 * @status_err: receive descriptor status and error fields 567 * @csum: receive descriptor csum field 568 * @sk_buff: socket buffer with received data 569 **/ 570 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 571 struct sk_buff *skb) 572 { 573 u16 status = (u16)status_err; 574 u8 errors = (u8)(status_err >> 24); 575 576 skb_checksum_none_assert(skb); 577 578 /* Rx checksum disabled */ 579 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 580 return; 581 582 /* Ignore Checksum bit is set */ 583 if (status & E1000_RXD_STAT_IXSM) 584 return; 585 586 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 587 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 588 /* let the stack verify checksum errors */ 589 adapter->hw_csum_err++; 590 return; 591 } 592 593 /* TCP/UDP Checksum has not been calculated */ 594 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 595 return; 596 597 /* It must be a TCP or UDP packet with a valid checksum */ 598 skb->ip_summed = CHECKSUM_UNNECESSARY; 599 adapter->hw_csum_good++; 600 } 601 602 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 603 { 604 struct e1000_adapter *adapter = rx_ring->adapter; 605 struct e1000_hw *hw = &adapter->hw; 606 s32 ret_val = __ew32_prepare(hw); 607 608 writel(i, rx_ring->tail); 609 610 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 611 u32 rctl = er32(RCTL); 612 ew32(RCTL, rctl & ~E1000_RCTL_EN); 613 e_err("ME firmware caused invalid RDT - resetting\n"); 614 schedule_work(&adapter->reset_task); 615 } 616 } 617 618 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 619 { 620 struct e1000_adapter *adapter = tx_ring->adapter; 621 struct e1000_hw *hw = &adapter->hw; 622 s32 ret_val = __ew32_prepare(hw); 623 624 writel(i, tx_ring->tail); 625 626 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 627 u32 tctl = er32(TCTL); 628 ew32(TCTL, tctl & ~E1000_TCTL_EN); 629 e_err("ME firmware caused invalid TDT - resetting\n"); 630 schedule_work(&adapter->reset_task); 631 } 632 } 633 634 /** 635 * e1000_alloc_rx_buffers - Replace used receive buffers 636 * @rx_ring: Rx descriptor ring 637 **/ 638 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 639 int cleaned_count, gfp_t gfp) 640 { 641 struct e1000_adapter *adapter = rx_ring->adapter; 642 struct net_device *netdev = adapter->netdev; 643 struct pci_dev *pdev = adapter->pdev; 644 union e1000_rx_desc_extended *rx_desc; 645 struct e1000_buffer *buffer_info; 646 struct sk_buff *skb; 647 unsigned int i; 648 unsigned int bufsz = adapter->rx_buffer_len; 649 650 i = rx_ring->next_to_use; 651 buffer_info = &rx_ring->buffer_info[i]; 652 653 while (cleaned_count--) { 654 skb = buffer_info->skb; 655 if (skb) { 656 skb_trim(skb, 0); 657 goto map_skb; 658 } 659 660 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 661 if (!skb) { 662 /* Better luck next round */ 663 adapter->alloc_rx_buff_failed++; 664 break; 665 } 666 667 buffer_info->skb = skb; 668 map_skb: 669 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 670 adapter->rx_buffer_len, 671 DMA_FROM_DEVICE); 672 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 673 dev_err(&pdev->dev, "Rx DMA map failed\n"); 674 adapter->rx_dma_failed++; 675 break; 676 } 677 678 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 679 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 680 681 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 682 /* Force memory writes to complete before letting h/w 683 * know there are new descriptors to fetch. (Only 684 * applicable for weak-ordered memory model archs, 685 * such as IA-64). 686 */ 687 wmb(); 688 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 689 e1000e_update_rdt_wa(rx_ring, i); 690 else 691 writel(i, rx_ring->tail); 692 } 693 i++; 694 if (i == rx_ring->count) 695 i = 0; 696 buffer_info = &rx_ring->buffer_info[i]; 697 } 698 699 rx_ring->next_to_use = i; 700 } 701 702 /** 703 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 704 * @rx_ring: Rx descriptor ring 705 **/ 706 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 707 int cleaned_count, gfp_t gfp) 708 { 709 struct e1000_adapter *adapter = rx_ring->adapter; 710 struct net_device *netdev = adapter->netdev; 711 struct pci_dev *pdev = adapter->pdev; 712 union e1000_rx_desc_packet_split *rx_desc; 713 struct e1000_buffer *buffer_info; 714 struct e1000_ps_page *ps_page; 715 struct sk_buff *skb; 716 unsigned int i, j; 717 718 i = rx_ring->next_to_use; 719 buffer_info = &rx_ring->buffer_info[i]; 720 721 while (cleaned_count--) { 722 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 723 724 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 725 ps_page = &buffer_info->ps_pages[j]; 726 if (j >= adapter->rx_ps_pages) { 727 /* all unused desc entries get hw null ptr */ 728 rx_desc->read.buffer_addr[j + 1] = 729 ~cpu_to_le64(0); 730 continue; 731 } 732 if (!ps_page->page) { 733 ps_page->page = alloc_page(gfp); 734 if (!ps_page->page) { 735 adapter->alloc_rx_buff_failed++; 736 goto no_buffers; 737 } 738 ps_page->dma = dma_map_page(&pdev->dev, 739 ps_page->page, 740 0, PAGE_SIZE, 741 DMA_FROM_DEVICE); 742 if (dma_mapping_error(&pdev->dev, 743 ps_page->dma)) { 744 dev_err(&adapter->pdev->dev, 745 "Rx DMA page map failed\n"); 746 adapter->rx_dma_failed++; 747 goto no_buffers; 748 } 749 } 750 /* Refresh the desc even if buffer_addrs 751 * didn't change because each write-back 752 * erases this info. 753 */ 754 rx_desc->read.buffer_addr[j + 1] = 755 cpu_to_le64(ps_page->dma); 756 } 757 758 skb = __netdev_alloc_skb_ip_align(netdev, 759 adapter->rx_ps_bsize0, 760 gfp); 761 762 if (!skb) { 763 adapter->alloc_rx_buff_failed++; 764 break; 765 } 766 767 buffer_info->skb = skb; 768 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 769 adapter->rx_ps_bsize0, 770 DMA_FROM_DEVICE); 771 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 772 dev_err(&pdev->dev, "Rx DMA map failed\n"); 773 adapter->rx_dma_failed++; 774 /* cleanup skb */ 775 dev_kfree_skb_any(skb); 776 buffer_info->skb = NULL; 777 break; 778 } 779 780 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 781 782 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 783 /* Force memory writes to complete before letting h/w 784 * know there are new descriptors to fetch. (Only 785 * applicable for weak-ordered memory model archs, 786 * such as IA-64). 787 */ 788 wmb(); 789 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 790 e1000e_update_rdt_wa(rx_ring, i << 1); 791 else 792 writel(i << 1, rx_ring->tail); 793 } 794 795 i++; 796 if (i == rx_ring->count) 797 i = 0; 798 buffer_info = &rx_ring->buffer_info[i]; 799 } 800 801 no_buffers: 802 rx_ring->next_to_use = i; 803 } 804 805 /** 806 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 807 * @rx_ring: Rx descriptor ring 808 * @cleaned_count: number of buffers to allocate this pass 809 **/ 810 811 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 812 int cleaned_count, gfp_t gfp) 813 { 814 struct e1000_adapter *adapter = rx_ring->adapter; 815 struct net_device *netdev = adapter->netdev; 816 struct pci_dev *pdev = adapter->pdev; 817 union e1000_rx_desc_extended *rx_desc; 818 struct e1000_buffer *buffer_info; 819 struct sk_buff *skb; 820 unsigned int i; 821 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 822 823 i = rx_ring->next_to_use; 824 buffer_info = &rx_ring->buffer_info[i]; 825 826 while (cleaned_count--) { 827 skb = buffer_info->skb; 828 if (skb) { 829 skb_trim(skb, 0); 830 goto check_page; 831 } 832 833 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 834 if (unlikely(!skb)) { 835 /* Better luck next round */ 836 adapter->alloc_rx_buff_failed++; 837 break; 838 } 839 840 buffer_info->skb = skb; 841 check_page: 842 /* allocate a new page if necessary */ 843 if (!buffer_info->page) { 844 buffer_info->page = alloc_page(gfp); 845 if (unlikely(!buffer_info->page)) { 846 adapter->alloc_rx_buff_failed++; 847 break; 848 } 849 } 850 851 if (!buffer_info->dma) 852 buffer_info->dma = dma_map_page(&pdev->dev, 853 buffer_info->page, 0, 854 PAGE_SIZE, 855 DMA_FROM_DEVICE); 856 857 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 858 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 859 860 if (unlikely(++i == rx_ring->count)) 861 i = 0; 862 buffer_info = &rx_ring->buffer_info[i]; 863 } 864 865 if (likely(rx_ring->next_to_use != i)) { 866 rx_ring->next_to_use = i; 867 if (unlikely(i-- == 0)) 868 i = (rx_ring->count - 1); 869 870 /* Force memory writes to complete before letting h/w 871 * know there are new descriptors to fetch. (Only 872 * applicable for weak-ordered memory model archs, 873 * such as IA-64). 874 */ 875 wmb(); 876 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 877 e1000e_update_rdt_wa(rx_ring, i); 878 else 879 writel(i, rx_ring->tail); 880 } 881 } 882 883 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 884 struct sk_buff *skb) 885 { 886 if (netdev->features & NETIF_F_RXHASH) 887 skb->rxhash = le32_to_cpu(rss); 888 } 889 890 /** 891 * e1000_clean_rx_irq - Send received data up the network stack 892 * @rx_ring: Rx descriptor ring 893 * 894 * the return value indicates whether actual cleaning was done, there 895 * is no guarantee that everything was cleaned 896 **/ 897 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 898 int work_to_do) 899 { 900 struct e1000_adapter *adapter = rx_ring->adapter; 901 struct net_device *netdev = adapter->netdev; 902 struct pci_dev *pdev = adapter->pdev; 903 struct e1000_hw *hw = &adapter->hw; 904 union e1000_rx_desc_extended *rx_desc, *next_rxd; 905 struct e1000_buffer *buffer_info, *next_buffer; 906 u32 length, staterr; 907 unsigned int i; 908 int cleaned_count = 0; 909 bool cleaned = false; 910 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 911 912 i = rx_ring->next_to_clean; 913 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 914 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 915 buffer_info = &rx_ring->buffer_info[i]; 916 917 while (staterr & E1000_RXD_STAT_DD) { 918 struct sk_buff *skb; 919 920 if (*work_done >= work_to_do) 921 break; 922 (*work_done)++; 923 rmb(); /* read descriptor and rx_buffer_info after status DD */ 924 925 skb = buffer_info->skb; 926 buffer_info->skb = NULL; 927 928 prefetch(skb->data - NET_IP_ALIGN); 929 930 i++; 931 if (i == rx_ring->count) 932 i = 0; 933 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 934 prefetch(next_rxd); 935 936 next_buffer = &rx_ring->buffer_info[i]; 937 938 cleaned = true; 939 cleaned_count++; 940 dma_unmap_single(&pdev->dev, 941 buffer_info->dma, 942 adapter->rx_buffer_len, 943 DMA_FROM_DEVICE); 944 buffer_info->dma = 0; 945 946 length = le16_to_cpu(rx_desc->wb.upper.length); 947 948 /* !EOP means multiple descriptors were used to store a single 949 * packet, if that's the case we need to toss it. In fact, we 950 * need to toss every packet with the EOP bit clear and the 951 * next frame that _does_ have the EOP bit set, as it is by 952 * definition only a frame fragment 953 */ 954 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 955 adapter->flags2 |= FLAG2_IS_DISCARDING; 956 957 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 958 /* All receives must fit into a single buffer */ 959 e_dbg("Receive packet consumed multiple buffers\n"); 960 /* recycle */ 961 buffer_info->skb = skb; 962 if (staterr & E1000_RXD_STAT_EOP) 963 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 964 goto next_desc; 965 } 966 967 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 968 !(netdev->features & NETIF_F_RXALL))) { 969 /* recycle */ 970 buffer_info->skb = skb; 971 goto next_desc; 972 } 973 974 /* adjust length to remove Ethernet CRC */ 975 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 976 /* If configured to store CRC, don't subtract FCS, 977 * but keep the FCS bytes out of the total_rx_bytes 978 * counter 979 */ 980 if (netdev->features & NETIF_F_RXFCS) 981 total_rx_bytes -= 4; 982 else 983 length -= 4; 984 } 985 986 total_rx_bytes += length; 987 total_rx_packets++; 988 989 /* code added for copybreak, this should improve 990 * performance for small packets with large amounts 991 * of reassembly being done in the stack 992 */ 993 if (length < copybreak) { 994 struct sk_buff *new_skb = 995 netdev_alloc_skb_ip_align(netdev, length); 996 if (new_skb) { 997 skb_copy_to_linear_data_offset(new_skb, 998 -NET_IP_ALIGN, 999 (skb->data - 1000 NET_IP_ALIGN), 1001 (length + 1002 NET_IP_ALIGN)); 1003 /* save the skb in buffer_info as good */ 1004 buffer_info->skb = skb; 1005 skb = new_skb; 1006 } 1007 /* else just continue with the old one */ 1008 } 1009 /* end copybreak code */ 1010 skb_put(skb, length); 1011 1012 /* Receive Checksum Offload */ 1013 e1000_rx_checksum(adapter, staterr, skb); 1014 1015 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1016 1017 e1000_receive_skb(adapter, netdev, skb, staterr, 1018 rx_desc->wb.upper.vlan); 1019 1020 next_desc: 1021 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1022 1023 /* return some buffers to hardware, one at a time is too slow */ 1024 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1025 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1026 GFP_ATOMIC); 1027 cleaned_count = 0; 1028 } 1029 1030 /* use prefetched values */ 1031 rx_desc = next_rxd; 1032 buffer_info = next_buffer; 1033 1034 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1035 } 1036 rx_ring->next_to_clean = i; 1037 1038 cleaned_count = e1000_desc_unused(rx_ring); 1039 if (cleaned_count) 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1041 1042 adapter->total_rx_bytes += total_rx_bytes; 1043 adapter->total_rx_packets += total_rx_packets; 1044 return cleaned; 1045 } 1046 1047 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1048 struct e1000_buffer *buffer_info) 1049 { 1050 struct e1000_adapter *adapter = tx_ring->adapter; 1051 1052 if (buffer_info->dma) { 1053 if (buffer_info->mapped_as_page) 1054 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1055 buffer_info->length, DMA_TO_DEVICE); 1056 else 1057 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1058 buffer_info->length, DMA_TO_DEVICE); 1059 buffer_info->dma = 0; 1060 } 1061 if (buffer_info->skb) { 1062 dev_kfree_skb_any(buffer_info->skb); 1063 buffer_info->skb = NULL; 1064 } 1065 buffer_info->time_stamp = 0; 1066 } 1067 1068 static void e1000_print_hw_hang(struct work_struct *work) 1069 { 1070 struct e1000_adapter *adapter = container_of(work, 1071 struct e1000_adapter, 1072 print_hang_task); 1073 struct net_device *netdev = adapter->netdev; 1074 struct e1000_ring *tx_ring = adapter->tx_ring; 1075 unsigned int i = tx_ring->next_to_clean; 1076 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1077 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1078 struct e1000_hw *hw = &adapter->hw; 1079 u16 phy_status, phy_1000t_status, phy_ext_status; 1080 u16 pci_status; 1081 1082 if (test_bit(__E1000_DOWN, &adapter->state)) 1083 return; 1084 1085 if (!adapter->tx_hang_recheck && 1086 (adapter->flags2 & FLAG2_DMA_BURST)) { 1087 /* May be block on write-back, flush and detect again 1088 * flush pending descriptor writebacks to memory 1089 */ 1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1091 /* execute the writes immediately */ 1092 e1e_flush(); 1093 /* Due to rare timing issues, write to TIDV again to ensure 1094 * the write is successful 1095 */ 1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1097 /* execute the writes immediately */ 1098 e1e_flush(); 1099 adapter->tx_hang_recheck = true; 1100 return; 1101 } 1102 /* Real hang detected */ 1103 adapter->tx_hang_recheck = false; 1104 netif_stop_queue(netdev); 1105 1106 e1e_rphy(hw, MII_BMSR, &phy_status); 1107 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1108 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1109 1110 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1111 1112 /* detected Hardware unit hang */ 1113 e_err("Detected Hardware Unit Hang:\n" 1114 " TDH <%x>\n" 1115 " TDT <%x>\n" 1116 " next_to_use <%x>\n" 1117 " next_to_clean <%x>\n" 1118 "buffer_info[next_to_clean]:\n" 1119 " time_stamp <%lx>\n" 1120 " next_to_watch <%x>\n" 1121 " jiffies <%lx>\n" 1122 " next_to_watch.status <%x>\n" 1123 "MAC Status <%x>\n" 1124 "PHY Status <%x>\n" 1125 "PHY 1000BASE-T Status <%x>\n" 1126 "PHY Extended Status <%x>\n" 1127 "PCI Status <%x>\n", 1128 readl(tx_ring->head), 1129 readl(tx_ring->tail), 1130 tx_ring->next_to_use, 1131 tx_ring->next_to_clean, 1132 tx_ring->buffer_info[eop].time_stamp, 1133 eop, 1134 jiffies, 1135 eop_desc->upper.fields.status, 1136 er32(STATUS), 1137 phy_status, 1138 phy_1000t_status, 1139 phy_ext_status, 1140 pci_status); 1141 1142 /* Suggest workaround for known h/w issue */ 1143 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1144 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1145 } 1146 1147 /** 1148 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1149 * @work: pointer to work struct 1150 * 1151 * This work function polls the TSYNCTXCTL valid bit to determine when a 1152 * timestamp has been taken for the current stored skb. The timestamp must 1153 * be for this skb because only one such packet is allowed in the queue. 1154 */ 1155 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1156 { 1157 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1158 tx_hwtstamp_work); 1159 struct e1000_hw *hw = &adapter->hw; 1160 1161 if (!adapter->tx_hwtstamp_skb) 1162 return; 1163 1164 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1165 struct skb_shared_hwtstamps shhwtstamps; 1166 u64 txstmp; 1167 1168 txstmp = er32(TXSTMPL); 1169 txstmp |= (u64)er32(TXSTMPH) << 32; 1170 1171 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1172 1173 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps); 1174 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1175 adapter->tx_hwtstamp_skb = NULL; 1176 } else { 1177 /* reschedule to check later */ 1178 schedule_work(&adapter->tx_hwtstamp_work); 1179 } 1180 } 1181 1182 /** 1183 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1184 * @tx_ring: Tx descriptor ring 1185 * 1186 * the return value indicates whether actual cleaning was done, there 1187 * is no guarantee that everything was cleaned 1188 **/ 1189 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1190 { 1191 struct e1000_adapter *adapter = tx_ring->adapter; 1192 struct net_device *netdev = adapter->netdev; 1193 struct e1000_hw *hw = &adapter->hw; 1194 struct e1000_tx_desc *tx_desc, *eop_desc; 1195 struct e1000_buffer *buffer_info; 1196 unsigned int i, eop; 1197 unsigned int count = 0; 1198 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1199 unsigned int bytes_compl = 0, pkts_compl = 0; 1200 1201 i = tx_ring->next_to_clean; 1202 eop = tx_ring->buffer_info[i].next_to_watch; 1203 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1204 1205 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1206 (count < tx_ring->count)) { 1207 bool cleaned = false; 1208 rmb(); /* read buffer_info after eop_desc */ 1209 for (; !cleaned; count++) { 1210 tx_desc = E1000_TX_DESC(*tx_ring, i); 1211 buffer_info = &tx_ring->buffer_info[i]; 1212 cleaned = (i == eop); 1213 1214 if (cleaned) { 1215 total_tx_packets += buffer_info->segs; 1216 total_tx_bytes += buffer_info->bytecount; 1217 if (buffer_info->skb) { 1218 bytes_compl += buffer_info->skb->len; 1219 pkts_compl++; 1220 } 1221 } 1222 1223 e1000_put_txbuf(tx_ring, buffer_info); 1224 tx_desc->upper.data = 0; 1225 1226 i++; 1227 if (i == tx_ring->count) 1228 i = 0; 1229 } 1230 1231 if (i == tx_ring->next_to_use) 1232 break; 1233 eop = tx_ring->buffer_info[i].next_to_watch; 1234 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1235 } 1236 1237 tx_ring->next_to_clean = i; 1238 1239 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1240 1241 #define TX_WAKE_THRESHOLD 32 1242 if (count && netif_carrier_ok(netdev) && 1243 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1244 /* Make sure that anybody stopping the queue after this 1245 * sees the new next_to_clean. 1246 */ 1247 smp_mb(); 1248 1249 if (netif_queue_stopped(netdev) && 1250 !(test_bit(__E1000_DOWN, &adapter->state))) { 1251 netif_wake_queue(netdev); 1252 ++adapter->restart_queue; 1253 } 1254 } 1255 1256 if (adapter->detect_tx_hung) { 1257 /* Detect a transmit hang in hardware, this serializes the 1258 * check with the clearing of time_stamp and movement of i 1259 */ 1260 adapter->detect_tx_hung = false; 1261 if (tx_ring->buffer_info[i].time_stamp && 1262 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1263 + (adapter->tx_timeout_factor * HZ)) && 1264 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1265 schedule_work(&adapter->print_hang_task); 1266 else 1267 adapter->tx_hang_recheck = false; 1268 } 1269 adapter->total_tx_bytes += total_tx_bytes; 1270 adapter->total_tx_packets += total_tx_packets; 1271 return count < tx_ring->count; 1272 } 1273 1274 /** 1275 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1276 * @rx_ring: Rx descriptor ring 1277 * 1278 * the return value indicates whether actual cleaning was done, there 1279 * is no guarantee that everything was cleaned 1280 **/ 1281 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1282 int work_to_do) 1283 { 1284 struct e1000_adapter *adapter = rx_ring->adapter; 1285 struct e1000_hw *hw = &adapter->hw; 1286 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1287 struct net_device *netdev = adapter->netdev; 1288 struct pci_dev *pdev = adapter->pdev; 1289 struct e1000_buffer *buffer_info, *next_buffer; 1290 struct e1000_ps_page *ps_page; 1291 struct sk_buff *skb; 1292 unsigned int i, j; 1293 u32 length, staterr; 1294 int cleaned_count = 0; 1295 bool cleaned = false; 1296 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1297 1298 i = rx_ring->next_to_clean; 1299 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1300 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1301 buffer_info = &rx_ring->buffer_info[i]; 1302 1303 while (staterr & E1000_RXD_STAT_DD) { 1304 if (*work_done >= work_to_do) 1305 break; 1306 (*work_done)++; 1307 skb = buffer_info->skb; 1308 rmb(); /* read descriptor and rx_buffer_info after status DD */ 1309 1310 /* in the packet split case this is header only */ 1311 prefetch(skb->data - NET_IP_ALIGN); 1312 1313 i++; 1314 if (i == rx_ring->count) 1315 i = 0; 1316 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1317 prefetch(next_rxd); 1318 1319 next_buffer = &rx_ring->buffer_info[i]; 1320 1321 cleaned = true; 1322 cleaned_count++; 1323 dma_unmap_single(&pdev->dev, buffer_info->dma, 1324 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1325 buffer_info->dma = 0; 1326 1327 /* see !EOP comment in other Rx routine */ 1328 if (!(staterr & E1000_RXD_STAT_EOP)) 1329 adapter->flags2 |= FLAG2_IS_DISCARDING; 1330 1331 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1332 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1333 dev_kfree_skb_irq(skb); 1334 if (staterr & E1000_RXD_STAT_EOP) 1335 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1336 goto next_desc; 1337 } 1338 1339 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1340 !(netdev->features & NETIF_F_RXALL))) { 1341 dev_kfree_skb_irq(skb); 1342 goto next_desc; 1343 } 1344 1345 length = le16_to_cpu(rx_desc->wb.middle.length0); 1346 1347 if (!length) { 1348 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1349 dev_kfree_skb_irq(skb); 1350 goto next_desc; 1351 } 1352 1353 /* Good Receive */ 1354 skb_put(skb, length); 1355 1356 { 1357 /* this looks ugly, but it seems compiler issues make 1358 * it more efficient than reusing j 1359 */ 1360 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1361 1362 /* page alloc/put takes too long and effects small 1363 * packet throughput, so unsplit small packets and 1364 * save the alloc/put only valid in softirq (napi) 1365 * context to call kmap_* 1366 */ 1367 if (l1 && (l1 <= copybreak) && 1368 ((length + l1) <= adapter->rx_ps_bsize0)) { 1369 u8 *vaddr; 1370 1371 ps_page = &buffer_info->ps_pages[0]; 1372 1373 /* there is no documentation about how to call 1374 * kmap_atomic, so we can't hold the mapping 1375 * very long 1376 */ 1377 dma_sync_single_for_cpu(&pdev->dev, 1378 ps_page->dma, 1379 PAGE_SIZE, 1380 DMA_FROM_DEVICE); 1381 vaddr = kmap_atomic(ps_page->page); 1382 memcpy(skb_tail_pointer(skb), vaddr, l1); 1383 kunmap_atomic(vaddr); 1384 dma_sync_single_for_device(&pdev->dev, 1385 ps_page->dma, 1386 PAGE_SIZE, 1387 DMA_FROM_DEVICE); 1388 1389 /* remove the CRC */ 1390 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1391 if (!(netdev->features & NETIF_F_RXFCS)) 1392 l1 -= 4; 1393 } 1394 1395 skb_put(skb, l1); 1396 goto copydone; 1397 } /* if */ 1398 } 1399 1400 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1401 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1402 if (!length) 1403 break; 1404 1405 ps_page = &buffer_info->ps_pages[j]; 1406 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1407 DMA_FROM_DEVICE); 1408 ps_page->dma = 0; 1409 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1410 ps_page->page = NULL; 1411 skb->len += length; 1412 skb->data_len += length; 1413 skb->truesize += PAGE_SIZE; 1414 } 1415 1416 /* strip the ethernet crc, problem is we're using pages now so 1417 * this whole operation can get a little cpu intensive 1418 */ 1419 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1420 if (!(netdev->features & NETIF_F_RXFCS)) 1421 pskb_trim(skb, skb->len - 4); 1422 } 1423 1424 copydone: 1425 total_rx_bytes += skb->len; 1426 total_rx_packets++; 1427 1428 e1000_rx_checksum(adapter, staterr, skb); 1429 1430 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1431 1432 if (rx_desc->wb.upper.header_status & 1433 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1434 adapter->rx_hdr_split++; 1435 1436 e1000_receive_skb(adapter, netdev, skb, staterr, 1437 rx_desc->wb.middle.vlan); 1438 1439 next_desc: 1440 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1441 buffer_info->skb = NULL; 1442 1443 /* return some buffers to hardware, one at a time is too slow */ 1444 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1445 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1446 GFP_ATOMIC); 1447 cleaned_count = 0; 1448 } 1449 1450 /* use prefetched values */ 1451 rx_desc = next_rxd; 1452 buffer_info = next_buffer; 1453 1454 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1455 } 1456 rx_ring->next_to_clean = i; 1457 1458 cleaned_count = e1000_desc_unused(rx_ring); 1459 if (cleaned_count) 1460 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1461 1462 adapter->total_rx_bytes += total_rx_bytes; 1463 adapter->total_rx_packets += total_rx_packets; 1464 return cleaned; 1465 } 1466 1467 /** 1468 * e1000_consume_page - helper function 1469 **/ 1470 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1471 u16 length) 1472 { 1473 bi->page = NULL; 1474 skb->len += length; 1475 skb->data_len += length; 1476 skb->truesize += PAGE_SIZE; 1477 } 1478 1479 /** 1480 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1481 * @adapter: board private structure 1482 * 1483 * the return value indicates whether actual cleaning was done, there 1484 * is no guarantee that everything was cleaned 1485 **/ 1486 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1487 int work_to_do) 1488 { 1489 struct e1000_adapter *adapter = rx_ring->adapter; 1490 struct net_device *netdev = adapter->netdev; 1491 struct pci_dev *pdev = adapter->pdev; 1492 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1493 struct e1000_buffer *buffer_info, *next_buffer; 1494 u32 length, staterr; 1495 unsigned int i; 1496 int cleaned_count = 0; 1497 bool cleaned = false; 1498 unsigned int total_rx_bytes=0, total_rx_packets=0; 1499 1500 i = rx_ring->next_to_clean; 1501 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1502 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1503 buffer_info = &rx_ring->buffer_info[i]; 1504 1505 while (staterr & E1000_RXD_STAT_DD) { 1506 struct sk_buff *skb; 1507 1508 if (*work_done >= work_to_do) 1509 break; 1510 (*work_done)++; 1511 rmb(); /* read descriptor and rx_buffer_info after status DD */ 1512 1513 skb = buffer_info->skb; 1514 buffer_info->skb = NULL; 1515 1516 ++i; 1517 if (i == rx_ring->count) 1518 i = 0; 1519 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1520 prefetch(next_rxd); 1521 1522 next_buffer = &rx_ring->buffer_info[i]; 1523 1524 cleaned = true; 1525 cleaned_count++; 1526 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1527 DMA_FROM_DEVICE); 1528 buffer_info->dma = 0; 1529 1530 length = le16_to_cpu(rx_desc->wb.upper.length); 1531 1532 /* errors is only valid for DD + EOP descriptors */ 1533 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1534 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1535 !(netdev->features & NETIF_F_RXALL)))) { 1536 /* recycle both page and skb */ 1537 buffer_info->skb = skb; 1538 /* an error means any chain goes out the window too */ 1539 if (rx_ring->rx_skb_top) 1540 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1541 rx_ring->rx_skb_top = NULL; 1542 goto next_desc; 1543 } 1544 1545 #define rxtop (rx_ring->rx_skb_top) 1546 if (!(staterr & E1000_RXD_STAT_EOP)) { 1547 /* this descriptor is only the beginning (or middle) */ 1548 if (!rxtop) { 1549 /* this is the beginning of a chain */ 1550 rxtop = skb; 1551 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1552 0, length); 1553 } else { 1554 /* this is the middle of a chain */ 1555 skb_fill_page_desc(rxtop, 1556 skb_shinfo(rxtop)->nr_frags, 1557 buffer_info->page, 0, length); 1558 /* re-use the skb, only consumed the page */ 1559 buffer_info->skb = skb; 1560 } 1561 e1000_consume_page(buffer_info, rxtop, length); 1562 goto next_desc; 1563 } else { 1564 if (rxtop) { 1565 /* end of the chain */ 1566 skb_fill_page_desc(rxtop, 1567 skb_shinfo(rxtop)->nr_frags, 1568 buffer_info->page, 0, length); 1569 /* re-use the current skb, we only consumed the 1570 * page 1571 */ 1572 buffer_info->skb = skb; 1573 skb = rxtop; 1574 rxtop = NULL; 1575 e1000_consume_page(buffer_info, skb, length); 1576 } else { 1577 /* no chain, got EOP, this buf is the packet 1578 * copybreak to save the put_page/alloc_page 1579 */ 1580 if (length <= copybreak && 1581 skb_tailroom(skb) >= length) { 1582 u8 *vaddr; 1583 vaddr = kmap_atomic(buffer_info->page); 1584 memcpy(skb_tail_pointer(skb), vaddr, 1585 length); 1586 kunmap_atomic(vaddr); 1587 /* re-use the page, so don't erase 1588 * buffer_info->page 1589 */ 1590 skb_put(skb, length); 1591 } else { 1592 skb_fill_page_desc(skb, 0, 1593 buffer_info->page, 0, 1594 length); 1595 e1000_consume_page(buffer_info, skb, 1596 length); 1597 } 1598 } 1599 } 1600 1601 /* Receive Checksum Offload */ 1602 e1000_rx_checksum(adapter, staterr, skb); 1603 1604 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1605 1606 /* probably a little skewed due to removing CRC */ 1607 total_rx_bytes += skb->len; 1608 total_rx_packets++; 1609 1610 /* eth type trans needs skb->data to point to something */ 1611 if (!pskb_may_pull(skb, ETH_HLEN)) { 1612 e_err("pskb_may_pull failed.\n"); 1613 dev_kfree_skb_irq(skb); 1614 goto next_desc; 1615 } 1616 1617 e1000_receive_skb(adapter, netdev, skb, staterr, 1618 rx_desc->wb.upper.vlan); 1619 1620 next_desc: 1621 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1622 1623 /* return some buffers to hardware, one at a time is too slow */ 1624 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1625 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1626 GFP_ATOMIC); 1627 cleaned_count = 0; 1628 } 1629 1630 /* use prefetched values */ 1631 rx_desc = next_rxd; 1632 buffer_info = next_buffer; 1633 1634 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1635 } 1636 rx_ring->next_to_clean = i; 1637 1638 cleaned_count = e1000_desc_unused(rx_ring); 1639 if (cleaned_count) 1640 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1641 1642 adapter->total_rx_bytes += total_rx_bytes; 1643 adapter->total_rx_packets += total_rx_packets; 1644 return cleaned; 1645 } 1646 1647 /** 1648 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1649 * @rx_ring: Rx descriptor ring 1650 **/ 1651 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1652 { 1653 struct e1000_adapter *adapter = rx_ring->adapter; 1654 struct e1000_buffer *buffer_info; 1655 struct e1000_ps_page *ps_page; 1656 struct pci_dev *pdev = adapter->pdev; 1657 unsigned int i, j; 1658 1659 /* Free all the Rx ring sk_buffs */ 1660 for (i = 0; i < rx_ring->count; i++) { 1661 buffer_info = &rx_ring->buffer_info[i]; 1662 if (buffer_info->dma) { 1663 if (adapter->clean_rx == e1000_clean_rx_irq) 1664 dma_unmap_single(&pdev->dev, buffer_info->dma, 1665 adapter->rx_buffer_len, 1666 DMA_FROM_DEVICE); 1667 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1668 dma_unmap_page(&pdev->dev, buffer_info->dma, 1669 PAGE_SIZE, 1670 DMA_FROM_DEVICE); 1671 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1672 dma_unmap_single(&pdev->dev, buffer_info->dma, 1673 adapter->rx_ps_bsize0, 1674 DMA_FROM_DEVICE); 1675 buffer_info->dma = 0; 1676 } 1677 1678 if (buffer_info->page) { 1679 put_page(buffer_info->page); 1680 buffer_info->page = NULL; 1681 } 1682 1683 if (buffer_info->skb) { 1684 dev_kfree_skb(buffer_info->skb); 1685 buffer_info->skb = NULL; 1686 } 1687 1688 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1689 ps_page = &buffer_info->ps_pages[j]; 1690 if (!ps_page->page) 1691 break; 1692 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1693 DMA_FROM_DEVICE); 1694 ps_page->dma = 0; 1695 put_page(ps_page->page); 1696 ps_page->page = NULL; 1697 } 1698 } 1699 1700 /* there also may be some cached data from a chained receive */ 1701 if (rx_ring->rx_skb_top) { 1702 dev_kfree_skb(rx_ring->rx_skb_top); 1703 rx_ring->rx_skb_top = NULL; 1704 } 1705 1706 /* Zero out the descriptor ring */ 1707 memset(rx_ring->desc, 0, rx_ring->size); 1708 1709 rx_ring->next_to_clean = 0; 1710 rx_ring->next_to_use = 0; 1711 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1712 1713 writel(0, rx_ring->head); 1714 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 1715 e1000e_update_rdt_wa(rx_ring, 0); 1716 else 1717 writel(0, rx_ring->tail); 1718 } 1719 1720 static void e1000e_downshift_workaround(struct work_struct *work) 1721 { 1722 struct e1000_adapter *adapter = container_of(work, 1723 struct e1000_adapter, downshift_task); 1724 1725 if (test_bit(__E1000_DOWN, &adapter->state)) 1726 return; 1727 1728 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1729 } 1730 1731 /** 1732 * e1000_intr_msi - Interrupt Handler 1733 * @irq: interrupt number 1734 * @data: pointer to a network interface device structure 1735 **/ 1736 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1737 { 1738 struct net_device *netdev = data; 1739 struct e1000_adapter *adapter = netdev_priv(netdev); 1740 struct e1000_hw *hw = &adapter->hw; 1741 u32 icr = er32(ICR); 1742 1743 /* read ICR disables interrupts using IAM */ 1744 if (icr & E1000_ICR_LSC) { 1745 hw->mac.get_link_status = true; 1746 /* ICH8 workaround-- Call gig speed drop workaround on cable 1747 * disconnect (LSC) before accessing any PHY registers 1748 */ 1749 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1750 (!(er32(STATUS) & E1000_STATUS_LU))) 1751 schedule_work(&adapter->downshift_task); 1752 1753 /* 80003ES2LAN workaround-- For packet buffer work-around on 1754 * link down event; disable receives here in the ISR and reset 1755 * adapter in watchdog 1756 */ 1757 if (netif_carrier_ok(netdev) && 1758 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1759 /* disable receives */ 1760 u32 rctl = er32(RCTL); 1761 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1762 adapter->flags |= FLAG_RESTART_NOW; 1763 } 1764 /* guard against interrupt when we're going down */ 1765 if (!test_bit(__E1000_DOWN, &adapter->state)) 1766 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1767 } 1768 1769 /* Reset on uncorrectable ECC error */ 1770 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1771 u32 pbeccsts = er32(PBECCSTS); 1772 1773 adapter->corr_errors += 1774 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1775 adapter->uncorr_errors += 1776 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1777 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1778 1779 /* Do the reset outside of interrupt context */ 1780 schedule_work(&adapter->reset_task); 1781 1782 /* return immediately since reset is imminent */ 1783 return IRQ_HANDLED; 1784 } 1785 1786 if (napi_schedule_prep(&adapter->napi)) { 1787 adapter->total_tx_bytes = 0; 1788 adapter->total_tx_packets = 0; 1789 adapter->total_rx_bytes = 0; 1790 adapter->total_rx_packets = 0; 1791 __napi_schedule(&adapter->napi); 1792 } 1793 1794 return IRQ_HANDLED; 1795 } 1796 1797 /** 1798 * e1000_intr - Interrupt Handler 1799 * @irq: interrupt number 1800 * @data: pointer to a network interface device structure 1801 **/ 1802 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1803 { 1804 struct net_device *netdev = data; 1805 struct e1000_adapter *adapter = netdev_priv(netdev); 1806 struct e1000_hw *hw = &adapter->hw; 1807 u32 rctl, icr = er32(ICR); 1808 1809 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1810 return IRQ_NONE; /* Not our interrupt */ 1811 1812 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1813 * not set, then the adapter didn't send an interrupt 1814 */ 1815 if (!(icr & E1000_ICR_INT_ASSERTED)) 1816 return IRQ_NONE; 1817 1818 /* Interrupt Auto-Mask...upon reading ICR, 1819 * interrupts are masked. No need for the 1820 * IMC write 1821 */ 1822 1823 if (icr & E1000_ICR_LSC) { 1824 hw->mac.get_link_status = true; 1825 /* ICH8 workaround-- Call gig speed drop workaround on cable 1826 * disconnect (LSC) before accessing any PHY registers 1827 */ 1828 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1829 (!(er32(STATUS) & E1000_STATUS_LU))) 1830 schedule_work(&adapter->downshift_task); 1831 1832 /* 80003ES2LAN workaround-- 1833 * For packet buffer work-around on link down event; 1834 * disable receives here in the ISR and 1835 * reset adapter in watchdog 1836 */ 1837 if (netif_carrier_ok(netdev) && 1838 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1839 /* disable receives */ 1840 rctl = er32(RCTL); 1841 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1842 adapter->flags |= FLAG_RESTART_NOW; 1843 } 1844 /* guard against interrupt when we're going down */ 1845 if (!test_bit(__E1000_DOWN, &adapter->state)) 1846 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1847 } 1848 1849 /* Reset on uncorrectable ECC error */ 1850 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) { 1851 u32 pbeccsts = er32(PBECCSTS); 1852 1853 adapter->corr_errors += 1854 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1855 adapter->uncorr_errors += 1856 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1857 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1858 1859 /* Do the reset outside of interrupt context */ 1860 schedule_work(&adapter->reset_task); 1861 1862 /* return immediately since reset is imminent */ 1863 return IRQ_HANDLED; 1864 } 1865 1866 if (napi_schedule_prep(&adapter->napi)) { 1867 adapter->total_tx_bytes = 0; 1868 adapter->total_tx_packets = 0; 1869 adapter->total_rx_bytes = 0; 1870 adapter->total_rx_packets = 0; 1871 __napi_schedule(&adapter->napi); 1872 } 1873 1874 return IRQ_HANDLED; 1875 } 1876 1877 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1878 { 1879 struct net_device *netdev = data; 1880 struct e1000_adapter *adapter = netdev_priv(netdev); 1881 struct e1000_hw *hw = &adapter->hw; 1882 u32 icr = er32(ICR); 1883 1884 if (!(icr & E1000_ICR_INT_ASSERTED)) { 1885 if (!test_bit(__E1000_DOWN, &adapter->state)) 1886 ew32(IMS, E1000_IMS_OTHER); 1887 return IRQ_NONE; 1888 } 1889 1890 if (icr & adapter->eiac_mask) 1891 ew32(ICS, (icr & adapter->eiac_mask)); 1892 1893 if (icr & E1000_ICR_OTHER) { 1894 if (!(icr & E1000_ICR_LSC)) 1895 goto no_link_interrupt; 1896 hw->mac.get_link_status = true; 1897 /* guard against interrupt when we're going down */ 1898 if (!test_bit(__E1000_DOWN, &adapter->state)) 1899 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1900 } 1901 1902 no_link_interrupt: 1903 if (!test_bit(__E1000_DOWN, &adapter->state)) 1904 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1905 1906 return IRQ_HANDLED; 1907 } 1908 1909 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1910 { 1911 struct net_device *netdev = data; 1912 struct e1000_adapter *adapter = netdev_priv(netdev); 1913 struct e1000_hw *hw = &adapter->hw; 1914 struct e1000_ring *tx_ring = adapter->tx_ring; 1915 1916 1917 adapter->total_tx_bytes = 0; 1918 adapter->total_tx_packets = 0; 1919 1920 if (!e1000_clean_tx_irq(tx_ring)) 1921 /* Ring was not completely cleaned, so fire another interrupt */ 1922 ew32(ICS, tx_ring->ims_val); 1923 1924 return IRQ_HANDLED; 1925 } 1926 1927 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1928 { 1929 struct net_device *netdev = data; 1930 struct e1000_adapter *adapter = netdev_priv(netdev); 1931 struct e1000_ring *rx_ring = adapter->rx_ring; 1932 1933 /* Write the ITR value calculated at the end of the 1934 * previous interrupt. 1935 */ 1936 if (rx_ring->set_itr) { 1937 writel(1000000000 / (rx_ring->itr_val * 256), 1938 rx_ring->itr_register); 1939 rx_ring->set_itr = 0; 1940 } 1941 1942 if (napi_schedule_prep(&adapter->napi)) { 1943 adapter->total_rx_bytes = 0; 1944 adapter->total_rx_packets = 0; 1945 __napi_schedule(&adapter->napi); 1946 } 1947 return IRQ_HANDLED; 1948 } 1949 1950 /** 1951 * e1000_configure_msix - Configure MSI-X hardware 1952 * 1953 * e1000_configure_msix sets up the hardware to properly 1954 * generate MSI-X interrupts. 1955 **/ 1956 static void e1000_configure_msix(struct e1000_adapter *adapter) 1957 { 1958 struct e1000_hw *hw = &adapter->hw; 1959 struct e1000_ring *rx_ring = adapter->rx_ring; 1960 struct e1000_ring *tx_ring = adapter->tx_ring; 1961 int vector = 0; 1962 u32 ctrl_ext, ivar = 0; 1963 1964 adapter->eiac_mask = 0; 1965 1966 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1967 if (hw->mac.type == e1000_82574) { 1968 u32 rfctl = er32(RFCTL); 1969 rfctl |= E1000_RFCTL_ACK_DIS; 1970 ew32(RFCTL, rfctl); 1971 } 1972 1973 #define E1000_IVAR_INT_ALLOC_VALID 0x8 1974 /* Configure Rx vector */ 1975 rx_ring->ims_val = E1000_IMS_RXQ0; 1976 adapter->eiac_mask |= rx_ring->ims_val; 1977 if (rx_ring->itr_val) 1978 writel(1000000000 / (rx_ring->itr_val * 256), 1979 rx_ring->itr_register); 1980 else 1981 writel(1, rx_ring->itr_register); 1982 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 1983 1984 /* Configure Tx vector */ 1985 tx_ring->ims_val = E1000_IMS_TXQ0; 1986 vector++; 1987 if (tx_ring->itr_val) 1988 writel(1000000000 / (tx_ring->itr_val * 256), 1989 tx_ring->itr_register); 1990 else 1991 writel(1, tx_ring->itr_register); 1992 adapter->eiac_mask |= tx_ring->ims_val; 1993 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 1994 1995 /* set vector for Other Causes, e.g. link changes */ 1996 vector++; 1997 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 1998 if (rx_ring->itr_val) 1999 writel(1000000000 / (rx_ring->itr_val * 256), 2000 hw->hw_addr + E1000_EITR_82574(vector)); 2001 else 2002 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2003 2004 /* Cause Tx interrupts on every write back */ 2005 ivar |= (1 << 31); 2006 2007 ew32(IVAR, ivar); 2008 2009 /* enable MSI-X PBA support */ 2010 ctrl_ext = er32(CTRL_EXT); 2011 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; 2012 2013 /* Auto-Mask Other interrupts upon ICR read */ 2014 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); 2015 ctrl_ext |= E1000_CTRL_EXT_EIAME; 2016 ew32(CTRL_EXT, ctrl_ext); 2017 e1e_flush(); 2018 } 2019 2020 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2021 { 2022 if (adapter->msix_entries) { 2023 pci_disable_msix(adapter->pdev); 2024 kfree(adapter->msix_entries); 2025 adapter->msix_entries = NULL; 2026 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2027 pci_disable_msi(adapter->pdev); 2028 adapter->flags &= ~FLAG_MSI_ENABLED; 2029 } 2030 } 2031 2032 /** 2033 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2034 * 2035 * Attempt to configure interrupts using the best available 2036 * capabilities of the hardware and kernel. 2037 **/ 2038 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2039 { 2040 int err; 2041 int i; 2042 2043 switch (adapter->int_mode) { 2044 case E1000E_INT_MODE_MSIX: 2045 if (adapter->flags & FLAG_HAS_MSIX) { 2046 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2047 adapter->msix_entries = kcalloc(adapter->num_vectors, 2048 sizeof(struct msix_entry), 2049 GFP_KERNEL); 2050 if (adapter->msix_entries) { 2051 for (i = 0; i < adapter->num_vectors; i++) 2052 adapter->msix_entries[i].entry = i; 2053 2054 err = pci_enable_msix(adapter->pdev, 2055 adapter->msix_entries, 2056 adapter->num_vectors); 2057 if (err == 0) 2058 return; 2059 } 2060 /* MSI-X failed, so fall through and try MSI */ 2061 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2062 e1000e_reset_interrupt_capability(adapter); 2063 } 2064 adapter->int_mode = E1000E_INT_MODE_MSI; 2065 /* Fall through */ 2066 case E1000E_INT_MODE_MSI: 2067 if (!pci_enable_msi(adapter->pdev)) { 2068 adapter->flags |= FLAG_MSI_ENABLED; 2069 } else { 2070 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2071 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2072 } 2073 /* Fall through */ 2074 case E1000E_INT_MODE_LEGACY: 2075 /* Don't do anything; this is the system default */ 2076 break; 2077 } 2078 2079 /* store the number of vectors being used */ 2080 adapter->num_vectors = 1; 2081 } 2082 2083 /** 2084 * e1000_request_msix - Initialize MSI-X interrupts 2085 * 2086 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2087 * kernel. 2088 **/ 2089 static int e1000_request_msix(struct e1000_adapter *adapter) 2090 { 2091 struct net_device *netdev = adapter->netdev; 2092 int err = 0, vector = 0; 2093 2094 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2095 snprintf(adapter->rx_ring->name, 2096 sizeof(adapter->rx_ring->name) - 1, 2097 "%s-rx-0", netdev->name); 2098 else 2099 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2100 err = request_irq(adapter->msix_entries[vector].vector, 2101 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2102 netdev); 2103 if (err) 2104 return err; 2105 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2106 E1000_EITR_82574(vector); 2107 adapter->rx_ring->itr_val = adapter->itr; 2108 vector++; 2109 2110 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2111 snprintf(adapter->tx_ring->name, 2112 sizeof(adapter->tx_ring->name) - 1, 2113 "%s-tx-0", netdev->name); 2114 else 2115 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2116 err = request_irq(adapter->msix_entries[vector].vector, 2117 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2118 netdev); 2119 if (err) 2120 return err; 2121 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2122 E1000_EITR_82574(vector); 2123 adapter->tx_ring->itr_val = adapter->itr; 2124 vector++; 2125 2126 err = request_irq(adapter->msix_entries[vector].vector, 2127 e1000_msix_other, 0, netdev->name, netdev); 2128 if (err) 2129 return err; 2130 2131 e1000_configure_msix(adapter); 2132 2133 return 0; 2134 } 2135 2136 /** 2137 * e1000_request_irq - initialize interrupts 2138 * 2139 * Attempts to configure interrupts using the best available 2140 * capabilities of the hardware and kernel. 2141 **/ 2142 static int e1000_request_irq(struct e1000_adapter *adapter) 2143 { 2144 struct net_device *netdev = adapter->netdev; 2145 int err; 2146 2147 if (adapter->msix_entries) { 2148 err = e1000_request_msix(adapter); 2149 if (!err) 2150 return err; 2151 /* fall back to MSI */ 2152 e1000e_reset_interrupt_capability(adapter); 2153 adapter->int_mode = E1000E_INT_MODE_MSI; 2154 e1000e_set_interrupt_capability(adapter); 2155 } 2156 if (adapter->flags & FLAG_MSI_ENABLED) { 2157 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2158 netdev->name, netdev); 2159 if (!err) 2160 return err; 2161 2162 /* fall back to legacy interrupt */ 2163 e1000e_reset_interrupt_capability(adapter); 2164 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2165 } 2166 2167 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2168 netdev->name, netdev); 2169 if (err) 2170 e_err("Unable to allocate interrupt, Error: %d\n", err); 2171 2172 return err; 2173 } 2174 2175 static void e1000_free_irq(struct e1000_adapter *adapter) 2176 { 2177 struct net_device *netdev = adapter->netdev; 2178 2179 if (adapter->msix_entries) { 2180 int vector = 0; 2181 2182 free_irq(adapter->msix_entries[vector].vector, netdev); 2183 vector++; 2184 2185 free_irq(adapter->msix_entries[vector].vector, netdev); 2186 vector++; 2187 2188 /* Other Causes interrupt vector */ 2189 free_irq(adapter->msix_entries[vector].vector, netdev); 2190 return; 2191 } 2192 2193 free_irq(adapter->pdev->irq, netdev); 2194 } 2195 2196 /** 2197 * e1000_irq_disable - Mask off interrupt generation on the NIC 2198 **/ 2199 static void e1000_irq_disable(struct e1000_adapter *adapter) 2200 { 2201 struct e1000_hw *hw = &adapter->hw; 2202 2203 ew32(IMC, ~0); 2204 if (adapter->msix_entries) 2205 ew32(EIAC_82574, 0); 2206 e1e_flush(); 2207 2208 if (adapter->msix_entries) { 2209 int i; 2210 for (i = 0; i < adapter->num_vectors; i++) 2211 synchronize_irq(adapter->msix_entries[i].vector); 2212 } else { 2213 synchronize_irq(adapter->pdev->irq); 2214 } 2215 } 2216 2217 /** 2218 * e1000_irq_enable - Enable default interrupt generation settings 2219 **/ 2220 static void e1000_irq_enable(struct e1000_adapter *adapter) 2221 { 2222 struct e1000_hw *hw = &adapter->hw; 2223 2224 if (adapter->msix_entries) { 2225 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2226 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); 2227 } else if (hw->mac.type == e1000_pch_lpt) { 2228 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2229 } else { 2230 ew32(IMS, IMS_ENABLE_MASK); 2231 } 2232 e1e_flush(); 2233 } 2234 2235 /** 2236 * e1000e_get_hw_control - get control of the h/w from f/w 2237 * @adapter: address of board private structure 2238 * 2239 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2240 * For ASF and Pass Through versions of f/w this means that 2241 * the driver is loaded. For AMT version (only with 82573) 2242 * of the f/w this means that the network i/f is open. 2243 **/ 2244 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2245 { 2246 struct e1000_hw *hw = &adapter->hw; 2247 u32 ctrl_ext; 2248 u32 swsm; 2249 2250 /* Let firmware know the driver has taken over */ 2251 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2252 swsm = er32(SWSM); 2253 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2254 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2255 ctrl_ext = er32(CTRL_EXT); 2256 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2257 } 2258 } 2259 2260 /** 2261 * e1000e_release_hw_control - release control of the h/w to f/w 2262 * @adapter: address of board private structure 2263 * 2264 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2265 * For ASF and Pass Through versions of f/w this means that the 2266 * driver is no longer loaded. For AMT version (only with 82573) i 2267 * of the f/w this means that the network i/f is closed. 2268 * 2269 **/ 2270 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2271 { 2272 struct e1000_hw *hw = &adapter->hw; 2273 u32 ctrl_ext; 2274 u32 swsm; 2275 2276 /* Let firmware taken over control of h/w */ 2277 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2278 swsm = er32(SWSM); 2279 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2280 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2281 ctrl_ext = er32(CTRL_EXT); 2282 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2283 } 2284 } 2285 2286 /** 2287 * e1000_alloc_ring_dma - allocate memory for a ring structure 2288 **/ 2289 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2290 struct e1000_ring *ring) 2291 { 2292 struct pci_dev *pdev = adapter->pdev; 2293 2294 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2295 GFP_KERNEL); 2296 if (!ring->desc) 2297 return -ENOMEM; 2298 2299 return 0; 2300 } 2301 2302 /** 2303 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2304 * @tx_ring: Tx descriptor ring 2305 * 2306 * Return 0 on success, negative on failure 2307 **/ 2308 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2309 { 2310 struct e1000_adapter *adapter = tx_ring->adapter; 2311 int err = -ENOMEM, size; 2312 2313 size = sizeof(struct e1000_buffer) * tx_ring->count; 2314 tx_ring->buffer_info = vzalloc(size); 2315 if (!tx_ring->buffer_info) 2316 goto err; 2317 2318 /* round up to nearest 4K */ 2319 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2320 tx_ring->size = ALIGN(tx_ring->size, 4096); 2321 2322 err = e1000_alloc_ring_dma(adapter, tx_ring); 2323 if (err) 2324 goto err; 2325 2326 tx_ring->next_to_use = 0; 2327 tx_ring->next_to_clean = 0; 2328 2329 return 0; 2330 err: 2331 vfree(tx_ring->buffer_info); 2332 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2333 return err; 2334 } 2335 2336 /** 2337 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2338 * @rx_ring: Rx descriptor ring 2339 * 2340 * Returns 0 on success, negative on failure 2341 **/ 2342 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2343 { 2344 struct e1000_adapter *adapter = rx_ring->adapter; 2345 struct e1000_buffer *buffer_info; 2346 int i, size, desc_len, err = -ENOMEM; 2347 2348 size = sizeof(struct e1000_buffer) * rx_ring->count; 2349 rx_ring->buffer_info = vzalloc(size); 2350 if (!rx_ring->buffer_info) 2351 goto err; 2352 2353 for (i = 0; i < rx_ring->count; i++) { 2354 buffer_info = &rx_ring->buffer_info[i]; 2355 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2356 sizeof(struct e1000_ps_page), 2357 GFP_KERNEL); 2358 if (!buffer_info->ps_pages) 2359 goto err_pages; 2360 } 2361 2362 desc_len = sizeof(union e1000_rx_desc_packet_split); 2363 2364 /* Round up to nearest 4K */ 2365 rx_ring->size = rx_ring->count * desc_len; 2366 rx_ring->size = ALIGN(rx_ring->size, 4096); 2367 2368 err = e1000_alloc_ring_dma(adapter, rx_ring); 2369 if (err) 2370 goto err_pages; 2371 2372 rx_ring->next_to_clean = 0; 2373 rx_ring->next_to_use = 0; 2374 rx_ring->rx_skb_top = NULL; 2375 2376 return 0; 2377 2378 err_pages: 2379 for (i = 0; i < rx_ring->count; i++) { 2380 buffer_info = &rx_ring->buffer_info[i]; 2381 kfree(buffer_info->ps_pages); 2382 } 2383 err: 2384 vfree(rx_ring->buffer_info); 2385 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2386 return err; 2387 } 2388 2389 /** 2390 * e1000_clean_tx_ring - Free Tx Buffers 2391 * @tx_ring: Tx descriptor ring 2392 **/ 2393 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2394 { 2395 struct e1000_adapter *adapter = tx_ring->adapter; 2396 struct e1000_buffer *buffer_info; 2397 unsigned long size; 2398 unsigned int i; 2399 2400 for (i = 0; i < tx_ring->count; i++) { 2401 buffer_info = &tx_ring->buffer_info[i]; 2402 e1000_put_txbuf(tx_ring, buffer_info); 2403 } 2404 2405 netdev_reset_queue(adapter->netdev); 2406 size = sizeof(struct e1000_buffer) * tx_ring->count; 2407 memset(tx_ring->buffer_info, 0, size); 2408 2409 memset(tx_ring->desc, 0, tx_ring->size); 2410 2411 tx_ring->next_to_use = 0; 2412 tx_ring->next_to_clean = 0; 2413 2414 writel(0, tx_ring->head); 2415 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2416 e1000e_update_tdt_wa(tx_ring, 0); 2417 else 2418 writel(0, tx_ring->tail); 2419 } 2420 2421 /** 2422 * e1000e_free_tx_resources - Free Tx Resources per Queue 2423 * @tx_ring: Tx descriptor ring 2424 * 2425 * Free all transmit software resources 2426 **/ 2427 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2428 { 2429 struct e1000_adapter *adapter = tx_ring->adapter; 2430 struct pci_dev *pdev = adapter->pdev; 2431 2432 e1000_clean_tx_ring(tx_ring); 2433 2434 vfree(tx_ring->buffer_info); 2435 tx_ring->buffer_info = NULL; 2436 2437 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2438 tx_ring->dma); 2439 tx_ring->desc = NULL; 2440 } 2441 2442 /** 2443 * e1000e_free_rx_resources - Free Rx Resources 2444 * @rx_ring: Rx descriptor ring 2445 * 2446 * Free all receive software resources 2447 **/ 2448 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2449 { 2450 struct e1000_adapter *adapter = rx_ring->adapter; 2451 struct pci_dev *pdev = adapter->pdev; 2452 int i; 2453 2454 e1000_clean_rx_ring(rx_ring); 2455 2456 for (i = 0; i < rx_ring->count; i++) 2457 kfree(rx_ring->buffer_info[i].ps_pages); 2458 2459 vfree(rx_ring->buffer_info); 2460 rx_ring->buffer_info = NULL; 2461 2462 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2463 rx_ring->dma); 2464 rx_ring->desc = NULL; 2465 } 2466 2467 /** 2468 * e1000_update_itr - update the dynamic ITR value based on statistics 2469 * @adapter: pointer to adapter 2470 * @itr_setting: current adapter->itr 2471 * @packets: the number of packets during this measurement interval 2472 * @bytes: the number of bytes during this measurement interval 2473 * 2474 * Stores a new ITR value based on packets and byte 2475 * counts during the last interrupt. The advantage of per interrupt 2476 * computation is faster updates and more accurate ITR for the current 2477 * traffic pattern. Constants in this function were computed 2478 * based on theoretical maximum wire speed and thresholds were set based 2479 * on testing data as well as attempting to minimize response time 2480 * while increasing bulk throughput. This functionality is controlled 2481 * by the InterruptThrottleRate module parameter. 2482 **/ 2483 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2484 { 2485 unsigned int retval = itr_setting; 2486 2487 if (packets == 0) 2488 return itr_setting; 2489 2490 switch (itr_setting) { 2491 case lowest_latency: 2492 /* handle TSO and jumbo frames */ 2493 if (bytes/packets > 8000) 2494 retval = bulk_latency; 2495 else if ((packets < 5) && (bytes > 512)) 2496 retval = low_latency; 2497 break; 2498 case low_latency: /* 50 usec aka 20000 ints/s */ 2499 if (bytes > 10000) { 2500 /* this if handles the TSO accounting */ 2501 if (bytes/packets > 8000) 2502 retval = bulk_latency; 2503 else if ((packets < 10) || ((bytes/packets) > 1200)) 2504 retval = bulk_latency; 2505 else if ((packets > 35)) 2506 retval = lowest_latency; 2507 } else if (bytes/packets > 2000) { 2508 retval = bulk_latency; 2509 } else if (packets <= 2 && bytes < 512) { 2510 retval = lowest_latency; 2511 } 2512 break; 2513 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2514 if (bytes > 25000) { 2515 if (packets > 35) 2516 retval = low_latency; 2517 } else if (bytes < 6000) { 2518 retval = low_latency; 2519 } 2520 break; 2521 } 2522 2523 return retval; 2524 } 2525 2526 static void e1000_set_itr(struct e1000_adapter *adapter) 2527 { 2528 u16 current_itr; 2529 u32 new_itr = adapter->itr; 2530 2531 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2532 if (adapter->link_speed != SPEED_1000) { 2533 current_itr = 0; 2534 new_itr = 4000; 2535 goto set_itr_now; 2536 } 2537 2538 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2539 new_itr = 0; 2540 goto set_itr_now; 2541 } 2542 2543 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2544 adapter->total_tx_packets, 2545 adapter->total_tx_bytes); 2546 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2547 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2548 adapter->tx_itr = low_latency; 2549 2550 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2551 adapter->total_rx_packets, 2552 adapter->total_rx_bytes); 2553 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2554 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2555 adapter->rx_itr = low_latency; 2556 2557 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2558 2559 switch (current_itr) { 2560 /* counts and packets in update_itr are dependent on these numbers */ 2561 case lowest_latency: 2562 new_itr = 70000; 2563 break; 2564 case low_latency: 2565 new_itr = 20000; /* aka hwitr = ~200 */ 2566 break; 2567 case bulk_latency: 2568 new_itr = 4000; 2569 break; 2570 default: 2571 break; 2572 } 2573 2574 set_itr_now: 2575 if (new_itr != adapter->itr) { 2576 /* this attempts to bias the interrupt rate towards Bulk 2577 * by adding intermediate steps when interrupt rate is 2578 * increasing 2579 */ 2580 new_itr = new_itr > adapter->itr ? 2581 min(adapter->itr + (new_itr >> 2), new_itr) : 2582 new_itr; 2583 adapter->itr = new_itr; 2584 adapter->rx_ring->itr_val = new_itr; 2585 if (adapter->msix_entries) 2586 adapter->rx_ring->set_itr = 1; 2587 else 2588 e1000e_write_itr(adapter, new_itr); 2589 } 2590 } 2591 2592 /** 2593 * e1000e_write_itr - write the ITR value to the appropriate registers 2594 * @adapter: address of board private structure 2595 * @itr: new ITR value to program 2596 * 2597 * e1000e_write_itr determines if the adapter is in MSI-X mode 2598 * and, if so, writes the EITR registers with the ITR value. 2599 * Otherwise, it writes the ITR value into the ITR register. 2600 **/ 2601 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2602 { 2603 struct e1000_hw *hw = &adapter->hw; 2604 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2605 2606 if (adapter->msix_entries) { 2607 int vector; 2608 2609 for (vector = 0; vector < adapter->num_vectors; vector++) 2610 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2611 } else { 2612 ew32(ITR, new_itr); 2613 } 2614 } 2615 2616 /** 2617 * e1000_alloc_queues - Allocate memory for all rings 2618 * @adapter: board private structure to initialize 2619 **/ 2620 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2621 { 2622 int size = sizeof(struct e1000_ring); 2623 2624 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2625 if (!adapter->tx_ring) 2626 goto err; 2627 adapter->tx_ring->count = adapter->tx_ring_count; 2628 adapter->tx_ring->adapter = adapter; 2629 2630 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2631 if (!adapter->rx_ring) 2632 goto err; 2633 adapter->rx_ring->count = adapter->rx_ring_count; 2634 adapter->rx_ring->adapter = adapter; 2635 2636 return 0; 2637 err: 2638 e_err("Unable to allocate memory for queues\n"); 2639 kfree(adapter->rx_ring); 2640 kfree(adapter->tx_ring); 2641 return -ENOMEM; 2642 } 2643 2644 /** 2645 * e1000e_poll - NAPI Rx polling callback 2646 * @napi: struct associated with this polling callback 2647 * @weight: number of packets driver is allowed to process this poll 2648 **/ 2649 static int e1000e_poll(struct napi_struct *napi, int weight) 2650 { 2651 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2652 napi); 2653 struct e1000_hw *hw = &adapter->hw; 2654 struct net_device *poll_dev = adapter->netdev; 2655 int tx_cleaned = 1, work_done = 0; 2656 2657 adapter = netdev_priv(poll_dev); 2658 2659 if (!adapter->msix_entries || 2660 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2661 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2662 2663 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2664 2665 if (!tx_cleaned) 2666 work_done = weight; 2667 2668 /* If weight not fully consumed, exit the polling mode */ 2669 if (work_done < weight) { 2670 if (adapter->itr_setting & 3) 2671 e1000_set_itr(adapter); 2672 napi_complete(napi); 2673 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2674 if (adapter->msix_entries) 2675 ew32(IMS, adapter->rx_ring->ims_val); 2676 else 2677 e1000_irq_enable(adapter); 2678 } 2679 } 2680 2681 return work_done; 2682 } 2683 2684 static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 2685 { 2686 struct e1000_adapter *adapter = netdev_priv(netdev); 2687 struct e1000_hw *hw = &adapter->hw; 2688 u32 vfta, index; 2689 2690 /* don't update vlan cookie if already programmed */ 2691 if ((adapter->hw.mng_cookie.status & 2692 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2693 (vid == adapter->mng_vlan_id)) 2694 return 0; 2695 2696 /* add VID to filter table */ 2697 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2698 index = (vid >> 5) & 0x7F; 2699 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2700 vfta |= (1 << (vid & 0x1F)); 2701 hw->mac.ops.write_vfta(hw, index, vfta); 2702 } 2703 2704 set_bit(vid, adapter->active_vlans); 2705 2706 return 0; 2707 } 2708 2709 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 2710 { 2711 struct e1000_adapter *adapter = netdev_priv(netdev); 2712 struct e1000_hw *hw = &adapter->hw; 2713 u32 vfta, index; 2714 2715 if ((adapter->hw.mng_cookie.status & 2716 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2717 (vid == adapter->mng_vlan_id)) { 2718 /* release control to f/w */ 2719 e1000e_release_hw_control(adapter); 2720 return 0; 2721 } 2722 2723 /* remove VID from filter table */ 2724 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2725 index = (vid >> 5) & 0x7F; 2726 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2727 vfta &= ~(1 << (vid & 0x1F)); 2728 hw->mac.ops.write_vfta(hw, index, vfta); 2729 } 2730 2731 clear_bit(vid, adapter->active_vlans); 2732 2733 return 0; 2734 } 2735 2736 /** 2737 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2738 * @adapter: board private structure to initialize 2739 **/ 2740 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2741 { 2742 struct net_device *netdev = adapter->netdev; 2743 struct e1000_hw *hw = &adapter->hw; 2744 u32 rctl; 2745 2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2747 /* disable VLAN receive filtering */ 2748 rctl = er32(RCTL); 2749 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2750 ew32(RCTL, rctl); 2751 2752 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2753 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 2754 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2755 } 2756 } 2757 } 2758 2759 /** 2760 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2761 * @adapter: board private structure to initialize 2762 **/ 2763 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2764 { 2765 struct e1000_hw *hw = &adapter->hw; 2766 u32 rctl; 2767 2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2769 /* enable VLAN receive filtering */ 2770 rctl = er32(RCTL); 2771 rctl |= E1000_RCTL_VFE; 2772 rctl &= ~E1000_RCTL_CFIEN; 2773 ew32(RCTL, rctl); 2774 } 2775 } 2776 2777 /** 2778 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping 2779 * @adapter: board private structure to initialize 2780 **/ 2781 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2782 { 2783 struct e1000_hw *hw = &adapter->hw; 2784 u32 ctrl; 2785 2786 /* disable VLAN tag insert/strip */ 2787 ctrl = er32(CTRL); 2788 ctrl &= ~E1000_CTRL_VME; 2789 ew32(CTRL, ctrl); 2790 } 2791 2792 /** 2793 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2794 * @adapter: board private structure to initialize 2795 **/ 2796 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2797 { 2798 struct e1000_hw *hw = &adapter->hw; 2799 u32 ctrl; 2800 2801 /* enable VLAN tag insert/strip */ 2802 ctrl = er32(CTRL); 2803 ctrl |= E1000_CTRL_VME; 2804 ew32(CTRL, ctrl); 2805 } 2806 2807 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2808 { 2809 struct net_device *netdev = adapter->netdev; 2810 u16 vid = adapter->hw.mng_cookie.vlan_id; 2811 u16 old_vid = adapter->mng_vlan_id; 2812 2813 if (adapter->hw.mng_cookie.status & 2814 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2815 e1000_vlan_rx_add_vid(netdev, vid); 2816 adapter->mng_vlan_id = vid; 2817 } 2818 2819 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2820 e1000_vlan_rx_kill_vid(netdev, old_vid); 2821 } 2822 2823 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2824 { 2825 u16 vid; 2826 2827 e1000_vlan_rx_add_vid(adapter->netdev, 0); 2828 2829 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2830 e1000_vlan_rx_add_vid(adapter->netdev, vid); 2831 } 2832 2833 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2834 { 2835 struct e1000_hw *hw = &adapter->hw; 2836 u32 manc, manc2h, mdef, i, j; 2837 2838 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2839 return; 2840 2841 manc = er32(MANC); 2842 2843 /* enable receiving management packets to the host. this will probably 2844 * generate destination unreachable messages from the host OS, but 2845 * the packets will be handled on SMBUS 2846 */ 2847 manc |= E1000_MANC_EN_MNG2HOST; 2848 manc2h = er32(MANC2H); 2849 2850 switch (hw->mac.type) { 2851 default: 2852 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2853 break; 2854 case e1000_82574: 2855 case e1000_82583: 2856 /* Check if IPMI pass-through decision filter already exists; 2857 * if so, enable it. 2858 */ 2859 for (i = 0, j = 0; i < 8; i++) { 2860 mdef = er32(MDEF(i)); 2861 2862 /* Ignore filters with anything other than IPMI ports */ 2863 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2864 continue; 2865 2866 /* Enable this decision filter in MANC2H */ 2867 if (mdef) 2868 manc2h |= (1 << i); 2869 2870 j |= mdef; 2871 } 2872 2873 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2874 break; 2875 2876 /* Create new decision filter in an empty filter */ 2877 for (i = 0, j = 0; i < 8; i++) 2878 if (er32(MDEF(i)) == 0) { 2879 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2880 E1000_MDEF_PORT_664)); 2881 manc2h |= (1 << 1); 2882 j++; 2883 break; 2884 } 2885 2886 if (!j) 2887 e_warn("Unable to create IPMI pass-through filter\n"); 2888 break; 2889 } 2890 2891 ew32(MANC2H, manc2h); 2892 ew32(MANC, manc); 2893 } 2894 2895 /** 2896 * e1000_configure_tx - Configure Transmit Unit after Reset 2897 * @adapter: board private structure 2898 * 2899 * Configure the Tx unit of the MAC after a reset. 2900 **/ 2901 static void e1000_configure_tx(struct e1000_adapter *adapter) 2902 { 2903 struct e1000_hw *hw = &adapter->hw; 2904 struct e1000_ring *tx_ring = adapter->tx_ring; 2905 u64 tdba; 2906 u32 tdlen, tarc; 2907 2908 /* Setup the HW Tx Head and Tail descriptor pointers */ 2909 tdba = tx_ring->dma; 2910 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2911 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2912 ew32(TDBAH(0), (tdba >> 32)); 2913 ew32(TDLEN(0), tdlen); 2914 ew32(TDH(0), 0); 2915 ew32(TDT(0), 0); 2916 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2917 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2918 2919 /* Set the Tx Interrupt Delay register */ 2920 ew32(TIDV, adapter->tx_int_delay); 2921 /* Tx irq moderation */ 2922 ew32(TADV, adapter->tx_abs_int_delay); 2923 2924 if (adapter->flags2 & FLAG2_DMA_BURST) { 2925 u32 txdctl = er32(TXDCTL(0)); 2926 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2927 E1000_TXDCTL_WTHRESH); 2928 /* set up some performance related parameters to encourage the 2929 * hardware to use the bus more efficiently in bursts, depends 2930 * on the tx_int_delay to be enabled, 2931 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2932 * hthresh = 1 ==> prefetch when one or more available 2933 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2934 * BEWARE: this seems to work but should be considered first if 2935 * there are Tx hangs or other Tx related bugs 2936 */ 2937 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2938 ew32(TXDCTL(0), txdctl); 2939 } 2940 /* erratum work around: set txdctl the same for both queues */ 2941 ew32(TXDCTL(1), er32(TXDCTL(0))); 2942 2943 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2944 tarc = er32(TARC(0)); 2945 /* set the speed mode bit, we'll clear it if we're not at 2946 * gigabit link later 2947 */ 2948 #define SPEED_MODE_BIT (1 << 21) 2949 tarc |= SPEED_MODE_BIT; 2950 ew32(TARC(0), tarc); 2951 } 2952 2953 /* errata: program both queues to unweighted RR */ 2954 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 2955 tarc = er32(TARC(0)); 2956 tarc |= 1; 2957 ew32(TARC(0), tarc); 2958 tarc = er32(TARC(1)); 2959 tarc |= 1; 2960 ew32(TARC(1), tarc); 2961 } 2962 2963 /* Setup Transmit Descriptor Settings for eop descriptor */ 2964 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 2965 2966 /* only set IDE if we are delaying interrupts using the timers */ 2967 if (adapter->tx_int_delay) 2968 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2969 2970 /* enable Report Status bit */ 2971 adapter->txd_cmd |= E1000_TXD_CMD_RS; 2972 2973 hw->mac.ops.config_collision_dist(hw); 2974 } 2975 2976 /** 2977 * e1000_setup_rctl - configure the receive control registers 2978 * @adapter: Board private structure 2979 **/ 2980 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 2981 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 2982 static void e1000_setup_rctl(struct e1000_adapter *adapter) 2983 { 2984 struct e1000_hw *hw = &adapter->hw; 2985 u32 rctl, rfctl; 2986 u32 pages = 0; 2987 2988 /* Workaround Si errata on PCHx - configure jumbo frame flow */ 2989 if (hw->mac.type >= e1000_pch2lan) { 2990 s32 ret_val; 2991 2992 if (adapter->netdev->mtu > ETH_DATA_LEN) 2993 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 2994 else 2995 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 2996 2997 if (ret_val) 2998 e_dbg("failed to enable jumbo frame workaround mode\n"); 2999 } 3000 3001 /* Program MC offset vector base */ 3002 rctl = er32(RCTL); 3003 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3004 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3005 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3006 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3007 3008 /* Do not Store bad packets */ 3009 rctl &= ~E1000_RCTL_SBP; 3010 3011 /* Enable Long Packet receive */ 3012 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3013 rctl &= ~E1000_RCTL_LPE; 3014 else 3015 rctl |= E1000_RCTL_LPE; 3016 3017 /* Some systems expect that the CRC is included in SMBUS traffic. The 3018 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3019 * host memory when this is enabled 3020 */ 3021 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3022 rctl |= E1000_RCTL_SECRC; 3023 3024 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3025 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3026 u16 phy_data; 3027 3028 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3029 phy_data &= 0xfff8; 3030 phy_data |= (1 << 2); 3031 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3032 3033 e1e_rphy(hw, 22, &phy_data); 3034 phy_data &= 0x0fff; 3035 phy_data |= (1 << 14); 3036 e1e_wphy(hw, 0x10, 0x2823); 3037 e1e_wphy(hw, 0x11, 0x0003); 3038 e1e_wphy(hw, 22, phy_data); 3039 } 3040 3041 /* Setup buffer sizes */ 3042 rctl &= ~E1000_RCTL_SZ_4096; 3043 rctl |= E1000_RCTL_BSEX; 3044 switch (adapter->rx_buffer_len) { 3045 case 2048: 3046 default: 3047 rctl |= E1000_RCTL_SZ_2048; 3048 rctl &= ~E1000_RCTL_BSEX; 3049 break; 3050 case 4096: 3051 rctl |= E1000_RCTL_SZ_4096; 3052 break; 3053 case 8192: 3054 rctl |= E1000_RCTL_SZ_8192; 3055 break; 3056 case 16384: 3057 rctl |= E1000_RCTL_SZ_16384; 3058 break; 3059 } 3060 3061 /* Enable Extended Status in all Receive Descriptors */ 3062 rfctl = er32(RFCTL); 3063 rfctl |= E1000_RFCTL_EXTEN; 3064 ew32(RFCTL, rfctl); 3065 3066 /* 82571 and greater support packet-split where the protocol 3067 * header is placed in skb->data and the packet data is 3068 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3069 * In the case of a non-split, skb->data is linearly filled, 3070 * followed by the page buffers. Therefore, skb->data is 3071 * sized to hold the largest protocol header. 3072 * 3073 * allocations using alloc_page take too long for regular MTU 3074 * so only enable packet split for jumbo frames 3075 * 3076 * Using pages when the page size is greater than 16k wastes 3077 * a lot of memory, since we allocate 3 pages at all times 3078 * per packet. 3079 */ 3080 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3081 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3082 adapter->rx_ps_pages = pages; 3083 else 3084 adapter->rx_ps_pages = 0; 3085 3086 if (adapter->rx_ps_pages) { 3087 u32 psrctl = 0; 3088 3089 /* Enable Packet split descriptors */ 3090 rctl |= E1000_RCTL_DTYP_PS; 3091 3092 psrctl |= adapter->rx_ps_bsize0 >> 3093 E1000_PSRCTL_BSIZE0_SHIFT; 3094 3095 switch (adapter->rx_ps_pages) { 3096 case 3: 3097 psrctl |= PAGE_SIZE << 3098 E1000_PSRCTL_BSIZE3_SHIFT; 3099 case 2: 3100 psrctl |= PAGE_SIZE << 3101 E1000_PSRCTL_BSIZE2_SHIFT; 3102 case 1: 3103 psrctl |= PAGE_SIZE >> 3104 E1000_PSRCTL_BSIZE1_SHIFT; 3105 break; 3106 } 3107 3108 ew32(PSRCTL, psrctl); 3109 } 3110 3111 /* This is useful for sniffing bad packets. */ 3112 if (adapter->netdev->features & NETIF_F_RXALL) { 3113 /* UPE and MPE will be handled by normal PROMISC logic 3114 * in e1000e_set_rx_mode 3115 */ 3116 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3117 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3118 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3119 3120 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3121 E1000_RCTL_DPF | /* Allow filtered pause */ 3122 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3123 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3124 * and that breaks VLANs. 3125 */ 3126 } 3127 3128 ew32(RCTL, rctl); 3129 /* just started the receive unit, no need to restart */ 3130 adapter->flags &= ~FLAG_RESTART_NOW; 3131 } 3132 3133 /** 3134 * e1000_configure_rx - Configure Receive Unit after Reset 3135 * @adapter: board private structure 3136 * 3137 * Configure the Rx unit of the MAC after a reset. 3138 **/ 3139 static void e1000_configure_rx(struct e1000_adapter *adapter) 3140 { 3141 struct e1000_hw *hw = &adapter->hw; 3142 struct e1000_ring *rx_ring = adapter->rx_ring; 3143 u64 rdba; 3144 u32 rdlen, rctl, rxcsum, ctrl_ext; 3145 3146 if (adapter->rx_ps_pages) { 3147 /* this is a 32 byte descriptor */ 3148 rdlen = rx_ring->count * 3149 sizeof(union e1000_rx_desc_packet_split); 3150 adapter->clean_rx = e1000_clean_rx_irq_ps; 3151 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3152 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3153 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3154 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3155 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3156 } else { 3157 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3158 adapter->clean_rx = e1000_clean_rx_irq; 3159 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3160 } 3161 3162 /* disable receives while setting up the descriptors */ 3163 rctl = er32(RCTL); 3164 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3165 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3166 e1e_flush(); 3167 usleep_range(10000, 20000); 3168 3169 if (adapter->flags2 & FLAG2_DMA_BURST) { 3170 /* set the writeback threshold (only takes effect if the RDTR 3171 * is set). set GRAN=1 and write back up to 0x4 worth, and 3172 * enable prefetching of 0x20 Rx descriptors 3173 * granularity = 01 3174 * wthresh = 04, 3175 * hthresh = 04, 3176 * pthresh = 0x20 3177 */ 3178 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3179 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3180 3181 /* override the delay timers for enabling bursting, only if 3182 * the value was not set by the user via module options 3183 */ 3184 if (adapter->rx_int_delay == DEFAULT_RDTR) 3185 adapter->rx_int_delay = BURST_RDTR; 3186 if (adapter->rx_abs_int_delay == DEFAULT_RADV) 3187 adapter->rx_abs_int_delay = BURST_RADV; 3188 } 3189 3190 /* set the Receive Delay Timer Register */ 3191 ew32(RDTR, adapter->rx_int_delay); 3192 3193 /* irq moderation */ 3194 ew32(RADV, adapter->rx_abs_int_delay); 3195 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3196 e1000e_write_itr(adapter, adapter->itr); 3197 3198 ctrl_ext = er32(CTRL_EXT); 3199 /* Auto-Mask interrupts upon ICR access */ 3200 ctrl_ext |= E1000_CTRL_EXT_IAME; 3201 ew32(IAM, 0xffffffff); 3202 ew32(CTRL_EXT, ctrl_ext); 3203 e1e_flush(); 3204 3205 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3206 * the Base and Length of the Rx Descriptor Ring 3207 */ 3208 rdba = rx_ring->dma; 3209 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3210 ew32(RDBAH(0), (rdba >> 32)); 3211 ew32(RDLEN(0), rdlen); 3212 ew32(RDH(0), 0); 3213 ew32(RDT(0), 0); 3214 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3215 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3216 3217 /* Enable Receive Checksum Offload for TCP and UDP */ 3218 rxcsum = er32(RXCSUM); 3219 if (adapter->netdev->features & NETIF_F_RXCSUM) 3220 rxcsum |= E1000_RXCSUM_TUOFL; 3221 else 3222 rxcsum &= ~E1000_RXCSUM_TUOFL; 3223 ew32(RXCSUM, rxcsum); 3224 3225 /* With jumbo frames, excessive C-state transition latencies result 3226 * in dropped transactions. 3227 */ 3228 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3229 u32 lat = 3230 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3231 adapter->max_frame_size) * 8 / 1000; 3232 3233 if (adapter->flags & FLAG_IS_ICH) { 3234 u32 rxdctl = er32(RXDCTL(0)); 3235 ew32(RXDCTL(0), rxdctl | 0x3); 3236 } 3237 3238 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat); 3239 } else { 3240 pm_qos_update_request(&adapter->netdev->pm_qos_req, 3241 PM_QOS_DEFAULT_VALUE); 3242 } 3243 3244 /* Enable Receives */ 3245 ew32(RCTL, rctl); 3246 } 3247 3248 /** 3249 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3250 * @netdev: network interface device structure 3251 * 3252 * Writes multicast address list to the MTA hash table. 3253 * Returns: -ENOMEM on failure 3254 * 0 on no addresses written 3255 * X on writing X addresses to MTA 3256 */ 3257 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3258 { 3259 struct e1000_adapter *adapter = netdev_priv(netdev); 3260 struct e1000_hw *hw = &adapter->hw; 3261 struct netdev_hw_addr *ha; 3262 u8 *mta_list; 3263 int i; 3264 3265 if (netdev_mc_empty(netdev)) { 3266 /* nothing to program, so clear mc list */ 3267 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3268 return 0; 3269 } 3270 3271 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3272 if (!mta_list) 3273 return -ENOMEM; 3274 3275 /* update_mc_addr_list expects a packed array of only addresses. */ 3276 i = 0; 3277 netdev_for_each_mc_addr(ha, netdev) 3278 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3279 3280 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3281 kfree(mta_list); 3282 3283 return netdev_mc_count(netdev); 3284 } 3285 3286 /** 3287 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3288 * @netdev: network interface device structure 3289 * 3290 * Writes unicast address list to the RAR table. 3291 * Returns: -ENOMEM on failure/insufficient address space 3292 * 0 on no addresses written 3293 * X on writing X addresses to the RAR table 3294 **/ 3295 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3296 { 3297 struct e1000_adapter *adapter = netdev_priv(netdev); 3298 struct e1000_hw *hw = &adapter->hw; 3299 unsigned int rar_entries = hw->mac.rar_entry_count; 3300 int count = 0; 3301 3302 /* save a rar entry for our hardware address */ 3303 rar_entries--; 3304 3305 /* save a rar entry for the LAA workaround */ 3306 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3307 rar_entries--; 3308 3309 /* return ENOMEM indicating insufficient memory for addresses */ 3310 if (netdev_uc_count(netdev) > rar_entries) 3311 return -ENOMEM; 3312 3313 if (!netdev_uc_empty(netdev) && rar_entries) { 3314 struct netdev_hw_addr *ha; 3315 3316 /* write the addresses in reverse order to avoid write 3317 * combining 3318 */ 3319 netdev_for_each_uc_addr(ha, netdev) { 3320 if (!rar_entries) 3321 break; 3322 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3323 count++; 3324 } 3325 } 3326 3327 /* zero out the remaining RAR entries not used above */ 3328 for (; rar_entries > 0; rar_entries--) { 3329 ew32(RAH(rar_entries), 0); 3330 ew32(RAL(rar_entries), 0); 3331 } 3332 e1e_flush(); 3333 3334 return count; 3335 } 3336 3337 /** 3338 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3339 * @netdev: network interface device structure 3340 * 3341 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3342 * address list or the network interface flags are updated. This routine is 3343 * responsible for configuring the hardware for proper unicast, multicast, 3344 * promiscuous mode, and all-multi behavior. 3345 **/ 3346 static void e1000e_set_rx_mode(struct net_device *netdev) 3347 { 3348 struct e1000_adapter *adapter = netdev_priv(netdev); 3349 struct e1000_hw *hw = &adapter->hw; 3350 u32 rctl; 3351 3352 /* Check for Promiscuous and All Multicast modes */ 3353 rctl = er32(RCTL); 3354 3355 /* clear the affected bits */ 3356 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3357 3358 if (netdev->flags & IFF_PROMISC) { 3359 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3360 /* Do not hardware filter VLANs in promisc mode */ 3361 e1000e_vlan_filter_disable(adapter); 3362 } else { 3363 int count; 3364 3365 if (netdev->flags & IFF_ALLMULTI) { 3366 rctl |= E1000_RCTL_MPE; 3367 } else { 3368 /* Write addresses to the MTA, if the attempt fails 3369 * then we should just turn on promiscuous mode so 3370 * that we can at least receive multicast traffic 3371 */ 3372 count = e1000e_write_mc_addr_list(netdev); 3373 if (count < 0) 3374 rctl |= E1000_RCTL_MPE; 3375 } 3376 e1000e_vlan_filter_enable(adapter); 3377 /* Write addresses to available RAR registers, if there is not 3378 * sufficient space to store all the addresses then enable 3379 * unicast promiscuous mode 3380 */ 3381 count = e1000e_write_uc_addr_list(netdev); 3382 if (count < 0) 3383 rctl |= E1000_RCTL_UPE; 3384 } 3385 3386 ew32(RCTL, rctl); 3387 3388 if (netdev->features & NETIF_F_HW_VLAN_RX) 3389 e1000e_vlan_strip_enable(adapter); 3390 else 3391 e1000e_vlan_strip_disable(adapter); 3392 } 3393 3394 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3395 { 3396 struct e1000_hw *hw = &adapter->hw; 3397 u32 mrqc, rxcsum; 3398 int i; 3399 static const u32 rsskey[10] = { 3400 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0, 3401 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe 3402 }; 3403 3404 /* Fill out hash function seed */ 3405 for (i = 0; i < 10; i++) 3406 ew32(RSSRK(i), rsskey[i]); 3407 3408 /* Direct all traffic to queue 0 */ 3409 for (i = 0; i < 32; i++) 3410 ew32(RETA(i), 0); 3411 3412 /* Disable raw packet checksumming so that RSS hash is placed in 3413 * descriptor on writeback. 3414 */ 3415 rxcsum = er32(RXCSUM); 3416 rxcsum |= E1000_RXCSUM_PCSD; 3417 3418 ew32(RXCSUM, rxcsum); 3419 3420 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3421 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3422 E1000_MRQC_RSS_FIELD_IPV6 | 3423 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3424 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3425 3426 ew32(MRQC, mrqc); 3427 } 3428 3429 /** 3430 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3431 * @adapter: board private structure 3432 * @timinca: pointer to returned time increment attributes 3433 * 3434 * Get attributes for incrementing the System Time Register SYSTIML/H at 3435 * the default base frequency, and set the cyclecounter shift value. 3436 **/ 3437 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3438 { 3439 struct e1000_hw *hw = &adapter->hw; 3440 u32 incvalue, incperiod, shift; 3441 3442 /* Make sure clock is enabled on I217 before checking the frequency */ 3443 if ((hw->mac.type == e1000_pch_lpt) && 3444 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3445 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3446 u32 fextnvm7 = er32(FEXTNVM7); 3447 3448 if (!(fextnvm7 & (1 << 0))) { 3449 ew32(FEXTNVM7, fextnvm7 | (1 << 0)); 3450 e1e_flush(); 3451 } 3452 } 3453 3454 switch (hw->mac.type) { 3455 case e1000_pch2lan: 3456 case e1000_pch_lpt: 3457 /* On I217, the clock frequency is 25MHz or 96MHz as 3458 * indicated by the System Clock Frequency Indication 3459 */ 3460 if ((hw->mac.type != e1000_pch_lpt) || 3461 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 3462 /* Stable 96MHz frequency */ 3463 incperiod = INCPERIOD_96MHz; 3464 incvalue = INCVALUE_96MHz; 3465 shift = INCVALUE_SHIFT_96MHz; 3466 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz; 3467 break; 3468 } 3469 /* fall-through */ 3470 case e1000_82574: 3471 case e1000_82583: 3472 /* Stable 25MHz frequency */ 3473 incperiod = INCPERIOD_25MHz; 3474 incvalue = INCVALUE_25MHz; 3475 shift = INCVALUE_SHIFT_25MHz; 3476 adapter->cc.shift = shift; 3477 break; 3478 default: 3479 return -EINVAL; 3480 } 3481 3482 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3483 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3484 3485 return 0; 3486 } 3487 3488 /** 3489 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3490 * @adapter: board private structure 3491 * 3492 * Outgoing time stamping can be enabled and disabled. Play nice and 3493 * disable it when requested, although it shouldn't cause any overhead 3494 * when no packet needs it. At most one packet in the queue may be 3495 * marked for time stamping, otherwise it would be impossible to tell 3496 * for sure to which packet the hardware time stamp belongs. 3497 * 3498 * Incoming time stamping has to be configured via the hardware filters. 3499 * Not all combinations are supported, in particular event type has to be 3500 * specified. Matching the kind of event packet is not supported, with the 3501 * exception of "all V2 events regardless of level 2 or 4". 3502 **/ 3503 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter) 3504 { 3505 struct e1000_hw *hw = &adapter->hw; 3506 struct hwtstamp_config *config = &adapter->hwtstamp_config; 3507 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3508 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3509 u32 rxmtrl = 0; 3510 u16 rxudp = 0; 3511 bool is_l4 = false; 3512 bool is_l2 = false; 3513 u32 regval; 3514 s32 ret_val; 3515 3516 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3517 return -EINVAL; 3518 3519 /* flags reserved for future extensions - must be zero */ 3520 if (config->flags) 3521 return -EINVAL; 3522 3523 switch (config->tx_type) { 3524 case HWTSTAMP_TX_OFF: 3525 tsync_tx_ctl = 0; 3526 break; 3527 case HWTSTAMP_TX_ON: 3528 break; 3529 default: 3530 return -ERANGE; 3531 } 3532 3533 switch (config->rx_filter) { 3534 case HWTSTAMP_FILTER_NONE: 3535 tsync_rx_ctl = 0; 3536 break; 3537 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3538 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3539 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3540 is_l4 = true; 3541 break; 3542 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3543 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3544 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3545 is_l4 = true; 3546 break; 3547 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3548 /* Also time stamps V2 L2 Path Delay Request/Response */ 3549 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3550 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3551 is_l2 = true; 3552 break; 3553 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3554 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3555 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3556 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3557 is_l2 = true; 3558 break; 3559 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3560 /* Hardware cannot filter just V2 L4 Sync messages; 3561 * fall-through to V2 (both L2 and L4) Sync. 3562 */ 3563 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3564 /* Also time stamps V2 Path Delay Request/Response. */ 3565 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3566 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3567 is_l2 = true; 3568 is_l4 = true; 3569 break; 3570 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3571 /* Hardware cannot filter just V2 L4 Delay Request messages; 3572 * fall-through to V2 (both L2 and L4) Delay Request. 3573 */ 3574 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3575 /* Also time stamps V2 Path Delay Request/Response. */ 3576 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3577 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3578 is_l2 = true; 3579 is_l4 = true; 3580 break; 3581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3582 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3583 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3584 * fall-through to all V2 (both L2 and L4) Events. 3585 */ 3586 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3587 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3588 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3589 is_l2 = true; 3590 is_l4 = true; 3591 break; 3592 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3593 /* For V1, the hardware can only filter Sync messages or 3594 * Delay Request messages but not both so fall-through to 3595 * time stamp all packets. 3596 */ 3597 case HWTSTAMP_FILTER_ALL: 3598 is_l2 = true; 3599 is_l4 = true; 3600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3601 config->rx_filter = HWTSTAMP_FILTER_ALL; 3602 break; 3603 default: 3604 return -ERANGE; 3605 } 3606 3607 /* enable/disable Tx h/w time stamping */ 3608 regval = er32(TSYNCTXCTL); 3609 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3610 regval |= tsync_tx_ctl; 3611 ew32(TSYNCTXCTL, regval); 3612 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3613 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3614 e_err("Timesync Tx Control register not set as expected\n"); 3615 return -EAGAIN; 3616 } 3617 3618 /* enable/disable Rx h/w time stamping */ 3619 regval = er32(TSYNCRXCTL); 3620 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3621 regval |= tsync_rx_ctl; 3622 ew32(TSYNCRXCTL, regval); 3623 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3624 E1000_TSYNCRXCTL_TYPE_MASK)) != 3625 (regval & (E1000_TSYNCRXCTL_ENABLED | 3626 E1000_TSYNCRXCTL_TYPE_MASK))) { 3627 e_err("Timesync Rx Control register not set as expected\n"); 3628 return -EAGAIN; 3629 } 3630 3631 /* L2: define ethertype filter for time stamped packets */ 3632 if (is_l2) 3633 rxmtrl |= ETH_P_1588; 3634 3635 /* define which PTP packets get time stamped */ 3636 ew32(RXMTRL, rxmtrl); 3637 3638 /* Filter by destination port */ 3639 if (is_l4) { 3640 rxudp = PTP_EV_PORT; 3641 cpu_to_be16s(&rxudp); 3642 } 3643 ew32(RXUDP, rxudp); 3644 3645 e1e_flush(); 3646 3647 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3648 er32(RXSTMPH); 3649 er32(TXSTMPH); 3650 3651 /* Get and set the System Time Register SYSTIM base frequency */ 3652 ret_val = e1000e_get_base_timinca(adapter, ®val); 3653 if (ret_val) 3654 return ret_val; 3655 ew32(TIMINCA, regval); 3656 3657 /* reset the ns time counter */ 3658 timecounter_init(&adapter->tc, &adapter->cc, 3659 ktime_to_ns(ktime_get_real())); 3660 3661 return 0; 3662 } 3663 3664 /** 3665 * e1000_configure - configure the hardware for Rx and Tx 3666 * @adapter: private board structure 3667 **/ 3668 static void e1000_configure(struct e1000_adapter *adapter) 3669 { 3670 struct e1000_ring *rx_ring = adapter->rx_ring; 3671 3672 e1000e_set_rx_mode(adapter->netdev); 3673 3674 e1000_restore_vlan(adapter); 3675 e1000_init_manageability_pt(adapter); 3676 3677 e1000_configure_tx(adapter); 3678 3679 if (adapter->netdev->features & NETIF_F_RXHASH) 3680 e1000e_setup_rss_hash(adapter); 3681 e1000_setup_rctl(adapter); 3682 e1000_configure_rx(adapter); 3683 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3684 } 3685 3686 /** 3687 * e1000e_power_up_phy - restore link in case the phy was powered down 3688 * @adapter: address of board private structure 3689 * 3690 * The phy may be powered down to save power and turn off link when the 3691 * driver is unloaded and wake on lan is not enabled (among others) 3692 * *** this routine MUST be followed by a call to e1000e_reset *** 3693 **/ 3694 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3695 { 3696 if (adapter->hw.phy.ops.power_up) 3697 adapter->hw.phy.ops.power_up(&adapter->hw); 3698 3699 adapter->hw.mac.ops.setup_link(&adapter->hw); 3700 } 3701 3702 /** 3703 * e1000_power_down_phy - Power down the PHY 3704 * 3705 * Power down the PHY so no link is implied when interface is down. 3706 * The PHY cannot be powered down if management or WoL is active. 3707 */ 3708 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3709 { 3710 /* WoL is enabled */ 3711 if (adapter->wol) 3712 return; 3713 3714 if (adapter->hw.phy.ops.power_down) 3715 adapter->hw.phy.ops.power_down(&adapter->hw); 3716 } 3717 3718 /** 3719 * e1000e_reset - bring the hardware into a known good state 3720 * 3721 * This function boots the hardware and enables some settings that 3722 * require a configuration cycle of the hardware - those cannot be 3723 * set/changed during runtime. After reset the device needs to be 3724 * properly configured for Rx, Tx etc. 3725 */ 3726 void e1000e_reset(struct e1000_adapter *adapter) 3727 { 3728 struct e1000_mac_info *mac = &adapter->hw.mac; 3729 struct e1000_fc_info *fc = &adapter->hw.fc; 3730 struct e1000_hw *hw = &adapter->hw; 3731 u32 tx_space, min_tx_space, min_rx_space; 3732 u32 pba = adapter->pba; 3733 u16 hwm; 3734 3735 /* reset Packet Buffer Allocation to default */ 3736 ew32(PBA, pba); 3737 3738 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 3739 /* To maintain wire speed transmits, the Tx FIFO should be 3740 * large enough to accommodate two full transmit packets, 3741 * rounded up to the next 1KB and expressed in KB. Likewise, 3742 * the Rx FIFO should be large enough to accommodate at least 3743 * one full receive packet and is similarly rounded up and 3744 * expressed in KB. 3745 */ 3746 pba = er32(PBA); 3747 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3748 tx_space = pba >> 16; 3749 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3750 pba &= 0xffff; 3751 /* the Tx fifo also stores 16 bytes of information about the Tx 3752 * but don't include ethernet FCS because hardware appends it 3753 */ 3754 min_tx_space = (adapter->max_frame_size + 3755 sizeof(struct e1000_tx_desc) - 3756 ETH_FCS_LEN) * 2; 3757 min_tx_space = ALIGN(min_tx_space, 1024); 3758 min_tx_space >>= 10; 3759 /* software strips receive CRC, so leave room for it */ 3760 min_rx_space = adapter->max_frame_size; 3761 min_rx_space = ALIGN(min_rx_space, 1024); 3762 min_rx_space >>= 10; 3763 3764 /* If current Tx allocation is less than the min Tx FIFO size, 3765 * and the min Tx FIFO size is less than the current Rx FIFO 3766 * allocation, take space away from current Rx allocation 3767 */ 3768 if ((tx_space < min_tx_space) && 3769 ((min_tx_space - tx_space) < pba)) { 3770 pba -= min_tx_space - tx_space; 3771 3772 /* if short on Rx space, Rx wins and must trump Tx 3773 * adjustment 3774 */ 3775 if (pba < min_rx_space) 3776 pba = min_rx_space; 3777 } 3778 3779 ew32(PBA, pba); 3780 } 3781 3782 /* flow control settings 3783 * 3784 * The high water mark must be low enough to fit one full frame 3785 * (or the size used for early receive) above it in the Rx FIFO. 3786 * Set it to the lower of: 3787 * - 90% of the Rx FIFO size, and 3788 * - the full Rx FIFO size minus one full frame 3789 */ 3790 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 3791 fc->pause_time = 0xFFFF; 3792 else 3793 fc->pause_time = E1000_FC_PAUSE_TIME; 3794 fc->send_xon = true; 3795 fc->current_mode = fc->requested_mode; 3796 3797 switch (hw->mac.type) { 3798 case e1000_ich9lan: 3799 case e1000_ich10lan: 3800 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3801 pba = 14; 3802 ew32(PBA, pba); 3803 fc->high_water = 0x2800; 3804 fc->low_water = fc->high_water - 8; 3805 break; 3806 } 3807 /* fall-through */ 3808 default: 3809 hwm = min(((pba << 10) * 9 / 10), 3810 ((pba << 10) - adapter->max_frame_size)); 3811 3812 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 3813 fc->low_water = fc->high_water - 8; 3814 break; 3815 case e1000_pchlan: 3816 /* Workaround PCH LOM adapter hangs with certain network 3817 * loads. If hangs persist, try disabling Tx flow control. 3818 */ 3819 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3820 fc->high_water = 0x3500; 3821 fc->low_water = 0x1500; 3822 } else { 3823 fc->high_water = 0x5000; 3824 fc->low_water = 0x3000; 3825 } 3826 fc->refresh_time = 0x1000; 3827 break; 3828 case e1000_pch2lan: 3829 case e1000_pch_lpt: 3830 fc->refresh_time = 0x0400; 3831 3832 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 3833 fc->high_water = 0x05C20; 3834 fc->low_water = 0x05048; 3835 fc->pause_time = 0x0650; 3836 break; 3837 } 3838 3839 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 3840 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 3841 break; 3842 } 3843 3844 /* Alignment of Tx data is on an arbitrary byte boundary with the 3845 * maximum size per Tx descriptor limited only to the transmit 3846 * allocation of the packet buffer minus 96 bytes with an upper 3847 * limit of 24KB due to receive synchronization limitations. 3848 */ 3849 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 3850 24 << 10); 3851 3852 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 3853 * fit in receive buffer. 3854 */ 3855 if (adapter->itr_setting & 0x3) { 3856 if ((adapter->max_frame_size * 2) > (pba << 10)) { 3857 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 3858 dev_info(&adapter->pdev->dev, 3859 "Interrupt Throttle Rate turned off\n"); 3860 adapter->flags2 |= FLAG2_DISABLE_AIM; 3861 e1000e_write_itr(adapter, 0); 3862 } 3863 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 3864 dev_info(&adapter->pdev->dev, 3865 "Interrupt Throttle Rate turned on\n"); 3866 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 3867 adapter->itr = 20000; 3868 e1000e_write_itr(adapter, adapter->itr); 3869 } 3870 } 3871 3872 /* Allow time for pending master requests to run */ 3873 mac->ops.reset_hw(hw); 3874 3875 /* For parts with AMT enabled, let the firmware know 3876 * that the network interface is in control 3877 */ 3878 if (adapter->flags & FLAG_HAS_AMT) 3879 e1000e_get_hw_control(adapter); 3880 3881 ew32(WUC, 0); 3882 3883 if (mac->ops.init_hw(hw)) 3884 e_err("Hardware Error\n"); 3885 3886 e1000_update_mng_vlan(adapter); 3887 3888 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 3889 ew32(VET, ETH_P_8021Q); 3890 3891 e1000e_reset_adaptive(hw); 3892 3893 /* initialize systim and reset the ns time counter */ 3894 e1000e_config_hwtstamp(adapter); 3895 3896 if (!netif_running(adapter->netdev) && 3897 !test_bit(__E1000_TESTING, &adapter->state)) { 3898 e1000_power_down_phy(adapter); 3899 return; 3900 } 3901 3902 e1000_get_phy_info(hw); 3903 3904 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 3905 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 3906 u16 phy_data = 0; 3907 /* speed up time to link by disabling smart power down, ignore 3908 * the return value of this function because there is nothing 3909 * different we would do if it failed 3910 */ 3911 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 3912 phy_data &= ~IGP02E1000_PM_SPD; 3913 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 3914 } 3915 } 3916 3917 int e1000e_up(struct e1000_adapter *adapter) 3918 { 3919 struct e1000_hw *hw = &adapter->hw; 3920 3921 /* hardware has been reset, we need to reload some things */ 3922 e1000_configure(adapter); 3923 3924 clear_bit(__E1000_DOWN, &adapter->state); 3925 3926 if (adapter->msix_entries) 3927 e1000_configure_msix(adapter); 3928 e1000_irq_enable(adapter); 3929 3930 netif_start_queue(adapter->netdev); 3931 3932 /* fire a link change interrupt to start the watchdog */ 3933 if (adapter->msix_entries) 3934 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 3935 else 3936 ew32(ICS, E1000_ICS_LSC); 3937 3938 return 0; 3939 } 3940 3941 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 3942 { 3943 struct e1000_hw *hw = &adapter->hw; 3944 3945 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 3946 return; 3947 3948 /* flush pending descriptor writebacks to memory */ 3949 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 3950 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 3951 3952 /* execute the writes immediately */ 3953 e1e_flush(); 3954 3955 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 3956 * write is successful 3957 */ 3958 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 3959 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 3960 3961 /* execute the writes immediately */ 3962 e1e_flush(); 3963 } 3964 3965 static void e1000e_update_stats(struct e1000_adapter *adapter); 3966 3967 void e1000e_down(struct e1000_adapter *adapter) 3968 { 3969 struct net_device *netdev = adapter->netdev; 3970 struct e1000_hw *hw = &adapter->hw; 3971 u32 tctl, rctl; 3972 3973 /* signal that we're down so the interrupt handler does not 3974 * reschedule our watchdog timer 3975 */ 3976 set_bit(__E1000_DOWN, &adapter->state); 3977 3978 /* disable receives in the hardware */ 3979 rctl = er32(RCTL); 3980 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3981 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3982 /* flush and sleep below */ 3983 3984 netif_stop_queue(netdev); 3985 3986 /* disable transmits in the hardware */ 3987 tctl = er32(TCTL); 3988 tctl &= ~E1000_TCTL_EN; 3989 ew32(TCTL, tctl); 3990 3991 /* flush both disables and wait for them to finish */ 3992 e1e_flush(); 3993 usleep_range(10000, 20000); 3994 3995 e1000_irq_disable(adapter); 3996 3997 del_timer_sync(&adapter->watchdog_timer); 3998 del_timer_sync(&adapter->phy_info_timer); 3999 4000 netif_carrier_off(netdev); 4001 4002 spin_lock(&adapter->stats64_lock); 4003 e1000e_update_stats(adapter); 4004 spin_unlock(&adapter->stats64_lock); 4005 4006 e1000e_flush_descriptors(adapter); 4007 e1000_clean_tx_ring(adapter->tx_ring); 4008 e1000_clean_rx_ring(adapter->rx_ring); 4009 4010 adapter->link_speed = 0; 4011 adapter->link_duplex = 0; 4012 4013 if (!pci_channel_offline(adapter->pdev)) 4014 e1000e_reset(adapter); 4015 4016 /* TODO: for power management, we could drop the link and 4017 * pci_disable_device here. 4018 */ 4019 } 4020 4021 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4022 { 4023 might_sleep(); 4024 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4025 usleep_range(1000, 2000); 4026 e1000e_down(adapter); 4027 e1000e_up(adapter); 4028 clear_bit(__E1000_RESETTING, &adapter->state); 4029 } 4030 4031 /** 4032 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4033 * @cc: cyclecounter structure 4034 **/ 4035 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc) 4036 { 4037 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4038 cc); 4039 struct e1000_hw *hw = &adapter->hw; 4040 cycle_t systim; 4041 4042 /* latch SYSTIMH on read of SYSTIML */ 4043 systim = (cycle_t)er32(SYSTIML); 4044 systim |= (cycle_t)er32(SYSTIMH) << 32; 4045 4046 return systim; 4047 } 4048 4049 /** 4050 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4051 * @adapter: board private structure to initialize 4052 * 4053 * e1000_sw_init initializes the Adapter private data structure. 4054 * Fields are initialized based on PCI device information and 4055 * OS network device settings (MTU size). 4056 **/ 4057 static int e1000_sw_init(struct e1000_adapter *adapter) 4058 { 4059 struct net_device *netdev = adapter->netdev; 4060 4061 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; 4062 adapter->rx_ps_bsize0 = 128; 4063 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4064 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4065 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4066 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4067 4068 spin_lock_init(&adapter->stats64_lock); 4069 4070 e1000e_set_interrupt_capability(adapter); 4071 4072 if (e1000_alloc_queues(adapter)) 4073 return -ENOMEM; 4074 4075 /* Setup hardware time stamping cyclecounter */ 4076 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4077 adapter->cc.read = e1000e_cyclecounter_read; 4078 adapter->cc.mask = CLOCKSOURCE_MASK(64); 4079 adapter->cc.mult = 1; 4080 /* cc.shift set in e1000e_get_base_tininca() */ 4081 4082 spin_lock_init(&adapter->systim_lock); 4083 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4084 } 4085 4086 /* Explicitly disable IRQ since the NIC can be in any state. */ 4087 e1000_irq_disable(adapter); 4088 4089 set_bit(__E1000_DOWN, &adapter->state); 4090 return 0; 4091 } 4092 4093 /** 4094 * e1000_intr_msi_test - Interrupt Handler 4095 * @irq: interrupt number 4096 * @data: pointer to a network interface device structure 4097 **/ 4098 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4099 { 4100 struct net_device *netdev = data; 4101 struct e1000_adapter *adapter = netdev_priv(netdev); 4102 struct e1000_hw *hw = &adapter->hw; 4103 u32 icr = er32(ICR); 4104 4105 e_dbg("icr is %08X\n", icr); 4106 if (icr & E1000_ICR_RXSEQ) { 4107 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4108 /* Force memory writes to complete before acknowledging the 4109 * interrupt is handled. 4110 */ 4111 wmb(); 4112 } 4113 4114 return IRQ_HANDLED; 4115 } 4116 4117 /** 4118 * e1000_test_msi_interrupt - Returns 0 for successful test 4119 * @adapter: board private struct 4120 * 4121 * code flow taken from tg3.c 4122 **/ 4123 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4124 { 4125 struct net_device *netdev = adapter->netdev; 4126 struct e1000_hw *hw = &adapter->hw; 4127 int err; 4128 4129 /* poll_enable hasn't been called yet, so don't need disable */ 4130 /* clear any pending events */ 4131 er32(ICR); 4132 4133 /* free the real vector and request a test handler */ 4134 e1000_free_irq(adapter); 4135 e1000e_reset_interrupt_capability(adapter); 4136 4137 /* Assume that the test fails, if it succeeds then the test 4138 * MSI irq handler will unset this flag 4139 */ 4140 adapter->flags |= FLAG_MSI_TEST_FAILED; 4141 4142 err = pci_enable_msi(adapter->pdev); 4143 if (err) 4144 goto msi_test_failed; 4145 4146 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4147 netdev->name, netdev); 4148 if (err) { 4149 pci_disable_msi(adapter->pdev); 4150 goto msi_test_failed; 4151 } 4152 4153 /* Force memory writes to complete before enabling and firing an 4154 * interrupt. 4155 */ 4156 wmb(); 4157 4158 e1000_irq_enable(adapter); 4159 4160 /* fire an unusual interrupt on the test handler */ 4161 ew32(ICS, E1000_ICS_RXSEQ); 4162 e1e_flush(); 4163 msleep(100); 4164 4165 e1000_irq_disable(adapter); 4166 4167 rmb(); /* read flags after interrupt has been fired */ 4168 4169 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4170 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4171 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4172 } else { 4173 e_dbg("MSI interrupt test succeeded!\n"); 4174 } 4175 4176 free_irq(adapter->pdev->irq, netdev); 4177 pci_disable_msi(adapter->pdev); 4178 4179 msi_test_failed: 4180 e1000e_set_interrupt_capability(adapter); 4181 return e1000_request_irq(adapter); 4182 } 4183 4184 /** 4185 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4186 * @adapter: board private struct 4187 * 4188 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4189 **/ 4190 static int e1000_test_msi(struct e1000_adapter *adapter) 4191 { 4192 int err; 4193 u16 pci_cmd; 4194 4195 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4196 return 0; 4197 4198 /* disable SERR in case the MSI write causes a master abort */ 4199 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4200 if (pci_cmd & PCI_COMMAND_SERR) 4201 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4202 pci_cmd & ~PCI_COMMAND_SERR); 4203 4204 err = e1000_test_msi_interrupt(adapter); 4205 4206 /* re-enable SERR */ 4207 if (pci_cmd & PCI_COMMAND_SERR) { 4208 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4209 pci_cmd |= PCI_COMMAND_SERR; 4210 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4211 } 4212 4213 return err; 4214 } 4215 4216 /** 4217 * e1000_open - Called when a network interface is made active 4218 * @netdev: network interface device structure 4219 * 4220 * Returns 0 on success, negative value on failure 4221 * 4222 * The open entry point is called when a network interface is made 4223 * active by the system (IFF_UP). At this point all resources needed 4224 * for transmit and receive operations are allocated, the interrupt 4225 * handler is registered with the OS, the watchdog timer is started, 4226 * and the stack is notified that the interface is ready. 4227 **/ 4228 static int e1000_open(struct net_device *netdev) 4229 { 4230 struct e1000_adapter *adapter = netdev_priv(netdev); 4231 struct e1000_hw *hw = &adapter->hw; 4232 struct pci_dev *pdev = adapter->pdev; 4233 int err; 4234 4235 /* disallow open during test */ 4236 if (test_bit(__E1000_TESTING, &adapter->state)) 4237 return -EBUSY; 4238 4239 pm_runtime_get_sync(&pdev->dev); 4240 4241 netif_carrier_off(netdev); 4242 4243 /* allocate transmit descriptors */ 4244 err = e1000e_setup_tx_resources(adapter->tx_ring); 4245 if (err) 4246 goto err_setup_tx; 4247 4248 /* allocate receive descriptors */ 4249 err = e1000e_setup_rx_resources(adapter->rx_ring); 4250 if (err) 4251 goto err_setup_rx; 4252 4253 /* If AMT is enabled, let the firmware know that the network 4254 * interface is now open and reset the part to a known state. 4255 */ 4256 if (adapter->flags & FLAG_HAS_AMT) { 4257 e1000e_get_hw_control(adapter); 4258 e1000e_reset(adapter); 4259 } 4260 4261 e1000e_power_up_phy(adapter); 4262 4263 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4264 if ((adapter->hw.mng_cookie.status & 4265 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4266 e1000_update_mng_vlan(adapter); 4267 4268 /* DMA latency requirement to workaround jumbo issue */ 4269 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4270 PM_QOS_DEFAULT_VALUE); 4271 4272 /* before we allocate an interrupt, we must be ready to handle it. 4273 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4274 * as soon as we call pci_request_irq, so we have to setup our 4275 * clean_rx handler before we do so. 4276 */ 4277 e1000_configure(adapter); 4278 4279 err = e1000_request_irq(adapter); 4280 if (err) 4281 goto err_req_irq; 4282 4283 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4284 * ignore e1000e MSI messages, which means we need to test our MSI 4285 * interrupt now 4286 */ 4287 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4288 err = e1000_test_msi(adapter); 4289 if (err) { 4290 e_err("Interrupt allocation failed\n"); 4291 goto err_req_irq; 4292 } 4293 } 4294 4295 /* From here on the code is the same as e1000e_up() */ 4296 clear_bit(__E1000_DOWN, &adapter->state); 4297 4298 napi_enable(&adapter->napi); 4299 4300 e1000_irq_enable(adapter); 4301 4302 adapter->tx_hang_recheck = false; 4303 netif_start_queue(netdev); 4304 4305 adapter->idle_check = true; 4306 pm_runtime_put(&pdev->dev); 4307 4308 /* fire a link status change interrupt to start the watchdog */ 4309 if (adapter->msix_entries) 4310 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 4311 else 4312 ew32(ICS, E1000_ICS_LSC); 4313 4314 return 0; 4315 4316 err_req_irq: 4317 e1000e_release_hw_control(adapter); 4318 e1000_power_down_phy(adapter); 4319 e1000e_free_rx_resources(adapter->rx_ring); 4320 err_setup_rx: 4321 e1000e_free_tx_resources(adapter->tx_ring); 4322 err_setup_tx: 4323 e1000e_reset(adapter); 4324 pm_runtime_put_sync(&pdev->dev); 4325 4326 return err; 4327 } 4328 4329 /** 4330 * e1000_close - Disables a network interface 4331 * @netdev: network interface device structure 4332 * 4333 * Returns 0, this is not allowed to fail 4334 * 4335 * The close entry point is called when an interface is de-activated 4336 * by the OS. The hardware is still under the drivers control, but 4337 * needs to be disabled. A global MAC reset is issued to stop the 4338 * hardware, and all transmit and receive resources are freed. 4339 **/ 4340 static int e1000_close(struct net_device *netdev) 4341 { 4342 struct e1000_adapter *adapter = netdev_priv(netdev); 4343 struct pci_dev *pdev = adapter->pdev; 4344 int count = E1000_CHECK_RESET_COUNT; 4345 4346 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4347 usleep_range(10000, 20000); 4348 4349 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4350 4351 pm_runtime_get_sync(&pdev->dev); 4352 4353 napi_disable(&adapter->napi); 4354 4355 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4356 e1000e_down(adapter); 4357 e1000_free_irq(adapter); 4358 } 4359 e1000_power_down_phy(adapter); 4360 4361 e1000e_free_tx_resources(adapter->tx_ring); 4362 e1000e_free_rx_resources(adapter->rx_ring); 4363 4364 /* kill manageability vlan ID if supported, but not if a vlan with 4365 * the same ID is registered on the host OS (let 8021q kill it) 4366 */ 4367 if (adapter->hw.mng_cookie.status & 4368 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4369 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4370 4371 /* If AMT is enabled, let the firmware know that the network 4372 * interface is now closed 4373 */ 4374 if ((adapter->flags & FLAG_HAS_AMT) && 4375 !test_bit(__E1000_TESTING, &adapter->state)) 4376 e1000e_release_hw_control(adapter); 4377 4378 pm_qos_remove_request(&adapter->netdev->pm_qos_req); 4379 4380 pm_runtime_put_sync(&pdev->dev); 4381 4382 return 0; 4383 } 4384 /** 4385 * e1000_set_mac - Change the Ethernet Address of the NIC 4386 * @netdev: network interface device structure 4387 * @p: pointer to an address structure 4388 * 4389 * Returns 0 on success, negative on failure 4390 **/ 4391 static int e1000_set_mac(struct net_device *netdev, void *p) 4392 { 4393 struct e1000_adapter *adapter = netdev_priv(netdev); 4394 struct e1000_hw *hw = &adapter->hw; 4395 struct sockaddr *addr = p; 4396 4397 if (!is_valid_ether_addr(addr->sa_data)) 4398 return -EADDRNOTAVAIL; 4399 4400 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4401 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4402 4403 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4404 4405 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4406 /* activate the work around */ 4407 e1000e_set_laa_state_82571(&adapter->hw, 1); 4408 4409 /* Hold a copy of the LAA in RAR[14] This is done so that 4410 * between the time RAR[0] gets clobbered and the time it 4411 * gets fixed (in e1000_watchdog), the actual LAA is in one 4412 * of the RARs and no incoming packets directed to this port 4413 * are dropped. Eventually the LAA will be in RAR[0] and 4414 * RAR[14] 4415 */ 4416 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4417 adapter->hw.mac.rar_entry_count - 1); 4418 } 4419 4420 return 0; 4421 } 4422 4423 /** 4424 * e1000e_update_phy_task - work thread to update phy 4425 * @work: pointer to our work struct 4426 * 4427 * this worker thread exists because we must acquire a 4428 * semaphore to read the phy, which we could msleep while 4429 * waiting for it, and we can't msleep in a timer. 4430 **/ 4431 static void e1000e_update_phy_task(struct work_struct *work) 4432 { 4433 struct e1000_adapter *adapter = container_of(work, 4434 struct e1000_adapter, update_phy_task); 4435 4436 if (test_bit(__E1000_DOWN, &adapter->state)) 4437 return; 4438 4439 e1000_get_phy_info(&adapter->hw); 4440 } 4441 4442 /** 4443 * e1000_update_phy_info - timre call-back to update PHY info 4444 * @data: pointer to adapter cast into an unsigned long 4445 * 4446 * Need to wait a few seconds after link up to get diagnostic information from 4447 * the phy 4448 **/ 4449 static void e1000_update_phy_info(unsigned long data) 4450 { 4451 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 4452 4453 if (test_bit(__E1000_DOWN, &adapter->state)) 4454 return; 4455 4456 schedule_work(&adapter->update_phy_task); 4457 } 4458 4459 /** 4460 * e1000e_update_phy_stats - Update the PHY statistics counters 4461 * @adapter: board private structure 4462 * 4463 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4464 **/ 4465 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4466 { 4467 struct e1000_hw *hw = &adapter->hw; 4468 s32 ret_val; 4469 u16 phy_data; 4470 4471 ret_val = hw->phy.ops.acquire(hw); 4472 if (ret_val) 4473 return; 4474 4475 /* A page set is expensive so check if already on desired page. 4476 * If not, set to the page with the PHY status registers. 4477 */ 4478 hw->phy.addr = 1; 4479 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4480 &phy_data); 4481 if (ret_val) 4482 goto release; 4483 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4484 ret_val = hw->phy.ops.set_page(hw, 4485 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4486 if (ret_val) 4487 goto release; 4488 } 4489 4490 /* Single Collision Count */ 4491 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4492 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4493 if (!ret_val) 4494 adapter->stats.scc += phy_data; 4495 4496 /* Excessive Collision Count */ 4497 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4498 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4499 if (!ret_val) 4500 adapter->stats.ecol += phy_data; 4501 4502 /* Multiple Collision Count */ 4503 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4504 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4505 if (!ret_val) 4506 adapter->stats.mcc += phy_data; 4507 4508 /* Late Collision Count */ 4509 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4510 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4511 if (!ret_val) 4512 adapter->stats.latecol += phy_data; 4513 4514 /* Collision Count - also used for adaptive IFS */ 4515 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4516 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4517 if (!ret_val) 4518 hw->mac.collision_delta = phy_data; 4519 4520 /* Defer Count */ 4521 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4522 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4523 if (!ret_val) 4524 adapter->stats.dc += phy_data; 4525 4526 /* Transmit with no CRS */ 4527 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4528 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4529 if (!ret_val) 4530 adapter->stats.tncrs += phy_data; 4531 4532 release: 4533 hw->phy.ops.release(hw); 4534 } 4535 4536 /** 4537 * e1000e_update_stats - Update the board statistics counters 4538 * @adapter: board private structure 4539 **/ 4540 static void e1000e_update_stats(struct e1000_adapter *adapter) 4541 { 4542 struct net_device *netdev = adapter->netdev; 4543 struct e1000_hw *hw = &adapter->hw; 4544 struct pci_dev *pdev = adapter->pdev; 4545 4546 /* Prevent stats update while adapter is being reset, or if the pci 4547 * connection is down. 4548 */ 4549 if (adapter->link_speed == 0) 4550 return; 4551 if (pci_channel_offline(pdev)) 4552 return; 4553 4554 adapter->stats.crcerrs += er32(CRCERRS); 4555 adapter->stats.gprc += er32(GPRC); 4556 adapter->stats.gorc += er32(GORCL); 4557 er32(GORCH); /* Clear gorc */ 4558 adapter->stats.bprc += er32(BPRC); 4559 adapter->stats.mprc += er32(MPRC); 4560 adapter->stats.roc += er32(ROC); 4561 4562 adapter->stats.mpc += er32(MPC); 4563 4564 /* Half-duplex statistics */ 4565 if (adapter->link_duplex == HALF_DUPLEX) { 4566 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4567 e1000e_update_phy_stats(adapter); 4568 } else { 4569 adapter->stats.scc += er32(SCC); 4570 adapter->stats.ecol += er32(ECOL); 4571 adapter->stats.mcc += er32(MCC); 4572 adapter->stats.latecol += er32(LATECOL); 4573 adapter->stats.dc += er32(DC); 4574 4575 hw->mac.collision_delta = er32(COLC); 4576 4577 if ((hw->mac.type != e1000_82574) && 4578 (hw->mac.type != e1000_82583)) 4579 adapter->stats.tncrs += er32(TNCRS); 4580 } 4581 adapter->stats.colc += hw->mac.collision_delta; 4582 } 4583 4584 adapter->stats.xonrxc += er32(XONRXC); 4585 adapter->stats.xontxc += er32(XONTXC); 4586 adapter->stats.xoffrxc += er32(XOFFRXC); 4587 adapter->stats.xofftxc += er32(XOFFTXC); 4588 adapter->stats.gptc += er32(GPTC); 4589 adapter->stats.gotc += er32(GOTCL); 4590 er32(GOTCH); /* Clear gotc */ 4591 adapter->stats.rnbc += er32(RNBC); 4592 adapter->stats.ruc += er32(RUC); 4593 4594 adapter->stats.mptc += er32(MPTC); 4595 adapter->stats.bptc += er32(BPTC); 4596 4597 /* used for adaptive IFS */ 4598 4599 hw->mac.tx_packet_delta = er32(TPT); 4600 adapter->stats.tpt += hw->mac.tx_packet_delta; 4601 4602 adapter->stats.algnerrc += er32(ALGNERRC); 4603 adapter->stats.rxerrc += er32(RXERRC); 4604 adapter->stats.cexterr += er32(CEXTERR); 4605 adapter->stats.tsctc += er32(TSCTC); 4606 adapter->stats.tsctfc += er32(TSCTFC); 4607 4608 /* Fill out the OS statistics structure */ 4609 netdev->stats.multicast = adapter->stats.mprc; 4610 netdev->stats.collisions = adapter->stats.colc; 4611 4612 /* Rx Errors */ 4613 4614 /* RLEC on some newer hardware can be incorrect so build 4615 * our own version based on RUC and ROC 4616 */ 4617 netdev->stats.rx_errors = adapter->stats.rxerrc + 4618 adapter->stats.crcerrs + adapter->stats.algnerrc + 4619 adapter->stats.ruc + adapter->stats.roc + 4620 adapter->stats.cexterr; 4621 netdev->stats.rx_length_errors = adapter->stats.ruc + 4622 adapter->stats.roc; 4623 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 4624 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 4625 netdev->stats.rx_missed_errors = adapter->stats.mpc; 4626 4627 /* Tx Errors */ 4628 netdev->stats.tx_errors = adapter->stats.ecol + 4629 adapter->stats.latecol; 4630 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 4631 netdev->stats.tx_window_errors = adapter->stats.latecol; 4632 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 4633 4634 /* Tx Dropped needs to be maintained elsewhere */ 4635 4636 /* Management Stats */ 4637 adapter->stats.mgptc += er32(MGTPTC); 4638 adapter->stats.mgprc += er32(MGTPRC); 4639 adapter->stats.mgpdc += er32(MGTPDC); 4640 4641 /* Correctable ECC Errors */ 4642 if (hw->mac.type == e1000_pch_lpt) { 4643 u32 pbeccsts = er32(PBECCSTS); 4644 adapter->corr_errors += 4645 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 4646 adapter->uncorr_errors += 4647 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 4648 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 4649 } 4650 } 4651 4652 /** 4653 * e1000_phy_read_status - Update the PHY register status snapshot 4654 * @adapter: board private structure 4655 **/ 4656 static void e1000_phy_read_status(struct e1000_adapter *adapter) 4657 { 4658 struct e1000_hw *hw = &adapter->hw; 4659 struct e1000_phy_regs *phy = &adapter->phy_regs; 4660 4661 if ((er32(STATUS) & E1000_STATUS_LU) && 4662 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 4663 int ret_val; 4664 4665 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 4666 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 4667 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 4668 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 4669 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 4670 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 4671 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 4672 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 4673 if (ret_val) 4674 e_warn("Error reading PHY register\n"); 4675 } else { 4676 /* Do not read PHY registers if link is not up 4677 * Set values to typical power-on defaults 4678 */ 4679 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 4680 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 4681 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 4682 BMSR_ERCAP); 4683 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 4684 ADVERTISE_ALL | ADVERTISE_CSMA); 4685 phy->lpa = 0; 4686 phy->expansion = EXPANSION_ENABLENPAGE; 4687 phy->ctrl1000 = ADVERTISE_1000FULL; 4688 phy->stat1000 = 0; 4689 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 4690 } 4691 } 4692 4693 static void e1000_print_link_info(struct e1000_adapter *adapter) 4694 { 4695 struct e1000_hw *hw = &adapter->hw; 4696 u32 ctrl = er32(CTRL); 4697 4698 /* Link status message must follow this format for user tools */ 4699 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4700 adapter->netdev->name, adapter->link_speed, 4701 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 4702 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 4703 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 4704 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 4705 } 4706 4707 static bool e1000e_has_link(struct e1000_adapter *adapter) 4708 { 4709 struct e1000_hw *hw = &adapter->hw; 4710 bool link_active = false; 4711 s32 ret_val = 0; 4712 4713 /* get_link_status is set on LSC (link status) interrupt or 4714 * Rx sequence error interrupt. get_link_status will stay 4715 * false until the check_for_link establishes link 4716 * for copper adapters ONLY 4717 */ 4718 switch (hw->phy.media_type) { 4719 case e1000_media_type_copper: 4720 if (hw->mac.get_link_status) { 4721 ret_val = hw->mac.ops.check_for_link(hw); 4722 link_active = !hw->mac.get_link_status; 4723 } else { 4724 link_active = true; 4725 } 4726 break; 4727 case e1000_media_type_fiber: 4728 ret_val = hw->mac.ops.check_for_link(hw); 4729 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 4730 break; 4731 case e1000_media_type_internal_serdes: 4732 ret_val = hw->mac.ops.check_for_link(hw); 4733 link_active = adapter->hw.mac.serdes_has_link; 4734 break; 4735 default: 4736 case e1000_media_type_unknown: 4737 break; 4738 } 4739 4740 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 4741 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 4742 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 4743 e_info("Gigabit has been disabled, downgrading speed\n"); 4744 } 4745 4746 return link_active; 4747 } 4748 4749 static void e1000e_enable_receives(struct e1000_adapter *adapter) 4750 { 4751 /* make sure the receive unit is started */ 4752 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 4753 (adapter->flags & FLAG_RESTART_NOW)) { 4754 struct e1000_hw *hw = &adapter->hw; 4755 u32 rctl = er32(RCTL); 4756 ew32(RCTL, rctl | E1000_RCTL_EN); 4757 adapter->flags &= ~FLAG_RESTART_NOW; 4758 } 4759 } 4760 4761 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 4762 { 4763 struct e1000_hw *hw = &adapter->hw; 4764 4765 /* With 82574 controllers, PHY needs to be checked periodically 4766 * for hung state and reset, if two calls return true 4767 */ 4768 if (e1000_check_phy_82574(hw)) 4769 adapter->phy_hang_count++; 4770 else 4771 adapter->phy_hang_count = 0; 4772 4773 if (adapter->phy_hang_count > 1) { 4774 adapter->phy_hang_count = 0; 4775 schedule_work(&adapter->reset_task); 4776 } 4777 } 4778 4779 /** 4780 * e1000_watchdog - Timer Call-back 4781 * @data: pointer to adapter cast into an unsigned long 4782 **/ 4783 static void e1000_watchdog(unsigned long data) 4784 { 4785 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 4786 4787 /* Do the rest outside of interrupt context */ 4788 schedule_work(&adapter->watchdog_task); 4789 4790 /* TODO: make this use queue_delayed_work() */ 4791 } 4792 4793 static void e1000_watchdog_task(struct work_struct *work) 4794 { 4795 struct e1000_adapter *adapter = container_of(work, 4796 struct e1000_adapter, watchdog_task); 4797 struct net_device *netdev = adapter->netdev; 4798 struct e1000_mac_info *mac = &adapter->hw.mac; 4799 struct e1000_phy_info *phy = &adapter->hw.phy; 4800 struct e1000_ring *tx_ring = adapter->tx_ring; 4801 struct e1000_hw *hw = &adapter->hw; 4802 u32 link, tctl; 4803 4804 if (test_bit(__E1000_DOWN, &adapter->state)) 4805 return; 4806 4807 link = e1000e_has_link(adapter); 4808 if ((netif_carrier_ok(netdev)) && link) { 4809 /* Cancel scheduled suspend requests. */ 4810 pm_runtime_resume(netdev->dev.parent); 4811 4812 e1000e_enable_receives(adapter); 4813 goto link_up; 4814 } 4815 4816 if ((e1000e_enable_tx_pkt_filtering(hw)) && 4817 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 4818 e1000_update_mng_vlan(adapter); 4819 4820 if (link) { 4821 if (!netif_carrier_ok(netdev)) { 4822 bool txb2b = true; 4823 4824 /* Cancel scheduled suspend requests. */ 4825 pm_runtime_resume(netdev->dev.parent); 4826 4827 /* update snapshot of PHY registers on LSC */ 4828 e1000_phy_read_status(adapter); 4829 mac->ops.get_link_up_info(&adapter->hw, 4830 &adapter->link_speed, 4831 &adapter->link_duplex); 4832 e1000_print_link_info(adapter); 4833 4834 /* check if SmartSpeed worked */ 4835 e1000e_check_downshift(hw); 4836 if (phy->speed_downgraded) 4837 netdev_warn(netdev, 4838 "Link Speed was downgraded by SmartSpeed\n"); 4839 4840 /* On supported PHYs, check for duplex mismatch only 4841 * if link has autonegotiated at 10/100 half 4842 */ 4843 if ((hw->phy.type == e1000_phy_igp_3 || 4844 hw->phy.type == e1000_phy_bm) && 4845 (hw->mac.autoneg == true) && 4846 (adapter->link_speed == SPEED_10 || 4847 adapter->link_speed == SPEED_100) && 4848 (adapter->link_duplex == HALF_DUPLEX)) { 4849 u16 autoneg_exp; 4850 4851 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 4852 4853 if (!(autoneg_exp & EXPANSION_NWAY)) 4854 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 4855 } 4856 4857 /* adjust timeout factor according to speed/duplex */ 4858 adapter->tx_timeout_factor = 1; 4859 switch (adapter->link_speed) { 4860 case SPEED_10: 4861 txb2b = false; 4862 adapter->tx_timeout_factor = 16; 4863 break; 4864 case SPEED_100: 4865 txb2b = false; 4866 adapter->tx_timeout_factor = 10; 4867 break; 4868 } 4869 4870 /* workaround: re-program speed mode bit after 4871 * link-up event 4872 */ 4873 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 4874 !txb2b) { 4875 u32 tarc0; 4876 tarc0 = er32(TARC(0)); 4877 tarc0 &= ~SPEED_MODE_BIT; 4878 ew32(TARC(0), tarc0); 4879 } 4880 4881 /* disable TSO for pcie and 10/100 speeds, to avoid 4882 * some hardware issues 4883 */ 4884 if (!(adapter->flags & FLAG_TSO_FORCE)) { 4885 switch (adapter->link_speed) { 4886 case SPEED_10: 4887 case SPEED_100: 4888 e_info("10/100 speed: disabling TSO\n"); 4889 netdev->features &= ~NETIF_F_TSO; 4890 netdev->features &= ~NETIF_F_TSO6; 4891 break; 4892 case SPEED_1000: 4893 netdev->features |= NETIF_F_TSO; 4894 netdev->features |= NETIF_F_TSO6; 4895 break; 4896 default: 4897 /* oops */ 4898 break; 4899 } 4900 } 4901 4902 /* enable transmits in the hardware, need to do this 4903 * after setting TARC(0) 4904 */ 4905 tctl = er32(TCTL); 4906 tctl |= E1000_TCTL_EN; 4907 ew32(TCTL, tctl); 4908 4909 /* Perform any post-link-up configuration before 4910 * reporting link up. 4911 */ 4912 if (phy->ops.cfg_on_link_up) 4913 phy->ops.cfg_on_link_up(hw); 4914 4915 netif_carrier_on(netdev); 4916 4917 if (!test_bit(__E1000_DOWN, &adapter->state)) 4918 mod_timer(&adapter->phy_info_timer, 4919 round_jiffies(jiffies + 2 * HZ)); 4920 } 4921 } else { 4922 if (netif_carrier_ok(netdev)) { 4923 adapter->link_speed = 0; 4924 adapter->link_duplex = 0; 4925 /* Link status message must follow this format */ 4926 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4927 netif_carrier_off(netdev); 4928 if (!test_bit(__E1000_DOWN, &adapter->state)) 4929 mod_timer(&adapter->phy_info_timer, 4930 round_jiffies(jiffies + 2 * HZ)); 4931 4932 /* The link is lost so the controller stops DMA. 4933 * If there is queued Tx work that cannot be done 4934 * or if on an 8000ES2LAN which requires a Rx packet 4935 * buffer work-around on link down event, reset the 4936 * controller to flush the Tx/Rx packet buffers. 4937 * (Do the reset outside of interrupt context). 4938 */ 4939 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) || 4940 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 4941 adapter->flags |= FLAG_RESTART_NOW; 4942 else 4943 pm_schedule_suspend(netdev->dev.parent, 4944 LINK_TIMEOUT); 4945 } 4946 } 4947 4948 link_up: 4949 spin_lock(&adapter->stats64_lock); 4950 e1000e_update_stats(adapter); 4951 4952 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 4953 adapter->tpt_old = adapter->stats.tpt; 4954 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 4955 adapter->colc_old = adapter->stats.colc; 4956 4957 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 4958 adapter->gorc_old = adapter->stats.gorc; 4959 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 4960 adapter->gotc_old = adapter->stats.gotc; 4961 spin_unlock(&adapter->stats64_lock); 4962 4963 if (adapter->flags & FLAG_RESTART_NOW) { 4964 schedule_work(&adapter->reset_task); 4965 /* return immediately since reset is imminent */ 4966 return; 4967 } 4968 4969 e1000e_update_adaptive(&adapter->hw); 4970 4971 /* Simple mode for Interrupt Throttle Rate (ITR) */ 4972 if (adapter->itr_setting == 4) { 4973 /* Symmetric Tx/Rx gets a reduced ITR=2000; 4974 * Total asymmetrical Tx or Rx gets ITR=8000; 4975 * everyone else is between 2000-8000. 4976 */ 4977 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 4978 u32 dif = (adapter->gotc > adapter->gorc ? 4979 adapter->gotc - adapter->gorc : 4980 adapter->gorc - adapter->gotc) / 10000; 4981 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 4982 4983 e1000e_write_itr(adapter, itr); 4984 } 4985 4986 /* Cause software interrupt to ensure Rx ring is cleaned */ 4987 if (adapter->msix_entries) 4988 ew32(ICS, adapter->rx_ring->ims_val); 4989 else 4990 ew32(ICS, E1000_ICS_RXDMT0); 4991 4992 /* flush pending descriptors to memory before detecting Tx hang */ 4993 e1000e_flush_descriptors(adapter); 4994 4995 /* Force detection of hung controller every watchdog period */ 4996 adapter->detect_tx_hung = true; 4997 4998 /* With 82571 controllers, LAA may be overwritten due to controller 4999 * reset from the other port. Set the appropriate LAA in RAR[0] 5000 */ 5001 if (e1000e_get_laa_state_82571(hw)) 5002 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5003 5004 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5005 e1000e_check_82574_phy_workaround(adapter); 5006 5007 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5008 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5009 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5010 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5011 er32(RXSTMPH); 5012 adapter->rx_hwtstamp_cleared++; 5013 } else { 5014 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5015 } 5016 } 5017 5018 /* Reset the timer */ 5019 if (!test_bit(__E1000_DOWN, &adapter->state)) 5020 mod_timer(&adapter->watchdog_timer, 5021 round_jiffies(jiffies + 2 * HZ)); 5022 } 5023 5024 #define E1000_TX_FLAGS_CSUM 0x00000001 5025 #define E1000_TX_FLAGS_VLAN 0x00000002 5026 #define E1000_TX_FLAGS_TSO 0x00000004 5027 #define E1000_TX_FLAGS_IPV4 0x00000008 5028 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5029 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5030 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5031 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5032 5033 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb) 5034 { 5035 struct e1000_context_desc *context_desc; 5036 struct e1000_buffer *buffer_info; 5037 unsigned int i; 5038 u32 cmd_length = 0; 5039 u16 ipcse = 0, mss; 5040 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5041 5042 if (!skb_is_gso(skb)) 5043 return 0; 5044 5045 if (skb_header_cloned(skb)) { 5046 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 5047 5048 if (err) 5049 return err; 5050 } 5051 5052 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5053 mss = skb_shinfo(skb)->gso_size; 5054 if (skb->protocol == htons(ETH_P_IP)) { 5055 struct iphdr *iph = ip_hdr(skb); 5056 iph->tot_len = 0; 5057 iph->check = 0; 5058 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5059 0, IPPROTO_TCP, 0); 5060 cmd_length = E1000_TXD_CMD_IP; 5061 ipcse = skb_transport_offset(skb) - 1; 5062 } else if (skb_is_gso_v6(skb)) { 5063 ipv6_hdr(skb)->payload_len = 0; 5064 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5065 &ipv6_hdr(skb)->daddr, 5066 0, IPPROTO_TCP, 0); 5067 ipcse = 0; 5068 } 5069 ipcss = skb_network_offset(skb); 5070 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5071 tucss = skb_transport_offset(skb); 5072 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5073 5074 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5075 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5076 5077 i = tx_ring->next_to_use; 5078 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5079 buffer_info = &tx_ring->buffer_info[i]; 5080 5081 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5082 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5083 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5084 context_desc->upper_setup.tcp_fields.tucss = tucss; 5085 context_desc->upper_setup.tcp_fields.tucso = tucso; 5086 context_desc->upper_setup.tcp_fields.tucse = 0; 5087 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5088 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5089 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5090 5091 buffer_info->time_stamp = jiffies; 5092 buffer_info->next_to_watch = i; 5093 5094 i++; 5095 if (i == tx_ring->count) 5096 i = 0; 5097 tx_ring->next_to_use = i; 5098 5099 return 1; 5100 } 5101 5102 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb) 5103 { 5104 struct e1000_adapter *adapter = tx_ring->adapter; 5105 struct e1000_context_desc *context_desc; 5106 struct e1000_buffer *buffer_info; 5107 unsigned int i; 5108 u8 css; 5109 u32 cmd_len = E1000_TXD_CMD_DEXT; 5110 __be16 protocol; 5111 5112 if (skb->ip_summed != CHECKSUM_PARTIAL) 5113 return 0; 5114 5115 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) 5116 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; 5117 else 5118 protocol = skb->protocol; 5119 5120 switch (protocol) { 5121 case cpu_to_be16(ETH_P_IP): 5122 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5123 cmd_len |= E1000_TXD_CMD_TCP; 5124 break; 5125 case cpu_to_be16(ETH_P_IPV6): 5126 /* XXX not handling all IPV6 headers */ 5127 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5128 cmd_len |= E1000_TXD_CMD_TCP; 5129 break; 5130 default: 5131 if (unlikely(net_ratelimit())) 5132 e_warn("checksum_partial proto=%x!\n", 5133 be16_to_cpu(protocol)); 5134 break; 5135 } 5136 5137 css = skb_checksum_start_offset(skb); 5138 5139 i = tx_ring->next_to_use; 5140 buffer_info = &tx_ring->buffer_info[i]; 5141 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5142 5143 context_desc->lower_setup.ip_config = 0; 5144 context_desc->upper_setup.tcp_fields.tucss = css; 5145 context_desc->upper_setup.tcp_fields.tucso = 5146 css + skb->csum_offset; 5147 context_desc->upper_setup.tcp_fields.tucse = 0; 5148 context_desc->tcp_seg_setup.data = 0; 5149 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5150 5151 buffer_info->time_stamp = jiffies; 5152 buffer_info->next_to_watch = i; 5153 5154 i++; 5155 if (i == tx_ring->count) 5156 i = 0; 5157 tx_ring->next_to_use = i; 5158 5159 return 1; 5160 } 5161 5162 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5163 unsigned int first, unsigned int max_per_txd, 5164 unsigned int nr_frags) 5165 { 5166 struct e1000_adapter *adapter = tx_ring->adapter; 5167 struct pci_dev *pdev = adapter->pdev; 5168 struct e1000_buffer *buffer_info; 5169 unsigned int len = skb_headlen(skb); 5170 unsigned int offset = 0, size, count = 0, i; 5171 unsigned int f, bytecount, segs; 5172 5173 i = tx_ring->next_to_use; 5174 5175 while (len) { 5176 buffer_info = &tx_ring->buffer_info[i]; 5177 size = min(len, max_per_txd); 5178 5179 buffer_info->length = size; 5180 buffer_info->time_stamp = jiffies; 5181 buffer_info->next_to_watch = i; 5182 buffer_info->dma = dma_map_single(&pdev->dev, 5183 skb->data + offset, 5184 size, DMA_TO_DEVICE); 5185 buffer_info->mapped_as_page = false; 5186 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5187 goto dma_error; 5188 5189 len -= size; 5190 offset += size; 5191 count++; 5192 5193 if (len) { 5194 i++; 5195 if (i == tx_ring->count) 5196 i = 0; 5197 } 5198 } 5199 5200 for (f = 0; f < nr_frags; f++) { 5201 const struct skb_frag_struct *frag; 5202 5203 frag = &skb_shinfo(skb)->frags[f]; 5204 len = skb_frag_size(frag); 5205 offset = 0; 5206 5207 while (len) { 5208 i++; 5209 if (i == tx_ring->count) 5210 i = 0; 5211 5212 buffer_info = &tx_ring->buffer_info[i]; 5213 size = min(len, max_per_txd); 5214 5215 buffer_info->length = size; 5216 buffer_info->time_stamp = jiffies; 5217 buffer_info->next_to_watch = i; 5218 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5219 offset, size, DMA_TO_DEVICE); 5220 buffer_info->mapped_as_page = true; 5221 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5222 goto dma_error; 5223 5224 len -= size; 5225 offset += size; 5226 count++; 5227 } 5228 } 5229 5230 segs = skb_shinfo(skb)->gso_segs ? : 1; 5231 /* multiply data chunks by size of headers */ 5232 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5233 5234 tx_ring->buffer_info[i].skb = skb; 5235 tx_ring->buffer_info[i].segs = segs; 5236 tx_ring->buffer_info[i].bytecount = bytecount; 5237 tx_ring->buffer_info[first].next_to_watch = i; 5238 5239 return count; 5240 5241 dma_error: 5242 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5243 buffer_info->dma = 0; 5244 if (count) 5245 count--; 5246 5247 while (count--) { 5248 if (i == 0) 5249 i += tx_ring->count; 5250 i--; 5251 buffer_info = &tx_ring->buffer_info[i]; 5252 e1000_put_txbuf(tx_ring, buffer_info); 5253 } 5254 5255 return 0; 5256 } 5257 5258 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5259 { 5260 struct e1000_adapter *adapter = tx_ring->adapter; 5261 struct e1000_tx_desc *tx_desc = NULL; 5262 struct e1000_buffer *buffer_info; 5263 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5264 unsigned int i; 5265 5266 if (tx_flags & E1000_TX_FLAGS_TSO) { 5267 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5268 E1000_TXD_CMD_TSE; 5269 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5270 5271 if (tx_flags & E1000_TX_FLAGS_IPV4) 5272 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5273 } 5274 5275 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5276 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5277 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5278 } 5279 5280 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5281 txd_lower |= E1000_TXD_CMD_VLE; 5282 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5283 } 5284 5285 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5286 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5287 5288 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5289 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5290 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5291 } 5292 5293 i = tx_ring->next_to_use; 5294 5295 do { 5296 buffer_info = &tx_ring->buffer_info[i]; 5297 tx_desc = E1000_TX_DESC(*tx_ring, i); 5298 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5299 tx_desc->lower.data = 5300 cpu_to_le32(txd_lower | buffer_info->length); 5301 tx_desc->upper.data = cpu_to_le32(txd_upper); 5302 5303 i++; 5304 if (i == tx_ring->count) 5305 i = 0; 5306 } while (--count > 0); 5307 5308 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5309 5310 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5311 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5312 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5313 5314 /* Force memory writes to complete before letting h/w 5315 * know there are new descriptors to fetch. (Only 5316 * applicable for weak-ordered memory model archs, 5317 * such as IA-64). 5318 */ 5319 wmb(); 5320 5321 tx_ring->next_to_use = i; 5322 5323 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5324 e1000e_update_tdt_wa(tx_ring, i); 5325 else 5326 writel(i, tx_ring->tail); 5327 5328 /* we need this if more than one processor can write to our tail 5329 * at a time, it synchronizes IO on IA64/Altix systems 5330 */ 5331 mmiowb(); 5332 } 5333 5334 #define MINIMUM_DHCP_PACKET_SIZE 282 5335 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5336 struct sk_buff *skb) 5337 { 5338 struct e1000_hw *hw = &adapter->hw; 5339 u16 length, offset; 5340 5341 if (vlan_tx_tag_present(skb) && 5342 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5343 (adapter->hw.mng_cookie.status & 5344 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5345 return 0; 5346 5347 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5348 return 0; 5349 5350 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP)) 5351 return 0; 5352 5353 { 5354 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14); 5355 struct udphdr *udp; 5356 5357 if (ip->protocol != IPPROTO_UDP) 5358 return 0; 5359 5360 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5361 if (ntohs(udp->dest) != 67) 5362 return 0; 5363 5364 offset = (u8 *)udp + 8 - skb->data; 5365 length = skb->len - offset; 5366 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5367 } 5368 5369 return 0; 5370 } 5371 5372 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5373 { 5374 struct e1000_adapter *adapter = tx_ring->adapter; 5375 5376 netif_stop_queue(adapter->netdev); 5377 /* Herbert's original patch had: 5378 * smp_mb__after_netif_stop_queue(); 5379 * but since that doesn't exist yet, just open code it. 5380 */ 5381 smp_mb(); 5382 5383 /* We need to check again in a case another CPU has just 5384 * made room available. 5385 */ 5386 if (e1000_desc_unused(tx_ring) < size) 5387 return -EBUSY; 5388 5389 /* A reprieve! */ 5390 netif_start_queue(adapter->netdev); 5391 ++adapter->restart_queue; 5392 return 0; 5393 } 5394 5395 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5396 { 5397 BUG_ON(size > tx_ring->count); 5398 5399 if (e1000_desc_unused(tx_ring) >= size) 5400 return 0; 5401 return __e1000_maybe_stop_tx(tx_ring, size); 5402 } 5403 5404 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5405 struct net_device *netdev) 5406 { 5407 struct e1000_adapter *adapter = netdev_priv(netdev); 5408 struct e1000_ring *tx_ring = adapter->tx_ring; 5409 unsigned int first; 5410 unsigned int tx_flags = 0; 5411 unsigned int len = skb_headlen(skb); 5412 unsigned int nr_frags; 5413 unsigned int mss; 5414 int count = 0; 5415 int tso; 5416 unsigned int f; 5417 5418 if (test_bit(__E1000_DOWN, &adapter->state)) { 5419 dev_kfree_skb_any(skb); 5420 return NETDEV_TX_OK; 5421 } 5422 5423 if (skb->len <= 0) { 5424 dev_kfree_skb_any(skb); 5425 return NETDEV_TX_OK; 5426 } 5427 5428 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5429 * pad skb in order to meet this minimum size requirement 5430 */ 5431 if (unlikely(skb->len < 17)) { 5432 if (skb_pad(skb, 17 - skb->len)) 5433 return NETDEV_TX_OK; 5434 skb->len = 17; 5435 skb_set_tail_pointer(skb, 17); 5436 } 5437 5438 mss = skb_shinfo(skb)->gso_size; 5439 if (mss) { 5440 u8 hdr_len; 5441 5442 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5443 * points to just header, pull a few bytes of payload from 5444 * frags into skb->data 5445 */ 5446 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5447 /* we do this workaround for ES2LAN, but it is un-necessary, 5448 * avoiding it could save a lot of cycles 5449 */ 5450 if (skb->data_len && (hdr_len == len)) { 5451 unsigned int pull_size; 5452 5453 pull_size = min_t(unsigned int, 4, skb->data_len); 5454 if (!__pskb_pull_tail(skb, pull_size)) { 5455 e_err("__pskb_pull_tail failed.\n"); 5456 dev_kfree_skb_any(skb); 5457 return NETDEV_TX_OK; 5458 } 5459 len = skb_headlen(skb); 5460 } 5461 } 5462 5463 /* reserve a descriptor for the offload context */ 5464 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5465 count++; 5466 count++; 5467 5468 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5469 5470 nr_frags = skb_shinfo(skb)->nr_frags; 5471 for (f = 0; f < nr_frags; f++) 5472 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5473 adapter->tx_fifo_limit); 5474 5475 if (adapter->hw.mac.tx_pkt_filtering) 5476 e1000_transfer_dhcp_info(adapter, skb); 5477 5478 /* need: count + 2 desc gap to keep tail from touching 5479 * head, otherwise try next time 5480 */ 5481 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5482 return NETDEV_TX_BUSY; 5483 5484 if (vlan_tx_tag_present(skb)) { 5485 tx_flags |= E1000_TX_FLAGS_VLAN; 5486 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT); 5487 } 5488 5489 first = tx_ring->next_to_use; 5490 5491 tso = e1000_tso(tx_ring, skb); 5492 if (tso < 0) { 5493 dev_kfree_skb_any(skb); 5494 return NETDEV_TX_OK; 5495 } 5496 5497 if (tso) 5498 tx_flags |= E1000_TX_FLAGS_TSO; 5499 else if (e1000_tx_csum(tx_ring, skb)) 5500 tx_flags |= E1000_TX_FLAGS_CSUM; 5501 5502 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5503 * 82571 hardware supports TSO capabilities for IPv6 as well... 5504 * no longer assume, we must. 5505 */ 5506 if (skb->protocol == htons(ETH_P_IP)) 5507 tx_flags |= E1000_TX_FLAGS_IPV4; 5508 5509 if (unlikely(skb->no_fcs)) 5510 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5511 5512 /* if count is 0 then mapping error has occurred */ 5513 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5514 nr_frags); 5515 if (count) { 5516 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5517 !adapter->tx_hwtstamp_skb)) { 5518 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5519 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5520 adapter->tx_hwtstamp_skb = skb_get(skb); 5521 schedule_work(&adapter->tx_hwtstamp_work); 5522 } else { 5523 skb_tx_timestamp(skb); 5524 } 5525 5526 netdev_sent_queue(netdev, skb->len); 5527 e1000_tx_queue(tx_ring, tx_flags, count); 5528 /* Make sure there is space in the ring for the next send. */ 5529 e1000_maybe_stop_tx(tx_ring, 5530 (MAX_SKB_FRAGS * 5531 DIV_ROUND_UP(PAGE_SIZE, 5532 adapter->tx_fifo_limit) + 2)); 5533 } else { 5534 dev_kfree_skb_any(skb); 5535 tx_ring->buffer_info[first].time_stamp = 0; 5536 tx_ring->next_to_use = first; 5537 } 5538 5539 return NETDEV_TX_OK; 5540 } 5541 5542 /** 5543 * e1000_tx_timeout - Respond to a Tx Hang 5544 * @netdev: network interface device structure 5545 **/ 5546 static void e1000_tx_timeout(struct net_device *netdev) 5547 { 5548 struct e1000_adapter *adapter = netdev_priv(netdev); 5549 5550 /* Do the reset outside of interrupt context */ 5551 adapter->tx_timeout_count++; 5552 schedule_work(&adapter->reset_task); 5553 } 5554 5555 static void e1000_reset_task(struct work_struct *work) 5556 { 5557 struct e1000_adapter *adapter; 5558 adapter = container_of(work, struct e1000_adapter, reset_task); 5559 5560 /* don't run the task if already down */ 5561 if (test_bit(__E1000_DOWN, &adapter->state)) 5562 return; 5563 5564 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5565 e1000e_dump(adapter); 5566 e_err("Reset adapter unexpectedly\n"); 5567 } 5568 e1000e_reinit_locked(adapter); 5569 } 5570 5571 /** 5572 * e1000_get_stats64 - Get System Network Statistics 5573 * @netdev: network interface device structure 5574 * @stats: rtnl_link_stats64 pointer 5575 * 5576 * Returns the address of the device statistics structure. 5577 **/ 5578 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 5579 struct rtnl_link_stats64 *stats) 5580 { 5581 struct e1000_adapter *adapter = netdev_priv(netdev); 5582 5583 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 5584 spin_lock(&adapter->stats64_lock); 5585 e1000e_update_stats(adapter); 5586 /* Fill out the OS statistics structure */ 5587 stats->rx_bytes = adapter->stats.gorc; 5588 stats->rx_packets = adapter->stats.gprc; 5589 stats->tx_bytes = adapter->stats.gotc; 5590 stats->tx_packets = adapter->stats.gptc; 5591 stats->multicast = adapter->stats.mprc; 5592 stats->collisions = adapter->stats.colc; 5593 5594 /* Rx Errors */ 5595 5596 /* RLEC on some newer hardware can be incorrect so build 5597 * our own version based on RUC and ROC 5598 */ 5599 stats->rx_errors = adapter->stats.rxerrc + 5600 adapter->stats.crcerrs + adapter->stats.algnerrc + 5601 adapter->stats.ruc + adapter->stats.roc + 5602 adapter->stats.cexterr; 5603 stats->rx_length_errors = adapter->stats.ruc + 5604 adapter->stats.roc; 5605 stats->rx_crc_errors = adapter->stats.crcerrs; 5606 stats->rx_frame_errors = adapter->stats.algnerrc; 5607 stats->rx_missed_errors = adapter->stats.mpc; 5608 5609 /* Tx Errors */ 5610 stats->tx_errors = adapter->stats.ecol + 5611 adapter->stats.latecol; 5612 stats->tx_aborted_errors = adapter->stats.ecol; 5613 stats->tx_window_errors = adapter->stats.latecol; 5614 stats->tx_carrier_errors = adapter->stats.tncrs; 5615 5616 /* Tx Dropped needs to be maintained elsewhere */ 5617 5618 spin_unlock(&adapter->stats64_lock); 5619 return stats; 5620 } 5621 5622 /** 5623 * e1000_change_mtu - Change the Maximum Transfer Unit 5624 * @netdev: network interface device structure 5625 * @new_mtu: new value for maximum frame size 5626 * 5627 * Returns 0 on success, negative on failure 5628 **/ 5629 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 5630 { 5631 struct e1000_adapter *adapter = netdev_priv(netdev); 5632 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5633 5634 /* Jumbo frame support */ 5635 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) && 5636 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 5637 e_err("Jumbo Frames not supported.\n"); 5638 return -EINVAL; 5639 } 5640 5641 /* Supported frame sizes */ 5642 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || 5643 (max_frame > adapter->max_hw_frame_size)) { 5644 e_err("Unsupported MTU setting\n"); 5645 return -EINVAL; 5646 } 5647 5648 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 5649 if ((adapter->hw.mac.type >= e1000_pch2lan) && 5650 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 5651 (new_mtu > ETH_DATA_LEN)) { 5652 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 5653 return -EINVAL; 5654 } 5655 5656 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 5657 usleep_range(1000, 2000); 5658 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 5659 adapter->max_frame_size = max_frame; 5660 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5661 netdev->mtu = new_mtu; 5662 if (netif_running(netdev)) 5663 e1000e_down(adapter); 5664 5665 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 5666 * means we reserve 2 more, this pushes us to allocate from the next 5667 * larger slab size. 5668 * i.e. RXBUFFER_2048 --> size-4096 slab 5669 * However with the new *_jumbo_rx* routines, jumbo receives will use 5670 * fragmented skbs 5671 */ 5672 5673 if (max_frame <= 2048) 5674 adapter->rx_buffer_len = 2048; 5675 else 5676 adapter->rx_buffer_len = 4096; 5677 5678 /* adjust allocation if LPE protects us, and we aren't using SBP */ 5679 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || 5680 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)) 5681 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN 5682 + ETH_FCS_LEN; 5683 5684 if (netif_running(netdev)) 5685 e1000e_up(adapter); 5686 else 5687 e1000e_reset(adapter); 5688 5689 clear_bit(__E1000_RESETTING, &adapter->state); 5690 5691 return 0; 5692 } 5693 5694 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 5695 int cmd) 5696 { 5697 struct e1000_adapter *adapter = netdev_priv(netdev); 5698 struct mii_ioctl_data *data = if_mii(ifr); 5699 5700 if (adapter->hw.phy.media_type != e1000_media_type_copper) 5701 return -EOPNOTSUPP; 5702 5703 switch (cmd) { 5704 case SIOCGMIIPHY: 5705 data->phy_id = adapter->hw.phy.addr; 5706 break; 5707 case SIOCGMIIREG: 5708 e1000_phy_read_status(adapter); 5709 5710 switch (data->reg_num & 0x1F) { 5711 case MII_BMCR: 5712 data->val_out = adapter->phy_regs.bmcr; 5713 break; 5714 case MII_BMSR: 5715 data->val_out = adapter->phy_regs.bmsr; 5716 break; 5717 case MII_PHYSID1: 5718 data->val_out = (adapter->hw.phy.id >> 16); 5719 break; 5720 case MII_PHYSID2: 5721 data->val_out = (adapter->hw.phy.id & 0xFFFF); 5722 break; 5723 case MII_ADVERTISE: 5724 data->val_out = adapter->phy_regs.advertise; 5725 break; 5726 case MII_LPA: 5727 data->val_out = adapter->phy_regs.lpa; 5728 break; 5729 case MII_EXPANSION: 5730 data->val_out = adapter->phy_regs.expansion; 5731 break; 5732 case MII_CTRL1000: 5733 data->val_out = adapter->phy_regs.ctrl1000; 5734 break; 5735 case MII_STAT1000: 5736 data->val_out = adapter->phy_regs.stat1000; 5737 break; 5738 case MII_ESTATUS: 5739 data->val_out = adapter->phy_regs.estatus; 5740 break; 5741 default: 5742 return -EIO; 5743 } 5744 break; 5745 case SIOCSMIIREG: 5746 default: 5747 return -EOPNOTSUPP; 5748 } 5749 return 0; 5750 } 5751 5752 /** 5753 * e1000e_hwtstamp_ioctl - control hardware time stamping 5754 * @netdev: network interface device structure 5755 * @ifreq: interface request 5756 * 5757 * Outgoing time stamping can be enabled and disabled. Play nice and 5758 * disable it when requested, although it shouldn't cause any overhead 5759 * when no packet needs it. At most one packet in the queue may be 5760 * marked for time stamping, otherwise it would be impossible to tell 5761 * for sure to which packet the hardware time stamp belongs. 5762 * 5763 * Incoming time stamping has to be configured via the hardware filters. 5764 * Not all combinations are supported, in particular event type has to be 5765 * specified. Matching the kind of event packet is not supported, with the 5766 * exception of "all V2 events regardless of level 2 or 4". 5767 **/ 5768 static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr) 5769 { 5770 struct e1000_adapter *adapter = netdev_priv(netdev); 5771 struct hwtstamp_config config; 5772 int ret_val; 5773 5774 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5775 return -EFAULT; 5776 5777 adapter->hwtstamp_config = config; 5778 5779 ret_val = e1000e_config_hwtstamp(adapter); 5780 if (ret_val) 5781 return ret_val; 5782 5783 config = adapter->hwtstamp_config; 5784 5785 switch (config.rx_filter) { 5786 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 5787 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 5788 case HWTSTAMP_FILTER_PTP_V2_SYNC: 5789 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 5790 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 5791 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 5792 /* With V2 type filters which specify a Sync or Delay Request, 5793 * Path Delay Request/Response messages are also time stamped 5794 * by hardware so notify the caller the requested packets plus 5795 * some others are time stamped. 5796 */ 5797 config.rx_filter = HWTSTAMP_FILTER_SOME; 5798 break; 5799 default: 5800 break; 5801 } 5802 5803 return copy_to_user(ifr->ifr_data, &config, 5804 sizeof(config)) ? -EFAULT : 0; 5805 } 5806 5807 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 5808 { 5809 switch (cmd) { 5810 case SIOCGMIIPHY: 5811 case SIOCGMIIREG: 5812 case SIOCSMIIREG: 5813 return e1000_mii_ioctl(netdev, ifr, cmd); 5814 case SIOCSHWTSTAMP: 5815 return e1000e_hwtstamp_ioctl(netdev, ifr); 5816 default: 5817 return -EOPNOTSUPP; 5818 } 5819 } 5820 5821 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 5822 { 5823 struct e1000_hw *hw = &adapter->hw; 5824 u32 i, mac_reg; 5825 u16 phy_reg, wuc_enable; 5826 int retval; 5827 5828 /* copy MAC RARs to PHY RARs */ 5829 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 5830 5831 retval = hw->phy.ops.acquire(hw); 5832 if (retval) { 5833 e_err("Could not acquire PHY\n"); 5834 return retval; 5835 } 5836 5837 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 5838 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 5839 if (retval) 5840 goto release; 5841 5842 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 5843 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 5844 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 5845 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 5846 (u16)(mac_reg & 0xFFFF)); 5847 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 5848 (u16)((mac_reg >> 16) & 0xFFFF)); 5849 } 5850 5851 /* configure PHY Rx Control register */ 5852 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 5853 mac_reg = er32(RCTL); 5854 if (mac_reg & E1000_RCTL_UPE) 5855 phy_reg |= BM_RCTL_UPE; 5856 if (mac_reg & E1000_RCTL_MPE) 5857 phy_reg |= BM_RCTL_MPE; 5858 phy_reg &= ~(BM_RCTL_MO_MASK); 5859 if (mac_reg & E1000_RCTL_MO_3) 5860 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 5861 << BM_RCTL_MO_SHIFT); 5862 if (mac_reg & E1000_RCTL_BAM) 5863 phy_reg |= BM_RCTL_BAM; 5864 if (mac_reg & E1000_RCTL_PMCF) 5865 phy_reg |= BM_RCTL_PMCF; 5866 mac_reg = er32(CTRL); 5867 if (mac_reg & E1000_CTRL_RFCE) 5868 phy_reg |= BM_RCTL_RFCE; 5869 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 5870 5871 /* enable PHY wakeup in MAC register */ 5872 ew32(WUFC, wufc); 5873 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN); 5874 5875 /* configure and enable PHY wakeup in PHY registers */ 5876 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 5877 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 5878 5879 /* activate PHY wakeup */ 5880 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 5881 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 5882 if (retval) 5883 e_err("Could not set PHY Host Wakeup bit\n"); 5884 release: 5885 hw->phy.ops.release(hw); 5886 5887 return retval; 5888 } 5889 5890 static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake, 5891 bool runtime) 5892 { 5893 struct net_device *netdev = pci_get_drvdata(pdev); 5894 struct e1000_adapter *adapter = netdev_priv(netdev); 5895 struct e1000_hw *hw = &adapter->hw; 5896 u32 ctrl, ctrl_ext, rctl, status; 5897 /* Runtime suspend should only enable wakeup for link changes */ 5898 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 5899 int retval = 0; 5900 5901 netif_device_detach(netdev); 5902 5903 if (netif_running(netdev)) { 5904 int count = E1000_CHECK_RESET_COUNT; 5905 5906 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 5907 usleep_range(10000, 20000); 5908 5909 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 5910 e1000e_down(adapter); 5911 e1000_free_irq(adapter); 5912 } 5913 e1000e_reset_interrupt_capability(adapter); 5914 5915 retval = pci_save_state(pdev); 5916 if (retval) 5917 return retval; 5918 5919 status = er32(STATUS); 5920 if (status & E1000_STATUS_LU) 5921 wufc &= ~E1000_WUFC_LNKC; 5922 5923 if (wufc) { 5924 e1000_setup_rctl(adapter); 5925 e1000e_set_rx_mode(netdev); 5926 5927 /* turn on all-multi mode if wake on multicast is enabled */ 5928 if (wufc & E1000_WUFC_MC) { 5929 rctl = er32(RCTL); 5930 rctl |= E1000_RCTL_MPE; 5931 ew32(RCTL, rctl); 5932 } 5933 5934 ctrl = er32(CTRL); 5935 /* advertise wake from D3Cold */ 5936 #define E1000_CTRL_ADVD3WUC 0x00100000 5937 /* phy power management enable */ 5938 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 5939 ctrl |= E1000_CTRL_ADVD3WUC; 5940 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 5941 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 5942 ew32(CTRL, ctrl); 5943 5944 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 5945 adapter->hw.phy.media_type == 5946 e1000_media_type_internal_serdes) { 5947 /* keep the laser running in D3 */ 5948 ctrl_ext = er32(CTRL_EXT); 5949 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 5950 ew32(CTRL_EXT, ctrl_ext); 5951 } 5952 5953 if (adapter->flags & FLAG_IS_ICH) 5954 e1000_suspend_workarounds_ich8lan(&adapter->hw); 5955 5956 /* Allow time for pending master requests to run */ 5957 e1000e_disable_pcie_master(&adapter->hw); 5958 5959 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 5960 /* enable wakeup by the PHY */ 5961 retval = e1000_init_phy_wakeup(adapter, wufc); 5962 if (retval) 5963 return retval; 5964 } else { 5965 /* enable wakeup by the MAC */ 5966 ew32(WUFC, wufc); 5967 ew32(WUC, E1000_WUC_PME_EN); 5968 } 5969 } else { 5970 ew32(WUC, 0); 5971 ew32(WUFC, 0); 5972 } 5973 5974 *enable_wake = !!wufc; 5975 5976 /* make sure adapter isn't asleep if manageability is enabled */ 5977 if ((adapter->flags & FLAG_MNG_PT_ENABLED) || 5978 (hw->mac.ops.check_mng_mode(hw))) 5979 *enable_wake = true; 5980 5981 if (adapter->hw.phy.type == e1000_phy_igp_3) 5982 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 5983 5984 /* Release control of h/w to f/w. If f/w is AMT enabled, this 5985 * would have already happened in close and is redundant. 5986 */ 5987 e1000e_release_hw_control(adapter); 5988 5989 pci_disable_device(pdev); 5990 5991 return 0; 5992 } 5993 5994 static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake) 5995 { 5996 if (sleep && wake) { 5997 pci_prepare_to_sleep(pdev); 5998 return; 5999 } 6000 6001 pci_wake_from_d3(pdev, wake); 6002 pci_set_power_state(pdev, PCI_D3hot); 6003 } 6004 6005 static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep, 6006 bool wake) 6007 { 6008 struct net_device *netdev = pci_get_drvdata(pdev); 6009 struct e1000_adapter *adapter = netdev_priv(netdev); 6010 6011 /* The pci-e switch on some quad port adapters will report a 6012 * correctable error when the MAC transitions from D0 to D3. To 6013 * prevent this we need to mask off the correctable errors on the 6014 * downstream port of the pci-e switch. 6015 */ 6016 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6017 struct pci_dev *us_dev = pdev->bus->self; 6018 u16 devctl; 6019 6020 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6021 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6022 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6023 6024 e1000_power_off(pdev, sleep, wake); 6025 6026 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6027 } else { 6028 e1000_power_off(pdev, sleep, wake); 6029 } 6030 } 6031 6032 #ifdef CONFIG_PCIEASPM 6033 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6034 { 6035 pci_disable_link_state_locked(pdev, state); 6036 } 6037 #else 6038 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6039 { 6040 u16 aspm_ctl = 0; 6041 6042 if (state & PCIE_LINK_STATE_L0S) 6043 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S; 6044 if (state & PCIE_LINK_STATE_L1) 6045 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1; 6046 6047 /* Both device and parent should have the same ASPM setting. 6048 * Disable ASPM in downstream component first and then upstream. 6049 */ 6050 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl); 6051 6052 if (pdev->bus->self) 6053 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL, 6054 aspm_ctl); 6055 } 6056 #endif 6057 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6058 { 6059 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6060 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "", 6061 (state & PCIE_LINK_STATE_L1) ? "L1" : ""); 6062 6063 __e1000e_disable_aspm(pdev, state); 6064 } 6065 6066 #ifdef CONFIG_PM 6067 static bool e1000e_pm_ready(struct e1000_adapter *adapter) 6068 { 6069 return !!adapter->tx_ring->buffer_info; 6070 } 6071 6072 static int __e1000_resume(struct pci_dev *pdev) 6073 { 6074 struct net_device *netdev = pci_get_drvdata(pdev); 6075 struct e1000_adapter *adapter = netdev_priv(netdev); 6076 struct e1000_hw *hw = &adapter->hw; 6077 u16 aspm_disable_flag = 0; 6078 u32 err; 6079 6080 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6081 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6082 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6083 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6084 if (aspm_disable_flag) 6085 e1000e_disable_aspm(pdev, aspm_disable_flag); 6086 6087 pci_set_power_state(pdev, PCI_D0); 6088 pci_restore_state(pdev); 6089 pci_save_state(pdev); 6090 6091 e1000e_set_interrupt_capability(adapter); 6092 if (netif_running(netdev)) { 6093 err = e1000_request_irq(adapter); 6094 if (err) 6095 return err; 6096 } 6097 6098 if (hw->mac.type >= e1000_pch2lan) 6099 e1000_resume_workarounds_pchlan(&adapter->hw); 6100 6101 e1000e_power_up_phy(adapter); 6102 6103 /* report the system wakeup cause from S3/S4 */ 6104 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6105 u16 phy_data; 6106 6107 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6108 if (phy_data) { 6109 e_info("PHY Wakeup cause - %s\n", 6110 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6111 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6112 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6113 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6114 phy_data & E1000_WUS_LNKC ? 6115 "Link Status Change" : "other"); 6116 } 6117 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6118 } else { 6119 u32 wus = er32(WUS); 6120 if (wus) { 6121 e_info("MAC Wakeup cause - %s\n", 6122 wus & E1000_WUS_EX ? "Unicast Packet" : 6123 wus & E1000_WUS_MC ? "Multicast Packet" : 6124 wus & E1000_WUS_BC ? "Broadcast Packet" : 6125 wus & E1000_WUS_MAG ? "Magic Packet" : 6126 wus & E1000_WUS_LNKC ? "Link Status Change" : 6127 "other"); 6128 } 6129 ew32(WUS, ~0); 6130 } 6131 6132 e1000e_reset(adapter); 6133 6134 e1000_init_manageability_pt(adapter); 6135 6136 if (netif_running(netdev)) 6137 e1000e_up(adapter); 6138 6139 netif_device_attach(netdev); 6140 6141 /* If the controller has AMT, do not set DRV_LOAD until the interface 6142 * is up. For all other cases, let the f/w know that the h/w is now 6143 * under the control of the driver. 6144 */ 6145 if (!(adapter->flags & FLAG_HAS_AMT)) 6146 e1000e_get_hw_control(adapter); 6147 6148 return 0; 6149 } 6150 6151 #ifdef CONFIG_PM_SLEEP 6152 static int e1000_suspend(struct device *dev) 6153 { 6154 struct pci_dev *pdev = to_pci_dev(dev); 6155 int retval; 6156 bool wake; 6157 6158 retval = __e1000_shutdown(pdev, &wake, false); 6159 if (!retval) 6160 e1000_complete_shutdown(pdev, true, wake); 6161 6162 return retval; 6163 } 6164 6165 static int e1000_resume(struct device *dev) 6166 { 6167 struct pci_dev *pdev = to_pci_dev(dev); 6168 struct net_device *netdev = pci_get_drvdata(pdev); 6169 struct e1000_adapter *adapter = netdev_priv(netdev); 6170 6171 if (e1000e_pm_ready(adapter)) 6172 adapter->idle_check = true; 6173 6174 return __e1000_resume(pdev); 6175 } 6176 #endif /* CONFIG_PM_SLEEP */ 6177 6178 #ifdef CONFIG_PM_RUNTIME 6179 static int e1000_runtime_suspend(struct device *dev) 6180 { 6181 struct pci_dev *pdev = to_pci_dev(dev); 6182 struct net_device *netdev = pci_get_drvdata(pdev); 6183 struct e1000_adapter *adapter = netdev_priv(netdev); 6184 6185 if (e1000e_pm_ready(adapter)) { 6186 bool wake; 6187 6188 __e1000_shutdown(pdev, &wake, true); 6189 } 6190 6191 return 0; 6192 } 6193 6194 static int e1000_idle(struct device *dev) 6195 { 6196 struct pci_dev *pdev = to_pci_dev(dev); 6197 struct net_device *netdev = pci_get_drvdata(pdev); 6198 struct e1000_adapter *adapter = netdev_priv(netdev); 6199 6200 if (!e1000e_pm_ready(adapter)) 6201 return 0; 6202 6203 if (adapter->idle_check) { 6204 adapter->idle_check = false; 6205 if (!e1000e_has_link(adapter)) 6206 pm_schedule_suspend(dev, MSEC_PER_SEC); 6207 } 6208 6209 return -EBUSY; 6210 } 6211 6212 static int e1000_runtime_resume(struct device *dev) 6213 { 6214 struct pci_dev *pdev = to_pci_dev(dev); 6215 struct net_device *netdev = pci_get_drvdata(pdev); 6216 struct e1000_adapter *adapter = netdev_priv(netdev); 6217 6218 if (!e1000e_pm_ready(adapter)) 6219 return 0; 6220 6221 adapter->idle_check = !dev->power.runtime_auto; 6222 return __e1000_resume(pdev); 6223 } 6224 #endif /* CONFIG_PM_RUNTIME */ 6225 #endif /* CONFIG_PM */ 6226 6227 static void e1000_shutdown(struct pci_dev *pdev) 6228 { 6229 bool wake = false; 6230 6231 __e1000_shutdown(pdev, &wake, false); 6232 6233 if (system_state == SYSTEM_POWER_OFF) 6234 e1000_complete_shutdown(pdev, false, wake); 6235 } 6236 6237 #ifdef CONFIG_NET_POLL_CONTROLLER 6238 6239 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6240 { 6241 struct net_device *netdev = data; 6242 struct e1000_adapter *adapter = netdev_priv(netdev); 6243 6244 if (adapter->msix_entries) { 6245 int vector, msix_irq; 6246 6247 vector = 0; 6248 msix_irq = adapter->msix_entries[vector].vector; 6249 disable_irq(msix_irq); 6250 e1000_intr_msix_rx(msix_irq, netdev); 6251 enable_irq(msix_irq); 6252 6253 vector++; 6254 msix_irq = adapter->msix_entries[vector].vector; 6255 disable_irq(msix_irq); 6256 e1000_intr_msix_tx(msix_irq, netdev); 6257 enable_irq(msix_irq); 6258 6259 vector++; 6260 msix_irq = adapter->msix_entries[vector].vector; 6261 disable_irq(msix_irq); 6262 e1000_msix_other(msix_irq, netdev); 6263 enable_irq(msix_irq); 6264 } 6265 6266 return IRQ_HANDLED; 6267 } 6268 6269 /** 6270 * e1000_netpoll 6271 * @netdev: network interface device structure 6272 * 6273 * Polling 'interrupt' - used by things like netconsole to send skbs 6274 * without having to re-enable interrupts. It's not called while 6275 * the interrupt routine is executing. 6276 */ 6277 static void e1000_netpoll(struct net_device *netdev) 6278 { 6279 struct e1000_adapter *adapter = netdev_priv(netdev); 6280 6281 switch (adapter->int_mode) { 6282 case E1000E_INT_MODE_MSIX: 6283 e1000_intr_msix(adapter->pdev->irq, netdev); 6284 break; 6285 case E1000E_INT_MODE_MSI: 6286 disable_irq(adapter->pdev->irq); 6287 e1000_intr_msi(adapter->pdev->irq, netdev); 6288 enable_irq(adapter->pdev->irq); 6289 break; 6290 default: /* E1000E_INT_MODE_LEGACY */ 6291 disable_irq(adapter->pdev->irq); 6292 e1000_intr(adapter->pdev->irq, netdev); 6293 enable_irq(adapter->pdev->irq); 6294 break; 6295 } 6296 } 6297 #endif 6298 6299 /** 6300 * e1000_io_error_detected - called when PCI error is detected 6301 * @pdev: Pointer to PCI device 6302 * @state: The current pci connection state 6303 * 6304 * This function is called after a PCI bus error affecting 6305 * this device has been detected. 6306 */ 6307 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6308 pci_channel_state_t state) 6309 { 6310 struct net_device *netdev = pci_get_drvdata(pdev); 6311 struct e1000_adapter *adapter = netdev_priv(netdev); 6312 6313 netif_device_detach(netdev); 6314 6315 if (state == pci_channel_io_perm_failure) 6316 return PCI_ERS_RESULT_DISCONNECT; 6317 6318 if (netif_running(netdev)) 6319 e1000e_down(adapter); 6320 pci_disable_device(pdev); 6321 6322 /* Request a slot slot reset. */ 6323 return PCI_ERS_RESULT_NEED_RESET; 6324 } 6325 6326 /** 6327 * e1000_io_slot_reset - called after the pci bus has been reset. 6328 * @pdev: Pointer to PCI device 6329 * 6330 * Restart the card from scratch, as if from a cold-boot. Implementation 6331 * resembles the first-half of the e1000_resume routine. 6332 */ 6333 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6334 { 6335 struct net_device *netdev = pci_get_drvdata(pdev); 6336 struct e1000_adapter *adapter = netdev_priv(netdev); 6337 struct e1000_hw *hw = &adapter->hw; 6338 u16 aspm_disable_flag = 0; 6339 int err; 6340 pci_ers_result_t result; 6341 6342 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6343 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6344 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6345 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6346 if (aspm_disable_flag) 6347 e1000e_disable_aspm(pdev, aspm_disable_flag); 6348 6349 err = pci_enable_device_mem(pdev); 6350 if (err) { 6351 dev_err(&pdev->dev, 6352 "Cannot re-enable PCI device after reset.\n"); 6353 result = PCI_ERS_RESULT_DISCONNECT; 6354 } else { 6355 pci_set_master(pdev); 6356 pdev->state_saved = true; 6357 pci_restore_state(pdev); 6358 6359 pci_enable_wake(pdev, PCI_D3hot, 0); 6360 pci_enable_wake(pdev, PCI_D3cold, 0); 6361 6362 e1000e_reset(adapter); 6363 ew32(WUS, ~0); 6364 result = PCI_ERS_RESULT_RECOVERED; 6365 } 6366 6367 pci_cleanup_aer_uncorrect_error_status(pdev); 6368 6369 return result; 6370 } 6371 6372 /** 6373 * e1000_io_resume - called when traffic can start flowing again. 6374 * @pdev: Pointer to PCI device 6375 * 6376 * This callback is called when the error recovery driver tells us that 6377 * its OK to resume normal operation. Implementation resembles the 6378 * second-half of the e1000_resume routine. 6379 */ 6380 static void e1000_io_resume(struct pci_dev *pdev) 6381 { 6382 struct net_device *netdev = pci_get_drvdata(pdev); 6383 struct e1000_adapter *adapter = netdev_priv(netdev); 6384 6385 e1000_init_manageability_pt(adapter); 6386 6387 if (netif_running(netdev)) { 6388 if (e1000e_up(adapter)) { 6389 dev_err(&pdev->dev, 6390 "can't bring device back up after reset\n"); 6391 return; 6392 } 6393 } 6394 6395 netif_device_attach(netdev); 6396 6397 /* If the controller has AMT, do not set DRV_LOAD until the interface 6398 * is up. For all other cases, let the f/w know that the h/w is now 6399 * under the control of the driver. 6400 */ 6401 if (!(adapter->flags & FLAG_HAS_AMT)) 6402 e1000e_get_hw_control(adapter); 6403 } 6404 6405 static void e1000_print_device_info(struct e1000_adapter *adapter) 6406 { 6407 struct e1000_hw *hw = &adapter->hw; 6408 struct net_device *netdev = adapter->netdev; 6409 u32 ret_val; 6410 u8 pba_str[E1000_PBANUM_LENGTH]; 6411 6412 /* print bus type/speed/width info */ 6413 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6414 /* bus width */ 6415 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6416 "Width x1"), 6417 /* MAC address */ 6418 netdev->dev_addr); 6419 e_info("Intel(R) PRO/%s Network Connection\n", 6420 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6421 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6422 E1000_PBANUM_LENGTH); 6423 if (ret_val) 6424 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6425 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6426 hw->mac.type, hw->phy.type, pba_str); 6427 } 6428 6429 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6430 { 6431 struct e1000_hw *hw = &adapter->hw; 6432 int ret_val; 6433 u16 buf = 0; 6434 6435 if (hw->mac.type != e1000_82573) 6436 return; 6437 6438 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6439 le16_to_cpus(&buf); 6440 if (!ret_val && (!(buf & (1 << 0)))) { 6441 /* Deep Smart Power Down (DSPD) */ 6442 dev_warn(&adapter->pdev->dev, 6443 "Warning: detected DSPD enabled in EEPROM\n"); 6444 } 6445 } 6446 6447 static int e1000_set_features(struct net_device *netdev, 6448 netdev_features_t features) 6449 { 6450 struct e1000_adapter *adapter = netdev_priv(netdev); 6451 netdev_features_t changed = features ^ netdev->features; 6452 6453 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6454 adapter->flags |= FLAG_TSO_FORCE; 6455 6456 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX | 6457 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6458 NETIF_F_RXALL))) 6459 return 0; 6460 6461 if (changed & NETIF_F_RXFCS) { 6462 if (features & NETIF_F_RXFCS) { 6463 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6464 } else { 6465 /* We need to take it back to defaults, which might mean 6466 * stripping is still disabled at the adapter level. 6467 */ 6468 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 6469 adapter->flags2 |= FLAG2_CRC_STRIPPING; 6470 else 6471 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6472 } 6473 } 6474 6475 netdev->features = features; 6476 6477 if (netif_running(netdev)) 6478 e1000e_reinit_locked(adapter); 6479 else 6480 e1000e_reset(adapter); 6481 6482 return 0; 6483 } 6484 6485 static const struct net_device_ops e1000e_netdev_ops = { 6486 .ndo_open = e1000_open, 6487 .ndo_stop = e1000_close, 6488 .ndo_start_xmit = e1000_xmit_frame, 6489 .ndo_get_stats64 = e1000e_get_stats64, 6490 .ndo_set_rx_mode = e1000e_set_rx_mode, 6491 .ndo_set_mac_address = e1000_set_mac, 6492 .ndo_change_mtu = e1000_change_mtu, 6493 .ndo_do_ioctl = e1000_ioctl, 6494 .ndo_tx_timeout = e1000_tx_timeout, 6495 .ndo_validate_addr = eth_validate_addr, 6496 6497 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 6498 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 6499 #ifdef CONFIG_NET_POLL_CONTROLLER 6500 .ndo_poll_controller = e1000_netpoll, 6501 #endif 6502 .ndo_set_features = e1000_set_features, 6503 }; 6504 6505 /** 6506 * e1000_probe - Device Initialization Routine 6507 * @pdev: PCI device information struct 6508 * @ent: entry in e1000_pci_tbl 6509 * 6510 * Returns 0 on success, negative on failure 6511 * 6512 * e1000_probe initializes an adapter identified by a pci_dev structure. 6513 * The OS initialization, configuring of the adapter private structure, 6514 * and a hardware reset occur. 6515 **/ 6516 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6517 { 6518 struct net_device *netdev; 6519 struct e1000_adapter *adapter; 6520 struct e1000_hw *hw; 6521 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 6522 resource_size_t mmio_start, mmio_len; 6523 resource_size_t flash_start, flash_len; 6524 static int cards_found; 6525 u16 aspm_disable_flag = 0; 6526 int i, err, pci_using_dac; 6527 u16 eeprom_data = 0; 6528 u16 eeprom_apme_mask = E1000_EEPROM_APME; 6529 6530 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 6531 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6532 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 6533 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6534 if (aspm_disable_flag) 6535 e1000e_disable_aspm(pdev, aspm_disable_flag); 6536 6537 err = pci_enable_device_mem(pdev); 6538 if (err) 6539 return err; 6540 6541 pci_using_dac = 0; 6542 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 6543 if (!err) { 6544 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 6545 if (!err) 6546 pci_using_dac = 1; 6547 } else { 6548 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 6549 if (err) { 6550 err = dma_set_coherent_mask(&pdev->dev, 6551 DMA_BIT_MASK(32)); 6552 if (err) { 6553 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 6554 goto err_dma; 6555 } 6556 } 6557 } 6558 6559 err = pci_request_selected_regions_exclusive(pdev, 6560 pci_select_bars(pdev, IORESOURCE_MEM), 6561 e1000e_driver_name); 6562 if (err) 6563 goto err_pci_reg; 6564 6565 /* AER (Advanced Error Reporting) hooks */ 6566 pci_enable_pcie_error_reporting(pdev); 6567 6568 pci_set_master(pdev); 6569 /* PCI config space info */ 6570 err = pci_save_state(pdev); 6571 if (err) 6572 goto err_alloc_etherdev; 6573 6574 err = -ENOMEM; 6575 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 6576 if (!netdev) 6577 goto err_alloc_etherdev; 6578 6579 SET_NETDEV_DEV(netdev, &pdev->dev); 6580 6581 netdev->irq = pdev->irq; 6582 6583 pci_set_drvdata(pdev, netdev); 6584 adapter = netdev_priv(netdev); 6585 hw = &adapter->hw; 6586 adapter->netdev = netdev; 6587 adapter->pdev = pdev; 6588 adapter->ei = ei; 6589 adapter->pba = ei->pba; 6590 adapter->flags = ei->flags; 6591 adapter->flags2 = ei->flags2; 6592 adapter->hw.adapter = adapter; 6593 adapter->hw.mac.type = ei->mac; 6594 adapter->max_hw_frame_size = ei->max_hw_frame_size; 6595 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6596 6597 mmio_start = pci_resource_start(pdev, 0); 6598 mmio_len = pci_resource_len(pdev, 0); 6599 6600 err = -EIO; 6601 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 6602 if (!adapter->hw.hw_addr) 6603 goto err_ioremap; 6604 6605 if ((adapter->flags & FLAG_HAS_FLASH) && 6606 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 6607 flash_start = pci_resource_start(pdev, 1); 6608 flash_len = pci_resource_len(pdev, 1); 6609 adapter->hw.flash_address = ioremap(flash_start, flash_len); 6610 if (!adapter->hw.flash_address) 6611 goto err_flashmap; 6612 } 6613 6614 /* construct the net_device struct */ 6615 netdev->netdev_ops = &e1000e_netdev_ops; 6616 e1000e_set_ethtool_ops(netdev); 6617 netdev->watchdog_timeo = 5 * HZ; 6618 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 6619 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 6620 6621 netdev->mem_start = mmio_start; 6622 netdev->mem_end = mmio_start + mmio_len; 6623 6624 adapter->bd_number = cards_found++; 6625 6626 e1000e_check_options(adapter); 6627 6628 /* setup adapter struct */ 6629 err = e1000_sw_init(adapter); 6630 if (err) 6631 goto err_sw_init; 6632 6633 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 6634 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 6635 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 6636 6637 err = ei->get_variants(adapter); 6638 if (err) 6639 goto err_hw_init; 6640 6641 if ((adapter->flags & FLAG_IS_ICH) && 6642 (adapter->flags & FLAG_READ_ONLY_NVM)) 6643 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 6644 6645 hw->mac.ops.get_bus_info(&adapter->hw); 6646 6647 adapter->hw.phy.autoneg_wait_to_complete = 0; 6648 6649 /* Copper options */ 6650 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 6651 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6652 adapter->hw.phy.disable_polarity_correction = 0; 6653 adapter->hw.phy.ms_type = e1000_ms_hw_default; 6654 } 6655 6656 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 6657 dev_info(&pdev->dev, 6658 "PHY reset is blocked due to SOL/IDER session.\n"); 6659 6660 /* Set initial default active device features */ 6661 netdev->features = (NETIF_F_SG | 6662 NETIF_F_HW_VLAN_RX | 6663 NETIF_F_HW_VLAN_TX | 6664 NETIF_F_TSO | 6665 NETIF_F_TSO6 | 6666 NETIF_F_RXHASH | 6667 NETIF_F_RXCSUM | 6668 NETIF_F_HW_CSUM); 6669 6670 /* Set user-changeable features (subset of all device features) */ 6671 netdev->hw_features = netdev->features; 6672 netdev->hw_features |= NETIF_F_RXFCS; 6673 netdev->priv_flags |= IFF_SUPP_NOFCS; 6674 netdev->hw_features |= NETIF_F_RXALL; 6675 6676 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 6677 netdev->features |= NETIF_F_HW_VLAN_FILTER; 6678 6679 netdev->vlan_features |= (NETIF_F_SG | 6680 NETIF_F_TSO | 6681 NETIF_F_TSO6 | 6682 NETIF_F_HW_CSUM); 6683 6684 netdev->priv_flags |= IFF_UNICAST_FLT; 6685 6686 if (pci_using_dac) { 6687 netdev->features |= NETIF_F_HIGHDMA; 6688 netdev->vlan_features |= NETIF_F_HIGHDMA; 6689 } 6690 6691 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 6692 adapter->flags |= FLAG_MNG_PT_ENABLED; 6693 6694 /* before reading the NVM, reset the controller to 6695 * put the device in a known good starting state 6696 */ 6697 adapter->hw.mac.ops.reset_hw(&adapter->hw); 6698 6699 /* systems with ASPM and others may see the checksum fail on the first 6700 * attempt. Let's give it a few tries 6701 */ 6702 for (i = 0;; i++) { 6703 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 6704 break; 6705 if (i == 2) { 6706 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 6707 err = -EIO; 6708 goto err_eeprom; 6709 } 6710 } 6711 6712 e1000_eeprom_checks(adapter); 6713 6714 /* copy the MAC address */ 6715 if (e1000e_read_mac_addr(&adapter->hw)) 6716 dev_err(&pdev->dev, 6717 "NVM Read Error while reading MAC address\n"); 6718 6719 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 6720 6721 if (!is_valid_ether_addr(netdev->dev_addr)) { 6722 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 6723 netdev->dev_addr); 6724 err = -EIO; 6725 goto err_eeprom; 6726 } 6727 6728 init_timer(&adapter->watchdog_timer); 6729 adapter->watchdog_timer.function = e1000_watchdog; 6730 adapter->watchdog_timer.data = (unsigned long) adapter; 6731 6732 init_timer(&adapter->phy_info_timer); 6733 adapter->phy_info_timer.function = e1000_update_phy_info; 6734 adapter->phy_info_timer.data = (unsigned long) adapter; 6735 6736 INIT_WORK(&adapter->reset_task, e1000_reset_task); 6737 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 6738 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 6739 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 6740 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 6741 6742 /* Initialize link parameters. User can change them with ethtool */ 6743 adapter->hw.mac.autoneg = 1; 6744 adapter->fc_autoneg = true; 6745 adapter->hw.fc.requested_mode = e1000_fc_default; 6746 adapter->hw.fc.current_mode = e1000_fc_default; 6747 adapter->hw.phy.autoneg_advertised = 0x2f; 6748 6749 /* ring size defaults */ 6750 adapter->rx_ring->count = E1000_DEFAULT_RXD; 6751 adapter->tx_ring->count = E1000_DEFAULT_TXD; 6752 6753 /* Initial Wake on LAN setting - If APM wake is enabled in 6754 * the EEPROM, enable the ACPI Magic Packet filter 6755 */ 6756 if (adapter->flags & FLAG_APME_IN_WUC) { 6757 /* APME bit in EEPROM is mapped to WUC.APME */ 6758 eeprom_data = er32(WUC); 6759 eeprom_apme_mask = E1000_WUC_APME; 6760 if ((hw->mac.type > e1000_ich10lan) && 6761 (eeprom_data & E1000_WUC_PHY_WAKE)) 6762 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 6763 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 6764 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 6765 (adapter->hw.bus.func == 1)) 6766 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B, 6767 1, &eeprom_data); 6768 else 6769 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A, 6770 1, &eeprom_data); 6771 } 6772 6773 /* fetch WoL from EEPROM */ 6774 if (eeprom_data & eeprom_apme_mask) 6775 adapter->eeprom_wol |= E1000_WUFC_MAG; 6776 6777 /* now that we have the eeprom settings, apply the special cases 6778 * where the eeprom may be wrong or the board simply won't support 6779 * wake on lan on a particular port 6780 */ 6781 if (!(adapter->flags & FLAG_HAS_WOL)) 6782 adapter->eeprom_wol = 0; 6783 6784 /* initialize the wol settings based on the eeprom settings */ 6785 adapter->wol = adapter->eeprom_wol; 6786 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 6787 6788 /* save off EEPROM version number */ 6789 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 6790 6791 /* reset the hardware with the new settings */ 6792 e1000e_reset(adapter); 6793 6794 /* If the controller has AMT, do not set DRV_LOAD until the interface 6795 * is up. For all other cases, let the f/w know that the h/w is now 6796 * under the control of the driver. 6797 */ 6798 if (!(adapter->flags & FLAG_HAS_AMT)) 6799 e1000e_get_hw_control(adapter); 6800 6801 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 6802 err = register_netdev(netdev); 6803 if (err) 6804 goto err_register; 6805 6806 /* carrier off reporting is important to ethtool even BEFORE open */ 6807 netif_carrier_off(netdev); 6808 6809 /* init PTP hardware clock */ 6810 e1000e_ptp_init(adapter); 6811 6812 e1000_print_device_info(adapter); 6813 6814 if (pci_dev_run_wake(pdev)) 6815 pm_runtime_put_noidle(&pdev->dev); 6816 6817 return 0; 6818 6819 err_register: 6820 if (!(adapter->flags & FLAG_HAS_AMT)) 6821 e1000e_release_hw_control(adapter); 6822 err_eeprom: 6823 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 6824 e1000_phy_hw_reset(&adapter->hw); 6825 err_hw_init: 6826 kfree(adapter->tx_ring); 6827 kfree(adapter->rx_ring); 6828 err_sw_init: 6829 if (adapter->hw.flash_address) 6830 iounmap(adapter->hw.flash_address); 6831 e1000e_reset_interrupt_capability(adapter); 6832 err_flashmap: 6833 iounmap(adapter->hw.hw_addr); 6834 err_ioremap: 6835 free_netdev(netdev); 6836 err_alloc_etherdev: 6837 pci_release_selected_regions(pdev, 6838 pci_select_bars(pdev, IORESOURCE_MEM)); 6839 err_pci_reg: 6840 err_dma: 6841 pci_disable_device(pdev); 6842 return err; 6843 } 6844 6845 /** 6846 * e1000_remove - Device Removal Routine 6847 * @pdev: PCI device information struct 6848 * 6849 * e1000_remove is called by the PCI subsystem to alert the driver 6850 * that it should release a PCI device. The could be caused by a 6851 * Hot-Plug event, or because the driver is going to be removed from 6852 * memory. 6853 **/ 6854 static void e1000_remove(struct pci_dev *pdev) 6855 { 6856 struct net_device *netdev = pci_get_drvdata(pdev); 6857 struct e1000_adapter *adapter = netdev_priv(netdev); 6858 bool down = test_bit(__E1000_DOWN, &adapter->state); 6859 6860 e1000e_ptp_remove(adapter); 6861 6862 /* The timers may be rescheduled, so explicitly disable them 6863 * from being rescheduled. 6864 */ 6865 if (!down) 6866 set_bit(__E1000_DOWN, &adapter->state); 6867 del_timer_sync(&adapter->watchdog_timer); 6868 del_timer_sync(&adapter->phy_info_timer); 6869 6870 cancel_work_sync(&adapter->reset_task); 6871 cancel_work_sync(&adapter->watchdog_task); 6872 cancel_work_sync(&adapter->downshift_task); 6873 cancel_work_sync(&adapter->update_phy_task); 6874 cancel_work_sync(&adapter->print_hang_task); 6875 6876 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 6877 cancel_work_sync(&adapter->tx_hwtstamp_work); 6878 if (adapter->tx_hwtstamp_skb) { 6879 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 6880 adapter->tx_hwtstamp_skb = NULL; 6881 } 6882 } 6883 6884 if (!(netdev->flags & IFF_UP)) 6885 e1000_power_down_phy(adapter); 6886 6887 /* Don't lie to e1000_close() down the road. */ 6888 if (!down) 6889 clear_bit(__E1000_DOWN, &adapter->state); 6890 unregister_netdev(netdev); 6891 6892 if (pci_dev_run_wake(pdev)) 6893 pm_runtime_get_noresume(&pdev->dev); 6894 6895 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6896 * would have already happened in close and is redundant. 6897 */ 6898 e1000e_release_hw_control(adapter); 6899 6900 e1000e_reset_interrupt_capability(adapter); 6901 kfree(adapter->tx_ring); 6902 kfree(adapter->rx_ring); 6903 6904 iounmap(adapter->hw.hw_addr); 6905 if (adapter->hw.flash_address) 6906 iounmap(adapter->hw.flash_address); 6907 pci_release_selected_regions(pdev, 6908 pci_select_bars(pdev, IORESOURCE_MEM)); 6909 6910 free_netdev(netdev); 6911 6912 /* AER disable */ 6913 pci_disable_pcie_error_reporting(pdev); 6914 6915 pci_disable_device(pdev); 6916 } 6917 6918 /* PCI Error Recovery (ERS) */ 6919 static const struct pci_error_handlers e1000_err_handler = { 6920 .error_detected = e1000_io_error_detected, 6921 .slot_reset = e1000_io_slot_reset, 6922 .resume = e1000_io_resume, 6923 }; 6924 6925 static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = { 6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 6927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 6928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 6929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 }, 6930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 6931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 6932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 6933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 6935 6936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 6937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 6940 6941 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 6943 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 6944 6945 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 6947 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 6948 6949 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 6950 board_80003es2lan }, 6951 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 6952 board_80003es2lan }, 6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 6954 board_80003es2lan }, 6955 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 6956 board_80003es2lan }, 6957 6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 6959 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 6964 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 6966 6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 6976 6977 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 6978 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 6979 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 6980 6981 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 6982 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 6984 6985 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 6987 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 6988 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 6989 6990 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 6991 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 6992 6993 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 6994 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 6995 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 6996 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 6997 6998 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 6999 }; 7000 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7001 7002 #ifdef CONFIG_PM 7003 static const struct dev_pm_ops e1000_pm_ops = { 7004 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume) 7005 SET_RUNTIME_PM_OPS(e1000_runtime_suspend, 7006 e1000_runtime_resume, e1000_idle) 7007 }; 7008 #endif 7009 7010 /* PCI Device API Driver */ 7011 static struct pci_driver e1000_driver = { 7012 .name = e1000e_driver_name, 7013 .id_table = e1000_pci_tbl, 7014 .probe = e1000_probe, 7015 .remove = e1000_remove, 7016 #ifdef CONFIG_PM 7017 .driver = { 7018 .pm = &e1000_pm_ops, 7019 }, 7020 #endif 7021 .shutdown = e1000_shutdown, 7022 .err_handler = &e1000_err_handler 7023 }; 7024 7025 /** 7026 * e1000_init_module - Driver Registration Routine 7027 * 7028 * e1000_init_module is the first routine called when the driver is 7029 * loaded. All it does is register with the PCI subsystem. 7030 **/ 7031 static int __init e1000_init_module(void) 7032 { 7033 int ret; 7034 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7035 e1000e_driver_version); 7036 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n"); 7037 ret = pci_register_driver(&e1000_driver); 7038 7039 return ret; 7040 } 7041 module_init(e1000_init_module); 7042 7043 /** 7044 * e1000_exit_module - Driver Exit Cleanup Routine 7045 * 7046 * e1000_exit_module is called just before the driver is removed 7047 * from memory. 7048 **/ 7049 static void __exit e1000_exit_module(void) 7050 { 7051 pci_unregister_driver(&e1000_driver); 7052 } 7053 module_exit(e1000_exit_module); 7054 7055 7056 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7057 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7058 MODULE_LICENSE("GPL"); 7059 MODULE_VERSION(DRV_VERSION); 7060 7061 /* netdev.c */ 7062