1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/module.h> 25 #include <linux/types.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/vmalloc.h> 29 #include <linux/pagemap.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/interrupt.h> 33 #include <linux/tcp.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/cpu.h> 41 #include <linux/smp.h> 42 #include <linux/pm_qos.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/aer.h> 45 #include <linux/prefetch.h> 46 47 #include "e1000.h" 48 49 #define DRV_EXTRAVERSION "-k" 50 51 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 52 char e1000e_driver_name[] = "e1000e"; 53 const char e1000e_driver_version[] = DRV_VERSION; 54 55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 56 static int debug = -1; 57 module_param(debug, int, 0); 58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 59 60 static const struct e1000_info *e1000_info_tbl[] = { 61 [board_82571] = &e1000_82571_info, 62 [board_82572] = &e1000_82572_info, 63 [board_82573] = &e1000_82573_info, 64 [board_82574] = &e1000_82574_info, 65 [board_82583] = &e1000_82583_info, 66 [board_80003es2lan] = &e1000_es2_info, 67 [board_ich8lan] = &e1000_ich8_info, 68 [board_ich9lan] = &e1000_ich9_info, 69 [board_ich10lan] = &e1000_ich10_info, 70 [board_pchlan] = &e1000_pch_info, 71 [board_pch2lan] = &e1000_pch2_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info, 73 [board_pch_spt] = &e1000_pch_spt_info, 74 [board_pch_cnp] = &e1000_pch_cnp_info, 75 }; 76 77 struct e1000_reg_info { 78 u32 ofs; 79 char *name; 80 }; 81 82 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 83 /* General Registers */ 84 {E1000_CTRL, "CTRL"}, 85 {E1000_STATUS, "STATUS"}, 86 {E1000_CTRL_EXT, "CTRL_EXT"}, 87 88 /* Interrupt Registers */ 89 {E1000_ICR, "ICR"}, 90 91 /* Rx Registers */ 92 {E1000_RCTL, "RCTL"}, 93 {E1000_RDLEN(0), "RDLEN"}, 94 {E1000_RDH(0), "RDH"}, 95 {E1000_RDT(0), "RDT"}, 96 {E1000_RDTR, "RDTR"}, 97 {E1000_RXDCTL(0), "RXDCTL"}, 98 {E1000_ERT, "ERT"}, 99 {E1000_RDBAL(0), "RDBAL"}, 100 {E1000_RDBAH(0), "RDBAH"}, 101 {E1000_RDFH, "RDFH"}, 102 {E1000_RDFT, "RDFT"}, 103 {E1000_RDFHS, "RDFHS"}, 104 {E1000_RDFTS, "RDFTS"}, 105 {E1000_RDFPC, "RDFPC"}, 106 107 /* Tx Registers */ 108 {E1000_TCTL, "TCTL"}, 109 {E1000_TDBAL(0), "TDBAL"}, 110 {E1000_TDBAH(0), "TDBAH"}, 111 {E1000_TDLEN(0), "TDLEN"}, 112 {E1000_TDH(0), "TDH"}, 113 {E1000_TDT(0), "TDT"}, 114 {E1000_TIDV, "TIDV"}, 115 {E1000_TXDCTL(0), "TXDCTL"}, 116 {E1000_TADV, "TADV"}, 117 {E1000_TARC(0), "TARC"}, 118 {E1000_TDFH, "TDFH"}, 119 {E1000_TDFT, "TDFT"}, 120 {E1000_TDFHS, "TDFHS"}, 121 {E1000_TDFTS, "TDFTS"}, 122 {E1000_TDFPC, "TDFPC"}, 123 124 /* List Terminator */ 125 {0, NULL} 126 }; 127 128 /** 129 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 130 * @hw: pointer to the HW structure 131 * 132 * When updating the MAC CSR registers, the Manageability Engine (ME) could 133 * be accessing the registers at the same time. Normally, this is handled in 134 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 135 * accesses later than it should which could result in the register to have 136 * an incorrect value. Workaround this by checking the FWSM register which 137 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 138 * and try again a number of times. 139 **/ 140 s32 __ew32_prepare(struct e1000_hw *hw) 141 { 142 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 143 144 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 145 udelay(50); 146 147 return i; 148 } 149 150 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 151 { 152 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 153 __ew32_prepare(hw); 154 155 writel(val, hw->hw_addr + reg); 156 } 157 158 /** 159 * e1000_regdump - register printout routine 160 * @hw: pointer to the HW structure 161 * @reginfo: pointer to the register info table 162 **/ 163 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 164 { 165 int n = 0; 166 char rname[16]; 167 u32 regs[8]; 168 169 switch (reginfo->ofs) { 170 case E1000_RXDCTL(0): 171 for (n = 0; n < 2; n++) 172 regs[n] = __er32(hw, E1000_RXDCTL(n)); 173 break; 174 case E1000_TXDCTL(0): 175 for (n = 0; n < 2; n++) 176 regs[n] = __er32(hw, E1000_TXDCTL(n)); 177 break; 178 case E1000_TARC(0): 179 for (n = 0; n < 2; n++) 180 regs[n] = __er32(hw, E1000_TARC(n)); 181 break; 182 default: 183 pr_info("%-15s %08x\n", 184 reginfo->name, __er32(hw, reginfo->ofs)); 185 return; 186 } 187 188 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 189 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 190 } 191 192 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 193 struct e1000_buffer *bi) 194 { 195 int i; 196 struct e1000_ps_page *ps_page; 197 198 for (i = 0; i < adapter->rx_ps_pages; i++) { 199 ps_page = &bi->ps_pages[i]; 200 201 if (ps_page->page) { 202 pr_info("packet dump for ps_page %d:\n", i); 203 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 204 16, 1, page_address(ps_page->page), 205 PAGE_SIZE, true); 206 } 207 } 208 } 209 210 /** 211 * e1000e_dump - Print registers, Tx-ring and Rx-ring 212 * @adapter: board private structure 213 **/ 214 static void e1000e_dump(struct e1000_adapter *adapter) 215 { 216 struct net_device *netdev = adapter->netdev; 217 struct e1000_hw *hw = &adapter->hw; 218 struct e1000_reg_info *reginfo; 219 struct e1000_ring *tx_ring = adapter->tx_ring; 220 struct e1000_tx_desc *tx_desc; 221 struct my_u0 { 222 __le64 a; 223 __le64 b; 224 } *u0; 225 struct e1000_buffer *buffer_info; 226 struct e1000_ring *rx_ring = adapter->rx_ring; 227 union e1000_rx_desc_packet_split *rx_desc_ps; 228 union e1000_rx_desc_extended *rx_desc; 229 struct my_u1 { 230 __le64 a; 231 __le64 b; 232 __le64 c; 233 __le64 d; 234 } *u1; 235 u32 staterr; 236 int i = 0; 237 238 if (!netif_msg_hw(adapter)) 239 return; 240 241 /* Print netdevice Info */ 242 if (netdev) { 243 dev_info(&adapter->pdev->dev, "Net device Info\n"); 244 pr_info("Device Name state trans_start\n"); 245 pr_info("%-15s %016lX %016lX\n", netdev->name, 246 netdev->state, dev_trans_start(netdev)); 247 } 248 249 /* Print Registers */ 250 dev_info(&adapter->pdev->dev, "Register Dump\n"); 251 pr_info(" Register Name Value\n"); 252 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 253 reginfo->name; reginfo++) { 254 e1000_regdump(hw, reginfo); 255 } 256 257 /* Print Tx Ring Summary */ 258 if (!netdev || !netif_running(netdev)) 259 return; 260 261 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 262 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 263 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 264 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 265 0, tx_ring->next_to_use, tx_ring->next_to_clean, 266 (unsigned long long)buffer_info->dma, 267 buffer_info->length, 268 buffer_info->next_to_watch, 269 (unsigned long long)buffer_info->time_stamp); 270 271 /* Print Tx Ring */ 272 if (!netif_msg_tx_done(adapter)) 273 goto rx_ring_summary; 274 275 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 276 277 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 278 * 279 * Legacy Transmit Descriptor 280 * +--------------------------------------------------------------+ 281 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 282 * +--------------------------------------------------------------+ 283 * 8 | Special | CSS | Status | CMD | CSO | Length | 284 * +--------------------------------------------------------------+ 285 * 63 48 47 36 35 32 31 24 23 16 15 0 286 * 287 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 288 * 63 48 47 40 39 32 31 16 15 8 7 0 289 * +----------------------------------------------------------------+ 290 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 291 * +----------------------------------------------------------------+ 292 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 293 * +----------------------------------------------------------------+ 294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 295 * 296 * Extended Data Descriptor (DTYP=0x1) 297 * +----------------------------------------------------------------+ 298 * 0 | Buffer Address [63:0] | 299 * +----------------------------------------------------------------+ 300 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 301 * +----------------------------------------------------------------+ 302 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 303 */ 304 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 305 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 306 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 307 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 308 const char *next_desc; 309 tx_desc = E1000_TX_DESC(*tx_ring, i); 310 buffer_info = &tx_ring->buffer_info[i]; 311 u0 = (struct my_u0 *)tx_desc; 312 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 313 next_desc = " NTC/U"; 314 else if (i == tx_ring->next_to_use) 315 next_desc = " NTU"; 316 else if (i == tx_ring->next_to_clean) 317 next_desc = " NTC"; 318 else 319 next_desc = ""; 320 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 321 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 322 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 323 i, 324 (unsigned long long)le64_to_cpu(u0->a), 325 (unsigned long long)le64_to_cpu(u0->b), 326 (unsigned long long)buffer_info->dma, 327 buffer_info->length, buffer_info->next_to_watch, 328 (unsigned long long)buffer_info->time_stamp, 329 buffer_info->skb, next_desc); 330 331 if (netif_msg_pktdata(adapter) && buffer_info->skb) 332 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 333 16, 1, buffer_info->skb->data, 334 buffer_info->skb->len, true); 335 } 336 337 /* Print Rx Ring Summary */ 338 rx_ring_summary: 339 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 340 pr_info("Queue [NTU] [NTC]\n"); 341 pr_info(" %5d %5X %5X\n", 342 0, rx_ring->next_to_use, rx_ring->next_to_clean); 343 344 /* Print Rx Ring */ 345 if (!netif_msg_rx_status(adapter)) 346 return; 347 348 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 349 switch (adapter->rx_ps_pages) { 350 case 1: 351 case 2: 352 case 3: 353 /* [Extended] Packet Split Receive Descriptor Format 354 * 355 * +-----------------------------------------------------+ 356 * 0 | Buffer Address 0 [63:0] | 357 * +-----------------------------------------------------+ 358 * 8 | Buffer Address 1 [63:0] | 359 * +-----------------------------------------------------+ 360 * 16 | Buffer Address 2 [63:0] | 361 * +-----------------------------------------------------+ 362 * 24 | Buffer Address 3 [63:0] | 363 * +-----------------------------------------------------+ 364 */ 365 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 366 /* [Extended] Receive Descriptor (Write-Back) Format 367 * 368 * 63 48 47 32 31 13 12 8 7 4 3 0 369 * +------------------------------------------------------+ 370 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 371 * | Checksum | Ident | | Queue | | Type | 372 * +------------------------------------------------------+ 373 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 374 * +------------------------------------------------------+ 375 * 63 48 47 32 31 20 19 0 376 */ 377 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 378 for (i = 0; i < rx_ring->count; i++) { 379 const char *next_desc; 380 buffer_info = &rx_ring->buffer_info[i]; 381 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 382 u1 = (struct my_u1 *)rx_desc_ps; 383 staterr = 384 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 385 386 if (i == rx_ring->next_to_use) 387 next_desc = " NTU"; 388 else if (i == rx_ring->next_to_clean) 389 next_desc = " NTC"; 390 else 391 next_desc = ""; 392 393 if (staterr & E1000_RXD_STAT_DD) { 394 /* Descriptor Done */ 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 396 "RWB", i, 397 (unsigned long long)le64_to_cpu(u1->a), 398 (unsigned long long)le64_to_cpu(u1->b), 399 (unsigned long long)le64_to_cpu(u1->c), 400 (unsigned long long)le64_to_cpu(u1->d), 401 buffer_info->skb, next_desc); 402 } else { 403 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 404 "R ", i, 405 (unsigned long long)le64_to_cpu(u1->a), 406 (unsigned long long)le64_to_cpu(u1->b), 407 (unsigned long long)le64_to_cpu(u1->c), 408 (unsigned long long)le64_to_cpu(u1->d), 409 (unsigned long long)buffer_info->dma, 410 buffer_info->skb, next_desc); 411 412 if (netif_msg_pktdata(adapter)) 413 e1000e_dump_ps_pages(adapter, 414 buffer_info); 415 } 416 } 417 break; 418 default: 419 case 0: 420 /* Extended Receive Descriptor (Read) Format 421 * 422 * +-----------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +-----------------------------------------------------+ 425 * 8 | Reserved | 426 * +-----------------------------------------------------+ 427 */ 428 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 429 /* Extended Receive Descriptor (Write-Back) Format 430 * 431 * 63 48 47 32 31 24 23 4 3 0 432 * +------------------------------------------------------+ 433 * | RSS Hash | | | | 434 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 435 * | Packet | IP | | | Type | 436 * | Checksum | Ident | | | | 437 * +------------------------------------------------------+ 438 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 439 * +------------------------------------------------------+ 440 * 63 48 47 32 31 20 19 0 441 */ 442 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 443 444 for (i = 0; i < rx_ring->count; i++) { 445 const char *next_desc; 446 447 buffer_info = &rx_ring->buffer_info[i]; 448 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 449 u1 = (struct my_u1 *)rx_desc; 450 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 451 452 if (i == rx_ring->next_to_use) 453 next_desc = " NTU"; 454 else if (i == rx_ring->next_to_clean) 455 next_desc = " NTC"; 456 else 457 next_desc = ""; 458 459 if (staterr & E1000_RXD_STAT_DD) { 460 /* Descriptor Done */ 461 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 462 "RWB", i, 463 (unsigned long long)le64_to_cpu(u1->a), 464 (unsigned long long)le64_to_cpu(u1->b), 465 buffer_info->skb, next_desc); 466 } else { 467 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 468 "R ", i, 469 (unsigned long long)le64_to_cpu(u1->a), 470 (unsigned long long)le64_to_cpu(u1->b), 471 (unsigned long long)buffer_info->dma, 472 buffer_info->skb, next_desc); 473 474 if (netif_msg_pktdata(adapter) && 475 buffer_info->skb) 476 print_hex_dump(KERN_INFO, "", 477 DUMP_PREFIX_ADDRESS, 16, 478 1, 479 buffer_info->skb->data, 480 adapter->rx_buffer_len, 481 true); 482 } 483 } 484 } 485 } 486 487 /** 488 * e1000_desc_unused - calculate if we have unused descriptors 489 **/ 490 static int e1000_desc_unused(struct e1000_ring *ring) 491 { 492 if (ring->next_to_clean > ring->next_to_use) 493 return ring->next_to_clean - ring->next_to_use - 1; 494 495 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 496 } 497 498 /** 499 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 500 * @adapter: board private structure 501 * @hwtstamps: time stamp structure to update 502 * @systim: unsigned 64bit system time value. 503 * 504 * Convert the system time value stored in the RX/TXSTMP registers into a 505 * hwtstamp which can be used by the upper level time stamping functions. 506 * 507 * The 'systim_lock' spinlock is used to protect the consistency of the 508 * system time value. This is needed because reading the 64 bit time 509 * value involves reading two 32 bit registers. The first read latches the 510 * value. 511 **/ 512 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 513 struct skb_shared_hwtstamps *hwtstamps, 514 u64 systim) 515 { 516 u64 ns; 517 unsigned long flags; 518 519 spin_lock_irqsave(&adapter->systim_lock, flags); 520 ns = timecounter_cyc2time(&adapter->tc, systim); 521 spin_unlock_irqrestore(&adapter->systim_lock, flags); 522 523 memset(hwtstamps, 0, sizeof(*hwtstamps)); 524 hwtstamps->hwtstamp = ns_to_ktime(ns); 525 } 526 527 /** 528 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 529 * @adapter: board private structure 530 * @status: descriptor extended error and status field 531 * @skb: particular skb to include time stamp 532 * 533 * If the time stamp is valid, convert it into the timecounter ns value 534 * and store that result into the shhwtstamps structure which is passed 535 * up the network stack. 536 **/ 537 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 538 struct sk_buff *skb) 539 { 540 struct e1000_hw *hw = &adapter->hw; 541 u64 rxstmp; 542 543 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 544 !(status & E1000_RXDEXT_STATERR_TST) || 545 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 546 return; 547 548 /* The Rx time stamp registers contain the time stamp. No other 549 * received packet will be time stamped until the Rx time stamp 550 * registers are read. Because only one packet can be time stamped 551 * at a time, the register values must belong to this packet and 552 * therefore none of the other additional attributes need to be 553 * compared. 554 */ 555 rxstmp = (u64)er32(RXSTMPL); 556 rxstmp |= (u64)er32(RXSTMPH) << 32; 557 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 558 559 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 560 } 561 562 /** 563 * e1000_receive_skb - helper function to handle Rx indications 564 * @adapter: board private structure 565 * @staterr: descriptor extended error and status field as written by hardware 566 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 567 * @skb: pointer to sk_buff to be indicated to stack 568 **/ 569 static void e1000_receive_skb(struct e1000_adapter *adapter, 570 struct net_device *netdev, struct sk_buff *skb, 571 u32 staterr, __le16 vlan) 572 { 573 u16 tag = le16_to_cpu(vlan); 574 575 e1000e_rx_hwtstamp(adapter, staterr, skb); 576 577 skb->protocol = eth_type_trans(skb, netdev); 578 579 if (staterr & E1000_RXD_STAT_VP) 580 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 581 582 napi_gro_receive(&adapter->napi, skb); 583 } 584 585 /** 586 * e1000_rx_checksum - Receive Checksum Offload 587 * @adapter: board private structure 588 * @status_err: receive descriptor status and error fields 589 * @csum: receive descriptor csum field 590 * @sk_buff: socket buffer with received data 591 **/ 592 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 593 struct sk_buff *skb) 594 { 595 u16 status = (u16)status_err; 596 u8 errors = (u8)(status_err >> 24); 597 598 skb_checksum_none_assert(skb); 599 600 /* Rx checksum disabled */ 601 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 602 return; 603 604 /* Ignore Checksum bit is set */ 605 if (status & E1000_RXD_STAT_IXSM) 606 return; 607 608 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 609 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 610 /* let the stack verify checksum errors */ 611 adapter->hw_csum_err++; 612 return; 613 } 614 615 /* TCP/UDP Checksum has not been calculated */ 616 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 617 return; 618 619 /* It must be a TCP or UDP packet with a valid checksum */ 620 skb->ip_summed = CHECKSUM_UNNECESSARY; 621 adapter->hw_csum_good++; 622 } 623 624 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 625 { 626 struct e1000_adapter *adapter = rx_ring->adapter; 627 struct e1000_hw *hw = &adapter->hw; 628 s32 ret_val = __ew32_prepare(hw); 629 630 writel(i, rx_ring->tail); 631 632 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 633 u32 rctl = er32(RCTL); 634 635 ew32(RCTL, rctl & ~E1000_RCTL_EN); 636 e_err("ME firmware caused invalid RDT - resetting\n"); 637 schedule_work(&adapter->reset_task); 638 } 639 } 640 641 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 642 { 643 struct e1000_adapter *adapter = tx_ring->adapter; 644 struct e1000_hw *hw = &adapter->hw; 645 s32 ret_val = __ew32_prepare(hw); 646 647 writel(i, tx_ring->tail); 648 649 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 650 u32 tctl = er32(TCTL); 651 652 ew32(TCTL, tctl & ~E1000_TCTL_EN); 653 e_err("ME firmware caused invalid TDT - resetting\n"); 654 schedule_work(&adapter->reset_task); 655 } 656 } 657 658 /** 659 * e1000_alloc_rx_buffers - Replace used receive buffers 660 * @rx_ring: Rx descriptor ring 661 **/ 662 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 663 int cleaned_count, gfp_t gfp) 664 { 665 struct e1000_adapter *adapter = rx_ring->adapter; 666 struct net_device *netdev = adapter->netdev; 667 struct pci_dev *pdev = adapter->pdev; 668 union e1000_rx_desc_extended *rx_desc; 669 struct e1000_buffer *buffer_info; 670 struct sk_buff *skb; 671 unsigned int i; 672 unsigned int bufsz = adapter->rx_buffer_len; 673 674 i = rx_ring->next_to_use; 675 buffer_info = &rx_ring->buffer_info[i]; 676 677 while (cleaned_count--) { 678 skb = buffer_info->skb; 679 if (skb) { 680 skb_trim(skb, 0); 681 goto map_skb; 682 } 683 684 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 685 if (!skb) { 686 /* Better luck next round */ 687 adapter->alloc_rx_buff_failed++; 688 break; 689 } 690 691 buffer_info->skb = skb; 692 map_skb: 693 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 694 adapter->rx_buffer_len, 695 DMA_FROM_DEVICE); 696 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 697 dev_err(&pdev->dev, "Rx DMA map failed\n"); 698 adapter->rx_dma_failed++; 699 break; 700 } 701 702 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 703 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 704 705 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 706 /* Force memory writes to complete before letting h/w 707 * know there are new descriptors to fetch. (Only 708 * applicable for weak-ordered memory model archs, 709 * such as IA-64). 710 */ 711 wmb(); 712 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 713 e1000e_update_rdt_wa(rx_ring, i); 714 else 715 writel(i, rx_ring->tail); 716 } 717 i++; 718 if (i == rx_ring->count) 719 i = 0; 720 buffer_info = &rx_ring->buffer_info[i]; 721 } 722 723 rx_ring->next_to_use = i; 724 } 725 726 /** 727 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 728 * @rx_ring: Rx descriptor ring 729 **/ 730 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 731 int cleaned_count, gfp_t gfp) 732 { 733 struct e1000_adapter *adapter = rx_ring->adapter; 734 struct net_device *netdev = adapter->netdev; 735 struct pci_dev *pdev = adapter->pdev; 736 union e1000_rx_desc_packet_split *rx_desc; 737 struct e1000_buffer *buffer_info; 738 struct e1000_ps_page *ps_page; 739 struct sk_buff *skb; 740 unsigned int i, j; 741 742 i = rx_ring->next_to_use; 743 buffer_info = &rx_ring->buffer_info[i]; 744 745 while (cleaned_count--) { 746 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 747 748 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 749 ps_page = &buffer_info->ps_pages[j]; 750 if (j >= adapter->rx_ps_pages) { 751 /* all unused desc entries get hw null ptr */ 752 rx_desc->read.buffer_addr[j + 1] = 753 ~cpu_to_le64(0); 754 continue; 755 } 756 if (!ps_page->page) { 757 ps_page->page = alloc_page(gfp); 758 if (!ps_page->page) { 759 adapter->alloc_rx_buff_failed++; 760 goto no_buffers; 761 } 762 ps_page->dma = dma_map_page(&pdev->dev, 763 ps_page->page, 764 0, PAGE_SIZE, 765 DMA_FROM_DEVICE); 766 if (dma_mapping_error(&pdev->dev, 767 ps_page->dma)) { 768 dev_err(&adapter->pdev->dev, 769 "Rx DMA page map failed\n"); 770 adapter->rx_dma_failed++; 771 goto no_buffers; 772 } 773 } 774 /* Refresh the desc even if buffer_addrs 775 * didn't change because each write-back 776 * erases this info. 777 */ 778 rx_desc->read.buffer_addr[j + 1] = 779 cpu_to_le64(ps_page->dma); 780 } 781 782 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 783 gfp); 784 785 if (!skb) { 786 adapter->alloc_rx_buff_failed++; 787 break; 788 } 789 790 buffer_info->skb = skb; 791 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 792 adapter->rx_ps_bsize0, 793 DMA_FROM_DEVICE); 794 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 795 dev_err(&pdev->dev, "Rx DMA map failed\n"); 796 adapter->rx_dma_failed++; 797 /* cleanup skb */ 798 dev_kfree_skb_any(skb); 799 buffer_info->skb = NULL; 800 break; 801 } 802 803 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 804 805 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 806 /* Force memory writes to complete before letting h/w 807 * know there are new descriptors to fetch. (Only 808 * applicable for weak-ordered memory model archs, 809 * such as IA-64). 810 */ 811 wmb(); 812 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 813 e1000e_update_rdt_wa(rx_ring, i << 1); 814 else 815 writel(i << 1, rx_ring->tail); 816 } 817 818 i++; 819 if (i == rx_ring->count) 820 i = 0; 821 buffer_info = &rx_ring->buffer_info[i]; 822 } 823 824 no_buffers: 825 rx_ring->next_to_use = i; 826 } 827 828 /** 829 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 830 * @rx_ring: Rx descriptor ring 831 * @cleaned_count: number of buffers to allocate this pass 832 **/ 833 834 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 835 int cleaned_count, gfp_t gfp) 836 { 837 struct e1000_adapter *adapter = rx_ring->adapter; 838 struct net_device *netdev = adapter->netdev; 839 struct pci_dev *pdev = adapter->pdev; 840 union e1000_rx_desc_extended *rx_desc; 841 struct e1000_buffer *buffer_info; 842 struct sk_buff *skb; 843 unsigned int i; 844 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 845 846 i = rx_ring->next_to_use; 847 buffer_info = &rx_ring->buffer_info[i]; 848 849 while (cleaned_count--) { 850 skb = buffer_info->skb; 851 if (skb) { 852 skb_trim(skb, 0); 853 goto check_page; 854 } 855 856 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 857 if (unlikely(!skb)) { 858 /* Better luck next round */ 859 adapter->alloc_rx_buff_failed++; 860 break; 861 } 862 863 buffer_info->skb = skb; 864 check_page: 865 /* allocate a new page if necessary */ 866 if (!buffer_info->page) { 867 buffer_info->page = alloc_page(gfp); 868 if (unlikely(!buffer_info->page)) { 869 adapter->alloc_rx_buff_failed++; 870 break; 871 } 872 } 873 874 if (!buffer_info->dma) { 875 buffer_info->dma = dma_map_page(&pdev->dev, 876 buffer_info->page, 0, 877 PAGE_SIZE, 878 DMA_FROM_DEVICE); 879 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 880 adapter->alloc_rx_buff_failed++; 881 break; 882 } 883 } 884 885 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 886 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 887 888 if (unlikely(++i == rx_ring->count)) 889 i = 0; 890 buffer_info = &rx_ring->buffer_info[i]; 891 } 892 893 if (likely(rx_ring->next_to_use != i)) { 894 rx_ring->next_to_use = i; 895 if (unlikely(i-- == 0)) 896 i = (rx_ring->count - 1); 897 898 /* Force memory writes to complete before letting h/w 899 * know there are new descriptors to fetch. (Only 900 * applicable for weak-ordered memory model archs, 901 * such as IA-64). 902 */ 903 wmb(); 904 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 905 e1000e_update_rdt_wa(rx_ring, i); 906 else 907 writel(i, rx_ring->tail); 908 } 909 } 910 911 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 912 struct sk_buff *skb) 913 { 914 if (netdev->features & NETIF_F_RXHASH) 915 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 916 } 917 918 /** 919 * e1000_clean_rx_irq - Send received data up the network stack 920 * @rx_ring: Rx descriptor ring 921 * 922 * the return value indicates whether actual cleaning was done, there 923 * is no guarantee that everything was cleaned 924 **/ 925 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 926 int work_to_do) 927 { 928 struct e1000_adapter *adapter = rx_ring->adapter; 929 struct net_device *netdev = adapter->netdev; 930 struct pci_dev *pdev = adapter->pdev; 931 struct e1000_hw *hw = &adapter->hw; 932 union e1000_rx_desc_extended *rx_desc, *next_rxd; 933 struct e1000_buffer *buffer_info, *next_buffer; 934 u32 length, staterr; 935 unsigned int i; 936 int cleaned_count = 0; 937 bool cleaned = false; 938 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 939 940 i = rx_ring->next_to_clean; 941 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 942 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 943 buffer_info = &rx_ring->buffer_info[i]; 944 945 while (staterr & E1000_RXD_STAT_DD) { 946 struct sk_buff *skb; 947 948 if (*work_done >= work_to_do) 949 break; 950 (*work_done)++; 951 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 952 953 skb = buffer_info->skb; 954 buffer_info->skb = NULL; 955 956 prefetch(skb->data - NET_IP_ALIGN); 957 958 i++; 959 if (i == rx_ring->count) 960 i = 0; 961 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 962 prefetch(next_rxd); 963 964 next_buffer = &rx_ring->buffer_info[i]; 965 966 cleaned = true; 967 cleaned_count++; 968 dma_unmap_single(&pdev->dev, buffer_info->dma, 969 adapter->rx_buffer_len, DMA_FROM_DEVICE); 970 buffer_info->dma = 0; 971 972 length = le16_to_cpu(rx_desc->wb.upper.length); 973 974 /* !EOP means multiple descriptors were used to store a single 975 * packet, if that's the case we need to toss it. In fact, we 976 * need to toss every packet with the EOP bit clear and the 977 * next frame that _does_ have the EOP bit set, as it is by 978 * definition only a frame fragment 979 */ 980 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 981 adapter->flags2 |= FLAG2_IS_DISCARDING; 982 983 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 984 /* All receives must fit into a single buffer */ 985 e_dbg("Receive packet consumed multiple buffers\n"); 986 /* recycle */ 987 buffer_info->skb = skb; 988 if (staterr & E1000_RXD_STAT_EOP) 989 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 990 goto next_desc; 991 } 992 993 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 994 !(netdev->features & NETIF_F_RXALL))) { 995 /* recycle */ 996 buffer_info->skb = skb; 997 goto next_desc; 998 } 999 1000 /* adjust length to remove Ethernet CRC */ 1001 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1002 /* If configured to store CRC, don't subtract FCS, 1003 * but keep the FCS bytes out of the total_rx_bytes 1004 * counter 1005 */ 1006 if (netdev->features & NETIF_F_RXFCS) 1007 total_rx_bytes -= 4; 1008 else 1009 length -= 4; 1010 } 1011 1012 total_rx_bytes += length; 1013 total_rx_packets++; 1014 1015 /* code added for copybreak, this should improve 1016 * performance for small packets with large amounts 1017 * of reassembly being done in the stack 1018 */ 1019 if (length < copybreak) { 1020 struct sk_buff *new_skb = 1021 napi_alloc_skb(&adapter->napi, length); 1022 if (new_skb) { 1023 skb_copy_to_linear_data_offset(new_skb, 1024 -NET_IP_ALIGN, 1025 (skb->data - 1026 NET_IP_ALIGN), 1027 (length + 1028 NET_IP_ALIGN)); 1029 /* save the skb in buffer_info as good */ 1030 buffer_info->skb = skb; 1031 skb = new_skb; 1032 } 1033 /* else just continue with the old one */ 1034 } 1035 /* end copybreak code */ 1036 skb_put(skb, length); 1037 1038 /* Receive Checksum Offload */ 1039 e1000_rx_checksum(adapter, staterr, skb); 1040 1041 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1042 1043 e1000_receive_skb(adapter, netdev, skb, staterr, 1044 rx_desc->wb.upper.vlan); 1045 1046 next_desc: 1047 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1048 1049 /* return some buffers to hardware, one at a time is too slow */ 1050 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1051 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1052 GFP_ATOMIC); 1053 cleaned_count = 0; 1054 } 1055 1056 /* use prefetched values */ 1057 rx_desc = next_rxd; 1058 buffer_info = next_buffer; 1059 1060 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1061 } 1062 rx_ring->next_to_clean = i; 1063 1064 cleaned_count = e1000_desc_unused(rx_ring); 1065 if (cleaned_count) 1066 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1067 1068 adapter->total_rx_bytes += total_rx_bytes; 1069 adapter->total_rx_packets += total_rx_packets; 1070 return cleaned; 1071 } 1072 1073 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1074 struct e1000_buffer *buffer_info, 1075 bool drop) 1076 { 1077 struct e1000_adapter *adapter = tx_ring->adapter; 1078 1079 if (buffer_info->dma) { 1080 if (buffer_info->mapped_as_page) 1081 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1082 buffer_info->length, DMA_TO_DEVICE); 1083 else 1084 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1085 buffer_info->length, DMA_TO_DEVICE); 1086 buffer_info->dma = 0; 1087 } 1088 if (buffer_info->skb) { 1089 if (drop) 1090 dev_kfree_skb_any(buffer_info->skb); 1091 else 1092 dev_consume_skb_any(buffer_info->skb); 1093 buffer_info->skb = NULL; 1094 } 1095 buffer_info->time_stamp = 0; 1096 } 1097 1098 static void e1000_print_hw_hang(struct work_struct *work) 1099 { 1100 struct e1000_adapter *adapter = container_of(work, 1101 struct e1000_adapter, 1102 print_hang_task); 1103 struct net_device *netdev = adapter->netdev; 1104 struct e1000_ring *tx_ring = adapter->tx_ring; 1105 unsigned int i = tx_ring->next_to_clean; 1106 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1107 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1108 struct e1000_hw *hw = &adapter->hw; 1109 u16 phy_status, phy_1000t_status, phy_ext_status; 1110 u16 pci_status; 1111 1112 if (test_bit(__E1000_DOWN, &adapter->state)) 1113 return; 1114 1115 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1116 /* May be block on write-back, flush and detect again 1117 * flush pending descriptor writebacks to memory 1118 */ 1119 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1120 /* execute the writes immediately */ 1121 e1e_flush(); 1122 /* Due to rare timing issues, write to TIDV again to ensure 1123 * the write is successful 1124 */ 1125 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1126 /* execute the writes immediately */ 1127 e1e_flush(); 1128 adapter->tx_hang_recheck = true; 1129 return; 1130 } 1131 adapter->tx_hang_recheck = false; 1132 1133 if (er32(TDH(0)) == er32(TDT(0))) { 1134 e_dbg("false hang detected, ignoring\n"); 1135 return; 1136 } 1137 1138 /* Real hang detected */ 1139 netif_stop_queue(netdev); 1140 1141 e1e_rphy(hw, MII_BMSR, &phy_status); 1142 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1143 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1144 1145 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1146 1147 /* detected Hardware unit hang */ 1148 e_err("Detected Hardware Unit Hang:\n" 1149 " TDH <%x>\n" 1150 " TDT <%x>\n" 1151 " next_to_use <%x>\n" 1152 " next_to_clean <%x>\n" 1153 "buffer_info[next_to_clean]:\n" 1154 " time_stamp <%lx>\n" 1155 " next_to_watch <%x>\n" 1156 " jiffies <%lx>\n" 1157 " next_to_watch.status <%x>\n" 1158 "MAC Status <%x>\n" 1159 "PHY Status <%x>\n" 1160 "PHY 1000BASE-T Status <%x>\n" 1161 "PHY Extended Status <%x>\n" 1162 "PCI Status <%x>\n", 1163 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1164 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1165 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1166 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1167 1168 e1000e_dump(adapter); 1169 1170 /* Suggest workaround for known h/w issue */ 1171 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1172 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1173 } 1174 1175 /** 1176 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1177 * @work: pointer to work struct 1178 * 1179 * This work function polls the TSYNCTXCTL valid bit to determine when a 1180 * timestamp has been taken for the current stored skb. The timestamp must 1181 * be for this skb because only one such packet is allowed in the queue. 1182 */ 1183 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1184 { 1185 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1186 tx_hwtstamp_work); 1187 struct e1000_hw *hw = &adapter->hw; 1188 1189 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1190 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1191 struct skb_shared_hwtstamps shhwtstamps; 1192 u64 txstmp; 1193 1194 txstmp = er32(TXSTMPL); 1195 txstmp |= (u64)er32(TXSTMPH) << 32; 1196 1197 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1198 1199 /* Clear the global tx_hwtstamp_skb pointer and force writes 1200 * prior to notifying the stack of a Tx timestamp. 1201 */ 1202 adapter->tx_hwtstamp_skb = NULL; 1203 wmb(); /* force write prior to skb_tstamp_tx */ 1204 1205 skb_tstamp_tx(skb, &shhwtstamps); 1206 dev_consume_skb_any(skb); 1207 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1208 + adapter->tx_timeout_factor * HZ)) { 1209 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1210 adapter->tx_hwtstamp_skb = NULL; 1211 adapter->tx_hwtstamp_timeouts++; 1212 e_warn("clearing Tx timestamp hang\n"); 1213 } else { 1214 /* reschedule to check later */ 1215 schedule_work(&adapter->tx_hwtstamp_work); 1216 } 1217 } 1218 1219 /** 1220 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1221 * @tx_ring: Tx descriptor ring 1222 * 1223 * the return value indicates whether actual cleaning was done, there 1224 * is no guarantee that everything was cleaned 1225 **/ 1226 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1227 { 1228 struct e1000_adapter *adapter = tx_ring->adapter; 1229 struct net_device *netdev = adapter->netdev; 1230 struct e1000_hw *hw = &adapter->hw; 1231 struct e1000_tx_desc *tx_desc, *eop_desc; 1232 struct e1000_buffer *buffer_info; 1233 unsigned int i, eop; 1234 unsigned int count = 0; 1235 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1236 unsigned int bytes_compl = 0, pkts_compl = 0; 1237 1238 i = tx_ring->next_to_clean; 1239 eop = tx_ring->buffer_info[i].next_to_watch; 1240 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1241 1242 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1243 (count < tx_ring->count)) { 1244 bool cleaned = false; 1245 1246 dma_rmb(); /* read buffer_info after eop_desc */ 1247 for (; !cleaned; count++) { 1248 tx_desc = E1000_TX_DESC(*tx_ring, i); 1249 buffer_info = &tx_ring->buffer_info[i]; 1250 cleaned = (i == eop); 1251 1252 if (cleaned) { 1253 total_tx_packets += buffer_info->segs; 1254 total_tx_bytes += buffer_info->bytecount; 1255 if (buffer_info->skb) { 1256 bytes_compl += buffer_info->skb->len; 1257 pkts_compl++; 1258 } 1259 } 1260 1261 e1000_put_txbuf(tx_ring, buffer_info, false); 1262 tx_desc->upper.data = 0; 1263 1264 i++; 1265 if (i == tx_ring->count) 1266 i = 0; 1267 } 1268 1269 if (i == tx_ring->next_to_use) 1270 break; 1271 eop = tx_ring->buffer_info[i].next_to_watch; 1272 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1273 } 1274 1275 tx_ring->next_to_clean = i; 1276 1277 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1278 1279 #define TX_WAKE_THRESHOLD 32 1280 if (count && netif_carrier_ok(netdev) && 1281 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1282 /* Make sure that anybody stopping the queue after this 1283 * sees the new next_to_clean. 1284 */ 1285 smp_mb(); 1286 1287 if (netif_queue_stopped(netdev) && 1288 !(test_bit(__E1000_DOWN, &adapter->state))) { 1289 netif_wake_queue(netdev); 1290 ++adapter->restart_queue; 1291 } 1292 } 1293 1294 if (adapter->detect_tx_hung) { 1295 /* Detect a transmit hang in hardware, this serializes the 1296 * check with the clearing of time_stamp and movement of i 1297 */ 1298 adapter->detect_tx_hung = false; 1299 if (tx_ring->buffer_info[i].time_stamp && 1300 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1301 + (adapter->tx_timeout_factor * HZ)) && 1302 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1303 schedule_work(&adapter->print_hang_task); 1304 else 1305 adapter->tx_hang_recheck = false; 1306 } 1307 adapter->total_tx_bytes += total_tx_bytes; 1308 adapter->total_tx_packets += total_tx_packets; 1309 return count < tx_ring->count; 1310 } 1311 1312 /** 1313 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1314 * @rx_ring: Rx descriptor ring 1315 * 1316 * the return value indicates whether actual cleaning was done, there 1317 * is no guarantee that everything was cleaned 1318 **/ 1319 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1320 int work_to_do) 1321 { 1322 struct e1000_adapter *adapter = rx_ring->adapter; 1323 struct e1000_hw *hw = &adapter->hw; 1324 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1325 struct net_device *netdev = adapter->netdev; 1326 struct pci_dev *pdev = adapter->pdev; 1327 struct e1000_buffer *buffer_info, *next_buffer; 1328 struct e1000_ps_page *ps_page; 1329 struct sk_buff *skb; 1330 unsigned int i, j; 1331 u32 length, staterr; 1332 int cleaned_count = 0; 1333 bool cleaned = false; 1334 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1335 1336 i = rx_ring->next_to_clean; 1337 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1338 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1339 buffer_info = &rx_ring->buffer_info[i]; 1340 1341 while (staterr & E1000_RXD_STAT_DD) { 1342 if (*work_done >= work_to_do) 1343 break; 1344 (*work_done)++; 1345 skb = buffer_info->skb; 1346 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1347 1348 /* in the packet split case this is header only */ 1349 prefetch(skb->data - NET_IP_ALIGN); 1350 1351 i++; 1352 if (i == rx_ring->count) 1353 i = 0; 1354 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1355 prefetch(next_rxd); 1356 1357 next_buffer = &rx_ring->buffer_info[i]; 1358 1359 cleaned = true; 1360 cleaned_count++; 1361 dma_unmap_single(&pdev->dev, buffer_info->dma, 1362 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1363 buffer_info->dma = 0; 1364 1365 /* see !EOP comment in other Rx routine */ 1366 if (!(staterr & E1000_RXD_STAT_EOP)) 1367 adapter->flags2 |= FLAG2_IS_DISCARDING; 1368 1369 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1370 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1371 dev_kfree_skb_irq(skb); 1372 if (staterr & E1000_RXD_STAT_EOP) 1373 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1374 goto next_desc; 1375 } 1376 1377 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1378 !(netdev->features & NETIF_F_RXALL))) { 1379 dev_kfree_skb_irq(skb); 1380 goto next_desc; 1381 } 1382 1383 length = le16_to_cpu(rx_desc->wb.middle.length0); 1384 1385 if (!length) { 1386 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1387 dev_kfree_skb_irq(skb); 1388 goto next_desc; 1389 } 1390 1391 /* Good Receive */ 1392 skb_put(skb, length); 1393 1394 { 1395 /* this looks ugly, but it seems compiler issues make 1396 * it more efficient than reusing j 1397 */ 1398 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1399 1400 /* page alloc/put takes too long and effects small 1401 * packet throughput, so unsplit small packets and 1402 * save the alloc/put only valid in softirq (napi) 1403 * context to call kmap_* 1404 */ 1405 if (l1 && (l1 <= copybreak) && 1406 ((length + l1) <= adapter->rx_ps_bsize0)) { 1407 u8 *vaddr; 1408 1409 ps_page = &buffer_info->ps_pages[0]; 1410 1411 /* there is no documentation about how to call 1412 * kmap_atomic, so we can't hold the mapping 1413 * very long 1414 */ 1415 dma_sync_single_for_cpu(&pdev->dev, 1416 ps_page->dma, 1417 PAGE_SIZE, 1418 DMA_FROM_DEVICE); 1419 vaddr = kmap_atomic(ps_page->page); 1420 memcpy(skb_tail_pointer(skb), vaddr, l1); 1421 kunmap_atomic(vaddr); 1422 dma_sync_single_for_device(&pdev->dev, 1423 ps_page->dma, 1424 PAGE_SIZE, 1425 DMA_FROM_DEVICE); 1426 1427 /* remove the CRC */ 1428 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1429 if (!(netdev->features & NETIF_F_RXFCS)) 1430 l1 -= 4; 1431 } 1432 1433 skb_put(skb, l1); 1434 goto copydone; 1435 } /* if */ 1436 } 1437 1438 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1439 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1440 if (!length) 1441 break; 1442 1443 ps_page = &buffer_info->ps_pages[j]; 1444 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1445 DMA_FROM_DEVICE); 1446 ps_page->dma = 0; 1447 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1448 ps_page->page = NULL; 1449 skb->len += length; 1450 skb->data_len += length; 1451 skb->truesize += PAGE_SIZE; 1452 } 1453 1454 /* strip the ethernet crc, problem is we're using pages now so 1455 * this whole operation can get a little cpu intensive 1456 */ 1457 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1458 if (!(netdev->features & NETIF_F_RXFCS)) 1459 pskb_trim(skb, skb->len - 4); 1460 } 1461 1462 copydone: 1463 total_rx_bytes += skb->len; 1464 total_rx_packets++; 1465 1466 e1000_rx_checksum(adapter, staterr, skb); 1467 1468 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1469 1470 if (rx_desc->wb.upper.header_status & 1471 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1472 adapter->rx_hdr_split++; 1473 1474 e1000_receive_skb(adapter, netdev, skb, staterr, 1475 rx_desc->wb.middle.vlan); 1476 1477 next_desc: 1478 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1479 buffer_info->skb = NULL; 1480 1481 /* return some buffers to hardware, one at a time is too slow */ 1482 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1483 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1484 GFP_ATOMIC); 1485 cleaned_count = 0; 1486 } 1487 1488 /* use prefetched values */ 1489 rx_desc = next_rxd; 1490 buffer_info = next_buffer; 1491 1492 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1493 } 1494 rx_ring->next_to_clean = i; 1495 1496 cleaned_count = e1000_desc_unused(rx_ring); 1497 if (cleaned_count) 1498 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1499 1500 adapter->total_rx_bytes += total_rx_bytes; 1501 adapter->total_rx_packets += total_rx_packets; 1502 return cleaned; 1503 } 1504 1505 /** 1506 * e1000_consume_page - helper function 1507 **/ 1508 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1509 u16 length) 1510 { 1511 bi->page = NULL; 1512 skb->len += length; 1513 skb->data_len += length; 1514 skb->truesize += PAGE_SIZE; 1515 } 1516 1517 /** 1518 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1519 * @adapter: board private structure 1520 * 1521 * the return value indicates whether actual cleaning was done, there 1522 * is no guarantee that everything was cleaned 1523 **/ 1524 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1525 int work_to_do) 1526 { 1527 struct e1000_adapter *adapter = rx_ring->adapter; 1528 struct net_device *netdev = adapter->netdev; 1529 struct pci_dev *pdev = adapter->pdev; 1530 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1531 struct e1000_buffer *buffer_info, *next_buffer; 1532 u32 length, staterr; 1533 unsigned int i; 1534 int cleaned_count = 0; 1535 bool cleaned = false; 1536 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1537 struct skb_shared_info *shinfo; 1538 1539 i = rx_ring->next_to_clean; 1540 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1541 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1542 buffer_info = &rx_ring->buffer_info[i]; 1543 1544 while (staterr & E1000_RXD_STAT_DD) { 1545 struct sk_buff *skb; 1546 1547 if (*work_done >= work_to_do) 1548 break; 1549 (*work_done)++; 1550 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1551 1552 skb = buffer_info->skb; 1553 buffer_info->skb = NULL; 1554 1555 ++i; 1556 if (i == rx_ring->count) 1557 i = 0; 1558 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1559 prefetch(next_rxd); 1560 1561 next_buffer = &rx_ring->buffer_info[i]; 1562 1563 cleaned = true; 1564 cleaned_count++; 1565 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1566 DMA_FROM_DEVICE); 1567 buffer_info->dma = 0; 1568 1569 length = le16_to_cpu(rx_desc->wb.upper.length); 1570 1571 /* errors is only valid for DD + EOP descriptors */ 1572 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1573 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1574 !(netdev->features & NETIF_F_RXALL)))) { 1575 /* recycle both page and skb */ 1576 buffer_info->skb = skb; 1577 /* an error means any chain goes out the window too */ 1578 if (rx_ring->rx_skb_top) 1579 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1580 rx_ring->rx_skb_top = NULL; 1581 goto next_desc; 1582 } 1583 #define rxtop (rx_ring->rx_skb_top) 1584 if (!(staterr & E1000_RXD_STAT_EOP)) { 1585 /* this descriptor is only the beginning (or middle) */ 1586 if (!rxtop) { 1587 /* this is the beginning of a chain */ 1588 rxtop = skb; 1589 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1590 0, length); 1591 } else { 1592 /* this is the middle of a chain */ 1593 shinfo = skb_shinfo(rxtop); 1594 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1595 buffer_info->page, 0, 1596 length); 1597 /* re-use the skb, only consumed the page */ 1598 buffer_info->skb = skb; 1599 } 1600 e1000_consume_page(buffer_info, rxtop, length); 1601 goto next_desc; 1602 } else { 1603 if (rxtop) { 1604 /* end of the chain */ 1605 shinfo = skb_shinfo(rxtop); 1606 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1607 buffer_info->page, 0, 1608 length); 1609 /* re-use the current skb, we only consumed the 1610 * page 1611 */ 1612 buffer_info->skb = skb; 1613 skb = rxtop; 1614 rxtop = NULL; 1615 e1000_consume_page(buffer_info, skb, length); 1616 } else { 1617 /* no chain, got EOP, this buf is the packet 1618 * copybreak to save the put_page/alloc_page 1619 */ 1620 if (length <= copybreak && 1621 skb_tailroom(skb) >= length) { 1622 u8 *vaddr; 1623 vaddr = kmap_atomic(buffer_info->page); 1624 memcpy(skb_tail_pointer(skb), vaddr, 1625 length); 1626 kunmap_atomic(vaddr); 1627 /* re-use the page, so don't erase 1628 * buffer_info->page 1629 */ 1630 skb_put(skb, length); 1631 } else { 1632 skb_fill_page_desc(skb, 0, 1633 buffer_info->page, 0, 1634 length); 1635 e1000_consume_page(buffer_info, skb, 1636 length); 1637 } 1638 } 1639 } 1640 1641 /* Receive Checksum Offload */ 1642 e1000_rx_checksum(adapter, staterr, skb); 1643 1644 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1645 1646 /* probably a little skewed due to removing CRC */ 1647 total_rx_bytes += skb->len; 1648 total_rx_packets++; 1649 1650 /* eth type trans needs skb->data to point to something */ 1651 if (!pskb_may_pull(skb, ETH_HLEN)) { 1652 e_err("pskb_may_pull failed.\n"); 1653 dev_kfree_skb_irq(skb); 1654 goto next_desc; 1655 } 1656 1657 e1000_receive_skb(adapter, netdev, skb, staterr, 1658 rx_desc->wb.upper.vlan); 1659 1660 next_desc: 1661 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1662 1663 /* return some buffers to hardware, one at a time is too slow */ 1664 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1665 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1666 GFP_ATOMIC); 1667 cleaned_count = 0; 1668 } 1669 1670 /* use prefetched values */ 1671 rx_desc = next_rxd; 1672 buffer_info = next_buffer; 1673 1674 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1675 } 1676 rx_ring->next_to_clean = i; 1677 1678 cleaned_count = e1000_desc_unused(rx_ring); 1679 if (cleaned_count) 1680 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1681 1682 adapter->total_rx_bytes += total_rx_bytes; 1683 adapter->total_rx_packets += total_rx_packets; 1684 return cleaned; 1685 } 1686 1687 /** 1688 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1689 * @rx_ring: Rx descriptor ring 1690 **/ 1691 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1692 { 1693 struct e1000_adapter *adapter = rx_ring->adapter; 1694 struct e1000_buffer *buffer_info; 1695 struct e1000_ps_page *ps_page; 1696 struct pci_dev *pdev = adapter->pdev; 1697 unsigned int i, j; 1698 1699 /* Free all the Rx ring sk_buffs */ 1700 for (i = 0; i < rx_ring->count; i++) { 1701 buffer_info = &rx_ring->buffer_info[i]; 1702 if (buffer_info->dma) { 1703 if (adapter->clean_rx == e1000_clean_rx_irq) 1704 dma_unmap_single(&pdev->dev, buffer_info->dma, 1705 adapter->rx_buffer_len, 1706 DMA_FROM_DEVICE); 1707 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1708 dma_unmap_page(&pdev->dev, buffer_info->dma, 1709 PAGE_SIZE, DMA_FROM_DEVICE); 1710 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1711 dma_unmap_single(&pdev->dev, buffer_info->dma, 1712 adapter->rx_ps_bsize0, 1713 DMA_FROM_DEVICE); 1714 buffer_info->dma = 0; 1715 } 1716 1717 if (buffer_info->page) { 1718 put_page(buffer_info->page); 1719 buffer_info->page = NULL; 1720 } 1721 1722 if (buffer_info->skb) { 1723 dev_kfree_skb(buffer_info->skb); 1724 buffer_info->skb = NULL; 1725 } 1726 1727 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1728 ps_page = &buffer_info->ps_pages[j]; 1729 if (!ps_page->page) 1730 break; 1731 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1732 DMA_FROM_DEVICE); 1733 ps_page->dma = 0; 1734 put_page(ps_page->page); 1735 ps_page->page = NULL; 1736 } 1737 } 1738 1739 /* there also may be some cached data from a chained receive */ 1740 if (rx_ring->rx_skb_top) { 1741 dev_kfree_skb(rx_ring->rx_skb_top); 1742 rx_ring->rx_skb_top = NULL; 1743 } 1744 1745 /* Zero out the descriptor ring */ 1746 memset(rx_ring->desc, 0, rx_ring->size); 1747 1748 rx_ring->next_to_clean = 0; 1749 rx_ring->next_to_use = 0; 1750 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1751 } 1752 1753 static void e1000e_downshift_workaround(struct work_struct *work) 1754 { 1755 struct e1000_adapter *adapter = container_of(work, 1756 struct e1000_adapter, 1757 downshift_task); 1758 1759 if (test_bit(__E1000_DOWN, &adapter->state)) 1760 return; 1761 1762 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1763 } 1764 1765 /** 1766 * e1000_intr_msi - Interrupt Handler 1767 * @irq: interrupt number 1768 * @data: pointer to a network interface device structure 1769 **/ 1770 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1771 { 1772 struct net_device *netdev = data; 1773 struct e1000_adapter *adapter = netdev_priv(netdev); 1774 struct e1000_hw *hw = &adapter->hw; 1775 u32 icr = er32(ICR); 1776 1777 /* read ICR disables interrupts using IAM */ 1778 if (icr & E1000_ICR_LSC) { 1779 hw->mac.get_link_status = true; 1780 /* ICH8 workaround-- Call gig speed drop workaround on cable 1781 * disconnect (LSC) before accessing any PHY registers 1782 */ 1783 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1784 (!(er32(STATUS) & E1000_STATUS_LU))) 1785 schedule_work(&adapter->downshift_task); 1786 1787 /* 80003ES2LAN workaround-- For packet buffer work-around on 1788 * link down event; disable receives here in the ISR and reset 1789 * adapter in watchdog 1790 */ 1791 if (netif_carrier_ok(netdev) && 1792 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1793 /* disable receives */ 1794 u32 rctl = er32(RCTL); 1795 1796 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1797 adapter->flags |= FLAG_RESTART_NOW; 1798 } 1799 /* guard against interrupt when we're going down */ 1800 if (!test_bit(__E1000_DOWN, &adapter->state)) 1801 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1802 } 1803 1804 /* Reset on uncorrectable ECC error */ 1805 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1806 u32 pbeccsts = er32(PBECCSTS); 1807 1808 adapter->corr_errors += 1809 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1810 adapter->uncorr_errors += 1811 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1812 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1813 1814 /* Do the reset outside of interrupt context */ 1815 schedule_work(&adapter->reset_task); 1816 1817 /* return immediately since reset is imminent */ 1818 return IRQ_HANDLED; 1819 } 1820 1821 if (napi_schedule_prep(&adapter->napi)) { 1822 adapter->total_tx_bytes = 0; 1823 adapter->total_tx_packets = 0; 1824 adapter->total_rx_bytes = 0; 1825 adapter->total_rx_packets = 0; 1826 __napi_schedule(&adapter->napi); 1827 } 1828 1829 return IRQ_HANDLED; 1830 } 1831 1832 /** 1833 * e1000_intr - Interrupt Handler 1834 * @irq: interrupt number 1835 * @data: pointer to a network interface device structure 1836 **/ 1837 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1838 { 1839 struct net_device *netdev = data; 1840 struct e1000_adapter *adapter = netdev_priv(netdev); 1841 struct e1000_hw *hw = &adapter->hw; 1842 u32 rctl, icr = er32(ICR); 1843 1844 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1845 return IRQ_NONE; /* Not our interrupt */ 1846 1847 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1848 * not set, then the adapter didn't send an interrupt 1849 */ 1850 if (!(icr & E1000_ICR_INT_ASSERTED)) 1851 return IRQ_NONE; 1852 1853 /* Interrupt Auto-Mask...upon reading ICR, 1854 * interrupts are masked. No need for the 1855 * IMC write 1856 */ 1857 1858 if (icr & E1000_ICR_LSC) { 1859 hw->mac.get_link_status = true; 1860 /* ICH8 workaround-- Call gig speed drop workaround on cable 1861 * disconnect (LSC) before accessing any PHY registers 1862 */ 1863 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1864 (!(er32(STATUS) & E1000_STATUS_LU))) 1865 schedule_work(&adapter->downshift_task); 1866 1867 /* 80003ES2LAN workaround-- 1868 * For packet buffer work-around on link down event; 1869 * disable receives here in the ISR and 1870 * reset adapter in watchdog 1871 */ 1872 if (netif_carrier_ok(netdev) && 1873 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1874 /* disable receives */ 1875 rctl = er32(RCTL); 1876 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1877 adapter->flags |= FLAG_RESTART_NOW; 1878 } 1879 /* guard against interrupt when we're going down */ 1880 if (!test_bit(__E1000_DOWN, &adapter->state)) 1881 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1882 } 1883 1884 /* Reset on uncorrectable ECC error */ 1885 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1886 u32 pbeccsts = er32(PBECCSTS); 1887 1888 adapter->corr_errors += 1889 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1890 adapter->uncorr_errors += 1891 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1892 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1893 1894 /* Do the reset outside of interrupt context */ 1895 schedule_work(&adapter->reset_task); 1896 1897 /* return immediately since reset is imminent */ 1898 return IRQ_HANDLED; 1899 } 1900 1901 if (napi_schedule_prep(&adapter->napi)) { 1902 adapter->total_tx_bytes = 0; 1903 adapter->total_tx_packets = 0; 1904 adapter->total_rx_bytes = 0; 1905 adapter->total_rx_packets = 0; 1906 __napi_schedule(&adapter->napi); 1907 } 1908 1909 return IRQ_HANDLED; 1910 } 1911 1912 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1913 { 1914 struct net_device *netdev = data; 1915 struct e1000_adapter *adapter = netdev_priv(netdev); 1916 struct e1000_hw *hw = &adapter->hw; 1917 u32 icr; 1918 bool enable = true; 1919 1920 icr = er32(ICR); 1921 if (icr & E1000_ICR_RXO) { 1922 ew32(ICR, E1000_ICR_RXO); 1923 enable = false; 1924 /* napi poll will re-enable Other, make sure it runs */ 1925 if (napi_schedule_prep(&adapter->napi)) { 1926 adapter->total_rx_bytes = 0; 1927 adapter->total_rx_packets = 0; 1928 __napi_schedule(&adapter->napi); 1929 } 1930 } 1931 if (icr & E1000_ICR_LSC) { 1932 ew32(ICR, E1000_ICR_LSC); 1933 hw->mac.get_link_status = true; 1934 /* guard against interrupt when we're going down */ 1935 if (!test_bit(__E1000_DOWN, &adapter->state)) 1936 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1937 } 1938 1939 if (enable && !test_bit(__E1000_DOWN, &adapter->state)) 1940 ew32(IMS, E1000_IMS_OTHER); 1941 1942 return IRQ_HANDLED; 1943 } 1944 1945 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1946 { 1947 struct net_device *netdev = data; 1948 struct e1000_adapter *adapter = netdev_priv(netdev); 1949 struct e1000_hw *hw = &adapter->hw; 1950 struct e1000_ring *tx_ring = adapter->tx_ring; 1951 1952 adapter->total_tx_bytes = 0; 1953 adapter->total_tx_packets = 0; 1954 1955 if (!e1000_clean_tx_irq(tx_ring)) 1956 /* Ring was not completely cleaned, so fire another interrupt */ 1957 ew32(ICS, tx_ring->ims_val); 1958 1959 if (!test_bit(__E1000_DOWN, &adapter->state)) 1960 ew32(IMS, adapter->tx_ring->ims_val); 1961 1962 return IRQ_HANDLED; 1963 } 1964 1965 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1966 { 1967 struct net_device *netdev = data; 1968 struct e1000_adapter *adapter = netdev_priv(netdev); 1969 struct e1000_ring *rx_ring = adapter->rx_ring; 1970 1971 /* Write the ITR value calculated at the end of the 1972 * previous interrupt. 1973 */ 1974 if (rx_ring->set_itr) { 1975 u32 itr = rx_ring->itr_val ? 1976 1000000000 / (rx_ring->itr_val * 256) : 0; 1977 1978 writel(itr, rx_ring->itr_register); 1979 rx_ring->set_itr = 0; 1980 } 1981 1982 if (napi_schedule_prep(&adapter->napi)) { 1983 adapter->total_rx_bytes = 0; 1984 adapter->total_rx_packets = 0; 1985 __napi_schedule(&adapter->napi); 1986 } 1987 return IRQ_HANDLED; 1988 } 1989 1990 /** 1991 * e1000_configure_msix - Configure MSI-X hardware 1992 * 1993 * e1000_configure_msix sets up the hardware to properly 1994 * generate MSI-X interrupts. 1995 **/ 1996 static void e1000_configure_msix(struct e1000_adapter *adapter) 1997 { 1998 struct e1000_hw *hw = &adapter->hw; 1999 struct e1000_ring *rx_ring = adapter->rx_ring; 2000 struct e1000_ring *tx_ring = adapter->tx_ring; 2001 int vector = 0; 2002 u32 ctrl_ext, ivar = 0; 2003 2004 adapter->eiac_mask = 0; 2005 2006 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 2007 if (hw->mac.type == e1000_82574) { 2008 u32 rfctl = er32(RFCTL); 2009 2010 rfctl |= E1000_RFCTL_ACK_DIS; 2011 ew32(RFCTL, rfctl); 2012 } 2013 2014 /* Configure Rx vector */ 2015 rx_ring->ims_val = E1000_IMS_RXQ0; 2016 adapter->eiac_mask |= rx_ring->ims_val; 2017 if (rx_ring->itr_val) 2018 writel(1000000000 / (rx_ring->itr_val * 256), 2019 rx_ring->itr_register); 2020 else 2021 writel(1, rx_ring->itr_register); 2022 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2023 2024 /* Configure Tx vector */ 2025 tx_ring->ims_val = E1000_IMS_TXQ0; 2026 vector++; 2027 if (tx_ring->itr_val) 2028 writel(1000000000 / (tx_ring->itr_val * 256), 2029 tx_ring->itr_register); 2030 else 2031 writel(1, tx_ring->itr_register); 2032 adapter->eiac_mask |= tx_ring->ims_val; 2033 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2034 2035 /* set vector for Other Causes, e.g. link changes */ 2036 vector++; 2037 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2038 if (rx_ring->itr_val) 2039 writel(1000000000 / (rx_ring->itr_val * 256), 2040 hw->hw_addr + E1000_EITR_82574(vector)); 2041 else 2042 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2043 adapter->eiac_mask |= E1000_IMS_OTHER; 2044 2045 /* Cause Tx interrupts on every write back */ 2046 ivar |= BIT(31); 2047 2048 ew32(IVAR, ivar); 2049 2050 /* enable MSI-X PBA support */ 2051 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2052 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2053 ew32(CTRL_EXT, ctrl_ext); 2054 e1e_flush(); 2055 } 2056 2057 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2058 { 2059 if (adapter->msix_entries) { 2060 pci_disable_msix(adapter->pdev); 2061 kfree(adapter->msix_entries); 2062 adapter->msix_entries = NULL; 2063 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2064 pci_disable_msi(adapter->pdev); 2065 adapter->flags &= ~FLAG_MSI_ENABLED; 2066 } 2067 } 2068 2069 /** 2070 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2071 * 2072 * Attempt to configure interrupts using the best available 2073 * capabilities of the hardware and kernel. 2074 **/ 2075 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2076 { 2077 int err; 2078 int i; 2079 2080 switch (adapter->int_mode) { 2081 case E1000E_INT_MODE_MSIX: 2082 if (adapter->flags & FLAG_HAS_MSIX) { 2083 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2084 adapter->msix_entries = kcalloc(adapter->num_vectors, 2085 sizeof(struct 2086 msix_entry), 2087 GFP_KERNEL); 2088 if (adapter->msix_entries) { 2089 struct e1000_adapter *a = adapter; 2090 2091 for (i = 0; i < adapter->num_vectors; i++) 2092 adapter->msix_entries[i].entry = i; 2093 2094 err = pci_enable_msix_range(a->pdev, 2095 a->msix_entries, 2096 a->num_vectors, 2097 a->num_vectors); 2098 if (err > 0) 2099 return; 2100 } 2101 /* MSI-X failed, so fall through and try MSI */ 2102 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2103 e1000e_reset_interrupt_capability(adapter); 2104 } 2105 adapter->int_mode = E1000E_INT_MODE_MSI; 2106 /* Fall through */ 2107 case E1000E_INT_MODE_MSI: 2108 if (!pci_enable_msi(adapter->pdev)) { 2109 adapter->flags |= FLAG_MSI_ENABLED; 2110 } else { 2111 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2112 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2113 } 2114 /* Fall through */ 2115 case E1000E_INT_MODE_LEGACY: 2116 /* Don't do anything; this is the system default */ 2117 break; 2118 } 2119 2120 /* store the number of vectors being used */ 2121 adapter->num_vectors = 1; 2122 } 2123 2124 /** 2125 * e1000_request_msix - Initialize MSI-X interrupts 2126 * 2127 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2128 * kernel. 2129 **/ 2130 static int e1000_request_msix(struct e1000_adapter *adapter) 2131 { 2132 struct net_device *netdev = adapter->netdev; 2133 int err = 0, vector = 0; 2134 2135 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2136 snprintf(adapter->rx_ring->name, 2137 sizeof(adapter->rx_ring->name) - 1, 2138 "%s-rx-0", netdev->name); 2139 else 2140 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2141 err = request_irq(adapter->msix_entries[vector].vector, 2142 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2143 netdev); 2144 if (err) 2145 return err; 2146 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2147 E1000_EITR_82574(vector); 2148 adapter->rx_ring->itr_val = adapter->itr; 2149 vector++; 2150 2151 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2152 snprintf(adapter->tx_ring->name, 2153 sizeof(adapter->tx_ring->name) - 1, 2154 "%s-tx-0", netdev->name); 2155 else 2156 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2157 err = request_irq(adapter->msix_entries[vector].vector, 2158 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2159 netdev); 2160 if (err) 2161 return err; 2162 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2163 E1000_EITR_82574(vector); 2164 adapter->tx_ring->itr_val = adapter->itr; 2165 vector++; 2166 2167 err = request_irq(adapter->msix_entries[vector].vector, 2168 e1000_msix_other, 0, netdev->name, netdev); 2169 if (err) 2170 return err; 2171 2172 e1000_configure_msix(adapter); 2173 2174 return 0; 2175 } 2176 2177 /** 2178 * e1000_request_irq - initialize interrupts 2179 * 2180 * Attempts to configure interrupts using the best available 2181 * capabilities of the hardware and kernel. 2182 **/ 2183 static int e1000_request_irq(struct e1000_adapter *adapter) 2184 { 2185 struct net_device *netdev = adapter->netdev; 2186 int err; 2187 2188 if (adapter->msix_entries) { 2189 err = e1000_request_msix(adapter); 2190 if (!err) 2191 return err; 2192 /* fall back to MSI */ 2193 e1000e_reset_interrupt_capability(adapter); 2194 adapter->int_mode = E1000E_INT_MODE_MSI; 2195 e1000e_set_interrupt_capability(adapter); 2196 } 2197 if (adapter->flags & FLAG_MSI_ENABLED) { 2198 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2199 netdev->name, netdev); 2200 if (!err) 2201 return err; 2202 2203 /* fall back to legacy interrupt */ 2204 e1000e_reset_interrupt_capability(adapter); 2205 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2206 } 2207 2208 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2209 netdev->name, netdev); 2210 if (err) 2211 e_err("Unable to allocate interrupt, Error: %d\n", err); 2212 2213 return err; 2214 } 2215 2216 static void e1000_free_irq(struct e1000_adapter *adapter) 2217 { 2218 struct net_device *netdev = adapter->netdev; 2219 2220 if (adapter->msix_entries) { 2221 int vector = 0; 2222 2223 free_irq(adapter->msix_entries[vector].vector, netdev); 2224 vector++; 2225 2226 free_irq(adapter->msix_entries[vector].vector, netdev); 2227 vector++; 2228 2229 /* Other Causes interrupt vector */ 2230 free_irq(adapter->msix_entries[vector].vector, netdev); 2231 return; 2232 } 2233 2234 free_irq(adapter->pdev->irq, netdev); 2235 } 2236 2237 /** 2238 * e1000_irq_disable - Mask off interrupt generation on the NIC 2239 **/ 2240 static void e1000_irq_disable(struct e1000_adapter *adapter) 2241 { 2242 struct e1000_hw *hw = &adapter->hw; 2243 2244 ew32(IMC, ~0); 2245 if (adapter->msix_entries) 2246 ew32(EIAC_82574, 0); 2247 e1e_flush(); 2248 2249 if (adapter->msix_entries) { 2250 int i; 2251 2252 for (i = 0; i < adapter->num_vectors; i++) 2253 synchronize_irq(adapter->msix_entries[i].vector); 2254 } else { 2255 synchronize_irq(adapter->pdev->irq); 2256 } 2257 } 2258 2259 /** 2260 * e1000_irq_enable - Enable default interrupt generation settings 2261 **/ 2262 static void e1000_irq_enable(struct e1000_adapter *adapter) 2263 { 2264 struct e1000_hw *hw = &adapter->hw; 2265 2266 if (adapter->msix_entries) { 2267 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2268 ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC); 2269 } else if (hw->mac.type >= e1000_pch_lpt) { 2270 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2271 } else { 2272 ew32(IMS, IMS_ENABLE_MASK); 2273 } 2274 e1e_flush(); 2275 } 2276 2277 /** 2278 * e1000e_get_hw_control - get control of the h/w from f/w 2279 * @adapter: address of board private structure 2280 * 2281 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2282 * For ASF and Pass Through versions of f/w this means that 2283 * the driver is loaded. For AMT version (only with 82573) 2284 * of the f/w this means that the network i/f is open. 2285 **/ 2286 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2287 { 2288 struct e1000_hw *hw = &adapter->hw; 2289 u32 ctrl_ext; 2290 u32 swsm; 2291 2292 /* Let firmware know the driver has taken over */ 2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2294 swsm = er32(SWSM); 2295 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2297 ctrl_ext = er32(CTRL_EXT); 2298 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2299 } 2300 } 2301 2302 /** 2303 * e1000e_release_hw_control - release control of the h/w to f/w 2304 * @adapter: address of board private structure 2305 * 2306 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2307 * For ASF and Pass Through versions of f/w this means that the 2308 * driver is no longer loaded. For AMT version (only with 82573) i 2309 * of the f/w this means that the network i/f is closed. 2310 * 2311 **/ 2312 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2313 { 2314 struct e1000_hw *hw = &adapter->hw; 2315 u32 ctrl_ext; 2316 u32 swsm; 2317 2318 /* Let firmware taken over control of h/w */ 2319 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2320 swsm = er32(SWSM); 2321 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2322 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2323 ctrl_ext = er32(CTRL_EXT); 2324 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2325 } 2326 } 2327 2328 /** 2329 * e1000_alloc_ring_dma - allocate memory for a ring structure 2330 **/ 2331 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2332 struct e1000_ring *ring) 2333 { 2334 struct pci_dev *pdev = adapter->pdev; 2335 2336 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2337 GFP_KERNEL); 2338 if (!ring->desc) 2339 return -ENOMEM; 2340 2341 return 0; 2342 } 2343 2344 /** 2345 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2346 * @tx_ring: Tx descriptor ring 2347 * 2348 * Return 0 on success, negative on failure 2349 **/ 2350 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2351 { 2352 struct e1000_adapter *adapter = tx_ring->adapter; 2353 int err = -ENOMEM, size; 2354 2355 size = sizeof(struct e1000_buffer) * tx_ring->count; 2356 tx_ring->buffer_info = vzalloc(size); 2357 if (!tx_ring->buffer_info) 2358 goto err; 2359 2360 /* round up to nearest 4K */ 2361 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2362 tx_ring->size = ALIGN(tx_ring->size, 4096); 2363 2364 err = e1000_alloc_ring_dma(adapter, tx_ring); 2365 if (err) 2366 goto err; 2367 2368 tx_ring->next_to_use = 0; 2369 tx_ring->next_to_clean = 0; 2370 2371 return 0; 2372 err: 2373 vfree(tx_ring->buffer_info); 2374 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2375 return err; 2376 } 2377 2378 /** 2379 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2380 * @rx_ring: Rx descriptor ring 2381 * 2382 * Returns 0 on success, negative on failure 2383 **/ 2384 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2385 { 2386 struct e1000_adapter *adapter = rx_ring->adapter; 2387 struct e1000_buffer *buffer_info; 2388 int i, size, desc_len, err = -ENOMEM; 2389 2390 size = sizeof(struct e1000_buffer) * rx_ring->count; 2391 rx_ring->buffer_info = vzalloc(size); 2392 if (!rx_ring->buffer_info) 2393 goto err; 2394 2395 for (i = 0; i < rx_ring->count; i++) { 2396 buffer_info = &rx_ring->buffer_info[i]; 2397 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2398 sizeof(struct e1000_ps_page), 2399 GFP_KERNEL); 2400 if (!buffer_info->ps_pages) 2401 goto err_pages; 2402 } 2403 2404 desc_len = sizeof(union e1000_rx_desc_packet_split); 2405 2406 /* Round up to nearest 4K */ 2407 rx_ring->size = rx_ring->count * desc_len; 2408 rx_ring->size = ALIGN(rx_ring->size, 4096); 2409 2410 err = e1000_alloc_ring_dma(adapter, rx_ring); 2411 if (err) 2412 goto err_pages; 2413 2414 rx_ring->next_to_clean = 0; 2415 rx_ring->next_to_use = 0; 2416 rx_ring->rx_skb_top = NULL; 2417 2418 return 0; 2419 2420 err_pages: 2421 for (i = 0; i < rx_ring->count; i++) { 2422 buffer_info = &rx_ring->buffer_info[i]; 2423 kfree(buffer_info->ps_pages); 2424 } 2425 err: 2426 vfree(rx_ring->buffer_info); 2427 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2428 return err; 2429 } 2430 2431 /** 2432 * e1000_clean_tx_ring - Free Tx Buffers 2433 * @tx_ring: Tx descriptor ring 2434 **/ 2435 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2436 { 2437 struct e1000_adapter *adapter = tx_ring->adapter; 2438 struct e1000_buffer *buffer_info; 2439 unsigned long size; 2440 unsigned int i; 2441 2442 for (i = 0; i < tx_ring->count; i++) { 2443 buffer_info = &tx_ring->buffer_info[i]; 2444 e1000_put_txbuf(tx_ring, buffer_info, false); 2445 } 2446 2447 netdev_reset_queue(adapter->netdev); 2448 size = sizeof(struct e1000_buffer) * tx_ring->count; 2449 memset(tx_ring->buffer_info, 0, size); 2450 2451 memset(tx_ring->desc, 0, tx_ring->size); 2452 2453 tx_ring->next_to_use = 0; 2454 tx_ring->next_to_clean = 0; 2455 } 2456 2457 /** 2458 * e1000e_free_tx_resources - Free Tx Resources per Queue 2459 * @tx_ring: Tx descriptor ring 2460 * 2461 * Free all transmit software resources 2462 **/ 2463 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2464 { 2465 struct e1000_adapter *adapter = tx_ring->adapter; 2466 struct pci_dev *pdev = adapter->pdev; 2467 2468 e1000_clean_tx_ring(tx_ring); 2469 2470 vfree(tx_ring->buffer_info); 2471 tx_ring->buffer_info = NULL; 2472 2473 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2474 tx_ring->dma); 2475 tx_ring->desc = NULL; 2476 } 2477 2478 /** 2479 * e1000e_free_rx_resources - Free Rx Resources 2480 * @rx_ring: Rx descriptor ring 2481 * 2482 * Free all receive software resources 2483 **/ 2484 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2485 { 2486 struct e1000_adapter *adapter = rx_ring->adapter; 2487 struct pci_dev *pdev = adapter->pdev; 2488 int i; 2489 2490 e1000_clean_rx_ring(rx_ring); 2491 2492 for (i = 0; i < rx_ring->count; i++) 2493 kfree(rx_ring->buffer_info[i].ps_pages); 2494 2495 vfree(rx_ring->buffer_info); 2496 rx_ring->buffer_info = NULL; 2497 2498 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2499 rx_ring->dma); 2500 rx_ring->desc = NULL; 2501 } 2502 2503 /** 2504 * e1000_update_itr - update the dynamic ITR value based on statistics 2505 * @adapter: pointer to adapter 2506 * @itr_setting: current adapter->itr 2507 * @packets: the number of packets during this measurement interval 2508 * @bytes: the number of bytes during this measurement interval 2509 * 2510 * Stores a new ITR value based on packets and byte 2511 * counts during the last interrupt. The advantage of per interrupt 2512 * computation is faster updates and more accurate ITR for the current 2513 * traffic pattern. Constants in this function were computed 2514 * based on theoretical maximum wire speed and thresholds were set based 2515 * on testing data as well as attempting to minimize response time 2516 * while increasing bulk throughput. This functionality is controlled 2517 * by the InterruptThrottleRate module parameter. 2518 **/ 2519 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2520 { 2521 unsigned int retval = itr_setting; 2522 2523 if (packets == 0) 2524 return itr_setting; 2525 2526 switch (itr_setting) { 2527 case lowest_latency: 2528 /* handle TSO and jumbo frames */ 2529 if (bytes / packets > 8000) 2530 retval = bulk_latency; 2531 else if ((packets < 5) && (bytes > 512)) 2532 retval = low_latency; 2533 break; 2534 case low_latency: /* 50 usec aka 20000 ints/s */ 2535 if (bytes > 10000) { 2536 /* this if handles the TSO accounting */ 2537 if (bytes / packets > 8000) 2538 retval = bulk_latency; 2539 else if ((packets < 10) || ((bytes / packets) > 1200)) 2540 retval = bulk_latency; 2541 else if ((packets > 35)) 2542 retval = lowest_latency; 2543 } else if (bytes / packets > 2000) { 2544 retval = bulk_latency; 2545 } else if (packets <= 2 && bytes < 512) { 2546 retval = lowest_latency; 2547 } 2548 break; 2549 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2550 if (bytes > 25000) { 2551 if (packets > 35) 2552 retval = low_latency; 2553 } else if (bytes < 6000) { 2554 retval = low_latency; 2555 } 2556 break; 2557 } 2558 2559 return retval; 2560 } 2561 2562 static void e1000_set_itr(struct e1000_adapter *adapter) 2563 { 2564 u16 current_itr; 2565 u32 new_itr = adapter->itr; 2566 2567 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2568 if (adapter->link_speed != SPEED_1000) { 2569 current_itr = 0; 2570 new_itr = 4000; 2571 goto set_itr_now; 2572 } 2573 2574 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2575 new_itr = 0; 2576 goto set_itr_now; 2577 } 2578 2579 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2580 adapter->total_tx_packets, 2581 adapter->total_tx_bytes); 2582 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2583 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2584 adapter->tx_itr = low_latency; 2585 2586 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2587 adapter->total_rx_packets, 2588 adapter->total_rx_bytes); 2589 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2590 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2591 adapter->rx_itr = low_latency; 2592 2593 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2594 2595 /* counts and packets in update_itr are dependent on these numbers */ 2596 switch (current_itr) { 2597 case lowest_latency: 2598 new_itr = 70000; 2599 break; 2600 case low_latency: 2601 new_itr = 20000; /* aka hwitr = ~200 */ 2602 break; 2603 case bulk_latency: 2604 new_itr = 4000; 2605 break; 2606 default: 2607 break; 2608 } 2609 2610 set_itr_now: 2611 if (new_itr != adapter->itr) { 2612 /* this attempts to bias the interrupt rate towards Bulk 2613 * by adding intermediate steps when interrupt rate is 2614 * increasing 2615 */ 2616 new_itr = new_itr > adapter->itr ? 2617 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2618 adapter->itr = new_itr; 2619 adapter->rx_ring->itr_val = new_itr; 2620 if (adapter->msix_entries) 2621 adapter->rx_ring->set_itr = 1; 2622 else 2623 e1000e_write_itr(adapter, new_itr); 2624 } 2625 } 2626 2627 /** 2628 * e1000e_write_itr - write the ITR value to the appropriate registers 2629 * @adapter: address of board private structure 2630 * @itr: new ITR value to program 2631 * 2632 * e1000e_write_itr determines if the adapter is in MSI-X mode 2633 * and, if so, writes the EITR registers with the ITR value. 2634 * Otherwise, it writes the ITR value into the ITR register. 2635 **/ 2636 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2637 { 2638 struct e1000_hw *hw = &adapter->hw; 2639 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2640 2641 if (adapter->msix_entries) { 2642 int vector; 2643 2644 for (vector = 0; vector < adapter->num_vectors; vector++) 2645 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2646 } else { 2647 ew32(ITR, new_itr); 2648 } 2649 } 2650 2651 /** 2652 * e1000_alloc_queues - Allocate memory for all rings 2653 * @adapter: board private structure to initialize 2654 **/ 2655 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2656 { 2657 int size = sizeof(struct e1000_ring); 2658 2659 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2660 if (!adapter->tx_ring) 2661 goto err; 2662 adapter->tx_ring->count = adapter->tx_ring_count; 2663 adapter->tx_ring->adapter = adapter; 2664 2665 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2666 if (!adapter->rx_ring) 2667 goto err; 2668 adapter->rx_ring->count = adapter->rx_ring_count; 2669 adapter->rx_ring->adapter = adapter; 2670 2671 return 0; 2672 err: 2673 e_err("Unable to allocate memory for queues\n"); 2674 kfree(adapter->rx_ring); 2675 kfree(adapter->tx_ring); 2676 return -ENOMEM; 2677 } 2678 2679 /** 2680 * e1000e_poll - NAPI Rx polling callback 2681 * @napi: struct associated with this polling callback 2682 * @weight: number of packets driver is allowed to process this poll 2683 **/ 2684 static int e1000e_poll(struct napi_struct *napi, int weight) 2685 { 2686 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2687 napi); 2688 struct e1000_hw *hw = &adapter->hw; 2689 struct net_device *poll_dev = adapter->netdev; 2690 int tx_cleaned = 1, work_done = 0; 2691 2692 adapter = netdev_priv(poll_dev); 2693 2694 if (!adapter->msix_entries || 2695 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2696 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2697 2698 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2699 2700 if (!tx_cleaned) 2701 work_done = weight; 2702 2703 /* If weight not fully consumed, exit the polling mode */ 2704 if (work_done < weight) { 2705 if (adapter->itr_setting & 3) 2706 e1000_set_itr(adapter); 2707 napi_complete_done(napi, work_done); 2708 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2709 if (adapter->msix_entries) 2710 ew32(IMS, adapter->rx_ring->ims_val | 2711 E1000_IMS_OTHER); 2712 else 2713 e1000_irq_enable(adapter); 2714 } 2715 } 2716 2717 return work_done; 2718 } 2719 2720 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2721 __always_unused __be16 proto, u16 vid) 2722 { 2723 struct e1000_adapter *adapter = netdev_priv(netdev); 2724 struct e1000_hw *hw = &adapter->hw; 2725 u32 vfta, index; 2726 2727 /* don't update vlan cookie if already programmed */ 2728 if ((adapter->hw.mng_cookie.status & 2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2730 (vid == adapter->mng_vlan_id)) 2731 return 0; 2732 2733 /* add VID to filter table */ 2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2735 index = (vid >> 5) & 0x7F; 2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2737 vfta |= BIT((vid & 0x1F)); 2738 hw->mac.ops.write_vfta(hw, index, vfta); 2739 } 2740 2741 set_bit(vid, adapter->active_vlans); 2742 2743 return 0; 2744 } 2745 2746 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2747 __always_unused __be16 proto, u16 vid) 2748 { 2749 struct e1000_adapter *adapter = netdev_priv(netdev); 2750 struct e1000_hw *hw = &adapter->hw; 2751 u32 vfta, index; 2752 2753 if ((adapter->hw.mng_cookie.status & 2754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2755 (vid == adapter->mng_vlan_id)) { 2756 /* release control to f/w */ 2757 e1000e_release_hw_control(adapter); 2758 return 0; 2759 } 2760 2761 /* remove VID from filter table */ 2762 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2763 index = (vid >> 5) & 0x7F; 2764 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2765 vfta &= ~BIT((vid & 0x1F)); 2766 hw->mac.ops.write_vfta(hw, index, vfta); 2767 } 2768 2769 clear_bit(vid, adapter->active_vlans); 2770 2771 return 0; 2772 } 2773 2774 /** 2775 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2776 * @adapter: board private structure to initialize 2777 **/ 2778 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2779 { 2780 struct net_device *netdev = adapter->netdev; 2781 struct e1000_hw *hw = &adapter->hw; 2782 u32 rctl; 2783 2784 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2785 /* disable VLAN receive filtering */ 2786 rctl = er32(RCTL); 2787 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2788 ew32(RCTL, rctl); 2789 2790 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2791 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2792 adapter->mng_vlan_id); 2793 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2794 } 2795 } 2796 } 2797 2798 /** 2799 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2800 * @adapter: board private structure to initialize 2801 **/ 2802 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2803 { 2804 struct e1000_hw *hw = &adapter->hw; 2805 u32 rctl; 2806 2807 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2808 /* enable VLAN receive filtering */ 2809 rctl = er32(RCTL); 2810 rctl |= E1000_RCTL_VFE; 2811 rctl &= ~E1000_RCTL_CFIEN; 2812 ew32(RCTL, rctl); 2813 } 2814 } 2815 2816 /** 2817 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2818 * @adapter: board private structure to initialize 2819 **/ 2820 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2821 { 2822 struct e1000_hw *hw = &adapter->hw; 2823 u32 ctrl; 2824 2825 /* disable VLAN tag insert/strip */ 2826 ctrl = er32(CTRL); 2827 ctrl &= ~E1000_CTRL_VME; 2828 ew32(CTRL, ctrl); 2829 } 2830 2831 /** 2832 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2833 * @adapter: board private structure to initialize 2834 **/ 2835 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2836 { 2837 struct e1000_hw *hw = &adapter->hw; 2838 u32 ctrl; 2839 2840 /* enable VLAN tag insert/strip */ 2841 ctrl = er32(CTRL); 2842 ctrl |= E1000_CTRL_VME; 2843 ew32(CTRL, ctrl); 2844 } 2845 2846 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2847 { 2848 struct net_device *netdev = adapter->netdev; 2849 u16 vid = adapter->hw.mng_cookie.vlan_id; 2850 u16 old_vid = adapter->mng_vlan_id; 2851 2852 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2853 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2854 adapter->mng_vlan_id = vid; 2855 } 2856 2857 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2858 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2859 } 2860 2861 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2862 { 2863 u16 vid; 2864 2865 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2866 2867 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2868 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2869 } 2870 2871 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2872 { 2873 struct e1000_hw *hw = &adapter->hw; 2874 u32 manc, manc2h, mdef, i, j; 2875 2876 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2877 return; 2878 2879 manc = er32(MANC); 2880 2881 /* enable receiving management packets to the host. this will probably 2882 * generate destination unreachable messages from the host OS, but 2883 * the packets will be handled on SMBUS 2884 */ 2885 manc |= E1000_MANC_EN_MNG2HOST; 2886 manc2h = er32(MANC2H); 2887 2888 switch (hw->mac.type) { 2889 default: 2890 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2891 break; 2892 case e1000_82574: 2893 case e1000_82583: 2894 /* Check if IPMI pass-through decision filter already exists; 2895 * if so, enable it. 2896 */ 2897 for (i = 0, j = 0; i < 8; i++) { 2898 mdef = er32(MDEF(i)); 2899 2900 /* Ignore filters with anything other than IPMI ports */ 2901 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2902 continue; 2903 2904 /* Enable this decision filter in MANC2H */ 2905 if (mdef) 2906 manc2h |= BIT(i); 2907 2908 j |= mdef; 2909 } 2910 2911 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2912 break; 2913 2914 /* Create new decision filter in an empty filter */ 2915 for (i = 0, j = 0; i < 8; i++) 2916 if (er32(MDEF(i)) == 0) { 2917 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2918 E1000_MDEF_PORT_664)); 2919 manc2h |= BIT(1); 2920 j++; 2921 break; 2922 } 2923 2924 if (!j) 2925 e_warn("Unable to create IPMI pass-through filter\n"); 2926 break; 2927 } 2928 2929 ew32(MANC2H, manc2h); 2930 ew32(MANC, manc); 2931 } 2932 2933 /** 2934 * e1000_configure_tx - Configure Transmit Unit after Reset 2935 * @adapter: board private structure 2936 * 2937 * Configure the Tx unit of the MAC after a reset. 2938 **/ 2939 static void e1000_configure_tx(struct e1000_adapter *adapter) 2940 { 2941 struct e1000_hw *hw = &adapter->hw; 2942 struct e1000_ring *tx_ring = adapter->tx_ring; 2943 u64 tdba; 2944 u32 tdlen, tctl, tarc; 2945 2946 /* Setup the HW Tx Head and Tail descriptor pointers */ 2947 tdba = tx_ring->dma; 2948 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2949 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2950 ew32(TDBAH(0), (tdba >> 32)); 2951 ew32(TDLEN(0), tdlen); 2952 ew32(TDH(0), 0); 2953 ew32(TDT(0), 0); 2954 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2955 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2956 2957 writel(0, tx_ring->head); 2958 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2959 e1000e_update_tdt_wa(tx_ring, 0); 2960 else 2961 writel(0, tx_ring->tail); 2962 2963 /* Set the Tx Interrupt Delay register */ 2964 ew32(TIDV, adapter->tx_int_delay); 2965 /* Tx irq moderation */ 2966 ew32(TADV, adapter->tx_abs_int_delay); 2967 2968 if (adapter->flags2 & FLAG2_DMA_BURST) { 2969 u32 txdctl = er32(TXDCTL(0)); 2970 2971 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2972 E1000_TXDCTL_WTHRESH); 2973 /* set up some performance related parameters to encourage the 2974 * hardware to use the bus more efficiently in bursts, depends 2975 * on the tx_int_delay to be enabled, 2976 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2977 * hthresh = 1 ==> prefetch when one or more available 2978 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2979 * BEWARE: this seems to work but should be considered first if 2980 * there are Tx hangs or other Tx related bugs 2981 */ 2982 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2983 ew32(TXDCTL(0), txdctl); 2984 } 2985 /* erratum work around: set txdctl the same for both queues */ 2986 ew32(TXDCTL(1), er32(TXDCTL(0))); 2987 2988 /* Program the Transmit Control Register */ 2989 tctl = er32(TCTL); 2990 tctl &= ~E1000_TCTL_CT; 2991 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2992 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2993 2994 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2995 tarc = er32(TARC(0)); 2996 /* set the speed mode bit, we'll clear it if we're not at 2997 * gigabit link later 2998 */ 2999 #define SPEED_MODE_BIT BIT(21) 3000 tarc |= SPEED_MODE_BIT; 3001 ew32(TARC(0), tarc); 3002 } 3003 3004 /* errata: program both queues to unweighted RR */ 3005 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3006 tarc = er32(TARC(0)); 3007 tarc |= 1; 3008 ew32(TARC(0), tarc); 3009 tarc = er32(TARC(1)); 3010 tarc |= 1; 3011 ew32(TARC(1), tarc); 3012 } 3013 3014 /* Setup Transmit Descriptor Settings for eop descriptor */ 3015 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3016 3017 /* only set IDE if we are delaying interrupts using the timers */ 3018 if (adapter->tx_int_delay) 3019 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3020 3021 /* enable Report Status bit */ 3022 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3023 3024 ew32(TCTL, tctl); 3025 3026 hw->mac.ops.config_collision_dist(hw); 3027 3028 /* SPT and KBL Si errata workaround to avoid data corruption */ 3029 if (hw->mac.type == e1000_pch_spt) { 3030 u32 reg_val; 3031 3032 reg_val = er32(IOSFPC); 3033 reg_val |= E1000_RCTL_RDMTS_HEX; 3034 ew32(IOSFPC, reg_val); 3035 3036 reg_val = er32(TARC(0)); 3037 /* SPT and KBL Si errata workaround to avoid Tx hang. 3038 * Dropping the number of outstanding requests from 3039 * 3 to 2 in order to avoid a buffer overrun. 3040 */ 3041 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3042 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 3043 ew32(TARC(0), reg_val); 3044 } 3045 } 3046 3047 /** 3048 * e1000_setup_rctl - configure the receive control registers 3049 * @adapter: Board private structure 3050 **/ 3051 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3052 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3053 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3054 { 3055 struct e1000_hw *hw = &adapter->hw; 3056 u32 rctl, rfctl; 3057 u32 pages = 0; 3058 3059 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3060 * If jumbo frames not set, program related MAC/PHY registers 3061 * to h/w defaults 3062 */ 3063 if (hw->mac.type >= e1000_pch2lan) { 3064 s32 ret_val; 3065 3066 if (adapter->netdev->mtu > ETH_DATA_LEN) 3067 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3068 else 3069 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3070 3071 if (ret_val) 3072 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3073 } 3074 3075 /* Program MC offset vector base */ 3076 rctl = er32(RCTL); 3077 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3078 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3079 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3080 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3081 3082 /* Do not Store bad packets */ 3083 rctl &= ~E1000_RCTL_SBP; 3084 3085 /* Enable Long Packet receive */ 3086 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3087 rctl &= ~E1000_RCTL_LPE; 3088 else 3089 rctl |= E1000_RCTL_LPE; 3090 3091 /* Some systems expect that the CRC is included in SMBUS traffic. The 3092 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3093 * host memory when this is enabled 3094 */ 3095 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3096 rctl |= E1000_RCTL_SECRC; 3097 3098 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3099 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3100 u16 phy_data; 3101 3102 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3103 phy_data &= 0xfff8; 3104 phy_data |= BIT(2); 3105 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3106 3107 e1e_rphy(hw, 22, &phy_data); 3108 phy_data &= 0x0fff; 3109 phy_data |= BIT(14); 3110 e1e_wphy(hw, 0x10, 0x2823); 3111 e1e_wphy(hw, 0x11, 0x0003); 3112 e1e_wphy(hw, 22, phy_data); 3113 } 3114 3115 /* Setup buffer sizes */ 3116 rctl &= ~E1000_RCTL_SZ_4096; 3117 rctl |= E1000_RCTL_BSEX; 3118 switch (adapter->rx_buffer_len) { 3119 case 2048: 3120 default: 3121 rctl |= E1000_RCTL_SZ_2048; 3122 rctl &= ~E1000_RCTL_BSEX; 3123 break; 3124 case 4096: 3125 rctl |= E1000_RCTL_SZ_4096; 3126 break; 3127 case 8192: 3128 rctl |= E1000_RCTL_SZ_8192; 3129 break; 3130 case 16384: 3131 rctl |= E1000_RCTL_SZ_16384; 3132 break; 3133 } 3134 3135 /* Enable Extended Status in all Receive Descriptors */ 3136 rfctl = er32(RFCTL); 3137 rfctl |= E1000_RFCTL_EXTEN; 3138 ew32(RFCTL, rfctl); 3139 3140 /* 82571 and greater support packet-split where the protocol 3141 * header is placed in skb->data and the packet data is 3142 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3143 * In the case of a non-split, skb->data is linearly filled, 3144 * followed by the page buffers. Therefore, skb->data is 3145 * sized to hold the largest protocol header. 3146 * 3147 * allocations using alloc_page take too long for regular MTU 3148 * so only enable packet split for jumbo frames 3149 * 3150 * Using pages when the page size is greater than 16k wastes 3151 * a lot of memory, since we allocate 3 pages at all times 3152 * per packet. 3153 */ 3154 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3155 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3156 adapter->rx_ps_pages = pages; 3157 else 3158 adapter->rx_ps_pages = 0; 3159 3160 if (adapter->rx_ps_pages) { 3161 u32 psrctl = 0; 3162 3163 /* Enable Packet split descriptors */ 3164 rctl |= E1000_RCTL_DTYP_PS; 3165 3166 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3167 3168 switch (adapter->rx_ps_pages) { 3169 case 3: 3170 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3171 /* fall-through */ 3172 case 2: 3173 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3174 /* fall-through */ 3175 case 1: 3176 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3177 break; 3178 } 3179 3180 ew32(PSRCTL, psrctl); 3181 } 3182 3183 /* This is useful for sniffing bad packets. */ 3184 if (adapter->netdev->features & NETIF_F_RXALL) { 3185 /* UPE and MPE will be handled by normal PROMISC logic 3186 * in e1000e_set_rx_mode 3187 */ 3188 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3189 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3190 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3191 3192 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3193 E1000_RCTL_DPF | /* Allow filtered pause */ 3194 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3195 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3196 * and that breaks VLANs. 3197 */ 3198 } 3199 3200 ew32(RCTL, rctl); 3201 /* just started the receive unit, no need to restart */ 3202 adapter->flags &= ~FLAG_RESTART_NOW; 3203 } 3204 3205 /** 3206 * e1000_configure_rx - Configure Receive Unit after Reset 3207 * @adapter: board private structure 3208 * 3209 * Configure the Rx unit of the MAC after a reset. 3210 **/ 3211 static void e1000_configure_rx(struct e1000_adapter *adapter) 3212 { 3213 struct e1000_hw *hw = &adapter->hw; 3214 struct e1000_ring *rx_ring = adapter->rx_ring; 3215 u64 rdba; 3216 u32 rdlen, rctl, rxcsum, ctrl_ext; 3217 3218 if (adapter->rx_ps_pages) { 3219 /* this is a 32 byte descriptor */ 3220 rdlen = rx_ring->count * 3221 sizeof(union e1000_rx_desc_packet_split); 3222 adapter->clean_rx = e1000_clean_rx_irq_ps; 3223 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3224 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3225 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3226 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3227 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3228 } else { 3229 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3230 adapter->clean_rx = e1000_clean_rx_irq; 3231 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3232 } 3233 3234 /* disable receives while setting up the descriptors */ 3235 rctl = er32(RCTL); 3236 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3237 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3238 e1e_flush(); 3239 usleep_range(10000, 20000); 3240 3241 if (adapter->flags2 & FLAG2_DMA_BURST) { 3242 /* set the writeback threshold (only takes effect if the RDTR 3243 * is set). set GRAN=1 and write back up to 0x4 worth, and 3244 * enable prefetching of 0x20 Rx descriptors 3245 * granularity = 01 3246 * wthresh = 04, 3247 * hthresh = 04, 3248 * pthresh = 0x20 3249 */ 3250 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3251 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3252 } 3253 3254 /* set the Receive Delay Timer Register */ 3255 ew32(RDTR, adapter->rx_int_delay); 3256 3257 /* irq moderation */ 3258 ew32(RADV, adapter->rx_abs_int_delay); 3259 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3260 e1000e_write_itr(adapter, adapter->itr); 3261 3262 ctrl_ext = er32(CTRL_EXT); 3263 /* Auto-Mask interrupts upon ICR access */ 3264 ctrl_ext |= E1000_CTRL_EXT_IAME; 3265 ew32(IAM, 0xffffffff); 3266 ew32(CTRL_EXT, ctrl_ext); 3267 e1e_flush(); 3268 3269 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3270 * the Base and Length of the Rx Descriptor Ring 3271 */ 3272 rdba = rx_ring->dma; 3273 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3274 ew32(RDBAH(0), (rdba >> 32)); 3275 ew32(RDLEN(0), rdlen); 3276 ew32(RDH(0), 0); 3277 ew32(RDT(0), 0); 3278 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3279 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3280 3281 writel(0, rx_ring->head); 3282 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3283 e1000e_update_rdt_wa(rx_ring, 0); 3284 else 3285 writel(0, rx_ring->tail); 3286 3287 /* Enable Receive Checksum Offload for TCP and UDP */ 3288 rxcsum = er32(RXCSUM); 3289 if (adapter->netdev->features & NETIF_F_RXCSUM) 3290 rxcsum |= E1000_RXCSUM_TUOFL; 3291 else 3292 rxcsum &= ~E1000_RXCSUM_TUOFL; 3293 ew32(RXCSUM, rxcsum); 3294 3295 /* With jumbo frames, excessive C-state transition latencies result 3296 * in dropped transactions. 3297 */ 3298 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3299 u32 lat = 3300 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3301 adapter->max_frame_size) * 8 / 1000; 3302 3303 if (adapter->flags & FLAG_IS_ICH) { 3304 u32 rxdctl = er32(RXDCTL(0)); 3305 3306 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); 3307 } 3308 3309 dev_info(&adapter->pdev->dev, 3310 "Some CPU C-states have been disabled in order to enable jumbo frames\n"); 3311 pm_qos_update_request(&adapter->pm_qos_req, lat); 3312 } else { 3313 pm_qos_update_request(&adapter->pm_qos_req, 3314 PM_QOS_DEFAULT_VALUE); 3315 } 3316 3317 /* Enable Receives */ 3318 ew32(RCTL, rctl); 3319 } 3320 3321 /** 3322 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3323 * @netdev: network interface device structure 3324 * 3325 * Writes multicast address list to the MTA hash table. 3326 * Returns: -ENOMEM on failure 3327 * 0 on no addresses written 3328 * X on writing X addresses to MTA 3329 */ 3330 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3331 { 3332 struct e1000_adapter *adapter = netdev_priv(netdev); 3333 struct e1000_hw *hw = &adapter->hw; 3334 struct netdev_hw_addr *ha; 3335 u8 *mta_list; 3336 int i; 3337 3338 if (netdev_mc_empty(netdev)) { 3339 /* nothing to program, so clear mc list */ 3340 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3341 return 0; 3342 } 3343 3344 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3345 if (!mta_list) 3346 return -ENOMEM; 3347 3348 /* update_mc_addr_list expects a packed array of only addresses. */ 3349 i = 0; 3350 netdev_for_each_mc_addr(ha, netdev) 3351 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3352 3353 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3354 kfree(mta_list); 3355 3356 return netdev_mc_count(netdev); 3357 } 3358 3359 /** 3360 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3361 * @netdev: network interface device structure 3362 * 3363 * Writes unicast address list to the RAR table. 3364 * Returns: -ENOMEM on failure/insufficient address space 3365 * 0 on no addresses written 3366 * X on writing X addresses to the RAR table 3367 **/ 3368 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3369 { 3370 struct e1000_adapter *adapter = netdev_priv(netdev); 3371 struct e1000_hw *hw = &adapter->hw; 3372 unsigned int rar_entries; 3373 int count = 0; 3374 3375 rar_entries = hw->mac.ops.rar_get_count(hw); 3376 3377 /* save a rar entry for our hardware address */ 3378 rar_entries--; 3379 3380 /* save a rar entry for the LAA workaround */ 3381 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3382 rar_entries--; 3383 3384 /* return ENOMEM indicating insufficient memory for addresses */ 3385 if (netdev_uc_count(netdev) > rar_entries) 3386 return -ENOMEM; 3387 3388 if (!netdev_uc_empty(netdev) && rar_entries) { 3389 struct netdev_hw_addr *ha; 3390 3391 /* write the addresses in reverse order to avoid write 3392 * combining 3393 */ 3394 netdev_for_each_uc_addr(ha, netdev) { 3395 int ret_val; 3396 3397 if (!rar_entries) 3398 break; 3399 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3400 if (ret_val < 0) 3401 return -ENOMEM; 3402 count++; 3403 } 3404 } 3405 3406 /* zero out the remaining RAR entries not used above */ 3407 for (; rar_entries > 0; rar_entries--) { 3408 ew32(RAH(rar_entries), 0); 3409 ew32(RAL(rar_entries), 0); 3410 } 3411 e1e_flush(); 3412 3413 return count; 3414 } 3415 3416 /** 3417 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3418 * @netdev: network interface device structure 3419 * 3420 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3421 * address list or the network interface flags are updated. This routine is 3422 * responsible for configuring the hardware for proper unicast, multicast, 3423 * promiscuous mode, and all-multi behavior. 3424 **/ 3425 static void e1000e_set_rx_mode(struct net_device *netdev) 3426 { 3427 struct e1000_adapter *adapter = netdev_priv(netdev); 3428 struct e1000_hw *hw = &adapter->hw; 3429 u32 rctl; 3430 3431 if (pm_runtime_suspended(netdev->dev.parent)) 3432 return; 3433 3434 /* Check for Promiscuous and All Multicast modes */ 3435 rctl = er32(RCTL); 3436 3437 /* clear the affected bits */ 3438 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3439 3440 if (netdev->flags & IFF_PROMISC) { 3441 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3442 /* Do not hardware filter VLANs in promisc mode */ 3443 e1000e_vlan_filter_disable(adapter); 3444 } else { 3445 int count; 3446 3447 if (netdev->flags & IFF_ALLMULTI) { 3448 rctl |= E1000_RCTL_MPE; 3449 } else { 3450 /* Write addresses to the MTA, if the attempt fails 3451 * then we should just turn on promiscuous mode so 3452 * that we can at least receive multicast traffic 3453 */ 3454 count = e1000e_write_mc_addr_list(netdev); 3455 if (count < 0) 3456 rctl |= E1000_RCTL_MPE; 3457 } 3458 e1000e_vlan_filter_enable(adapter); 3459 /* Write addresses to available RAR registers, if there is not 3460 * sufficient space to store all the addresses then enable 3461 * unicast promiscuous mode 3462 */ 3463 count = e1000e_write_uc_addr_list(netdev); 3464 if (count < 0) 3465 rctl |= E1000_RCTL_UPE; 3466 } 3467 3468 ew32(RCTL, rctl); 3469 3470 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3471 e1000e_vlan_strip_enable(adapter); 3472 else 3473 e1000e_vlan_strip_disable(adapter); 3474 } 3475 3476 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3477 { 3478 struct e1000_hw *hw = &adapter->hw; 3479 u32 mrqc, rxcsum; 3480 u32 rss_key[10]; 3481 int i; 3482 3483 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3484 for (i = 0; i < 10; i++) 3485 ew32(RSSRK(i), rss_key[i]); 3486 3487 /* Direct all traffic to queue 0 */ 3488 for (i = 0; i < 32; i++) 3489 ew32(RETA(i), 0); 3490 3491 /* Disable raw packet checksumming so that RSS hash is placed in 3492 * descriptor on writeback. 3493 */ 3494 rxcsum = er32(RXCSUM); 3495 rxcsum |= E1000_RXCSUM_PCSD; 3496 3497 ew32(RXCSUM, rxcsum); 3498 3499 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3500 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3501 E1000_MRQC_RSS_FIELD_IPV6 | 3502 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3503 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3504 3505 ew32(MRQC, mrqc); 3506 } 3507 3508 /** 3509 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3510 * @adapter: board private structure 3511 * @timinca: pointer to returned time increment attributes 3512 * 3513 * Get attributes for incrementing the System Time Register SYSTIML/H at 3514 * the default base frequency, and set the cyclecounter shift value. 3515 **/ 3516 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3517 { 3518 struct e1000_hw *hw = &adapter->hw; 3519 u32 incvalue, incperiod, shift; 3520 3521 /* Make sure clock is enabled on I217/I218/I219 before checking 3522 * the frequency 3523 */ 3524 if ((hw->mac.type >= e1000_pch_lpt) && 3525 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3526 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3527 u32 fextnvm7 = er32(FEXTNVM7); 3528 3529 if (!(fextnvm7 & BIT(0))) { 3530 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3531 e1e_flush(); 3532 } 3533 } 3534 3535 switch (hw->mac.type) { 3536 case e1000_pch2lan: 3537 /* Stable 96MHz frequency */ 3538 incperiod = INCPERIOD_96MHZ; 3539 incvalue = INCVALUE_96MHZ; 3540 shift = INCVALUE_SHIFT_96MHZ; 3541 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3542 break; 3543 case e1000_pch_lpt: 3544 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3545 /* Stable 96MHz frequency */ 3546 incperiod = INCPERIOD_96MHZ; 3547 incvalue = INCVALUE_96MHZ; 3548 shift = INCVALUE_SHIFT_96MHZ; 3549 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3550 } else { 3551 /* Stable 25MHz frequency */ 3552 incperiod = INCPERIOD_25MHZ; 3553 incvalue = INCVALUE_25MHZ; 3554 shift = INCVALUE_SHIFT_25MHZ; 3555 adapter->cc.shift = shift; 3556 } 3557 break; 3558 case e1000_pch_spt: 3559 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3560 /* Stable 24MHz frequency */ 3561 incperiod = INCPERIOD_24MHZ; 3562 incvalue = INCVALUE_24MHZ; 3563 shift = INCVALUE_SHIFT_24MHZ; 3564 adapter->cc.shift = shift; 3565 break; 3566 } 3567 return -EINVAL; 3568 case e1000_pch_cnp: 3569 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3570 /* Stable 24MHz frequency */ 3571 incperiod = INCPERIOD_24MHZ; 3572 incvalue = INCVALUE_24MHZ; 3573 shift = INCVALUE_SHIFT_24MHZ; 3574 adapter->cc.shift = shift; 3575 } else { 3576 /* Stable 38400KHz frequency */ 3577 incperiod = INCPERIOD_38400KHZ; 3578 incvalue = INCVALUE_38400KHZ; 3579 shift = INCVALUE_SHIFT_38400KHZ; 3580 adapter->cc.shift = shift; 3581 } 3582 break; 3583 case e1000_82574: 3584 case e1000_82583: 3585 /* Stable 25MHz frequency */ 3586 incperiod = INCPERIOD_25MHZ; 3587 incvalue = INCVALUE_25MHZ; 3588 shift = INCVALUE_SHIFT_25MHZ; 3589 adapter->cc.shift = shift; 3590 break; 3591 default: 3592 return -EINVAL; 3593 } 3594 3595 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3596 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3597 3598 return 0; 3599 } 3600 3601 /** 3602 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3603 * @adapter: board private structure 3604 * 3605 * Outgoing time stamping can be enabled and disabled. Play nice and 3606 * disable it when requested, although it shouldn't cause any overhead 3607 * when no packet needs it. At most one packet in the queue may be 3608 * marked for time stamping, otherwise it would be impossible to tell 3609 * for sure to which packet the hardware time stamp belongs. 3610 * 3611 * Incoming time stamping has to be configured via the hardware filters. 3612 * Not all combinations are supported, in particular event type has to be 3613 * specified. Matching the kind of event packet is not supported, with the 3614 * exception of "all V2 events regardless of level 2 or 4". 3615 **/ 3616 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3617 struct hwtstamp_config *config) 3618 { 3619 struct e1000_hw *hw = &adapter->hw; 3620 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3621 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3622 u32 rxmtrl = 0; 3623 u16 rxudp = 0; 3624 bool is_l4 = false; 3625 bool is_l2 = false; 3626 u32 regval; 3627 3628 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3629 return -EINVAL; 3630 3631 /* flags reserved for future extensions - must be zero */ 3632 if (config->flags) 3633 return -EINVAL; 3634 3635 switch (config->tx_type) { 3636 case HWTSTAMP_TX_OFF: 3637 tsync_tx_ctl = 0; 3638 break; 3639 case HWTSTAMP_TX_ON: 3640 break; 3641 default: 3642 return -ERANGE; 3643 } 3644 3645 switch (config->rx_filter) { 3646 case HWTSTAMP_FILTER_NONE: 3647 tsync_rx_ctl = 0; 3648 break; 3649 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3651 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3652 is_l4 = true; 3653 break; 3654 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3655 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3656 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3657 is_l4 = true; 3658 break; 3659 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3660 /* Also time stamps V2 L2 Path Delay Request/Response */ 3661 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3662 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3663 is_l2 = true; 3664 break; 3665 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3666 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3667 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3668 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3669 is_l2 = true; 3670 break; 3671 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3672 /* Hardware cannot filter just V2 L4 Sync messages; 3673 * fall-through to V2 (both L2 and L4) Sync. 3674 */ 3675 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3676 /* Also time stamps V2 Path Delay Request/Response. */ 3677 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3678 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3679 is_l2 = true; 3680 is_l4 = true; 3681 break; 3682 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3683 /* Hardware cannot filter just V2 L4 Delay Request messages; 3684 * fall-through to V2 (both L2 and L4) Delay Request. 3685 */ 3686 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3687 /* Also time stamps V2 Path Delay Request/Response. */ 3688 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3689 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3690 is_l2 = true; 3691 is_l4 = true; 3692 break; 3693 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3694 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3695 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3696 * fall-through to all V2 (both L2 and L4) Events. 3697 */ 3698 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3699 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3700 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3701 is_l2 = true; 3702 is_l4 = true; 3703 break; 3704 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3705 /* For V1, the hardware can only filter Sync messages or 3706 * Delay Request messages but not both so fall-through to 3707 * time stamp all packets. 3708 */ 3709 case HWTSTAMP_FILTER_NTP_ALL: 3710 case HWTSTAMP_FILTER_ALL: 3711 is_l2 = true; 3712 is_l4 = true; 3713 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3714 config->rx_filter = HWTSTAMP_FILTER_ALL; 3715 break; 3716 default: 3717 return -ERANGE; 3718 } 3719 3720 adapter->hwtstamp_config = *config; 3721 3722 /* enable/disable Tx h/w time stamping */ 3723 regval = er32(TSYNCTXCTL); 3724 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3725 regval |= tsync_tx_ctl; 3726 ew32(TSYNCTXCTL, regval); 3727 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3728 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3729 e_err("Timesync Tx Control register not set as expected\n"); 3730 return -EAGAIN; 3731 } 3732 3733 /* enable/disable Rx h/w time stamping */ 3734 regval = er32(TSYNCRXCTL); 3735 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3736 regval |= tsync_rx_ctl; 3737 ew32(TSYNCRXCTL, regval); 3738 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3739 E1000_TSYNCRXCTL_TYPE_MASK)) != 3740 (regval & (E1000_TSYNCRXCTL_ENABLED | 3741 E1000_TSYNCRXCTL_TYPE_MASK))) { 3742 e_err("Timesync Rx Control register not set as expected\n"); 3743 return -EAGAIN; 3744 } 3745 3746 /* L2: define ethertype filter for time stamped packets */ 3747 if (is_l2) 3748 rxmtrl |= ETH_P_1588; 3749 3750 /* define which PTP packets get time stamped */ 3751 ew32(RXMTRL, rxmtrl); 3752 3753 /* Filter by destination port */ 3754 if (is_l4) { 3755 rxudp = PTP_EV_PORT; 3756 cpu_to_be16s(&rxudp); 3757 } 3758 ew32(RXUDP, rxudp); 3759 3760 e1e_flush(); 3761 3762 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3763 er32(RXSTMPH); 3764 er32(TXSTMPH); 3765 3766 return 0; 3767 } 3768 3769 /** 3770 * e1000_configure - configure the hardware for Rx and Tx 3771 * @adapter: private board structure 3772 **/ 3773 static void e1000_configure(struct e1000_adapter *adapter) 3774 { 3775 struct e1000_ring *rx_ring = adapter->rx_ring; 3776 3777 e1000e_set_rx_mode(adapter->netdev); 3778 3779 e1000_restore_vlan(adapter); 3780 e1000_init_manageability_pt(adapter); 3781 3782 e1000_configure_tx(adapter); 3783 3784 if (adapter->netdev->features & NETIF_F_RXHASH) 3785 e1000e_setup_rss_hash(adapter); 3786 e1000_setup_rctl(adapter); 3787 e1000_configure_rx(adapter); 3788 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3789 } 3790 3791 /** 3792 * e1000e_power_up_phy - restore link in case the phy was powered down 3793 * @adapter: address of board private structure 3794 * 3795 * The phy may be powered down to save power and turn off link when the 3796 * driver is unloaded and wake on lan is not enabled (among others) 3797 * *** this routine MUST be followed by a call to e1000e_reset *** 3798 **/ 3799 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3800 { 3801 if (adapter->hw.phy.ops.power_up) 3802 adapter->hw.phy.ops.power_up(&adapter->hw); 3803 3804 adapter->hw.mac.ops.setup_link(&adapter->hw); 3805 } 3806 3807 /** 3808 * e1000_power_down_phy - Power down the PHY 3809 * 3810 * Power down the PHY so no link is implied when interface is down. 3811 * The PHY cannot be powered down if management or WoL is active. 3812 */ 3813 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3814 { 3815 if (adapter->hw.phy.ops.power_down) 3816 adapter->hw.phy.ops.power_down(&adapter->hw); 3817 } 3818 3819 /** 3820 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3821 * 3822 * We want to clear all pending descriptors from the TX ring. 3823 * zeroing happens when the HW reads the regs. We assign the ring itself as 3824 * the data of the next descriptor. We don't care about the data we are about 3825 * to reset the HW. 3826 */ 3827 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3828 { 3829 struct e1000_hw *hw = &adapter->hw; 3830 struct e1000_ring *tx_ring = adapter->tx_ring; 3831 struct e1000_tx_desc *tx_desc = NULL; 3832 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3833 u16 size = 512; 3834 3835 tctl = er32(TCTL); 3836 ew32(TCTL, tctl | E1000_TCTL_EN); 3837 tdt = er32(TDT(0)); 3838 BUG_ON(tdt != tx_ring->next_to_use); 3839 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3840 tx_desc->buffer_addr = tx_ring->dma; 3841 3842 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3843 tx_desc->upper.data = 0; 3844 /* flush descriptors to memory before notifying the HW */ 3845 wmb(); 3846 tx_ring->next_to_use++; 3847 if (tx_ring->next_to_use == tx_ring->count) 3848 tx_ring->next_to_use = 0; 3849 ew32(TDT(0), tx_ring->next_to_use); 3850 mmiowb(); 3851 usleep_range(200, 250); 3852 } 3853 3854 /** 3855 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3856 * 3857 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3858 */ 3859 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3860 { 3861 u32 rctl, rxdctl; 3862 struct e1000_hw *hw = &adapter->hw; 3863 3864 rctl = er32(RCTL); 3865 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3866 e1e_flush(); 3867 usleep_range(100, 150); 3868 3869 rxdctl = er32(RXDCTL(0)); 3870 /* zero the lower 14 bits (prefetch and host thresholds) */ 3871 rxdctl &= 0xffffc000; 3872 3873 /* update thresholds: prefetch threshold to 31, host threshold to 1 3874 * and make sure the granularity is "descriptors" and not "cache lines" 3875 */ 3876 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3877 3878 ew32(RXDCTL(0), rxdctl); 3879 /* momentarily enable the RX ring for the changes to take effect */ 3880 ew32(RCTL, rctl | E1000_RCTL_EN); 3881 e1e_flush(); 3882 usleep_range(100, 150); 3883 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3884 } 3885 3886 /** 3887 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3888 * 3889 * In i219, the descriptor rings must be emptied before resetting the HW 3890 * or before changing the device state to D3 during runtime (runtime PM). 3891 * 3892 * Failure to do this will cause the HW to enter a unit hang state which can 3893 * only be released by PCI reset on the device 3894 * 3895 */ 3896 3897 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3898 { 3899 u16 hang_state; 3900 u32 fext_nvm11, tdlen; 3901 struct e1000_hw *hw = &adapter->hw; 3902 3903 /* First, disable MULR fix in FEXTNVM11 */ 3904 fext_nvm11 = er32(FEXTNVM11); 3905 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3906 ew32(FEXTNVM11, fext_nvm11); 3907 /* do nothing if we're not in faulty state, or if the queue is empty */ 3908 tdlen = er32(TDLEN(0)); 3909 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3910 &hang_state); 3911 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3912 return; 3913 e1000_flush_tx_ring(adapter); 3914 /* recheck, maybe the fault is caused by the rx ring */ 3915 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3916 &hang_state); 3917 if (hang_state & FLUSH_DESC_REQUIRED) 3918 e1000_flush_rx_ring(adapter); 3919 } 3920 3921 /** 3922 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3923 * @adapter: board private structure 3924 * 3925 * When the MAC is reset, all hardware bits for timesync will be reset to the 3926 * default values. This function will restore the settings last in place. 3927 * Since the clock SYSTIME registers are reset, we will simply restore the 3928 * cyclecounter to the kernel real clock time. 3929 **/ 3930 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3931 { 3932 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3933 struct e1000_hw *hw = &adapter->hw; 3934 unsigned long flags; 3935 u32 timinca; 3936 s32 ret_val; 3937 3938 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3939 return; 3940 3941 if (info->adjfreq) { 3942 /* restore the previous ptp frequency delta */ 3943 ret_val = info->adjfreq(info, adapter->ptp_delta); 3944 } else { 3945 /* set the default base frequency if no adjustment possible */ 3946 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3947 if (!ret_val) 3948 ew32(TIMINCA, timinca); 3949 } 3950 3951 if (ret_val) { 3952 dev_warn(&adapter->pdev->dev, 3953 "Failed to restore TIMINCA clock rate delta: %d\n", 3954 ret_val); 3955 return; 3956 } 3957 3958 /* reset the systim ns time counter */ 3959 spin_lock_irqsave(&adapter->systim_lock, flags); 3960 timecounter_init(&adapter->tc, &adapter->cc, 3961 ktime_to_ns(ktime_get_real())); 3962 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3963 3964 /* restore the previous hwtstamp configuration settings */ 3965 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3966 } 3967 3968 /** 3969 * e1000e_reset - bring the hardware into a known good state 3970 * 3971 * This function boots the hardware and enables some settings that 3972 * require a configuration cycle of the hardware - those cannot be 3973 * set/changed during runtime. After reset the device needs to be 3974 * properly configured for Rx, Tx etc. 3975 */ 3976 void e1000e_reset(struct e1000_adapter *adapter) 3977 { 3978 struct e1000_mac_info *mac = &adapter->hw.mac; 3979 struct e1000_fc_info *fc = &adapter->hw.fc; 3980 struct e1000_hw *hw = &adapter->hw; 3981 u32 tx_space, min_tx_space, min_rx_space; 3982 u32 pba = adapter->pba; 3983 u16 hwm; 3984 3985 /* reset Packet Buffer Allocation to default */ 3986 ew32(PBA, pba); 3987 3988 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3989 /* To maintain wire speed transmits, the Tx FIFO should be 3990 * large enough to accommodate two full transmit packets, 3991 * rounded up to the next 1KB and expressed in KB. Likewise, 3992 * the Rx FIFO should be large enough to accommodate at least 3993 * one full receive packet and is similarly rounded up and 3994 * expressed in KB. 3995 */ 3996 pba = er32(PBA); 3997 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3998 tx_space = pba >> 16; 3999 /* lower 16 bits has Rx packet buffer allocation size in KB */ 4000 pba &= 0xffff; 4001 /* the Tx fifo also stores 16 bytes of information about the Tx 4002 * but don't include ethernet FCS because hardware appends it 4003 */ 4004 min_tx_space = (adapter->max_frame_size + 4005 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4006 min_tx_space = ALIGN(min_tx_space, 1024); 4007 min_tx_space >>= 10; 4008 /* software strips receive CRC, so leave room for it */ 4009 min_rx_space = adapter->max_frame_size; 4010 min_rx_space = ALIGN(min_rx_space, 1024); 4011 min_rx_space >>= 10; 4012 4013 /* If current Tx allocation is less than the min Tx FIFO size, 4014 * and the min Tx FIFO size is less than the current Rx FIFO 4015 * allocation, take space away from current Rx allocation 4016 */ 4017 if ((tx_space < min_tx_space) && 4018 ((min_tx_space - tx_space) < pba)) { 4019 pba -= min_tx_space - tx_space; 4020 4021 /* if short on Rx space, Rx wins and must trump Tx 4022 * adjustment 4023 */ 4024 if (pba < min_rx_space) 4025 pba = min_rx_space; 4026 } 4027 4028 ew32(PBA, pba); 4029 } 4030 4031 /* flow control settings 4032 * 4033 * The high water mark must be low enough to fit one full frame 4034 * (or the size used for early receive) above it in the Rx FIFO. 4035 * Set it to the lower of: 4036 * - 90% of the Rx FIFO size, and 4037 * - the full Rx FIFO size minus one full frame 4038 */ 4039 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4040 fc->pause_time = 0xFFFF; 4041 else 4042 fc->pause_time = E1000_FC_PAUSE_TIME; 4043 fc->send_xon = true; 4044 fc->current_mode = fc->requested_mode; 4045 4046 switch (hw->mac.type) { 4047 case e1000_ich9lan: 4048 case e1000_ich10lan: 4049 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4050 pba = 14; 4051 ew32(PBA, pba); 4052 fc->high_water = 0x2800; 4053 fc->low_water = fc->high_water - 8; 4054 break; 4055 } 4056 /* fall-through */ 4057 default: 4058 hwm = min(((pba << 10) * 9 / 10), 4059 ((pba << 10) - adapter->max_frame_size)); 4060 4061 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4062 fc->low_water = fc->high_water - 8; 4063 break; 4064 case e1000_pchlan: 4065 /* Workaround PCH LOM adapter hangs with certain network 4066 * loads. If hangs persist, try disabling Tx flow control. 4067 */ 4068 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4069 fc->high_water = 0x3500; 4070 fc->low_water = 0x1500; 4071 } else { 4072 fc->high_water = 0x5000; 4073 fc->low_water = 0x3000; 4074 } 4075 fc->refresh_time = 0x1000; 4076 break; 4077 case e1000_pch2lan: 4078 case e1000_pch_lpt: 4079 case e1000_pch_spt: 4080 case e1000_pch_cnp: 4081 fc->refresh_time = 0x0400; 4082 4083 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4084 fc->high_water = 0x05C20; 4085 fc->low_water = 0x05048; 4086 fc->pause_time = 0x0650; 4087 break; 4088 } 4089 4090 pba = 14; 4091 ew32(PBA, pba); 4092 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4093 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4094 break; 4095 } 4096 4097 /* Alignment of Tx data is on an arbitrary byte boundary with the 4098 * maximum size per Tx descriptor limited only to the transmit 4099 * allocation of the packet buffer minus 96 bytes with an upper 4100 * limit of 24KB due to receive synchronization limitations. 4101 */ 4102 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4103 24 << 10); 4104 4105 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4106 * fit in receive buffer. 4107 */ 4108 if (adapter->itr_setting & 0x3) { 4109 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4110 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4111 dev_info(&adapter->pdev->dev, 4112 "Interrupt Throttle Rate off\n"); 4113 adapter->flags2 |= FLAG2_DISABLE_AIM; 4114 e1000e_write_itr(adapter, 0); 4115 } 4116 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4117 dev_info(&adapter->pdev->dev, 4118 "Interrupt Throttle Rate on\n"); 4119 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4120 adapter->itr = 20000; 4121 e1000e_write_itr(adapter, adapter->itr); 4122 } 4123 } 4124 4125 if (hw->mac.type >= e1000_pch_spt) 4126 e1000_flush_desc_rings(adapter); 4127 /* Allow time for pending master requests to run */ 4128 mac->ops.reset_hw(hw); 4129 4130 /* For parts with AMT enabled, let the firmware know 4131 * that the network interface is in control 4132 */ 4133 if (adapter->flags & FLAG_HAS_AMT) 4134 e1000e_get_hw_control(adapter); 4135 4136 ew32(WUC, 0); 4137 4138 if (mac->ops.init_hw(hw)) 4139 e_err("Hardware Error\n"); 4140 4141 e1000_update_mng_vlan(adapter); 4142 4143 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4144 ew32(VET, ETH_P_8021Q); 4145 4146 e1000e_reset_adaptive(hw); 4147 4148 /* restore systim and hwtstamp settings */ 4149 e1000e_systim_reset(adapter); 4150 4151 /* Set EEE advertisement as appropriate */ 4152 if (adapter->flags2 & FLAG2_HAS_EEE) { 4153 s32 ret_val; 4154 u16 adv_addr; 4155 4156 switch (hw->phy.type) { 4157 case e1000_phy_82579: 4158 adv_addr = I82579_EEE_ADVERTISEMENT; 4159 break; 4160 case e1000_phy_i217: 4161 adv_addr = I217_EEE_ADVERTISEMENT; 4162 break; 4163 default: 4164 dev_err(&adapter->pdev->dev, 4165 "Invalid PHY type setting EEE advertisement\n"); 4166 return; 4167 } 4168 4169 ret_val = hw->phy.ops.acquire(hw); 4170 if (ret_val) { 4171 dev_err(&adapter->pdev->dev, 4172 "EEE advertisement - unable to acquire PHY\n"); 4173 return; 4174 } 4175 4176 e1000_write_emi_reg_locked(hw, adv_addr, 4177 hw->dev_spec.ich8lan.eee_disable ? 4178 0 : adapter->eee_advert); 4179 4180 hw->phy.ops.release(hw); 4181 } 4182 4183 if (!netif_running(adapter->netdev) && 4184 !test_bit(__E1000_TESTING, &adapter->state)) 4185 e1000_power_down_phy(adapter); 4186 4187 e1000_get_phy_info(hw); 4188 4189 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4190 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4191 u16 phy_data = 0; 4192 /* speed up time to link by disabling smart power down, ignore 4193 * the return value of this function because there is nothing 4194 * different we would do if it failed 4195 */ 4196 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4197 phy_data &= ~IGP02E1000_PM_SPD; 4198 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4199 } 4200 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4201 u32 reg; 4202 4203 /* Fextnvm7 @ 0xe4[2] = 1 */ 4204 reg = er32(FEXTNVM7); 4205 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4206 ew32(FEXTNVM7, reg); 4207 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4208 reg = er32(FEXTNVM9); 4209 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4210 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4211 ew32(FEXTNVM9, reg); 4212 } 4213 4214 } 4215 4216 /** 4217 * e1000e_trigger_lsc - trigger an LSC interrupt 4218 * @adapter: 4219 * 4220 * Fire a link status change interrupt to start the watchdog. 4221 **/ 4222 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4223 { 4224 struct e1000_hw *hw = &adapter->hw; 4225 4226 if (adapter->msix_entries) 4227 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4228 else 4229 ew32(ICS, E1000_ICS_LSC); 4230 } 4231 4232 void e1000e_up(struct e1000_adapter *adapter) 4233 { 4234 /* hardware has been reset, we need to reload some things */ 4235 e1000_configure(adapter); 4236 4237 clear_bit(__E1000_DOWN, &adapter->state); 4238 4239 if (adapter->msix_entries) 4240 e1000_configure_msix(adapter); 4241 e1000_irq_enable(adapter); 4242 4243 netif_start_queue(adapter->netdev); 4244 4245 e1000e_trigger_lsc(adapter); 4246 } 4247 4248 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4249 { 4250 struct e1000_hw *hw = &adapter->hw; 4251 4252 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4253 return; 4254 4255 /* flush pending descriptor writebacks to memory */ 4256 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4257 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4258 4259 /* execute the writes immediately */ 4260 e1e_flush(); 4261 4262 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4263 * write is successful 4264 */ 4265 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4266 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4267 4268 /* execute the writes immediately */ 4269 e1e_flush(); 4270 } 4271 4272 static void e1000e_update_stats(struct e1000_adapter *adapter); 4273 4274 /** 4275 * e1000e_down - quiesce the device and optionally reset the hardware 4276 * @adapter: board private structure 4277 * @reset: boolean flag to reset the hardware or not 4278 */ 4279 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4280 { 4281 struct net_device *netdev = adapter->netdev; 4282 struct e1000_hw *hw = &adapter->hw; 4283 u32 tctl, rctl; 4284 4285 /* signal that we're down so the interrupt handler does not 4286 * reschedule our watchdog timer 4287 */ 4288 set_bit(__E1000_DOWN, &adapter->state); 4289 4290 netif_carrier_off(netdev); 4291 4292 /* disable receives in the hardware */ 4293 rctl = er32(RCTL); 4294 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4295 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4296 /* flush and sleep below */ 4297 4298 netif_stop_queue(netdev); 4299 4300 /* disable transmits in the hardware */ 4301 tctl = er32(TCTL); 4302 tctl &= ~E1000_TCTL_EN; 4303 ew32(TCTL, tctl); 4304 4305 /* flush both disables and wait for them to finish */ 4306 e1e_flush(); 4307 usleep_range(10000, 20000); 4308 4309 e1000_irq_disable(adapter); 4310 4311 napi_synchronize(&adapter->napi); 4312 4313 del_timer_sync(&adapter->watchdog_timer); 4314 del_timer_sync(&adapter->phy_info_timer); 4315 4316 spin_lock(&adapter->stats64_lock); 4317 e1000e_update_stats(adapter); 4318 spin_unlock(&adapter->stats64_lock); 4319 4320 e1000e_flush_descriptors(adapter); 4321 4322 adapter->link_speed = 0; 4323 adapter->link_duplex = 0; 4324 4325 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4326 if ((hw->mac.type >= e1000_pch2lan) && 4327 (adapter->netdev->mtu > ETH_DATA_LEN) && 4328 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4329 e_dbg("failed to disable jumbo frame workaround mode\n"); 4330 4331 if (!pci_channel_offline(adapter->pdev)) { 4332 if (reset) 4333 e1000e_reset(adapter); 4334 else if (hw->mac.type >= e1000_pch_spt) 4335 e1000_flush_desc_rings(adapter); 4336 } 4337 e1000_clean_tx_ring(adapter->tx_ring); 4338 e1000_clean_rx_ring(adapter->rx_ring); 4339 } 4340 4341 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4342 { 4343 might_sleep(); 4344 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4345 usleep_range(1000, 2000); 4346 e1000e_down(adapter, true); 4347 e1000e_up(adapter); 4348 clear_bit(__E1000_RESETTING, &adapter->state); 4349 } 4350 4351 /** 4352 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4353 * @hw: pointer to the HW structure 4354 * @systim: time value read, sanitized and returned 4355 * 4356 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4357 * check to see that the time is incrementing at a reasonable 4358 * rate and is a multiple of incvalue. 4359 **/ 4360 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim) 4361 { 4362 u64 time_delta, rem, temp; 4363 u64 systim_next; 4364 u32 incvalue; 4365 int i; 4366 4367 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4368 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4369 /* latch SYSTIMH on read of SYSTIML */ 4370 systim_next = (u64)er32(SYSTIML); 4371 systim_next |= (u64)er32(SYSTIMH) << 32; 4372 4373 time_delta = systim_next - systim; 4374 temp = time_delta; 4375 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4376 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4377 4378 systim = systim_next; 4379 4380 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4381 break; 4382 } 4383 4384 return systim; 4385 } 4386 4387 /** 4388 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4389 * @cc: cyclecounter structure 4390 **/ 4391 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4392 { 4393 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4394 cc); 4395 struct e1000_hw *hw = &adapter->hw; 4396 u32 systimel, systimeh; 4397 u64 systim; 4398 /* SYSTIMH latching upon SYSTIML read does not work well. 4399 * This means that if SYSTIML overflows after we read it but before 4400 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4401 * will experience a huge non linear increment in the systime value 4402 * to fix that we test for overflow and if true, we re-read systime. 4403 */ 4404 systimel = er32(SYSTIML); 4405 systimeh = er32(SYSTIMH); 4406 /* Is systimel is so large that overflow is possible? */ 4407 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4408 u32 systimel_2 = er32(SYSTIML); 4409 if (systimel > systimel_2) { 4410 /* There was an overflow, read again SYSTIMH, and use 4411 * systimel_2 4412 */ 4413 systimeh = er32(SYSTIMH); 4414 systimel = systimel_2; 4415 } 4416 } 4417 systim = (u64)systimel; 4418 systim |= (u64)systimeh << 32; 4419 4420 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4421 systim = e1000e_sanitize_systim(hw, systim); 4422 4423 return systim; 4424 } 4425 4426 /** 4427 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4428 * @adapter: board private structure to initialize 4429 * 4430 * e1000_sw_init initializes the Adapter private data structure. 4431 * Fields are initialized based on PCI device information and 4432 * OS network device settings (MTU size). 4433 **/ 4434 static int e1000_sw_init(struct e1000_adapter *adapter) 4435 { 4436 struct net_device *netdev = adapter->netdev; 4437 4438 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4439 adapter->rx_ps_bsize0 = 128; 4440 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4441 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4442 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4443 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4444 4445 spin_lock_init(&adapter->stats64_lock); 4446 4447 e1000e_set_interrupt_capability(adapter); 4448 4449 if (e1000_alloc_queues(adapter)) 4450 return -ENOMEM; 4451 4452 /* Setup hardware time stamping cyclecounter */ 4453 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4454 adapter->cc.read = e1000e_cyclecounter_read; 4455 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4456 adapter->cc.mult = 1; 4457 /* cc.shift set in e1000e_get_base_tininca() */ 4458 4459 spin_lock_init(&adapter->systim_lock); 4460 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4461 } 4462 4463 /* Explicitly disable IRQ since the NIC can be in any state. */ 4464 e1000_irq_disable(adapter); 4465 4466 set_bit(__E1000_DOWN, &adapter->state); 4467 return 0; 4468 } 4469 4470 /** 4471 * e1000_intr_msi_test - Interrupt Handler 4472 * @irq: interrupt number 4473 * @data: pointer to a network interface device structure 4474 **/ 4475 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4476 { 4477 struct net_device *netdev = data; 4478 struct e1000_adapter *adapter = netdev_priv(netdev); 4479 struct e1000_hw *hw = &adapter->hw; 4480 u32 icr = er32(ICR); 4481 4482 e_dbg("icr is %08X\n", icr); 4483 if (icr & E1000_ICR_RXSEQ) { 4484 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4485 /* Force memory writes to complete before acknowledging the 4486 * interrupt is handled. 4487 */ 4488 wmb(); 4489 } 4490 4491 return IRQ_HANDLED; 4492 } 4493 4494 /** 4495 * e1000_test_msi_interrupt - Returns 0 for successful test 4496 * @adapter: board private struct 4497 * 4498 * code flow taken from tg3.c 4499 **/ 4500 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4501 { 4502 struct net_device *netdev = adapter->netdev; 4503 struct e1000_hw *hw = &adapter->hw; 4504 int err; 4505 4506 /* poll_enable hasn't been called yet, so don't need disable */ 4507 /* clear any pending events */ 4508 er32(ICR); 4509 4510 /* free the real vector and request a test handler */ 4511 e1000_free_irq(adapter); 4512 e1000e_reset_interrupt_capability(adapter); 4513 4514 /* Assume that the test fails, if it succeeds then the test 4515 * MSI irq handler will unset this flag 4516 */ 4517 adapter->flags |= FLAG_MSI_TEST_FAILED; 4518 4519 err = pci_enable_msi(adapter->pdev); 4520 if (err) 4521 goto msi_test_failed; 4522 4523 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4524 netdev->name, netdev); 4525 if (err) { 4526 pci_disable_msi(adapter->pdev); 4527 goto msi_test_failed; 4528 } 4529 4530 /* Force memory writes to complete before enabling and firing an 4531 * interrupt. 4532 */ 4533 wmb(); 4534 4535 e1000_irq_enable(adapter); 4536 4537 /* fire an unusual interrupt on the test handler */ 4538 ew32(ICS, E1000_ICS_RXSEQ); 4539 e1e_flush(); 4540 msleep(100); 4541 4542 e1000_irq_disable(adapter); 4543 4544 rmb(); /* read flags after interrupt has been fired */ 4545 4546 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4547 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4548 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4549 } else { 4550 e_dbg("MSI interrupt test succeeded!\n"); 4551 } 4552 4553 free_irq(adapter->pdev->irq, netdev); 4554 pci_disable_msi(adapter->pdev); 4555 4556 msi_test_failed: 4557 e1000e_set_interrupt_capability(adapter); 4558 return e1000_request_irq(adapter); 4559 } 4560 4561 /** 4562 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4563 * @adapter: board private struct 4564 * 4565 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4566 **/ 4567 static int e1000_test_msi(struct e1000_adapter *adapter) 4568 { 4569 int err; 4570 u16 pci_cmd; 4571 4572 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4573 return 0; 4574 4575 /* disable SERR in case the MSI write causes a master abort */ 4576 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4577 if (pci_cmd & PCI_COMMAND_SERR) 4578 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4579 pci_cmd & ~PCI_COMMAND_SERR); 4580 4581 err = e1000_test_msi_interrupt(adapter); 4582 4583 /* re-enable SERR */ 4584 if (pci_cmd & PCI_COMMAND_SERR) { 4585 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4586 pci_cmd |= PCI_COMMAND_SERR; 4587 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4588 } 4589 4590 return err; 4591 } 4592 4593 /** 4594 * e1000e_open - Called when a network interface is made active 4595 * @netdev: network interface device structure 4596 * 4597 * Returns 0 on success, negative value on failure 4598 * 4599 * The open entry point is called when a network interface is made 4600 * active by the system (IFF_UP). At this point all resources needed 4601 * for transmit and receive operations are allocated, the interrupt 4602 * handler is registered with the OS, the watchdog timer is started, 4603 * and the stack is notified that the interface is ready. 4604 **/ 4605 int e1000e_open(struct net_device *netdev) 4606 { 4607 struct e1000_adapter *adapter = netdev_priv(netdev); 4608 struct e1000_hw *hw = &adapter->hw; 4609 struct pci_dev *pdev = adapter->pdev; 4610 int err; 4611 4612 /* disallow open during test */ 4613 if (test_bit(__E1000_TESTING, &adapter->state)) 4614 return -EBUSY; 4615 4616 pm_runtime_get_sync(&pdev->dev); 4617 4618 netif_carrier_off(netdev); 4619 4620 /* allocate transmit descriptors */ 4621 err = e1000e_setup_tx_resources(adapter->tx_ring); 4622 if (err) 4623 goto err_setup_tx; 4624 4625 /* allocate receive descriptors */ 4626 err = e1000e_setup_rx_resources(adapter->rx_ring); 4627 if (err) 4628 goto err_setup_rx; 4629 4630 /* If AMT is enabled, let the firmware know that the network 4631 * interface is now open and reset the part to a known state. 4632 */ 4633 if (adapter->flags & FLAG_HAS_AMT) { 4634 e1000e_get_hw_control(adapter); 4635 e1000e_reset(adapter); 4636 } 4637 4638 e1000e_power_up_phy(adapter); 4639 4640 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4641 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4642 e1000_update_mng_vlan(adapter); 4643 4644 /* DMA latency requirement to workaround jumbo issue */ 4645 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4646 PM_QOS_DEFAULT_VALUE); 4647 4648 /* before we allocate an interrupt, we must be ready to handle it. 4649 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4650 * as soon as we call pci_request_irq, so we have to setup our 4651 * clean_rx handler before we do so. 4652 */ 4653 e1000_configure(adapter); 4654 4655 err = e1000_request_irq(adapter); 4656 if (err) 4657 goto err_req_irq; 4658 4659 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4660 * ignore e1000e MSI messages, which means we need to test our MSI 4661 * interrupt now 4662 */ 4663 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4664 err = e1000_test_msi(adapter); 4665 if (err) { 4666 e_err("Interrupt allocation failed\n"); 4667 goto err_req_irq; 4668 } 4669 } 4670 4671 /* From here on the code is the same as e1000e_up() */ 4672 clear_bit(__E1000_DOWN, &adapter->state); 4673 4674 napi_enable(&adapter->napi); 4675 4676 e1000_irq_enable(adapter); 4677 4678 adapter->tx_hang_recheck = false; 4679 netif_start_queue(netdev); 4680 4681 hw->mac.get_link_status = true; 4682 pm_runtime_put(&pdev->dev); 4683 4684 e1000e_trigger_lsc(adapter); 4685 4686 return 0; 4687 4688 err_req_irq: 4689 pm_qos_remove_request(&adapter->pm_qos_req); 4690 e1000e_release_hw_control(adapter); 4691 e1000_power_down_phy(adapter); 4692 e1000e_free_rx_resources(adapter->rx_ring); 4693 err_setup_rx: 4694 e1000e_free_tx_resources(adapter->tx_ring); 4695 err_setup_tx: 4696 e1000e_reset(adapter); 4697 pm_runtime_put_sync(&pdev->dev); 4698 4699 return err; 4700 } 4701 4702 /** 4703 * e1000e_close - Disables a network interface 4704 * @netdev: network interface device structure 4705 * 4706 * Returns 0, this is not allowed to fail 4707 * 4708 * The close entry point is called when an interface is de-activated 4709 * by the OS. The hardware is still under the drivers control, but 4710 * needs to be disabled. A global MAC reset is issued to stop the 4711 * hardware, and all transmit and receive resources are freed. 4712 **/ 4713 int e1000e_close(struct net_device *netdev) 4714 { 4715 struct e1000_adapter *adapter = netdev_priv(netdev); 4716 struct pci_dev *pdev = adapter->pdev; 4717 int count = E1000_CHECK_RESET_COUNT; 4718 4719 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4720 usleep_range(10000, 20000); 4721 4722 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4723 4724 pm_runtime_get_sync(&pdev->dev); 4725 4726 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4727 e1000e_down(adapter, true); 4728 e1000_free_irq(adapter); 4729 4730 /* Link status message must follow this format */ 4731 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4732 } 4733 4734 napi_disable(&adapter->napi); 4735 4736 e1000e_free_tx_resources(adapter->tx_ring); 4737 e1000e_free_rx_resources(adapter->rx_ring); 4738 4739 /* kill manageability vlan ID if supported, but not if a vlan with 4740 * the same ID is registered on the host OS (let 8021q kill it) 4741 */ 4742 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4743 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4744 adapter->mng_vlan_id); 4745 4746 /* If AMT is enabled, let the firmware know that the network 4747 * interface is now closed 4748 */ 4749 if ((adapter->flags & FLAG_HAS_AMT) && 4750 !test_bit(__E1000_TESTING, &adapter->state)) 4751 e1000e_release_hw_control(adapter); 4752 4753 pm_qos_remove_request(&adapter->pm_qos_req); 4754 4755 pm_runtime_put_sync(&pdev->dev); 4756 4757 return 0; 4758 } 4759 4760 /** 4761 * e1000_set_mac - Change the Ethernet Address of the NIC 4762 * @netdev: network interface device structure 4763 * @p: pointer to an address structure 4764 * 4765 * Returns 0 on success, negative on failure 4766 **/ 4767 static int e1000_set_mac(struct net_device *netdev, void *p) 4768 { 4769 struct e1000_adapter *adapter = netdev_priv(netdev); 4770 struct e1000_hw *hw = &adapter->hw; 4771 struct sockaddr *addr = p; 4772 4773 if (!is_valid_ether_addr(addr->sa_data)) 4774 return -EADDRNOTAVAIL; 4775 4776 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4777 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4778 4779 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4780 4781 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4782 /* activate the work around */ 4783 e1000e_set_laa_state_82571(&adapter->hw, 1); 4784 4785 /* Hold a copy of the LAA in RAR[14] This is done so that 4786 * between the time RAR[0] gets clobbered and the time it 4787 * gets fixed (in e1000_watchdog), the actual LAA is in one 4788 * of the RARs and no incoming packets directed to this port 4789 * are dropped. Eventually the LAA will be in RAR[0] and 4790 * RAR[14] 4791 */ 4792 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4793 adapter->hw.mac.rar_entry_count - 1); 4794 } 4795 4796 return 0; 4797 } 4798 4799 /** 4800 * e1000e_update_phy_task - work thread to update phy 4801 * @work: pointer to our work struct 4802 * 4803 * this worker thread exists because we must acquire a 4804 * semaphore to read the phy, which we could msleep while 4805 * waiting for it, and we can't msleep in a timer. 4806 **/ 4807 static void e1000e_update_phy_task(struct work_struct *work) 4808 { 4809 struct e1000_adapter *adapter = container_of(work, 4810 struct e1000_adapter, 4811 update_phy_task); 4812 struct e1000_hw *hw = &adapter->hw; 4813 4814 if (test_bit(__E1000_DOWN, &adapter->state)) 4815 return; 4816 4817 e1000_get_phy_info(hw); 4818 4819 /* Enable EEE on 82579 after link up */ 4820 if (hw->phy.type >= e1000_phy_82579) 4821 e1000_set_eee_pchlan(hw); 4822 } 4823 4824 /** 4825 * e1000_update_phy_info - timre call-back to update PHY info 4826 * @data: pointer to adapter cast into an unsigned long 4827 * 4828 * Need to wait a few seconds after link up to get diagnostic information from 4829 * the phy 4830 **/ 4831 static void e1000_update_phy_info(struct timer_list *t) 4832 { 4833 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4834 4835 if (test_bit(__E1000_DOWN, &adapter->state)) 4836 return; 4837 4838 schedule_work(&adapter->update_phy_task); 4839 } 4840 4841 /** 4842 * e1000e_update_phy_stats - Update the PHY statistics counters 4843 * @adapter: board private structure 4844 * 4845 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4846 **/ 4847 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4848 { 4849 struct e1000_hw *hw = &adapter->hw; 4850 s32 ret_val; 4851 u16 phy_data; 4852 4853 ret_val = hw->phy.ops.acquire(hw); 4854 if (ret_val) 4855 return; 4856 4857 /* A page set is expensive so check if already on desired page. 4858 * If not, set to the page with the PHY status registers. 4859 */ 4860 hw->phy.addr = 1; 4861 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4862 &phy_data); 4863 if (ret_val) 4864 goto release; 4865 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4866 ret_val = hw->phy.ops.set_page(hw, 4867 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4868 if (ret_val) 4869 goto release; 4870 } 4871 4872 /* Single Collision Count */ 4873 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4874 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4875 if (!ret_val) 4876 adapter->stats.scc += phy_data; 4877 4878 /* Excessive Collision Count */ 4879 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4880 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4881 if (!ret_val) 4882 adapter->stats.ecol += phy_data; 4883 4884 /* Multiple Collision Count */ 4885 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4886 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4887 if (!ret_val) 4888 adapter->stats.mcc += phy_data; 4889 4890 /* Late Collision Count */ 4891 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4892 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4893 if (!ret_val) 4894 adapter->stats.latecol += phy_data; 4895 4896 /* Collision Count - also used for adaptive IFS */ 4897 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4899 if (!ret_val) 4900 hw->mac.collision_delta = phy_data; 4901 4902 /* Defer Count */ 4903 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4905 if (!ret_val) 4906 adapter->stats.dc += phy_data; 4907 4908 /* Transmit with no CRS */ 4909 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4911 if (!ret_val) 4912 adapter->stats.tncrs += phy_data; 4913 4914 release: 4915 hw->phy.ops.release(hw); 4916 } 4917 4918 /** 4919 * e1000e_update_stats - Update the board statistics counters 4920 * @adapter: board private structure 4921 **/ 4922 static void e1000e_update_stats(struct e1000_adapter *adapter) 4923 { 4924 struct net_device *netdev = adapter->netdev; 4925 struct e1000_hw *hw = &adapter->hw; 4926 struct pci_dev *pdev = adapter->pdev; 4927 4928 /* Prevent stats update while adapter is being reset, or if the pci 4929 * connection is down. 4930 */ 4931 if (adapter->link_speed == 0) 4932 return; 4933 if (pci_channel_offline(pdev)) 4934 return; 4935 4936 adapter->stats.crcerrs += er32(CRCERRS); 4937 adapter->stats.gprc += er32(GPRC); 4938 adapter->stats.gorc += er32(GORCL); 4939 er32(GORCH); /* Clear gorc */ 4940 adapter->stats.bprc += er32(BPRC); 4941 adapter->stats.mprc += er32(MPRC); 4942 adapter->stats.roc += er32(ROC); 4943 4944 adapter->stats.mpc += er32(MPC); 4945 4946 /* Half-duplex statistics */ 4947 if (adapter->link_duplex == HALF_DUPLEX) { 4948 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4949 e1000e_update_phy_stats(adapter); 4950 } else { 4951 adapter->stats.scc += er32(SCC); 4952 adapter->stats.ecol += er32(ECOL); 4953 adapter->stats.mcc += er32(MCC); 4954 adapter->stats.latecol += er32(LATECOL); 4955 adapter->stats.dc += er32(DC); 4956 4957 hw->mac.collision_delta = er32(COLC); 4958 4959 if ((hw->mac.type != e1000_82574) && 4960 (hw->mac.type != e1000_82583)) 4961 adapter->stats.tncrs += er32(TNCRS); 4962 } 4963 adapter->stats.colc += hw->mac.collision_delta; 4964 } 4965 4966 adapter->stats.xonrxc += er32(XONRXC); 4967 adapter->stats.xontxc += er32(XONTXC); 4968 adapter->stats.xoffrxc += er32(XOFFRXC); 4969 adapter->stats.xofftxc += er32(XOFFTXC); 4970 adapter->stats.gptc += er32(GPTC); 4971 adapter->stats.gotc += er32(GOTCL); 4972 er32(GOTCH); /* Clear gotc */ 4973 adapter->stats.rnbc += er32(RNBC); 4974 adapter->stats.ruc += er32(RUC); 4975 4976 adapter->stats.mptc += er32(MPTC); 4977 adapter->stats.bptc += er32(BPTC); 4978 4979 /* used for adaptive IFS */ 4980 4981 hw->mac.tx_packet_delta = er32(TPT); 4982 adapter->stats.tpt += hw->mac.tx_packet_delta; 4983 4984 adapter->stats.algnerrc += er32(ALGNERRC); 4985 adapter->stats.rxerrc += er32(RXERRC); 4986 adapter->stats.cexterr += er32(CEXTERR); 4987 adapter->stats.tsctc += er32(TSCTC); 4988 adapter->stats.tsctfc += er32(TSCTFC); 4989 4990 /* Fill out the OS statistics structure */ 4991 netdev->stats.multicast = adapter->stats.mprc; 4992 netdev->stats.collisions = adapter->stats.colc; 4993 4994 /* Rx Errors */ 4995 4996 /* RLEC on some newer hardware can be incorrect so build 4997 * our own version based on RUC and ROC 4998 */ 4999 netdev->stats.rx_errors = adapter->stats.rxerrc + 5000 adapter->stats.crcerrs + adapter->stats.algnerrc + 5001 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5002 netdev->stats.rx_length_errors = adapter->stats.ruc + 5003 adapter->stats.roc; 5004 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5005 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5006 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5007 5008 /* Tx Errors */ 5009 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5010 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5011 netdev->stats.tx_window_errors = adapter->stats.latecol; 5012 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5013 5014 /* Tx Dropped needs to be maintained elsewhere */ 5015 5016 /* Management Stats */ 5017 adapter->stats.mgptc += er32(MGTPTC); 5018 adapter->stats.mgprc += er32(MGTPRC); 5019 adapter->stats.mgpdc += er32(MGTPDC); 5020 5021 /* Correctable ECC Errors */ 5022 if (hw->mac.type >= e1000_pch_lpt) { 5023 u32 pbeccsts = er32(PBECCSTS); 5024 5025 adapter->corr_errors += 5026 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5027 adapter->uncorr_errors += 5028 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5029 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5030 } 5031 } 5032 5033 /** 5034 * e1000_phy_read_status - Update the PHY register status snapshot 5035 * @adapter: board private structure 5036 **/ 5037 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5038 { 5039 struct e1000_hw *hw = &adapter->hw; 5040 struct e1000_phy_regs *phy = &adapter->phy_regs; 5041 5042 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5043 (er32(STATUS) & E1000_STATUS_LU) && 5044 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5045 int ret_val; 5046 5047 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5048 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5049 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5050 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5051 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5052 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5053 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5054 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5055 if (ret_val) 5056 e_warn("Error reading PHY register\n"); 5057 } else { 5058 /* Do not read PHY registers if link is not up 5059 * Set values to typical power-on defaults 5060 */ 5061 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5062 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5063 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5064 BMSR_ERCAP); 5065 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5066 ADVERTISE_ALL | ADVERTISE_CSMA); 5067 phy->lpa = 0; 5068 phy->expansion = EXPANSION_ENABLENPAGE; 5069 phy->ctrl1000 = ADVERTISE_1000FULL; 5070 phy->stat1000 = 0; 5071 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5072 } 5073 } 5074 5075 static void e1000_print_link_info(struct e1000_adapter *adapter) 5076 { 5077 struct e1000_hw *hw = &adapter->hw; 5078 u32 ctrl = er32(CTRL); 5079 5080 /* Link status message must follow this format for user tools */ 5081 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5082 adapter->netdev->name, adapter->link_speed, 5083 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5084 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5085 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5086 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5087 } 5088 5089 static bool e1000e_has_link(struct e1000_adapter *adapter) 5090 { 5091 struct e1000_hw *hw = &adapter->hw; 5092 bool link_active = false; 5093 s32 ret_val = 0; 5094 5095 /* get_link_status is set on LSC (link status) interrupt or 5096 * Rx sequence error interrupt. get_link_status will stay 5097 * true until the check_for_link establishes link 5098 * for copper adapters ONLY 5099 */ 5100 switch (hw->phy.media_type) { 5101 case e1000_media_type_copper: 5102 if (hw->mac.get_link_status) { 5103 ret_val = hw->mac.ops.check_for_link(hw); 5104 link_active = ret_val > 0; 5105 } else { 5106 link_active = true; 5107 } 5108 break; 5109 case e1000_media_type_fiber: 5110 ret_val = hw->mac.ops.check_for_link(hw); 5111 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5112 break; 5113 case e1000_media_type_internal_serdes: 5114 ret_val = hw->mac.ops.check_for_link(hw); 5115 link_active = hw->mac.serdes_has_link; 5116 break; 5117 default: 5118 case e1000_media_type_unknown: 5119 break; 5120 } 5121 5122 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5123 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5124 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5125 e_info("Gigabit has been disabled, downgrading speed\n"); 5126 } 5127 5128 return link_active; 5129 } 5130 5131 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5132 { 5133 /* make sure the receive unit is started */ 5134 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5135 (adapter->flags & FLAG_RESTART_NOW)) { 5136 struct e1000_hw *hw = &adapter->hw; 5137 u32 rctl = er32(RCTL); 5138 5139 ew32(RCTL, rctl | E1000_RCTL_EN); 5140 adapter->flags &= ~FLAG_RESTART_NOW; 5141 } 5142 } 5143 5144 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5145 { 5146 struct e1000_hw *hw = &adapter->hw; 5147 5148 /* With 82574 controllers, PHY needs to be checked periodically 5149 * for hung state and reset, if two calls return true 5150 */ 5151 if (e1000_check_phy_82574(hw)) 5152 adapter->phy_hang_count++; 5153 else 5154 adapter->phy_hang_count = 0; 5155 5156 if (adapter->phy_hang_count > 1) { 5157 adapter->phy_hang_count = 0; 5158 e_dbg("PHY appears hung - resetting\n"); 5159 schedule_work(&adapter->reset_task); 5160 } 5161 } 5162 5163 /** 5164 * e1000_watchdog - Timer Call-back 5165 * @data: pointer to adapter cast into an unsigned long 5166 **/ 5167 static void e1000_watchdog(struct timer_list *t) 5168 { 5169 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5170 5171 /* Do the rest outside of interrupt context */ 5172 schedule_work(&adapter->watchdog_task); 5173 5174 /* TODO: make this use queue_delayed_work() */ 5175 } 5176 5177 static void e1000_watchdog_task(struct work_struct *work) 5178 { 5179 struct e1000_adapter *adapter = container_of(work, 5180 struct e1000_adapter, 5181 watchdog_task); 5182 struct net_device *netdev = adapter->netdev; 5183 struct e1000_mac_info *mac = &adapter->hw.mac; 5184 struct e1000_phy_info *phy = &adapter->hw.phy; 5185 struct e1000_ring *tx_ring = adapter->tx_ring; 5186 struct e1000_hw *hw = &adapter->hw; 5187 u32 link, tctl; 5188 5189 if (test_bit(__E1000_DOWN, &adapter->state)) 5190 return; 5191 5192 link = e1000e_has_link(adapter); 5193 if ((netif_carrier_ok(netdev)) && link) { 5194 /* Cancel scheduled suspend requests. */ 5195 pm_runtime_resume(netdev->dev.parent); 5196 5197 e1000e_enable_receives(adapter); 5198 goto link_up; 5199 } 5200 5201 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5202 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5203 e1000_update_mng_vlan(adapter); 5204 5205 if (link) { 5206 if (!netif_carrier_ok(netdev)) { 5207 bool txb2b = true; 5208 5209 /* Cancel scheduled suspend requests. */ 5210 pm_runtime_resume(netdev->dev.parent); 5211 5212 /* update snapshot of PHY registers on LSC */ 5213 e1000_phy_read_status(adapter); 5214 mac->ops.get_link_up_info(&adapter->hw, 5215 &adapter->link_speed, 5216 &adapter->link_duplex); 5217 e1000_print_link_info(adapter); 5218 5219 /* check if SmartSpeed worked */ 5220 e1000e_check_downshift(hw); 5221 if (phy->speed_downgraded) 5222 netdev_warn(netdev, 5223 "Link Speed was downgraded by SmartSpeed\n"); 5224 5225 /* On supported PHYs, check for duplex mismatch only 5226 * if link has autonegotiated at 10/100 half 5227 */ 5228 if ((hw->phy.type == e1000_phy_igp_3 || 5229 hw->phy.type == e1000_phy_bm) && 5230 hw->mac.autoneg && 5231 (adapter->link_speed == SPEED_10 || 5232 adapter->link_speed == SPEED_100) && 5233 (adapter->link_duplex == HALF_DUPLEX)) { 5234 u16 autoneg_exp; 5235 5236 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5237 5238 if (!(autoneg_exp & EXPANSION_NWAY)) 5239 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5240 } 5241 5242 /* adjust timeout factor according to speed/duplex */ 5243 adapter->tx_timeout_factor = 1; 5244 switch (adapter->link_speed) { 5245 case SPEED_10: 5246 txb2b = false; 5247 adapter->tx_timeout_factor = 16; 5248 break; 5249 case SPEED_100: 5250 txb2b = false; 5251 adapter->tx_timeout_factor = 10; 5252 break; 5253 } 5254 5255 /* workaround: re-program speed mode bit after 5256 * link-up event 5257 */ 5258 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5259 !txb2b) { 5260 u32 tarc0; 5261 5262 tarc0 = er32(TARC(0)); 5263 tarc0 &= ~SPEED_MODE_BIT; 5264 ew32(TARC(0), tarc0); 5265 } 5266 5267 /* disable TSO for pcie and 10/100 speeds, to avoid 5268 * some hardware issues 5269 */ 5270 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5271 switch (adapter->link_speed) { 5272 case SPEED_10: 5273 case SPEED_100: 5274 e_info("10/100 speed: disabling TSO\n"); 5275 netdev->features &= ~NETIF_F_TSO; 5276 netdev->features &= ~NETIF_F_TSO6; 5277 break; 5278 case SPEED_1000: 5279 netdev->features |= NETIF_F_TSO; 5280 netdev->features |= NETIF_F_TSO6; 5281 break; 5282 default: 5283 /* oops */ 5284 break; 5285 } 5286 } 5287 5288 /* enable transmits in the hardware, need to do this 5289 * after setting TARC(0) 5290 */ 5291 tctl = er32(TCTL); 5292 tctl |= E1000_TCTL_EN; 5293 ew32(TCTL, tctl); 5294 5295 /* Perform any post-link-up configuration before 5296 * reporting link up. 5297 */ 5298 if (phy->ops.cfg_on_link_up) 5299 phy->ops.cfg_on_link_up(hw); 5300 5301 netif_carrier_on(netdev); 5302 5303 if (!test_bit(__E1000_DOWN, &adapter->state)) 5304 mod_timer(&adapter->phy_info_timer, 5305 round_jiffies(jiffies + 2 * HZ)); 5306 } 5307 } else { 5308 if (netif_carrier_ok(netdev)) { 5309 adapter->link_speed = 0; 5310 adapter->link_duplex = 0; 5311 /* Link status message must follow this format */ 5312 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 5313 netif_carrier_off(netdev); 5314 if (!test_bit(__E1000_DOWN, &adapter->state)) 5315 mod_timer(&adapter->phy_info_timer, 5316 round_jiffies(jiffies + 2 * HZ)); 5317 5318 /* 8000ES2LAN requires a Rx packet buffer work-around 5319 * on link down event; reset the controller to flush 5320 * the Rx packet buffer. 5321 */ 5322 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5323 adapter->flags |= FLAG_RESTART_NOW; 5324 else 5325 pm_schedule_suspend(netdev->dev.parent, 5326 LINK_TIMEOUT); 5327 } 5328 } 5329 5330 link_up: 5331 spin_lock(&adapter->stats64_lock); 5332 e1000e_update_stats(adapter); 5333 5334 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5335 adapter->tpt_old = adapter->stats.tpt; 5336 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5337 adapter->colc_old = adapter->stats.colc; 5338 5339 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5340 adapter->gorc_old = adapter->stats.gorc; 5341 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5342 adapter->gotc_old = adapter->stats.gotc; 5343 spin_unlock(&adapter->stats64_lock); 5344 5345 /* If the link is lost the controller stops DMA, but 5346 * if there is queued Tx work it cannot be done. So 5347 * reset the controller to flush the Tx packet buffers. 5348 */ 5349 if (!netif_carrier_ok(netdev) && 5350 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5351 adapter->flags |= FLAG_RESTART_NOW; 5352 5353 /* If reset is necessary, do it outside of interrupt context. */ 5354 if (adapter->flags & FLAG_RESTART_NOW) { 5355 schedule_work(&adapter->reset_task); 5356 /* return immediately since reset is imminent */ 5357 return; 5358 } 5359 5360 e1000e_update_adaptive(&adapter->hw); 5361 5362 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5363 if (adapter->itr_setting == 4) { 5364 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5365 * Total asymmetrical Tx or Rx gets ITR=8000; 5366 * everyone else is between 2000-8000. 5367 */ 5368 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5369 u32 dif = (adapter->gotc > adapter->gorc ? 5370 adapter->gotc - adapter->gorc : 5371 adapter->gorc - adapter->gotc) / 10000; 5372 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5373 5374 e1000e_write_itr(adapter, itr); 5375 } 5376 5377 /* Cause software interrupt to ensure Rx ring is cleaned */ 5378 if (adapter->msix_entries) 5379 ew32(ICS, adapter->rx_ring->ims_val); 5380 else 5381 ew32(ICS, E1000_ICS_RXDMT0); 5382 5383 /* flush pending descriptors to memory before detecting Tx hang */ 5384 e1000e_flush_descriptors(adapter); 5385 5386 /* Force detection of hung controller every watchdog period */ 5387 adapter->detect_tx_hung = true; 5388 5389 /* With 82571 controllers, LAA may be overwritten due to controller 5390 * reset from the other port. Set the appropriate LAA in RAR[0] 5391 */ 5392 if (e1000e_get_laa_state_82571(hw)) 5393 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5394 5395 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5396 e1000e_check_82574_phy_workaround(adapter); 5397 5398 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5399 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5400 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5401 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5402 er32(RXSTMPH); 5403 adapter->rx_hwtstamp_cleared++; 5404 } else { 5405 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5406 } 5407 } 5408 5409 /* Reset the timer */ 5410 if (!test_bit(__E1000_DOWN, &adapter->state)) 5411 mod_timer(&adapter->watchdog_timer, 5412 round_jiffies(jiffies + 2 * HZ)); 5413 } 5414 5415 #define E1000_TX_FLAGS_CSUM 0x00000001 5416 #define E1000_TX_FLAGS_VLAN 0x00000002 5417 #define E1000_TX_FLAGS_TSO 0x00000004 5418 #define E1000_TX_FLAGS_IPV4 0x00000008 5419 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5420 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5421 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5422 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5423 5424 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5425 __be16 protocol) 5426 { 5427 struct e1000_context_desc *context_desc; 5428 struct e1000_buffer *buffer_info; 5429 unsigned int i; 5430 u32 cmd_length = 0; 5431 u16 ipcse = 0, mss; 5432 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5433 int err; 5434 5435 if (!skb_is_gso(skb)) 5436 return 0; 5437 5438 err = skb_cow_head(skb, 0); 5439 if (err < 0) 5440 return err; 5441 5442 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5443 mss = skb_shinfo(skb)->gso_size; 5444 if (protocol == htons(ETH_P_IP)) { 5445 struct iphdr *iph = ip_hdr(skb); 5446 iph->tot_len = 0; 5447 iph->check = 0; 5448 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5449 0, IPPROTO_TCP, 0); 5450 cmd_length = E1000_TXD_CMD_IP; 5451 ipcse = skb_transport_offset(skb) - 1; 5452 } else if (skb_is_gso_v6(skb)) { 5453 ipv6_hdr(skb)->payload_len = 0; 5454 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5455 &ipv6_hdr(skb)->daddr, 5456 0, IPPROTO_TCP, 0); 5457 ipcse = 0; 5458 } 5459 ipcss = skb_network_offset(skb); 5460 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5461 tucss = skb_transport_offset(skb); 5462 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5463 5464 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5465 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5466 5467 i = tx_ring->next_to_use; 5468 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5469 buffer_info = &tx_ring->buffer_info[i]; 5470 5471 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5472 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5473 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5474 context_desc->upper_setup.tcp_fields.tucss = tucss; 5475 context_desc->upper_setup.tcp_fields.tucso = tucso; 5476 context_desc->upper_setup.tcp_fields.tucse = 0; 5477 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5478 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5479 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5480 5481 buffer_info->time_stamp = jiffies; 5482 buffer_info->next_to_watch = i; 5483 5484 i++; 5485 if (i == tx_ring->count) 5486 i = 0; 5487 tx_ring->next_to_use = i; 5488 5489 return 1; 5490 } 5491 5492 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5493 __be16 protocol) 5494 { 5495 struct e1000_adapter *adapter = tx_ring->adapter; 5496 struct e1000_context_desc *context_desc; 5497 struct e1000_buffer *buffer_info; 5498 unsigned int i; 5499 u8 css; 5500 u32 cmd_len = E1000_TXD_CMD_DEXT; 5501 5502 if (skb->ip_summed != CHECKSUM_PARTIAL) 5503 return false; 5504 5505 switch (protocol) { 5506 case cpu_to_be16(ETH_P_IP): 5507 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5508 cmd_len |= E1000_TXD_CMD_TCP; 5509 break; 5510 case cpu_to_be16(ETH_P_IPV6): 5511 /* XXX not handling all IPV6 headers */ 5512 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5513 cmd_len |= E1000_TXD_CMD_TCP; 5514 break; 5515 default: 5516 if (unlikely(net_ratelimit())) 5517 e_warn("checksum_partial proto=%x!\n", 5518 be16_to_cpu(protocol)); 5519 break; 5520 } 5521 5522 css = skb_checksum_start_offset(skb); 5523 5524 i = tx_ring->next_to_use; 5525 buffer_info = &tx_ring->buffer_info[i]; 5526 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5527 5528 context_desc->lower_setup.ip_config = 0; 5529 context_desc->upper_setup.tcp_fields.tucss = css; 5530 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5531 context_desc->upper_setup.tcp_fields.tucse = 0; 5532 context_desc->tcp_seg_setup.data = 0; 5533 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5534 5535 buffer_info->time_stamp = jiffies; 5536 buffer_info->next_to_watch = i; 5537 5538 i++; 5539 if (i == tx_ring->count) 5540 i = 0; 5541 tx_ring->next_to_use = i; 5542 5543 return true; 5544 } 5545 5546 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5547 unsigned int first, unsigned int max_per_txd, 5548 unsigned int nr_frags) 5549 { 5550 struct e1000_adapter *adapter = tx_ring->adapter; 5551 struct pci_dev *pdev = adapter->pdev; 5552 struct e1000_buffer *buffer_info; 5553 unsigned int len = skb_headlen(skb); 5554 unsigned int offset = 0, size, count = 0, i; 5555 unsigned int f, bytecount, segs; 5556 5557 i = tx_ring->next_to_use; 5558 5559 while (len) { 5560 buffer_info = &tx_ring->buffer_info[i]; 5561 size = min(len, max_per_txd); 5562 5563 buffer_info->length = size; 5564 buffer_info->time_stamp = jiffies; 5565 buffer_info->next_to_watch = i; 5566 buffer_info->dma = dma_map_single(&pdev->dev, 5567 skb->data + offset, 5568 size, DMA_TO_DEVICE); 5569 buffer_info->mapped_as_page = false; 5570 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5571 goto dma_error; 5572 5573 len -= size; 5574 offset += size; 5575 count++; 5576 5577 if (len) { 5578 i++; 5579 if (i == tx_ring->count) 5580 i = 0; 5581 } 5582 } 5583 5584 for (f = 0; f < nr_frags; f++) { 5585 const struct skb_frag_struct *frag; 5586 5587 frag = &skb_shinfo(skb)->frags[f]; 5588 len = skb_frag_size(frag); 5589 offset = 0; 5590 5591 while (len) { 5592 i++; 5593 if (i == tx_ring->count) 5594 i = 0; 5595 5596 buffer_info = &tx_ring->buffer_info[i]; 5597 size = min(len, max_per_txd); 5598 5599 buffer_info->length = size; 5600 buffer_info->time_stamp = jiffies; 5601 buffer_info->next_to_watch = i; 5602 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5603 offset, size, 5604 DMA_TO_DEVICE); 5605 buffer_info->mapped_as_page = true; 5606 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5607 goto dma_error; 5608 5609 len -= size; 5610 offset += size; 5611 count++; 5612 } 5613 } 5614 5615 segs = skb_shinfo(skb)->gso_segs ? : 1; 5616 /* multiply data chunks by size of headers */ 5617 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5618 5619 tx_ring->buffer_info[i].skb = skb; 5620 tx_ring->buffer_info[i].segs = segs; 5621 tx_ring->buffer_info[i].bytecount = bytecount; 5622 tx_ring->buffer_info[first].next_to_watch = i; 5623 5624 return count; 5625 5626 dma_error: 5627 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5628 buffer_info->dma = 0; 5629 if (count) 5630 count--; 5631 5632 while (count--) { 5633 if (i == 0) 5634 i += tx_ring->count; 5635 i--; 5636 buffer_info = &tx_ring->buffer_info[i]; 5637 e1000_put_txbuf(tx_ring, buffer_info, true); 5638 } 5639 5640 return 0; 5641 } 5642 5643 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5644 { 5645 struct e1000_adapter *adapter = tx_ring->adapter; 5646 struct e1000_tx_desc *tx_desc = NULL; 5647 struct e1000_buffer *buffer_info; 5648 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5649 unsigned int i; 5650 5651 if (tx_flags & E1000_TX_FLAGS_TSO) { 5652 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5653 E1000_TXD_CMD_TSE; 5654 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5655 5656 if (tx_flags & E1000_TX_FLAGS_IPV4) 5657 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5658 } 5659 5660 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5661 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5662 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5663 } 5664 5665 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5666 txd_lower |= E1000_TXD_CMD_VLE; 5667 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5668 } 5669 5670 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5671 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5672 5673 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5674 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5675 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5676 } 5677 5678 i = tx_ring->next_to_use; 5679 5680 do { 5681 buffer_info = &tx_ring->buffer_info[i]; 5682 tx_desc = E1000_TX_DESC(*tx_ring, i); 5683 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5684 tx_desc->lower.data = cpu_to_le32(txd_lower | 5685 buffer_info->length); 5686 tx_desc->upper.data = cpu_to_le32(txd_upper); 5687 5688 i++; 5689 if (i == tx_ring->count) 5690 i = 0; 5691 } while (--count > 0); 5692 5693 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5694 5695 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5696 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5697 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5698 5699 /* Force memory writes to complete before letting h/w 5700 * know there are new descriptors to fetch. (Only 5701 * applicable for weak-ordered memory model archs, 5702 * such as IA-64). 5703 */ 5704 wmb(); 5705 5706 tx_ring->next_to_use = i; 5707 } 5708 5709 #define MINIMUM_DHCP_PACKET_SIZE 282 5710 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5711 struct sk_buff *skb) 5712 { 5713 struct e1000_hw *hw = &adapter->hw; 5714 u16 length, offset; 5715 5716 if (skb_vlan_tag_present(skb) && 5717 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5718 (adapter->hw.mng_cookie.status & 5719 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5720 return 0; 5721 5722 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5723 return 0; 5724 5725 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5726 return 0; 5727 5728 { 5729 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5730 struct udphdr *udp; 5731 5732 if (ip->protocol != IPPROTO_UDP) 5733 return 0; 5734 5735 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5736 if (ntohs(udp->dest) != 67) 5737 return 0; 5738 5739 offset = (u8 *)udp + 8 - skb->data; 5740 length = skb->len - offset; 5741 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5742 } 5743 5744 return 0; 5745 } 5746 5747 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5748 { 5749 struct e1000_adapter *adapter = tx_ring->adapter; 5750 5751 netif_stop_queue(adapter->netdev); 5752 /* Herbert's original patch had: 5753 * smp_mb__after_netif_stop_queue(); 5754 * but since that doesn't exist yet, just open code it. 5755 */ 5756 smp_mb(); 5757 5758 /* We need to check again in a case another CPU has just 5759 * made room available. 5760 */ 5761 if (e1000_desc_unused(tx_ring) < size) 5762 return -EBUSY; 5763 5764 /* A reprieve! */ 5765 netif_start_queue(adapter->netdev); 5766 ++adapter->restart_queue; 5767 return 0; 5768 } 5769 5770 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5771 { 5772 BUG_ON(size > tx_ring->count); 5773 5774 if (e1000_desc_unused(tx_ring) >= size) 5775 return 0; 5776 return __e1000_maybe_stop_tx(tx_ring, size); 5777 } 5778 5779 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5780 struct net_device *netdev) 5781 { 5782 struct e1000_adapter *adapter = netdev_priv(netdev); 5783 struct e1000_ring *tx_ring = adapter->tx_ring; 5784 unsigned int first; 5785 unsigned int tx_flags = 0; 5786 unsigned int len = skb_headlen(skb); 5787 unsigned int nr_frags; 5788 unsigned int mss; 5789 int count = 0; 5790 int tso; 5791 unsigned int f; 5792 __be16 protocol = vlan_get_protocol(skb); 5793 5794 if (test_bit(__E1000_DOWN, &adapter->state)) { 5795 dev_kfree_skb_any(skb); 5796 return NETDEV_TX_OK; 5797 } 5798 5799 if (skb->len <= 0) { 5800 dev_kfree_skb_any(skb); 5801 return NETDEV_TX_OK; 5802 } 5803 5804 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5805 * pad skb in order to meet this minimum size requirement 5806 */ 5807 if (skb_put_padto(skb, 17)) 5808 return NETDEV_TX_OK; 5809 5810 mss = skb_shinfo(skb)->gso_size; 5811 if (mss) { 5812 u8 hdr_len; 5813 5814 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5815 * points to just header, pull a few bytes of payload from 5816 * frags into skb->data 5817 */ 5818 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5819 /* we do this workaround for ES2LAN, but it is un-necessary, 5820 * avoiding it could save a lot of cycles 5821 */ 5822 if (skb->data_len && (hdr_len == len)) { 5823 unsigned int pull_size; 5824 5825 pull_size = min_t(unsigned int, 4, skb->data_len); 5826 if (!__pskb_pull_tail(skb, pull_size)) { 5827 e_err("__pskb_pull_tail failed.\n"); 5828 dev_kfree_skb_any(skb); 5829 return NETDEV_TX_OK; 5830 } 5831 len = skb_headlen(skb); 5832 } 5833 } 5834 5835 /* reserve a descriptor for the offload context */ 5836 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5837 count++; 5838 count++; 5839 5840 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5841 5842 nr_frags = skb_shinfo(skb)->nr_frags; 5843 for (f = 0; f < nr_frags; f++) 5844 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5845 adapter->tx_fifo_limit); 5846 5847 if (adapter->hw.mac.tx_pkt_filtering) 5848 e1000_transfer_dhcp_info(adapter, skb); 5849 5850 /* need: count + 2 desc gap to keep tail from touching 5851 * head, otherwise try next time 5852 */ 5853 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5854 return NETDEV_TX_BUSY; 5855 5856 if (skb_vlan_tag_present(skb)) { 5857 tx_flags |= E1000_TX_FLAGS_VLAN; 5858 tx_flags |= (skb_vlan_tag_get(skb) << 5859 E1000_TX_FLAGS_VLAN_SHIFT); 5860 } 5861 5862 first = tx_ring->next_to_use; 5863 5864 tso = e1000_tso(tx_ring, skb, protocol); 5865 if (tso < 0) { 5866 dev_kfree_skb_any(skb); 5867 return NETDEV_TX_OK; 5868 } 5869 5870 if (tso) 5871 tx_flags |= E1000_TX_FLAGS_TSO; 5872 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5873 tx_flags |= E1000_TX_FLAGS_CSUM; 5874 5875 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5876 * 82571 hardware supports TSO capabilities for IPv6 as well... 5877 * no longer assume, we must. 5878 */ 5879 if (protocol == htons(ETH_P_IP)) 5880 tx_flags |= E1000_TX_FLAGS_IPV4; 5881 5882 if (unlikely(skb->no_fcs)) 5883 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5884 5885 /* if count is 0 then mapping error has occurred */ 5886 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5887 nr_frags); 5888 if (count) { 5889 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5890 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5891 if (!adapter->tx_hwtstamp_skb) { 5892 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5893 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5894 adapter->tx_hwtstamp_skb = skb_get(skb); 5895 adapter->tx_hwtstamp_start = jiffies; 5896 schedule_work(&adapter->tx_hwtstamp_work); 5897 } else { 5898 adapter->tx_hwtstamp_skipped++; 5899 } 5900 } 5901 5902 skb_tx_timestamp(skb); 5903 5904 netdev_sent_queue(netdev, skb->len); 5905 e1000_tx_queue(tx_ring, tx_flags, count); 5906 /* Make sure there is space in the ring for the next send. */ 5907 e1000_maybe_stop_tx(tx_ring, 5908 (MAX_SKB_FRAGS * 5909 DIV_ROUND_UP(PAGE_SIZE, 5910 adapter->tx_fifo_limit) + 2)); 5911 5912 if (!skb->xmit_more || 5913 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5914 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5915 e1000e_update_tdt_wa(tx_ring, 5916 tx_ring->next_to_use); 5917 else 5918 writel(tx_ring->next_to_use, tx_ring->tail); 5919 5920 /* we need this if more than one processor can write 5921 * to our tail at a time, it synchronizes IO on 5922 *IA64/Altix systems 5923 */ 5924 mmiowb(); 5925 } 5926 } else { 5927 dev_kfree_skb_any(skb); 5928 tx_ring->buffer_info[first].time_stamp = 0; 5929 tx_ring->next_to_use = first; 5930 } 5931 5932 return NETDEV_TX_OK; 5933 } 5934 5935 /** 5936 * e1000_tx_timeout - Respond to a Tx Hang 5937 * @netdev: network interface device structure 5938 **/ 5939 static void e1000_tx_timeout(struct net_device *netdev) 5940 { 5941 struct e1000_adapter *adapter = netdev_priv(netdev); 5942 5943 /* Do the reset outside of interrupt context */ 5944 adapter->tx_timeout_count++; 5945 schedule_work(&adapter->reset_task); 5946 } 5947 5948 static void e1000_reset_task(struct work_struct *work) 5949 { 5950 struct e1000_adapter *adapter; 5951 adapter = container_of(work, struct e1000_adapter, reset_task); 5952 5953 /* don't run the task if already down */ 5954 if (test_bit(__E1000_DOWN, &adapter->state)) 5955 return; 5956 5957 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5958 e1000e_dump(adapter); 5959 e_err("Reset adapter unexpectedly\n"); 5960 } 5961 e1000e_reinit_locked(adapter); 5962 } 5963 5964 /** 5965 * e1000_get_stats64 - Get System Network Statistics 5966 * @netdev: network interface device structure 5967 * @stats: rtnl_link_stats64 pointer 5968 * 5969 * Returns the address of the device statistics structure. 5970 **/ 5971 void e1000e_get_stats64(struct net_device *netdev, 5972 struct rtnl_link_stats64 *stats) 5973 { 5974 struct e1000_adapter *adapter = netdev_priv(netdev); 5975 5976 spin_lock(&adapter->stats64_lock); 5977 e1000e_update_stats(adapter); 5978 /* Fill out the OS statistics structure */ 5979 stats->rx_bytes = adapter->stats.gorc; 5980 stats->rx_packets = adapter->stats.gprc; 5981 stats->tx_bytes = adapter->stats.gotc; 5982 stats->tx_packets = adapter->stats.gptc; 5983 stats->multicast = adapter->stats.mprc; 5984 stats->collisions = adapter->stats.colc; 5985 5986 /* Rx Errors */ 5987 5988 /* RLEC on some newer hardware can be incorrect so build 5989 * our own version based on RUC and ROC 5990 */ 5991 stats->rx_errors = adapter->stats.rxerrc + 5992 adapter->stats.crcerrs + adapter->stats.algnerrc + 5993 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5994 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5995 stats->rx_crc_errors = adapter->stats.crcerrs; 5996 stats->rx_frame_errors = adapter->stats.algnerrc; 5997 stats->rx_missed_errors = adapter->stats.mpc; 5998 5999 /* Tx Errors */ 6000 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 6001 stats->tx_aborted_errors = adapter->stats.ecol; 6002 stats->tx_window_errors = adapter->stats.latecol; 6003 stats->tx_carrier_errors = adapter->stats.tncrs; 6004 6005 /* Tx Dropped needs to be maintained elsewhere */ 6006 6007 spin_unlock(&adapter->stats64_lock); 6008 } 6009 6010 /** 6011 * e1000_change_mtu - Change the Maximum Transfer Unit 6012 * @netdev: network interface device structure 6013 * @new_mtu: new value for maximum frame size 6014 * 6015 * Returns 0 on success, negative on failure 6016 **/ 6017 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6018 { 6019 struct e1000_adapter *adapter = netdev_priv(netdev); 6020 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6021 6022 /* Jumbo frame support */ 6023 if ((new_mtu > ETH_DATA_LEN) && 6024 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6025 e_err("Jumbo Frames not supported.\n"); 6026 return -EINVAL; 6027 } 6028 6029 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6030 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6031 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6032 (new_mtu > ETH_DATA_LEN)) { 6033 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6034 return -EINVAL; 6035 } 6036 6037 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6038 usleep_range(1000, 2000); 6039 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6040 adapter->max_frame_size = max_frame; 6041 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6042 netdev->mtu = new_mtu; 6043 6044 pm_runtime_get_sync(netdev->dev.parent); 6045 6046 if (netif_running(netdev)) 6047 e1000e_down(adapter, true); 6048 6049 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6050 * means we reserve 2 more, this pushes us to allocate from the next 6051 * larger slab size. 6052 * i.e. RXBUFFER_2048 --> size-4096 slab 6053 * However with the new *_jumbo_rx* routines, jumbo receives will use 6054 * fragmented skbs 6055 */ 6056 6057 if (max_frame <= 2048) 6058 adapter->rx_buffer_len = 2048; 6059 else 6060 adapter->rx_buffer_len = 4096; 6061 6062 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6063 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6064 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6065 6066 if (netif_running(netdev)) 6067 e1000e_up(adapter); 6068 else 6069 e1000e_reset(adapter); 6070 6071 pm_runtime_put_sync(netdev->dev.parent); 6072 6073 clear_bit(__E1000_RESETTING, &adapter->state); 6074 6075 return 0; 6076 } 6077 6078 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6079 int cmd) 6080 { 6081 struct e1000_adapter *adapter = netdev_priv(netdev); 6082 struct mii_ioctl_data *data = if_mii(ifr); 6083 6084 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6085 return -EOPNOTSUPP; 6086 6087 switch (cmd) { 6088 case SIOCGMIIPHY: 6089 data->phy_id = adapter->hw.phy.addr; 6090 break; 6091 case SIOCGMIIREG: 6092 e1000_phy_read_status(adapter); 6093 6094 switch (data->reg_num & 0x1F) { 6095 case MII_BMCR: 6096 data->val_out = adapter->phy_regs.bmcr; 6097 break; 6098 case MII_BMSR: 6099 data->val_out = adapter->phy_regs.bmsr; 6100 break; 6101 case MII_PHYSID1: 6102 data->val_out = (adapter->hw.phy.id >> 16); 6103 break; 6104 case MII_PHYSID2: 6105 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6106 break; 6107 case MII_ADVERTISE: 6108 data->val_out = adapter->phy_regs.advertise; 6109 break; 6110 case MII_LPA: 6111 data->val_out = adapter->phy_regs.lpa; 6112 break; 6113 case MII_EXPANSION: 6114 data->val_out = adapter->phy_regs.expansion; 6115 break; 6116 case MII_CTRL1000: 6117 data->val_out = adapter->phy_regs.ctrl1000; 6118 break; 6119 case MII_STAT1000: 6120 data->val_out = adapter->phy_regs.stat1000; 6121 break; 6122 case MII_ESTATUS: 6123 data->val_out = adapter->phy_regs.estatus; 6124 break; 6125 default: 6126 return -EIO; 6127 } 6128 break; 6129 case SIOCSMIIREG: 6130 default: 6131 return -EOPNOTSUPP; 6132 } 6133 return 0; 6134 } 6135 6136 /** 6137 * e1000e_hwtstamp_ioctl - control hardware time stamping 6138 * @netdev: network interface device structure 6139 * @ifreq: interface request 6140 * 6141 * Outgoing time stamping can be enabled and disabled. Play nice and 6142 * disable it when requested, although it shouldn't cause any overhead 6143 * when no packet needs it. At most one packet in the queue may be 6144 * marked for time stamping, otherwise it would be impossible to tell 6145 * for sure to which packet the hardware time stamp belongs. 6146 * 6147 * Incoming time stamping has to be configured via the hardware filters. 6148 * Not all combinations are supported, in particular event type has to be 6149 * specified. Matching the kind of event packet is not supported, with the 6150 * exception of "all V2 events regardless of level 2 or 4". 6151 **/ 6152 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6153 { 6154 struct e1000_adapter *adapter = netdev_priv(netdev); 6155 struct hwtstamp_config config; 6156 int ret_val; 6157 6158 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6159 return -EFAULT; 6160 6161 ret_val = e1000e_config_hwtstamp(adapter, &config); 6162 if (ret_val) 6163 return ret_val; 6164 6165 switch (config.rx_filter) { 6166 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6167 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6168 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6169 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6170 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6171 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6172 /* With V2 type filters which specify a Sync or Delay Request, 6173 * Path Delay Request/Response messages are also time stamped 6174 * by hardware so notify the caller the requested packets plus 6175 * some others are time stamped. 6176 */ 6177 config.rx_filter = HWTSTAMP_FILTER_SOME; 6178 break; 6179 default: 6180 break; 6181 } 6182 6183 return copy_to_user(ifr->ifr_data, &config, 6184 sizeof(config)) ? -EFAULT : 0; 6185 } 6186 6187 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6188 { 6189 struct e1000_adapter *adapter = netdev_priv(netdev); 6190 6191 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6192 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6193 } 6194 6195 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6196 { 6197 switch (cmd) { 6198 case SIOCGMIIPHY: 6199 case SIOCGMIIREG: 6200 case SIOCSMIIREG: 6201 return e1000_mii_ioctl(netdev, ifr, cmd); 6202 case SIOCSHWTSTAMP: 6203 return e1000e_hwtstamp_set(netdev, ifr); 6204 case SIOCGHWTSTAMP: 6205 return e1000e_hwtstamp_get(netdev, ifr); 6206 default: 6207 return -EOPNOTSUPP; 6208 } 6209 } 6210 6211 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6212 { 6213 struct e1000_hw *hw = &adapter->hw; 6214 u32 i, mac_reg, wuc; 6215 u16 phy_reg, wuc_enable; 6216 int retval; 6217 6218 /* copy MAC RARs to PHY RARs */ 6219 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6220 6221 retval = hw->phy.ops.acquire(hw); 6222 if (retval) { 6223 e_err("Could not acquire PHY\n"); 6224 return retval; 6225 } 6226 6227 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6228 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6229 if (retval) 6230 goto release; 6231 6232 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6233 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6234 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6235 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6236 (u16)(mac_reg & 0xFFFF)); 6237 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6238 (u16)((mac_reg >> 16) & 0xFFFF)); 6239 } 6240 6241 /* configure PHY Rx Control register */ 6242 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6243 mac_reg = er32(RCTL); 6244 if (mac_reg & E1000_RCTL_UPE) 6245 phy_reg |= BM_RCTL_UPE; 6246 if (mac_reg & E1000_RCTL_MPE) 6247 phy_reg |= BM_RCTL_MPE; 6248 phy_reg &= ~(BM_RCTL_MO_MASK); 6249 if (mac_reg & E1000_RCTL_MO_3) 6250 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6251 << BM_RCTL_MO_SHIFT); 6252 if (mac_reg & E1000_RCTL_BAM) 6253 phy_reg |= BM_RCTL_BAM; 6254 if (mac_reg & E1000_RCTL_PMCF) 6255 phy_reg |= BM_RCTL_PMCF; 6256 mac_reg = er32(CTRL); 6257 if (mac_reg & E1000_CTRL_RFCE) 6258 phy_reg |= BM_RCTL_RFCE; 6259 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6260 6261 wuc = E1000_WUC_PME_EN; 6262 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6263 wuc |= E1000_WUC_APME; 6264 6265 /* enable PHY wakeup in MAC register */ 6266 ew32(WUFC, wufc); 6267 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6268 E1000_WUC_PME_STATUS | wuc)); 6269 6270 /* configure and enable PHY wakeup in PHY registers */ 6271 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6272 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6273 6274 /* activate PHY wakeup */ 6275 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6276 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6277 if (retval) 6278 e_err("Could not set PHY Host Wakeup bit\n"); 6279 release: 6280 hw->phy.ops.release(hw); 6281 6282 return retval; 6283 } 6284 6285 static void e1000e_flush_lpic(struct pci_dev *pdev) 6286 { 6287 struct net_device *netdev = pci_get_drvdata(pdev); 6288 struct e1000_adapter *adapter = netdev_priv(netdev); 6289 struct e1000_hw *hw = &adapter->hw; 6290 u32 ret_val; 6291 6292 pm_runtime_get_sync(netdev->dev.parent); 6293 6294 ret_val = hw->phy.ops.acquire(hw); 6295 if (ret_val) 6296 goto fl_out; 6297 6298 pr_info("EEE TX LPI TIMER: %08X\n", 6299 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6300 6301 hw->phy.ops.release(hw); 6302 6303 fl_out: 6304 pm_runtime_put_sync(netdev->dev.parent); 6305 } 6306 6307 static int e1000e_pm_freeze(struct device *dev) 6308 { 6309 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6310 struct e1000_adapter *adapter = netdev_priv(netdev); 6311 6312 netif_device_detach(netdev); 6313 6314 if (netif_running(netdev)) { 6315 int count = E1000_CHECK_RESET_COUNT; 6316 6317 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6318 usleep_range(10000, 20000); 6319 6320 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6321 6322 /* Quiesce the device without resetting the hardware */ 6323 e1000e_down(adapter, false); 6324 e1000_free_irq(adapter); 6325 } 6326 e1000e_reset_interrupt_capability(adapter); 6327 6328 /* Allow time for pending master requests to run */ 6329 e1000e_disable_pcie_master(&adapter->hw); 6330 6331 return 0; 6332 } 6333 6334 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6335 { 6336 struct net_device *netdev = pci_get_drvdata(pdev); 6337 struct e1000_adapter *adapter = netdev_priv(netdev); 6338 struct e1000_hw *hw = &adapter->hw; 6339 u32 ctrl, ctrl_ext, rctl, status; 6340 /* Runtime suspend should only enable wakeup for link changes */ 6341 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6342 int retval = 0; 6343 6344 status = er32(STATUS); 6345 if (status & E1000_STATUS_LU) 6346 wufc &= ~E1000_WUFC_LNKC; 6347 6348 if (wufc) { 6349 e1000_setup_rctl(adapter); 6350 e1000e_set_rx_mode(netdev); 6351 6352 /* turn on all-multi mode if wake on multicast is enabled */ 6353 if (wufc & E1000_WUFC_MC) { 6354 rctl = er32(RCTL); 6355 rctl |= E1000_RCTL_MPE; 6356 ew32(RCTL, rctl); 6357 } 6358 6359 ctrl = er32(CTRL); 6360 ctrl |= E1000_CTRL_ADVD3WUC; 6361 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6362 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6363 ew32(CTRL, ctrl); 6364 6365 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6366 adapter->hw.phy.media_type == 6367 e1000_media_type_internal_serdes) { 6368 /* keep the laser running in D3 */ 6369 ctrl_ext = er32(CTRL_EXT); 6370 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6371 ew32(CTRL_EXT, ctrl_ext); 6372 } 6373 6374 if (!runtime) 6375 e1000e_power_up_phy(adapter); 6376 6377 if (adapter->flags & FLAG_IS_ICH) 6378 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6379 6380 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6381 /* enable wakeup by the PHY */ 6382 retval = e1000_init_phy_wakeup(adapter, wufc); 6383 if (retval) 6384 return retval; 6385 } else { 6386 /* enable wakeup by the MAC */ 6387 ew32(WUFC, wufc); 6388 ew32(WUC, E1000_WUC_PME_EN); 6389 } 6390 } else { 6391 ew32(WUC, 0); 6392 ew32(WUFC, 0); 6393 6394 e1000_power_down_phy(adapter); 6395 } 6396 6397 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6398 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6399 } else if (hw->mac.type >= e1000_pch_lpt) { 6400 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6401 /* ULP does not support wake from unicast, multicast 6402 * or broadcast. 6403 */ 6404 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6405 6406 if (retval) 6407 return retval; 6408 } 6409 6410 /* Ensure that the appropriate bits are set in LPI_CTRL 6411 * for EEE in Sx 6412 */ 6413 if ((hw->phy.type >= e1000_phy_i217) && 6414 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6415 u16 lpi_ctrl = 0; 6416 6417 retval = hw->phy.ops.acquire(hw); 6418 if (!retval) { 6419 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6420 &lpi_ctrl); 6421 if (!retval) { 6422 if (adapter->eee_advert & 6423 hw->dev_spec.ich8lan.eee_lp_ability & 6424 I82579_EEE_100_SUPPORTED) 6425 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6426 if (adapter->eee_advert & 6427 hw->dev_spec.ich8lan.eee_lp_ability & 6428 I82579_EEE_1000_SUPPORTED) 6429 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6430 6431 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6432 lpi_ctrl); 6433 } 6434 } 6435 hw->phy.ops.release(hw); 6436 } 6437 6438 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6439 * would have already happened in close and is redundant. 6440 */ 6441 e1000e_release_hw_control(adapter); 6442 6443 pci_clear_master(pdev); 6444 6445 /* The pci-e switch on some quad port adapters will report a 6446 * correctable error when the MAC transitions from D0 to D3. To 6447 * prevent this we need to mask off the correctable errors on the 6448 * downstream port of the pci-e switch. 6449 * 6450 * We don't have the associated upstream bridge while assigning 6451 * the PCI device into guest. For example, the KVM on power is 6452 * one of the cases. 6453 */ 6454 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6455 struct pci_dev *us_dev = pdev->bus->self; 6456 u16 devctl; 6457 6458 if (!us_dev) 6459 return 0; 6460 6461 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6462 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6463 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6464 6465 pci_save_state(pdev); 6466 pci_prepare_to_sleep(pdev); 6467 6468 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6469 } 6470 6471 return 0; 6472 } 6473 6474 /** 6475 * __e1000e_disable_aspm - Disable ASPM states 6476 * @pdev: pointer to PCI device struct 6477 * @state: bit-mask of ASPM states to disable 6478 * @locked: indication if this context holds pci_bus_sem locked. 6479 * 6480 * Some devices *must* have certain ASPM states disabled per hardware errata. 6481 **/ 6482 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6483 { 6484 struct pci_dev *parent = pdev->bus->self; 6485 u16 aspm_dis_mask = 0; 6486 u16 pdev_aspmc, parent_aspmc; 6487 6488 switch (state) { 6489 case PCIE_LINK_STATE_L0S: 6490 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6491 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6492 /* fall-through - can't have L1 without L0s */ 6493 case PCIE_LINK_STATE_L1: 6494 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6495 break; 6496 default: 6497 return; 6498 } 6499 6500 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6501 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6502 6503 if (parent) { 6504 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6505 &parent_aspmc); 6506 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6507 } 6508 6509 /* Nothing to do if the ASPM states to be disabled already are */ 6510 if (!(pdev_aspmc & aspm_dis_mask) && 6511 (!parent || !(parent_aspmc & aspm_dis_mask))) 6512 return; 6513 6514 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6515 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6516 "L0s" : "", 6517 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6518 "L1" : ""); 6519 6520 #ifdef CONFIG_PCIEASPM 6521 if (locked) 6522 pci_disable_link_state_locked(pdev, state); 6523 else 6524 pci_disable_link_state(pdev, state); 6525 6526 /* Double-check ASPM control. If not disabled by the above, the 6527 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6528 * not enabled); override by writing PCI config space directly. 6529 */ 6530 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6531 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6532 6533 if (!(aspm_dis_mask & pdev_aspmc)) 6534 return; 6535 #endif 6536 6537 /* Both device and parent should have the same ASPM setting. 6538 * Disable ASPM in downstream component first and then upstream. 6539 */ 6540 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6541 6542 if (parent) 6543 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6544 aspm_dis_mask); 6545 } 6546 6547 /** 6548 * e1000e_disable_aspm - Disable ASPM states. 6549 * @pdev: pointer to PCI device struct 6550 * @state: bit-mask of ASPM states to disable 6551 * 6552 * This function acquires the pci_bus_sem! 6553 * Some devices *must* have certain ASPM states disabled per hardware errata. 6554 **/ 6555 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6556 { 6557 __e1000e_disable_aspm(pdev, state, 0); 6558 } 6559 6560 /** 6561 * e1000e_disable_aspm_locked Disable ASPM states. 6562 * @pdev: pointer to PCI device struct 6563 * @state: bit-mask of ASPM states to disable 6564 * 6565 * This function must be called with pci_bus_sem acquired! 6566 * Some devices *must* have certain ASPM states disabled per hardware errata. 6567 **/ 6568 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6569 { 6570 __e1000e_disable_aspm(pdev, state, 1); 6571 } 6572 6573 #ifdef CONFIG_PM 6574 static int __e1000_resume(struct pci_dev *pdev) 6575 { 6576 struct net_device *netdev = pci_get_drvdata(pdev); 6577 struct e1000_adapter *adapter = netdev_priv(netdev); 6578 struct e1000_hw *hw = &adapter->hw; 6579 u16 aspm_disable_flag = 0; 6580 6581 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6582 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6583 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6584 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6585 if (aspm_disable_flag) 6586 e1000e_disable_aspm(pdev, aspm_disable_flag); 6587 6588 pci_set_master(pdev); 6589 6590 if (hw->mac.type >= e1000_pch2lan) 6591 e1000_resume_workarounds_pchlan(&adapter->hw); 6592 6593 e1000e_power_up_phy(adapter); 6594 6595 /* report the system wakeup cause from S3/S4 */ 6596 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6597 u16 phy_data; 6598 6599 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6600 if (phy_data) { 6601 e_info("PHY Wakeup cause - %s\n", 6602 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6603 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6604 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6605 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6606 phy_data & E1000_WUS_LNKC ? 6607 "Link Status Change" : "other"); 6608 } 6609 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6610 } else { 6611 u32 wus = er32(WUS); 6612 6613 if (wus) { 6614 e_info("MAC Wakeup cause - %s\n", 6615 wus & E1000_WUS_EX ? "Unicast Packet" : 6616 wus & E1000_WUS_MC ? "Multicast Packet" : 6617 wus & E1000_WUS_BC ? "Broadcast Packet" : 6618 wus & E1000_WUS_MAG ? "Magic Packet" : 6619 wus & E1000_WUS_LNKC ? "Link Status Change" : 6620 "other"); 6621 } 6622 ew32(WUS, ~0); 6623 } 6624 6625 e1000e_reset(adapter); 6626 6627 e1000_init_manageability_pt(adapter); 6628 6629 /* If the controller has AMT, do not set DRV_LOAD until the interface 6630 * is up. For all other cases, let the f/w know that the h/w is now 6631 * under the control of the driver. 6632 */ 6633 if (!(adapter->flags & FLAG_HAS_AMT)) 6634 e1000e_get_hw_control(adapter); 6635 6636 return 0; 6637 } 6638 6639 #ifdef CONFIG_PM_SLEEP 6640 static int e1000e_pm_thaw(struct device *dev) 6641 { 6642 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6643 struct e1000_adapter *adapter = netdev_priv(netdev); 6644 6645 e1000e_set_interrupt_capability(adapter); 6646 if (netif_running(netdev)) { 6647 u32 err = e1000_request_irq(adapter); 6648 6649 if (err) 6650 return err; 6651 6652 e1000e_up(adapter); 6653 } 6654 6655 netif_device_attach(netdev); 6656 6657 return 0; 6658 } 6659 6660 static int e1000e_pm_suspend(struct device *dev) 6661 { 6662 struct pci_dev *pdev = to_pci_dev(dev); 6663 int rc; 6664 6665 e1000e_flush_lpic(pdev); 6666 6667 e1000e_pm_freeze(dev); 6668 6669 rc = __e1000_shutdown(pdev, false); 6670 if (rc) 6671 e1000e_pm_thaw(dev); 6672 6673 return rc; 6674 } 6675 6676 static int e1000e_pm_resume(struct device *dev) 6677 { 6678 struct pci_dev *pdev = to_pci_dev(dev); 6679 int rc; 6680 6681 rc = __e1000_resume(pdev); 6682 if (rc) 6683 return rc; 6684 6685 return e1000e_pm_thaw(dev); 6686 } 6687 #endif /* CONFIG_PM_SLEEP */ 6688 6689 static int e1000e_pm_runtime_idle(struct device *dev) 6690 { 6691 struct pci_dev *pdev = to_pci_dev(dev); 6692 struct net_device *netdev = pci_get_drvdata(pdev); 6693 struct e1000_adapter *adapter = netdev_priv(netdev); 6694 u16 eee_lp; 6695 6696 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6697 6698 if (!e1000e_has_link(adapter)) { 6699 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6700 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6701 } 6702 6703 return -EBUSY; 6704 } 6705 6706 static int e1000e_pm_runtime_resume(struct device *dev) 6707 { 6708 struct pci_dev *pdev = to_pci_dev(dev); 6709 struct net_device *netdev = pci_get_drvdata(pdev); 6710 struct e1000_adapter *adapter = netdev_priv(netdev); 6711 int rc; 6712 6713 rc = __e1000_resume(pdev); 6714 if (rc) 6715 return rc; 6716 6717 if (netdev->flags & IFF_UP) 6718 e1000e_up(adapter); 6719 6720 return rc; 6721 } 6722 6723 static int e1000e_pm_runtime_suspend(struct device *dev) 6724 { 6725 struct pci_dev *pdev = to_pci_dev(dev); 6726 struct net_device *netdev = pci_get_drvdata(pdev); 6727 struct e1000_adapter *adapter = netdev_priv(netdev); 6728 6729 if (netdev->flags & IFF_UP) { 6730 int count = E1000_CHECK_RESET_COUNT; 6731 6732 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6733 usleep_range(10000, 20000); 6734 6735 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6736 6737 /* Down the device without resetting the hardware */ 6738 e1000e_down(adapter, false); 6739 } 6740 6741 if (__e1000_shutdown(pdev, true)) { 6742 e1000e_pm_runtime_resume(dev); 6743 return -EBUSY; 6744 } 6745 6746 return 0; 6747 } 6748 #endif /* CONFIG_PM */ 6749 6750 static void e1000_shutdown(struct pci_dev *pdev) 6751 { 6752 e1000e_flush_lpic(pdev); 6753 6754 e1000e_pm_freeze(&pdev->dev); 6755 6756 __e1000_shutdown(pdev, false); 6757 } 6758 6759 #ifdef CONFIG_NET_POLL_CONTROLLER 6760 6761 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6762 { 6763 struct net_device *netdev = data; 6764 struct e1000_adapter *adapter = netdev_priv(netdev); 6765 6766 if (adapter->msix_entries) { 6767 int vector, msix_irq; 6768 6769 vector = 0; 6770 msix_irq = adapter->msix_entries[vector].vector; 6771 if (disable_hardirq(msix_irq)) 6772 e1000_intr_msix_rx(msix_irq, netdev); 6773 enable_irq(msix_irq); 6774 6775 vector++; 6776 msix_irq = adapter->msix_entries[vector].vector; 6777 if (disable_hardirq(msix_irq)) 6778 e1000_intr_msix_tx(msix_irq, netdev); 6779 enable_irq(msix_irq); 6780 6781 vector++; 6782 msix_irq = adapter->msix_entries[vector].vector; 6783 if (disable_hardirq(msix_irq)) 6784 e1000_msix_other(msix_irq, netdev); 6785 enable_irq(msix_irq); 6786 } 6787 6788 return IRQ_HANDLED; 6789 } 6790 6791 /** 6792 * e1000_netpoll 6793 * @netdev: network interface device structure 6794 * 6795 * Polling 'interrupt' - used by things like netconsole to send skbs 6796 * without having to re-enable interrupts. It's not called while 6797 * the interrupt routine is executing. 6798 */ 6799 static void e1000_netpoll(struct net_device *netdev) 6800 { 6801 struct e1000_adapter *adapter = netdev_priv(netdev); 6802 6803 switch (adapter->int_mode) { 6804 case E1000E_INT_MODE_MSIX: 6805 e1000_intr_msix(adapter->pdev->irq, netdev); 6806 break; 6807 case E1000E_INT_MODE_MSI: 6808 if (disable_hardirq(adapter->pdev->irq)) 6809 e1000_intr_msi(adapter->pdev->irq, netdev); 6810 enable_irq(adapter->pdev->irq); 6811 break; 6812 default: /* E1000E_INT_MODE_LEGACY */ 6813 if (disable_hardirq(adapter->pdev->irq)) 6814 e1000_intr(adapter->pdev->irq, netdev); 6815 enable_irq(adapter->pdev->irq); 6816 break; 6817 } 6818 } 6819 #endif 6820 6821 /** 6822 * e1000_io_error_detected - called when PCI error is detected 6823 * @pdev: Pointer to PCI device 6824 * @state: The current pci connection state 6825 * 6826 * This function is called after a PCI bus error affecting 6827 * this device has been detected. 6828 */ 6829 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6830 pci_channel_state_t state) 6831 { 6832 struct net_device *netdev = pci_get_drvdata(pdev); 6833 struct e1000_adapter *adapter = netdev_priv(netdev); 6834 6835 netif_device_detach(netdev); 6836 6837 if (state == pci_channel_io_perm_failure) 6838 return PCI_ERS_RESULT_DISCONNECT; 6839 6840 if (netif_running(netdev)) 6841 e1000e_down(adapter, true); 6842 pci_disable_device(pdev); 6843 6844 /* Request a slot slot reset. */ 6845 return PCI_ERS_RESULT_NEED_RESET; 6846 } 6847 6848 /** 6849 * e1000_io_slot_reset - called after the pci bus has been reset. 6850 * @pdev: Pointer to PCI device 6851 * 6852 * Restart the card from scratch, as if from a cold-boot. Implementation 6853 * resembles the first-half of the e1000e_pm_resume routine. 6854 */ 6855 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6856 { 6857 struct net_device *netdev = pci_get_drvdata(pdev); 6858 struct e1000_adapter *adapter = netdev_priv(netdev); 6859 struct e1000_hw *hw = &adapter->hw; 6860 u16 aspm_disable_flag = 0; 6861 int err; 6862 pci_ers_result_t result; 6863 6864 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6865 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6866 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6867 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6868 if (aspm_disable_flag) 6869 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 6870 6871 err = pci_enable_device_mem(pdev); 6872 if (err) { 6873 dev_err(&pdev->dev, 6874 "Cannot re-enable PCI device after reset.\n"); 6875 result = PCI_ERS_RESULT_DISCONNECT; 6876 } else { 6877 pdev->state_saved = true; 6878 pci_restore_state(pdev); 6879 pci_set_master(pdev); 6880 6881 pci_enable_wake(pdev, PCI_D3hot, 0); 6882 pci_enable_wake(pdev, PCI_D3cold, 0); 6883 6884 e1000e_reset(adapter); 6885 ew32(WUS, ~0); 6886 result = PCI_ERS_RESULT_RECOVERED; 6887 } 6888 6889 pci_cleanup_aer_uncorrect_error_status(pdev); 6890 6891 return result; 6892 } 6893 6894 /** 6895 * e1000_io_resume - called when traffic can start flowing again. 6896 * @pdev: Pointer to PCI device 6897 * 6898 * This callback is called when the error recovery driver tells us that 6899 * its OK to resume normal operation. Implementation resembles the 6900 * second-half of the e1000e_pm_resume routine. 6901 */ 6902 static void e1000_io_resume(struct pci_dev *pdev) 6903 { 6904 struct net_device *netdev = pci_get_drvdata(pdev); 6905 struct e1000_adapter *adapter = netdev_priv(netdev); 6906 6907 e1000_init_manageability_pt(adapter); 6908 6909 if (netif_running(netdev)) 6910 e1000e_up(adapter); 6911 6912 netif_device_attach(netdev); 6913 6914 /* If the controller has AMT, do not set DRV_LOAD until the interface 6915 * is up. For all other cases, let the f/w know that the h/w is now 6916 * under the control of the driver. 6917 */ 6918 if (!(adapter->flags & FLAG_HAS_AMT)) 6919 e1000e_get_hw_control(adapter); 6920 } 6921 6922 static void e1000_print_device_info(struct e1000_adapter *adapter) 6923 { 6924 struct e1000_hw *hw = &adapter->hw; 6925 struct net_device *netdev = adapter->netdev; 6926 u32 ret_val; 6927 u8 pba_str[E1000_PBANUM_LENGTH]; 6928 6929 /* print bus type/speed/width info */ 6930 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6931 /* bus width */ 6932 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6933 "Width x1"), 6934 /* MAC address */ 6935 netdev->dev_addr); 6936 e_info("Intel(R) PRO/%s Network Connection\n", 6937 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6938 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6939 E1000_PBANUM_LENGTH); 6940 if (ret_val) 6941 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6942 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6943 hw->mac.type, hw->phy.type, pba_str); 6944 } 6945 6946 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6947 { 6948 struct e1000_hw *hw = &adapter->hw; 6949 int ret_val; 6950 u16 buf = 0; 6951 6952 if (hw->mac.type != e1000_82573) 6953 return; 6954 6955 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6956 le16_to_cpus(&buf); 6957 if (!ret_val && (!(buf & BIT(0)))) { 6958 /* Deep Smart Power Down (DSPD) */ 6959 dev_warn(&adapter->pdev->dev, 6960 "Warning: detected DSPD enabled in EEPROM\n"); 6961 } 6962 } 6963 6964 static netdev_features_t e1000_fix_features(struct net_device *netdev, 6965 netdev_features_t features) 6966 { 6967 struct e1000_adapter *adapter = netdev_priv(netdev); 6968 struct e1000_hw *hw = &adapter->hw; 6969 6970 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6971 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 6972 features &= ~NETIF_F_RXFCS; 6973 6974 /* Since there is no support for separate Rx/Tx vlan accel 6975 * enable/disable make sure Tx flag is always in same state as Rx. 6976 */ 6977 if (features & NETIF_F_HW_VLAN_CTAG_RX) 6978 features |= NETIF_F_HW_VLAN_CTAG_TX; 6979 else 6980 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 6981 6982 return features; 6983 } 6984 6985 static int e1000_set_features(struct net_device *netdev, 6986 netdev_features_t features) 6987 { 6988 struct e1000_adapter *adapter = netdev_priv(netdev); 6989 netdev_features_t changed = features ^ netdev->features; 6990 6991 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6992 adapter->flags |= FLAG_TSO_FORCE; 6993 6994 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6995 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6996 NETIF_F_RXALL))) 6997 return 0; 6998 6999 if (changed & NETIF_F_RXFCS) { 7000 if (features & NETIF_F_RXFCS) { 7001 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7002 } else { 7003 /* We need to take it back to defaults, which might mean 7004 * stripping is still disabled at the adapter level. 7005 */ 7006 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7007 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7008 else 7009 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7010 } 7011 } 7012 7013 netdev->features = features; 7014 7015 if (netif_running(netdev)) 7016 e1000e_reinit_locked(adapter); 7017 else 7018 e1000e_reset(adapter); 7019 7020 return 0; 7021 } 7022 7023 static const struct net_device_ops e1000e_netdev_ops = { 7024 .ndo_open = e1000e_open, 7025 .ndo_stop = e1000e_close, 7026 .ndo_start_xmit = e1000_xmit_frame, 7027 .ndo_get_stats64 = e1000e_get_stats64, 7028 .ndo_set_rx_mode = e1000e_set_rx_mode, 7029 .ndo_set_mac_address = e1000_set_mac, 7030 .ndo_change_mtu = e1000_change_mtu, 7031 .ndo_do_ioctl = e1000_ioctl, 7032 .ndo_tx_timeout = e1000_tx_timeout, 7033 .ndo_validate_addr = eth_validate_addr, 7034 7035 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7036 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7037 #ifdef CONFIG_NET_POLL_CONTROLLER 7038 .ndo_poll_controller = e1000_netpoll, 7039 #endif 7040 .ndo_set_features = e1000_set_features, 7041 .ndo_fix_features = e1000_fix_features, 7042 .ndo_features_check = passthru_features_check, 7043 }; 7044 7045 /** 7046 * e1000_probe - Device Initialization Routine 7047 * @pdev: PCI device information struct 7048 * @ent: entry in e1000_pci_tbl 7049 * 7050 * Returns 0 on success, negative on failure 7051 * 7052 * e1000_probe initializes an adapter identified by a pci_dev structure. 7053 * The OS initialization, configuring of the adapter private structure, 7054 * and a hardware reset occur. 7055 **/ 7056 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7057 { 7058 struct net_device *netdev; 7059 struct e1000_adapter *adapter; 7060 struct e1000_hw *hw; 7061 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7062 resource_size_t mmio_start, mmio_len; 7063 resource_size_t flash_start, flash_len; 7064 static int cards_found; 7065 u16 aspm_disable_flag = 0; 7066 int bars, i, err, pci_using_dac; 7067 u16 eeprom_data = 0; 7068 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7069 s32 ret_val = 0; 7070 7071 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7072 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7073 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7074 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7075 if (aspm_disable_flag) 7076 e1000e_disable_aspm(pdev, aspm_disable_flag); 7077 7078 err = pci_enable_device_mem(pdev); 7079 if (err) 7080 return err; 7081 7082 pci_using_dac = 0; 7083 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7084 if (!err) { 7085 pci_using_dac = 1; 7086 } else { 7087 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7088 if (err) { 7089 dev_err(&pdev->dev, 7090 "No usable DMA configuration, aborting\n"); 7091 goto err_dma; 7092 } 7093 } 7094 7095 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7096 err = pci_request_selected_regions_exclusive(pdev, bars, 7097 e1000e_driver_name); 7098 if (err) 7099 goto err_pci_reg; 7100 7101 /* AER (Advanced Error Reporting) hooks */ 7102 pci_enable_pcie_error_reporting(pdev); 7103 7104 pci_set_master(pdev); 7105 /* PCI config space info */ 7106 err = pci_save_state(pdev); 7107 if (err) 7108 goto err_alloc_etherdev; 7109 7110 err = -ENOMEM; 7111 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7112 if (!netdev) 7113 goto err_alloc_etherdev; 7114 7115 SET_NETDEV_DEV(netdev, &pdev->dev); 7116 7117 netdev->irq = pdev->irq; 7118 7119 pci_set_drvdata(pdev, netdev); 7120 adapter = netdev_priv(netdev); 7121 hw = &adapter->hw; 7122 adapter->netdev = netdev; 7123 adapter->pdev = pdev; 7124 adapter->ei = ei; 7125 adapter->pba = ei->pba; 7126 adapter->flags = ei->flags; 7127 adapter->flags2 = ei->flags2; 7128 adapter->hw.adapter = adapter; 7129 adapter->hw.mac.type = ei->mac; 7130 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7131 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7132 7133 mmio_start = pci_resource_start(pdev, 0); 7134 mmio_len = pci_resource_len(pdev, 0); 7135 7136 err = -EIO; 7137 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7138 if (!adapter->hw.hw_addr) 7139 goto err_ioremap; 7140 7141 if ((adapter->flags & FLAG_HAS_FLASH) && 7142 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7143 (hw->mac.type < e1000_pch_spt)) { 7144 flash_start = pci_resource_start(pdev, 1); 7145 flash_len = pci_resource_len(pdev, 1); 7146 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7147 if (!adapter->hw.flash_address) 7148 goto err_flashmap; 7149 } 7150 7151 /* Set default EEE advertisement */ 7152 if (adapter->flags2 & FLAG2_HAS_EEE) 7153 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7154 7155 /* construct the net_device struct */ 7156 netdev->netdev_ops = &e1000e_netdev_ops; 7157 e1000e_set_ethtool_ops(netdev); 7158 netdev->watchdog_timeo = 5 * HZ; 7159 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7160 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7161 7162 netdev->mem_start = mmio_start; 7163 netdev->mem_end = mmio_start + mmio_len; 7164 7165 adapter->bd_number = cards_found++; 7166 7167 e1000e_check_options(adapter); 7168 7169 /* setup adapter struct */ 7170 err = e1000_sw_init(adapter); 7171 if (err) 7172 goto err_sw_init; 7173 7174 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7175 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7176 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7177 7178 err = ei->get_variants(adapter); 7179 if (err) 7180 goto err_hw_init; 7181 7182 if ((adapter->flags & FLAG_IS_ICH) && 7183 (adapter->flags & FLAG_READ_ONLY_NVM) && 7184 (hw->mac.type < e1000_pch_spt)) 7185 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7186 7187 hw->mac.ops.get_bus_info(&adapter->hw); 7188 7189 adapter->hw.phy.autoneg_wait_to_complete = 0; 7190 7191 /* Copper options */ 7192 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7193 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7194 adapter->hw.phy.disable_polarity_correction = 0; 7195 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7196 } 7197 7198 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7199 dev_info(&pdev->dev, 7200 "PHY reset is blocked due to SOL/IDER session.\n"); 7201 7202 /* Set initial default active device features */ 7203 netdev->features = (NETIF_F_SG | 7204 NETIF_F_HW_VLAN_CTAG_RX | 7205 NETIF_F_HW_VLAN_CTAG_TX | 7206 NETIF_F_TSO | 7207 NETIF_F_TSO6 | 7208 NETIF_F_RXHASH | 7209 NETIF_F_RXCSUM | 7210 NETIF_F_HW_CSUM); 7211 7212 /* Set user-changeable features (subset of all device features) */ 7213 netdev->hw_features = netdev->features; 7214 netdev->hw_features |= NETIF_F_RXFCS; 7215 netdev->priv_flags |= IFF_SUPP_NOFCS; 7216 netdev->hw_features |= NETIF_F_RXALL; 7217 7218 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7219 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7220 7221 netdev->vlan_features |= (NETIF_F_SG | 7222 NETIF_F_TSO | 7223 NETIF_F_TSO6 | 7224 NETIF_F_HW_CSUM); 7225 7226 netdev->priv_flags |= IFF_UNICAST_FLT; 7227 7228 if (pci_using_dac) { 7229 netdev->features |= NETIF_F_HIGHDMA; 7230 netdev->vlan_features |= NETIF_F_HIGHDMA; 7231 } 7232 7233 /* MTU range: 68 - max_hw_frame_size */ 7234 netdev->min_mtu = ETH_MIN_MTU; 7235 netdev->max_mtu = adapter->max_hw_frame_size - 7236 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7237 7238 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7239 adapter->flags |= FLAG_MNG_PT_ENABLED; 7240 7241 /* before reading the NVM, reset the controller to 7242 * put the device in a known good starting state 7243 */ 7244 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7245 7246 /* systems with ASPM and others may see the checksum fail on the first 7247 * attempt. Let's give it a few tries 7248 */ 7249 for (i = 0;; i++) { 7250 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7251 break; 7252 if (i == 2) { 7253 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7254 err = -EIO; 7255 goto err_eeprom; 7256 } 7257 } 7258 7259 e1000_eeprom_checks(adapter); 7260 7261 /* copy the MAC address */ 7262 if (e1000e_read_mac_addr(&adapter->hw)) 7263 dev_err(&pdev->dev, 7264 "NVM Read Error while reading MAC address\n"); 7265 7266 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7267 7268 if (!is_valid_ether_addr(netdev->dev_addr)) { 7269 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7270 netdev->dev_addr); 7271 err = -EIO; 7272 goto err_eeprom; 7273 } 7274 7275 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7276 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7277 7278 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7279 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7280 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7281 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7282 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7283 7284 /* Initialize link parameters. User can change them with ethtool */ 7285 adapter->hw.mac.autoneg = 1; 7286 adapter->fc_autoneg = true; 7287 adapter->hw.fc.requested_mode = e1000_fc_default; 7288 adapter->hw.fc.current_mode = e1000_fc_default; 7289 adapter->hw.phy.autoneg_advertised = 0x2f; 7290 7291 /* Initial Wake on LAN setting - If APM wake is enabled in 7292 * the EEPROM, enable the ACPI Magic Packet filter 7293 */ 7294 if (adapter->flags & FLAG_APME_IN_WUC) { 7295 /* APME bit in EEPROM is mapped to WUC.APME */ 7296 eeprom_data = er32(WUC); 7297 eeprom_apme_mask = E1000_WUC_APME; 7298 if ((hw->mac.type > e1000_ich10lan) && 7299 (eeprom_data & E1000_WUC_PHY_WAKE)) 7300 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7301 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7302 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7303 (adapter->hw.bus.func == 1)) 7304 ret_val = e1000_read_nvm(&adapter->hw, 7305 NVM_INIT_CONTROL3_PORT_B, 7306 1, &eeprom_data); 7307 else 7308 ret_val = e1000_read_nvm(&adapter->hw, 7309 NVM_INIT_CONTROL3_PORT_A, 7310 1, &eeprom_data); 7311 } 7312 7313 /* fetch WoL from EEPROM */ 7314 if (ret_val) 7315 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7316 else if (eeprom_data & eeprom_apme_mask) 7317 adapter->eeprom_wol |= E1000_WUFC_MAG; 7318 7319 /* now that we have the eeprom settings, apply the special cases 7320 * where the eeprom may be wrong or the board simply won't support 7321 * wake on lan on a particular port 7322 */ 7323 if (!(adapter->flags & FLAG_HAS_WOL)) 7324 adapter->eeprom_wol = 0; 7325 7326 /* initialize the wol settings based on the eeprom settings */ 7327 adapter->wol = adapter->eeprom_wol; 7328 7329 /* make sure adapter isn't asleep if manageability is enabled */ 7330 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7331 (hw->mac.ops.check_mng_mode(hw))) 7332 device_wakeup_enable(&pdev->dev); 7333 7334 /* save off EEPROM version number */ 7335 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7336 7337 if (ret_val) { 7338 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7339 adapter->eeprom_vers = 0; 7340 } 7341 7342 /* init PTP hardware clock */ 7343 e1000e_ptp_init(adapter); 7344 7345 /* reset the hardware with the new settings */ 7346 e1000e_reset(adapter); 7347 7348 /* If the controller has AMT, do not set DRV_LOAD until the interface 7349 * is up. For all other cases, let the f/w know that the h/w is now 7350 * under the control of the driver. 7351 */ 7352 if (!(adapter->flags & FLAG_HAS_AMT)) 7353 e1000e_get_hw_control(adapter); 7354 7355 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7356 err = register_netdev(netdev); 7357 if (err) 7358 goto err_register; 7359 7360 /* carrier off reporting is important to ethtool even BEFORE open */ 7361 netif_carrier_off(netdev); 7362 7363 e1000_print_device_info(adapter); 7364 7365 if (pci_dev_run_wake(pdev)) 7366 pm_runtime_put_noidle(&pdev->dev); 7367 7368 return 0; 7369 7370 err_register: 7371 if (!(adapter->flags & FLAG_HAS_AMT)) 7372 e1000e_release_hw_control(adapter); 7373 err_eeprom: 7374 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7375 e1000_phy_hw_reset(&adapter->hw); 7376 err_hw_init: 7377 kfree(adapter->tx_ring); 7378 kfree(adapter->rx_ring); 7379 err_sw_init: 7380 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7381 iounmap(adapter->hw.flash_address); 7382 e1000e_reset_interrupt_capability(adapter); 7383 err_flashmap: 7384 iounmap(adapter->hw.hw_addr); 7385 err_ioremap: 7386 free_netdev(netdev); 7387 err_alloc_etherdev: 7388 pci_release_mem_regions(pdev); 7389 err_pci_reg: 7390 err_dma: 7391 pci_disable_device(pdev); 7392 return err; 7393 } 7394 7395 /** 7396 * e1000_remove - Device Removal Routine 7397 * @pdev: PCI device information struct 7398 * 7399 * e1000_remove is called by the PCI subsystem to alert the driver 7400 * that it should release a PCI device. The could be caused by a 7401 * Hot-Plug event, or because the driver is going to be removed from 7402 * memory. 7403 **/ 7404 static void e1000_remove(struct pci_dev *pdev) 7405 { 7406 struct net_device *netdev = pci_get_drvdata(pdev); 7407 struct e1000_adapter *adapter = netdev_priv(netdev); 7408 bool down = test_bit(__E1000_DOWN, &adapter->state); 7409 7410 e1000e_ptp_remove(adapter); 7411 7412 /* The timers may be rescheduled, so explicitly disable them 7413 * from being rescheduled. 7414 */ 7415 if (!down) 7416 set_bit(__E1000_DOWN, &adapter->state); 7417 del_timer_sync(&adapter->watchdog_timer); 7418 del_timer_sync(&adapter->phy_info_timer); 7419 7420 cancel_work_sync(&adapter->reset_task); 7421 cancel_work_sync(&adapter->watchdog_task); 7422 cancel_work_sync(&adapter->downshift_task); 7423 cancel_work_sync(&adapter->update_phy_task); 7424 cancel_work_sync(&adapter->print_hang_task); 7425 7426 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7427 cancel_work_sync(&adapter->tx_hwtstamp_work); 7428 if (adapter->tx_hwtstamp_skb) { 7429 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7430 adapter->tx_hwtstamp_skb = NULL; 7431 } 7432 } 7433 7434 /* Don't lie to e1000_close() down the road. */ 7435 if (!down) 7436 clear_bit(__E1000_DOWN, &adapter->state); 7437 unregister_netdev(netdev); 7438 7439 if (pci_dev_run_wake(pdev)) 7440 pm_runtime_get_noresume(&pdev->dev); 7441 7442 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7443 * would have already happened in close and is redundant. 7444 */ 7445 e1000e_release_hw_control(adapter); 7446 7447 e1000e_reset_interrupt_capability(adapter); 7448 kfree(adapter->tx_ring); 7449 kfree(adapter->rx_ring); 7450 7451 iounmap(adapter->hw.hw_addr); 7452 if ((adapter->hw.flash_address) && 7453 (adapter->hw.mac.type < e1000_pch_spt)) 7454 iounmap(adapter->hw.flash_address); 7455 pci_release_mem_regions(pdev); 7456 7457 free_netdev(netdev); 7458 7459 /* AER disable */ 7460 pci_disable_pcie_error_reporting(pdev); 7461 7462 pci_disable_device(pdev); 7463 } 7464 7465 /* PCI Error Recovery (ERS) */ 7466 static const struct pci_error_handlers e1000_err_handler = { 7467 .error_detected = e1000_io_error_detected, 7468 .slot_reset = e1000_io_slot_reset, 7469 .resume = e1000_io_resume, 7470 }; 7471 7472 static const struct pci_device_id e1000_pci_tbl[] = { 7473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7477 board_82571 }, 7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7483 7484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7488 7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7492 7493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7496 7497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7498 board_80003es2lan }, 7499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7500 board_80003es2lan }, 7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7502 board_80003es2lan }, 7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7504 board_80003es2lan }, 7505 7506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7514 7515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7524 7525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7528 7529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7532 7533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7537 7538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7540 7541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7561 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7565 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7566 7567 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7568 }; 7569 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7570 7571 static const struct dev_pm_ops e1000_pm_ops = { 7572 #ifdef CONFIG_PM_SLEEP 7573 .suspend = e1000e_pm_suspend, 7574 .resume = e1000e_pm_resume, 7575 .freeze = e1000e_pm_freeze, 7576 .thaw = e1000e_pm_thaw, 7577 .poweroff = e1000e_pm_suspend, 7578 .restore = e1000e_pm_resume, 7579 #endif 7580 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7581 e1000e_pm_runtime_idle) 7582 }; 7583 7584 /* PCI Device API Driver */ 7585 static struct pci_driver e1000_driver = { 7586 .name = e1000e_driver_name, 7587 .id_table = e1000_pci_tbl, 7588 .probe = e1000_probe, 7589 .remove = e1000_remove, 7590 .driver = { 7591 .pm = &e1000_pm_ops, 7592 }, 7593 .shutdown = e1000_shutdown, 7594 .err_handler = &e1000_err_handler 7595 }; 7596 7597 /** 7598 * e1000_init_module - Driver Registration Routine 7599 * 7600 * e1000_init_module is the first routine called when the driver is 7601 * loaded. All it does is register with the PCI subsystem. 7602 **/ 7603 static int __init e1000_init_module(void) 7604 { 7605 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7606 e1000e_driver_version); 7607 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7608 7609 return pci_register_driver(&e1000_driver); 7610 } 7611 module_init(e1000_init_module); 7612 7613 /** 7614 * e1000_exit_module - Driver Exit Cleanup Routine 7615 * 7616 * e1000_exit_module is called just before the driver is removed 7617 * from memory. 7618 **/ 7619 static void __exit e1000_exit_module(void) 7620 { 7621 pci_unregister_driver(&e1000_driver); 7622 } 7623 module_exit(e1000_exit_module); 7624 7625 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7626 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7627 MODULE_LICENSE("GPL"); 7628 MODULE_VERSION(DRV_VERSION); 7629 7630 /* netdev.c */ 7631