1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/module.h> 25 #include <linux/types.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/vmalloc.h> 29 #include <linux/pagemap.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/interrupt.h> 33 #include <linux/tcp.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/cpu.h> 41 #include <linux/smp.h> 42 #include <linux/pm_qos.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/aer.h> 45 #include <linux/prefetch.h> 46 47 #include "e1000.h" 48 49 #define DRV_EXTRAVERSION "-k" 50 51 #define DRV_VERSION "2.3.2" DRV_EXTRAVERSION 52 char e1000e_driver_name[] = "e1000e"; 53 const char e1000e_driver_version[] = DRV_VERSION; 54 55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 56 static int debug = -1; 57 module_param(debug, int, 0); 58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 59 60 static const struct e1000_info *e1000_info_tbl[] = { 61 [board_82571] = &e1000_82571_info, 62 [board_82572] = &e1000_82572_info, 63 [board_82573] = &e1000_82573_info, 64 [board_82574] = &e1000_82574_info, 65 [board_82583] = &e1000_82583_info, 66 [board_80003es2lan] = &e1000_es2_info, 67 [board_ich8lan] = &e1000_ich8_info, 68 [board_ich9lan] = &e1000_ich9_info, 69 [board_ich10lan] = &e1000_ich10_info, 70 [board_pchlan] = &e1000_pch_info, 71 [board_pch2lan] = &e1000_pch2_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info, 73 [board_pch_spt] = &e1000_pch_spt_info, 74 }; 75 76 struct e1000_reg_info { 77 u32 ofs; 78 char *name; 79 }; 80 81 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 82 /* General Registers */ 83 {E1000_CTRL, "CTRL"}, 84 {E1000_STATUS, "STATUS"}, 85 {E1000_CTRL_EXT, "CTRL_EXT"}, 86 87 /* Interrupt Registers */ 88 {E1000_ICR, "ICR"}, 89 90 /* Rx Registers */ 91 {E1000_RCTL, "RCTL"}, 92 {E1000_RDLEN(0), "RDLEN"}, 93 {E1000_RDH(0), "RDH"}, 94 {E1000_RDT(0), "RDT"}, 95 {E1000_RDTR, "RDTR"}, 96 {E1000_RXDCTL(0), "RXDCTL"}, 97 {E1000_ERT, "ERT"}, 98 {E1000_RDBAL(0), "RDBAL"}, 99 {E1000_RDBAH(0), "RDBAH"}, 100 {E1000_RDFH, "RDFH"}, 101 {E1000_RDFT, "RDFT"}, 102 {E1000_RDFHS, "RDFHS"}, 103 {E1000_RDFTS, "RDFTS"}, 104 {E1000_RDFPC, "RDFPC"}, 105 106 /* Tx Registers */ 107 {E1000_TCTL, "TCTL"}, 108 {E1000_TDBAL(0), "TDBAL"}, 109 {E1000_TDBAH(0), "TDBAH"}, 110 {E1000_TDLEN(0), "TDLEN"}, 111 {E1000_TDH(0), "TDH"}, 112 {E1000_TDT(0), "TDT"}, 113 {E1000_TIDV, "TIDV"}, 114 {E1000_TXDCTL(0), "TXDCTL"}, 115 {E1000_TADV, "TADV"}, 116 {E1000_TARC(0), "TARC"}, 117 {E1000_TDFH, "TDFH"}, 118 {E1000_TDFT, "TDFT"}, 119 {E1000_TDFHS, "TDFHS"}, 120 {E1000_TDFTS, "TDFTS"}, 121 {E1000_TDFPC, "TDFPC"}, 122 123 /* List Terminator */ 124 {0, NULL} 125 }; 126 127 /** 128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 129 * @hw: pointer to the HW structure 130 * 131 * When updating the MAC CSR registers, the Manageability Engine (ME) could 132 * be accessing the registers at the same time. Normally, this is handled in 133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 134 * accesses later than it should which could result in the register to have 135 * an incorrect value. Workaround this by checking the FWSM register which 136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 137 * and try again a number of times. 138 **/ 139 s32 __ew32_prepare(struct e1000_hw *hw) 140 { 141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 142 143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 144 udelay(50); 145 146 return i; 147 } 148 149 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 150 { 151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 152 __ew32_prepare(hw); 153 154 writel(val, hw->hw_addr + reg); 155 } 156 157 /** 158 * e1000_regdump - register printout routine 159 * @hw: pointer to the HW structure 160 * @reginfo: pointer to the register info table 161 **/ 162 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 163 { 164 int n = 0; 165 char rname[16]; 166 u32 regs[8]; 167 168 switch (reginfo->ofs) { 169 case E1000_RXDCTL(0): 170 for (n = 0; n < 2; n++) 171 regs[n] = __er32(hw, E1000_RXDCTL(n)); 172 break; 173 case E1000_TXDCTL(0): 174 for (n = 0; n < 2; n++) 175 regs[n] = __er32(hw, E1000_TXDCTL(n)); 176 break; 177 case E1000_TARC(0): 178 for (n = 0; n < 2; n++) 179 regs[n] = __er32(hw, E1000_TARC(n)); 180 break; 181 default: 182 pr_info("%-15s %08x\n", 183 reginfo->name, __er32(hw, reginfo->ofs)); 184 return; 185 } 186 187 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 188 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 189 } 190 191 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 192 struct e1000_buffer *bi) 193 { 194 int i; 195 struct e1000_ps_page *ps_page; 196 197 for (i = 0; i < adapter->rx_ps_pages; i++) { 198 ps_page = &bi->ps_pages[i]; 199 200 if (ps_page->page) { 201 pr_info("packet dump for ps_page %d:\n", i); 202 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 203 16, 1, page_address(ps_page->page), 204 PAGE_SIZE, true); 205 } 206 } 207 } 208 209 /** 210 * e1000e_dump - Print registers, Tx-ring and Rx-ring 211 * @adapter: board private structure 212 **/ 213 static void e1000e_dump(struct e1000_adapter *adapter) 214 { 215 struct net_device *netdev = adapter->netdev; 216 struct e1000_hw *hw = &adapter->hw; 217 struct e1000_reg_info *reginfo; 218 struct e1000_ring *tx_ring = adapter->tx_ring; 219 struct e1000_tx_desc *tx_desc; 220 struct my_u0 { 221 __le64 a; 222 __le64 b; 223 } *u0; 224 struct e1000_buffer *buffer_info; 225 struct e1000_ring *rx_ring = adapter->rx_ring; 226 union e1000_rx_desc_packet_split *rx_desc_ps; 227 union e1000_rx_desc_extended *rx_desc; 228 struct my_u1 { 229 __le64 a; 230 __le64 b; 231 __le64 c; 232 __le64 d; 233 } *u1; 234 u32 staterr; 235 int i = 0; 236 237 if (!netif_msg_hw(adapter)) 238 return; 239 240 /* Print netdevice Info */ 241 if (netdev) { 242 dev_info(&adapter->pdev->dev, "Net device Info\n"); 243 pr_info("Device Name state trans_start last_rx\n"); 244 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 245 netdev->state, netdev->trans_start, netdev->last_rx); 246 } 247 248 /* Print Registers */ 249 dev_info(&adapter->pdev->dev, "Register Dump\n"); 250 pr_info(" Register Name Value\n"); 251 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 252 reginfo->name; reginfo++) { 253 e1000_regdump(hw, reginfo); 254 } 255 256 /* Print Tx Ring Summary */ 257 if (!netdev || !netif_running(netdev)) 258 return; 259 260 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 261 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 262 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 263 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 264 0, tx_ring->next_to_use, tx_ring->next_to_clean, 265 (unsigned long long)buffer_info->dma, 266 buffer_info->length, 267 buffer_info->next_to_watch, 268 (unsigned long long)buffer_info->time_stamp); 269 270 /* Print Tx Ring */ 271 if (!netif_msg_tx_done(adapter)) 272 goto rx_ring_summary; 273 274 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 275 276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 277 * 278 * Legacy Transmit Descriptor 279 * +--------------------------------------------------------------+ 280 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 281 * +--------------------------------------------------------------+ 282 * 8 | Special | CSS | Status | CMD | CSO | Length | 283 * +--------------------------------------------------------------+ 284 * 63 48 47 36 35 32 31 24 23 16 15 0 285 * 286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 287 * 63 48 47 40 39 32 31 16 15 8 7 0 288 * +----------------------------------------------------------------+ 289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 290 * +----------------------------------------------------------------+ 291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 292 * +----------------------------------------------------------------+ 293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 294 * 295 * Extended Data Descriptor (DTYP=0x1) 296 * +----------------------------------------------------------------+ 297 * 0 | Buffer Address [63:0] | 298 * +----------------------------------------------------------------+ 299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 300 * +----------------------------------------------------------------+ 301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 302 */ 303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 306 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 307 const char *next_desc; 308 tx_desc = E1000_TX_DESC(*tx_ring, i); 309 buffer_info = &tx_ring->buffer_info[i]; 310 u0 = (struct my_u0 *)tx_desc; 311 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 312 next_desc = " NTC/U"; 313 else if (i == tx_ring->next_to_use) 314 next_desc = " NTU"; 315 else if (i == tx_ring->next_to_clean) 316 next_desc = " NTC"; 317 else 318 next_desc = ""; 319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 320 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' : 321 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')), 322 i, 323 (unsigned long long)le64_to_cpu(u0->a), 324 (unsigned long long)le64_to_cpu(u0->b), 325 (unsigned long long)buffer_info->dma, 326 buffer_info->length, buffer_info->next_to_watch, 327 (unsigned long long)buffer_info->time_stamp, 328 buffer_info->skb, next_desc); 329 330 if (netif_msg_pktdata(adapter) && buffer_info->skb) 331 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 332 16, 1, buffer_info->skb->data, 333 buffer_info->skb->len, true); 334 } 335 336 /* Print Rx Ring Summary */ 337 rx_ring_summary: 338 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 339 pr_info("Queue [NTU] [NTC]\n"); 340 pr_info(" %5d %5X %5X\n", 341 0, rx_ring->next_to_use, rx_ring->next_to_clean); 342 343 /* Print Rx Ring */ 344 if (!netif_msg_rx_status(adapter)) 345 return; 346 347 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 348 switch (adapter->rx_ps_pages) { 349 case 1: 350 case 2: 351 case 3: 352 /* [Extended] Packet Split Receive Descriptor Format 353 * 354 * +-----------------------------------------------------+ 355 * 0 | Buffer Address 0 [63:0] | 356 * +-----------------------------------------------------+ 357 * 8 | Buffer Address 1 [63:0] | 358 * +-----------------------------------------------------+ 359 * 16 | Buffer Address 2 [63:0] | 360 * +-----------------------------------------------------+ 361 * 24 | Buffer Address 3 [63:0] | 362 * +-----------------------------------------------------+ 363 */ 364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 365 /* [Extended] Receive Descriptor (Write-Back) Format 366 * 367 * 63 48 47 32 31 13 12 8 7 4 3 0 368 * +------------------------------------------------------+ 369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 370 * | Checksum | Ident | | Queue | | Type | 371 * +------------------------------------------------------+ 372 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 373 * +------------------------------------------------------+ 374 * 63 48 47 32 31 20 19 0 375 */ 376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 377 for (i = 0; i < rx_ring->count; i++) { 378 const char *next_desc; 379 buffer_info = &rx_ring->buffer_info[i]; 380 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 381 u1 = (struct my_u1 *)rx_desc_ps; 382 staterr = 383 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 384 385 if (i == rx_ring->next_to_use) 386 next_desc = " NTU"; 387 else if (i == rx_ring->next_to_clean) 388 next_desc = " NTC"; 389 else 390 next_desc = ""; 391 392 if (staterr & E1000_RXD_STAT_DD) { 393 /* Descriptor Done */ 394 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 395 "RWB", i, 396 (unsigned long long)le64_to_cpu(u1->a), 397 (unsigned long long)le64_to_cpu(u1->b), 398 (unsigned long long)le64_to_cpu(u1->c), 399 (unsigned long long)le64_to_cpu(u1->d), 400 buffer_info->skb, next_desc); 401 } else { 402 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 403 "R ", i, 404 (unsigned long long)le64_to_cpu(u1->a), 405 (unsigned long long)le64_to_cpu(u1->b), 406 (unsigned long long)le64_to_cpu(u1->c), 407 (unsigned long long)le64_to_cpu(u1->d), 408 (unsigned long long)buffer_info->dma, 409 buffer_info->skb, next_desc); 410 411 if (netif_msg_pktdata(adapter)) 412 e1000e_dump_ps_pages(adapter, 413 buffer_info); 414 } 415 } 416 break; 417 default: 418 case 0: 419 /* Extended Receive Descriptor (Read) Format 420 * 421 * +-----------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +-----------------------------------------------------+ 424 * 8 | Reserved | 425 * +-----------------------------------------------------+ 426 */ 427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 428 /* Extended Receive Descriptor (Write-Back) Format 429 * 430 * 63 48 47 32 31 24 23 4 3 0 431 * +------------------------------------------------------+ 432 * | RSS Hash | | | | 433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 434 * | Packet | IP | | | Type | 435 * | Checksum | Ident | | | | 436 * +------------------------------------------------------+ 437 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 438 * +------------------------------------------------------+ 439 * 63 48 47 32 31 20 19 0 440 */ 441 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 442 443 for (i = 0; i < rx_ring->count; i++) { 444 const char *next_desc; 445 446 buffer_info = &rx_ring->buffer_info[i]; 447 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 448 u1 = (struct my_u1 *)rx_desc; 449 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 450 451 if (i == rx_ring->next_to_use) 452 next_desc = " NTU"; 453 else if (i == rx_ring->next_to_clean) 454 next_desc = " NTC"; 455 else 456 next_desc = ""; 457 458 if (staterr & E1000_RXD_STAT_DD) { 459 /* Descriptor Done */ 460 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 461 "RWB", i, 462 (unsigned long long)le64_to_cpu(u1->a), 463 (unsigned long long)le64_to_cpu(u1->b), 464 buffer_info->skb, next_desc); 465 } else { 466 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 467 "R ", i, 468 (unsigned long long)le64_to_cpu(u1->a), 469 (unsigned long long)le64_to_cpu(u1->b), 470 (unsigned long long)buffer_info->dma, 471 buffer_info->skb, next_desc); 472 473 if (netif_msg_pktdata(adapter) && 474 buffer_info->skb) 475 print_hex_dump(KERN_INFO, "", 476 DUMP_PREFIX_ADDRESS, 16, 477 1, 478 buffer_info->skb->data, 479 adapter->rx_buffer_len, 480 true); 481 } 482 } 483 } 484 } 485 486 /** 487 * e1000_desc_unused - calculate if we have unused descriptors 488 **/ 489 static int e1000_desc_unused(struct e1000_ring *ring) 490 { 491 if (ring->next_to_clean > ring->next_to_use) 492 return ring->next_to_clean - ring->next_to_use - 1; 493 494 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 495 } 496 497 /** 498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 499 * @adapter: board private structure 500 * @hwtstamps: time stamp structure to update 501 * @systim: unsigned 64bit system time value. 502 * 503 * Convert the system time value stored in the RX/TXSTMP registers into a 504 * hwtstamp which can be used by the upper level time stamping functions. 505 * 506 * The 'systim_lock' spinlock is used to protect the consistency of the 507 * system time value. This is needed because reading the 64 bit time 508 * value involves reading two 32 bit registers. The first read latches the 509 * value. 510 **/ 511 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 512 struct skb_shared_hwtstamps *hwtstamps, 513 u64 systim) 514 { 515 u64 ns; 516 unsigned long flags; 517 518 spin_lock_irqsave(&adapter->systim_lock, flags); 519 ns = timecounter_cyc2time(&adapter->tc, systim); 520 spin_unlock_irqrestore(&adapter->systim_lock, flags); 521 522 memset(hwtstamps, 0, sizeof(*hwtstamps)); 523 hwtstamps->hwtstamp = ns_to_ktime(ns); 524 } 525 526 /** 527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 528 * @adapter: board private structure 529 * @status: descriptor extended error and status field 530 * @skb: particular skb to include time stamp 531 * 532 * If the time stamp is valid, convert it into the timecounter ns value 533 * and store that result into the shhwtstamps structure which is passed 534 * up the network stack. 535 **/ 536 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 537 struct sk_buff *skb) 538 { 539 struct e1000_hw *hw = &adapter->hw; 540 u64 rxstmp; 541 542 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 543 !(status & E1000_RXDEXT_STATERR_TST) || 544 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 545 return; 546 547 /* The Rx time stamp registers contain the time stamp. No other 548 * received packet will be time stamped until the Rx time stamp 549 * registers are read. Because only one packet can be time stamped 550 * at a time, the register values must belong to this packet and 551 * therefore none of the other additional attributes need to be 552 * compared. 553 */ 554 rxstmp = (u64)er32(RXSTMPL); 555 rxstmp |= (u64)er32(RXSTMPH) << 32; 556 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 557 558 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 559 } 560 561 /** 562 * e1000_receive_skb - helper function to handle Rx indications 563 * @adapter: board private structure 564 * @staterr: descriptor extended error and status field as written by hardware 565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 566 * @skb: pointer to sk_buff to be indicated to stack 567 **/ 568 static void e1000_receive_skb(struct e1000_adapter *adapter, 569 struct net_device *netdev, struct sk_buff *skb, 570 u32 staterr, __le16 vlan) 571 { 572 u16 tag = le16_to_cpu(vlan); 573 574 e1000e_rx_hwtstamp(adapter, staterr, skb); 575 576 skb->protocol = eth_type_trans(skb, netdev); 577 578 if (staterr & E1000_RXD_STAT_VP) 579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 580 581 napi_gro_receive(&adapter->napi, skb); 582 } 583 584 /** 585 * e1000_rx_checksum - Receive Checksum Offload 586 * @adapter: board private structure 587 * @status_err: receive descriptor status and error fields 588 * @csum: receive descriptor csum field 589 * @sk_buff: socket buffer with received data 590 **/ 591 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 592 struct sk_buff *skb) 593 { 594 u16 status = (u16)status_err; 595 u8 errors = (u8)(status_err >> 24); 596 597 skb_checksum_none_assert(skb); 598 599 /* Rx checksum disabled */ 600 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 601 return; 602 603 /* Ignore Checksum bit is set */ 604 if (status & E1000_RXD_STAT_IXSM) 605 return; 606 607 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 608 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 609 /* let the stack verify checksum errors */ 610 adapter->hw_csum_err++; 611 return; 612 } 613 614 /* TCP/UDP Checksum has not been calculated */ 615 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 616 return; 617 618 /* It must be a TCP or UDP packet with a valid checksum */ 619 skb->ip_summed = CHECKSUM_UNNECESSARY; 620 adapter->hw_csum_good++; 621 } 622 623 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 624 { 625 struct e1000_adapter *adapter = rx_ring->adapter; 626 struct e1000_hw *hw = &adapter->hw; 627 s32 ret_val = __ew32_prepare(hw); 628 629 writel(i, rx_ring->tail); 630 631 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 632 u32 rctl = er32(RCTL); 633 634 ew32(RCTL, rctl & ~E1000_RCTL_EN); 635 e_err("ME firmware caused invalid RDT - resetting\n"); 636 schedule_work(&adapter->reset_task); 637 } 638 } 639 640 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 641 { 642 struct e1000_adapter *adapter = tx_ring->adapter; 643 struct e1000_hw *hw = &adapter->hw; 644 s32 ret_val = __ew32_prepare(hw); 645 646 writel(i, tx_ring->tail); 647 648 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 649 u32 tctl = er32(TCTL); 650 651 ew32(TCTL, tctl & ~E1000_TCTL_EN); 652 e_err("ME firmware caused invalid TDT - resetting\n"); 653 schedule_work(&adapter->reset_task); 654 } 655 } 656 657 /** 658 * e1000_alloc_rx_buffers - Replace used receive buffers 659 * @rx_ring: Rx descriptor ring 660 **/ 661 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 662 int cleaned_count, gfp_t gfp) 663 { 664 struct e1000_adapter *adapter = rx_ring->adapter; 665 struct net_device *netdev = adapter->netdev; 666 struct pci_dev *pdev = adapter->pdev; 667 union e1000_rx_desc_extended *rx_desc; 668 struct e1000_buffer *buffer_info; 669 struct sk_buff *skb; 670 unsigned int i; 671 unsigned int bufsz = adapter->rx_buffer_len; 672 673 i = rx_ring->next_to_use; 674 buffer_info = &rx_ring->buffer_info[i]; 675 676 while (cleaned_count--) { 677 skb = buffer_info->skb; 678 if (skb) { 679 skb_trim(skb, 0); 680 goto map_skb; 681 } 682 683 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 684 if (!skb) { 685 /* Better luck next round */ 686 adapter->alloc_rx_buff_failed++; 687 break; 688 } 689 690 buffer_info->skb = skb; 691 map_skb: 692 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 693 adapter->rx_buffer_len, 694 DMA_FROM_DEVICE); 695 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 696 dev_err(&pdev->dev, "Rx DMA map failed\n"); 697 adapter->rx_dma_failed++; 698 break; 699 } 700 701 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 702 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 703 704 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 705 /* Force memory writes to complete before letting h/w 706 * know there are new descriptors to fetch. (Only 707 * applicable for weak-ordered memory model archs, 708 * such as IA-64). 709 */ 710 wmb(); 711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 712 e1000e_update_rdt_wa(rx_ring, i); 713 else 714 writel(i, rx_ring->tail); 715 } 716 i++; 717 if (i == rx_ring->count) 718 i = 0; 719 buffer_info = &rx_ring->buffer_info[i]; 720 } 721 722 rx_ring->next_to_use = i; 723 } 724 725 /** 726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 727 * @rx_ring: Rx descriptor ring 728 **/ 729 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 730 int cleaned_count, gfp_t gfp) 731 { 732 struct e1000_adapter *adapter = rx_ring->adapter; 733 struct net_device *netdev = adapter->netdev; 734 struct pci_dev *pdev = adapter->pdev; 735 union e1000_rx_desc_packet_split *rx_desc; 736 struct e1000_buffer *buffer_info; 737 struct e1000_ps_page *ps_page; 738 struct sk_buff *skb; 739 unsigned int i, j; 740 741 i = rx_ring->next_to_use; 742 buffer_info = &rx_ring->buffer_info[i]; 743 744 while (cleaned_count--) { 745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 746 747 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 748 ps_page = &buffer_info->ps_pages[j]; 749 if (j >= adapter->rx_ps_pages) { 750 /* all unused desc entries get hw null ptr */ 751 rx_desc->read.buffer_addr[j + 1] = 752 ~cpu_to_le64(0); 753 continue; 754 } 755 if (!ps_page->page) { 756 ps_page->page = alloc_page(gfp); 757 if (!ps_page->page) { 758 adapter->alloc_rx_buff_failed++; 759 goto no_buffers; 760 } 761 ps_page->dma = dma_map_page(&pdev->dev, 762 ps_page->page, 763 0, PAGE_SIZE, 764 DMA_FROM_DEVICE); 765 if (dma_mapping_error(&pdev->dev, 766 ps_page->dma)) { 767 dev_err(&adapter->pdev->dev, 768 "Rx DMA page map failed\n"); 769 adapter->rx_dma_failed++; 770 goto no_buffers; 771 } 772 } 773 /* Refresh the desc even if buffer_addrs 774 * didn't change because each write-back 775 * erases this info. 776 */ 777 rx_desc->read.buffer_addr[j + 1] = 778 cpu_to_le64(ps_page->dma); 779 } 780 781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 782 gfp); 783 784 if (!skb) { 785 adapter->alloc_rx_buff_failed++; 786 break; 787 } 788 789 buffer_info->skb = skb; 790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 791 adapter->rx_ps_bsize0, 792 DMA_FROM_DEVICE); 793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 794 dev_err(&pdev->dev, "Rx DMA map failed\n"); 795 adapter->rx_dma_failed++; 796 /* cleanup skb */ 797 dev_kfree_skb_any(skb); 798 buffer_info->skb = NULL; 799 break; 800 } 801 802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 803 804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 805 /* Force memory writes to complete before letting h/w 806 * know there are new descriptors to fetch. (Only 807 * applicable for weak-ordered memory model archs, 808 * such as IA-64). 809 */ 810 wmb(); 811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 812 e1000e_update_rdt_wa(rx_ring, i << 1); 813 else 814 writel(i << 1, rx_ring->tail); 815 } 816 817 i++; 818 if (i == rx_ring->count) 819 i = 0; 820 buffer_info = &rx_ring->buffer_info[i]; 821 } 822 823 no_buffers: 824 rx_ring->next_to_use = i; 825 } 826 827 /** 828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 829 * @rx_ring: Rx descriptor ring 830 * @cleaned_count: number of buffers to allocate this pass 831 **/ 832 833 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 834 int cleaned_count, gfp_t gfp) 835 { 836 struct e1000_adapter *adapter = rx_ring->adapter; 837 struct net_device *netdev = adapter->netdev; 838 struct pci_dev *pdev = adapter->pdev; 839 union e1000_rx_desc_extended *rx_desc; 840 struct e1000_buffer *buffer_info; 841 struct sk_buff *skb; 842 unsigned int i; 843 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 844 845 i = rx_ring->next_to_use; 846 buffer_info = &rx_ring->buffer_info[i]; 847 848 while (cleaned_count--) { 849 skb = buffer_info->skb; 850 if (skb) { 851 skb_trim(skb, 0); 852 goto check_page; 853 } 854 855 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 856 if (unlikely(!skb)) { 857 /* Better luck next round */ 858 adapter->alloc_rx_buff_failed++; 859 break; 860 } 861 862 buffer_info->skb = skb; 863 check_page: 864 /* allocate a new page if necessary */ 865 if (!buffer_info->page) { 866 buffer_info->page = alloc_page(gfp); 867 if (unlikely(!buffer_info->page)) { 868 adapter->alloc_rx_buff_failed++; 869 break; 870 } 871 } 872 873 if (!buffer_info->dma) { 874 buffer_info->dma = dma_map_page(&pdev->dev, 875 buffer_info->page, 0, 876 PAGE_SIZE, 877 DMA_FROM_DEVICE); 878 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 879 adapter->alloc_rx_buff_failed++; 880 break; 881 } 882 } 883 884 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 885 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 886 887 if (unlikely(++i == rx_ring->count)) 888 i = 0; 889 buffer_info = &rx_ring->buffer_info[i]; 890 } 891 892 if (likely(rx_ring->next_to_use != i)) { 893 rx_ring->next_to_use = i; 894 if (unlikely(i-- == 0)) 895 i = (rx_ring->count - 1); 896 897 /* Force memory writes to complete before letting h/w 898 * know there are new descriptors to fetch. (Only 899 * applicable for weak-ordered memory model archs, 900 * such as IA-64). 901 */ 902 wmb(); 903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 904 e1000e_update_rdt_wa(rx_ring, i); 905 else 906 writel(i, rx_ring->tail); 907 } 908 } 909 910 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 911 struct sk_buff *skb) 912 { 913 if (netdev->features & NETIF_F_RXHASH) 914 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 915 } 916 917 /** 918 * e1000_clean_rx_irq - Send received data up the network stack 919 * @rx_ring: Rx descriptor ring 920 * 921 * the return value indicates whether actual cleaning was done, there 922 * is no guarantee that everything was cleaned 923 **/ 924 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 925 int work_to_do) 926 { 927 struct e1000_adapter *adapter = rx_ring->adapter; 928 struct net_device *netdev = adapter->netdev; 929 struct pci_dev *pdev = adapter->pdev; 930 struct e1000_hw *hw = &adapter->hw; 931 union e1000_rx_desc_extended *rx_desc, *next_rxd; 932 struct e1000_buffer *buffer_info, *next_buffer; 933 u32 length, staterr; 934 unsigned int i; 935 int cleaned_count = 0; 936 bool cleaned = false; 937 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 938 939 i = rx_ring->next_to_clean; 940 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 941 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 942 buffer_info = &rx_ring->buffer_info[i]; 943 944 while (staterr & E1000_RXD_STAT_DD) { 945 struct sk_buff *skb; 946 947 if (*work_done >= work_to_do) 948 break; 949 (*work_done)++; 950 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 951 952 skb = buffer_info->skb; 953 buffer_info->skb = NULL; 954 955 prefetch(skb->data - NET_IP_ALIGN); 956 957 i++; 958 if (i == rx_ring->count) 959 i = 0; 960 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 961 prefetch(next_rxd); 962 963 next_buffer = &rx_ring->buffer_info[i]; 964 965 cleaned = true; 966 cleaned_count++; 967 dma_unmap_single(&pdev->dev, buffer_info->dma, 968 adapter->rx_buffer_len, DMA_FROM_DEVICE); 969 buffer_info->dma = 0; 970 971 length = le16_to_cpu(rx_desc->wb.upper.length); 972 973 /* !EOP means multiple descriptors were used to store a single 974 * packet, if that's the case we need to toss it. In fact, we 975 * need to toss every packet with the EOP bit clear and the 976 * next frame that _does_ have the EOP bit set, as it is by 977 * definition only a frame fragment 978 */ 979 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 980 adapter->flags2 |= FLAG2_IS_DISCARDING; 981 982 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 983 /* All receives must fit into a single buffer */ 984 e_dbg("Receive packet consumed multiple buffers\n"); 985 /* recycle */ 986 buffer_info->skb = skb; 987 if (staterr & E1000_RXD_STAT_EOP) 988 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 989 goto next_desc; 990 } 991 992 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 993 !(netdev->features & NETIF_F_RXALL))) { 994 /* recycle */ 995 buffer_info->skb = skb; 996 goto next_desc; 997 } 998 999 /* adjust length to remove Ethernet CRC */ 1000 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1001 /* If configured to store CRC, don't subtract FCS, 1002 * but keep the FCS bytes out of the total_rx_bytes 1003 * counter 1004 */ 1005 if (netdev->features & NETIF_F_RXFCS) 1006 total_rx_bytes -= 4; 1007 else 1008 length -= 4; 1009 } 1010 1011 total_rx_bytes += length; 1012 total_rx_packets++; 1013 1014 /* code added for copybreak, this should improve 1015 * performance for small packets with large amounts 1016 * of reassembly being done in the stack 1017 */ 1018 if (length < copybreak) { 1019 struct sk_buff *new_skb = 1020 napi_alloc_skb(&adapter->napi, length); 1021 if (new_skb) { 1022 skb_copy_to_linear_data_offset(new_skb, 1023 -NET_IP_ALIGN, 1024 (skb->data - 1025 NET_IP_ALIGN), 1026 (length + 1027 NET_IP_ALIGN)); 1028 /* save the skb in buffer_info as good */ 1029 buffer_info->skb = skb; 1030 skb = new_skb; 1031 } 1032 /* else just continue with the old one */ 1033 } 1034 /* end copybreak code */ 1035 skb_put(skb, length); 1036 1037 /* Receive Checksum Offload */ 1038 e1000_rx_checksum(adapter, staterr, skb); 1039 1040 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1041 1042 e1000_receive_skb(adapter, netdev, skb, staterr, 1043 rx_desc->wb.upper.vlan); 1044 1045 next_desc: 1046 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1047 1048 /* return some buffers to hardware, one at a time is too slow */ 1049 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1050 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1051 GFP_ATOMIC); 1052 cleaned_count = 0; 1053 } 1054 1055 /* use prefetched values */ 1056 rx_desc = next_rxd; 1057 buffer_info = next_buffer; 1058 1059 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1060 } 1061 rx_ring->next_to_clean = i; 1062 1063 cleaned_count = e1000_desc_unused(rx_ring); 1064 if (cleaned_count) 1065 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1066 1067 adapter->total_rx_bytes += total_rx_bytes; 1068 adapter->total_rx_packets += total_rx_packets; 1069 return cleaned; 1070 } 1071 1072 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1073 struct e1000_buffer *buffer_info) 1074 { 1075 struct e1000_adapter *adapter = tx_ring->adapter; 1076 1077 if (buffer_info->dma) { 1078 if (buffer_info->mapped_as_page) 1079 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1080 buffer_info->length, DMA_TO_DEVICE); 1081 else 1082 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1083 buffer_info->length, DMA_TO_DEVICE); 1084 buffer_info->dma = 0; 1085 } 1086 if (buffer_info->skb) { 1087 dev_kfree_skb_any(buffer_info->skb); 1088 buffer_info->skb = NULL; 1089 } 1090 buffer_info->time_stamp = 0; 1091 } 1092 1093 static void e1000_print_hw_hang(struct work_struct *work) 1094 { 1095 struct e1000_adapter *adapter = container_of(work, 1096 struct e1000_adapter, 1097 print_hang_task); 1098 struct net_device *netdev = adapter->netdev; 1099 struct e1000_ring *tx_ring = adapter->tx_ring; 1100 unsigned int i = tx_ring->next_to_clean; 1101 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1102 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1103 struct e1000_hw *hw = &adapter->hw; 1104 u16 phy_status, phy_1000t_status, phy_ext_status; 1105 u16 pci_status; 1106 1107 if (test_bit(__E1000_DOWN, &adapter->state)) 1108 return; 1109 1110 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1111 /* May be block on write-back, flush and detect again 1112 * flush pending descriptor writebacks to memory 1113 */ 1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1115 /* execute the writes immediately */ 1116 e1e_flush(); 1117 /* Due to rare timing issues, write to TIDV again to ensure 1118 * the write is successful 1119 */ 1120 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1121 /* execute the writes immediately */ 1122 e1e_flush(); 1123 adapter->tx_hang_recheck = true; 1124 return; 1125 } 1126 adapter->tx_hang_recheck = false; 1127 1128 if (er32(TDH(0)) == er32(TDT(0))) { 1129 e_dbg("false hang detected, ignoring\n"); 1130 return; 1131 } 1132 1133 /* Real hang detected */ 1134 netif_stop_queue(netdev); 1135 1136 e1e_rphy(hw, MII_BMSR, &phy_status); 1137 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1138 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1139 1140 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1141 1142 /* detected Hardware unit hang */ 1143 e_err("Detected Hardware Unit Hang:\n" 1144 " TDH <%x>\n" 1145 " TDT <%x>\n" 1146 " next_to_use <%x>\n" 1147 " next_to_clean <%x>\n" 1148 "buffer_info[next_to_clean]:\n" 1149 " time_stamp <%lx>\n" 1150 " next_to_watch <%x>\n" 1151 " jiffies <%lx>\n" 1152 " next_to_watch.status <%x>\n" 1153 "MAC Status <%x>\n" 1154 "PHY Status <%x>\n" 1155 "PHY 1000BASE-T Status <%x>\n" 1156 "PHY Extended Status <%x>\n" 1157 "PCI Status <%x>\n", 1158 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1159 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1160 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1161 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1162 1163 e1000e_dump(adapter); 1164 1165 /* Suggest workaround for known h/w issue */ 1166 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1167 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1168 } 1169 1170 /** 1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1172 * @work: pointer to work struct 1173 * 1174 * This work function polls the TSYNCTXCTL valid bit to determine when a 1175 * timestamp has been taken for the current stored skb. The timestamp must 1176 * be for this skb because only one such packet is allowed in the queue. 1177 */ 1178 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1179 { 1180 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1181 tx_hwtstamp_work); 1182 struct e1000_hw *hw = &adapter->hw; 1183 1184 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1185 struct skb_shared_hwtstamps shhwtstamps; 1186 u64 txstmp; 1187 1188 txstmp = er32(TXSTMPL); 1189 txstmp |= (u64)er32(TXSTMPH) << 32; 1190 1191 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1192 1193 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps); 1194 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1195 adapter->tx_hwtstamp_skb = NULL; 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1197 + adapter->tx_timeout_factor * HZ)) { 1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1199 adapter->tx_hwtstamp_skb = NULL; 1200 adapter->tx_hwtstamp_timeouts++; 1201 e_warn("clearing Tx timestamp hang\n"); 1202 } else { 1203 /* reschedule to check later */ 1204 schedule_work(&adapter->tx_hwtstamp_work); 1205 } 1206 } 1207 1208 /** 1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1210 * @tx_ring: Tx descriptor ring 1211 * 1212 * the return value indicates whether actual cleaning was done, there 1213 * is no guarantee that everything was cleaned 1214 **/ 1215 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1216 { 1217 struct e1000_adapter *adapter = tx_ring->adapter; 1218 struct net_device *netdev = adapter->netdev; 1219 struct e1000_hw *hw = &adapter->hw; 1220 struct e1000_tx_desc *tx_desc, *eop_desc; 1221 struct e1000_buffer *buffer_info; 1222 unsigned int i, eop; 1223 unsigned int count = 0; 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1225 unsigned int bytes_compl = 0, pkts_compl = 0; 1226 1227 i = tx_ring->next_to_clean; 1228 eop = tx_ring->buffer_info[i].next_to_watch; 1229 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1230 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1232 (count < tx_ring->count)) { 1233 bool cleaned = false; 1234 1235 dma_rmb(); /* read buffer_info after eop_desc */ 1236 for (; !cleaned; count++) { 1237 tx_desc = E1000_TX_DESC(*tx_ring, i); 1238 buffer_info = &tx_ring->buffer_info[i]; 1239 cleaned = (i == eop); 1240 1241 if (cleaned) { 1242 total_tx_packets += buffer_info->segs; 1243 total_tx_bytes += buffer_info->bytecount; 1244 if (buffer_info->skb) { 1245 bytes_compl += buffer_info->skb->len; 1246 pkts_compl++; 1247 } 1248 } 1249 1250 e1000_put_txbuf(tx_ring, buffer_info); 1251 tx_desc->upper.data = 0; 1252 1253 i++; 1254 if (i == tx_ring->count) 1255 i = 0; 1256 } 1257 1258 if (i == tx_ring->next_to_use) 1259 break; 1260 eop = tx_ring->buffer_info[i].next_to_watch; 1261 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1262 } 1263 1264 tx_ring->next_to_clean = i; 1265 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1267 1268 #define TX_WAKE_THRESHOLD 32 1269 if (count && netif_carrier_ok(netdev) && 1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1271 /* Make sure that anybody stopping the queue after this 1272 * sees the new next_to_clean. 1273 */ 1274 smp_mb(); 1275 1276 if (netif_queue_stopped(netdev) && 1277 !(test_bit(__E1000_DOWN, &adapter->state))) { 1278 netif_wake_queue(netdev); 1279 ++adapter->restart_queue; 1280 } 1281 } 1282 1283 if (adapter->detect_tx_hung) { 1284 /* Detect a transmit hang in hardware, this serializes the 1285 * check with the clearing of time_stamp and movement of i 1286 */ 1287 adapter->detect_tx_hung = false; 1288 if (tx_ring->buffer_info[i].time_stamp && 1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1290 + (adapter->tx_timeout_factor * HZ)) && 1291 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1292 schedule_work(&adapter->print_hang_task); 1293 else 1294 adapter->tx_hang_recheck = false; 1295 } 1296 adapter->total_tx_bytes += total_tx_bytes; 1297 adapter->total_tx_packets += total_tx_packets; 1298 return count < tx_ring->count; 1299 } 1300 1301 /** 1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1303 * @rx_ring: Rx descriptor ring 1304 * 1305 * the return value indicates whether actual cleaning was done, there 1306 * is no guarantee that everything was cleaned 1307 **/ 1308 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1309 int work_to_do) 1310 { 1311 struct e1000_adapter *adapter = rx_ring->adapter; 1312 struct e1000_hw *hw = &adapter->hw; 1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1314 struct net_device *netdev = adapter->netdev; 1315 struct pci_dev *pdev = adapter->pdev; 1316 struct e1000_buffer *buffer_info, *next_buffer; 1317 struct e1000_ps_page *ps_page; 1318 struct sk_buff *skb; 1319 unsigned int i, j; 1320 u32 length, staterr; 1321 int cleaned_count = 0; 1322 bool cleaned = false; 1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1324 1325 i = rx_ring->next_to_clean; 1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1328 buffer_info = &rx_ring->buffer_info[i]; 1329 1330 while (staterr & E1000_RXD_STAT_DD) { 1331 if (*work_done >= work_to_do) 1332 break; 1333 (*work_done)++; 1334 skb = buffer_info->skb; 1335 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1336 1337 /* in the packet split case this is header only */ 1338 prefetch(skb->data - NET_IP_ALIGN); 1339 1340 i++; 1341 if (i == rx_ring->count) 1342 i = 0; 1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1344 prefetch(next_rxd); 1345 1346 next_buffer = &rx_ring->buffer_info[i]; 1347 1348 cleaned = true; 1349 cleaned_count++; 1350 dma_unmap_single(&pdev->dev, buffer_info->dma, 1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1352 buffer_info->dma = 0; 1353 1354 /* see !EOP comment in other Rx routine */ 1355 if (!(staterr & E1000_RXD_STAT_EOP)) 1356 adapter->flags2 |= FLAG2_IS_DISCARDING; 1357 1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1359 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1360 dev_kfree_skb_irq(skb); 1361 if (staterr & E1000_RXD_STAT_EOP) 1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1363 goto next_desc; 1364 } 1365 1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1367 !(netdev->features & NETIF_F_RXALL))) { 1368 dev_kfree_skb_irq(skb); 1369 goto next_desc; 1370 } 1371 1372 length = le16_to_cpu(rx_desc->wb.middle.length0); 1373 1374 if (!length) { 1375 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1376 dev_kfree_skb_irq(skb); 1377 goto next_desc; 1378 } 1379 1380 /* Good Receive */ 1381 skb_put(skb, length); 1382 1383 { 1384 /* this looks ugly, but it seems compiler issues make 1385 * it more efficient than reusing j 1386 */ 1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1388 1389 /* page alloc/put takes too long and effects small 1390 * packet throughput, so unsplit small packets and 1391 * save the alloc/put only valid in softirq (napi) 1392 * context to call kmap_* 1393 */ 1394 if (l1 && (l1 <= copybreak) && 1395 ((length + l1) <= adapter->rx_ps_bsize0)) { 1396 u8 *vaddr; 1397 1398 ps_page = &buffer_info->ps_pages[0]; 1399 1400 /* there is no documentation about how to call 1401 * kmap_atomic, so we can't hold the mapping 1402 * very long 1403 */ 1404 dma_sync_single_for_cpu(&pdev->dev, 1405 ps_page->dma, 1406 PAGE_SIZE, 1407 DMA_FROM_DEVICE); 1408 vaddr = kmap_atomic(ps_page->page); 1409 memcpy(skb_tail_pointer(skb), vaddr, l1); 1410 kunmap_atomic(vaddr); 1411 dma_sync_single_for_device(&pdev->dev, 1412 ps_page->dma, 1413 PAGE_SIZE, 1414 DMA_FROM_DEVICE); 1415 1416 /* remove the CRC */ 1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1418 if (!(netdev->features & NETIF_F_RXFCS)) 1419 l1 -= 4; 1420 } 1421 1422 skb_put(skb, l1); 1423 goto copydone; 1424 } /* if */ 1425 } 1426 1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1429 if (!length) 1430 break; 1431 1432 ps_page = &buffer_info->ps_pages[j]; 1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1434 DMA_FROM_DEVICE); 1435 ps_page->dma = 0; 1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1437 ps_page->page = NULL; 1438 skb->len += length; 1439 skb->data_len += length; 1440 skb->truesize += PAGE_SIZE; 1441 } 1442 1443 /* strip the ethernet crc, problem is we're using pages now so 1444 * this whole operation can get a little cpu intensive 1445 */ 1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1447 if (!(netdev->features & NETIF_F_RXFCS)) 1448 pskb_trim(skb, skb->len - 4); 1449 } 1450 1451 copydone: 1452 total_rx_bytes += skb->len; 1453 total_rx_packets++; 1454 1455 e1000_rx_checksum(adapter, staterr, skb); 1456 1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1458 1459 if (rx_desc->wb.upper.header_status & 1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1461 adapter->rx_hdr_split++; 1462 1463 e1000_receive_skb(adapter, netdev, skb, staterr, 1464 rx_desc->wb.middle.vlan); 1465 1466 next_desc: 1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1468 buffer_info->skb = NULL; 1469 1470 /* return some buffers to hardware, one at a time is too slow */ 1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1472 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1473 GFP_ATOMIC); 1474 cleaned_count = 0; 1475 } 1476 1477 /* use prefetched values */ 1478 rx_desc = next_rxd; 1479 buffer_info = next_buffer; 1480 1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1482 } 1483 rx_ring->next_to_clean = i; 1484 1485 cleaned_count = e1000_desc_unused(rx_ring); 1486 if (cleaned_count) 1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1488 1489 adapter->total_rx_bytes += total_rx_bytes; 1490 adapter->total_rx_packets += total_rx_packets; 1491 return cleaned; 1492 } 1493 1494 /** 1495 * e1000_consume_page - helper function 1496 **/ 1497 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1498 u16 length) 1499 { 1500 bi->page = NULL; 1501 skb->len += length; 1502 skb->data_len += length; 1503 skb->truesize += PAGE_SIZE; 1504 } 1505 1506 /** 1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1508 * @adapter: board private structure 1509 * 1510 * the return value indicates whether actual cleaning was done, there 1511 * is no guarantee that everything was cleaned 1512 **/ 1513 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1514 int work_to_do) 1515 { 1516 struct e1000_adapter *adapter = rx_ring->adapter; 1517 struct net_device *netdev = adapter->netdev; 1518 struct pci_dev *pdev = adapter->pdev; 1519 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1520 struct e1000_buffer *buffer_info, *next_buffer; 1521 u32 length, staterr; 1522 unsigned int i; 1523 int cleaned_count = 0; 1524 bool cleaned = false; 1525 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1526 struct skb_shared_info *shinfo; 1527 1528 i = rx_ring->next_to_clean; 1529 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1531 buffer_info = &rx_ring->buffer_info[i]; 1532 1533 while (staterr & E1000_RXD_STAT_DD) { 1534 struct sk_buff *skb; 1535 1536 if (*work_done >= work_to_do) 1537 break; 1538 (*work_done)++; 1539 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1540 1541 skb = buffer_info->skb; 1542 buffer_info->skb = NULL; 1543 1544 ++i; 1545 if (i == rx_ring->count) 1546 i = 0; 1547 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1548 prefetch(next_rxd); 1549 1550 next_buffer = &rx_ring->buffer_info[i]; 1551 1552 cleaned = true; 1553 cleaned_count++; 1554 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1555 DMA_FROM_DEVICE); 1556 buffer_info->dma = 0; 1557 1558 length = le16_to_cpu(rx_desc->wb.upper.length); 1559 1560 /* errors is only valid for DD + EOP descriptors */ 1561 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1562 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1563 !(netdev->features & NETIF_F_RXALL)))) { 1564 /* recycle both page and skb */ 1565 buffer_info->skb = skb; 1566 /* an error means any chain goes out the window too */ 1567 if (rx_ring->rx_skb_top) 1568 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1569 rx_ring->rx_skb_top = NULL; 1570 goto next_desc; 1571 } 1572 #define rxtop (rx_ring->rx_skb_top) 1573 if (!(staterr & E1000_RXD_STAT_EOP)) { 1574 /* this descriptor is only the beginning (or middle) */ 1575 if (!rxtop) { 1576 /* this is the beginning of a chain */ 1577 rxtop = skb; 1578 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1579 0, length); 1580 } else { 1581 /* this is the middle of a chain */ 1582 shinfo = skb_shinfo(rxtop); 1583 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1584 buffer_info->page, 0, 1585 length); 1586 /* re-use the skb, only consumed the page */ 1587 buffer_info->skb = skb; 1588 } 1589 e1000_consume_page(buffer_info, rxtop, length); 1590 goto next_desc; 1591 } else { 1592 if (rxtop) { 1593 /* end of the chain */ 1594 shinfo = skb_shinfo(rxtop); 1595 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1596 buffer_info->page, 0, 1597 length); 1598 /* re-use the current skb, we only consumed the 1599 * page 1600 */ 1601 buffer_info->skb = skb; 1602 skb = rxtop; 1603 rxtop = NULL; 1604 e1000_consume_page(buffer_info, skb, length); 1605 } else { 1606 /* no chain, got EOP, this buf is the packet 1607 * copybreak to save the put_page/alloc_page 1608 */ 1609 if (length <= copybreak && 1610 skb_tailroom(skb) >= length) { 1611 u8 *vaddr; 1612 vaddr = kmap_atomic(buffer_info->page); 1613 memcpy(skb_tail_pointer(skb), vaddr, 1614 length); 1615 kunmap_atomic(vaddr); 1616 /* re-use the page, so don't erase 1617 * buffer_info->page 1618 */ 1619 skb_put(skb, length); 1620 } else { 1621 skb_fill_page_desc(skb, 0, 1622 buffer_info->page, 0, 1623 length); 1624 e1000_consume_page(buffer_info, skb, 1625 length); 1626 } 1627 } 1628 } 1629 1630 /* Receive Checksum Offload */ 1631 e1000_rx_checksum(adapter, staterr, skb); 1632 1633 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1634 1635 /* probably a little skewed due to removing CRC */ 1636 total_rx_bytes += skb->len; 1637 total_rx_packets++; 1638 1639 /* eth type trans needs skb->data to point to something */ 1640 if (!pskb_may_pull(skb, ETH_HLEN)) { 1641 e_err("pskb_may_pull failed.\n"); 1642 dev_kfree_skb_irq(skb); 1643 goto next_desc; 1644 } 1645 1646 e1000_receive_skb(adapter, netdev, skb, staterr, 1647 rx_desc->wb.upper.vlan); 1648 1649 next_desc: 1650 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1651 1652 /* return some buffers to hardware, one at a time is too slow */ 1653 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1654 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1655 GFP_ATOMIC); 1656 cleaned_count = 0; 1657 } 1658 1659 /* use prefetched values */ 1660 rx_desc = next_rxd; 1661 buffer_info = next_buffer; 1662 1663 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1664 } 1665 rx_ring->next_to_clean = i; 1666 1667 cleaned_count = e1000_desc_unused(rx_ring); 1668 if (cleaned_count) 1669 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1670 1671 adapter->total_rx_bytes += total_rx_bytes; 1672 adapter->total_rx_packets += total_rx_packets; 1673 return cleaned; 1674 } 1675 1676 /** 1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1678 * @rx_ring: Rx descriptor ring 1679 **/ 1680 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1681 { 1682 struct e1000_adapter *adapter = rx_ring->adapter; 1683 struct e1000_buffer *buffer_info; 1684 struct e1000_ps_page *ps_page; 1685 struct pci_dev *pdev = adapter->pdev; 1686 unsigned int i, j; 1687 1688 /* Free all the Rx ring sk_buffs */ 1689 for (i = 0; i < rx_ring->count; i++) { 1690 buffer_info = &rx_ring->buffer_info[i]; 1691 if (buffer_info->dma) { 1692 if (adapter->clean_rx == e1000_clean_rx_irq) 1693 dma_unmap_single(&pdev->dev, buffer_info->dma, 1694 adapter->rx_buffer_len, 1695 DMA_FROM_DEVICE); 1696 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1697 dma_unmap_page(&pdev->dev, buffer_info->dma, 1698 PAGE_SIZE, DMA_FROM_DEVICE); 1699 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1700 dma_unmap_single(&pdev->dev, buffer_info->dma, 1701 adapter->rx_ps_bsize0, 1702 DMA_FROM_DEVICE); 1703 buffer_info->dma = 0; 1704 } 1705 1706 if (buffer_info->page) { 1707 put_page(buffer_info->page); 1708 buffer_info->page = NULL; 1709 } 1710 1711 if (buffer_info->skb) { 1712 dev_kfree_skb(buffer_info->skb); 1713 buffer_info->skb = NULL; 1714 } 1715 1716 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1717 ps_page = &buffer_info->ps_pages[j]; 1718 if (!ps_page->page) 1719 break; 1720 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1721 DMA_FROM_DEVICE); 1722 ps_page->dma = 0; 1723 put_page(ps_page->page); 1724 ps_page->page = NULL; 1725 } 1726 } 1727 1728 /* there also may be some cached data from a chained receive */ 1729 if (rx_ring->rx_skb_top) { 1730 dev_kfree_skb(rx_ring->rx_skb_top); 1731 rx_ring->rx_skb_top = NULL; 1732 } 1733 1734 /* Zero out the descriptor ring */ 1735 memset(rx_ring->desc, 0, rx_ring->size); 1736 1737 rx_ring->next_to_clean = 0; 1738 rx_ring->next_to_use = 0; 1739 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1740 1741 writel(0, rx_ring->head); 1742 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 1743 e1000e_update_rdt_wa(rx_ring, 0); 1744 else 1745 writel(0, rx_ring->tail); 1746 } 1747 1748 static void e1000e_downshift_workaround(struct work_struct *work) 1749 { 1750 struct e1000_adapter *adapter = container_of(work, 1751 struct e1000_adapter, 1752 downshift_task); 1753 1754 if (test_bit(__E1000_DOWN, &adapter->state)) 1755 return; 1756 1757 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1758 } 1759 1760 /** 1761 * e1000_intr_msi - Interrupt Handler 1762 * @irq: interrupt number 1763 * @data: pointer to a network interface device structure 1764 **/ 1765 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1766 { 1767 struct net_device *netdev = data; 1768 struct e1000_adapter *adapter = netdev_priv(netdev); 1769 struct e1000_hw *hw = &adapter->hw; 1770 u32 icr = er32(ICR); 1771 1772 /* read ICR disables interrupts using IAM */ 1773 if (icr & E1000_ICR_LSC) { 1774 hw->mac.get_link_status = true; 1775 /* ICH8 workaround-- Call gig speed drop workaround on cable 1776 * disconnect (LSC) before accessing any PHY registers 1777 */ 1778 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1779 (!(er32(STATUS) & E1000_STATUS_LU))) 1780 schedule_work(&adapter->downshift_task); 1781 1782 /* 80003ES2LAN workaround-- For packet buffer work-around on 1783 * link down event; disable receives here in the ISR and reset 1784 * adapter in watchdog 1785 */ 1786 if (netif_carrier_ok(netdev) && 1787 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1788 /* disable receives */ 1789 u32 rctl = er32(RCTL); 1790 1791 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1792 adapter->flags |= FLAG_RESTART_NOW; 1793 } 1794 /* guard against interrupt when we're going down */ 1795 if (!test_bit(__E1000_DOWN, &adapter->state)) 1796 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1797 } 1798 1799 /* Reset on uncorrectable ECC error */ 1800 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) || 1801 (hw->mac.type == e1000_pch_spt))) { 1802 u32 pbeccsts = er32(PBECCSTS); 1803 1804 adapter->corr_errors += 1805 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1806 adapter->uncorr_errors += 1807 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1808 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1809 1810 /* Do the reset outside of interrupt context */ 1811 schedule_work(&adapter->reset_task); 1812 1813 /* return immediately since reset is imminent */ 1814 return IRQ_HANDLED; 1815 } 1816 1817 if (napi_schedule_prep(&adapter->napi)) { 1818 adapter->total_tx_bytes = 0; 1819 adapter->total_tx_packets = 0; 1820 adapter->total_rx_bytes = 0; 1821 adapter->total_rx_packets = 0; 1822 __napi_schedule(&adapter->napi); 1823 } 1824 1825 return IRQ_HANDLED; 1826 } 1827 1828 /** 1829 * e1000_intr - Interrupt Handler 1830 * @irq: interrupt number 1831 * @data: pointer to a network interface device structure 1832 **/ 1833 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1834 { 1835 struct net_device *netdev = data; 1836 struct e1000_adapter *adapter = netdev_priv(netdev); 1837 struct e1000_hw *hw = &adapter->hw; 1838 u32 rctl, icr = er32(ICR); 1839 1840 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1841 return IRQ_NONE; /* Not our interrupt */ 1842 1843 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1844 * not set, then the adapter didn't send an interrupt 1845 */ 1846 if (!(icr & E1000_ICR_INT_ASSERTED)) 1847 return IRQ_NONE; 1848 1849 /* Interrupt Auto-Mask...upon reading ICR, 1850 * interrupts are masked. No need for the 1851 * IMC write 1852 */ 1853 1854 if (icr & E1000_ICR_LSC) { 1855 hw->mac.get_link_status = true; 1856 /* ICH8 workaround-- Call gig speed drop workaround on cable 1857 * disconnect (LSC) before accessing any PHY registers 1858 */ 1859 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1860 (!(er32(STATUS) & E1000_STATUS_LU))) 1861 schedule_work(&adapter->downshift_task); 1862 1863 /* 80003ES2LAN workaround-- 1864 * For packet buffer work-around on link down event; 1865 * disable receives here in the ISR and 1866 * reset adapter in watchdog 1867 */ 1868 if (netif_carrier_ok(netdev) && 1869 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1870 /* disable receives */ 1871 rctl = er32(RCTL); 1872 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1873 adapter->flags |= FLAG_RESTART_NOW; 1874 } 1875 /* guard against interrupt when we're going down */ 1876 if (!test_bit(__E1000_DOWN, &adapter->state)) 1877 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1878 } 1879 1880 /* Reset on uncorrectable ECC error */ 1881 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) || 1882 (hw->mac.type == e1000_pch_spt))) { 1883 u32 pbeccsts = er32(PBECCSTS); 1884 1885 adapter->corr_errors += 1886 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1887 adapter->uncorr_errors += 1888 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1889 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1890 1891 /* Do the reset outside of interrupt context */ 1892 schedule_work(&adapter->reset_task); 1893 1894 /* return immediately since reset is imminent */ 1895 return IRQ_HANDLED; 1896 } 1897 1898 if (napi_schedule_prep(&adapter->napi)) { 1899 adapter->total_tx_bytes = 0; 1900 adapter->total_tx_packets = 0; 1901 adapter->total_rx_bytes = 0; 1902 adapter->total_rx_packets = 0; 1903 __napi_schedule(&adapter->napi); 1904 } 1905 1906 return IRQ_HANDLED; 1907 } 1908 1909 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1910 { 1911 struct net_device *netdev = data; 1912 struct e1000_adapter *adapter = netdev_priv(netdev); 1913 struct e1000_hw *hw = &adapter->hw; 1914 u32 icr = er32(ICR); 1915 1916 if (!(icr & E1000_ICR_INT_ASSERTED)) { 1917 if (!test_bit(__E1000_DOWN, &adapter->state)) 1918 ew32(IMS, E1000_IMS_OTHER); 1919 return IRQ_NONE; 1920 } 1921 1922 if (icr & adapter->eiac_mask) 1923 ew32(ICS, (icr & adapter->eiac_mask)); 1924 1925 if (icr & E1000_ICR_OTHER) { 1926 if (!(icr & E1000_ICR_LSC)) 1927 goto no_link_interrupt; 1928 hw->mac.get_link_status = true; 1929 /* guard against interrupt when we're going down */ 1930 if (!test_bit(__E1000_DOWN, &adapter->state)) 1931 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1932 } 1933 1934 no_link_interrupt: 1935 if (!test_bit(__E1000_DOWN, &adapter->state)) 1936 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1937 1938 return IRQ_HANDLED; 1939 } 1940 1941 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1942 { 1943 struct net_device *netdev = data; 1944 struct e1000_adapter *adapter = netdev_priv(netdev); 1945 struct e1000_hw *hw = &adapter->hw; 1946 struct e1000_ring *tx_ring = adapter->tx_ring; 1947 1948 adapter->total_tx_bytes = 0; 1949 adapter->total_tx_packets = 0; 1950 1951 if (!e1000_clean_tx_irq(tx_ring)) 1952 /* Ring was not completely cleaned, so fire another interrupt */ 1953 ew32(ICS, tx_ring->ims_val); 1954 1955 return IRQ_HANDLED; 1956 } 1957 1958 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1959 { 1960 struct net_device *netdev = data; 1961 struct e1000_adapter *adapter = netdev_priv(netdev); 1962 struct e1000_ring *rx_ring = adapter->rx_ring; 1963 1964 /* Write the ITR value calculated at the end of the 1965 * previous interrupt. 1966 */ 1967 if (rx_ring->set_itr) { 1968 writel(1000000000 / (rx_ring->itr_val * 256), 1969 rx_ring->itr_register); 1970 rx_ring->set_itr = 0; 1971 } 1972 1973 if (napi_schedule_prep(&adapter->napi)) { 1974 adapter->total_rx_bytes = 0; 1975 adapter->total_rx_packets = 0; 1976 __napi_schedule(&adapter->napi); 1977 } 1978 return IRQ_HANDLED; 1979 } 1980 1981 /** 1982 * e1000_configure_msix - Configure MSI-X hardware 1983 * 1984 * e1000_configure_msix sets up the hardware to properly 1985 * generate MSI-X interrupts. 1986 **/ 1987 static void e1000_configure_msix(struct e1000_adapter *adapter) 1988 { 1989 struct e1000_hw *hw = &adapter->hw; 1990 struct e1000_ring *rx_ring = adapter->rx_ring; 1991 struct e1000_ring *tx_ring = adapter->tx_ring; 1992 int vector = 0; 1993 u32 ctrl_ext, ivar = 0; 1994 1995 adapter->eiac_mask = 0; 1996 1997 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 1998 if (hw->mac.type == e1000_82574) { 1999 u32 rfctl = er32(RFCTL); 2000 2001 rfctl |= E1000_RFCTL_ACK_DIS; 2002 ew32(RFCTL, rfctl); 2003 } 2004 2005 /* Configure Rx vector */ 2006 rx_ring->ims_val = E1000_IMS_RXQ0; 2007 adapter->eiac_mask |= rx_ring->ims_val; 2008 if (rx_ring->itr_val) 2009 writel(1000000000 / (rx_ring->itr_val * 256), 2010 rx_ring->itr_register); 2011 else 2012 writel(1, rx_ring->itr_register); 2013 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2014 2015 /* Configure Tx vector */ 2016 tx_ring->ims_val = E1000_IMS_TXQ0; 2017 vector++; 2018 if (tx_ring->itr_val) 2019 writel(1000000000 / (tx_ring->itr_val * 256), 2020 tx_ring->itr_register); 2021 else 2022 writel(1, tx_ring->itr_register); 2023 adapter->eiac_mask |= tx_ring->ims_val; 2024 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2025 2026 /* set vector for Other Causes, e.g. link changes */ 2027 vector++; 2028 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2029 if (rx_ring->itr_val) 2030 writel(1000000000 / (rx_ring->itr_val * 256), 2031 hw->hw_addr + E1000_EITR_82574(vector)); 2032 else 2033 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2034 2035 /* Cause Tx interrupts on every write back */ 2036 ivar |= (1 << 31); 2037 2038 ew32(IVAR, ivar); 2039 2040 /* enable MSI-X PBA support */ 2041 ctrl_ext = er32(CTRL_EXT); 2042 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR; 2043 2044 /* Auto-Mask Other interrupts upon ICR read */ 2045 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER); 2046 ctrl_ext |= E1000_CTRL_EXT_EIAME; 2047 ew32(CTRL_EXT, ctrl_ext); 2048 e1e_flush(); 2049 } 2050 2051 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2052 { 2053 if (adapter->msix_entries) { 2054 pci_disable_msix(adapter->pdev); 2055 kfree(adapter->msix_entries); 2056 adapter->msix_entries = NULL; 2057 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2058 pci_disable_msi(adapter->pdev); 2059 adapter->flags &= ~FLAG_MSI_ENABLED; 2060 } 2061 } 2062 2063 /** 2064 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2065 * 2066 * Attempt to configure interrupts using the best available 2067 * capabilities of the hardware and kernel. 2068 **/ 2069 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2070 { 2071 int err; 2072 int i; 2073 2074 switch (adapter->int_mode) { 2075 case E1000E_INT_MODE_MSIX: 2076 if (adapter->flags & FLAG_HAS_MSIX) { 2077 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2078 adapter->msix_entries = kcalloc(adapter->num_vectors, 2079 sizeof(struct 2080 msix_entry), 2081 GFP_KERNEL); 2082 if (adapter->msix_entries) { 2083 struct e1000_adapter *a = adapter; 2084 2085 for (i = 0; i < adapter->num_vectors; i++) 2086 adapter->msix_entries[i].entry = i; 2087 2088 err = pci_enable_msix_range(a->pdev, 2089 a->msix_entries, 2090 a->num_vectors, 2091 a->num_vectors); 2092 if (err > 0) 2093 return; 2094 } 2095 /* MSI-X failed, so fall through and try MSI */ 2096 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2097 e1000e_reset_interrupt_capability(adapter); 2098 } 2099 adapter->int_mode = E1000E_INT_MODE_MSI; 2100 /* Fall through */ 2101 case E1000E_INT_MODE_MSI: 2102 if (!pci_enable_msi(adapter->pdev)) { 2103 adapter->flags |= FLAG_MSI_ENABLED; 2104 } else { 2105 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2106 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2107 } 2108 /* Fall through */ 2109 case E1000E_INT_MODE_LEGACY: 2110 /* Don't do anything; this is the system default */ 2111 break; 2112 } 2113 2114 /* store the number of vectors being used */ 2115 adapter->num_vectors = 1; 2116 } 2117 2118 /** 2119 * e1000_request_msix - Initialize MSI-X interrupts 2120 * 2121 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2122 * kernel. 2123 **/ 2124 static int e1000_request_msix(struct e1000_adapter *adapter) 2125 { 2126 struct net_device *netdev = adapter->netdev; 2127 int err = 0, vector = 0; 2128 2129 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2130 snprintf(adapter->rx_ring->name, 2131 sizeof(adapter->rx_ring->name) - 1, 2132 "%s-rx-0", netdev->name); 2133 else 2134 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2135 err = request_irq(adapter->msix_entries[vector].vector, 2136 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2137 netdev); 2138 if (err) 2139 return err; 2140 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2141 E1000_EITR_82574(vector); 2142 adapter->rx_ring->itr_val = adapter->itr; 2143 vector++; 2144 2145 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2146 snprintf(adapter->tx_ring->name, 2147 sizeof(adapter->tx_ring->name) - 1, 2148 "%s-tx-0", netdev->name); 2149 else 2150 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2151 err = request_irq(adapter->msix_entries[vector].vector, 2152 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2153 netdev); 2154 if (err) 2155 return err; 2156 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2157 E1000_EITR_82574(vector); 2158 adapter->tx_ring->itr_val = adapter->itr; 2159 vector++; 2160 2161 err = request_irq(adapter->msix_entries[vector].vector, 2162 e1000_msix_other, 0, netdev->name, netdev); 2163 if (err) 2164 return err; 2165 2166 e1000_configure_msix(adapter); 2167 2168 return 0; 2169 } 2170 2171 /** 2172 * e1000_request_irq - initialize interrupts 2173 * 2174 * Attempts to configure interrupts using the best available 2175 * capabilities of the hardware and kernel. 2176 **/ 2177 static int e1000_request_irq(struct e1000_adapter *adapter) 2178 { 2179 struct net_device *netdev = adapter->netdev; 2180 int err; 2181 2182 if (adapter->msix_entries) { 2183 err = e1000_request_msix(adapter); 2184 if (!err) 2185 return err; 2186 /* fall back to MSI */ 2187 e1000e_reset_interrupt_capability(adapter); 2188 adapter->int_mode = E1000E_INT_MODE_MSI; 2189 e1000e_set_interrupt_capability(adapter); 2190 } 2191 if (adapter->flags & FLAG_MSI_ENABLED) { 2192 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2193 netdev->name, netdev); 2194 if (!err) 2195 return err; 2196 2197 /* fall back to legacy interrupt */ 2198 e1000e_reset_interrupt_capability(adapter); 2199 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2200 } 2201 2202 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2203 netdev->name, netdev); 2204 if (err) 2205 e_err("Unable to allocate interrupt, Error: %d\n", err); 2206 2207 return err; 2208 } 2209 2210 static void e1000_free_irq(struct e1000_adapter *adapter) 2211 { 2212 struct net_device *netdev = adapter->netdev; 2213 2214 if (adapter->msix_entries) { 2215 int vector = 0; 2216 2217 free_irq(adapter->msix_entries[vector].vector, netdev); 2218 vector++; 2219 2220 free_irq(adapter->msix_entries[vector].vector, netdev); 2221 vector++; 2222 2223 /* Other Causes interrupt vector */ 2224 free_irq(adapter->msix_entries[vector].vector, netdev); 2225 return; 2226 } 2227 2228 free_irq(adapter->pdev->irq, netdev); 2229 } 2230 2231 /** 2232 * e1000_irq_disable - Mask off interrupt generation on the NIC 2233 **/ 2234 static void e1000_irq_disable(struct e1000_adapter *adapter) 2235 { 2236 struct e1000_hw *hw = &adapter->hw; 2237 2238 ew32(IMC, ~0); 2239 if (adapter->msix_entries) 2240 ew32(EIAC_82574, 0); 2241 e1e_flush(); 2242 2243 if (adapter->msix_entries) { 2244 int i; 2245 2246 for (i = 0; i < adapter->num_vectors; i++) 2247 synchronize_irq(adapter->msix_entries[i].vector); 2248 } else { 2249 synchronize_irq(adapter->pdev->irq); 2250 } 2251 } 2252 2253 /** 2254 * e1000_irq_enable - Enable default interrupt generation settings 2255 **/ 2256 static void e1000_irq_enable(struct e1000_adapter *adapter) 2257 { 2258 struct e1000_hw *hw = &adapter->hw; 2259 2260 if (adapter->msix_entries) { 2261 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2262 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC); 2263 } else if ((hw->mac.type == e1000_pch_lpt) || 2264 (hw->mac.type == e1000_pch_spt)) { 2265 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2266 } else { 2267 ew32(IMS, IMS_ENABLE_MASK); 2268 } 2269 e1e_flush(); 2270 } 2271 2272 /** 2273 * e1000e_get_hw_control - get control of the h/w from f/w 2274 * @adapter: address of board private structure 2275 * 2276 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2277 * For ASF and Pass Through versions of f/w this means that 2278 * the driver is loaded. For AMT version (only with 82573) 2279 * of the f/w this means that the network i/f is open. 2280 **/ 2281 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2282 { 2283 struct e1000_hw *hw = &adapter->hw; 2284 u32 ctrl_ext; 2285 u32 swsm; 2286 2287 /* Let firmware know the driver has taken over */ 2288 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2289 swsm = er32(SWSM); 2290 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2291 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2292 ctrl_ext = er32(CTRL_EXT); 2293 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2294 } 2295 } 2296 2297 /** 2298 * e1000e_release_hw_control - release control of the h/w to f/w 2299 * @adapter: address of board private structure 2300 * 2301 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2302 * For ASF and Pass Through versions of f/w this means that the 2303 * driver is no longer loaded. For AMT version (only with 82573) i 2304 * of the f/w this means that the network i/f is closed. 2305 * 2306 **/ 2307 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2308 { 2309 struct e1000_hw *hw = &adapter->hw; 2310 u32 ctrl_ext; 2311 u32 swsm; 2312 2313 /* Let firmware taken over control of h/w */ 2314 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2315 swsm = er32(SWSM); 2316 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2317 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2318 ctrl_ext = er32(CTRL_EXT); 2319 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2320 } 2321 } 2322 2323 /** 2324 * e1000_alloc_ring_dma - allocate memory for a ring structure 2325 **/ 2326 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2327 struct e1000_ring *ring) 2328 { 2329 struct pci_dev *pdev = adapter->pdev; 2330 2331 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2332 GFP_KERNEL); 2333 if (!ring->desc) 2334 return -ENOMEM; 2335 2336 return 0; 2337 } 2338 2339 /** 2340 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2341 * @tx_ring: Tx descriptor ring 2342 * 2343 * Return 0 on success, negative on failure 2344 **/ 2345 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2346 { 2347 struct e1000_adapter *adapter = tx_ring->adapter; 2348 int err = -ENOMEM, size; 2349 2350 size = sizeof(struct e1000_buffer) * tx_ring->count; 2351 tx_ring->buffer_info = vzalloc(size); 2352 if (!tx_ring->buffer_info) 2353 goto err; 2354 2355 /* round up to nearest 4K */ 2356 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2357 tx_ring->size = ALIGN(tx_ring->size, 4096); 2358 2359 err = e1000_alloc_ring_dma(adapter, tx_ring); 2360 if (err) 2361 goto err; 2362 2363 tx_ring->next_to_use = 0; 2364 tx_ring->next_to_clean = 0; 2365 2366 return 0; 2367 err: 2368 vfree(tx_ring->buffer_info); 2369 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2370 return err; 2371 } 2372 2373 /** 2374 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2375 * @rx_ring: Rx descriptor ring 2376 * 2377 * Returns 0 on success, negative on failure 2378 **/ 2379 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2380 { 2381 struct e1000_adapter *adapter = rx_ring->adapter; 2382 struct e1000_buffer *buffer_info; 2383 int i, size, desc_len, err = -ENOMEM; 2384 2385 size = sizeof(struct e1000_buffer) * rx_ring->count; 2386 rx_ring->buffer_info = vzalloc(size); 2387 if (!rx_ring->buffer_info) 2388 goto err; 2389 2390 for (i = 0; i < rx_ring->count; i++) { 2391 buffer_info = &rx_ring->buffer_info[i]; 2392 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2393 sizeof(struct e1000_ps_page), 2394 GFP_KERNEL); 2395 if (!buffer_info->ps_pages) 2396 goto err_pages; 2397 } 2398 2399 desc_len = sizeof(union e1000_rx_desc_packet_split); 2400 2401 /* Round up to nearest 4K */ 2402 rx_ring->size = rx_ring->count * desc_len; 2403 rx_ring->size = ALIGN(rx_ring->size, 4096); 2404 2405 err = e1000_alloc_ring_dma(adapter, rx_ring); 2406 if (err) 2407 goto err_pages; 2408 2409 rx_ring->next_to_clean = 0; 2410 rx_ring->next_to_use = 0; 2411 rx_ring->rx_skb_top = NULL; 2412 2413 return 0; 2414 2415 err_pages: 2416 for (i = 0; i < rx_ring->count; i++) { 2417 buffer_info = &rx_ring->buffer_info[i]; 2418 kfree(buffer_info->ps_pages); 2419 } 2420 err: 2421 vfree(rx_ring->buffer_info); 2422 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2423 return err; 2424 } 2425 2426 /** 2427 * e1000_clean_tx_ring - Free Tx Buffers 2428 * @tx_ring: Tx descriptor ring 2429 **/ 2430 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2431 { 2432 struct e1000_adapter *adapter = tx_ring->adapter; 2433 struct e1000_buffer *buffer_info; 2434 unsigned long size; 2435 unsigned int i; 2436 2437 for (i = 0; i < tx_ring->count; i++) { 2438 buffer_info = &tx_ring->buffer_info[i]; 2439 e1000_put_txbuf(tx_ring, buffer_info); 2440 } 2441 2442 netdev_reset_queue(adapter->netdev); 2443 size = sizeof(struct e1000_buffer) * tx_ring->count; 2444 memset(tx_ring->buffer_info, 0, size); 2445 2446 memset(tx_ring->desc, 0, tx_ring->size); 2447 2448 tx_ring->next_to_use = 0; 2449 tx_ring->next_to_clean = 0; 2450 2451 writel(0, tx_ring->head); 2452 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2453 e1000e_update_tdt_wa(tx_ring, 0); 2454 else 2455 writel(0, tx_ring->tail); 2456 } 2457 2458 /** 2459 * e1000e_free_tx_resources - Free Tx Resources per Queue 2460 * @tx_ring: Tx descriptor ring 2461 * 2462 * Free all transmit software resources 2463 **/ 2464 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2465 { 2466 struct e1000_adapter *adapter = tx_ring->adapter; 2467 struct pci_dev *pdev = adapter->pdev; 2468 2469 e1000_clean_tx_ring(tx_ring); 2470 2471 vfree(tx_ring->buffer_info); 2472 tx_ring->buffer_info = NULL; 2473 2474 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2475 tx_ring->dma); 2476 tx_ring->desc = NULL; 2477 } 2478 2479 /** 2480 * e1000e_free_rx_resources - Free Rx Resources 2481 * @rx_ring: Rx descriptor ring 2482 * 2483 * Free all receive software resources 2484 **/ 2485 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2486 { 2487 struct e1000_adapter *adapter = rx_ring->adapter; 2488 struct pci_dev *pdev = adapter->pdev; 2489 int i; 2490 2491 e1000_clean_rx_ring(rx_ring); 2492 2493 for (i = 0; i < rx_ring->count; i++) 2494 kfree(rx_ring->buffer_info[i].ps_pages); 2495 2496 vfree(rx_ring->buffer_info); 2497 rx_ring->buffer_info = NULL; 2498 2499 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2500 rx_ring->dma); 2501 rx_ring->desc = NULL; 2502 } 2503 2504 /** 2505 * e1000_update_itr - update the dynamic ITR value based on statistics 2506 * @adapter: pointer to adapter 2507 * @itr_setting: current adapter->itr 2508 * @packets: the number of packets during this measurement interval 2509 * @bytes: the number of bytes during this measurement interval 2510 * 2511 * Stores a new ITR value based on packets and byte 2512 * counts during the last interrupt. The advantage of per interrupt 2513 * computation is faster updates and more accurate ITR for the current 2514 * traffic pattern. Constants in this function were computed 2515 * based on theoretical maximum wire speed and thresholds were set based 2516 * on testing data as well as attempting to minimize response time 2517 * while increasing bulk throughput. This functionality is controlled 2518 * by the InterruptThrottleRate module parameter. 2519 **/ 2520 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2521 { 2522 unsigned int retval = itr_setting; 2523 2524 if (packets == 0) 2525 return itr_setting; 2526 2527 switch (itr_setting) { 2528 case lowest_latency: 2529 /* handle TSO and jumbo frames */ 2530 if (bytes / packets > 8000) 2531 retval = bulk_latency; 2532 else if ((packets < 5) && (bytes > 512)) 2533 retval = low_latency; 2534 break; 2535 case low_latency: /* 50 usec aka 20000 ints/s */ 2536 if (bytes > 10000) { 2537 /* this if handles the TSO accounting */ 2538 if (bytes / packets > 8000) 2539 retval = bulk_latency; 2540 else if ((packets < 10) || ((bytes / packets) > 1200)) 2541 retval = bulk_latency; 2542 else if ((packets > 35)) 2543 retval = lowest_latency; 2544 } else if (bytes / packets > 2000) { 2545 retval = bulk_latency; 2546 } else if (packets <= 2 && bytes < 512) { 2547 retval = lowest_latency; 2548 } 2549 break; 2550 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2551 if (bytes > 25000) { 2552 if (packets > 35) 2553 retval = low_latency; 2554 } else if (bytes < 6000) { 2555 retval = low_latency; 2556 } 2557 break; 2558 } 2559 2560 return retval; 2561 } 2562 2563 static void e1000_set_itr(struct e1000_adapter *adapter) 2564 { 2565 u16 current_itr; 2566 u32 new_itr = adapter->itr; 2567 2568 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2569 if (adapter->link_speed != SPEED_1000) { 2570 current_itr = 0; 2571 new_itr = 4000; 2572 goto set_itr_now; 2573 } 2574 2575 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2576 new_itr = 0; 2577 goto set_itr_now; 2578 } 2579 2580 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2581 adapter->total_tx_packets, 2582 adapter->total_tx_bytes); 2583 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2584 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2585 adapter->tx_itr = low_latency; 2586 2587 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2588 adapter->total_rx_packets, 2589 adapter->total_rx_bytes); 2590 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2591 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2592 adapter->rx_itr = low_latency; 2593 2594 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2595 2596 /* counts and packets in update_itr are dependent on these numbers */ 2597 switch (current_itr) { 2598 case lowest_latency: 2599 new_itr = 70000; 2600 break; 2601 case low_latency: 2602 new_itr = 20000; /* aka hwitr = ~200 */ 2603 break; 2604 case bulk_latency: 2605 new_itr = 4000; 2606 break; 2607 default: 2608 break; 2609 } 2610 2611 set_itr_now: 2612 if (new_itr != adapter->itr) { 2613 /* this attempts to bias the interrupt rate towards Bulk 2614 * by adding intermediate steps when interrupt rate is 2615 * increasing 2616 */ 2617 new_itr = new_itr > adapter->itr ? 2618 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2619 adapter->itr = new_itr; 2620 adapter->rx_ring->itr_val = new_itr; 2621 if (adapter->msix_entries) 2622 adapter->rx_ring->set_itr = 1; 2623 else 2624 e1000e_write_itr(adapter, new_itr); 2625 } 2626 } 2627 2628 /** 2629 * e1000e_write_itr - write the ITR value to the appropriate registers 2630 * @adapter: address of board private structure 2631 * @itr: new ITR value to program 2632 * 2633 * e1000e_write_itr determines if the adapter is in MSI-X mode 2634 * and, if so, writes the EITR registers with the ITR value. 2635 * Otherwise, it writes the ITR value into the ITR register. 2636 **/ 2637 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2638 { 2639 struct e1000_hw *hw = &adapter->hw; 2640 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2641 2642 if (adapter->msix_entries) { 2643 int vector; 2644 2645 for (vector = 0; vector < adapter->num_vectors; vector++) 2646 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2647 } else { 2648 ew32(ITR, new_itr); 2649 } 2650 } 2651 2652 /** 2653 * e1000_alloc_queues - Allocate memory for all rings 2654 * @adapter: board private structure to initialize 2655 **/ 2656 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2657 { 2658 int size = sizeof(struct e1000_ring); 2659 2660 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2661 if (!adapter->tx_ring) 2662 goto err; 2663 adapter->tx_ring->count = adapter->tx_ring_count; 2664 adapter->tx_ring->adapter = adapter; 2665 2666 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2667 if (!adapter->rx_ring) 2668 goto err; 2669 adapter->rx_ring->count = adapter->rx_ring_count; 2670 adapter->rx_ring->adapter = adapter; 2671 2672 return 0; 2673 err: 2674 e_err("Unable to allocate memory for queues\n"); 2675 kfree(adapter->rx_ring); 2676 kfree(adapter->tx_ring); 2677 return -ENOMEM; 2678 } 2679 2680 /** 2681 * e1000e_poll - NAPI Rx polling callback 2682 * @napi: struct associated with this polling callback 2683 * @weight: number of packets driver is allowed to process this poll 2684 **/ 2685 static int e1000e_poll(struct napi_struct *napi, int weight) 2686 { 2687 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2688 napi); 2689 struct e1000_hw *hw = &adapter->hw; 2690 struct net_device *poll_dev = adapter->netdev; 2691 int tx_cleaned = 1, work_done = 0; 2692 2693 adapter = netdev_priv(poll_dev); 2694 2695 if (!adapter->msix_entries || 2696 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2697 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2698 2699 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2700 2701 if (!tx_cleaned) 2702 work_done = weight; 2703 2704 /* If weight not fully consumed, exit the polling mode */ 2705 if (work_done < weight) { 2706 if (adapter->itr_setting & 3) 2707 e1000_set_itr(adapter); 2708 napi_complete(napi); 2709 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2710 if (adapter->msix_entries) 2711 ew32(IMS, adapter->rx_ring->ims_val); 2712 else 2713 e1000_irq_enable(adapter); 2714 } 2715 } 2716 2717 return work_done; 2718 } 2719 2720 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2721 __always_unused __be16 proto, u16 vid) 2722 { 2723 struct e1000_adapter *adapter = netdev_priv(netdev); 2724 struct e1000_hw *hw = &adapter->hw; 2725 u32 vfta, index; 2726 2727 /* don't update vlan cookie if already programmed */ 2728 if ((adapter->hw.mng_cookie.status & 2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2730 (vid == adapter->mng_vlan_id)) 2731 return 0; 2732 2733 /* add VID to filter table */ 2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2735 index = (vid >> 5) & 0x7F; 2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2737 vfta |= (1 << (vid & 0x1F)); 2738 hw->mac.ops.write_vfta(hw, index, vfta); 2739 } 2740 2741 set_bit(vid, adapter->active_vlans); 2742 2743 return 0; 2744 } 2745 2746 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2747 __always_unused __be16 proto, u16 vid) 2748 { 2749 struct e1000_adapter *adapter = netdev_priv(netdev); 2750 struct e1000_hw *hw = &adapter->hw; 2751 u32 vfta, index; 2752 2753 if ((adapter->hw.mng_cookie.status & 2754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2755 (vid == adapter->mng_vlan_id)) { 2756 /* release control to f/w */ 2757 e1000e_release_hw_control(adapter); 2758 return 0; 2759 } 2760 2761 /* remove VID from filter table */ 2762 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2763 index = (vid >> 5) & 0x7F; 2764 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2765 vfta &= ~(1 << (vid & 0x1F)); 2766 hw->mac.ops.write_vfta(hw, index, vfta); 2767 } 2768 2769 clear_bit(vid, adapter->active_vlans); 2770 2771 return 0; 2772 } 2773 2774 /** 2775 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2776 * @adapter: board private structure to initialize 2777 **/ 2778 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2779 { 2780 struct net_device *netdev = adapter->netdev; 2781 struct e1000_hw *hw = &adapter->hw; 2782 u32 rctl; 2783 2784 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2785 /* disable VLAN receive filtering */ 2786 rctl = er32(RCTL); 2787 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2788 ew32(RCTL, rctl); 2789 2790 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2791 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2792 adapter->mng_vlan_id); 2793 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2794 } 2795 } 2796 } 2797 2798 /** 2799 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2800 * @adapter: board private structure to initialize 2801 **/ 2802 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2803 { 2804 struct e1000_hw *hw = &adapter->hw; 2805 u32 rctl; 2806 2807 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2808 /* enable VLAN receive filtering */ 2809 rctl = er32(RCTL); 2810 rctl |= E1000_RCTL_VFE; 2811 rctl &= ~E1000_RCTL_CFIEN; 2812 ew32(RCTL, rctl); 2813 } 2814 } 2815 2816 /** 2817 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping 2818 * @adapter: board private structure to initialize 2819 **/ 2820 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2821 { 2822 struct e1000_hw *hw = &adapter->hw; 2823 u32 ctrl; 2824 2825 /* disable VLAN tag insert/strip */ 2826 ctrl = er32(CTRL); 2827 ctrl &= ~E1000_CTRL_VME; 2828 ew32(CTRL, ctrl); 2829 } 2830 2831 /** 2832 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2833 * @adapter: board private structure to initialize 2834 **/ 2835 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2836 { 2837 struct e1000_hw *hw = &adapter->hw; 2838 u32 ctrl; 2839 2840 /* enable VLAN tag insert/strip */ 2841 ctrl = er32(CTRL); 2842 ctrl |= E1000_CTRL_VME; 2843 ew32(CTRL, ctrl); 2844 } 2845 2846 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2847 { 2848 struct net_device *netdev = adapter->netdev; 2849 u16 vid = adapter->hw.mng_cookie.vlan_id; 2850 u16 old_vid = adapter->mng_vlan_id; 2851 2852 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2853 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2854 adapter->mng_vlan_id = vid; 2855 } 2856 2857 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2858 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2859 } 2860 2861 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2862 { 2863 u16 vid; 2864 2865 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2866 2867 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2868 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2869 } 2870 2871 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2872 { 2873 struct e1000_hw *hw = &adapter->hw; 2874 u32 manc, manc2h, mdef, i, j; 2875 2876 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2877 return; 2878 2879 manc = er32(MANC); 2880 2881 /* enable receiving management packets to the host. this will probably 2882 * generate destination unreachable messages from the host OS, but 2883 * the packets will be handled on SMBUS 2884 */ 2885 manc |= E1000_MANC_EN_MNG2HOST; 2886 manc2h = er32(MANC2H); 2887 2888 switch (hw->mac.type) { 2889 default: 2890 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2891 break; 2892 case e1000_82574: 2893 case e1000_82583: 2894 /* Check if IPMI pass-through decision filter already exists; 2895 * if so, enable it. 2896 */ 2897 for (i = 0, j = 0; i < 8; i++) { 2898 mdef = er32(MDEF(i)); 2899 2900 /* Ignore filters with anything other than IPMI ports */ 2901 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2902 continue; 2903 2904 /* Enable this decision filter in MANC2H */ 2905 if (mdef) 2906 manc2h |= (1 << i); 2907 2908 j |= mdef; 2909 } 2910 2911 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2912 break; 2913 2914 /* Create new decision filter in an empty filter */ 2915 for (i = 0, j = 0; i < 8; i++) 2916 if (er32(MDEF(i)) == 0) { 2917 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2918 E1000_MDEF_PORT_664)); 2919 manc2h |= (1 << 1); 2920 j++; 2921 break; 2922 } 2923 2924 if (!j) 2925 e_warn("Unable to create IPMI pass-through filter\n"); 2926 break; 2927 } 2928 2929 ew32(MANC2H, manc2h); 2930 ew32(MANC, manc); 2931 } 2932 2933 /** 2934 * e1000_configure_tx - Configure Transmit Unit after Reset 2935 * @adapter: board private structure 2936 * 2937 * Configure the Tx unit of the MAC after a reset. 2938 **/ 2939 static void e1000_configure_tx(struct e1000_adapter *adapter) 2940 { 2941 struct e1000_hw *hw = &adapter->hw; 2942 struct e1000_ring *tx_ring = adapter->tx_ring; 2943 u64 tdba; 2944 u32 tdlen, tctl, tarc; 2945 2946 /* Setup the HW Tx Head and Tail descriptor pointers */ 2947 tdba = tx_ring->dma; 2948 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2949 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2950 ew32(TDBAH(0), (tdba >> 32)); 2951 ew32(TDLEN(0), tdlen); 2952 ew32(TDH(0), 0); 2953 ew32(TDT(0), 0); 2954 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2955 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2956 2957 /* Set the Tx Interrupt Delay register */ 2958 ew32(TIDV, adapter->tx_int_delay); 2959 /* Tx irq moderation */ 2960 ew32(TADV, adapter->tx_abs_int_delay); 2961 2962 if (adapter->flags2 & FLAG2_DMA_BURST) { 2963 u32 txdctl = er32(TXDCTL(0)); 2964 2965 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2966 E1000_TXDCTL_WTHRESH); 2967 /* set up some performance related parameters to encourage the 2968 * hardware to use the bus more efficiently in bursts, depends 2969 * on the tx_int_delay to be enabled, 2970 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2971 * hthresh = 1 ==> prefetch when one or more available 2972 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2973 * BEWARE: this seems to work but should be considered first if 2974 * there are Tx hangs or other Tx related bugs 2975 */ 2976 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2977 ew32(TXDCTL(0), txdctl); 2978 } 2979 /* erratum work around: set txdctl the same for both queues */ 2980 ew32(TXDCTL(1), er32(TXDCTL(0))); 2981 2982 /* Program the Transmit Control Register */ 2983 tctl = er32(TCTL); 2984 tctl &= ~E1000_TCTL_CT; 2985 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2986 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2987 2988 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2989 tarc = er32(TARC(0)); 2990 /* set the speed mode bit, we'll clear it if we're not at 2991 * gigabit link later 2992 */ 2993 #define SPEED_MODE_BIT (1 << 21) 2994 tarc |= SPEED_MODE_BIT; 2995 ew32(TARC(0), tarc); 2996 } 2997 2998 /* errata: program both queues to unweighted RR */ 2999 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3000 tarc = er32(TARC(0)); 3001 tarc |= 1; 3002 ew32(TARC(0), tarc); 3003 tarc = er32(TARC(1)); 3004 tarc |= 1; 3005 ew32(TARC(1), tarc); 3006 } 3007 3008 /* Setup Transmit Descriptor Settings for eop descriptor */ 3009 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3010 3011 /* only set IDE if we are delaying interrupts using the timers */ 3012 if (adapter->tx_int_delay) 3013 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3014 3015 /* enable Report Status bit */ 3016 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3017 3018 ew32(TCTL, tctl); 3019 3020 hw->mac.ops.config_collision_dist(hw); 3021 3022 /* SPT Si errata workaround to avoid data corruption */ 3023 if (hw->mac.type == e1000_pch_spt) { 3024 u32 reg_val; 3025 3026 reg_val = er32(IOSFPC); 3027 reg_val |= E1000_RCTL_RDMTS_HEX; 3028 ew32(IOSFPC, reg_val); 3029 3030 reg_val = er32(TARC(0)); 3031 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 3032 ew32(TARC(0), reg_val); 3033 } 3034 } 3035 3036 /** 3037 * e1000_setup_rctl - configure the receive control registers 3038 * @adapter: Board private structure 3039 **/ 3040 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3041 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3042 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3043 { 3044 struct e1000_hw *hw = &adapter->hw; 3045 u32 rctl, rfctl; 3046 u32 pages = 0; 3047 3048 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3049 * If jumbo frames not set, program related MAC/PHY registers 3050 * to h/w defaults 3051 */ 3052 if (hw->mac.type >= e1000_pch2lan) { 3053 s32 ret_val; 3054 3055 if (adapter->netdev->mtu > ETH_DATA_LEN) 3056 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3057 else 3058 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3059 3060 if (ret_val) 3061 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3062 } 3063 3064 /* Program MC offset vector base */ 3065 rctl = er32(RCTL); 3066 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3067 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3068 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3069 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3070 3071 /* Do not Store bad packets */ 3072 rctl &= ~E1000_RCTL_SBP; 3073 3074 /* Enable Long Packet receive */ 3075 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3076 rctl &= ~E1000_RCTL_LPE; 3077 else 3078 rctl |= E1000_RCTL_LPE; 3079 3080 /* Some systems expect that the CRC is included in SMBUS traffic. The 3081 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3082 * host memory when this is enabled 3083 */ 3084 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3085 rctl |= E1000_RCTL_SECRC; 3086 3087 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3088 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3089 u16 phy_data; 3090 3091 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3092 phy_data &= 0xfff8; 3093 phy_data |= (1 << 2); 3094 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3095 3096 e1e_rphy(hw, 22, &phy_data); 3097 phy_data &= 0x0fff; 3098 phy_data |= (1 << 14); 3099 e1e_wphy(hw, 0x10, 0x2823); 3100 e1e_wphy(hw, 0x11, 0x0003); 3101 e1e_wphy(hw, 22, phy_data); 3102 } 3103 3104 /* Setup buffer sizes */ 3105 rctl &= ~E1000_RCTL_SZ_4096; 3106 rctl |= E1000_RCTL_BSEX; 3107 switch (adapter->rx_buffer_len) { 3108 case 2048: 3109 default: 3110 rctl |= E1000_RCTL_SZ_2048; 3111 rctl &= ~E1000_RCTL_BSEX; 3112 break; 3113 case 4096: 3114 rctl |= E1000_RCTL_SZ_4096; 3115 break; 3116 case 8192: 3117 rctl |= E1000_RCTL_SZ_8192; 3118 break; 3119 case 16384: 3120 rctl |= E1000_RCTL_SZ_16384; 3121 break; 3122 } 3123 3124 /* Enable Extended Status in all Receive Descriptors */ 3125 rfctl = er32(RFCTL); 3126 rfctl |= E1000_RFCTL_EXTEN; 3127 ew32(RFCTL, rfctl); 3128 3129 /* 82571 and greater support packet-split where the protocol 3130 * header is placed in skb->data and the packet data is 3131 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3132 * In the case of a non-split, skb->data is linearly filled, 3133 * followed by the page buffers. Therefore, skb->data is 3134 * sized to hold the largest protocol header. 3135 * 3136 * allocations using alloc_page take too long for regular MTU 3137 * so only enable packet split for jumbo frames 3138 * 3139 * Using pages when the page size is greater than 16k wastes 3140 * a lot of memory, since we allocate 3 pages at all times 3141 * per packet. 3142 */ 3143 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3144 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3145 adapter->rx_ps_pages = pages; 3146 else 3147 adapter->rx_ps_pages = 0; 3148 3149 if (adapter->rx_ps_pages) { 3150 u32 psrctl = 0; 3151 3152 /* Enable Packet split descriptors */ 3153 rctl |= E1000_RCTL_DTYP_PS; 3154 3155 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3156 3157 switch (adapter->rx_ps_pages) { 3158 case 3: 3159 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3160 /* fall-through */ 3161 case 2: 3162 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3163 /* fall-through */ 3164 case 1: 3165 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3166 break; 3167 } 3168 3169 ew32(PSRCTL, psrctl); 3170 } 3171 3172 /* This is useful for sniffing bad packets. */ 3173 if (adapter->netdev->features & NETIF_F_RXALL) { 3174 /* UPE and MPE will be handled by normal PROMISC logic 3175 * in e1000e_set_rx_mode 3176 */ 3177 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3178 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3179 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3180 3181 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3182 E1000_RCTL_DPF | /* Allow filtered pause */ 3183 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3184 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3185 * and that breaks VLANs. 3186 */ 3187 } 3188 3189 ew32(RCTL, rctl); 3190 /* just started the receive unit, no need to restart */ 3191 adapter->flags &= ~FLAG_RESTART_NOW; 3192 } 3193 3194 /** 3195 * e1000_configure_rx - Configure Receive Unit after Reset 3196 * @adapter: board private structure 3197 * 3198 * Configure the Rx unit of the MAC after a reset. 3199 **/ 3200 static void e1000_configure_rx(struct e1000_adapter *adapter) 3201 { 3202 struct e1000_hw *hw = &adapter->hw; 3203 struct e1000_ring *rx_ring = adapter->rx_ring; 3204 u64 rdba; 3205 u32 rdlen, rctl, rxcsum, ctrl_ext; 3206 3207 if (adapter->rx_ps_pages) { 3208 /* this is a 32 byte descriptor */ 3209 rdlen = rx_ring->count * 3210 sizeof(union e1000_rx_desc_packet_split); 3211 adapter->clean_rx = e1000_clean_rx_irq_ps; 3212 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3213 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3215 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3216 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3217 } else { 3218 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3219 adapter->clean_rx = e1000_clean_rx_irq; 3220 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3221 } 3222 3223 /* disable receives while setting up the descriptors */ 3224 rctl = er32(RCTL); 3225 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3226 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3227 e1e_flush(); 3228 usleep_range(10000, 20000); 3229 3230 if (adapter->flags2 & FLAG2_DMA_BURST) { 3231 /* set the writeback threshold (only takes effect if the RDTR 3232 * is set). set GRAN=1 and write back up to 0x4 worth, and 3233 * enable prefetching of 0x20 Rx descriptors 3234 * granularity = 01 3235 * wthresh = 04, 3236 * hthresh = 04, 3237 * pthresh = 0x20 3238 */ 3239 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3240 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3241 3242 /* override the delay timers for enabling bursting, only if 3243 * the value was not set by the user via module options 3244 */ 3245 if (adapter->rx_int_delay == DEFAULT_RDTR) 3246 adapter->rx_int_delay = BURST_RDTR; 3247 if (adapter->rx_abs_int_delay == DEFAULT_RADV) 3248 adapter->rx_abs_int_delay = BURST_RADV; 3249 } 3250 3251 /* set the Receive Delay Timer Register */ 3252 ew32(RDTR, adapter->rx_int_delay); 3253 3254 /* irq moderation */ 3255 ew32(RADV, adapter->rx_abs_int_delay); 3256 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3257 e1000e_write_itr(adapter, adapter->itr); 3258 3259 ctrl_ext = er32(CTRL_EXT); 3260 /* Auto-Mask interrupts upon ICR access */ 3261 ctrl_ext |= E1000_CTRL_EXT_IAME; 3262 ew32(IAM, 0xffffffff); 3263 ew32(CTRL_EXT, ctrl_ext); 3264 e1e_flush(); 3265 3266 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3267 * the Base and Length of the Rx Descriptor Ring 3268 */ 3269 rdba = rx_ring->dma; 3270 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3271 ew32(RDBAH(0), (rdba >> 32)); 3272 ew32(RDLEN(0), rdlen); 3273 ew32(RDH(0), 0); 3274 ew32(RDT(0), 0); 3275 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3276 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3277 3278 /* Enable Receive Checksum Offload for TCP and UDP */ 3279 rxcsum = er32(RXCSUM); 3280 if (adapter->netdev->features & NETIF_F_RXCSUM) 3281 rxcsum |= E1000_RXCSUM_TUOFL; 3282 else 3283 rxcsum &= ~E1000_RXCSUM_TUOFL; 3284 ew32(RXCSUM, rxcsum); 3285 3286 /* With jumbo frames, excessive C-state transition latencies result 3287 * in dropped transactions. 3288 */ 3289 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3290 u32 lat = 3291 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3292 adapter->max_frame_size) * 8 / 1000; 3293 3294 if (adapter->flags & FLAG_IS_ICH) { 3295 u32 rxdctl = er32(RXDCTL(0)); 3296 3297 ew32(RXDCTL(0), rxdctl | 0x3); 3298 } 3299 3300 pm_qos_update_request(&adapter->pm_qos_req, lat); 3301 } else { 3302 pm_qos_update_request(&adapter->pm_qos_req, 3303 PM_QOS_DEFAULT_VALUE); 3304 } 3305 3306 /* Enable Receives */ 3307 ew32(RCTL, rctl); 3308 } 3309 3310 /** 3311 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3312 * @netdev: network interface device structure 3313 * 3314 * Writes multicast address list to the MTA hash table. 3315 * Returns: -ENOMEM on failure 3316 * 0 on no addresses written 3317 * X on writing X addresses to MTA 3318 */ 3319 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3320 { 3321 struct e1000_adapter *adapter = netdev_priv(netdev); 3322 struct e1000_hw *hw = &adapter->hw; 3323 struct netdev_hw_addr *ha; 3324 u8 *mta_list; 3325 int i; 3326 3327 if (netdev_mc_empty(netdev)) { 3328 /* nothing to program, so clear mc list */ 3329 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3330 return 0; 3331 } 3332 3333 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3334 if (!mta_list) 3335 return -ENOMEM; 3336 3337 /* update_mc_addr_list expects a packed array of only addresses. */ 3338 i = 0; 3339 netdev_for_each_mc_addr(ha, netdev) 3340 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3341 3342 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3343 kfree(mta_list); 3344 3345 return netdev_mc_count(netdev); 3346 } 3347 3348 /** 3349 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3350 * @netdev: network interface device structure 3351 * 3352 * Writes unicast address list to the RAR table. 3353 * Returns: -ENOMEM on failure/insufficient address space 3354 * 0 on no addresses written 3355 * X on writing X addresses to the RAR table 3356 **/ 3357 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3358 { 3359 struct e1000_adapter *adapter = netdev_priv(netdev); 3360 struct e1000_hw *hw = &adapter->hw; 3361 unsigned int rar_entries; 3362 int count = 0; 3363 3364 rar_entries = hw->mac.ops.rar_get_count(hw); 3365 3366 /* save a rar entry for our hardware address */ 3367 rar_entries--; 3368 3369 /* save a rar entry for the LAA workaround */ 3370 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3371 rar_entries--; 3372 3373 /* return ENOMEM indicating insufficient memory for addresses */ 3374 if (netdev_uc_count(netdev) > rar_entries) 3375 return -ENOMEM; 3376 3377 if (!netdev_uc_empty(netdev) && rar_entries) { 3378 struct netdev_hw_addr *ha; 3379 3380 /* write the addresses in reverse order to avoid write 3381 * combining 3382 */ 3383 netdev_for_each_uc_addr(ha, netdev) { 3384 int rval; 3385 3386 if (!rar_entries) 3387 break; 3388 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3389 if (rval < 0) 3390 return -ENOMEM; 3391 count++; 3392 } 3393 } 3394 3395 /* zero out the remaining RAR entries not used above */ 3396 for (; rar_entries > 0; rar_entries--) { 3397 ew32(RAH(rar_entries), 0); 3398 ew32(RAL(rar_entries), 0); 3399 } 3400 e1e_flush(); 3401 3402 return count; 3403 } 3404 3405 /** 3406 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3407 * @netdev: network interface device structure 3408 * 3409 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3410 * address list or the network interface flags are updated. This routine is 3411 * responsible for configuring the hardware for proper unicast, multicast, 3412 * promiscuous mode, and all-multi behavior. 3413 **/ 3414 static void e1000e_set_rx_mode(struct net_device *netdev) 3415 { 3416 struct e1000_adapter *adapter = netdev_priv(netdev); 3417 struct e1000_hw *hw = &adapter->hw; 3418 u32 rctl; 3419 3420 if (pm_runtime_suspended(netdev->dev.parent)) 3421 return; 3422 3423 /* Check for Promiscuous and All Multicast modes */ 3424 rctl = er32(RCTL); 3425 3426 /* clear the affected bits */ 3427 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3428 3429 if (netdev->flags & IFF_PROMISC) { 3430 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3431 /* Do not hardware filter VLANs in promisc mode */ 3432 e1000e_vlan_filter_disable(adapter); 3433 } else { 3434 int count; 3435 3436 if (netdev->flags & IFF_ALLMULTI) { 3437 rctl |= E1000_RCTL_MPE; 3438 } else { 3439 /* Write addresses to the MTA, if the attempt fails 3440 * then we should just turn on promiscuous mode so 3441 * that we can at least receive multicast traffic 3442 */ 3443 count = e1000e_write_mc_addr_list(netdev); 3444 if (count < 0) 3445 rctl |= E1000_RCTL_MPE; 3446 } 3447 e1000e_vlan_filter_enable(adapter); 3448 /* Write addresses to available RAR registers, if there is not 3449 * sufficient space to store all the addresses then enable 3450 * unicast promiscuous mode 3451 */ 3452 count = e1000e_write_uc_addr_list(netdev); 3453 if (count < 0) 3454 rctl |= E1000_RCTL_UPE; 3455 } 3456 3457 ew32(RCTL, rctl); 3458 3459 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3460 e1000e_vlan_strip_enable(adapter); 3461 else 3462 e1000e_vlan_strip_disable(adapter); 3463 } 3464 3465 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3466 { 3467 struct e1000_hw *hw = &adapter->hw; 3468 u32 mrqc, rxcsum; 3469 u32 rss_key[10]; 3470 int i; 3471 3472 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3473 for (i = 0; i < 10; i++) 3474 ew32(RSSRK(i), rss_key[i]); 3475 3476 /* Direct all traffic to queue 0 */ 3477 for (i = 0; i < 32; i++) 3478 ew32(RETA(i), 0); 3479 3480 /* Disable raw packet checksumming so that RSS hash is placed in 3481 * descriptor on writeback. 3482 */ 3483 rxcsum = er32(RXCSUM); 3484 rxcsum |= E1000_RXCSUM_PCSD; 3485 3486 ew32(RXCSUM, rxcsum); 3487 3488 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3489 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3490 E1000_MRQC_RSS_FIELD_IPV6 | 3491 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3492 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3493 3494 ew32(MRQC, mrqc); 3495 } 3496 3497 /** 3498 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3499 * @adapter: board private structure 3500 * @timinca: pointer to returned time increment attributes 3501 * 3502 * Get attributes for incrementing the System Time Register SYSTIML/H at 3503 * the default base frequency, and set the cyclecounter shift value. 3504 **/ 3505 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3506 { 3507 struct e1000_hw *hw = &adapter->hw; 3508 u32 incvalue, incperiod, shift; 3509 3510 /* Make sure clock is enabled on I217/I218/I219 before checking 3511 * the frequency 3512 */ 3513 if (((hw->mac.type == e1000_pch_lpt) || 3514 (hw->mac.type == e1000_pch_spt)) && 3515 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3516 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3517 u32 fextnvm7 = er32(FEXTNVM7); 3518 3519 if (!(fextnvm7 & (1 << 0))) { 3520 ew32(FEXTNVM7, fextnvm7 | (1 << 0)); 3521 e1e_flush(); 3522 } 3523 } 3524 3525 switch (hw->mac.type) { 3526 case e1000_pch2lan: 3527 case e1000_pch_lpt: 3528 case e1000_pch_spt: 3529 /* On I217, I218 and I219, the clock frequency is 25MHz 3530 * or 96MHz as indicated by the System Clock Frequency 3531 * Indication 3532 */ 3533 if (((hw->mac.type != e1000_pch_lpt) && 3534 (hw->mac.type != e1000_pch_spt)) || 3535 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 3536 /* Stable 96MHz frequency */ 3537 incperiod = INCPERIOD_96MHz; 3538 incvalue = INCVALUE_96MHz; 3539 shift = INCVALUE_SHIFT_96MHz; 3540 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz; 3541 break; 3542 } 3543 /* fall-through */ 3544 case e1000_82574: 3545 case e1000_82583: 3546 /* Stable 25MHz frequency */ 3547 incperiod = INCPERIOD_25MHz; 3548 incvalue = INCVALUE_25MHz; 3549 shift = INCVALUE_SHIFT_25MHz; 3550 adapter->cc.shift = shift; 3551 break; 3552 default: 3553 return -EINVAL; 3554 } 3555 3556 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3557 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3558 3559 return 0; 3560 } 3561 3562 /** 3563 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3564 * @adapter: board private structure 3565 * 3566 * Outgoing time stamping can be enabled and disabled. Play nice and 3567 * disable it when requested, although it shouldn't cause any overhead 3568 * when no packet needs it. At most one packet in the queue may be 3569 * marked for time stamping, otherwise it would be impossible to tell 3570 * for sure to which packet the hardware time stamp belongs. 3571 * 3572 * Incoming time stamping has to be configured via the hardware filters. 3573 * Not all combinations are supported, in particular event type has to be 3574 * specified. Matching the kind of event packet is not supported, with the 3575 * exception of "all V2 events regardless of level 2 or 4". 3576 **/ 3577 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3578 struct hwtstamp_config *config) 3579 { 3580 struct e1000_hw *hw = &adapter->hw; 3581 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3582 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3583 u32 rxmtrl = 0; 3584 u16 rxudp = 0; 3585 bool is_l4 = false; 3586 bool is_l2 = false; 3587 u32 regval; 3588 s32 ret_val; 3589 3590 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3591 return -EINVAL; 3592 3593 /* flags reserved for future extensions - must be zero */ 3594 if (config->flags) 3595 return -EINVAL; 3596 3597 switch (config->tx_type) { 3598 case HWTSTAMP_TX_OFF: 3599 tsync_tx_ctl = 0; 3600 break; 3601 case HWTSTAMP_TX_ON: 3602 break; 3603 default: 3604 return -ERANGE; 3605 } 3606 3607 switch (config->rx_filter) { 3608 case HWTSTAMP_FILTER_NONE: 3609 tsync_rx_ctl = 0; 3610 break; 3611 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3612 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3613 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3614 is_l4 = true; 3615 break; 3616 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3617 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3618 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3619 is_l4 = true; 3620 break; 3621 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3622 /* Also time stamps V2 L2 Path Delay Request/Response */ 3623 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3624 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3625 is_l2 = true; 3626 break; 3627 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3628 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3629 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3630 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3631 is_l2 = true; 3632 break; 3633 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3634 /* Hardware cannot filter just V2 L4 Sync messages; 3635 * fall-through to V2 (both L2 and L4) Sync. 3636 */ 3637 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3638 /* Also time stamps V2 Path Delay Request/Response. */ 3639 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3640 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3641 is_l2 = true; 3642 is_l4 = true; 3643 break; 3644 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3645 /* Hardware cannot filter just V2 L4 Delay Request messages; 3646 * fall-through to V2 (both L2 and L4) Delay Request. 3647 */ 3648 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3649 /* Also time stamps V2 Path Delay Request/Response. */ 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3651 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3652 is_l2 = true; 3653 is_l4 = true; 3654 break; 3655 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3656 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3657 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3658 * fall-through to all V2 (both L2 and L4) Events. 3659 */ 3660 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3661 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3662 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3663 is_l2 = true; 3664 is_l4 = true; 3665 break; 3666 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3667 /* For V1, the hardware can only filter Sync messages or 3668 * Delay Request messages but not both so fall-through to 3669 * time stamp all packets. 3670 */ 3671 case HWTSTAMP_FILTER_ALL: 3672 is_l2 = true; 3673 is_l4 = true; 3674 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3675 config->rx_filter = HWTSTAMP_FILTER_ALL; 3676 break; 3677 default: 3678 return -ERANGE; 3679 } 3680 3681 adapter->hwtstamp_config = *config; 3682 3683 /* enable/disable Tx h/w time stamping */ 3684 regval = er32(TSYNCTXCTL); 3685 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3686 regval |= tsync_tx_ctl; 3687 ew32(TSYNCTXCTL, regval); 3688 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3689 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3690 e_err("Timesync Tx Control register not set as expected\n"); 3691 return -EAGAIN; 3692 } 3693 3694 /* enable/disable Rx h/w time stamping */ 3695 regval = er32(TSYNCRXCTL); 3696 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3697 regval |= tsync_rx_ctl; 3698 ew32(TSYNCRXCTL, regval); 3699 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3700 E1000_TSYNCRXCTL_TYPE_MASK)) != 3701 (regval & (E1000_TSYNCRXCTL_ENABLED | 3702 E1000_TSYNCRXCTL_TYPE_MASK))) { 3703 e_err("Timesync Rx Control register not set as expected\n"); 3704 return -EAGAIN; 3705 } 3706 3707 /* L2: define ethertype filter for time stamped packets */ 3708 if (is_l2) 3709 rxmtrl |= ETH_P_1588; 3710 3711 /* define which PTP packets get time stamped */ 3712 ew32(RXMTRL, rxmtrl); 3713 3714 /* Filter by destination port */ 3715 if (is_l4) { 3716 rxudp = PTP_EV_PORT; 3717 cpu_to_be16s(&rxudp); 3718 } 3719 ew32(RXUDP, rxudp); 3720 3721 e1e_flush(); 3722 3723 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3724 er32(RXSTMPH); 3725 er32(TXSTMPH); 3726 3727 /* Get and set the System Time Register SYSTIM base frequency */ 3728 ret_val = e1000e_get_base_timinca(adapter, ®val); 3729 if (ret_val) 3730 return ret_val; 3731 ew32(TIMINCA, regval); 3732 3733 /* reset the ns time counter */ 3734 timecounter_init(&adapter->tc, &adapter->cc, 3735 ktime_to_ns(ktime_get_real())); 3736 3737 return 0; 3738 } 3739 3740 /** 3741 * e1000_configure - configure the hardware for Rx and Tx 3742 * @adapter: private board structure 3743 **/ 3744 static void e1000_configure(struct e1000_adapter *adapter) 3745 { 3746 struct e1000_ring *rx_ring = adapter->rx_ring; 3747 3748 e1000e_set_rx_mode(adapter->netdev); 3749 3750 e1000_restore_vlan(adapter); 3751 e1000_init_manageability_pt(adapter); 3752 3753 e1000_configure_tx(adapter); 3754 3755 if (adapter->netdev->features & NETIF_F_RXHASH) 3756 e1000e_setup_rss_hash(adapter); 3757 e1000_setup_rctl(adapter); 3758 e1000_configure_rx(adapter); 3759 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3760 } 3761 3762 /** 3763 * e1000e_power_up_phy - restore link in case the phy was powered down 3764 * @adapter: address of board private structure 3765 * 3766 * The phy may be powered down to save power and turn off link when the 3767 * driver is unloaded and wake on lan is not enabled (among others) 3768 * *** this routine MUST be followed by a call to e1000e_reset *** 3769 **/ 3770 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3771 { 3772 if (adapter->hw.phy.ops.power_up) 3773 adapter->hw.phy.ops.power_up(&adapter->hw); 3774 3775 adapter->hw.mac.ops.setup_link(&adapter->hw); 3776 } 3777 3778 /** 3779 * e1000_power_down_phy - Power down the PHY 3780 * 3781 * Power down the PHY so no link is implied when interface is down. 3782 * The PHY cannot be powered down if management or WoL is active. 3783 */ 3784 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3785 { 3786 if (adapter->hw.phy.ops.power_down) 3787 adapter->hw.phy.ops.power_down(&adapter->hw); 3788 } 3789 3790 /** 3791 * e1000e_reset - bring the hardware into a known good state 3792 * 3793 * This function boots the hardware and enables some settings that 3794 * require a configuration cycle of the hardware - those cannot be 3795 * set/changed during runtime. After reset the device needs to be 3796 * properly configured for Rx, Tx etc. 3797 */ 3798 void e1000e_reset(struct e1000_adapter *adapter) 3799 { 3800 struct e1000_mac_info *mac = &adapter->hw.mac; 3801 struct e1000_fc_info *fc = &adapter->hw.fc; 3802 struct e1000_hw *hw = &adapter->hw; 3803 u32 tx_space, min_tx_space, min_rx_space; 3804 u32 pba = adapter->pba; 3805 u16 hwm; 3806 3807 /* reset Packet Buffer Allocation to default */ 3808 ew32(PBA, pba); 3809 3810 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 3811 /* To maintain wire speed transmits, the Tx FIFO should be 3812 * large enough to accommodate two full transmit packets, 3813 * rounded up to the next 1KB and expressed in KB. Likewise, 3814 * the Rx FIFO should be large enough to accommodate at least 3815 * one full receive packet and is similarly rounded up and 3816 * expressed in KB. 3817 */ 3818 pba = er32(PBA); 3819 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3820 tx_space = pba >> 16; 3821 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3822 pba &= 0xffff; 3823 /* the Tx fifo also stores 16 bytes of information about the Tx 3824 * but don't include ethernet FCS because hardware appends it 3825 */ 3826 min_tx_space = (adapter->max_frame_size + 3827 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 3828 min_tx_space = ALIGN(min_tx_space, 1024); 3829 min_tx_space >>= 10; 3830 /* software strips receive CRC, so leave room for it */ 3831 min_rx_space = adapter->max_frame_size; 3832 min_rx_space = ALIGN(min_rx_space, 1024); 3833 min_rx_space >>= 10; 3834 3835 /* If current Tx allocation is less than the min Tx FIFO size, 3836 * and the min Tx FIFO size is less than the current Rx FIFO 3837 * allocation, take space away from current Rx allocation 3838 */ 3839 if ((tx_space < min_tx_space) && 3840 ((min_tx_space - tx_space) < pba)) { 3841 pba -= min_tx_space - tx_space; 3842 3843 /* if short on Rx space, Rx wins and must trump Tx 3844 * adjustment 3845 */ 3846 if (pba < min_rx_space) 3847 pba = min_rx_space; 3848 } 3849 3850 ew32(PBA, pba); 3851 } 3852 3853 /* flow control settings 3854 * 3855 * The high water mark must be low enough to fit one full frame 3856 * (or the size used for early receive) above it in the Rx FIFO. 3857 * Set it to the lower of: 3858 * - 90% of the Rx FIFO size, and 3859 * - the full Rx FIFO size minus one full frame 3860 */ 3861 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 3862 fc->pause_time = 0xFFFF; 3863 else 3864 fc->pause_time = E1000_FC_PAUSE_TIME; 3865 fc->send_xon = true; 3866 fc->current_mode = fc->requested_mode; 3867 3868 switch (hw->mac.type) { 3869 case e1000_ich9lan: 3870 case e1000_ich10lan: 3871 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3872 pba = 14; 3873 ew32(PBA, pba); 3874 fc->high_water = 0x2800; 3875 fc->low_water = fc->high_water - 8; 3876 break; 3877 } 3878 /* fall-through */ 3879 default: 3880 hwm = min(((pba << 10) * 9 / 10), 3881 ((pba << 10) - adapter->max_frame_size)); 3882 3883 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 3884 fc->low_water = fc->high_water - 8; 3885 break; 3886 case e1000_pchlan: 3887 /* Workaround PCH LOM adapter hangs with certain network 3888 * loads. If hangs persist, try disabling Tx flow control. 3889 */ 3890 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3891 fc->high_water = 0x3500; 3892 fc->low_water = 0x1500; 3893 } else { 3894 fc->high_water = 0x5000; 3895 fc->low_water = 0x3000; 3896 } 3897 fc->refresh_time = 0x1000; 3898 break; 3899 case e1000_pch2lan: 3900 case e1000_pch_lpt: 3901 case e1000_pch_spt: 3902 fc->refresh_time = 0x0400; 3903 3904 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 3905 fc->high_water = 0x05C20; 3906 fc->low_water = 0x05048; 3907 fc->pause_time = 0x0650; 3908 break; 3909 } 3910 3911 pba = 14; 3912 ew32(PBA, pba); 3913 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 3914 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 3915 break; 3916 } 3917 3918 /* Alignment of Tx data is on an arbitrary byte boundary with the 3919 * maximum size per Tx descriptor limited only to the transmit 3920 * allocation of the packet buffer minus 96 bytes with an upper 3921 * limit of 24KB due to receive synchronization limitations. 3922 */ 3923 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 3924 24 << 10); 3925 3926 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 3927 * fit in receive buffer. 3928 */ 3929 if (adapter->itr_setting & 0x3) { 3930 if ((adapter->max_frame_size * 2) > (pba << 10)) { 3931 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 3932 dev_info(&adapter->pdev->dev, 3933 "Interrupt Throttle Rate off\n"); 3934 adapter->flags2 |= FLAG2_DISABLE_AIM; 3935 e1000e_write_itr(adapter, 0); 3936 } 3937 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 3938 dev_info(&adapter->pdev->dev, 3939 "Interrupt Throttle Rate on\n"); 3940 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 3941 adapter->itr = 20000; 3942 e1000e_write_itr(adapter, adapter->itr); 3943 } 3944 } 3945 3946 /* Allow time for pending master requests to run */ 3947 mac->ops.reset_hw(hw); 3948 3949 /* For parts with AMT enabled, let the firmware know 3950 * that the network interface is in control 3951 */ 3952 if (adapter->flags & FLAG_HAS_AMT) 3953 e1000e_get_hw_control(adapter); 3954 3955 ew32(WUC, 0); 3956 3957 if (mac->ops.init_hw(hw)) 3958 e_err("Hardware Error\n"); 3959 3960 e1000_update_mng_vlan(adapter); 3961 3962 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 3963 ew32(VET, ETH_P_8021Q); 3964 3965 e1000e_reset_adaptive(hw); 3966 3967 /* initialize systim and reset the ns time counter */ 3968 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3969 3970 /* Set EEE advertisement as appropriate */ 3971 if (adapter->flags2 & FLAG2_HAS_EEE) { 3972 s32 ret_val; 3973 u16 adv_addr; 3974 3975 switch (hw->phy.type) { 3976 case e1000_phy_82579: 3977 adv_addr = I82579_EEE_ADVERTISEMENT; 3978 break; 3979 case e1000_phy_i217: 3980 adv_addr = I217_EEE_ADVERTISEMENT; 3981 break; 3982 default: 3983 dev_err(&adapter->pdev->dev, 3984 "Invalid PHY type setting EEE advertisement\n"); 3985 return; 3986 } 3987 3988 ret_val = hw->phy.ops.acquire(hw); 3989 if (ret_val) { 3990 dev_err(&adapter->pdev->dev, 3991 "EEE advertisement - unable to acquire PHY\n"); 3992 return; 3993 } 3994 3995 e1000_write_emi_reg_locked(hw, adv_addr, 3996 hw->dev_spec.ich8lan.eee_disable ? 3997 0 : adapter->eee_advert); 3998 3999 hw->phy.ops.release(hw); 4000 } 4001 4002 if (!netif_running(adapter->netdev) && 4003 !test_bit(__E1000_TESTING, &adapter->state)) 4004 e1000_power_down_phy(adapter); 4005 4006 e1000_get_phy_info(hw); 4007 4008 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4009 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4010 u16 phy_data = 0; 4011 /* speed up time to link by disabling smart power down, ignore 4012 * the return value of this function because there is nothing 4013 * different we would do if it failed 4014 */ 4015 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4016 phy_data &= ~IGP02E1000_PM_SPD; 4017 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4018 } 4019 } 4020 4021 int e1000e_up(struct e1000_adapter *adapter) 4022 { 4023 struct e1000_hw *hw = &adapter->hw; 4024 4025 /* hardware has been reset, we need to reload some things */ 4026 e1000_configure(adapter); 4027 4028 clear_bit(__E1000_DOWN, &adapter->state); 4029 4030 if (adapter->msix_entries) 4031 e1000_configure_msix(adapter); 4032 e1000_irq_enable(adapter); 4033 4034 netif_start_queue(adapter->netdev); 4035 4036 /* fire a link change interrupt to start the watchdog */ 4037 if (adapter->msix_entries) 4038 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 4039 else 4040 ew32(ICS, E1000_ICS_LSC); 4041 4042 return 0; 4043 } 4044 4045 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4046 { 4047 struct e1000_hw *hw = &adapter->hw; 4048 4049 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4050 return; 4051 4052 /* flush pending descriptor writebacks to memory */ 4053 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4054 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4055 4056 /* execute the writes immediately */ 4057 e1e_flush(); 4058 4059 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4060 * write is successful 4061 */ 4062 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4063 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4064 4065 /* execute the writes immediately */ 4066 e1e_flush(); 4067 } 4068 4069 static void e1000e_update_stats(struct e1000_adapter *adapter); 4070 4071 /** 4072 * e1000e_down - quiesce the device and optionally reset the hardware 4073 * @adapter: board private structure 4074 * @reset: boolean flag to reset the hardware or not 4075 */ 4076 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4077 { 4078 struct net_device *netdev = adapter->netdev; 4079 struct e1000_hw *hw = &adapter->hw; 4080 u32 tctl, rctl; 4081 4082 /* signal that we're down so the interrupt handler does not 4083 * reschedule our watchdog timer 4084 */ 4085 set_bit(__E1000_DOWN, &adapter->state); 4086 4087 netif_carrier_off(netdev); 4088 4089 /* disable receives in the hardware */ 4090 rctl = er32(RCTL); 4091 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4092 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4093 /* flush and sleep below */ 4094 4095 netif_stop_queue(netdev); 4096 4097 /* disable transmits in the hardware */ 4098 tctl = er32(TCTL); 4099 tctl &= ~E1000_TCTL_EN; 4100 ew32(TCTL, tctl); 4101 4102 /* flush both disables and wait for them to finish */ 4103 e1e_flush(); 4104 usleep_range(10000, 20000); 4105 4106 e1000_irq_disable(adapter); 4107 4108 napi_synchronize(&adapter->napi); 4109 4110 del_timer_sync(&adapter->watchdog_timer); 4111 del_timer_sync(&adapter->phy_info_timer); 4112 4113 spin_lock(&adapter->stats64_lock); 4114 e1000e_update_stats(adapter); 4115 spin_unlock(&adapter->stats64_lock); 4116 4117 e1000e_flush_descriptors(adapter); 4118 e1000_clean_tx_ring(adapter->tx_ring); 4119 e1000_clean_rx_ring(adapter->rx_ring); 4120 4121 adapter->link_speed = 0; 4122 adapter->link_duplex = 0; 4123 4124 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4125 if ((hw->mac.type >= e1000_pch2lan) && 4126 (adapter->netdev->mtu > ETH_DATA_LEN) && 4127 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4128 e_dbg("failed to disable jumbo frame workaround mode\n"); 4129 4130 if (reset && !pci_channel_offline(adapter->pdev)) 4131 e1000e_reset(adapter); 4132 } 4133 4134 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4135 { 4136 might_sleep(); 4137 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4138 usleep_range(1000, 2000); 4139 e1000e_down(adapter, true); 4140 e1000e_up(adapter); 4141 clear_bit(__E1000_RESETTING, &adapter->state); 4142 } 4143 4144 /** 4145 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4146 * @cc: cyclecounter structure 4147 **/ 4148 static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc) 4149 { 4150 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4151 cc); 4152 struct e1000_hw *hw = &adapter->hw; 4153 cycle_t systim, systim_next; 4154 4155 /* latch SYSTIMH on read of SYSTIML */ 4156 systim = (cycle_t)er32(SYSTIML); 4157 systim |= (cycle_t)er32(SYSTIMH) << 32; 4158 4159 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) { 4160 u64 incvalue, time_delta, rem, temp; 4161 int i; 4162 4163 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L 4164 * check to see that the time is incrementing at a reasonable 4165 * rate and is a multiple of incvalue 4166 */ 4167 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4168 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4169 /* latch SYSTIMH on read of SYSTIML */ 4170 systim_next = (cycle_t)er32(SYSTIML); 4171 systim_next |= (cycle_t)er32(SYSTIMH) << 32; 4172 4173 time_delta = systim_next - systim; 4174 temp = time_delta; 4175 rem = do_div(temp, incvalue); 4176 4177 systim = systim_next; 4178 4179 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && 4180 (rem == 0)) 4181 break; 4182 } 4183 } 4184 return systim; 4185 } 4186 4187 /** 4188 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4189 * @adapter: board private structure to initialize 4190 * 4191 * e1000_sw_init initializes the Adapter private data structure. 4192 * Fields are initialized based on PCI device information and 4193 * OS network device settings (MTU size). 4194 **/ 4195 static int e1000_sw_init(struct e1000_adapter *adapter) 4196 { 4197 struct net_device *netdev = adapter->netdev; 4198 4199 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; 4200 adapter->rx_ps_bsize0 = 128; 4201 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4202 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4203 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4204 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4205 4206 spin_lock_init(&adapter->stats64_lock); 4207 4208 e1000e_set_interrupt_capability(adapter); 4209 4210 if (e1000_alloc_queues(adapter)) 4211 return -ENOMEM; 4212 4213 /* Setup hardware time stamping cyclecounter */ 4214 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4215 adapter->cc.read = e1000e_cyclecounter_read; 4216 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4217 adapter->cc.mult = 1; 4218 /* cc.shift set in e1000e_get_base_tininca() */ 4219 4220 spin_lock_init(&adapter->systim_lock); 4221 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4222 } 4223 4224 /* Explicitly disable IRQ since the NIC can be in any state. */ 4225 e1000_irq_disable(adapter); 4226 4227 set_bit(__E1000_DOWN, &adapter->state); 4228 return 0; 4229 } 4230 4231 /** 4232 * e1000_intr_msi_test - Interrupt Handler 4233 * @irq: interrupt number 4234 * @data: pointer to a network interface device structure 4235 **/ 4236 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4237 { 4238 struct net_device *netdev = data; 4239 struct e1000_adapter *adapter = netdev_priv(netdev); 4240 struct e1000_hw *hw = &adapter->hw; 4241 u32 icr = er32(ICR); 4242 4243 e_dbg("icr is %08X\n", icr); 4244 if (icr & E1000_ICR_RXSEQ) { 4245 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4246 /* Force memory writes to complete before acknowledging the 4247 * interrupt is handled. 4248 */ 4249 wmb(); 4250 } 4251 4252 return IRQ_HANDLED; 4253 } 4254 4255 /** 4256 * e1000_test_msi_interrupt - Returns 0 for successful test 4257 * @adapter: board private struct 4258 * 4259 * code flow taken from tg3.c 4260 **/ 4261 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4262 { 4263 struct net_device *netdev = adapter->netdev; 4264 struct e1000_hw *hw = &adapter->hw; 4265 int err; 4266 4267 /* poll_enable hasn't been called yet, so don't need disable */ 4268 /* clear any pending events */ 4269 er32(ICR); 4270 4271 /* free the real vector and request a test handler */ 4272 e1000_free_irq(adapter); 4273 e1000e_reset_interrupt_capability(adapter); 4274 4275 /* Assume that the test fails, if it succeeds then the test 4276 * MSI irq handler will unset this flag 4277 */ 4278 adapter->flags |= FLAG_MSI_TEST_FAILED; 4279 4280 err = pci_enable_msi(adapter->pdev); 4281 if (err) 4282 goto msi_test_failed; 4283 4284 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4285 netdev->name, netdev); 4286 if (err) { 4287 pci_disable_msi(adapter->pdev); 4288 goto msi_test_failed; 4289 } 4290 4291 /* Force memory writes to complete before enabling and firing an 4292 * interrupt. 4293 */ 4294 wmb(); 4295 4296 e1000_irq_enable(adapter); 4297 4298 /* fire an unusual interrupt on the test handler */ 4299 ew32(ICS, E1000_ICS_RXSEQ); 4300 e1e_flush(); 4301 msleep(100); 4302 4303 e1000_irq_disable(adapter); 4304 4305 rmb(); /* read flags after interrupt has been fired */ 4306 4307 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4308 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4309 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4310 } else { 4311 e_dbg("MSI interrupt test succeeded!\n"); 4312 } 4313 4314 free_irq(adapter->pdev->irq, netdev); 4315 pci_disable_msi(adapter->pdev); 4316 4317 msi_test_failed: 4318 e1000e_set_interrupt_capability(adapter); 4319 return e1000_request_irq(adapter); 4320 } 4321 4322 /** 4323 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4324 * @adapter: board private struct 4325 * 4326 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4327 **/ 4328 static int e1000_test_msi(struct e1000_adapter *adapter) 4329 { 4330 int err; 4331 u16 pci_cmd; 4332 4333 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4334 return 0; 4335 4336 /* disable SERR in case the MSI write causes a master abort */ 4337 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4338 if (pci_cmd & PCI_COMMAND_SERR) 4339 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4340 pci_cmd & ~PCI_COMMAND_SERR); 4341 4342 err = e1000_test_msi_interrupt(adapter); 4343 4344 /* re-enable SERR */ 4345 if (pci_cmd & PCI_COMMAND_SERR) { 4346 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4347 pci_cmd |= PCI_COMMAND_SERR; 4348 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4349 } 4350 4351 return err; 4352 } 4353 4354 /** 4355 * e1000_open - Called when a network interface is made active 4356 * @netdev: network interface device structure 4357 * 4358 * Returns 0 on success, negative value on failure 4359 * 4360 * The open entry point is called when a network interface is made 4361 * active by the system (IFF_UP). At this point all resources needed 4362 * for transmit and receive operations are allocated, the interrupt 4363 * handler is registered with the OS, the watchdog timer is started, 4364 * and the stack is notified that the interface is ready. 4365 **/ 4366 static int e1000_open(struct net_device *netdev) 4367 { 4368 struct e1000_adapter *adapter = netdev_priv(netdev); 4369 struct e1000_hw *hw = &adapter->hw; 4370 struct pci_dev *pdev = adapter->pdev; 4371 int err; 4372 4373 /* disallow open during test */ 4374 if (test_bit(__E1000_TESTING, &adapter->state)) 4375 return -EBUSY; 4376 4377 pm_runtime_get_sync(&pdev->dev); 4378 4379 netif_carrier_off(netdev); 4380 4381 /* allocate transmit descriptors */ 4382 err = e1000e_setup_tx_resources(adapter->tx_ring); 4383 if (err) 4384 goto err_setup_tx; 4385 4386 /* allocate receive descriptors */ 4387 err = e1000e_setup_rx_resources(adapter->rx_ring); 4388 if (err) 4389 goto err_setup_rx; 4390 4391 /* If AMT is enabled, let the firmware know that the network 4392 * interface is now open and reset the part to a known state. 4393 */ 4394 if (adapter->flags & FLAG_HAS_AMT) { 4395 e1000e_get_hw_control(adapter); 4396 e1000e_reset(adapter); 4397 } 4398 4399 e1000e_power_up_phy(adapter); 4400 4401 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4402 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4403 e1000_update_mng_vlan(adapter); 4404 4405 /* DMA latency requirement to workaround jumbo issue */ 4406 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4407 PM_QOS_DEFAULT_VALUE); 4408 4409 /* before we allocate an interrupt, we must be ready to handle it. 4410 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4411 * as soon as we call pci_request_irq, so we have to setup our 4412 * clean_rx handler before we do so. 4413 */ 4414 e1000_configure(adapter); 4415 4416 err = e1000_request_irq(adapter); 4417 if (err) 4418 goto err_req_irq; 4419 4420 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4421 * ignore e1000e MSI messages, which means we need to test our MSI 4422 * interrupt now 4423 */ 4424 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4425 err = e1000_test_msi(adapter); 4426 if (err) { 4427 e_err("Interrupt allocation failed\n"); 4428 goto err_req_irq; 4429 } 4430 } 4431 4432 /* From here on the code is the same as e1000e_up() */ 4433 clear_bit(__E1000_DOWN, &adapter->state); 4434 4435 napi_enable(&adapter->napi); 4436 4437 e1000_irq_enable(adapter); 4438 4439 adapter->tx_hang_recheck = false; 4440 netif_start_queue(netdev); 4441 4442 hw->mac.get_link_status = true; 4443 pm_runtime_put(&pdev->dev); 4444 4445 /* fire a link status change interrupt to start the watchdog */ 4446 if (adapter->msix_entries) 4447 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER); 4448 else 4449 ew32(ICS, E1000_ICS_LSC); 4450 4451 return 0; 4452 4453 err_req_irq: 4454 e1000e_release_hw_control(adapter); 4455 e1000_power_down_phy(adapter); 4456 e1000e_free_rx_resources(adapter->rx_ring); 4457 err_setup_rx: 4458 e1000e_free_tx_resources(adapter->tx_ring); 4459 err_setup_tx: 4460 e1000e_reset(adapter); 4461 pm_runtime_put_sync(&pdev->dev); 4462 4463 return err; 4464 } 4465 4466 /** 4467 * e1000_close - Disables a network interface 4468 * @netdev: network interface device structure 4469 * 4470 * Returns 0, this is not allowed to fail 4471 * 4472 * The close entry point is called when an interface is de-activated 4473 * by the OS. The hardware is still under the drivers control, but 4474 * needs to be disabled. A global MAC reset is issued to stop the 4475 * hardware, and all transmit and receive resources are freed. 4476 **/ 4477 static int e1000_close(struct net_device *netdev) 4478 { 4479 struct e1000_adapter *adapter = netdev_priv(netdev); 4480 struct pci_dev *pdev = adapter->pdev; 4481 int count = E1000_CHECK_RESET_COUNT; 4482 4483 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4484 usleep_range(10000, 20000); 4485 4486 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4487 4488 pm_runtime_get_sync(&pdev->dev); 4489 4490 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4491 e1000e_down(adapter, true); 4492 e1000_free_irq(adapter); 4493 4494 /* Link status message must follow this format */ 4495 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4496 } 4497 4498 napi_disable(&adapter->napi); 4499 4500 e1000e_free_tx_resources(adapter->tx_ring); 4501 e1000e_free_rx_resources(adapter->rx_ring); 4502 4503 /* kill manageability vlan ID if supported, but not if a vlan with 4504 * the same ID is registered on the host OS (let 8021q kill it) 4505 */ 4506 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4507 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4508 adapter->mng_vlan_id); 4509 4510 /* If AMT is enabled, let the firmware know that the network 4511 * interface is now closed 4512 */ 4513 if ((adapter->flags & FLAG_HAS_AMT) && 4514 !test_bit(__E1000_TESTING, &adapter->state)) 4515 e1000e_release_hw_control(adapter); 4516 4517 pm_qos_remove_request(&adapter->pm_qos_req); 4518 4519 pm_runtime_put_sync(&pdev->dev); 4520 4521 return 0; 4522 } 4523 4524 /** 4525 * e1000_set_mac - Change the Ethernet Address of the NIC 4526 * @netdev: network interface device structure 4527 * @p: pointer to an address structure 4528 * 4529 * Returns 0 on success, negative on failure 4530 **/ 4531 static int e1000_set_mac(struct net_device *netdev, void *p) 4532 { 4533 struct e1000_adapter *adapter = netdev_priv(netdev); 4534 struct e1000_hw *hw = &adapter->hw; 4535 struct sockaddr *addr = p; 4536 4537 if (!is_valid_ether_addr(addr->sa_data)) 4538 return -EADDRNOTAVAIL; 4539 4540 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4541 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4542 4543 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4544 4545 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4546 /* activate the work around */ 4547 e1000e_set_laa_state_82571(&adapter->hw, 1); 4548 4549 /* Hold a copy of the LAA in RAR[14] This is done so that 4550 * between the time RAR[0] gets clobbered and the time it 4551 * gets fixed (in e1000_watchdog), the actual LAA is in one 4552 * of the RARs and no incoming packets directed to this port 4553 * are dropped. Eventually the LAA will be in RAR[0] and 4554 * RAR[14] 4555 */ 4556 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4557 adapter->hw.mac.rar_entry_count - 1); 4558 } 4559 4560 return 0; 4561 } 4562 4563 /** 4564 * e1000e_update_phy_task - work thread to update phy 4565 * @work: pointer to our work struct 4566 * 4567 * this worker thread exists because we must acquire a 4568 * semaphore to read the phy, which we could msleep while 4569 * waiting for it, and we can't msleep in a timer. 4570 **/ 4571 static void e1000e_update_phy_task(struct work_struct *work) 4572 { 4573 struct e1000_adapter *adapter = container_of(work, 4574 struct e1000_adapter, 4575 update_phy_task); 4576 struct e1000_hw *hw = &adapter->hw; 4577 4578 if (test_bit(__E1000_DOWN, &adapter->state)) 4579 return; 4580 4581 e1000_get_phy_info(hw); 4582 4583 /* Enable EEE on 82579 after link up */ 4584 if (hw->phy.type >= e1000_phy_82579) 4585 e1000_set_eee_pchlan(hw); 4586 } 4587 4588 /** 4589 * e1000_update_phy_info - timre call-back to update PHY info 4590 * @data: pointer to adapter cast into an unsigned long 4591 * 4592 * Need to wait a few seconds after link up to get diagnostic information from 4593 * the phy 4594 **/ 4595 static void e1000_update_phy_info(unsigned long data) 4596 { 4597 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 4598 4599 if (test_bit(__E1000_DOWN, &adapter->state)) 4600 return; 4601 4602 schedule_work(&adapter->update_phy_task); 4603 } 4604 4605 /** 4606 * e1000e_update_phy_stats - Update the PHY statistics counters 4607 * @adapter: board private structure 4608 * 4609 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4610 **/ 4611 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4612 { 4613 struct e1000_hw *hw = &adapter->hw; 4614 s32 ret_val; 4615 u16 phy_data; 4616 4617 ret_val = hw->phy.ops.acquire(hw); 4618 if (ret_val) 4619 return; 4620 4621 /* A page set is expensive so check if already on desired page. 4622 * If not, set to the page with the PHY status registers. 4623 */ 4624 hw->phy.addr = 1; 4625 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4626 &phy_data); 4627 if (ret_val) 4628 goto release; 4629 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4630 ret_val = hw->phy.ops.set_page(hw, 4631 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4632 if (ret_val) 4633 goto release; 4634 } 4635 4636 /* Single Collision Count */ 4637 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4638 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4639 if (!ret_val) 4640 adapter->stats.scc += phy_data; 4641 4642 /* Excessive Collision Count */ 4643 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4644 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4645 if (!ret_val) 4646 adapter->stats.ecol += phy_data; 4647 4648 /* Multiple Collision Count */ 4649 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4650 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4651 if (!ret_val) 4652 adapter->stats.mcc += phy_data; 4653 4654 /* Late Collision Count */ 4655 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4656 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4657 if (!ret_val) 4658 adapter->stats.latecol += phy_data; 4659 4660 /* Collision Count - also used for adaptive IFS */ 4661 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4662 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4663 if (!ret_val) 4664 hw->mac.collision_delta = phy_data; 4665 4666 /* Defer Count */ 4667 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4668 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4669 if (!ret_val) 4670 adapter->stats.dc += phy_data; 4671 4672 /* Transmit with no CRS */ 4673 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4674 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4675 if (!ret_val) 4676 adapter->stats.tncrs += phy_data; 4677 4678 release: 4679 hw->phy.ops.release(hw); 4680 } 4681 4682 /** 4683 * e1000e_update_stats - Update the board statistics counters 4684 * @adapter: board private structure 4685 **/ 4686 static void e1000e_update_stats(struct e1000_adapter *adapter) 4687 { 4688 struct net_device *netdev = adapter->netdev; 4689 struct e1000_hw *hw = &adapter->hw; 4690 struct pci_dev *pdev = adapter->pdev; 4691 4692 /* Prevent stats update while adapter is being reset, or if the pci 4693 * connection is down. 4694 */ 4695 if (adapter->link_speed == 0) 4696 return; 4697 if (pci_channel_offline(pdev)) 4698 return; 4699 4700 adapter->stats.crcerrs += er32(CRCERRS); 4701 adapter->stats.gprc += er32(GPRC); 4702 adapter->stats.gorc += er32(GORCL); 4703 er32(GORCH); /* Clear gorc */ 4704 adapter->stats.bprc += er32(BPRC); 4705 adapter->stats.mprc += er32(MPRC); 4706 adapter->stats.roc += er32(ROC); 4707 4708 adapter->stats.mpc += er32(MPC); 4709 4710 /* Half-duplex statistics */ 4711 if (adapter->link_duplex == HALF_DUPLEX) { 4712 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4713 e1000e_update_phy_stats(adapter); 4714 } else { 4715 adapter->stats.scc += er32(SCC); 4716 adapter->stats.ecol += er32(ECOL); 4717 adapter->stats.mcc += er32(MCC); 4718 adapter->stats.latecol += er32(LATECOL); 4719 adapter->stats.dc += er32(DC); 4720 4721 hw->mac.collision_delta = er32(COLC); 4722 4723 if ((hw->mac.type != e1000_82574) && 4724 (hw->mac.type != e1000_82583)) 4725 adapter->stats.tncrs += er32(TNCRS); 4726 } 4727 adapter->stats.colc += hw->mac.collision_delta; 4728 } 4729 4730 adapter->stats.xonrxc += er32(XONRXC); 4731 adapter->stats.xontxc += er32(XONTXC); 4732 adapter->stats.xoffrxc += er32(XOFFRXC); 4733 adapter->stats.xofftxc += er32(XOFFTXC); 4734 adapter->stats.gptc += er32(GPTC); 4735 adapter->stats.gotc += er32(GOTCL); 4736 er32(GOTCH); /* Clear gotc */ 4737 adapter->stats.rnbc += er32(RNBC); 4738 adapter->stats.ruc += er32(RUC); 4739 4740 adapter->stats.mptc += er32(MPTC); 4741 adapter->stats.bptc += er32(BPTC); 4742 4743 /* used for adaptive IFS */ 4744 4745 hw->mac.tx_packet_delta = er32(TPT); 4746 adapter->stats.tpt += hw->mac.tx_packet_delta; 4747 4748 adapter->stats.algnerrc += er32(ALGNERRC); 4749 adapter->stats.rxerrc += er32(RXERRC); 4750 adapter->stats.cexterr += er32(CEXTERR); 4751 adapter->stats.tsctc += er32(TSCTC); 4752 adapter->stats.tsctfc += er32(TSCTFC); 4753 4754 /* Fill out the OS statistics structure */ 4755 netdev->stats.multicast = adapter->stats.mprc; 4756 netdev->stats.collisions = adapter->stats.colc; 4757 4758 /* Rx Errors */ 4759 4760 /* RLEC on some newer hardware can be incorrect so build 4761 * our own version based on RUC and ROC 4762 */ 4763 netdev->stats.rx_errors = adapter->stats.rxerrc + 4764 adapter->stats.crcerrs + adapter->stats.algnerrc + 4765 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4766 netdev->stats.rx_length_errors = adapter->stats.ruc + 4767 adapter->stats.roc; 4768 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 4769 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 4770 netdev->stats.rx_missed_errors = adapter->stats.mpc; 4771 4772 /* Tx Errors */ 4773 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 4774 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 4775 netdev->stats.tx_window_errors = adapter->stats.latecol; 4776 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 4777 4778 /* Tx Dropped needs to be maintained elsewhere */ 4779 4780 /* Management Stats */ 4781 adapter->stats.mgptc += er32(MGTPTC); 4782 adapter->stats.mgprc += er32(MGTPRC); 4783 adapter->stats.mgpdc += er32(MGTPDC); 4784 4785 /* Correctable ECC Errors */ 4786 if ((hw->mac.type == e1000_pch_lpt) || 4787 (hw->mac.type == e1000_pch_spt)) { 4788 u32 pbeccsts = er32(PBECCSTS); 4789 4790 adapter->corr_errors += 4791 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 4792 adapter->uncorr_errors += 4793 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 4794 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 4795 } 4796 } 4797 4798 /** 4799 * e1000_phy_read_status - Update the PHY register status snapshot 4800 * @adapter: board private structure 4801 **/ 4802 static void e1000_phy_read_status(struct e1000_adapter *adapter) 4803 { 4804 struct e1000_hw *hw = &adapter->hw; 4805 struct e1000_phy_regs *phy = &adapter->phy_regs; 4806 4807 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 4808 (er32(STATUS) & E1000_STATUS_LU) && 4809 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 4810 int ret_val; 4811 4812 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 4813 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 4814 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 4815 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 4816 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 4817 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 4818 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 4819 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 4820 if (ret_val) 4821 e_warn("Error reading PHY register\n"); 4822 } else { 4823 /* Do not read PHY registers if link is not up 4824 * Set values to typical power-on defaults 4825 */ 4826 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 4827 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 4828 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 4829 BMSR_ERCAP); 4830 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 4831 ADVERTISE_ALL | ADVERTISE_CSMA); 4832 phy->lpa = 0; 4833 phy->expansion = EXPANSION_ENABLENPAGE; 4834 phy->ctrl1000 = ADVERTISE_1000FULL; 4835 phy->stat1000 = 0; 4836 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 4837 } 4838 } 4839 4840 static void e1000_print_link_info(struct e1000_adapter *adapter) 4841 { 4842 struct e1000_hw *hw = &adapter->hw; 4843 u32 ctrl = er32(CTRL); 4844 4845 /* Link status message must follow this format for user tools */ 4846 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4847 adapter->netdev->name, adapter->link_speed, 4848 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 4849 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 4850 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 4851 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 4852 } 4853 4854 static bool e1000e_has_link(struct e1000_adapter *adapter) 4855 { 4856 struct e1000_hw *hw = &adapter->hw; 4857 bool link_active = false; 4858 s32 ret_val = 0; 4859 4860 /* get_link_status is set on LSC (link status) interrupt or 4861 * Rx sequence error interrupt. get_link_status will stay 4862 * false until the check_for_link establishes link 4863 * for copper adapters ONLY 4864 */ 4865 switch (hw->phy.media_type) { 4866 case e1000_media_type_copper: 4867 if (hw->mac.get_link_status) { 4868 ret_val = hw->mac.ops.check_for_link(hw); 4869 link_active = !hw->mac.get_link_status; 4870 } else { 4871 link_active = true; 4872 } 4873 break; 4874 case e1000_media_type_fiber: 4875 ret_val = hw->mac.ops.check_for_link(hw); 4876 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 4877 break; 4878 case e1000_media_type_internal_serdes: 4879 ret_val = hw->mac.ops.check_for_link(hw); 4880 link_active = adapter->hw.mac.serdes_has_link; 4881 break; 4882 default: 4883 case e1000_media_type_unknown: 4884 break; 4885 } 4886 4887 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 4888 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 4889 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 4890 e_info("Gigabit has been disabled, downgrading speed\n"); 4891 } 4892 4893 return link_active; 4894 } 4895 4896 static void e1000e_enable_receives(struct e1000_adapter *adapter) 4897 { 4898 /* make sure the receive unit is started */ 4899 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 4900 (adapter->flags & FLAG_RESTART_NOW)) { 4901 struct e1000_hw *hw = &adapter->hw; 4902 u32 rctl = er32(RCTL); 4903 4904 ew32(RCTL, rctl | E1000_RCTL_EN); 4905 adapter->flags &= ~FLAG_RESTART_NOW; 4906 } 4907 } 4908 4909 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 4910 { 4911 struct e1000_hw *hw = &adapter->hw; 4912 4913 /* With 82574 controllers, PHY needs to be checked periodically 4914 * for hung state and reset, if two calls return true 4915 */ 4916 if (e1000_check_phy_82574(hw)) 4917 adapter->phy_hang_count++; 4918 else 4919 adapter->phy_hang_count = 0; 4920 4921 if (adapter->phy_hang_count > 1) { 4922 adapter->phy_hang_count = 0; 4923 e_dbg("PHY appears hung - resetting\n"); 4924 schedule_work(&adapter->reset_task); 4925 } 4926 } 4927 4928 /** 4929 * e1000_watchdog - Timer Call-back 4930 * @data: pointer to adapter cast into an unsigned long 4931 **/ 4932 static void e1000_watchdog(unsigned long data) 4933 { 4934 struct e1000_adapter *adapter = (struct e1000_adapter *)data; 4935 4936 /* Do the rest outside of interrupt context */ 4937 schedule_work(&adapter->watchdog_task); 4938 4939 /* TODO: make this use queue_delayed_work() */ 4940 } 4941 4942 static void e1000_watchdog_task(struct work_struct *work) 4943 { 4944 struct e1000_adapter *adapter = container_of(work, 4945 struct e1000_adapter, 4946 watchdog_task); 4947 struct net_device *netdev = adapter->netdev; 4948 struct e1000_mac_info *mac = &adapter->hw.mac; 4949 struct e1000_phy_info *phy = &adapter->hw.phy; 4950 struct e1000_ring *tx_ring = adapter->tx_ring; 4951 struct e1000_hw *hw = &adapter->hw; 4952 u32 link, tctl; 4953 4954 if (test_bit(__E1000_DOWN, &adapter->state)) 4955 return; 4956 4957 link = e1000e_has_link(adapter); 4958 if ((netif_carrier_ok(netdev)) && link) { 4959 /* Cancel scheduled suspend requests. */ 4960 pm_runtime_resume(netdev->dev.parent); 4961 4962 e1000e_enable_receives(adapter); 4963 goto link_up; 4964 } 4965 4966 if ((e1000e_enable_tx_pkt_filtering(hw)) && 4967 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 4968 e1000_update_mng_vlan(adapter); 4969 4970 if (link) { 4971 if (!netif_carrier_ok(netdev)) { 4972 bool txb2b = true; 4973 4974 /* Cancel scheduled suspend requests. */ 4975 pm_runtime_resume(netdev->dev.parent); 4976 4977 /* update snapshot of PHY registers on LSC */ 4978 e1000_phy_read_status(adapter); 4979 mac->ops.get_link_up_info(&adapter->hw, 4980 &adapter->link_speed, 4981 &adapter->link_duplex); 4982 e1000_print_link_info(adapter); 4983 4984 /* check if SmartSpeed worked */ 4985 e1000e_check_downshift(hw); 4986 if (phy->speed_downgraded) 4987 netdev_warn(netdev, 4988 "Link Speed was downgraded by SmartSpeed\n"); 4989 4990 /* On supported PHYs, check for duplex mismatch only 4991 * if link has autonegotiated at 10/100 half 4992 */ 4993 if ((hw->phy.type == e1000_phy_igp_3 || 4994 hw->phy.type == e1000_phy_bm) && 4995 hw->mac.autoneg && 4996 (adapter->link_speed == SPEED_10 || 4997 adapter->link_speed == SPEED_100) && 4998 (adapter->link_duplex == HALF_DUPLEX)) { 4999 u16 autoneg_exp; 5000 5001 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5002 5003 if (!(autoneg_exp & EXPANSION_NWAY)) 5004 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5005 } 5006 5007 /* adjust timeout factor according to speed/duplex */ 5008 adapter->tx_timeout_factor = 1; 5009 switch (adapter->link_speed) { 5010 case SPEED_10: 5011 txb2b = false; 5012 adapter->tx_timeout_factor = 16; 5013 break; 5014 case SPEED_100: 5015 txb2b = false; 5016 adapter->tx_timeout_factor = 10; 5017 break; 5018 } 5019 5020 /* workaround: re-program speed mode bit after 5021 * link-up event 5022 */ 5023 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5024 !txb2b) { 5025 u32 tarc0; 5026 5027 tarc0 = er32(TARC(0)); 5028 tarc0 &= ~SPEED_MODE_BIT; 5029 ew32(TARC(0), tarc0); 5030 } 5031 5032 /* disable TSO for pcie and 10/100 speeds, to avoid 5033 * some hardware issues 5034 */ 5035 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5036 switch (adapter->link_speed) { 5037 case SPEED_10: 5038 case SPEED_100: 5039 e_info("10/100 speed: disabling TSO\n"); 5040 netdev->features &= ~NETIF_F_TSO; 5041 netdev->features &= ~NETIF_F_TSO6; 5042 break; 5043 case SPEED_1000: 5044 netdev->features |= NETIF_F_TSO; 5045 netdev->features |= NETIF_F_TSO6; 5046 break; 5047 default: 5048 /* oops */ 5049 break; 5050 } 5051 } 5052 5053 /* enable transmits in the hardware, need to do this 5054 * after setting TARC(0) 5055 */ 5056 tctl = er32(TCTL); 5057 tctl |= E1000_TCTL_EN; 5058 ew32(TCTL, tctl); 5059 5060 /* Perform any post-link-up configuration before 5061 * reporting link up. 5062 */ 5063 if (phy->ops.cfg_on_link_up) 5064 phy->ops.cfg_on_link_up(hw); 5065 5066 netif_carrier_on(netdev); 5067 5068 if (!test_bit(__E1000_DOWN, &adapter->state)) 5069 mod_timer(&adapter->phy_info_timer, 5070 round_jiffies(jiffies + 2 * HZ)); 5071 } 5072 } else { 5073 if (netif_carrier_ok(netdev)) { 5074 adapter->link_speed = 0; 5075 adapter->link_duplex = 0; 5076 /* Link status message must follow this format */ 5077 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 5078 netif_carrier_off(netdev); 5079 if (!test_bit(__E1000_DOWN, &adapter->state)) 5080 mod_timer(&adapter->phy_info_timer, 5081 round_jiffies(jiffies + 2 * HZ)); 5082 5083 /* 8000ES2LAN requires a Rx packet buffer work-around 5084 * on link down event; reset the controller to flush 5085 * the Rx packet buffer. 5086 */ 5087 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5088 adapter->flags |= FLAG_RESTART_NOW; 5089 else 5090 pm_schedule_suspend(netdev->dev.parent, 5091 LINK_TIMEOUT); 5092 } 5093 } 5094 5095 link_up: 5096 spin_lock(&adapter->stats64_lock); 5097 e1000e_update_stats(adapter); 5098 5099 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5100 adapter->tpt_old = adapter->stats.tpt; 5101 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5102 adapter->colc_old = adapter->stats.colc; 5103 5104 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5105 adapter->gorc_old = adapter->stats.gorc; 5106 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5107 adapter->gotc_old = adapter->stats.gotc; 5108 spin_unlock(&adapter->stats64_lock); 5109 5110 /* If the link is lost the controller stops DMA, but 5111 * if there is queued Tx work it cannot be done. So 5112 * reset the controller to flush the Tx packet buffers. 5113 */ 5114 if (!netif_carrier_ok(netdev) && 5115 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5116 adapter->flags |= FLAG_RESTART_NOW; 5117 5118 /* If reset is necessary, do it outside of interrupt context. */ 5119 if (adapter->flags & FLAG_RESTART_NOW) { 5120 schedule_work(&adapter->reset_task); 5121 /* return immediately since reset is imminent */ 5122 return; 5123 } 5124 5125 e1000e_update_adaptive(&adapter->hw); 5126 5127 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5128 if (adapter->itr_setting == 4) { 5129 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5130 * Total asymmetrical Tx or Rx gets ITR=8000; 5131 * everyone else is between 2000-8000. 5132 */ 5133 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5134 u32 dif = (adapter->gotc > adapter->gorc ? 5135 adapter->gotc - adapter->gorc : 5136 adapter->gorc - adapter->gotc) / 10000; 5137 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5138 5139 e1000e_write_itr(adapter, itr); 5140 } 5141 5142 /* Cause software interrupt to ensure Rx ring is cleaned */ 5143 if (adapter->msix_entries) 5144 ew32(ICS, adapter->rx_ring->ims_val); 5145 else 5146 ew32(ICS, E1000_ICS_RXDMT0); 5147 5148 /* flush pending descriptors to memory before detecting Tx hang */ 5149 e1000e_flush_descriptors(adapter); 5150 5151 /* Force detection of hung controller every watchdog period */ 5152 adapter->detect_tx_hung = true; 5153 5154 /* With 82571 controllers, LAA may be overwritten due to controller 5155 * reset from the other port. Set the appropriate LAA in RAR[0] 5156 */ 5157 if (e1000e_get_laa_state_82571(hw)) 5158 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5159 5160 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5161 e1000e_check_82574_phy_workaround(adapter); 5162 5163 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5164 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5165 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5166 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5167 er32(RXSTMPH); 5168 adapter->rx_hwtstamp_cleared++; 5169 } else { 5170 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5171 } 5172 } 5173 5174 /* Reset the timer */ 5175 if (!test_bit(__E1000_DOWN, &adapter->state)) 5176 mod_timer(&adapter->watchdog_timer, 5177 round_jiffies(jiffies + 2 * HZ)); 5178 } 5179 5180 #define E1000_TX_FLAGS_CSUM 0x00000001 5181 #define E1000_TX_FLAGS_VLAN 0x00000002 5182 #define E1000_TX_FLAGS_TSO 0x00000004 5183 #define E1000_TX_FLAGS_IPV4 0x00000008 5184 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5185 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5186 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5187 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5188 5189 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5190 __be16 protocol) 5191 { 5192 struct e1000_context_desc *context_desc; 5193 struct e1000_buffer *buffer_info; 5194 unsigned int i; 5195 u32 cmd_length = 0; 5196 u16 ipcse = 0, mss; 5197 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5198 int err; 5199 5200 if (!skb_is_gso(skb)) 5201 return 0; 5202 5203 err = skb_cow_head(skb, 0); 5204 if (err < 0) 5205 return err; 5206 5207 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5208 mss = skb_shinfo(skb)->gso_size; 5209 if (protocol == htons(ETH_P_IP)) { 5210 struct iphdr *iph = ip_hdr(skb); 5211 iph->tot_len = 0; 5212 iph->check = 0; 5213 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5214 0, IPPROTO_TCP, 0); 5215 cmd_length = E1000_TXD_CMD_IP; 5216 ipcse = skb_transport_offset(skb) - 1; 5217 } else if (skb_is_gso_v6(skb)) { 5218 ipv6_hdr(skb)->payload_len = 0; 5219 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5220 &ipv6_hdr(skb)->daddr, 5221 0, IPPROTO_TCP, 0); 5222 ipcse = 0; 5223 } 5224 ipcss = skb_network_offset(skb); 5225 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5226 tucss = skb_transport_offset(skb); 5227 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5228 5229 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5230 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5231 5232 i = tx_ring->next_to_use; 5233 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5234 buffer_info = &tx_ring->buffer_info[i]; 5235 5236 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5237 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5238 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5239 context_desc->upper_setup.tcp_fields.tucss = tucss; 5240 context_desc->upper_setup.tcp_fields.tucso = tucso; 5241 context_desc->upper_setup.tcp_fields.tucse = 0; 5242 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5243 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5244 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5245 5246 buffer_info->time_stamp = jiffies; 5247 buffer_info->next_to_watch = i; 5248 5249 i++; 5250 if (i == tx_ring->count) 5251 i = 0; 5252 tx_ring->next_to_use = i; 5253 5254 return 1; 5255 } 5256 5257 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5258 __be16 protocol) 5259 { 5260 struct e1000_adapter *adapter = tx_ring->adapter; 5261 struct e1000_context_desc *context_desc; 5262 struct e1000_buffer *buffer_info; 5263 unsigned int i; 5264 u8 css; 5265 u32 cmd_len = E1000_TXD_CMD_DEXT; 5266 5267 if (skb->ip_summed != CHECKSUM_PARTIAL) 5268 return false; 5269 5270 switch (protocol) { 5271 case cpu_to_be16(ETH_P_IP): 5272 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5273 cmd_len |= E1000_TXD_CMD_TCP; 5274 break; 5275 case cpu_to_be16(ETH_P_IPV6): 5276 /* XXX not handling all IPV6 headers */ 5277 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5278 cmd_len |= E1000_TXD_CMD_TCP; 5279 break; 5280 default: 5281 if (unlikely(net_ratelimit())) 5282 e_warn("checksum_partial proto=%x!\n", 5283 be16_to_cpu(protocol)); 5284 break; 5285 } 5286 5287 css = skb_checksum_start_offset(skb); 5288 5289 i = tx_ring->next_to_use; 5290 buffer_info = &tx_ring->buffer_info[i]; 5291 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5292 5293 context_desc->lower_setup.ip_config = 0; 5294 context_desc->upper_setup.tcp_fields.tucss = css; 5295 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5296 context_desc->upper_setup.tcp_fields.tucse = 0; 5297 context_desc->tcp_seg_setup.data = 0; 5298 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5299 5300 buffer_info->time_stamp = jiffies; 5301 buffer_info->next_to_watch = i; 5302 5303 i++; 5304 if (i == tx_ring->count) 5305 i = 0; 5306 tx_ring->next_to_use = i; 5307 5308 return true; 5309 } 5310 5311 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5312 unsigned int first, unsigned int max_per_txd, 5313 unsigned int nr_frags) 5314 { 5315 struct e1000_adapter *adapter = tx_ring->adapter; 5316 struct pci_dev *pdev = adapter->pdev; 5317 struct e1000_buffer *buffer_info; 5318 unsigned int len = skb_headlen(skb); 5319 unsigned int offset = 0, size, count = 0, i; 5320 unsigned int f, bytecount, segs; 5321 5322 i = tx_ring->next_to_use; 5323 5324 while (len) { 5325 buffer_info = &tx_ring->buffer_info[i]; 5326 size = min(len, max_per_txd); 5327 5328 buffer_info->length = size; 5329 buffer_info->time_stamp = jiffies; 5330 buffer_info->next_to_watch = i; 5331 buffer_info->dma = dma_map_single(&pdev->dev, 5332 skb->data + offset, 5333 size, DMA_TO_DEVICE); 5334 buffer_info->mapped_as_page = false; 5335 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5336 goto dma_error; 5337 5338 len -= size; 5339 offset += size; 5340 count++; 5341 5342 if (len) { 5343 i++; 5344 if (i == tx_ring->count) 5345 i = 0; 5346 } 5347 } 5348 5349 for (f = 0; f < nr_frags; f++) { 5350 const struct skb_frag_struct *frag; 5351 5352 frag = &skb_shinfo(skb)->frags[f]; 5353 len = skb_frag_size(frag); 5354 offset = 0; 5355 5356 while (len) { 5357 i++; 5358 if (i == tx_ring->count) 5359 i = 0; 5360 5361 buffer_info = &tx_ring->buffer_info[i]; 5362 size = min(len, max_per_txd); 5363 5364 buffer_info->length = size; 5365 buffer_info->time_stamp = jiffies; 5366 buffer_info->next_to_watch = i; 5367 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5368 offset, size, 5369 DMA_TO_DEVICE); 5370 buffer_info->mapped_as_page = true; 5371 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5372 goto dma_error; 5373 5374 len -= size; 5375 offset += size; 5376 count++; 5377 } 5378 } 5379 5380 segs = skb_shinfo(skb)->gso_segs ? : 1; 5381 /* multiply data chunks by size of headers */ 5382 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5383 5384 tx_ring->buffer_info[i].skb = skb; 5385 tx_ring->buffer_info[i].segs = segs; 5386 tx_ring->buffer_info[i].bytecount = bytecount; 5387 tx_ring->buffer_info[first].next_to_watch = i; 5388 5389 return count; 5390 5391 dma_error: 5392 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5393 buffer_info->dma = 0; 5394 if (count) 5395 count--; 5396 5397 while (count--) { 5398 if (i == 0) 5399 i += tx_ring->count; 5400 i--; 5401 buffer_info = &tx_ring->buffer_info[i]; 5402 e1000_put_txbuf(tx_ring, buffer_info); 5403 } 5404 5405 return 0; 5406 } 5407 5408 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5409 { 5410 struct e1000_adapter *adapter = tx_ring->adapter; 5411 struct e1000_tx_desc *tx_desc = NULL; 5412 struct e1000_buffer *buffer_info; 5413 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5414 unsigned int i; 5415 5416 if (tx_flags & E1000_TX_FLAGS_TSO) { 5417 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5418 E1000_TXD_CMD_TSE; 5419 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5420 5421 if (tx_flags & E1000_TX_FLAGS_IPV4) 5422 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5423 } 5424 5425 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5426 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5427 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5428 } 5429 5430 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5431 txd_lower |= E1000_TXD_CMD_VLE; 5432 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5433 } 5434 5435 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5436 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5437 5438 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5439 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5440 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5441 } 5442 5443 i = tx_ring->next_to_use; 5444 5445 do { 5446 buffer_info = &tx_ring->buffer_info[i]; 5447 tx_desc = E1000_TX_DESC(*tx_ring, i); 5448 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5449 tx_desc->lower.data = cpu_to_le32(txd_lower | 5450 buffer_info->length); 5451 tx_desc->upper.data = cpu_to_le32(txd_upper); 5452 5453 i++; 5454 if (i == tx_ring->count) 5455 i = 0; 5456 } while (--count > 0); 5457 5458 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5459 5460 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5461 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5462 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5463 5464 /* Force memory writes to complete before letting h/w 5465 * know there are new descriptors to fetch. (Only 5466 * applicable for weak-ordered memory model archs, 5467 * such as IA-64). 5468 */ 5469 wmb(); 5470 5471 tx_ring->next_to_use = i; 5472 } 5473 5474 #define MINIMUM_DHCP_PACKET_SIZE 282 5475 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5476 struct sk_buff *skb) 5477 { 5478 struct e1000_hw *hw = &adapter->hw; 5479 u16 length, offset; 5480 5481 if (skb_vlan_tag_present(skb) && 5482 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5483 (adapter->hw.mng_cookie.status & 5484 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5485 return 0; 5486 5487 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5488 return 0; 5489 5490 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5491 return 0; 5492 5493 { 5494 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5495 struct udphdr *udp; 5496 5497 if (ip->protocol != IPPROTO_UDP) 5498 return 0; 5499 5500 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5501 if (ntohs(udp->dest) != 67) 5502 return 0; 5503 5504 offset = (u8 *)udp + 8 - skb->data; 5505 length = skb->len - offset; 5506 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5507 } 5508 5509 return 0; 5510 } 5511 5512 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5513 { 5514 struct e1000_adapter *adapter = tx_ring->adapter; 5515 5516 netif_stop_queue(adapter->netdev); 5517 /* Herbert's original patch had: 5518 * smp_mb__after_netif_stop_queue(); 5519 * but since that doesn't exist yet, just open code it. 5520 */ 5521 smp_mb(); 5522 5523 /* We need to check again in a case another CPU has just 5524 * made room available. 5525 */ 5526 if (e1000_desc_unused(tx_ring) < size) 5527 return -EBUSY; 5528 5529 /* A reprieve! */ 5530 netif_start_queue(adapter->netdev); 5531 ++adapter->restart_queue; 5532 return 0; 5533 } 5534 5535 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5536 { 5537 BUG_ON(size > tx_ring->count); 5538 5539 if (e1000_desc_unused(tx_ring) >= size) 5540 return 0; 5541 return __e1000_maybe_stop_tx(tx_ring, size); 5542 } 5543 5544 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5545 struct net_device *netdev) 5546 { 5547 struct e1000_adapter *adapter = netdev_priv(netdev); 5548 struct e1000_ring *tx_ring = adapter->tx_ring; 5549 unsigned int first; 5550 unsigned int tx_flags = 0; 5551 unsigned int len = skb_headlen(skb); 5552 unsigned int nr_frags; 5553 unsigned int mss; 5554 int count = 0; 5555 int tso; 5556 unsigned int f; 5557 __be16 protocol = vlan_get_protocol(skb); 5558 5559 if (test_bit(__E1000_DOWN, &adapter->state)) { 5560 dev_kfree_skb_any(skb); 5561 return NETDEV_TX_OK; 5562 } 5563 5564 if (skb->len <= 0) { 5565 dev_kfree_skb_any(skb); 5566 return NETDEV_TX_OK; 5567 } 5568 5569 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5570 * pad skb in order to meet this minimum size requirement 5571 */ 5572 if (skb_put_padto(skb, 17)) 5573 return NETDEV_TX_OK; 5574 5575 mss = skb_shinfo(skb)->gso_size; 5576 if (mss) { 5577 u8 hdr_len; 5578 5579 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5580 * points to just header, pull a few bytes of payload from 5581 * frags into skb->data 5582 */ 5583 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5584 /* we do this workaround for ES2LAN, but it is un-necessary, 5585 * avoiding it could save a lot of cycles 5586 */ 5587 if (skb->data_len && (hdr_len == len)) { 5588 unsigned int pull_size; 5589 5590 pull_size = min_t(unsigned int, 4, skb->data_len); 5591 if (!__pskb_pull_tail(skb, pull_size)) { 5592 e_err("__pskb_pull_tail failed.\n"); 5593 dev_kfree_skb_any(skb); 5594 return NETDEV_TX_OK; 5595 } 5596 len = skb_headlen(skb); 5597 } 5598 } 5599 5600 /* reserve a descriptor for the offload context */ 5601 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5602 count++; 5603 count++; 5604 5605 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5606 5607 nr_frags = skb_shinfo(skb)->nr_frags; 5608 for (f = 0; f < nr_frags; f++) 5609 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5610 adapter->tx_fifo_limit); 5611 5612 if (adapter->hw.mac.tx_pkt_filtering) 5613 e1000_transfer_dhcp_info(adapter, skb); 5614 5615 /* need: count + 2 desc gap to keep tail from touching 5616 * head, otherwise try next time 5617 */ 5618 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5619 return NETDEV_TX_BUSY; 5620 5621 if (skb_vlan_tag_present(skb)) { 5622 tx_flags |= E1000_TX_FLAGS_VLAN; 5623 tx_flags |= (skb_vlan_tag_get(skb) << 5624 E1000_TX_FLAGS_VLAN_SHIFT); 5625 } 5626 5627 first = tx_ring->next_to_use; 5628 5629 tso = e1000_tso(tx_ring, skb, protocol); 5630 if (tso < 0) { 5631 dev_kfree_skb_any(skb); 5632 return NETDEV_TX_OK; 5633 } 5634 5635 if (tso) 5636 tx_flags |= E1000_TX_FLAGS_TSO; 5637 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5638 tx_flags |= E1000_TX_FLAGS_CSUM; 5639 5640 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5641 * 82571 hardware supports TSO capabilities for IPv6 as well... 5642 * no longer assume, we must. 5643 */ 5644 if (protocol == htons(ETH_P_IP)) 5645 tx_flags |= E1000_TX_FLAGS_IPV4; 5646 5647 if (unlikely(skb->no_fcs)) 5648 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5649 5650 /* if count is 0 then mapping error has occurred */ 5651 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5652 nr_frags); 5653 if (count) { 5654 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5655 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) && 5656 !adapter->tx_hwtstamp_skb) { 5657 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5658 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5659 adapter->tx_hwtstamp_skb = skb_get(skb); 5660 adapter->tx_hwtstamp_start = jiffies; 5661 schedule_work(&adapter->tx_hwtstamp_work); 5662 } else { 5663 skb_tx_timestamp(skb); 5664 } 5665 5666 netdev_sent_queue(netdev, skb->len); 5667 e1000_tx_queue(tx_ring, tx_flags, count); 5668 /* Make sure there is space in the ring for the next send. */ 5669 e1000_maybe_stop_tx(tx_ring, 5670 (MAX_SKB_FRAGS * 5671 DIV_ROUND_UP(PAGE_SIZE, 5672 adapter->tx_fifo_limit) + 2)); 5673 5674 if (!skb->xmit_more || 5675 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5676 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5677 e1000e_update_tdt_wa(tx_ring, 5678 tx_ring->next_to_use); 5679 else 5680 writel(tx_ring->next_to_use, tx_ring->tail); 5681 5682 /* we need this if more than one processor can write 5683 * to our tail at a time, it synchronizes IO on 5684 *IA64/Altix systems 5685 */ 5686 mmiowb(); 5687 } 5688 } else { 5689 dev_kfree_skb_any(skb); 5690 tx_ring->buffer_info[first].time_stamp = 0; 5691 tx_ring->next_to_use = first; 5692 } 5693 5694 return NETDEV_TX_OK; 5695 } 5696 5697 /** 5698 * e1000_tx_timeout - Respond to a Tx Hang 5699 * @netdev: network interface device structure 5700 **/ 5701 static void e1000_tx_timeout(struct net_device *netdev) 5702 { 5703 struct e1000_adapter *adapter = netdev_priv(netdev); 5704 5705 /* Do the reset outside of interrupt context */ 5706 adapter->tx_timeout_count++; 5707 schedule_work(&adapter->reset_task); 5708 } 5709 5710 static void e1000_reset_task(struct work_struct *work) 5711 { 5712 struct e1000_adapter *adapter; 5713 adapter = container_of(work, struct e1000_adapter, reset_task); 5714 5715 /* don't run the task if already down */ 5716 if (test_bit(__E1000_DOWN, &adapter->state)) 5717 return; 5718 5719 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5720 e1000e_dump(adapter); 5721 e_err("Reset adapter unexpectedly\n"); 5722 } 5723 e1000e_reinit_locked(adapter); 5724 } 5725 5726 /** 5727 * e1000_get_stats64 - Get System Network Statistics 5728 * @netdev: network interface device structure 5729 * @stats: rtnl_link_stats64 pointer 5730 * 5731 * Returns the address of the device statistics structure. 5732 **/ 5733 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 5734 struct rtnl_link_stats64 *stats) 5735 { 5736 struct e1000_adapter *adapter = netdev_priv(netdev); 5737 5738 memset(stats, 0, sizeof(struct rtnl_link_stats64)); 5739 spin_lock(&adapter->stats64_lock); 5740 e1000e_update_stats(adapter); 5741 /* Fill out the OS statistics structure */ 5742 stats->rx_bytes = adapter->stats.gorc; 5743 stats->rx_packets = adapter->stats.gprc; 5744 stats->tx_bytes = adapter->stats.gotc; 5745 stats->tx_packets = adapter->stats.gptc; 5746 stats->multicast = adapter->stats.mprc; 5747 stats->collisions = adapter->stats.colc; 5748 5749 /* Rx Errors */ 5750 5751 /* RLEC on some newer hardware can be incorrect so build 5752 * our own version based on RUC and ROC 5753 */ 5754 stats->rx_errors = adapter->stats.rxerrc + 5755 adapter->stats.crcerrs + adapter->stats.algnerrc + 5756 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5757 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5758 stats->rx_crc_errors = adapter->stats.crcerrs; 5759 stats->rx_frame_errors = adapter->stats.algnerrc; 5760 stats->rx_missed_errors = adapter->stats.mpc; 5761 5762 /* Tx Errors */ 5763 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5764 stats->tx_aborted_errors = adapter->stats.ecol; 5765 stats->tx_window_errors = adapter->stats.latecol; 5766 stats->tx_carrier_errors = adapter->stats.tncrs; 5767 5768 /* Tx Dropped needs to be maintained elsewhere */ 5769 5770 spin_unlock(&adapter->stats64_lock); 5771 return stats; 5772 } 5773 5774 /** 5775 * e1000_change_mtu - Change the Maximum Transfer Unit 5776 * @netdev: network interface device structure 5777 * @new_mtu: new value for maximum frame size 5778 * 5779 * Returns 0 on success, negative on failure 5780 **/ 5781 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 5782 { 5783 struct e1000_adapter *adapter = netdev_priv(netdev); 5784 int max_frame = new_mtu + VLAN_HLEN + ETH_HLEN + ETH_FCS_LEN; 5785 5786 /* Jumbo frame support */ 5787 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) && 5788 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 5789 e_err("Jumbo Frames not supported.\n"); 5790 return -EINVAL; 5791 } 5792 5793 /* Supported frame sizes */ 5794 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || 5795 (max_frame > adapter->max_hw_frame_size)) { 5796 e_err("Unsupported MTU setting\n"); 5797 return -EINVAL; 5798 } 5799 5800 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 5801 if ((adapter->hw.mac.type >= e1000_pch2lan) && 5802 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 5803 (new_mtu > ETH_DATA_LEN)) { 5804 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 5805 return -EINVAL; 5806 } 5807 5808 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 5809 usleep_range(1000, 2000); 5810 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 5811 adapter->max_frame_size = max_frame; 5812 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5813 netdev->mtu = new_mtu; 5814 5815 pm_runtime_get_sync(netdev->dev.parent); 5816 5817 if (netif_running(netdev)) 5818 e1000e_down(adapter, true); 5819 5820 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 5821 * means we reserve 2 more, this pushes us to allocate from the next 5822 * larger slab size. 5823 * i.e. RXBUFFER_2048 --> size-4096 slab 5824 * However with the new *_jumbo_rx* routines, jumbo receives will use 5825 * fragmented skbs 5826 */ 5827 5828 if (max_frame <= 2048) 5829 adapter->rx_buffer_len = 2048; 5830 else 5831 adapter->rx_buffer_len = 4096; 5832 5833 /* adjust allocation if LPE protects us, and we aren't using SBP */ 5834 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) || 5835 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)) 5836 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN 5837 + ETH_FCS_LEN; 5838 5839 if (netif_running(netdev)) 5840 e1000e_up(adapter); 5841 else 5842 e1000e_reset(adapter); 5843 5844 pm_runtime_put_sync(netdev->dev.parent); 5845 5846 clear_bit(__E1000_RESETTING, &adapter->state); 5847 5848 return 0; 5849 } 5850 5851 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 5852 int cmd) 5853 { 5854 struct e1000_adapter *adapter = netdev_priv(netdev); 5855 struct mii_ioctl_data *data = if_mii(ifr); 5856 5857 if (adapter->hw.phy.media_type != e1000_media_type_copper) 5858 return -EOPNOTSUPP; 5859 5860 switch (cmd) { 5861 case SIOCGMIIPHY: 5862 data->phy_id = adapter->hw.phy.addr; 5863 break; 5864 case SIOCGMIIREG: 5865 e1000_phy_read_status(adapter); 5866 5867 switch (data->reg_num & 0x1F) { 5868 case MII_BMCR: 5869 data->val_out = adapter->phy_regs.bmcr; 5870 break; 5871 case MII_BMSR: 5872 data->val_out = adapter->phy_regs.bmsr; 5873 break; 5874 case MII_PHYSID1: 5875 data->val_out = (adapter->hw.phy.id >> 16); 5876 break; 5877 case MII_PHYSID2: 5878 data->val_out = (adapter->hw.phy.id & 0xFFFF); 5879 break; 5880 case MII_ADVERTISE: 5881 data->val_out = adapter->phy_regs.advertise; 5882 break; 5883 case MII_LPA: 5884 data->val_out = adapter->phy_regs.lpa; 5885 break; 5886 case MII_EXPANSION: 5887 data->val_out = adapter->phy_regs.expansion; 5888 break; 5889 case MII_CTRL1000: 5890 data->val_out = adapter->phy_regs.ctrl1000; 5891 break; 5892 case MII_STAT1000: 5893 data->val_out = adapter->phy_regs.stat1000; 5894 break; 5895 case MII_ESTATUS: 5896 data->val_out = adapter->phy_regs.estatus; 5897 break; 5898 default: 5899 return -EIO; 5900 } 5901 break; 5902 case SIOCSMIIREG: 5903 default: 5904 return -EOPNOTSUPP; 5905 } 5906 return 0; 5907 } 5908 5909 /** 5910 * e1000e_hwtstamp_ioctl - control hardware time stamping 5911 * @netdev: network interface device structure 5912 * @ifreq: interface request 5913 * 5914 * Outgoing time stamping can be enabled and disabled. Play nice and 5915 * disable it when requested, although it shouldn't cause any overhead 5916 * when no packet needs it. At most one packet in the queue may be 5917 * marked for time stamping, otherwise it would be impossible to tell 5918 * for sure to which packet the hardware time stamp belongs. 5919 * 5920 * Incoming time stamping has to be configured via the hardware filters. 5921 * Not all combinations are supported, in particular event type has to be 5922 * specified. Matching the kind of event packet is not supported, with the 5923 * exception of "all V2 events regardless of level 2 or 4". 5924 **/ 5925 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 5926 { 5927 struct e1000_adapter *adapter = netdev_priv(netdev); 5928 struct hwtstamp_config config; 5929 int ret_val; 5930 5931 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5932 return -EFAULT; 5933 5934 ret_val = e1000e_config_hwtstamp(adapter, &config); 5935 if (ret_val) 5936 return ret_val; 5937 5938 switch (config.rx_filter) { 5939 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 5940 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 5941 case HWTSTAMP_FILTER_PTP_V2_SYNC: 5942 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 5943 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 5944 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 5945 /* With V2 type filters which specify a Sync or Delay Request, 5946 * Path Delay Request/Response messages are also time stamped 5947 * by hardware so notify the caller the requested packets plus 5948 * some others are time stamped. 5949 */ 5950 config.rx_filter = HWTSTAMP_FILTER_SOME; 5951 break; 5952 default: 5953 break; 5954 } 5955 5956 return copy_to_user(ifr->ifr_data, &config, 5957 sizeof(config)) ? -EFAULT : 0; 5958 } 5959 5960 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 5961 { 5962 struct e1000_adapter *adapter = netdev_priv(netdev); 5963 5964 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 5965 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 5966 } 5967 5968 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 5969 { 5970 switch (cmd) { 5971 case SIOCGMIIPHY: 5972 case SIOCGMIIREG: 5973 case SIOCSMIIREG: 5974 return e1000_mii_ioctl(netdev, ifr, cmd); 5975 case SIOCSHWTSTAMP: 5976 return e1000e_hwtstamp_set(netdev, ifr); 5977 case SIOCGHWTSTAMP: 5978 return e1000e_hwtstamp_get(netdev, ifr); 5979 default: 5980 return -EOPNOTSUPP; 5981 } 5982 } 5983 5984 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 5985 { 5986 struct e1000_hw *hw = &adapter->hw; 5987 u32 i, mac_reg, wuc; 5988 u16 phy_reg, wuc_enable; 5989 int retval; 5990 5991 /* copy MAC RARs to PHY RARs */ 5992 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 5993 5994 retval = hw->phy.ops.acquire(hw); 5995 if (retval) { 5996 e_err("Could not acquire PHY\n"); 5997 return retval; 5998 } 5999 6000 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6001 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6002 if (retval) 6003 goto release; 6004 6005 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6006 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6007 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6008 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6009 (u16)(mac_reg & 0xFFFF)); 6010 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6011 (u16)((mac_reg >> 16) & 0xFFFF)); 6012 } 6013 6014 /* configure PHY Rx Control register */ 6015 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6016 mac_reg = er32(RCTL); 6017 if (mac_reg & E1000_RCTL_UPE) 6018 phy_reg |= BM_RCTL_UPE; 6019 if (mac_reg & E1000_RCTL_MPE) 6020 phy_reg |= BM_RCTL_MPE; 6021 phy_reg &= ~(BM_RCTL_MO_MASK); 6022 if (mac_reg & E1000_RCTL_MO_3) 6023 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6024 << BM_RCTL_MO_SHIFT); 6025 if (mac_reg & E1000_RCTL_BAM) 6026 phy_reg |= BM_RCTL_BAM; 6027 if (mac_reg & E1000_RCTL_PMCF) 6028 phy_reg |= BM_RCTL_PMCF; 6029 mac_reg = er32(CTRL); 6030 if (mac_reg & E1000_CTRL_RFCE) 6031 phy_reg |= BM_RCTL_RFCE; 6032 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6033 6034 wuc = E1000_WUC_PME_EN; 6035 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6036 wuc |= E1000_WUC_APME; 6037 6038 /* enable PHY wakeup in MAC register */ 6039 ew32(WUFC, wufc); 6040 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6041 E1000_WUC_PME_STATUS | wuc)); 6042 6043 /* configure and enable PHY wakeup in PHY registers */ 6044 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6045 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6046 6047 /* activate PHY wakeup */ 6048 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6049 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6050 if (retval) 6051 e_err("Could not set PHY Host Wakeup bit\n"); 6052 release: 6053 hw->phy.ops.release(hw); 6054 6055 return retval; 6056 } 6057 6058 static void e1000e_flush_lpic(struct pci_dev *pdev) 6059 { 6060 struct net_device *netdev = pci_get_drvdata(pdev); 6061 struct e1000_adapter *adapter = netdev_priv(netdev); 6062 struct e1000_hw *hw = &adapter->hw; 6063 u32 ret_val; 6064 6065 pm_runtime_get_sync(netdev->dev.parent); 6066 6067 ret_val = hw->phy.ops.acquire(hw); 6068 if (ret_val) 6069 goto fl_out; 6070 6071 pr_info("EEE TX LPI TIMER: %08X\n", 6072 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6073 6074 hw->phy.ops.release(hw); 6075 6076 fl_out: 6077 pm_runtime_put_sync(netdev->dev.parent); 6078 } 6079 6080 static int e1000e_pm_freeze(struct device *dev) 6081 { 6082 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6083 struct e1000_adapter *adapter = netdev_priv(netdev); 6084 6085 netif_device_detach(netdev); 6086 6087 if (netif_running(netdev)) { 6088 int count = E1000_CHECK_RESET_COUNT; 6089 6090 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6091 usleep_range(10000, 20000); 6092 6093 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6094 6095 /* Quiesce the device without resetting the hardware */ 6096 e1000e_down(adapter, false); 6097 e1000_free_irq(adapter); 6098 } 6099 e1000e_reset_interrupt_capability(adapter); 6100 6101 /* Allow time for pending master requests to run */ 6102 e1000e_disable_pcie_master(&adapter->hw); 6103 6104 return 0; 6105 } 6106 6107 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6108 { 6109 struct net_device *netdev = pci_get_drvdata(pdev); 6110 struct e1000_adapter *adapter = netdev_priv(netdev); 6111 struct e1000_hw *hw = &adapter->hw; 6112 u32 ctrl, ctrl_ext, rctl, status; 6113 /* Runtime suspend should only enable wakeup for link changes */ 6114 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6115 int retval = 0; 6116 6117 status = er32(STATUS); 6118 if (status & E1000_STATUS_LU) 6119 wufc &= ~E1000_WUFC_LNKC; 6120 6121 if (wufc) { 6122 e1000_setup_rctl(adapter); 6123 e1000e_set_rx_mode(netdev); 6124 6125 /* turn on all-multi mode if wake on multicast is enabled */ 6126 if (wufc & E1000_WUFC_MC) { 6127 rctl = er32(RCTL); 6128 rctl |= E1000_RCTL_MPE; 6129 ew32(RCTL, rctl); 6130 } 6131 6132 ctrl = er32(CTRL); 6133 ctrl |= E1000_CTRL_ADVD3WUC; 6134 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6135 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6136 ew32(CTRL, ctrl); 6137 6138 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6139 adapter->hw.phy.media_type == 6140 e1000_media_type_internal_serdes) { 6141 /* keep the laser running in D3 */ 6142 ctrl_ext = er32(CTRL_EXT); 6143 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6144 ew32(CTRL_EXT, ctrl_ext); 6145 } 6146 6147 if (!runtime) 6148 e1000e_power_up_phy(adapter); 6149 6150 if (adapter->flags & FLAG_IS_ICH) 6151 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6152 6153 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6154 /* enable wakeup by the PHY */ 6155 retval = e1000_init_phy_wakeup(adapter, wufc); 6156 if (retval) 6157 return retval; 6158 } else { 6159 /* enable wakeup by the MAC */ 6160 ew32(WUFC, wufc); 6161 ew32(WUC, E1000_WUC_PME_EN); 6162 } 6163 } else { 6164 ew32(WUC, 0); 6165 ew32(WUFC, 0); 6166 6167 e1000_power_down_phy(adapter); 6168 } 6169 6170 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6171 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6172 } else if ((hw->mac.type == e1000_pch_lpt) || 6173 (hw->mac.type == e1000_pch_spt)) { 6174 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6175 /* ULP does not support wake from unicast, multicast 6176 * or broadcast. 6177 */ 6178 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6179 6180 if (retval) 6181 return retval; 6182 } 6183 6184 6185 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6186 * would have already happened in close and is redundant. 6187 */ 6188 e1000e_release_hw_control(adapter); 6189 6190 pci_clear_master(pdev); 6191 6192 /* The pci-e switch on some quad port adapters will report a 6193 * correctable error when the MAC transitions from D0 to D3. To 6194 * prevent this we need to mask off the correctable errors on the 6195 * downstream port of the pci-e switch. 6196 * 6197 * We don't have the associated upstream bridge while assigning 6198 * the PCI device into guest. For example, the KVM on power is 6199 * one of the cases. 6200 */ 6201 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6202 struct pci_dev *us_dev = pdev->bus->self; 6203 u16 devctl; 6204 6205 if (!us_dev) 6206 return 0; 6207 6208 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6209 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6210 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6211 6212 pci_save_state(pdev); 6213 pci_prepare_to_sleep(pdev); 6214 6215 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6216 } 6217 6218 return 0; 6219 } 6220 6221 /** 6222 * e1000e_disable_aspm - Disable ASPM states 6223 * @pdev: pointer to PCI device struct 6224 * @state: bit-mask of ASPM states to disable 6225 * 6226 * Some devices *must* have certain ASPM states disabled per hardware errata. 6227 **/ 6228 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6229 { 6230 struct pci_dev *parent = pdev->bus->self; 6231 u16 aspm_dis_mask = 0; 6232 u16 pdev_aspmc, parent_aspmc; 6233 6234 switch (state) { 6235 case PCIE_LINK_STATE_L0S: 6236 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6237 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6238 /* fall-through - can't have L1 without L0s */ 6239 case PCIE_LINK_STATE_L1: 6240 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6241 break; 6242 default: 6243 return; 6244 } 6245 6246 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6247 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6248 6249 if (parent) { 6250 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6251 &parent_aspmc); 6252 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6253 } 6254 6255 /* Nothing to do if the ASPM states to be disabled already are */ 6256 if (!(pdev_aspmc & aspm_dis_mask) && 6257 (!parent || !(parent_aspmc & aspm_dis_mask))) 6258 return; 6259 6260 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6261 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6262 "L0s" : "", 6263 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6264 "L1" : ""); 6265 6266 #ifdef CONFIG_PCIEASPM 6267 pci_disable_link_state_locked(pdev, state); 6268 6269 /* Double-check ASPM control. If not disabled by the above, the 6270 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6271 * not enabled); override by writing PCI config space directly. 6272 */ 6273 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6274 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6275 6276 if (!(aspm_dis_mask & pdev_aspmc)) 6277 return; 6278 #endif 6279 6280 /* Both device and parent should have the same ASPM setting. 6281 * Disable ASPM in downstream component first and then upstream. 6282 */ 6283 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6284 6285 if (parent) 6286 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6287 aspm_dis_mask); 6288 } 6289 6290 #ifdef CONFIG_PM 6291 static int __e1000_resume(struct pci_dev *pdev) 6292 { 6293 struct net_device *netdev = pci_get_drvdata(pdev); 6294 struct e1000_adapter *adapter = netdev_priv(netdev); 6295 struct e1000_hw *hw = &adapter->hw; 6296 u16 aspm_disable_flag = 0; 6297 6298 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6299 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6300 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6301 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6302 if (aspm_disable_flag) 6303 e1000e_disable_aspm(pdev, aspm_disable_flag); 6304 6305 pci_set_master(pdev); 6306 6307 if (hw->mac.type >= e1000_pch2lan) 6308 e1000_resume_workarounds_pchlan(&adapter->hw); 6309 6310 e1000e_power_up_phy(adapter); 6311 6312 /* report the system wakeup cause from S3/S4 */ 6313 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6314 u16 phy_data; 6315 6316 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6317 if (phy_data) { 6318 e_info("PHY Wakeup cause - %s\n", 6319 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6320 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6321 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6322 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6323 phy_data & E1000_WUS_LNKC ? 6324 "Link Status Change" : "other"); 6325 } 6326 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6327 } else { 6328 u32 wus = er32(WUS); 6329 6330 if (wus) { 6331 e_info("MAC Wakeup cause - %s\n", 6332 wus & E1000_WUS_EX ? "Unicast Packet" : 6333 wus & E1000_WUS_MC ? "Multicast Packet" : 6334 wus & E1000_WUS_BC ? "Broadcast Packet" : 6335 wus & E1000_WUS_MAG ? "Magic Packet" : 6336 wus & E1000_WUS_LNKC ? "Link Status Change" : 6337 "other"); 6338 } 6339 ew32(WUS, ~0); 6340 } 6341 6342 e1000e_reset(adapter); 6343 6344 e1000_init_manageability_pt(adapter); 6345 6346 /* If the controller has AMT, do not set DRV_LOAD until the interface 6347 * is up. For all other cases, let the f/w know that the h/w is now 6348 * under the control of the driver. 6349 */ 6350 if (!(adapter->flags & FLAG_HAS_AMT)) 6351 e1000e_get_hw_control(adapter); 6352 6353 return 0; 6354 } 6355 6356 #ifdef CONFIG_PM_SLEEP 6357 static int e1000e_pm_thaw(struct device *dev) 6358 { 6359 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6360 struct e1000_adapter *adapter = netdev_priv(netdev); 6361 6362 e1000e_set_interrupt_capability(adapter); 6363 if (netif_running(netdev)) { 6364 u32 err = e1000_request_irq(adapter); 6365 6366 if (err) 6367 return err; 6368 6369 e1000e_up(adapter); 6370 } 6371 6372 netif_device_attach(netdev); 6373 6374 return 0; 6375 } 6376 6377 static int e1000e_pm_suspend(struct device *dev) 6378 { 6379 struct pci_dev *pdev = to_pci_dev(dev); 6380 6381 e1000e_flush_lpic(pdev); 6382 6383 e1000e_pm_freeze(dev); 6384 6385 return __e1000_shutdown(pdev, false); 6386 } 6387 6388 static int e1000e_pm_resume(struct device *dev) 6389 { 6390 struct pci_dev *pdev = to_pci_dev(dev); 6391 int rc; 6392 6393 rc = __e1000_resume(pdev); 6394 if (rc) 6395 return rc; 6396 6397 return e1000e_pm_thaw(dev); 6398 } 6399 #endif /* CONFIG_PM_SLEEP */ 6400 6401 static int e1000e_pm_runtime_idle(struct device *dev) 6402 { 6403 struct pci_dev *pdev = to_pci_dev(dev); 6404 struct net_device *netdev = pci_get_drvdata(pdev); 6405 struct e1000_adapter *adapter = netdev_priv(netdev); 6406 u16 eee_lp; 6407 6408 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6409 6410 if (!e1000e_has_link(adapter)) { 6411 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6412 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6413 } 6414 6415 return -EBUSY; 6416 } 6417 6418 static int e1000e_pm_runtime_resume(struct device *dev) 6419 { 6420 struct pci_dev *pdev = to_pci_dev(dev); 6421 struct net_device *netdev = pci_get_drvdata(pdev); 6422 struct e1000_adapter *adapter = netdev_priv(netdev); 6423 int rc; 6424 6425 rc = __e1000_resume(pdev); 6426 if (rc) 6427 return rc; 6428 6429 if (netdev->flags & IFF_UP) 6430 rc = e1000e_up(adapter); 6431 6432 return rc; 6433 } 6434 6435 static int e1000e_pm_runtime_suspend(struct device *dev) 6436 { 6437 struct pci_dev *pdev = to_pci_dev(dev); 6438 struct net_device *netdev = pci_get_drvdata(pdev); 6439 struct e1000_adapter *adapter = netdev_priv(netdev); 6440 6441 if (netdev->flags & IFF_UP) { 6442 int count = E1000_CHECK_RESET_COUNT; 6443 6444 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6445 usleep_range(10000, 20000); 6446 6447 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6448 6449 /* Down the device without resetting the hardware */ 6450 e1000e_down(adapter, false); 6451 } 6452 6453 if (__e1000_shutdown(pdev, true)) { 6454 e1000e_pm_runtime_resume(dev); 6455 return -EBUSY; 6456 } 6457 6458 return 0; 6459 } 6460 #endif /* CONFIG_PM */ 6461 6462 static void e1000_shutdown(struct pci_dev *pdev) 6463 { 6464 e1000e_flush_lpic(pdev); 6465 6466 e1000e_pm_freeze(&pdev->dev); 6467 6468 __e1000_shutdown(pdev, false); 6469 } 6470 6471 #ifdef CONFIG_NET_POLL_CONTROLLER 6472 6473 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6474 { 6475 struct net_device *netdev = data; 6476 struct e1000_adapter *adapter = netdev_priv(netdev); 6477 6478 if (adapter->msix_entries) { 6479 int vector, msix_irq; 6480 6481 vector = 0; 6482 msix_irq = adapter->msix_entries[vector].vector; 6483 disable_irq(msix_irq); 6484 e1000_intr_msix_rx(msix_irq, netdev); 6485 enable_irq(msix_irq); 6486 6487 vector++; 6488 msix_irq = adapter->msix_entries[vector].vector; 6489 disable_irq(msix_irq); 6490 e1000_intr_msix_tx(msix_irq, netdev); 6491 enable_irq(msix_irq); 6492 6493 vector++; 6494 msix_irq = adapter->msix_entries[vector].vector; 6495 disable_irq(msix_irq); 6496 e1000_msix_other(msix_irq, netdev); 6497 enable_irq(msix_irq); 6498 } 6499 6500 return IRQ_HANDLED; 6501 } 6502 6503 /** 6504 * e1000_netpoll 6505 * @netdev: network interface device structure 6506 * 6507 * Polling 'interrupt' - used by things like netconsole to send skbs 6508 * without having to re-enable interrupts. It's not called while 6509 * the interrupt routine is executing. 6510 */ 6511 static void e1000_netpoll(struct net_device *netdev) 6512 { 6513 struct e1000_adapter *adapter = netdev_priv(netdev); 6514 6515 switch (adapter->int_mode) { 6516 case E1000E_INT_MODE_MSIX: 6517 e1000_intr_msix(adapter->pdev->irq, netdev); 6518 break; 6519 case E1000E_INT_MODE_MSI: 6520 disable_irq(adapter->pdev->irq); 6521 e1000_intr_msi(adapter->pdev->irq, netdev); 6522 enable_irq(adapter->pdev->irq); 6523 break; 6524 default: /* E1000E_INT_MODE_LEGACY */ 6525 disable_irq(adapter->pdev->irq); 6526 e1000_intr(adapter->pdev->irq, netdev); 6527 enable_irq(adapter->pdev->irq); 6528 break; 6529 } 6530 } 6531 #endif 6532 6533 /** 6534 * e1000_io_error_detected - called when PCI error is detected 6535 * @pdev: Pointer to PCI device 6536 * @state: The current pci connection state 6537 * 6538 * This function is called after a PCI bus error affecting 6539 * this device has been detected. 6540 */ 6541 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6542 pci_channel_state_t state) 6543 { 6544 struct net_device *netdev = pci_get_drvdata(pdev); 6545 struct e1000_adapter *adapter = netdev_priv(netdev); 6546 6547 netif_device_detach(netdev); 6548 6549 if (state == pci_channel_io_perm_failure) 6550 return PCI_ERS_RESULT_DISCONNECT; 6551 6552 if (netif_running(netdev)) 6553 e1000e_down(adapter, true); 6554 pci_disable_device(pdev); 6555 6556 /* Request a slot slot reset. */ 6557 return PCI_ERS_RESULT_NEED_RESET; 6558 } 6559 6560 /** 6561 * e1000_io_slot_reset - called after the pci bus has been reset. 6562 * @pdev: Pointer to PCI device 6563 * 6564 * Restart the card from scratch, as if from a cold-boot. Implementation 6565 * resembles the first-half of the e1000e_pm_resume routine. 6566 */ 6567 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6568 { 6569 struct net_device *netdev = pci_get_drvdata(pdev); 6570 struct e1000_adapter *adapter = netdev_priv(netdev); 6571 struct e1000_hw *hw = &adapter->hw; 6572 u16 aspm_disable_flag = 0; 6573 int err; 6574 pci_ers_result_t result; 6575 6576 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6577 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6578 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6579 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6580 if (aspm_disable_flag) 6581 e1000e_disable_aspm(pdev, aspm_disable_flag); 6582 6583 err = pci_enable_device_mem(pdev); 6584 if (err) { 6585 dev_err(&pdev->dev, 6586 "Cannot re-enable PCI device after reset.\n"); 6587 result = PCI_ERS_RESULT_DISCONNECT; 6588 } else { 6589 pdev->state_saved = true; 6590 pci_restore_state(pdev); 6591 pci_set_master(pdev); 6592 6593 pci_enable_wake(pdev, PCI_D3hot, 0); 6594 pci_enable_wake(pdev, PCI_D3cold, 0); 6595 6596 e1000e_reset(adapter); 6597 ew32(WUS, ~0); 6598 result = PCI_ERS_RESULT_RECOVERED; 6599 } 6600 6601 pci_cleanup_aer_uncorrect_error_status(pdev); 6602 6603 return result; 6604 } 6605 6606 /** 6607 * e1000_io_resume - called when traffic can start flowing again. 6608 * @pdev: Pointer to PCI device 6609 * 6610 * This callback is called when the error recovery driver tells us that 6611 * its OK to resume normal operation. Implementation resembles the 6612 * second-half of the e1000e_pm_resume routine. 6613 */ 6614 static void e1000_io_resume(struct pci_dev *pdev) 6615 { 6616 struct net_device *netdev = pci_get_drvdata(pdev); 6617 struct e1000_adapter *adapter = netdev_priv(netdev); 6618 6619 e1000_init_manageability_pt(adapter); 6620 6621 if (netif_running(netdev)) { 6622 if (e1000e_up(adapter)) { 6623 dev_err(&pdev->dev, 6624 "can't bring device back up after reset\n"); 6625 return; 6626 } 6627 } 6628 6629 netif_device_attach(netdev); 6630 6631 /* If the controller has AMT, do not set DRV_LOAD until the interface 6632 * is up. For all other cases, let the f/w know that the h/w is now 6633 * under the control of the driver. 6634 */ 6635 if (!(adapter->flags & FLAG_HAS_AMT)) 6636 e1000e_get_hw_control(adapter); 6637 } 6638 6639 static void e1000_print_device_info(struct e1000_adapter *adapter) 6640 { 6641 struct e1000_hw *hw = &adapter->hw; 6642 struct net_device *netdev = adapter->netdev; 6643 u32 ret_val; 6644 u8 pba_str[E1000_PBANUM_LENGTH]; 6645 6646 /* print bus type/speed/width info */ 6647 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6648 /* bus width */ 6649 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6650 "Width x1"), 6651 /* MAC address */ 6652 netdev->dev_addr); 6653 e_info("Intel(R) PRO/%s Network Connection\n", 6654 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6655 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6656 E1000_PBANUM_LENGTH); 6657 if (ret_val) 6658 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6659 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6660 hw->mac.type, hw->phy.type, pba_str); 6661 } 6662 6663 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6664 { 6665 struct e1000_hw *hw = &adapter->hw; 6666 int ret_val; 6667 u16 buf = 0; 6668 6669 if (hw->mac.type != e1000_82573) 6670 return; 6671 6672 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6673 le16_to_cpus(&buf); 6674 if (!ret_val && (!(buf & (1 << 0)))) { 6675 /* Deep Smart Power Down (DSPD) */ 6676 dev_warn(&adapter->pdev->dev, 6677 "Warning: detected DSPD enabled in EEPROM\n"); 6678 } 6679 } 6680 6681 static int e1000_set_features(struct net_device *netdev, 6682 netdev_features_t features) 6683 { 6684 struct e1000_adapter *adapter = netdev_priv(netdev); 6685 netdev_features_t changed = features ^ netdev->features; 6686 6687 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6688 adapter->flags |= FLAG_TSO_FORCE; 6689 6690 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6691 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6692 NETIF_F_RXALL))) 6693 return 0; 6694 6695 if (changed & NETIF_F_RXFCS) { 6696 if (features & NETIF_F_RXFCS) { 6697 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6698 } else { 6699 /* We need to take it back to defaults, which might mean 6700 * stripping is still disabled at the adapter level. 6701 */ 6702 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 6703 adapter->flags2 |= FLAG2_CRC_STRIPPING; 6704 else 6705 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6706 } 6707 } 6708 6709 netdev->features = features; 6710 6711 if (netif_running(netdev)) 6712 e1000e_reinit_locked(adapter); 6713 else 6714 e1000e_reset(adapter); 6715 6716 return 0; 6717 } 6718 6719 static const struct net_device_ops e1000e_netdev_ops = { 6720 .ndo_open = e1000_open, 6721 .ndo_stop = e1000_close, 6722 .ndo_start_xmit = e1000_xmit_frame, 6723 .ndo_get_stats64 = e1000e_get_stats64, 6724 .ndo_set_rx_mode = e1000e_set_rx_mode, 6725 .ndo_set_mac_address = e1000_set_mac, 6726 .ndo_change_mtu = e1000_change_mtu, 6727 .ndo_do_ioctl = e1000_ioctl, 6728 .ndo_tx_timeout = e1000_tx_timeout, 6729 .ndo_validate_addr = eth_validate_addr, 6730 6731 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 6732 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 6733 #ifdef CONFIG_NET_POLL_CONTROLLER 6734 .ndo_poll_controller = e1000_netpoll, 6735 #endif 6736 .ndo_set_features = e1000_set_features, 6737 }; 6738 6739 /** 6740 * e1000_probe - Device Initialization Routine 6741 * @pdev: PCI device information struct 6742 * @ent: entry in e1000_pci_tbl 6743 * 6744 * Returns 0 on success, negative on failure 6745 * 6746 * e1000_probe initializes an adapter identified by a pci_dev structure. 6747 * The OS initialization, configuring of the adapter private structure, 6748 * and a hardware reset occur. 6749 **/ 6750 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6751 { 6752 struct net_device *netdev; 6753 struct e1000_adapter *adapter; 6754 struct e1000_hw *hw; 6755 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 6756 resource_size_t mmio_start, mmio_len; 6757 resource_size_t flash_start, flash_len; 6758 static int cards_found; 6759 u16 aspm_disable_flag = 0; 6760 int bars, i, err, pci_using_dac; 6761 u16 eeprom_data = 0; 6762 u16 eeprom_apme_mask = E1000_EEPROM_APME; 6763 s32 rval = 0; 6764 6765 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 6766 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6767 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 6768 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6769 if (aspm_disable_flag) 6770 e1000e_disable_aspm(pdev, aspm_disable_flag); 6771 6772 err = pci_enable_device_mem(pdev); 6773 if (err) 6774 return err; 6775 6776 pci_using_dac = 0; 6777 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6778 if (!err) { 6779 pci_using_dac = 1; 6780 } else { 6781 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 6782 if (err) { 6783 dev_err(&pdev->dev, 6784 "No usable DMA configuration, aborting\n"); 6785 goto err_dma; 6786 } 6787 } 6788 6789 bars = pci_select_bars(pdev, IORESOURCE_MEM); 6790 err = pci_request_selected_regions_exclusive(pdev, bars, 6791 e1000e_driver_name); 6792 if (err) 6793 goto err_pci_reg; 6794 6795 /* AER (Advanced Error Reporting) hooks */ 6796 pci_enable_pcie_error_reporting(pdev); 6797 6798 pci_set_master(pdev); 6799 /* PCI config space info */ 6800 err = pci_save_state(pdev); 6801 if (err) 6802 goto err_alloc_etherdev; 6803 6804 err = -ENOMEM; 6805 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 6806 if (!netdev) 6807 goto err_alloc_etherdev; 6808 6809 SET_NETDEV_DEV(netdev, &pdev->dev); 6810 6811 netdev->irq = pdev->irq; 6812 6813 pci_set_drvdata(pdev, netdev); 6814 adapter = netdev_priv(netdev); 6815 hw = &adapter->hw; 6816 adapter->netdev = netdev; 6817 adapter->pdev = pdev; 6818 adapter->ei = ei; 6819 adapter->pba = ei->pba; 6820 adapter->flags = ei->flags; 6821 adapter->flags2 = ei->flags2; 6822 adapter->hw.adapter = adapter; 6823 adapter->hw.mac.type = ei->mac; 6824 adapter->max_hw_frame_size = ei->max_hw_frame_size; 6825 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6826 6827 mmio_start = pci_resource_start(pdev, 0); 6828 mmio_len = pci_resource_len(pdev, 0); 6829 6830 err = -EIO; 6831 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 6832 if (!adapter->hw.hw_addr) 6833 goto err_ioremap; 6834 6835 if ((adapter->flags & FLAG_HAS_FLASH) && 6836 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 6837 (hw->mac.type < e1000_pch_spt)) { 6838 flash_start = pci_resource_start(pdev, 1); 6839 flash_len = pci_resource_len(pdev, 1); 6840 adapter->hw.flash_address = ioremap(flash_start, flash_len); 6841 if (!adapter->hw.flash_address) 6842 goto err_flashmap; 6843 } 6844 6845 /* Set default EEE advertisement */ 6846 if (adapter->flags2 & FLAG2_HAS_EEE) 6847 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 6848 6849 /* construct the net_device struct */ 6850 netdev->netdev_ops = &e1000e_netdev_ops; 6851 e1000e_set_ethtool_ops(netdev); 6852 netdev->watchdog_timeo = 5 * HZ; 6853 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 6854 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 6855 6856 netdev->mem_start = mmio_start; 6857 netdev->mem_end = mmio_start + mmio_len; 6858 6859 adapter->bd_number = cards_found++; 6860 6861 e1000e_check_options(adapter); 6862 6863 /* setup adapter struct */ 6864 err = e1000_sw_init(adapter); 6865 if (err) 6866 goto err_sw_init; 6867 6868 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 6869 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 6870 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 6871 6872 err = ei->get_variants(adapter); 6873 if (err) 6874 goto err_hw_init; 6875 6876 if ((adapter->flags & FLAG_IS_ICH) && 6877 (adapter->flags & FLAG_READ_ONLY_NVM) && 6878 (hw->mac.type < e1000_pch_spt)) 6879 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 6880 6881 hw->mac.ops.get_bus_info(&adapter->hw); 6882 6883 adapter->hw.phy.autoneg_wait_to_complete = 0; 6884 6885 /* Copper options */ 6886 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 6887 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6888 adapter->hw.phy.disable_polarity_correction = 0; 6889 adapter->hw.phy.ms_type = e1000_ms_hw_default; 6890 } 6891 6892 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 6893 dev_info(&pdev->dev, 6894 "PHY reset is blocked due to SOL/IDER session.\n"); 6895 6896 /* Set initial default active device features */ 6897 netdev->features = (NETIF_F_SG | 6898 NETIF_F_HW_VLAN_CTAG_RX | 6899 NETIF_F_HW_VLAN_CTAG_TX | 6900 NETIF_F_TSO | 6901 NETIF_F_TSO6 | 6902 NETIF_F_RXHASH | 6903 NETIF_F_RXCSUM | 6904 NETIF_F_HW_CSUM); 6905 6906 /* Set user-changeable features (subset of all device features) */ 6907 netdev->hw_features = netdev->features; 6908 netdev->hw_features |= NETIF_F_RXFCS; 6909 netdev->priv_flags |= IFF_SUPP_NOFCS; 6910 netdev->hw_features |= NETIF_F_RXALL; 6911 6912 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 6913 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6914 6915 netdev->vlan_features |= (NETIF_F_SG | 6916 NETIF_F_TSO | 6917 NETIF_F_TSO6 | 6918 NETIF_F_HW_CSUM); 6919 6920 netdev->priv_flags |= IFF_UNICAST_FLT; 6921 6922 if (pci_using_dac) { 6923 netdev->features |= NETIF_F_HIGHDMA; 6924 netdev->vlan_features |= NETIF_F_HIGHDMA; 6925 } 6926 6927 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 6928 adapter->flags |= FLAG_MNG_PT_ENABLED; 6929 6930 /* before reading the NVM, reset the controller to 6931 * put the device in a known good starting state 6932 */ 6933 adapter->hw.mac.ops.reset_hw(&adapter->hw); 6934 6935 /* systems with ASPM and others may see the checksum fail on the first 6936 * attempt. Let's give it a few tries 6937 */ 6938 for (i = 0;; i++) { 6939 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 6940 break; 6941 if (i == 2) { 6942 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 6943 err = -EIO; 6944 goto err_eeprom; 6945 } 6946 } 6947 6948 e1000_eeprom_checks(adapter); 6949 6950 /* copy the MAC address */ 6951 if (e1000e_read_mac_addr(&adapter->hw)) 6952 dev_err(&pdev->dev, 6953 "NVM Read Error while reading MAC address\n"); 6954 6955 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 6956 6957 if (!is_valid_ether_addr(netdev->dev_addr)) { 6958 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 6959 netdev->dev_addr); 6960 err = -EIO; 6961 goto err_eeprom; 6962 } 6963 6964 init_timer(&adapter->watchdog_timer); 6965 adapter->watchdog_timer.function = e1000_watchdog; 6966 adapter->watchdog_timer.data = (unsigned long)adapter; 6967 6968 init_timer(&adapter->phy_info_timer); 6969 adapter->phy_info_timer.function = e1000_update_phy_info; 6970 adapter->phy_info_timer.data = (unsigned long)adapter; 6971 6972 INIT_WORK(&adapter->reset_task, e1000_reset_task); 6973 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 6974 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 6975 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 6976 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 6977 6978 /* Initialize link parameters. User can change them with ethtool */ 6979 adapter->hw.mac.autoneg = 1; 6980 adapter->fc_autoneg = true; 6981 adapter->hw.fc.requested_mode = e1000_fc_default; 6982 adapter->hw.fc.current_mode = e1000_fc_default; 6983 adapter->hw.phy.autoneg_advertised = 0x2f; 6984 6985 /* Initial Wake on LAN setting - If APM wake is enabled in 6986 * the EEPROM, enable the ACPI Magic Packet filter 6987 */ 6988 if (adapter->flags & FLAG_APME_IN_WUC) { 6989 /* APME bit in EEPROM is mapped to WUC.APME */ 6990 eeprom_data = er32(WUC); 6991 eeprom_apme_mask = E1000_WUC_APME; 6992 if ((hw->mac.type > e1000_ich10lan) && 6993 (eeprom_data & E1000_WUC_PHY_WAKE)) 6994 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 6995 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 6996 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 6997 (adapter->hw.bus.func == 1)) 6998 rval = e1000_read_nvm(&adapter->hw, 6999 NVM_INIT_CONTROL3_PORT_B, 7000 1, &eeprom_data); 7001 else 7002 rval = e1000_read_nvm(&adapter->hw, 7003 NVM_INIT_CONTROL3_PORT_A, 7004 1, &eeprom_data); 7005 } 7006 7007 /* fetch WoL from EEPROM */ 7008 if (rval) 7009 e_dbg("NVM read error getting WoL initial values: %d\n", rval); 7010 else if (eeprom_data & eeprom_apme_mask) 7011 adapter->eeprom_wol |= E1000_WUFC_MAG; 7012 7013 /* now that we have the eeprom settings, apply the special cases 7014 * where the eeprom may be wrong or the board simply won't support 7015 * wake on lan on a particular port 7016 */ 7017 if (!(adapter->flags & FLAG_HAS_WOL)) 7018 adapter->eeprom_wol = 0; 7019 7020 /* initialize the wol settings based on the eeprom settings */ 7021 adapter->wol = adapter->eeprom_wol; 7022 7023 /* make sure adapter isn't asleep if manageability is enabled */ 7024 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7025 (hw->mac.ops.check_mng_mode(hw))) 7026 device_wakeup_enable(&pdev->dev); 7027 7028 /* save off EEPROM version number */ 7029 rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7030 7031 if (rval) { 7032 e_dbg("NVM read error getting EEPROM version: %d\n", rval); 7033 adapter->eeprom_vers = 0; 7034 } 7035 7036 /* reset the hardware with the new settings */ 7037 e1000e_reset(adapter); 7038 7039 /* If the controller has AMT, do not set DRV_LOAD until the interface 7040 * is up. For all other cases, let the f/w know that the h/w is now 7041 * under the control of the driver. 7042 */ 7043 if (!(adapter->flags & FLAG_HAS_AMT)) 7044 e1000e_get_hw_control(adapter); 7045 7046 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7047 err = register_netdev(netdev); 7048 if (err) 7049 goto err_register; 7050 7051 /* carrier off reporting is important to ethtool even BEFORE open */ 7052 netif_carrier_off(netdev); 7053 7054 /* init PTP hardware clock */ 7055 e1000e_ptp_init(adapter); 7056 7057 e1000_print_device_info(adapter); 7058 7059 if (pci_dev_run_wake(pdev)) 7060 pm_runtime_put_noidle(&pdev->dev); 7061 7062 return 0; 7063 7064 err_register: 7065 if (!(adapter->flags & FLAG_HAS_AMT)) 7066 e1000e_release_hw_control(adapter); 7067 err_eeprom: 7068 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7069 e1000_phy_hw_reset(&adapter->hw); 7070 err_hw_init: 7071 kfree(adapter->tx_ring); 7072 kfree(adapter->rx_ring); 7073 err_sw_init: 7074 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7075 iounmap(adapter->hw.flash_address); 7076 e1000e_reset_interrupt_capability(adapter); 7077 err_flashmap: 7078 iounmap(adapter->hw.hw_addr); 7079 err_ioremap: 7080 free_netdev(netdev); 7081 err_alloc_etherdev: 7082 pci_release_selected_regions(pdev, 7083 pci_select_bars(pdev, IORESOURCE_MEM)); 7084 err_pci_reg: 7085 err_dma: 7086 pci_disable_device(pdev); 7087 return err; 7088 } 7089 7090 /** 7091 * e1000_remove - Device Removal Routine 7092 * @pdev: PCI device information struct 7093 * 7094 * e1000_remove is called by the PCI subsystem to alert the driver 7095 * that it should release a PCI device. The could be caused by a 7096 * Hot-Plug event, or because the driver is going to be removed from 7097 * memory. 7098 **/ 7099 static void e1000_remove(struct pci_dev *pdev) 7100 { 7101 struct net_device *netdev = pci_get_drvdata(pdev); 7102 struct e1000_adapter *adapter = netdev_priv(netdev); 7103 bool down = test_bit(__E1000_DOWN, &adapter->state); 7104 7105 e1000e_ptp_remove(adapter); 7106 7107 /* The timers may be rescheduled, so explicitly disable them 7108 * from being rescheduled. 7109 */ 7110 if (!down) 7111 set_bit(__E1000_DOWN, &adapter->state); 7112 del_timer_sync(&adapter->watchdog_timer); 7113 del_timer_sync(&adapter->phy_info_timer); 7114 7115 cancel_work_sync(&adapter->reset_task); 7116 cancel_work_sync(&adapter->watchdog_task); 7117 cancel_work_sync(&adapter->downshift_task); 7118 cancel_work_sync(&adapter->update_phy_task); 7119 cancel_work_sync(&adapter->print_hang_task); 7120 7121 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7122 cancel_work_sync(&adapter->tx_hwtstamp_work); 7123 if (adapter->tx_hwtstamp_skb) { 7124 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 7125 adapter->tx_hwtstamp_skb = NULL; 7126 } 7127 } 7128 7129 /* Don't lie to e1000_close() down the road. */ 7130 if (!down) 7131 clear_bit(__E1000_DOWN, &adapter->state); 7132 unregister_netdev(netdev); 7133 7134 if (pci_dev_run_wake(pdev)) 7135 pm_runtime_get_noresume(&pdev->dev); 7136 7137 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7138 * would have already happened in close and is redundant. 7139 */ 7140 e1000e_release_hw_control(adapter); 7141 7142 e1000e_reset_interrupt_capability(adapter); 7143 kfree(adapter->tx_ring); 7144 kfree(adapter->rx_ring); 7145 7146 iounmap(adapter->hw.hw_addr); 7147 if ((adapter->hw.flash_address) && 7148 (adapter->hw.mac.type < e1000_pch_spt)) 7149 iounmap(adapter->hw.flash_address); 7150 pci_release_selected_regions(pdev, 7151 pci_select_bars(pdev, IORESOURCE_MEM)); 7152 7153 free_netdev(netdev); 7154 7155 /* AER disable */ 7156 pci_disable_pcie_error_reporting(pdev); 7157 7158 pci_disable_device(pdev); 7159 } 7160 7161 /* PCI Error Recovery (ERS) */ 7162 static const struct pci_error_handlers e1000_err_handler = { 7163 .error_detected = e1000_io_error_detected, 7164 .slot_reset = e1000_io_slot_reset, 7165 .resume = e1000_io_resume, 7166 }; 7167 7168 static const struct pci_device_id e1000_pci_tbl[] = { 7169 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7170 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7171 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7172 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7173 board_82571 }, 7174 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7175 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7176 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7177 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7178 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7179 7180 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7181 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7182 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7183 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7184 7185 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7186 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7187 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7188 7189 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7190 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7191 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7192 7193 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7194 board_80003es2lan }, 7195 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7196 board_80003es2lan }, 7197 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7198 board_80003es2lan }, 7199 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7200 board_80003es2lan }, 7201 7202 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7203 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7204 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7205 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7206 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7207 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7208 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7209 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7210 7211 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7212 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7213 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7214 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7215 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7216 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7217 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7218 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7219 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7220 7221 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7222 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7223 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7224 7225 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7226 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7227 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7228 7229 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7230 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7231 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7232 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7233 7234 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7235 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7236 7237 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7238 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7239 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7240 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7241 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7242 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7243 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7244 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7245 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7246 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7247 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7248 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7249 7250 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7251 }; 7252 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7253 7254 static const struct dev_pm_ops e1000_pm_ops = { 7255 #ifdef CONFIG_PM_SLEEP 7256 .suspend = e1000e_pm_suspend, 7257 .resume = e1000e_pm_resume, 7258 .freeze = e1000e_pm_freeze, 7259 .thaw = e1000e_pm_thaw, 7260 .poweroff = e1000e_pm_suspend, 7261 .restore = e1000e_pm_resume, 7262 #endif 7263 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7264 e1000e_pm_runtime_idle) 7265 }; 7266 7267 /* PCI Device API Driver */ 7268 static struct pci_driver e1000_driver = { 7269 .name = e1000e_driver_name, 7270 .id_table = e1000_pci_tbl, 7271 .probe = e1000_probe, 7272 .remove = e1000_remove, 7273 .driver = { 7274 .pm = &e1000_pm_ops, 7275 }, 7276 .shutdown = e1000_shutdown, 7277 .err_handler = &e1000_err_handler 7278 }; 7279 7280 /** 7281 * e1000_init_module - Driver Registration Routine 7282 * 7283 * e1000_init_module is the first routine called when the driver is 7284 * loaded. All it does is register with the PCI subsystem. 7285 **/ 7286 static int __init e1000_init_module(void) 7287 { 7288 int ret; 7289 7290 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7291 e1000e_driver_version); 7292 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n"); 7293 ret = pci_register_driver(&e1000_driver); 7294 7295 return ret; 7296 } 7297 module_init(e1000_init_module); 7298 7299 /** 7300 * e1000_exit_module - Driver Exit Cleanup Routine 7301 * 7302 * e1000_exit_module is called just before the driver is removed 7303 * from memory. 7304 **/ 7305 static void __exit e1000_exit_module(void) 7306 { 7307 pci_unregister_driver(&e1000_driver); 7308 } 7309 module_exit(e1000_exit_module); 7310 7311 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7312 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7313 MODULE_LICENSE("GPL"); 7314 MODULE_VERSION(DRV_VERSION); 7315 7316 /* netdev.c */ 7317