1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24 #include <linux/module.h> 25 #include <linux/types.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/vmalloc.h> 29 #include <linux/pagemap.h> 30 #include <linux/delay.h> 31 #include <linux/netdevice.h> 32 #include <linux/interrupt.h> 33 #include <linux/tcp.h> 34 #include <linux/ipv6.h> 35 #include <linux/slab.h> 36 #include <net/checksum.h> 37 #include <net/ip6_checksum.h> 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/cpu.h> 41 #include <linux/smp.h> 42 #include <linux/pm_qos.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/aer.h> 45 #include <linux/prefetch.h> 46 47 #include "e1000.h" 48 49 #define DRV_EXTRAVERSION "-k" 50 51 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION 52 char e1000e_driver_name[] = "e1000e"; 53 const char e1000e_driver_version[] = DRV_VERSION; 54 55 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 56 static int debug = -1; 57 module_param(debug, int, 0); 58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 59 60 static const struct e1000_info *e1000_info_tbl[] = { 61 [board_82571] = &e1000_82571_info, 62 [board_82572] = &e1000_82572_info, 63 [board_82573] = &e1000_82573_info, 64 [board_82574] = &e1000_82574_info, 65 [board_82583] = &e1000_82583_info, 66 [board_80003es2lan] = &e1000_es2_info, 67 [board_ich8lan] = &e1000_ich8_info, 68 [board_ich9lan] = &e1000_ich9_info, 69 [board_ich10lan] = &e1000_ich10_info, 70 [board_pchlan] = &e1000_pch_info, 71 [board_pch2lan] = &e1000_pch2_info, 72 [board_pch_lpt] = &e1000_pch_lpt_info, 73 [board_pch_spt] = &e1000_pch_spt_info, 74 [board_pch_cnp] = &e1000_pch_cnp_info, 75 }; 76 77 struct e1000_reg_info { 78 u32 ofs; 79 char *name; 80 }; 81 82 static const struct e1000_reg_info e1000_reg_info_tbl[] = { 83 /* General Registers */ 84 {E1000_CTRL, "CTRL"}, 85 {E1000_STATUS, "STATUS"}, 86 {E1000_CTRL_EXT, "CTRL_EXT"}, 87 88 /* Interrupt Registers */ 89 {E1000_ICR, "ICR"}, 90 91 /* Rx Registers */ 92 {E1000_RCTL, "RCTL"}, 93 {E1000_RDLEN(0), "RDLEN"}, 94 {E1000_RDH(0), "RDH"}, 95 {E1000_RDT(0), "RDT"}, 96 {E1000_RDTR, "RDTR"}, 97 {E1000_RXDCTL(0), "RXDCTL"}, 98 {E1000_ERT, "ERT"}, 99 {E1000_RDBAL(0), "RDBAL"}, 100 {E1000_RDBAH(0), "RDBAH"}, 101 {E1000_RDFH, "RDFH"}, 102 {E1000_RDFT, "RDFT"}, 103 {E1000_RDFHS, "RDFHS"}, 104 {E1000_RDFTS, "RDFTS"}, 105 {E1000_RDFPC, "RDFPC"}, 106 107 /* Tx Registers */ 108 {E1000_TCTL, "TCTL"}, 109 {E1000_TDBAL(0), "TDBAL"}, 110 {E1000_TDBAH(0), "TDBAH"}, 111 {E1000_TDLEN(0), "TDLEN"}, 112 {E1000_TDH(0), "TDH"}, 113 {E1000_TDT(0), "TDT"}, 114 {E1000_TIDV, "TIDV"}, 115 {E1000_TXDCTL(0), "TXDCTL"}, 116 {E1000_TADV, "TADV"}, 117 {E1000_TARC(0), "TARC"}, 118 {E1000_TDFH, "TDFH"}, 119 {E1000_TDFT, "TDFT"}, 120 {E1000_TDFHS, "TDFHS"}, 121 {E1000_TDFTS, "TDFTS"}, 122 {E1000_TDFPC, "TDFPC"}, 123 124 /* List Terminator */ 125 {0, NULL} 126 }; 127 128 /** 129 * __ew32_prepare - prepare to write to MAC CSR register on certain parts 130 * @hw: pointer to the HW structure 131 * 132 * When updating the MAC CSR registers, the Manageability Engine (ME) could 133 * be accessing the registers at the same time. Normally, this is handled in 134 * h/w by an arbiter but on some parts there is a bug that acknowledges Host 135 * accesses later than it should which could result in the register to have 136 * an incorrect value. Workaround this by checking the FWSM register which 137 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set 138 * and try again a number of times. 139 **/ 140 s32 __ew32_prepare(struct e1000_hw *hw) 141 { 142 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; 143 144 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) 145 udelay(50); 146 147 return i; 148 } 149 150 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) 151 { 152 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 153 __ew32_prepare(hw); 154 155 writel(val, hw->hw_addr + reg); 156 } 157 158 /** 159 * e1000_regdump - register printout routine 160 * @hw: pointer to the HW structure 161 * @reginfo: pointer to the register info table 162 **/ 163 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 164 { 165 int n = 0; 166 char rname[16]; 167 u32 regs[8]; 168 169 switch (reginfo->ofs) { 170 case E1000_RXDCTL(0): 171 for (n = 0; n < 2; n++) 172 regs[n] = __er32(hw, E1000_RXDCTL(n)); 173 break; 174 case E1000_TXDCTL(0): 175 for (n = 0; n < 2; n++) 176 regs[n] = __er32(hw, E1000_TXDCTL(n)); 177 break; 178 case E1000_TARC(0): 179 for (n = 0; n < 2; n++) 180 regs[n] = __er32(hw, E1000_TARC(n)); 181 break; 182 default: 183 pr_info("%-15s %08x\n", 184 reginfo->name, __er32(hw, reginfo->ofs)); 185 return; 186 } 187 188 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); 189 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); 190 } 191 192 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, 193 struct e1000_buffer *bi) 194 { 195 int i; 196 struct e1000_ps_page *ps_page; 197 198 for (i = 0; i < adapter->rx_ps_pages; i++) { 199 ps_page = &bi->ps_pages[i]; 200 201 if (ps_page->page) { 202 pr_info("packet dump for ps_page %d:\n", i); 203 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 204 16, 1, page_address(ps_page->page), 205 PAGE_SIZE, true); 206 } 207 } 208 } 209 210 /** 211 * e1000e_dump - Print registers, Tx-ring and Rx-ring 212 * @adapter: board private structure 213 **/ 214 static void e1000e_dump(struct e1000_adapter *adapter) 215 { 216 struct net_device *netdev = adapter->netdev; 217 struct e1000_hw *hw = &adapter->hw; 218 struct e1000_reg_info *reginfo; 219 struct e1000_ring *tx_ring = adapter->tx_ring; 220 struct e1000_tx_desc *tx_desc; 221 struct my_u0 { 222 __le64 a; 223 __le64 b; 224 } *u0; 225 struct e1000_buffer *buffer_info; 226 struct e1000_ring *rx_ring = adapter->rx_ring; 227 union e1000_rx_desc_packet_split *rx_desc_ps; 228 union e1000_rx_desc_extended *rx_desc; 229 struct my_u1 { 230 __le64 a; 231 __le64 b; 232 __le64 c; 233 __le64 d; 234 } *u1; 235 u32 staterr; 236 int i = 0; 237 238 if (!netif_msg_hw(adapter)) 239 return; 240 241 /* Print netdevice Info */ 242 if (netdev) { 243 dev_info(&adapter->pdev->dev, "Net device Info\n"); 244 pr_info("Device Name state trans_start\n"); 245 pr_info("%-15s %016lX %016lX\n", netdev->name, 246 netdev->state, dev_trans_start(netdev)); 247 } 248 249 /* Print Registers */ 250 dev_info(&adapter->pdev->dev, "Register Dump\n"); 251 pr_info(" Register Name Value\n"); 252 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; 253 reginfo->name; reginfo++) { 254 e1000_regdump(hw, reginfo); 255 } 256 257 /* Print Tx Ring Summary */ 258 if (!netdev || !netif_running(netdev)) 259 return; 260 261 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); 262 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 263 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; 264 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", 265 0, tx_ring->next_to_use, tx_ring->next_to_clean, 266 (unsigned long long)buffer_info->dma, 267 buffer_info->length, 268 buffer_info->next_to_watch, 269 (unsigned long long)buffer_info->time_stamp); 270 271 /* Print Tx Ring */ 272 if (!netif_msg_tx_done(adapter)) 273 goto rx_ring_summary; 274 275 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); 276 277 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) 278 * 279 * Legacy Transmit Descriptor 280 * +--------------------------------------------------------------+ 281 * 0 | Buffer Address [63:0] (Reserved on Write Back) | 282 * +--------------------------------------------------------------+ 283 * 8 | Special | CSS | Status | CMD | CSO | Length | 284 * +--------------------------------------------------------------+ 285 * 63 48 47 36 35 32 31 24 23 16 15 0 286 * 287 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload 288 * 63 48 47 40 39 32 31 16 15 8 7 0 289 * +----------------------------------------------------------------+ 290 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | 291 * +----------------------------------------------------------------+ 292 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | 293 * +----------------------------------------------------------------+ 294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 295 * 296 * Extended Data Descriptor (DTYP=0x1) 297 * +----------------------------------------------------------------+ 298 * 0 | Buffer Address [63:0] | 299 * +----------------------------------------------------------------+ 300 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | 301 * +----------------------------------------------------------------+ 302 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 303 */ 304 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); 305 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); 306 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); 307 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 308 const char *next_desc; 309 tx_desc = E1000_TX_DESC(*tx_ring, i); 310 buffer_info = &tx_ring->buffer_info[i]; 311 u0 = (struct my_u0 *)tx_desc; 312 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) 313 next_desc = " NTC/U"; 314 else if (i == tx_ring->next_to_use) 315 next_desc = " NTU"; 316 else if (i == tx_ring->next_to_clean) 317 next_desc = " NTC"; 318 else 319 next_desc = ""; 320 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", 321 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : 322 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), 323 i, 324 (unsigned long long)le64_to_cpu(u0->a), 325 (unsigned long long)le64_to_cpu(u0->b), 326 (unsigned long long)buffer_info->dma, 327 buffer_info->length, buffer_info->next_to_watch, 328 (unsigned long long)buffer_info->time_stamp, 329 buffer_info->skb, next_desc); 330 331 if (netif_msg_pktdata(adapter) && buffer_info->skb) 332 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 333 16, 1, buffer_info->skb->data, 334 buffer_info->skb->len, true); 335 } 336 337 /* Print Rx Ring Summary */ 338 rx_ring_summary: 339 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); 340 pr_info("Queue [NTU] [NTC]\n"); 341 pr_info(" %5d %5X %5X\n", 342 0, rx_ring->next_to_use, rx_ring->next_to_clean); 343 344 /* Print Rx Ring */ 345 if (!netif_msg_rx_status(adapter)) 346 return; 347 348 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); 349 switch (adapter->rx_ps_pages) { 350 case 1: 351 case 2: 352 case 3: 353 /* [Extended] Packet Split Receive Descriptor Format 354 * 355 * +-----------------------------------------------------+ 356 * 0 | Buffer Address 0 [63:0] | 357 * +-----------------------------------------------------+ 358 * 8 | Buffer Address 1 [63:0] | 359 * +-----------------------------------------------------+ 360 * 16 | Buffer Address 2 [63:0] | 361 * +-----------------------------------------------------+ 362 * 24 | Buffer Address 3 [63:0] | 363 * +-----------------------------------------------------+ 364 */ 365 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); 366 /* [Extended] Receive Descriptor (Write-Back) Format 367 * 368 * 63 48 47 32 31 13 12 8 7 4 3 0 369 * +------------------------------------------------------+ 370 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | 371 * | Checksum | Ident | | Queue | | Type | 372 * +------------------------------------------------------+ 373 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 374 * +------------------------------------------------------+ 375 * 63 48 47 32 31 20 19 0 376 */ 377 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); 378 for (i = 0; i < rx_ring->count; i++) { 379 const char *next_desc; 380 buffer_info = &rx_ring->buffer_info[i]; 381 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); 382 u1 = (struct my_u1 *)rx_desc_ps; 383 staterr = 384 le32_to_cpu(rx_desc_ps->wb.middle.status_error); 385 386 if (i == rx_ring->next_to_use) 387 next_desc = " NTU"; 388 else if (i == rx_ring->next_to_clean) 389 next_desc = " NTC"; 390 else 391 next_desc = ""; 392 393 if (staterr & E1000_RXD_STAT_DD) { 394 /* Descriptor Done */ 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", 396 "RWB", i, 397 (unsigned long long)le64_to_cpu(u1->a), 398 (unsigned long long)le64_to_cpu(u1->b), 399 (unsigned long long)le64_to_cpu(u1->c), 400 (unsigned long long)le64_to_cpu(u1->d), 401 buffer_info->skb, next_desc); 402 } else { 403 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", 404 "R ", i, 405 (unsigned long long)le64_to_cpu(u1->a), 406 (unsigned long long)le64_to_cpu(u1->b), 407 (unsigned long long)le64_to_cpu(u1->c), 408 (unsigned long long)le64_to_cpu(u1->d), 409 (unsigned long long)buffer_info->dma, 410 buffer_info->skb, next_desc); 411 412 if (netif_msg_pktdata(adapter)) 413 e1000e_dump_ps_pages(adapter, 414 buffer_info); 415 } 416 } 417 break; 418 default: 419 case 0: 420 /* Extended Receive Descriptor (Read) Format 421 * 422 * +-----------------------------------------------------+ 423 * 0 | Buffer Address [63:0] | 424 * +-----------------------------------------------------+ 425 * 8 | Reserved | 426 * +-----------------------------------------------------+ 427 */ 428 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); 429 /* Extended Receive Descriptor (Write-Back) Format 430 * 431 * 63 48 47 32 31 24 23 4 3 0 432 * +------------------------------------------------------+ 433 * | RSS Hash | | | | 434 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | 435 * | Packet | IP | | | Type | 436 * | Checksum | Ident | | | | 437 * +------------------------------------------------------+ 438 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 439 * +------------------------------------------------------+ 440 * 63 48 47 32 31 20 19 0 441 */ 442 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); 443 444 for (i = 0; i < rx_ring->count; i++) { 445 const char *next_desc; 446 447 buffer_info = &rx_ring->buffer_info[i]; 448 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 449 u1 = (struct my_u1 *)rx_desc; 450 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 451 452 if (i == rx_ring->next_to_use) 453 next_desc = " NTU"; 454 else if (i == rx_ring->next_to_clean) 455 next_desc = " NTC"; 456 else 457 next_desc = ""; 458 459 if (staterr & E1000_RXD_STAT_DD) { 460 /* Descriptor Done */ 461 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", 462 "RWB", i, 463 (unsigned long long)le64_to_cpu(u1->a), 464 (unsigned long long)le64_to_cpu(u1->b), 465 buffer_info->skb, next_desc); 466 } else { 467 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", 468 "R ", i, 469 (unsigned long long)le64_to_cpu(u1->a), 470 (unsigned long long)le64_to_cpu(u1->b), 471 (unsigned long long)buffer_info->dma, 472 buffer_info->skb, next_desc); 473 474 if (netif_msg_pktdata(adapter) && 475 buffer_info->skb) 476 print_hex_dump(KERN_INFO, "", 477 DUMP_PREFIX_ADDRESS, 16, 478 1, 479 buffer_info->skb->data, 480 adapter->rx_buffer_len, 481 true); 482 } 483 } 484 } 485 } 486 487 /** 488 * e1000_desc_unused - calculate if we have unused descriptors 489 **/ 490 static int e1000_desc_unused(struct e1000_ring *ring) 491 { 492 if (ring->next_to_clean > ring->next_to_use) 493 return ring->next_to_clean - ring->next_to_use - 1; 494 495 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 496 } 497 498 /** 499 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp 500 * @adapter: board private structure 501 * @hwtstamps: time stamp structure to update 502 * @systim: unsigned 64bit system time value. 503 * 504 * Convert the system time value stored in the RX/TXSTMP registers into a 505 * hwtstamp which can be used by the upper level time stamping functions. 506 * 507 * The 'systim_lock' spinlock is used to protect the consistency of the 508 * system time value. This is needed because reading the 64 bit time 509 * value involves reading two 32 bit registers. The first read latches the 510 * value. 511 **/ 512 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, 513 struct skb_shared_hwtstamps *hwtstamps, 514 u64 systim) 515 { 516 u64 ns; 517 unsigned long flags; 518 519 spin_lock_irqsave(&adapter->systim_lock, flags); 520 ns = timecounter_cyc2time(&adapter->tc, systim); 521 spin_unlock_irqrestore(&adapter->systim_lock, flags); 522 523 memset(hwtstamps, 0, sizeof(*hwtstamps)); 524 hwtstamps->hwtstamp = ns_to_ktime(ns); 525 } 526 527 /** 528 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp 529 * @adapter: board private structure 530 * @status: descriptor extended error and status field 531 * @skb: particular skb to include time stamp 532 * 533 * If the time stamp is valid, convert it into the timecounter ns value 534 * and store that result into the shhwtstamps structure which is passed 535 * up the network stack. 536 **/ 537 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, 538 struct sk_buff *skb) 539 { 540 struct e1000_hw *hw = &adapter->hw; 541 u64 rxstmp; 542 543 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || 544 !(status & E1000_RXDEXT_STATERR_TST) || 545 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 546 return; 547 548 /* The Rx time stamp registers contain the time stamp. No other 549 * received packet will be time stamped until the Rx time stamp 550 * registers are read. Because only one packet can be time stamped 551 * at a time, the register values must belong to this packet and 552 * therefore none of the other additional attributes need to be 553 * compared. 554 */ 555 rxstmp = (u64)er32(RXSTMPL); 556 rxstmp |= (u64)er32(RXSTMPH) << 32; 557 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); 558 559 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; 560 } 561 562 /** 563 * e1000_receive_skb - helper function to handle Rx indications 564 * @adapter: board private structure 565 * @staterr: descriptor extended error and status field as written by hardware 566 * @vlan: descriptor vlan field as written by hardware (no le/be conversion) 567 * @skb: pointer to sk_buff to be indicated to stack 568 **/ 569 static void e1000_receive_skb(struct e1000_adapter *adapter, 570 struct net_device *netdev, struct sk_buff *skb, 571 u32 staterr, __le16 vlan) 572 { 573 u16 tag = le16_to_cpu(vlan); 574 575 e1000e_rx_hwtstamp(adapter, staterr, skb); 576 577 skb->protocol = eth_type_trans(skb, netdev); 578 579 if (staterr & E1000_RXD_STAT_VP) 580 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); 581 582 napi_gro_receive(&adapter->napi, skb); 583 } 584 585 /** 586 * e1000_rx_checksum - Receive Checksum Offload 587 * @adapter: board private structure 588 * @status_err: receive descriptor status and error fields 589 * @csum: receive descriptor csum field 590 * @sk_buff: socket buffer with received data 591 **/ 592 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, 593 struct sk_buff *skb) 594 { 595 u16 status = (u16)status_err; 596 u8 errors = (u8)(status_err >> 24); 597 598 skb_checksum_none_assert(skb); 599 600 /* Rx checksum disabled */ 601 if (!(adapter->netdev->features & NETIF_F_RXCSUM)) 602 return; 603 604 /* Ignore Checksum bit is set */ 605 if (status & E1000_RXD_STAT_IXSM) 606 return; 607 608 /* TCP/UDP checksum error bit or IP checksum error bit is set */ 609 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { 610 /* let the stack verify checksum errors */ 611 adapter->hw_csum_err++; 612 return; 613 } 614 615 /* TCP/UDP Checksum has not been calculated */ 616 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) 617 return; 618 619 /* It must be a TCP or UDP packet with a valid checksum */ 620 skb->ip_summed = CHECKSUM_UNNECESSARY; 621 adapter->hw_csum_good++; 622 } 623 624 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) 625 { 626 struct e1000_adapter *adapter = rx_ring->adapter; 627 struct e1000_hw *hw = &adapter->hw; 628 s32 ret_val = __ew32_prepare(hw); 629 630 writel(i, rx_ring->tail); 631 632 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { 633 u32 rctl = er32(RCTL); 634 635 ew32(RCTL, rctl & ~E1000_RCTL_EN); 636 e_err("ME firmware caused invalid RDT - resetting\n"); 637 schedule_work(&adapter->reset_task); 638 } 639 } 640 641 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) 642 { 643 struct e1000_adapter *adapter = tx_ring->adapter; 644 struct e1000_hw *hw = &adapter->hw; 645 s32 ret_val = __ew32_prepare(hw); 646 647 writel(i, tx_ring->tail); 648 649 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { 650 u32 tctl = er32(TCTL); 651 652 ew32(TCTL, tctl & ~E1000_TCTL_EN); 653 e_err("ME firmware caused invalid TDT - resetting\n"); 654 schedule_work(&adapter->reset_task); 655 } 656 } 657 658 /** 659 * e1000_alloc_rx_buffers - Replace used receive buffers 660 * @rx_ring: Rx descriptor ring 661 **/ 662 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, 663 int cleaned_count, gfp_t gfp) 664 { 665 struct e1000_adapter *adapter = rx_ring->adapter; 666 struct net_device *netdev = adapter->netdev; 667 struct pci_dev *pdev = adapter->pdev; 668 union e1000_rx_desc_extended *rx_desc; 669 struct e1000_buffer *buffer_info; 670 struct sk_buff *skb; 671 unsigned int i; 672 unsigned int bufsz = adapter->rx_buffer_len; 673 674 i = rx_ring->next_to_use; 675 buffer_info = &rx_ring->buffer_info[i]; 676 677 while (cleaned_count--) { 678 skb = buffer_info->skb; 679 if (skb) { 680 skb_trim(skb, 0); 681 goto map_skb; 682 } 683 684 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 685 if (!skb) { 686 /* Better luck next round */ 687 adapter->alloc_rx_buff_failed++; 688 break; 689 } 690 691 buffer_info->skb = skb; 692 map_skb: 693 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 694 adapter->rx_buffer_len, 695 DMA_FROM_DEVICE); 696 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 697 dev_err(&pdev->dev, "Rx DMA map failed\n"); 698 adapter->rx_dma_failed++; 699 break; 700 } 701 702 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 703 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 704 705 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 706 /* Force memory writes to complete before letting h/w 707 * know there are new descriptors to fetch. (Only 708 * applicable for weak-ordered memory model archs, 709 * such as IA-64). 710 */ 711 wmb(); 712 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 713 e1000e_update_rdt_wa(rx_ring, i); 714 else 715 writel(i, rx_ring->tail); 716 } 717 i++; 718 if (i == rx_ring->count) 719 i = 0; 720 buffer_info = &rx_ring->buffer_info[i]; 721 } 722 723 rx_ring->next_to_use = i; 724 } 725 726 /** 727 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split 728 * @rx_ring: Rx descriptor ring 729 **/ 730 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, 731 int cleaned_count, gfp_t gfp) 732 { 733 struct e1000_adapter *adapter = rx_ring->adapter; 734 struct net_device *netdev = adapter->netdev; 735 struct pci_dev *pdev = adapter->pdev; 736 union e1000_rx_desc_packet_split *rx_desc; 737 struct e1000_buffer *buffer_info; 738 struct e1000_ps_page *ps_page; 739 struct sk_buff *skb; 740 unsigned int i, j; 741 742 i = rx_ring->next_to_use; 743 buffer_info = &rx_ring->buffer_info[i]; 744 745 while (cleaned_count--) { 746 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 747 748 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 749 ps_page = &buffer_info->ps_pages[j]; 750 if (j >= adapter->rx_ps_pages) { 751 /* all unused desc entries get hw null ptr */ 752 rx_desc->read.buffer_addr[j + 1] = 753 ~cpu_to_le64(0); 754 continue; 755 } 756 if (!ps_page->page) { 757 ps_page->page = alloc_page(gfp); 758 if (!ps_page->page) { 759 adapter->alloc_rx_buff_failed++; 760 goto no_buffers; 761 } 762 ps_page->dma = dma_map_page(&pdev->dev, 763 ps_page->page, 764 0, PAGE_SIZE, 765 DMA_FROM_DEVICE); 766 if (dma_mapping_error(&pdev->dev, 767 ps_page->dma)) { 768 dev_err(&adapter->pdev->dev, 769 "Rx DMA page map failed\n"); 770 adapter->rx_dma_failed++; 771 goto no_buffers; 772 } 773 } 774 /* Refresh the desc even if buffer_addrs 775 * didn't change because each write-back 776 * erases this info. 777 */ 778 rx_desc->read.buffer_addr[j + 1] = 779 cpu_to_le64(ps_page->dma); 780 } 781 782 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, 783 gfp); 784 785 if (!skb) { 786 adapter->alloc_rx_buff_failed++; 787 break; 788 } 789 790 buffer_info->skb = skb; 791 buffer_info->dma = dma_map_single(&pdev->dev, skb->data, 792 adapter->rx_ps_bsize0, 793 DMA_FROM_DEVICE); 794 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 795 dev_err(&pdev->dev, "Rx DMA map failed\n"); 796 adapter->rx_dma_failed++; 797 /* cleanup skb */ 798 dev_kfree_skb_any(skb); 799 buffer_info->skb = NULL; 800 break; 801 } 802 803 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 804 805 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 806 /* Force memory writes to complete before letting h/w 807 * know there are new descriptors to fetch. (Only 808 * applicable for weak-ordered memory model archs, 809 * such as IA-64). 810 */ 811 wmb(); 812 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 813 e1000e_update_rdt_wa(rx_ring, i << 1); 814 else 815 writel(i << 1, rx_ring->tail); 816 } 817 818 i++; 819 if (i == rx_ring->count) 820 i = 0; 821 buffer_info = &rx_ring->buffer_info[i]; 822 } 823 824 no_buffers: 825 rx_ring->next_to_use = i; 826 } 827 828 /** 829 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers 830 * @rx_ring: Rx descriptor ring 831 * @cleaned_count: number of buffers to allocate this pass 832 **/ 833 834 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, 835 int cleaned_count, gfp_t gfp) 836 { 837 struct e1000_adapter *adapter = rx_ring->adapter; 838 struct net_device *netdev = adapter->netdev; 839 struct pci_dev *pdev = adapter->pdev; 840 union e1000_rx_desc_extended *rx_desc; 841 struct e1000_buffer *buffer_info; 842 struct sk_buff *skb; 843 unsigned int i; 844 unsigned int bufsz = 256 - 16; /* for skb_reserve */ 845 846 i = rx_ring->next_to_use; 847 buffer_info = &rx_ring->buffer_info[i]; 848 849 while (cleaned_count--) { 850 skb = buffer_info->skb; 851 if (skb) { 852 skb_trim(skb, 0); 853 goto check_page; 854 } 855 856 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); 857 if (unlikely(!skb)) { 858 /* Better luck next round */ 859 adapter->alloc_rx_buff_failed++; 860 break; 861 } 862 863 buffer_info->skb = skb; 864 check_page: 865 /* allocate a new page if necessary */ 866 if (!buffer_info->page) { 867 buffer_info->page = alloc_page(gfp); 868 if (unlikely(!buffer_info->page)) { 869 adapter->alloc_rx_buff_failed++; 870 break; 871 } 872 } 873 874 if (!buffer_info->dma) { 875 buffer_info->dma = dma_map_page(&pdev->dev, 876 buffer_info->page, 0, 877 PAGE_SIZE, 878 DMA_FROM_DEVICE); 879 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { 880 adapter->alloc_rx_buff_failed++; 881 break; 882 } 883 } 884 885 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 886 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 887 888 if (unlikely(++i == rx_ring->count)) 889 i = 0; 890 buffer_info = &rx_ring->buffer_info[i]; 891 } 892 893 if (likely(rx_ring->next_to_use != i)) { 894 rx_ring->next_to_use = i; 895 if (unlikely(i-- == 0)) 896 i = (rx_ring->count - 1); 897 898 /* Force memory writes to complete before letting h/w 899 * know there are new descriptors to fetch. (Only 900 * applicable for weak-ordered memory model archs, 901 * such as IA-64). 902 */ 903 wmb(); 904 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 905 e1000e_update_rdt_wa(rx_ring, i); 906 else 907 writel(i, rx_ring->tail); 908 } 909 } 910 911 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, 912 struct sk_buff *skb) 913 { 914 if (netdev->features & NETIF_F_RXHASH) 915 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); 916 } 917 918 /** 919 * e1000_clean_rx_irq - Send received data up the network stack 920 * @rx_ring: Rx descriptor ring 921 * 922 * the return value indicates whether actual cleaning was done, there 923 * is no guarantee that everything was cleaned 924 **/ 925 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, 926 int work_to_do) 927 { 928 struct e1000_adapter *adapter = rx_ring->adapter; 929 struct net_device *netdev = adapter->netdev; 930 struct pci_dev *pdev = adapter->pdev; 931 struct e1000_hw *hw = &adapter->hw; 932 union e1000_rx_desc_extended *rx_desc, *next_rxd; 933 struct e1000_buffer *buffer_info, *next_buffer; 934 u32 length, staterr; 935 unsigned int i; 936 int cleaned_count = 0; 937 bool cleaned = false; 938 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 939 940 i = rx_ring->next_to_clean; 941 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 942 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 943 buffer_info = &rx_ring->buffer_info[i]; 944 945 while (staterr & E1000_RXD_STAT_DD) { 946 struct sk_buff *skb; 947 948 if (*work_done >= work_to_do) 949 break; 950 (*work_done)++; 951 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 952 953 skb = buffer_info->skb; 954 buffer_info->skb = NULL; 955 956 prefetch(skb->data - NET_IP_ALIGN); 957 958 i++; 959 if (i == rx_ring->count) 960 i = 0; 961 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 962 prefetch(next_rxd); 963 964 next_buffer = &rx_ring->buffer_info[i]; 965 966 cleaned = true; 967 cleaned_count++; 968 dma_unmap_single(&pdev->dev, buffer_info->dma, 969 adapter->rx_buffer_len, DMA_FROM_DEVICE); 970 buffer_info->dma = 0; 971 972 length = le16_to_cpu(rx_desc->wb.upper.length); 973 974 /* !EOP means multiple descriptors were used to store a single 975 * packet, if that's the case we need to toss it. In fact, we 976 * need to toss every packet with the EOP bit clear and the 977 * next frame that _does_ have the EOP bit set, as it is by 978 * definition only a frame fragment 979 */ 980 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) 981 adapter->flags2 |= FLAG2_IS_DISCARDING; 982 983 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 984 /* All receives must fit into a single buffer */ 985 e_dbg("Receive packet consumed multiple buffers\n"); 986 /* recycle */ 987 buffer_info->skb = skb; 988 if (staterr & E1000_RXD_STAT_EOP) 989 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 990 goto next_desc; 991 } 992 993 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 994 !(netdev->features & NETIF_F_RXALL))) { 995 /* recycle */ 996 buffer_info->skb = skb; 997 goto next_desc; 998 } 999 1000 /* adjust length to remove Ethernet CRC */ 1001 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1002 /* If configured to store CRC, don't subtract FCS, 1003 * but keep the FCS bytes out of the total_rx_bytes 1004 * counter 1005 */ 1006 if (netdev->features & NETIF_F_RXFCS) 1007 total_rx_bytes -= 4; 1008 else 1009 length -= 4; 1010 } 1011 1012 total_rx_bytes += length; 1013 total_rx_packets++; 1014 1015 /* code added for copybreak, this should improve 1016 * performance for small packets with large amounts 1017 * of reassembly being done in the stack 1018 */ 1019 if (length < copybreak) { 1020 struct sk_buff *new_skb = 1021 napi_alloc_skb(&adapter->napi, length); 1022 if (new_skb) { 1023 skb_copy_to_linear_data_offset(new_skb, 1024 -NET_IP_ALIGN, 1025 (skb->data - 1026 NET_IP_ALIGN), 1027 (length + 1028 NET_IP_ALIGN)); 1029 /* save the skb in buffer_info as good */ 1030 buffer_info->skb = skb; 1031 skb = new_skb; 1032 } 1033 /* else just continue with the old one */ 1034 } 1035 /* end copybreak code */ 1036 skb_put(skb, length); 1037 1038 /* Receive Checksum Offload */ 1039 e1000_rx_checksum(adapter, staterr, skb); 1040 1041 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1042 1043 e1000_receive_skb(adapter, netdev, skb, staterr, 1044 rx_desc->wb.upper.vlan); 1045 1046 next_desc: 1047 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1048 1049 /* return some buffers to hardware, one at a time is too slow */ 1050 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1051 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1052 GFP_ATOMIC); 1053 cleaned_count = 0; 1054 } 1055 1056 /* use prefetched values */ 1057 rx_desc = next_rxd; 1058 buffer_info = next_buffer; 1059 1060 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1061 } 1062 rx_ring->next_to_clean = i; 1063 1064 cleaned_count = e1000_desc_unused(rx_ring); 1065 if (cleaned_count) 1066 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1067 1068 adapter->total_rx_bytes += total_rx_bytes; 1069 adapter->total_rx_packets += total_rx_packets; 1070 return cleaned; 1071 } 1072 1073 static void e1000_put_txbuf(struct e1000_ring *tx_ring, 1074 struct e1000_buffer *buffer_info, 1075 bool drop) 1076 { 1077 struct e1000_adapter *adapter = tx_ring->adapter; 1078 1079 if (buffer_info->dma) { 1080 if (buffer_info->mapped_as_page) 1081 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, 1082 buffer_info->length, DMA_TO_DEVICE); 1083 else 1084 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1085 buffer_info->length, DMA_TO_DEVICE); 1086 buffer_info->dma = 0; 1087 } 1088 if (buffer_info->skb) { 1089 if (drop) 1090 dev_kfree_skb_any(buffer_info->skb); 1091 else 1092 dev_consume_skb_any(buffer_info->skb); 1093 buffer_info->skb = NULL; 1094 } 1095 buffer_info->time_stamp = 0; 1096 } 1097 1098 static void e1000_print_hw_hang(struct work_struct *work) 1099 { 1100 struct e1000_adapter *adapter = container_of(work, 1101 struct e1000_adapter, 1102 print_hang_task); 1103 struct net_device *netdev = adapter->netdev; 1104 struct e1000_ring *tx_ring = adapter->tx_ring; 1105 unsigned int i = tx_ring->next_to_clean; 1106 unsigned int eop = tx_ring->buffer_info[i].next_to_watch; 1107 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); 1108 struct e1000_hw *hw = &adapter->hw; 1109 u16 phy_status, phy_1000t_status, phy_ext_status; 1110 u16 pci_status; 1111 1112 if (test_bit(__E1000_DOWN, &adapter->state)) 1113 return; 1114 1115 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { 1116 /* May be block on write-back, flush and detect again 1117 * flush pending descriptor writebacks to memory 1118 */ 1119 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1120 /* execute the writes immediately */ 1121 e1e_flush(); 1122 /* Due to rare timing issues, write to TIDV again to ensure 1123 * the write is successful 1124 */ 1125 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1126 /* execute the writes immediately */ 1127 e1e_flush(); 1128 adapter->tx_hang_recheck = true; 1129 return; 1130 } 1131 adapter->tx_hang_recheck = false; 1132 1133 if (er32(TDH(0)) == er32(TDT(0))) { 1134 e_dbg("false hang detected, ignoring\n"); 1135 return; 1136 } 1137 1138 /* Real hang detected */ 1139 netif_stop_queue(netdev); 1140 1141 e1e_rphy(hw, MII_BMSR, &phy_status); 1142 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); 1143 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); 1144 1145 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); 1146 1147 /* detected Hardware unit hang */ 1148 e_err("Detected Hardware Unit Hang:\n" 1149 " TDH <%x>\n" 1150 " TDT <%x>\n" 1151 " next_to_use <%x>\n" 1152 " next_to_clean <%x>\n" 1153 "buffer_info[next_to_clean]:\n" 1154 " time_stamp <%lx>\n" 1155 " next_to_watch <%x>\n" 1156 " jiffies <%lx>\n" 1157 " next_to_watch.status <%x>\n" 1158 "MAC Status <%x>\n" 1159 "PHY Status <%x>\n" 1160 "PHY 1000BASE-T Status <%x>\n" 1161 "PHY Extended Status <%x>\n" 1162 "PCI Status <%x>\n", 1163 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, 1164 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, 1165 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), 1166 phy_status, phy_1000t_status, phy_ext_status, pci_status); 1167 1168 e1000e_dump(adapter); 1169 1170 /* Suggest workaround for known h/w issue */ 1171 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) 1172 e_err("Try turning off Tx pause (flow control) via ethtool\n"); 1173 } 1174 1175 /** 1176 * e1000e_tx_hwtstamp_work - check for Tx time stamp 1177 * @work: pointer to work struct 1178 * 1179 * This work function polls the TSYNCTXCTL valid bit to determine when a 1180 * timestamp has been taken for the current stored skb. The timestamp must 1181 * be for this skb because only one such packet is allowed in the queue. 1182 */ 1183 static void e1000e_tx_hwtstamp_work(struct work_struct *work) 1184 { 1185 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 1186 tx_hwtstamp_work); 1187 struct e1000_hw *hw = &adapter->hw; 1188 1189 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { 1190 struct sk_buff *skb = adapter->tx_hwtstamp_skb; 1191 struct skb_shared_hwtstamps shhwtstamps; 1192 u64 txstmp; 1193 1194 txstmp = er32(TXSTMPL); 1195 txstmp |= (u64)er32(TXSTMPH) << 32; 1196 1197 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); 1198 1199 /* Clear the global tx_hwtstamp_skb pointer and force writes 1200 * prior to notifying the stack of a Tx timestamp. 1201 */ 1202 adapter->tx_hwtstamp_skb = NULL; 1203 wmb(); /* force write prior to skb_tstamp_tx */ 1204 1205 skb_tstamp_tx(skb, &shhwtstamps); 1206 dev_consume_skb_any(skb); 1207 } else if (time_after(jiffies, adapter->tx_hwtstamp_start 1208 + adapter->tx_timeout_factor * HZ)) { 1209 dev_kfree_skb_any(adapter->tx_hwtstamp_skb); 1210 adapter->tx_hwtstamp_skb = NULL; 1211 adapter->tx_hwtstamp_timeouts++; 1212 e_warn("clearing Tx timestamp hang\n"); 1213 } else { 1214 /* reschedule to check later */ 1215 schedule_work(&adapter->tx_hwtstamp_work); 1216 } 1217 } 1218 1219 /** 1220 * e1000_clean_tx_irq - Reclaim resources after transmit completes 1221 * @tx_ring: Tx descriptor ring 1222 * 1223 * the return value indicates whether actual cleaning was done, there 1224 * is no guarantee that everything was cleaned 1225 **/ 1226 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) 1227 { 1228 struct e1000_adapter *adapter = tx_ring->adapter; 1229 struct net_device *netdev = adapter->netdev; 1230 struct e1000_hw *hw = &adapter->hw; 1231 struct e1000_tx_desc *tx_desc, *eop_desc; 1232 struct e1000_buffer *buffer_info; 1233 unsigned int i, eop; 1234 unsigned int count = 0; 1235 unsigned int total_tx_bytes = 0, total_tx_packets = 0; 1236 unsigned int bytes_compl = 0, pkts_compl = 0; 1237 1238 i = tx_ring->next_to_clean; 1239 eop = tx_ring->buffer_info[i].next_to_watch; 1240 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1241 1242 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && 1243 (count < tx_ring->count)) { 1244 bool cleaned = false; 1245 1246 dma_rmb(); /* read buffer_info after eop_desc */ 1247 for (; !cleaned; count++) { 1248 tx_desc = E1000_TX_DESC(*tx_ring, i); 1249 buffer_info = &tx_ring->buffer_info[i]; 1250 cleaned = (i == eop); 1251 1252 if (cleaned) { 1253 total_tx_packets += buffer_info->segs; 1254 total_tx_bytes += buffer_info->bytecount; 1255 if (buffer_info->skb) { 1256 bytes_compl += buffer_info->skb->len; 1257 pkts_compl++; 1258 } 1259 } 1260 1261 e1000_put_txbuf(tx_ring, buffer_info, false); 1262 tx_desc->upper.data = 0; 1263 1264 i++; 1265 if (i == tx_ring->count) 1266 i = 0; 1267 } 1268 1269 if (i == tx_ring->next_to_use) 1270 break; 1271 eop = tx_ring->buffer_info[i].next_to_watch; 1272 eop_desc = E1000_TX_DESC(*tx_ring, eop); 1273 } 1274 1275 tx_ring->next_to_clean = i; 1276 1277 netdev_completed_queue(netdev, pkts_compl, bytes_compl); 1278 1279 #define TX_WAKE_THRESHOLD 32 1280 if (count && netif_carrier_ok(netdev) && 1281 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { 1282 /* Make sure that anybody stopping the queue after this 1283 * sees the new next_to_clean. 1284 */ 1285 smp_mb(); 1286 1287 if (netif_queue_stopped(netdev) && 1288 !(test_bit(__E1000_DOWN, &adapter->state))) { 1289 netif_wake_queue(netdev); 1290 ++adapter->restart_queue; 1291 } 1292 } 1293 1294 if (adapter->detect_tx_hung) { 1295 /* Detect a transmit hang in hardware, this serializes the 1296 * check with the clearing of time_stamp and movement of i 1297 */ 1298 adapter->detect_tx_hung = false; 1299 if (tx_ring->buffer_info[i].time_stamp && 1300 time_after(jiffies, tx_ring->buffer_info[i].time_stamp 1301 + (adapter->tx_timeout_factor * HZ)) && 1302 !(er32(STATUS) & E1000_STATUS_TXOFF)) 1303 schedule_work(&adapter->print_hang_task); 1304 else 1305 adapter->tx_hang_recheck = false; 1306 } 1307 adapter->total_tx_bytes += total_tx_bytes; 1308 adapter->total_tx_packets += total_tx_packets; 1309 return count < tx_ring->count; 1310 } 1311 1312 /** 1313 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split 1314 * @rx_ring: Rx descriptor ring 1315 * 1316 * the return value indicates whether actual cleaning was done, there 1317 * is no guarantee that everything was cleaned 1318 **/ 1319 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, 1320 int work_to_do) 1321 { 1322 struct e1000_adapter *adapter = rx_ring->adapter; 1323 struct e1000_hw *hw = &adapter->hw; 1324 union e1000_rx_desc_packet_split *rx_desc, *next_rxd; 1325 struct net_device *netdev = adapter->netdev; 1326 struct pci_dev *pdev = adapter->pdev; 1327 struct e1000_buffer *buffer_info, *next_buffer; 1328 struct e1000_ps_page *ps_page; 1329 struct sk_buff *skb; 1330 unsigned int i, j; 1331 u32 length, staterr; 1332 int cleaned_count = 0; 1333 bool cleaned = false; 1334 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1335 1336 i = rx_ring->next_to_clean; 1337 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 1338 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1339 buffer_info = &rx_ring->buffer_info[i]; 1340 1341 while (staterr & E1000_RXD_STAT_DD) { 1342 if (*work_done >= work_to_do) 1343 break; 1344 (*work_done)++; 1345 skb = buffer_info->skb; 1346 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1347 1348 /* in the packet split case this is header only */ 1349 prefetch(skb->data - NET_IP_ALIGN); 1350 1351 i++; 1352 if (i == rx_ring->count) 1353 i = 0; 1354 next_rxd = E1000_RX_DESC_PS(*rx_ring, i); 1355 prefetch(next_rxd); 1356 1357 next_buffer = &rx_ring->buffer_info[i]; 1358 1359 cleaned = true; 1360 cleaned_count++; 1361 dma_unmap_single(&pdev->dev, buffer_info->dma, 1362 adapter->rx_ps_bsize0, DMA_FROM_DEVICE); 1363 buffer_info->dma = 0; 1364 1365 /* see !EOP comment in other Rx routine */ 1366 if (!(staterr & E1000_RXD_STAT_EOP)) 1367 adapter->flags2 |= FLAG2_IS_DISCARDING; 1368 1369 if (adapter->flags2 & FLAG2_IS_DISCARDING) { 1370 e_dbg("Packet Split buffers didn't pick up the full packet\n"); 1371 dev_kfree_skb_irq(skb); 1372 if (staterr & E1000_RXD_STAT_EOP) 1373 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1374 goto next_desc; 1375 } 1376 1377 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1378 !(netdev->features & NETIF_F_RXALL))) { 1379 dev_kfree_skb_irq(skb); 1380 goto next_desc; 1381 } 1382 1383 length = le16_to_cpu(rx_desc->wb.middle.length0); 1384 1385 if (!length) { 1386 e_dbg("Last part of the packet spanning multiple descriptors\n"); 1387 dev_kfree_skb_irq(skb); 1388 goto next_desc; 1389 } 1390 1391 /* Good Receive */ 1392 skb_put(skb, length); 1393 1394 { 1395 /* this looks ugly, but it seems compiler issues make 1396 * it more efficient than reusing j 1397 */ 1398 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1399 1400 /* page alloc/put takes too long and effects small 1401 * packet throughput, so unsplit small packets and 1402 * save the alloc/put only valid in softirq (napi) 1403 * context to call kmap_* 1404 */ 1405 if (l1 && (l1 <= copybreak) && 1406 ((length + l1) <= adapter->rx_ps_bsize0)) { 1407 u8 *vaddr; 1408 1409 ps_page = &buffer_info->ps_pages[0]; 1410 1411 /* there is no documentation about how to call 1412 * kmap_atomic, so we can't hold the mapping 1413 * very long 1414 */ 1415 dma_sync_single_for_cpu(&pdev->dev, 1416 ps_page->dma, 1417 PAGE_SIZE, 1418 DMA_FROM_DEVICE); 1419 vaddr = kmap_atomic(ps_page->page); 1420 memcpy(skb_tail_pointer(skb), vaddr, l1); 1421 kunmap_atomic(vaddr); 1422 dma_sync_single_for_device(&pdev->dev, 1423 ps_page->dma, 1424 PAGE_SIZE, 1425 DMA_FROM_DEVICE); 1426 1427 /* remove the CRC */ 1428 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1429 if (!(netdev->features & NETIF_F_RXFCS)) 1430 l1 -= 4; 1431 } 1432 1433 skb_put(skb, l1); 1434 goto copydone; 1435 } /* if */ 1436 } 1437 1438 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1439 length = le16_to_cpu(rx_desc->wb.upper.length[j]); 1440 if (!length) 1441 break; 1442 1443 ps_page = &buffer_info->ps_pages[j]; 1444 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1445 DMA_FROM_DEVICE); 1446 ps_page->dma = 0; 1447 skb_fill_page_desc(skb, j, ps_page->page, 0, length); 1448 ps_page->page = NULL; 1449 skb->len += length; 1450 skb->data_len += length; 1451 skb->truesize += PAGE_SIZE; 1452 } 1453 1454 /* strip the ethernet crc, problem is we're using pages now so 1455 * this whole operation can get a little cpu intensive 1456 */ 1457 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { 1458 if (!(netdev->features & NETIF_F_RXFCS)) 1459 pskb_trim(skb, skb->len - 4); 1460 } 1461 1462 copydone: 1463 total_rx_bytes += skb->len; 1464 total_rx_packets++; 1465 1466 e1000_rx_checksum(adapter, staterr, skb); 1467 1468 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1469 1470 if (rx_desc->wb.upper.header_status & 1471 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) 1472 adapter->rx_hdr_split++; 1473 1474 e1000_receive_skb(adapter, netdev, skb, staterr, 1475 rx_desc->wb.middle.vlan); 1476 1477 next_desc: 1478 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); 1479 buffer_info->skb = NULL; 1480 1481 /* return some buffers to hardware, one at a time is too slow */ 1482 if (cleaned_count >= E1000_RX_BUFFER_WRITE) { 1483 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1484 GFP_ATOMIC); 1485 cleaned_count = 0; 1486 } 1487 1488 /* use prefetched values */ 1489 rx_desc = next_rxd; 1490 buffer_info = next_buffer; 1491 1492 staterr = le32_to_cpu(rx_desc->wb.middle.status_error); 1493 } 1494 rx_ring->next_to_clean = i; 1495 1496 cleaned_count = e1000_desc_unused(rx_ring); 1497 if (cleaned_count) 1498 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1499 1500 adapter->total_rx_bytes += total_rx_bytes; 1501 adapter->total_rx_packets += total_rx_packets; 1502 return cleaned; 1503 } 1504 1505 /** 1506 * e1000_consume_page - helper function 1507 **/ 1508 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, 1509 u16 length) 1510 { 1511 bi->page = NULL; 1512 skb->len += length; 1513 skb->data_len += length; 1514 skb->truesize += PAGE_SIZE; 1515 } 1516 1517 /** 1518 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy 1519 * @adapter: board private structure 1520 * 1521 * the return value indicates whether actual cleaning was done, there 1522 * is no guarantee that everything was cleaned 1523 **/ 1524 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, 1525 int work_to_do) 1526 { 1527 struct e1000_adapter *adapter = rx_ring->adapter; 1528 struct net_device *netdev = adapter->netdev; 1529 struct pci_dev *pdev = adapter->pdev; 1530 union e1000_rx_desc_extended *rx_desc, *next_rxd; 1531 struct e1000_buffer *buffer_info, *next_buffer; 1532 u32 length, staterr; 1533 unsigned int i; 1534 int cleaned_count = 0; 1535 bool cleaned = false; 1536 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1537 struct skb_shared_info *shinfo; 1538 1539 i = rx_ring->next_to_clean; 1540 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); 1541 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1542 buffer_info = &rx_ring->buffer_info[i]; 1543 1544 while (staterr & E1000_RXD_STAT_DD) { 1545 struct sk_buff *skb; 1546 1547 if (*work_done >= work_to_do) 1548 break; 1549 (*work_done)++; 1550 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ 1551 1552 skb = buffer_info->skb; 1553 buffer_info->skb = NULL; 1554 1555 ++i; 1556 if (i == rx_ring->count) 1557 i = 0; 1558 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); 1559 prefetch(next_rxd); 1560 1561 next_buffer = &rx_ring->buffer_info[i]; 1562 1563 cleaned = true; 1564 cleaned_count++; 1565 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, 1566 DMA_FROM_DEVICE); 1567 buffer_info->dma = 0; 1568 1569 length = le16_to_cpu(rx_desc->wb.upper.length); 1570 1571 /* errors is only valid for DD + EOP descriptors */ 1572 if (unlikely((staterr & E1000_RXD_STAT_EOP) && 1573 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && 1574 !(netdev->features & NETIF_F_RXALL)))) { 1575 /* recycle both page and skb */ 1576 buffer_info->skb = skb; 1577 /* an error means any chain goes out the window too */ 1578 if (rx_ring->rx_skb_top) 1579 dev_kfree_skb_irq(rx_ring->rx_skb_top); 1580 rx_ring->rx_skb_top = NULL; 1581 goto next_desc; 1582 } 1583 #define rxtop (rx_ring->rx_skb_top) 1584 if (!(staterr & E1000_RXD_STAT_EOP)) { 1585 /* this descriptor is only the beginning (or middle) */ 1586 if (!rxtop) { 1587 /* this is the beginning of a chain */ 1588 rxtop = skb; 1589 skb_fill_page_desc(rxtop, 0, buffer_info->page, 1590 0, length); 1591 } else { 1592 /* this is the middle of a chain */ 1593 shinfo = skb_shinfo(rxtop); 1594 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1595 buffer_info->page, 0, 1596 length); 1597 /* re-use the skb, only consumed the page */ 1598 buffer_info->skb = skb; 1599 } 1600 e1000_consume_page(buffer_info, rxtop, length); 1601 goto next_desc; 1602 } else { 1603 if (rxtop) { 1604 /* end of the chain */ 1605 shinfo = skb_shinfo(rxtop); 1606 skb_fill_page_desc(rxtop, shinfo->nr_frags, 1607 buffer_info->page, 0, 1608 length); 1609 /* re-use the current skb, we only consumed the 1610 * page 1611 */ 1612 buffer_info->skb = skb; 1613 skb = rxtop; 1614 rxtop = NULL; 1615 e1000_consume_page(buffer_info, skb, length); 1616 } else { 1617 /* no chain, got EOP, this buf is the packet 1618 * copybreak to save the put_page/alloc_page 1619 */ 1620 if (length <= copybreak && 1621 skb_tailroom(skb) >= length) { 1622 u8 *vaddr; 1623 vaddr = kmap_atomic(buffer_info->page); 1624 memcpy(skb_tail_pointer(skb), vaddr, 1625 length); 1626 kunmap_atomic(vaddr); 1627 /* re-use the page, so don't erase 1628 * buffer_info->page 1629 */ 1630 skb_put(skb, length); 1631 } else { 1632 skb_fill_page_desc(skb, 0, 1633 buffer_info->page, 0, 1634 length); 1635 e1000_consume_page(buffer_info, skb, 1636 length); 1637 } 1638 } 1639 } 1640 1641 /* Receive Checksum Offload */ 1642 e1000_rx_checksum(adapter, staterr, skb); 1643 1644 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); 1645 1646 /* probably a little skewed due to removing CRC */ 1647 total_rx_bytes += skb->len; 1648 total_rx_packets++; 1649 1650 /* eth type trans needs skb->data to point to something */ 1651 if (!pskb_may_pull(skb, ETH_HLEN)) { 1652 e_err("pskb_may_pull failed.\n"); 1653 dev_kfree_skb_irq(skb); 1654 goto next_desc; 1655 } 1656 1657 e1000_receive_skb(adapter, netdev, skb, staterr, 1658 rx_desc->wb.upper.vlan); 1659 1660 next_desc: 1661 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); 1662 1663 /* return some buffers to hardware, one at a time is too slow */ 1664 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { 1665 adapter->alloc_rx_buf(rx_ring, cleaned_count, 1666 GFP_ATOMIC); 1667 cleaned_count = 0; 1668 } 1669 1670 /* use prefetched values */ 1671 rx_desc = next_rxd; 1672 buffer_info = next_buffer; 1673 1674 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 1675 } 1676 rx_ring->next_to_clean = i; 1677 1678 cleaned_count = e1000_desc_unused(rx_ring); 1679 if (cleaned_count) 1680 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); 1681 1682 adapter->total_rx_bytes += total_rx_bytes; 1683 adapter->total_rx_packets += total_rx_packets; 1684 return cleaned; 1685 } 1686 1687 /** 1688 * e1000_clean_rx_ring - Free Rx Buffers per Queue 1689 * @rx_ring: Rx descriptor ring 1690 **/ 1691 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) 1692 { 1693 struct e1000_adapter *adapter = rx_ring->adapter; 1694 struct e1000_buffer *buffer_info; 1695 struct e1000_ps_page *ps_page; 1696 struct pci_dev *pdev = adapter->pdev; 1697 unsigned int i, j; 1698 1699 /* Free all the Rx ring sk_buffs */ 1700 for (i = 0; i < rx_ring->count; i++) { 1701 buffer_info = &rx_ring->buffer_info[i]; 1702 if (buffer_info->dma) { 1703 if (adapter->clean_rx == e1000_clean_rx_irq) 1704 dma_unmap_single(&pdev->dev, buffer_info->dma, 1705 adapter->rx_buffer_len, 1706 DMA_FROM_DEVICE); 1707 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) 1708 dma_unmap_page(&pdev->dev, buffer_info->dma, 1709 PAGE_SIZE, DMA_FROM_DEVICE); 1710 else if (adapter->clean_rx == e1000_clean_rx_irq_ps) 1711 dma_unmap_single(&pdev->dev, buffer_info->dma, 1712 adapter->rx_ps_bsize0, 1713 DMA_FROM_DEVICE); 1714 buffer_info->dma = 0; 1715 } 1716 1717 if (buffer_info->page) { 1718 put_page(buffer_info->page); 1719 buffer_info->page = NULL; 1720 } 1721 1722 if (buffer_info->skb) { 1723 dev_kfree_skb(buffer_info->skb); 1724 buffer_info->skb = NULL; 1725 } 1726 1727 for (j = 0; j < PS_PAGE_BUFFERS; j++) { 1728 ps_page = &buffer_info->ps_pages[j]; 1729 if (!ps_page->page) 1730 break; 1731 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, 1732 DMA_FROM_DEVICE); 1733 ps_page->dma = 0; 1734 put_page(ps_page->page); 1735 ps_page->page = NULL; 1736 } 1737 } 1738 1739 /* there also may be some cached data from a chained receive */ 1740 if (rx_ring->rx_skb_top) { 1741 dev_kfree_skb(rx_ring->rx_skb_top); 1742 rx_ring->rx_skb_top = NULL; 1743 } 1744 1745 /* Zero out the descriptor ring */ 1746 memset(rx_ring->desc, 0, rx_ring->size); 1747 1748 rx_ring->next_to_clean = 0; 1749 rx_ring->next_to_use = 0; 1750 adapter->flags2 &= ~FLAG2_IS_DISCARDING; 1751 } 1752 1753 static void e1000e_downshift_workaround(struct work_struct *work) 1754 { 1755 struct e1000_adapter *adapter = container_of(work, 1756 struct e1000_adapter, 1757 downshift_task); 1758 1759 if (test_bit(__E1000_DOWN, &adapter->state)) 1760 return; 1761 1762 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); 1763 } 1764 1765 /** 1766 * e1000_intr_msi - Interrupt Handler 1767 * @irq: interrupt number 1768 * @data: pointer to a network interface device structure 1769 **/ 1770 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) 1771 { 1772 struct net_device *netdev = data; 1773 struct e1000_adapter *adapter = netdev_priv(netdev); 1774 struct e1000_hw *hw = &adapter->hw; 1775 u32 icr = er32(ICR); 1776 1777 /* read ICR disables interrupts using IAM */ 1778 if (icr & E1000_ICR_LSC) { 1779 hw->mac.get_link_status = true; 1780 /* ICH8 workaround-- Call gig speed drop workaround on cable 1781 * disconnect (LSC) before accessing any PHY registers 1782 */ 1783 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1784 (!(er32(STATUS) & E1000_STATUS_LU))) 1785 schedule_work(&adapter->downshift_task); 1786 1787 /* 80003ES2LAN workaround-- For packet buffer work-around on 1788 * link down event; disable receives here in the ISR and reset 1789 * adapter in watchdog 1790 */ 1791 if (netif_carrier_ok(netdev) && 1792 adapter->flags & FLAG_RX_NEEDS_RESTART) { 1793 /* disable receives */ 1794 u32 rctl = er32(RCTL); 1795 1796 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1797 adapter->flags |= FLAG_RESTART_NOW; 1798 } 1799 /* guard against interrupt when we're going down */ 1800 if (!test_bit(__E1000_DOWN, &adapter->state)) 1801 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1802 } 1803 1804 /* Reset on uncorrectable ECC error */ 1805 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1806 u32 pbeccsts = er32(PBECCSTS); 1807 1808 adapter->corr_errors += 1809 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1810 adapter->uncorr_errors += 1811 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1812 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1813 1814 /* Do the reset outside of interrupt context */ 1815 schedule_work(&adapter->reset_task); 1816 1817 /* return immediately since reset is imminent */ 1818 return IRQ_HANDLED; 1819 } 1820 1821 if (napi_schedule_prep(&adapter->napi)) { 1822 adapter->total_tx_bytes = 0; 1823 adapter->total_tx_packets = 0; 1824 adapter->total_rx_bytes = 0; 1825 adapter->total_rx_packets = 0; 1826 __napi_schedule(&adapter->napi); 1827 } 1828 1829 return IRQ_HANDLED; 1830 } 1831 1832 /** 1833 * e1000_intr - Interrupt Handler 1834 * @irq: interrupt number 1835 * @data: pointer to a network interface device structure 1836 **/ 1837 static irqreturn_t e1000_intr(int __always_unused irq, void *data) 1838 { 1839 struct net_device *netdev = data; 1840 struct e1000_adapter *adapter = netdev_priv(netdev); 1841 struct e1000_hw *hw = &adapter->hw; 1842 u32 rctl, icr = er32(ICR); 1843 1844 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1845 return IRQ_NONE; /* Not our interrupt */ 1846 1847 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 1848 * not set, then the adapter didn't send an interrupt 1849 */ 1850 if (!(icr & E1000_ICR_INT_ASSERTED)) 1851 return IRQ_NONE; 1852 1853 /* Interrupt Auto-Mask...upon reading ICR, 1854 * interrupts are masked. No need for the 1855 * IMC write 1856 */ 1857 1858 if (icr & E1000_ICR_LSC) { 1859 hw->mac.get_link_status = true; 1860 /* ICH8 workaround-- Call gig speed drop workaround on cable 1861 * disconnect (LSC) before accessing any PHY registers 1862 */ 1863 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1864 (!(er32(STATUS) & E1000_STATUS_LU))) 1865 schedule_work(&adapter->downshift_task); 1866 1867 /* 80003ES2LAN workaround-- 1868 * For packet buffer work-around on link down event; 1869 * disable receives here in the ISR and 1870 * reset adapter in watchdog 1871 */ 1872 if (netif_carrier_ok(netdev) && 1873 (adapter->flags & FLAG_RX_NEEDS_RESTART)) { 1874 /* disable receives */ 1875 rctl = er32(RCTL); 1876 ew32(RCTL, rctl & ~E1000_RCTL_EN); 1877 adapter->flags |= FLAG_RESTART_NOW; 1878 } 1879 /* guard against interrupt when we're going down */ 1880 if (!test_bit(__E1000_DOWN, &adapter->state)) 1881 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1882 } 1883 1884 /* Reset on uncorrectable ECC error */ 1885 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { 1886 u32 pbeccsts = er32(PBECCSTS); 1887 1888 adapter->corr_errors += 1889 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1890 adapter->uncorr_errors += 1891 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1892 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1893 1894 /* Do the reset outside of interrupt context */ 1895 schedule_work(&adapter->reset_task); 1896 1897 /* return immediately since reset is imminent */ 1898 return IRQ_HANDLED; 1899 } 1900 1901 if (napi_schedule_prep(&adapter->napi)) { 1902 adapter->total_tx_bytes = 0; 1903 adapter->total_tx_packets = 0; 1904 adapter->total_rx_bytes = 0; 1905 adapter->total_rx_packets = 0; 1906 __napi_schedule(&adapter->napi); 1907 } 1908 1909 return IRQ_HANDLED; 1910 } 1911 1912 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) 1913 { 1914 struct net_device *netdev = data; 1915 struct e1000_adapter *adapter = netdev_priv(netdev); 1916 struct e1000_hw *hw = &adapter->hw; 1917 u32 icr; 1918 bool enable = true; 1919 1920 icr = er32(ICR); 1921 if (icr & E1000_ICR_RXO) { 1922 ew32(ICR, E1000_ICR_RXO); 1923 enable = false; 1924 /* napi poll will re-enable Other, make sure it runs */ 1925 if (napi_schedule_prep(&adapter->napi)) { 1926 adapter->total_rx_bytes = 0; 1927 adapter->total_rx_packets = 0; 1928 __napi_schedule(&adapter->napi); 1929 } 1930 } 1931 if (icr & E1000_ICR_LSC) { 1932 ew32(ICR, E1000_ICR_LSC); 1933 hw->mac.get_link_status = true; 1934 /* guard against interrupt when we're going down */ 1935 if (!test_bit(__E1000_DOWN, &adapter->state)) 1936 mod_timer(&adapter->watchdog_timer, jiffies + 1); 1937 } 1938 1939 if (enable && !test_bit(__E1000_DOWN, &adapter->state)) 1940 ew32(IMS, E1000_IMS_OTHER); 1941 1942 return IRQ_HANDLED; 1943 } 1944 1945 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) 1946 { 1947 struct net_device *netdev = data; 1948 struct e1000_adapter *adapter = netdev_priv(netdev); 1949 struct e1000_hw *hw = &adapter->hw; 1950 struct e1000_ring *tx_ring = adapter->tx_ring; 1951 1952 adapter->total_tx_bytes = 0; 1953 adapter->total_tx_packets = 0; 1954 1955 if (!e1000_clean_tx_irq(tx_ring)) 1956 /* Ring was not completely cleaned, so fire another interrupt */ 1957 ew32(ICS, tx_ring->ims_val); 1958 1959 if (!test_bit(__E1000_DOWN, &adapter->state)) 1960 ew32(IMS, adapter->tx_ring->ims_val); 1961 1962 return IRQ_HANDLED; 1963 } 1964 1965 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) 1966 { 1967 struct net_device *netdev = data; 1968 struct e1000_adapter *adapter = netdev_priv(netdev); 1969 struct e1000_ring *rx_ring = adapter->rx_ring; 1970 1971 /* Write the ITR value calculated at the end of the 1972 * previous interrupt. 1973 */ 1974 if (rx_ring->set_itr) { 1975 u32 itr = rx_ring->itr_val ? 1976 1000000000 / (rx_ring->itr_val * 256) : 0; 1977 1978 writel(itr, rx_ring->itr_register); 1979 rx_ring->set_itr = 0; 1980 } 1981 1982 if (napi_schedule_prep(&adapter->napi)) { 1983 adapter->total_rx_bytes = 0; 1984 adapter->total_rx_packets = 0; 1985 __napi_schedule(&adapter->napi); 1986 } 1987 return IRQ_HANDLED; 1988 } 1989 1990 /** 1991 * e1000_configure_msix - Configure MSI-X hardware 1992 * 1993 * e1000_configure_msix sets up the hardware to properly 1994 * generate MSI-X interrupts. 1995 **/ 1996 static void e1000_configure_msix(struct e1000_adapter *adapter) 1997 { 1998 struct e1000_hw *hw = &adapter->hw; 1999 struct e1000_ring *rx_ring = adapter->rx_ring; 2000 struct e1000_ring *tx_ring = adapter->tx_ring; 2001 int vector = 0; 2002 u32 ctrl_ext, ivar = 0; 2003 2004 adapter->eiac_mask = 0; 2005 2006 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ 2007 if (hw->mac.type == e1000_82574) { 2008 u32 rfctl = er32(RFCTL); 2009 2010 rfctl |= E1000_RFCTL_ACK_DIS; 2011 ew32(RFCTL, rfctl); 2012 } 2013 2014 /* Configure Rx vector */ 2015 rx_ring->ims_val = E1000_IMS_RXQ0; 2016 adapter->eiac_mask |= rx_ring->ims_val; 2017 if (rx_ring->itr_val) 2018 writel(1000000000 / (rx_ring->itr_val * 256), 2019 rx_ring->itr_register); 2020 else 2021 writel(1, rx_ring->itr_register); 2022 ivar = E1000_IVAR_INT_ALLOC_VALID | vector; 2023 2024 /* Configure Tx vector */ 2025 tx_ring->ims_val = E1000_IMS_TXQ0; 2026 vector++; 2027 if (tx_ring->itr_val) 2028 writel(1000000000 / (tx_ring->itr_val * 256), 2029 tx_ring->itr_register); 2030 else 2031 writel(1, tx_ring->itr_register); 2032 adapter->eiac_mask |= tx_ring->ims_val; 2033 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); 2034 2035 /* set vector for Other Causes, e.g. link changes */ 2036 vector++; 2037 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); 2038 if (rx_ring->itr_val) 2039 writel(1000000000 / (rx_ring->itr_val * 256), 2040 hw->hw_addr + E1000_EITR_82574(vector)); 2041 else 2042 writel(1, hw->hw_addr + E1000_EITR_82574(vector)); 2043 adapter->eiac_mask |= E1000_IMS_OTHER; 2044 2045 /* Cause Tx interrupts on every write back */ 2046 ivar |= BIT(31); 2047 2048 ew32(IVAR, ivar); 2049 2050 /* enable MSI-X PBA support */ 2051 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; 2052 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; 2053 ew32(CTRL_EXT, ctrl_ext); 2054 e1e_flush(); 2055 } 2056 2057 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) 2058 { 2059 if (adapter->msix_entries) { 2060 pci_disable_msix(adapter->pdev); 2061 kfree(adapter->msix_entries); 2062 adapter->msix_entries = NULL; 2063 } else if (adapter->flags & FLAG_MSI_ENABLED) { 2064 pci_disable_msi(adapter->pdev); 2065 adapter->flags &= ~FLAG_MSI_ENABLED; 2066 } 2067 } 2068 2069 /** 2070 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported 2071 * 2072 * Attempt to configure interrupts using the best available 2073 * capabilities of the hardware and kernel. 2074 **/ 2075 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) 2076 { 2077 int err; 2078 int i; 2079 2080 switch (adapter->int_mode) { 2081 case E1000E_INT_MODE_MSIX: 2082 if (adapter->flags & FLAG_HAS_MSIX) { 2083 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ 2084 adapter->msix_entries = kcalloc(adapter->num_vectors, 2085 sizeof(struct 2086 msix_entry), 2087 GFP_KERNEL); 2088 if (adapter->msix_entries) { 2089 struct e1000_adapter *a = adapter; 2090 2091 for (i = 0; i < adapter->num_vectors; i++) 2092 adapter->msix_entries[i].entry = i; 2093 2094 err = pci_enable_msix_range(a->pdev, 2095 a->msix_entries, 2096 a->num_vectors, 2097 a->num_vectors); 2098 if (err > 0) 2099 return; 2100 } 2101 /* MSI-X failed, so fall through and try MSI */ 2102 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); 2103 e1000e_reset_interrupt_capability(adapter); 2104 } 2105 adapter->int_mode = E1000E_INT_MODE_MSI; 2106 /* Fall through */ 2107 case E1000E_INT_MODE_MSI: 2108 if (!pci_enable_msi(adapter->pdev)) { 2109 adapter->flags |= FLAG_MSI_ENABLED; 2110 } else { 2111 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2112 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); 2113 } 2114 /* Fall through */ 2115 case E1000E_INT_MODE_LEGACY: 2116 /* Don't do anything; this is the system default */ 2117 break; 2118 } 2119 2120 /* store the number of vectors being used */ 2121 adapter->num_vectors = 1; 2122 } 2123 2124 /** 2125 * e1000_request_msix - Initialize MSI-X interrupts 2126 * 2127 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the 2128 * kernel. 2129 **/ 2130 static int e1000_request_msix(struct e1000_adapter *adapter) 2131 { 2132 struct net_device *netdev = adapter->netdev; 2133 int err = 0, vector = 0; 2134 2135 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2136 snprintf(adapter->rx_ring->name, 2137 sizeof(adapter->rx_ring->name) - 1, 2138 "%s-rx-0", netdev->name); 2139 else 2140 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 2141 err = request_irq(adapter->msix_entries[vector].vector, 2142 e1000_intr_msix_rx, 0, adapter->rx_ring->name, 2143 netdev); 2144 if (err) 2145 return err; 2146 adapter->rx_ring->itr_register = adapter->hw.hw_addr + 2147 E1000_EITR_82574(vector); 2148 adapter->rx_ring->itr_val = adapter->itr; 2149 vector++; 2150 2151 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 2152 snprintf(adapter->tx_ring->name, 2153 sizeof(adapter->tx_ring->name) - 1, 2154 "%s-tx-0", netdev->name); 2155 else 2156 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 2157 err = request_irq(adapter->msix_entries[vector].vector, 2158 e1000_intr_msix_tx, 0, adapter->tx_ring->name, 2159 netdev); 2160 if (err) 2161 return err; 2162 adapter->tx_ring->itr_register = adapter->hw.hw_addr + 2163 E1000_EITR_82574(vector); 2164 adapter->tx_ring->itr_val = adapter->itr; 2165 vector++; 2166 2167 err = request_irq(adapter->msix_entries[vector].vector, 2168 e1000_msix_other, 0, netdev->name, netdev); 2169 if (err) 2170 return err; 2171 2172 e1000_configure_msix(adapter); 2173 2174 return 0; 2175 } 2176 2177 /** 2178 * e1000_request_irq - initialize interrupts 2179 * 2180 * Attempts to configure interrupts using the best available 2181 * capabilities of the hardware and kernel. 2182 **/ 2183 static int e1000_request_irq(struct e1000_adapter *adapter) 2184 { 2185 struct net_device *netdev = adapter->netdev; 2186 int err; 2187 2188 if (adapter->msix_entries) { 2189 err = e1000_request_msix(adapter); 2190 if (!err) 2191 return err; 2192 /* fall back to MSI */ 2193 e1000e_reset_interrupt_capability(adapter); 2194 adapter->int_mode = E1000E_INT_MODE_MSI; 2195 e1000e_set_interrupt_capability(adapter); 2196 } 2197 if (adapter->flags & FLAG_MSI_ENABLED) { 2198 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, 2199 netdev->name, netdev); 2200 if (!err) 2201 return err; 2202 2203 /* fall back to legacy interrupt */ 2204 e1000e_reset_interrupt_capability(adapter); 2205 adapter->int_mode = E1000E_INT_MODE_LEGACY; 2206 } 2207 2208 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, 2209 netdev->name, netdev); 2210 if (err) 2211 e_err("Unable to allocate interrupt, Error: %d\n", err); 2212 2213 return err; 2214 } 2215 2216 static void e1000_free_irq(struct e1000_adapter *adapter) 2217 { 2218 struct net_device *netdev = adapter->netdev; 2219 2220 if (adapter->msix_entries) { 2221 int vector = 0; 2222 2223 free_irq(adapter->msix_entries[vector].vector, netdev); 2224 vector++; 2225 2226 free_irq(adapter->msix_entries[vector].vector, netdev); 2227 vector++; 2228 2229 /* Other Causes interrupt vector */ 2230 free_irq(adapter->msix_entries[vector].vector, netdev); 2231 return; 2232 } 2233 2234 free_irq(adapter->pdev->irq, netdev); 2235 } 2236 2237 /** 2238 * e1000_irq_disable - Mask off interrupt generation on the NIC 2239 **/ 2240 static void e1000_irq_disable(struct e1000_adapter *adapter) 2241 { 2242 struct e1000_hw *hw = &adapter->hw; 2243 2244 ew32(IMC, ~0); 2245 if (adapter->msix_entries) 2246 ew32(EIAC_82574, 0); 2247 e1e_flush(); 2248 2249 if (adapter->msix_entries) { 2250 int i; 2251 2252 for (i = 0; i < adapter->num_vectors; i++) 2253 synchronize_irq(adapter->msix_entries[i].vector); 2254 } else { 2255 synchronize_irq(adapter->pdev->irq); 2256 } 2257 } 2258 2259 /** 2260 * e1000_irq_enable - Enable default interrupt generation settings 2261 **/ 2262 static void e1000_irq_enable(struct e1000_adapter *adapter) 2263 { 2264 struct e1000_hw *hw = &adapter->hw; 2265 2266 if (adapter->msix_entries) { 2267 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); 2268 ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC); 2269 } else if (hw->mac.type >= e1000_pch_lpt) { 2270 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); 2271 } else { 2272 ew32(IMS, IMS_ENABLE_MASK); 2273 } 2274 e1e_flush(); 2275 } 2276 2277 /** 2278 * e1000e_get_hw_control - get control of the h/w from f/w 2279 * @adapter: address of board private structure 2280 * 2281 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2282 * For ASF and Pass Through versions of f/w this means that 2283 * the driver is loaded. For AMT version (only with 82573) 2284 * of the f/w this means that the network i/f is open. 2285 **/ 2286 void e1000e_get_hw_control(struct e1000_adapter *adapter) 2287 { 2288 struct e1000_hw *hw = &adapter->hw; 2289 u32 ctrl_ext; 2290 u32 swsm; 2291 2292 /* Let firmware know the driver has taken over */ 2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2294 swsm = er32(SWSM); 2295 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); 2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2297 ctrl_ext = er32(CTRL_EXT); 2298 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 2299 } 2300 } 2301 2302 /** 2303 * e1000e_release_hw_control - release control of the h/w to f/w 2304 * @adapter: address of board private structure 2305 * 2306 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. 2307 * For ASF and Pass Through versions of f/w this means that the 2308 * driver is no longer loaded. For AMT version (only with 82573) i 2309 * of the f/w this means that the network i/f is closed. 2310 * 2311 **/ 2312 void e1000e_release_hw_control(struct e1000_adapter *adapter) 2313 { 2314 struct e1000_hw *hw = &adapter->hw; 2315 u32 ctrl_ext; 2316 u32 swsm; 2317 2318 /* Let firmware taken over control of h/w */ 2319 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { 2320 swsm = er32(SWSM); 2321 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 2322 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { 2323 ctrl_ext = er32(CTRL_EXT); 2324 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 2325 } 2326 } 2327 2328 /** 2329 * e1000_alloc_ring_dma - allocate memory for a ring structure 2330 **/ 2331 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, 2332 struct e1000_ring *ring) 2333 { 2334 struct pci_dev *pdev = adapter->pdev; 2335 2336 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma, 2337 GFP_KERNEL); 2338 if (!ring->desc) 2339 return -ENOMEM; 2340 2341 return 0; 2342 } 2343 2344 /** 2345 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) 2346 * @tx_ring: Tx descriptor ring 2347 * 2348 * Return 0 on success, negative on failure 2349 **/ 2350 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) 2351 { 2352 struct e1000_adapter *adapter = tx_ring->adapter; 2353 int err = -ENOMEM, size; 2354 2355 size = sizeof(struct e1000_buffer) * tx_ring->count; 2356 tx_ring->buffer_info = vzalloc(size); 2357 if (!tx_ring->buffer_info) 2358 goto err; 2359 2360 /* round up to nearest 4K */ 2361 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); 2362 tx_ring->size = ALIGN(tx_ring->size, 4096); 2363 2364 err = e1000_alloc_ring_dma(adapter, tx_ring); 2365 if (err) 2366 goto err; 2367 2368 tx_ring->next_to_use = 0; 2369 tx_ring->next_to_clean = 0; 2370 2371 return 0; 2372 err: 2373 vfree(tx_ring->buffer_info); 2374 e_err("Unable to allocate memory for the transmit descriptor ring\n"); 2375 return err; 2376 } 2377 2378 /** 2379 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) 2380 * @rx_ring: Rx descriptor ring 2381 * 2382 * Returns 0 on success, negative on failure 2383 **/ 2384 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) 2385 { 2386 struct e1000_adapter *adapter = rx_ring->adapter; 2387 struct e1000_buffer *buffer_info; 2388 int i, size, desc_len, err = -ENOMEM; 2389 2390 size = sizeof(struct e1000_buffer) * rx_ring->count; 2391 rx_ring->buffer_info = vzalloc(size); 2392 if (!rx_ring->buffer_info) 2393 goto err; 2394 2395 for (i = 0; i < rx_ring->count; i++) { 2396 buffer_info = &rx_ring->buffer_info[i]; 2397 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, 2398 sizeof(struct e1000_ps_page), 2399 GFP_KERNEL); 2400 if (!buffer_info->ps_pages) 2401 goto err_pages; 2402 } 2403 2404 desc_len = sizeof(union e1000_rx_desc_packet_split); 2405 2406 /* Round up to nearest 4K */ 2407 rx_ring->size = rx_ring->count * desc_len; 2408 rx_ring->size = ALIGN(rx_ring->size, 4096); 2409 2410 err = e1000_alloc_ring_dma(adapter, rx_ring); 2411 if (err) 2412 goto err_pages; 2413 2414 rx_ring->next_to_clean = 0; 2415 rx_ring->next_to_use = 0; 2416 rx_ring->rx_skb_top = NULL; 2417 2418 return 0; 2419 2420 err_pages: 2421 for (i = 0; i < rx_ring->count; i++) { 2422 buffer_info = &rx_ring->buffer_info[i]; 2423 kfree(buffer_info->ps_pages); 2424 } 2425 err: 2426 vfree(rx_ring->buffer_info); 2427 e_err("Unable to allocate memory for the receive descriptor ring\n"); 2428 return err; 2429 } 2430 2431 /** 2432 * e1000_clean_tx_ring - Free Tx Buffers 2433 * @tx_ring: Tx descriptor ring 2434 **/ 2435 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) 2436 { 2437 struct e1000_adapter *adapter = tx_ring->adapter; 2438 struct e1000_buffer *buffer_info; 2439 unsigned long size; 2440 unsigned int i; 2441 2442 for (i = 0; i < tx_ring->count; i++) { 2443 buffer_info = &tx_ring->buffer_info[i]; 2444 e1000_put_txbuf(tx_ring, buffer_info, false); 2445 } 2446 2447 netdev_reset_queue(adapter->netdev); 2448 size = sizeof(struct e1000_buffer) * tx_ring->count; 2449 memset(tx_ring->buffer_info, 0, size); 2450 2451 memset(tx_ring->desc, 0, tx_ring->size); 2452 2453 tx_ring->next_to_use = 0; 2454 tx_ring->next_to_clean = 0; 2455 } 2456 2457 /** 2458 * e1000e_free_tx_resources - Free Tx Resources per Queue 2459 * @tx_ring: Tx descriptor ring 2460 * 2461 * Free all transmit software resources 2462 **/ 2463 void e1000e_free_tx_resources(struct e1000_ring *tx_ring) 2464 { 2465 struct e1000_adapter *adapter = tx_ring->adapter; 2466 struct pci_dev *pdev = adapter->pdev; 2467 2468 e1000_clean_tx_ring(tx_ring); 2469 2470 vfree(tx_ring->buffer_info); 2471 tx_ring->buffer_info = NULL; 2472 2473 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 2474 tx_ring->dma); 2475 tx_ring->desc = NULL; 2476 } 2477 2478 /** 2479 * e1000e_free_rx_resources - Free Rx Resources 2480 * @rx_ring: Rx descriptor ring 2481 * 2482 * Free all receive software resources 2483 **/ 2484 void e1000e_free_rx_resources(struct e1000_ring *rx_ring) 2485 { 2486 struct e1000_adapter *adapter = rx_ring->adapter; 2487 struct pci_dev *pdev = adapter->pdev; 2488 int i; 2489 2490 e1000_clean_rx_ring(rx_ring); 2491 2492 for (i = 0; i < rx_ring->count; i++) 2493 kfree(rx_ring->buffer_info[i].ps_pages); 2494 2495 vfree(rx_ring->buffer_info); 2496 rx_ring->buffer_info = NULL; 2497 2498 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 2499 rx_ring->dma); 2500 rx_ring->desc = NULL; 2501 } 2502 2503 /** 2504 * e1000_update_itr - update the dynamic ITR value based on statistics 2505 * @adapter: pointer to adapter 2506 * @itr_setting: current adapter->itr 2507 * @packets: the number of packets during this measurement interval 2508 * @bytes: the number of bytes during this measurement interval 2509 * 2510 * Stores a new ITR value based on packets and byte 2511 * counts during the last interrupt. The advantage of per interrupt 2512 * computation is faster updates and more accurate ITR for the current 2513 * traffic pattern. Constants in this function were computed 2514 * based on theoretical maximum wire speed and thresholds were set based 2515 * on testing data as well as attempting to minimize response time 2516 * while increasing bulk throughput. This functionality is controlled 2517 * by the InterruptThrottleRate module parameter. 2518 **/ 2519 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) 2520 { 2521 unsigned int retval = itr_setting; 2522 2523 if (packets == 0) 2524 return itr_setting; 2525 2526 switch (itr_setting) { 2527 case lowest_latency: 2528 /* handle TSO and jumbo frames */ 2529 if (bytes / packets > 8000) 2530 retval = bulk_latency; 2531 else if ((packets < 5) && (bytes > 512)) 2532 retval = low_latency; 2533 break; 2534 case low_latency: /* 50 usec aka 20000 ints/s */ 2535 if (bytes > 10000) { 2536 /* this if handles the TSO accounting */ 2537 if (bytes / packets > 8000) 2538 retval = bulk_latency; 2539 else if ((packets < 10) || ((bytes / packets) > 1200)) 2540 retval = bulk_latency; 2541 else if ((packets > 35)) 2542 retval = lowest_latency; 2543 } else if (bytes / packets > 2000) { 2544 retval = bulk_latency; 2545 } else if (packets <= 2 && bytes < 512) { 2546 retval = lowest_latency; 2547 } 2548 break; 2549 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2550 if (bytes > 25000) { 2551 if (packets > 35) 2552 retval = low_latency; 2553 } else if (bytes < 6000) { 2554 retval = low_latency; 2555 } 2556 break; 2557 } 2558 2559 return retval; 2560 } 2561 2562 static void e1000_set_itr(struct e1000_adapter *adapter) 2563 { 2564 u16 current_itr; 2565 u32 new_itr = adapter->itr; 2566 2567 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2568 if (adapter->link_speed != SPEED_1000) { 2569 current_itr = 0; 2570 new_itr = 4000; 2571 goto set_itr_now; 2572 } 2573 2574 if (adapter->flags2 & FLAG2_DISABLE_AIM) { 2575 new_itr = 0; 2576 goto set_itr_now; 2577 } 2578 2579 adapter->tx_itr = e1000_update_itr(adapter->tx_itr, 2580 adapter->total_tx_packets, 2581 adapter->total_tx_bytes); 2582 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2583 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) 2584 adapter->tx_itr = low_latency; 2585 2586 adapter->rx_itr = e1000_update_itr(adapter->rx_itr, 2587 adapter->total_rx_packets, 2588 adapter->total_rx_bytes); 2589 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2590 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) 2591 adapter->rx_itr = low_latency; 2592 2593 current_itr = max(adapter->rx_itr, adapter->tx_itr); 2594 2595 /* counts and packets in update_itr are dependent on these numbers */ 2596 switch (current_itr) { 2597 case lowest_latency: 2598 new_itr = 70000; 2599 break; 2600 case low_latency: 2601 new_itr = 20000; /* aka hwitr = ~200 */ 2602 break; 2603 case bulk_latency: 2604 new_itr = 4000; 2605 break; 2606 default: 2607 break; 2608 } 2609 2610 set_itr_now: 2611 if (new_itr != adapter->itr) { 2612 /* this attempts to bias the interrupt rate towards Bulk 2613 * by adding intermediate steps when interrupt rate is 2614 * increasing 2615 */ 2616 new_itr = new_itr > adapter->itr ? 2617 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; 2618 adapter->itr = new_itr; 2619 adapter->rx_ring->itr_val = new_itr; 2620 if (adapter->msix_entries) 2621 adapter->rx_ring->set_itr = 1; 2622 else 2623 e1000e_write_itr(adapter, new_itr); 2624 } 2625 } 2626 2627 /** 2628 * e1000e_write_itr - write the ITR value to the appropriate registers 2629 * @adapter: address of board private structure 2630 * @itr: new ITR value to program 2631 * 2632 * e1000e_write_itr determines if the adapter is in MSI-X mode 2633 * and, if so, writes the EITR registers with the ITR value. 2634 * Otherwise, it writes the ITR value into the ITR register. 2635 **/ 2636 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) 2637 { 2638 struct e1000_hw *hw = &adapter->hw; 2639 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; 2640 2641 if (adapter->msix_entries) { 2642 int vector; 2643 2644 for (vector = 0; vector < adapter->num_vectors; vector++) 2645 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); 2646 } else { 2647 ew32(ITR, new_itr); 2648 } 2649 } 2650 2651 /** 2652 * e1000_alloc_queues - Allocate memory for all rings 2653 * @adapter: board private structure to initialize 2654 **/ 2655 static int e1000_alloc_queues(struct e1000_adapter *adapter) 2656 { 2657 int size = sizeof(struct e1000_ring); 2658 2659 adapter->tx_ring = kzalloc(size, GFP_KERNEL); 2660 if (!adapter->tx_ring) 2661 goto err; 2662 adapter->tx_ring->count = adapter->tx_ring_count; 2663 adapter->tx_ring->adapter = adapter; 2664 2665 adapter->rx_ring = kzalloc(size, GFP_KERNEL); 2666 if (!adapter->rx_ring) 2667 goto err; 2668 adapter->rx_ring->count = adapter->rx_ring_count; 2669 adapter->rx_ring->adapter = adapter; 2670 2671 return 0; 2672 err: 2673 e_err("Unable to allocate memory for queues\n"); 2674 kfree(adapter->rx_ring); 2675 kfree(adapter->tx_ring); 2676 return -ENOMEM; 2677 } 2678 2679 /** 2680 * e1000e_poll - NAPI Rx polling callback 2681 * @napi: struct associated with this polling callback 2682 * @weight: number of packets driver is allowed to process this poll 2683 **/ 2684 static int e1000e_poll(struct napi_struct *napi, int weight) 2685 { 2686 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, 2687 napi); 2688 struct e1000_hw *hw = &adapter->hw; 2689 struct net_device *poll_dev = adapter->netdev; 2690 int tx_cleaned = 1, work_done = 0; 2691 2692 adapter = netdev_priv(poll_dev); 2693 2694 if (!adapter->msix_entries || 2695 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) 2696 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); 2697 2698 adapter->clean_rx(adapter->rx_ring, &work_done, weight); 2699 2700 if (!tx_cleaned) 2701 work_done = weight; 2702 2703 /* If weight not fully consumed, exit the polling mode */ 2704 if (work_done < weight) { 2705 if (adapter->itr_setting & 3) 2706 e1000_set_itr(adapter); 2707 napi_complete_done(napi, work_done); 2708 if (!test_bit(__E1000_DOWN, &adapter->state)) { 2709 if (adapter->msix_entries) 2710 ew32(IMS, adapter->rx_ring->ims_val | 2711 E1000_IMS_OTHER); 2712 else 2713 e1000_irq_enable(adapter); 2714 } 2715 } 2716 2717 return work_done; 2718 } 2719 2720 static int e1000_vlan_rx_add_vid(struct net_device *netdev, 2721 __always_unused __be16 proto, u16 vid) 2722 { 2723 struct e1000_adapter *adapter = netdev_priv(netdev); 2724 struct e1000_hw *hw = &adapter->hw; 2725 u32 vfta, index; 2726 2727 /* don't update vlan cookie if already programmed */ 2728 if ((adapter->hw.mng_cookie.status & 2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2730 (vid == adapter->mng_vlan_id)) 2731 return 0; 2732 2733 /* add VID to filter table */ 2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2735 index = (vid >> 5) & 0x7F; 2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2737 vfta |= BIT((vid & 0x1F)); 2738 hw->mac.ops.write_vfta(hw, index, vfta); 2739 } 2740 2741 set_bit(vid, adapter->active_vlans); 2742 2743 return 0; 2744 } 2745 2746 static int e1000_vlan_rx_kill_vid(struct net_device *netdev, 2747 __always_unused __be16 proto, u16 vid) 2748 { 2749 struct e1000_adapter *adapter = netdev_priv(netdev); 2750 struct e1000_hw *hw = &adapter->hw; 2751 u32 vfta, index; 2752 2753 if ((adapter->hw.mng_cookie.status & 2754 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && 2755 (vid == adapter->mng_vlan_id)) { 2756 /* release control to f/w */ 2757 e1000e_release_hw_control(adapter); 2758 return 0; 2759 } 2760 2761 /* remove VID from filter table */ 2762 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2763 index = (vid >> 5) & 0x7F; 2764 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); 2765 vfta &= ~BIT((vid & 0x1F)); 2766 hw->mac.ops.write_vfta(hw, index, vfta); 2767 } 2768 2769 clear_bit(vid, adapter->active_vlans); 2770 2771 return 0; 2772 } 2773 2774 /** 2775 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering 2776 * @adapter: board private structure to initialize 2777 **/ 2778 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) 2779 { 2780 struct net_device *netdev = adapter->netdev; 2781 struct e1000_hw *hw = &adapter->hw; 2782 u32 rctl; 2783 2784 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2785 /* disable VLAN receive filtering */ 2786 rctl = er32(RCTL); 2787 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 2788 ew32(RCTL, rctl); 2789 2790 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 2791 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 2792 adapter->mng_vlan_id); 2793 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 2794 } 2795 } 2796 } 2797 2798 /** 2799 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering 2800 * @adapter: board private structure to initialize 2801 **/ 2802 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) 2803 { 2804 struct e1000_hw *hw = &adapter->hw; 2805 u32 rctl; 2806 2807 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { 2808 /* enable VLAN receive filtering */ 2809 rctl = er32(RCTL); 2810 rctl |= E1000_RCTL_VFE; 2811 rctl &= ~E1000_RCTL_CFIEN; 2812 ew32(RCTL, rctl); 2813 } 2814 } 2815 2816 /** 2817 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping 2818 * @adapter: board private structure to initialize 2819 **/ 2820 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) 2821 { 2822 struct e1000_hw *hw = &adapter->hw; 2823 u32 ctrl; 2824 2825 /* disable VLAN tag insert/strip */ 2826 ctrl = er32(CTRL); 2827 ctrl &= ~E1000_CTRL_VME; 2828 ew32(CTRL, ctrl); 2829 } 2830 2831 /** 2832 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping 2833 * @adapter: board private structure to initialize 2834 **/ 2835 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) 2836 { 2837 struct e1000_hw *hw = &adapter->hw; 2838 u32 ctrl; 2839 2840 /* enable VLAN tag insert/strip */ 2841 ctrl = er32(CTRL); 2842 ctrl |= E1000_CTRL_VME; 2843 ew32(CTRL, ctrl); 2844 } 2845 2846 static void e1000_update_mng_vlan(struct e1000_adapter *adapter) 2847 { 2848 struct net_device *netdev = adapter->netdev; 2849 u16 vid = adapter->hw.mng_cookie.vlan_id; 2850 u16 old_vid = adapter->mng_vlan_id; 2851 2852 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 2853 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 2854 adapter->mng_vlan_id = vid; 2855 } 2856 2857 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) 2858 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); 2859 } 2860 2861 static void e1000_restore_vlan(struct e1000_adapter *adapter) 2862 { 2863 u16 vid; 2864 2865 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 2866 2867 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2868 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 2869 } 2870 2871 static void e1000_init_manageability_pt(struct e1000_adapter *adapter) 2872 { 2873 struct e1000_hw *hw = &adapter->hw; 2874 u32 manc, manc2h, mdef, i, j; 2875 2876 if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) 2877 return; 2878 2879 manc = er32(MANC); 2880 2881 /* enable receiving management packets to the host. this will probably 2882 * generate destination unreachable messages from the host OS, but 2883 * the packets will be handled on SMBUS 2884 */ 2885 manc |= E1000_MANC_EN_MNG2HOST; 2886 manc2h = er32(MANC2H); 2887 2888 switch (hw->mac.type) { 2889 default: 2890 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); 2891 break; 2892 case e1000_82574: 2893 case e1000_82583: 2894 /* Check if IPMI pass-through decision filter already exists; 2895 * if so, enable it. 2896 */ 2897 for (i = 0, j = 0; i < 8; i++) { 2898 mdef = er32(MDEF(i)); 2899 2900 /* Ignore filters with anything other than IPMI ports */ 2901 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2902 continue; 2903 2904 /* Enable this decision filter in MANC2H */ 2905 if (mdef) 2906 manc2h |= BIT(i); 2907 2908 j |= mdef; 2909 } 2910 2911 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) 2912 break; 2913 2914 /* Create new decision filter in an empty filter */ 2915 for (i = 0, j = 0; i < 8; i++) 2916 if (er32(MDEF(i)) == 0) { 2917 ew32(MDEF(i), (E1000_MDEF_PORT_623 | 2918 E1000_MDEF_PORT_664)); 2919 manc2h |= BIT(1); 2920 j++; 2921 break; 2922 } 2923 2924 if (!j) 2925 e_warn("Unable to create IPMI pass-through filter\n"); 2926 break; 2927 } 2928 2929 ew32(MANC2H, manc2h); 2930 ew32(MANC, manc); 2931 } 2932 2933 /** 2934 * e1000_configure_tx - Configure Transmit Unit after Reset 2935 * @adapter: board private structure 2936 * 2937 * Configure the Tx unit of the MAC after a reset. 2938 **/ 2939 static void e1000_configure_tx(struct e1000_adapter *adapter) 2940 { 2941 struct e1000_hw *hw = &adapter->hw; 2942 struct e1000_ring *tx_ring = adapter->tx_ring; 2943 u64 tdba; 2944 u32 tdlen, tctl, tarc; 2945 2946 /* Setup the HW Tx Head and Tail descriptor pointers */ 2947 tdba = tx_ring->dma; 2948 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); 2949 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); 2950 ew32(TDBAH(0), (tdba >> 32)); 2951 ew32(TDLEN(0), tdlen); 2952 ew32(TDH(0), 0); 2953 ew32(TDT(0), 0); 2954 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); 2955 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); 2956 2957 writel(0, tx_ring->head); 2958 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 2959 e1000e_update_tdt_wa(tx_ring, 0); 2960 else 2961 writel(0, tx_ring->tail); 2962 2963 /* Set the Tx Interrupt Delay register */ 2964 ew32(TIDV, adapter->tx_int_delay); 2965 /* Tx irq moderation */ 2966 ew32(TADV, adapter->tx_abs_int_delay); 2967 2968 if (adapter->flags2 & FLAG2_DMA_BURST) { 2969 u32 txdctl = er32(TXDCTL(0)); 2970 2971 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2972 E1000_TXDCTL_WTHRESH); 2973 /* set up some performance related parameters to encourage the 2974 * hardware to use the bus more efficiently in bursts, depends 2975 * on the tx_int_delay to be enabled, 2976 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2977 * hthresh = 1 ==> prefetch when one or more available 2978 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2979 * BEWARE: this seems to work but should be considered first if 2980 * there are Tx hangs or other Tx related bugs 2981 */ 2982 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; 2983 ew32(TXDCTL(0), txdctl); 2984 } 2985 /* erratum work around: set txdctl the same for both queues */ 2986 ew32(TXDCTL(1), er32(TXDCTL(0))); 2987 2988 /* Program the Transmit Control Register */ 2989 tctl = er32(TCTL); 2990 tctl &= ~E1000_TCTL_CT; 2991 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2992 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2993 2994 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2995 tarc = er32(TARC(0)); 2996 /* set the speed mode bit, we'll clear it if we're not at 2997 * gigabit link later 2998 */ 2999 #define SPEED_MODE_BIT BIT(21) 3000 tarc |= SPEED_MODE_BIT; 3001 ew32(TARC(0), tarc); 3002 } 3003 3004 /* errata: program both queues to unweighted RR */ 3005 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { 3006 tarc = er32(TARC(0)); 3007 tarc |= 1; 3008 ew32(TARC(0), tarc); 3009 tarc = er32(TARC(1)); 3010 tarc |= 1; 3011 ew32(TARC(1), tarc); 3012 } 3013 3014 /* Setup Transmit Descriptor Settings for eop descriptor */ 3015 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 3016 3017 /* only set IDE if we are delaying interrupts using the timers */ 3018 if (adapter->tx_int_delay) 3019 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3020 3021 /* enable Report Status bit */ 3022 adapter->txd_cmd |= E1000_TXD_CMD_RS; 3023 3024 ew32(TCTL, tctl); 3025 3026 hw->mac.ops.config_collision_dist(hw); 3027 3028 /* SPT and KBL Si errata workaround to avoid data corruption */ 3029 if (hw->mac.type == e1000_pch_spt) { 3030 u32 reg_val; 3031 3032 reg_val = er32(IOSFPC); 3033 reg_val |= E1000_RCTL_RDMTS_HEX; 3034 ew32(IOSFPC, reg_val); 3035 3036 reg_val = er32(TARC(0)); 3037 /* SPT and KBL Si errata workaround to avoid Tx hang */ 3038 reg_val &= ~BIT(28); 3039 reg_val |= BIT(29); 3040 ew32(TARC(0), reg_val); 3041 } 3042 } 3043 3044 /** 3045 * e1000_setup_rctl - configure the receive control registers 3046 * @adapter: Board private structure 3047 **/ 3048 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ 3049 (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) 3050 static void e1000_setup_rctl(struct e1000_adapter *adapter) 3051 { 3052 struct e1000_hw *hw = &adapter->hw; 3053 u32 rctl, rfctl; 3054 u32 pages = 0; 3055 3056 /* Workaround Si errata on PCHx - configure jumbo frame flow. 3057 * If jumbo frames not set, program related MAC/PHY registers 3058 * to h/w defaults 3059 */ 3060 if (hw->mac.type >= e1000_pch2lan) { 3061 s32 ret_val; 3062 3063 if (adapter->netdev->mtu > ETH_DATA_LEN) 3064 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); 3065 else 3066 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); 3067 3068 if (ret_val) 3069 e_dbg("failed to enable|disable jumbo frame workaround mode\n"); 3070 } 3071 3072 /* Program MC offset vector base */ 3073 rctl = er32(RCTL); 3074 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3075 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3076 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3077 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3078 3079 /* Do not Store bad packets */ 3080 rctl &= ~E1000_RCTL_SBP; 3081 3082 /* Enable Long Packet receive */ 3083 if (adapter->netdev->mtu <= ETH_DATA_LEN) 3084 rctl &= ~E1000_RCTL_LPE; 3085 else 3086 rctl |= E1000_RCTL_LPE; 3087 3088 /* Some systems expect that the CRC is included in SMBUS traffic. The 3089 * hardware strips the CRC before sending to both SMBUS (BMC) and to 3090 * host memory when this is enabled 3091 */ 3092 if (adapter->flags2 & FLAG2_CRC_STRIPPING) 3093 rctl |= E1000_RCTL_SECRC; 3094 3095 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ 3096 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { 3097 u16 phy_data; 3098 3099 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); 3100 phy_data &= 0xfff8; 3101 phy_data |= BIT(2); 3102 e1e_wphy(hw, PHY_REG(770, 26), phy_data); 3103 3104 e1e_rphy(hw, 22, &phy_data); 3105 phy_data &= 0x0fff; 3106 phy_data |= BIT(14); 3107 e1e_wphy(hw, 0x10, 0x2823); 3108 e1e_wphy(hw, 0x11, 0x0003); 3109 e1e_wphy(hw, 22, phy_data); 3110 } 3111 3112 /* Setup buffer sizes */ 3113 rctl &= ~E1000_RCTL_SZ_4096; 3114 rctl |= E1000_RCTL_BSEX; 3115 switch (adapter->rx_buffer_len) { 3116 case 2048: 3117 default: 3118 rctl |= E1000_RCTL_SZ_2048; 3119 rctl &= ~E1000_RCTL_BSEX; 3120 break; 3121 case 4096: 3122 rctl |= E1000_RCTL_SZ_4096; 3123 break; 3124 case 8192: 3125 rctl |= E1000_RCTL_SZ_8192; 3126 break; 3127 case 16384: 3128 rctl |= E1000_RCTL_SZ_16384; 3129 break; 3130 } 3131 3132 /* Enable Extended Status in all Receive Descriptors */ 3133 rfctl = er32(RFCTL); 3134 rfctl |= E1000_RFCTL_EXTEN; 3135 ew32(RFCTL, rfctl); 3136 3137 /* 82571 and greater support packet-split where the protocol 3138 * header is placed in skb->data and the packet data is 3139 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 3140 * In the case of a non-split, skb->data is linearly filled, 3141 * followed by the page buffers. Therefore, skb->data is 3142 * sized to hold the largest protocol header. 3143 * 3144 * allocations using alloc_page take too long for regular MTU 3145 * so only enable packet split for jumbo frames 3146 * 3147 * Using pages when the page size is greater than 16k wastes 3148 * a lot of memory, since we allocate 3 pages at all times 3149 * per packet. 3150 */ 3151 pages = PAGE_USE_COUNT(adapter->netdev->mtu); 3152 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) 3153 adapter->rx_ps_pages = pages; 3154 else 3155 adapter->rx_ps_pages = 0; 3156 3157 if (adapter->rx_ps_pages) { 3158 u32 psrctl = 0; 3159 3160 /* Enable Packet split descriptors */ 3161 rctl |= E1000_RCTL_DTYP_PS; 3162 3163 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; 3164 3165 switch (adapter->rx_ps_pages) { 3166 case 3: 3167 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; 3168 /* fall-through */ 3169 case 2: 3170 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; 3171 /* fall-through */ 3172 case 1: 3173 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; 3174 break; 3175 } 3176 3177 ew32(PSRCTL, psrctl); 3178 } 3179 3180 /* This is useful for sniffing bad packets. */ 3181 if (adapter->netdev->features & NETIF_F_RXALL) { 3182 /* UPE and MPE will be handled by normal PROMISC logic 3183 * in e1000e_set_rx_mode 3184 */ 3185 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3186 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3187 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3188 3189 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3190 E1000_RCTL_DPF | /* Allow filtered pause */ 3191 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3192 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3193 * and that breaks VLANs. 3194 */ 3195 } 3196 3197 ew32(RCTL, rctl); 3198 /* just started the receive unit, no need to restart */ 3199 adapter->flags &= ~FLAG_RESTART_NOW; 3200 } 3201 3202 /** 3203 * e1000_configure_rx - Configure Receive Unit after Reset 3204 * @adapter: board private structure 3205 * 3206 * Configure the Rx unit of the MAC after a reset. 3207 **/ 3208 static void e1000_configure_rx(struct e1000_adapter *adapter) 3209 { 3210 struct e1000_hw *hw = &adapter->hw; 3211 struct e1000_ring *rx_ring = adapter->rx_ring; 3212 u64 rdba; 3213 u32 rdlen, rctl, rxcsum, ctrl_ext; 3214 3215 if (adapter->rx_ps_pages) { 3216 /* this is a 32 byte descriptor */ 3217 rdlen = rx_ring->count * 3218 sizeof(union e1000_rx_desc_packet_split); 3219 adapter->clean_rx = e1000_clean_rx_irq_ps; 3220 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; 3221 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { 3222 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3223 adapter->clean_rx = e1000_clean_jumbo_rx_irq; 3224 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; 3225 } else { 3226 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); 3227 adapter->clean_rx = e1000_clean_rx_irq; 3228 adapter->alloc_rx_buf = e1000_alloc_rx_buffers; 3229 } 3230 3231 /* disable receives while setting up the descriptors */ 3232 rctl = er32(RCTL); 3233 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 3234 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3235 e1e_flush(); 3236 usleep_range(10000, 20000); 3237 3238 if (adapter->flags2 & FLAG2_DMA_BURST) { 3239 /* set the writeback threshold (only takes effect if the RDTR 3240 * is set). set GRAN=1 and write back up to 0x4 worth, and 3241 * enable prefetching of 0x20 Rx descriptors 3242 * granularity = 01 3243 * wthresh = 04, 3244 * hthresh = 04, 3245 * pthresh = 0x20 3246 */ 3247 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3248 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3249 } 3250 3251 /* set the Receive Delay Timer Register */ 3252 ew32(RDTR, adapter->rx_int_delay); 3253 3254 /* irq moderation */ 3255 ew32(RADV, adapter->rx_abs_int_delay); 3256 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) 3257 e1000e_write_itr(adapter, adapter->itr); 3258 3259 ctrl_ext = er32(CTRL_EXT); 3260 /* Auto-Mask interrupts upon ICR access */ 3261 ctrl_ext |= E1000_CTRL_EXT_IAME; 3262 ew32(IAM, 0xffffffff); 3263 ew32(CTRL_EXT, ctrl_ext); 3264 e1e_flush(); 3265 3266 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3267 * the Base and Length of the Rx Descriptor Ring 3268 */ 3269 rdba = rx_ring->dma; 3270 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); 3271 ew32(RDBAH(0), (rdba >> 32)); 3272 ew32(RDLEN(0), rdlen); 3273 ew32(RDH(0), 0); 3274 ew32(RDT(0), 0); 3275 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); 3276 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); 3277 3278 writel(0, rx_ring->head); 3279 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 3280 e1000e_update_rdt_wa(rx_ring, 0); 3281 else 3282 writel(0, rx_ring->tail); 3283 3284 /* Enable Receive Checksum Offload for TCP and UDP */ 3285 rxcsum = er32(RXCSUM); 3286 if (adapter->netdev->features & NETIF_F_RXCSUM) 3287 rxcsum |= E1000_RXCSUM_TUOFL; 3288 else 3289 rxcsum &= ~E1000_RXCSUM_TUOFL; 3290 ew32(RXCSUM, rxcsum); 3291 3292 /* With jumbo frames, excessive C-state transition latencies result 3293 * in dropped transactions. 3294 */ 3295 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3296 u32 lat = 3297 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - 3298 adapter->max_frame_size) * 8 / 1000; 3299 3300 if (adapter->flags & FLAG_IS_ICH) { 3301 u32 rxdctl = er32(RXDCTL(0)); 3302 3303 ew32(RXDCTL(0), rxdctl | 0x3); 3304 } 3305 3306 pm_qos_update_request(&adapter->pm_qos_req, lat); 3307 } else { 3308 pm_qos_update_request(&adapter->pm_qos_req, 3309 PM_QOS_DEFAULT_VALUE); 3310 } 3311 3312 /* Enable Receives */ 3313 ew32(RCTL, rctl); 3314 } 3315 3316 /** 3317 * e1000e_write_mc_addr_list - write multicast addresses to MTA 3318 * @netdev: network interface device structure 3319 * 3320 * Writes multicast address list to the MTA hash table. 3321 * Returns: -ENOMEM on failure 3322 * 0 on no addresses written 3323 * X on writing X addresses to MTA 3324 */ 3325 static int e1000e_write_mc_addr_list(struct net_device *netdev) 3326 { 3327 struct e1000_adapter *adapter = netdev_priv(netdev); 3328 struct e1000_hw *hw = &adapter->hw; 3329 struct netdev_hw_addr *ha; 3330 u8 *mta_list; 3331 int i; 3332 3333 if (netdev_mc_empty(netdev)) { 3334 /* nothing to program, so clear mc list */ 3335 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); 3336 return 0; 3337 } 3338 3339 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); 3340 if (!mta_list) 3341 return -ENOMEM; 3342 3343 /* update_mc_addr_list expects a packed array of only addresses. */ 3344 i = 0; 3345 netdev_for_each_mc_addr(ha, netdev) 3346 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3347 3348 hw->mac.ops.update_mc_addr_list(hw, mta_list, i); 3349 kfree(mta_list); 3350 3351 return netdev_mc_count(netdev); 3352 } 3353 3354 /** 3355 * e1000e_write_uc_addr_list - write unicast addresses to RAR table 3356 * @netdev: network interface device structure 3357 * 3358 * Writes unicast address list to the RAR table. 3359 * Returns: -ENOMEM on failure/insufficient address space 3360 * 0 on no addresses written 3361 * X on writing X addresses to the RAR table 3362 **/ 3363 static int e1000e_write_uc_addr_list(struct net_device *netdev) 3364 { 3365 struct e1000_adapter *adapter = netdev_priv(netdev); 3366 struct e1000_hw *hw = &adapter->hw; 3367 unsigned int rar_entries; 3368 int count = 0; 3369 3370 rar_entries = hw->mac.ops.rar_get_count(hw); 3371 3372 /* save a rar entry for our hardware address */ 3373 rar_entries--; 3374 3375 /* save a rar entry for the LAA workaround */ 3376 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) 3377 rar_entries--; 3378 3379 /* return ENOMEM indicating insufficient memory for addresses */ 3380 if (netdev_uc_count(netdev) > rar_entries) 3381 return -ENOMEM; 3382 3383 if (!netdev_uc_empty(netdev) && rar_entries) { 3384 struct netdev_hw_addr *ha; 3385 3386 /* write the addresses in reverse order to avoid write 3387 * combining 3388 */ 3389 netdev_for_each_uc_addr(ha, netdev) { 3390 int ret_val; 3391 3392 if (!rar_entries) 3393 break; 3394 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); 3395 if (ret_val < 0) 3396 return -ENOMEM; 3397 count++; 3398 } 3399 } 3400 3401 /* zero out the remaining RAR entries not used above */ 3402 for (; rar_entries > 0; rar_entries--) { 3403 ew32(RAH(rar_entries), 0); 3404 ew32(RAL(rar_entries), 0); 3405 } 3406 e1e_flush(); 3407 3408 return count; 3409 } 3410 3411 /** 3412 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set 3413 * @netdev: network interface device structure 3414 * 3415 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast 3416 * address list or the network interface flags are updated. This routine is 3417 * responsible for configuring the hardware for proper unicast, multicast, 3418 * promiscuous mode, and all-multi behavior. 3419 **/ 3420 static void e1000e_set_rx_mode(struct net_device *netdev) 3421 { 3422 struct e1000_adapter *adapter = netdev_priv(netdev); 3423 struct e1000_hw *hw = &adapter->hw; 3424 u32 rctl; 3425 3426 if (pm_runtime_suspended(netdev->dev.parent)) 3427 return; 3428 3429 /* Check for Promiscuous and All Multicast modes */ 3430 rctl = er32(RCTL); 3431 3432 /* clear the affected bits */ 3433 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 3434 3435 if (netdev->flags & IFF_PROMISC) { 3436 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3437 /* Do not hardware filter VLANs in promisc mode */ 3438 e1000e_vlan_filter_disable(adapter); 3439 } else { 3440 int count; 3441 3442 if (netdev->flags & IFF_ALLMULTI) { 3443 rctl |= E1000_RCTL_MPE; 3444 } else { 3445 /* Write addresses to the MTA, if the attempt fails 3446 * then we should just turn on promiscuous mode so 3447 * that we can at least receive multicast traffic 3448 */ 3449 count = e1000e_write_mc_addr_list(netdev); 3450 if (count < 0) 3451 rctl |= E1000_RCTL_MPE; 3452 } 3453 e1000e_vlan_filter_enable(adapter); 3454 /* Write addresses to available RAR registers, if there is not 3455 * sufficient space to store all the addresses then enable 3456 * unicast promiscuous mode 3457 */ 3458 count = e1000e_write_uc_addr_list(netdev); 3459 if (count < 0) 3460 rctl |= E1000_RCTL_UPE; 3461 } 3462 3463 ew32(RCTL, rctl); 3464 3465 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 3466 e1000e_vlan_strip_enable(adapter); 3467 else 3468 e1000e_vlan_strip_disable(adapter); 3469 } 3470 3471 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) 3472 { 3473 struct e1000_hw *hw = &adapter->hw; 3474 u32 mrqc, rxcsum; 3475 u32 rss_key[10]; 3476 int i; 3477 3478 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3479 for (i = 0; i < 10; i++) 3480 ew32(RSSRK(i), rss_key[i]); 3481 3482 /* Direct all traffic to queue 0 */ 3483 for (i = 0; i < 32; i++) 3484 ew32(RETA(i), 0); 3485 3486 /* Disable raw packet checksumming so that RSS hash is placed in 3487 * descriptor on writeback. 3488 */ 3489 rxcsum = er32(RXCSUM); 3490 rxcsum |= E1000_RXCSUM_PCSD; 3491 3492 ew32(RXCSUM, rxcsum); 3493 3494 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | 3495 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3496 E1000_MRQC_RSS_FIELD_IPV6 | 3497 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3498 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3499 3500 ew32(MRQC, mrqc); 3501 } 3502 3503 /** 3504 * e1000e_get_base_timinca - get default SYSTIM time increment attributes 3505 * @adapter: board private structure 3506 * @timinca: pointer to returned time increment attributes 3507 * 3508 * Get attributes for incrementing the System Time Register SYSTIML/H at 3509 * the default base frequency, and set the cyclecounter shift value. 3510 **/ 3511 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) 3512 { 3513 struct e1000_hw *hw = &adapter->hw; 3514 u32 incvalue, incperiod, shift; 3515 3516 /* Make sure clock is enabled on I217/I218/I219 before checking 3517 * the frequency 3518 */ 3519 if ((hw->mac.type >= e1000_pch_lpt) && 3520 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && 3521 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { 3522 u32 fextnvm7 = er32(FEXTNVM7); 3523 3524 if (!(fextnvm7 & BIT(0))) { 3525 ew32(FEXTNVM7, fextnvm7 | BIT(0)); 3526 e1e_flush(); 3527 } 3528 } 3529 3530 switch (hw->mac.type) { 3531 case e1000_pch2lan: 3532 /* Stable 96MHz frequency */ 3533 incperiod = INCPERIOD_96MHZ; 3534 incvalue = INCVALUE_96MHZ; 3535 shift = INCVALUE_SHIFT_96MHZ; 3536 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3537 break; 3538 case e1000_pch_lpt: 3539 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3540 /* Stable 96MHz frequency */ 3541 incperiod = INCPERIOD_96MHZ; 3542 incvalue = INCVALUE_96MHZ; 3543 shift = INCVALUE_SHIFT_96MHZ; 3544 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; 3545 } else { 3546 /* Stable 25MHz frequency */ 3547 incperiod = INCPERIOD_25MHZ; 3548 incvalue = INCVALUE_25MHZ; 3549 shift = INCVALUE_SHIFT_25MHZ; 3550 adapter->cc.shift = shift; 3551 } 3552 break; 3553 case e1000_pch_spt: 3554 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3555 /* Stable 24MHz frequency */ 3556 incperiod = INCPERIOD_24MHZ; 3557 incvalue = INCVALUE_24MHZ; 3558 shift = INCVALUE_SHIFT_24MHZ; 3559 adapter->cc.shift = shift; 3560 break; 3561 } 3562 return -EINVAL; 3563 case e1000_pch_cnp: 3564 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { 3565 /* Stable 24MHz frequency */ 3566 incperiod = INCPERIOD_24MHZ; 3567 incvalue = INCVALUE_24MHZ; 3568 shift = INCVALUE_SHIFT_24MHZ; 3569 adapter->cc.shift = shift; 3570 } else { 3571 /* Stable 38400KHz frequency */ 3572 incperiod = INCPERIOD_38400KHZ; 3573 incvalue = INCVALUE_38400KHZ; 3574 shift = INCVALUE_SHIFT_38400KHZ; 3575 adapter->cc.shift = shift; 3576 } 3577 break; 3578 case e1000_82574: 3579 case e1000_82583: 3580 /* Stable 25MHz frequency */ 3581 incperiod = INCPERIOD_25MHZ; 3582 incvalue = INCVALUE_25MHZ; 3583 shift = INCVALUE_SHIFT_25MHZ; 3584 adapter->cc.shift = shift; 3585 break; 3586 default: 3587 return -EINVAL; 3588 } 3589 3590 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | 3591 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); 3592 3593 return 0; 3594 } 3595 3596 /** 3597 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable 3598 * @adapter: board private structure 3599 * 3600 * Outgoing time stamping can be enabled and disabled. Play nice and 3601 * disable it when requested, although it shouldn't cause any overhead 3602 * when no packet needs it. At most one packet in the queue may be 3603 * marked for time stamping, otherwise it would be impossible to tell 3604 * for sure to which packet the hardware time stamp belongs. 3605 * 3606 * Incoming time stamping has to be configured via the hardware filters. 3607 * Not all combinations are supported, in particular event type has to be 3608 * specified. Matching the kind of event packet is not supported, with the 3609 * exception of "all V2 events regardless of level 2 or 4". 3610 **/ 3611 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, 3612 struct hwtstamp_config *config) 3613 { 3614 struct e1000_hw *hw = &adapter->hw; 3615 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 3616 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 3617 u32 rxmtrl = 0; 3618 u16 rxudp = 0; 3619 bool is_l4 = false; 3620 bool is_l2 = false; 3621 u32 regval; 3622 3623 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3624 return -EINVAL; 3625 3626 /* flags reserved for future extensions - must be zero */ 3627 if (config->flags) 3628 return -EINVAL; 3629 3630 switch (config->tx_type) { 3631 case HWTSTAMP_TX_OFF: 3632 tsync_tx_ctl = 0; 3633 break; 3634 case HWTSTAMP_TX_ON: 3635 break; 3636 default: 3637 return -ERANGE; 3638 } 3639 3640 switch (config->rx_filter) { 3641 case HWTSTAMP_FILTER_NONE: 3642 tsync_rx_ctl = 0; 3643 break; 3644 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3645 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3646 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; 3647 is_l4 = true; 3648 break; 3649 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3650 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 3651 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; 3652 is_l4 = true; 3653 break; 3654 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3655 /* Also time stamps V2 L2 Path Delay Request/Response */ 3656 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3657 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3658 is_l2 = true; 3659 break; 3660 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3661 /* Also time stamps V2 L2 Path Delay Request/Response. */ 3662 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; 3663 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3664 is_l2 = true; 3665 break; 3666 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3667 /* Hardware cannot filter just V2 L4 Sync messages; 3668 * fall-through to V2 (both L2 and L4) Sync. 3669 */ 3670 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3671 /* Also time stamps V2 Path Delay Request/Response. */ 3672 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3673 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; 3674 is_l2 = true; 3675 is_l4 = true; 3676 break; 3677 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3678 /* Hardware cannot filter just V2 L4 Delay Request messages; 3679 * fall-through to V2 (both L2 and L4) Delay Request. 3680 */ 3681 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3682 /* Also time stamps V2 Path Delay Request/Response. */ 3683 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; 3684 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; 3685 is_l2 = true; 3686 is_l4 = true; 3687 break; 3688 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3689 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3690 /* Hardware cannot filter just V2 L4 or L2 Event messages; 3691 * fall-through to all V2 (both L2 and L4) Events. 3692 */ 3693 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3694 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 3695 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 3696 is_l2 = true; 3697 is_l4 = true; 3698 break; 3699 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3700 /* For V1, the hardware can only filter Sync messages or 3701 * Delay Request messages but not both so fall-through to 3702 * time stamp all packets. 3703 */ 3704 case HWTSTAMP_FILTER_NTP_ALL: 3705 case HWTSTAMP_FILTER_ALL: 3706 is_l2 = true; 3707 is_l4 = true; 3708 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 3709 config->rx_filter = HWTSTAMP_FILTER_ALL; 3710 break; 3711 default: 3712 return -ERANGE; 3713 } 3714 3715 adapter->hwtstamp_config = *config; 3716 3717 /* enable/disable Tx h/w time stamping */ 3718 regval = er32(TSYNCTXCTL); 3719 regval &= ~E1000_TSYNCTXCTL_ENABLED; 3720 regval |= tsync_tx_ctl; 3721 ew32(TSYNCTXCTL, regval); 3722 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != 3723 (regval & E1000_TSYNCTXCTL_ENABLED)) { 3724 e_err("Timesync Tx Control register not set as expected\n"); 3725 return -EAGAIN; 3726 } 3727 3728 /* enable/disable Rx h/w time stamping */ 3729 regval = er32(TSYNCRXCTL); 3730 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 3731 regval |= tsync_rx_ctl; 3732 ew32(TSYNCRXCTL, regval); 3733 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | 3734 E1000_TSYNCRXCTL_TYPE_MASK)) != 3735 (regval & (E1000_TSYNCRXCTL_ENABLED | 3736 E1000_TSYNCRXCTL_TYPE_MASK))) { 3737 e_err("Timesync Rx Control register not set as expected\n"); 3738 return -EAGAIN; 3739 } 3740 3741 /* L2: define ethertype filter for time stamped packets */ 3742 if (is_l2) 3743 rxmtrl |= ETH_P_1588; 3744 3745 /* define which PTP packets get time stamped */ 3746 ew32(RXMTRL, rxmtrl); 3747 3748 /* Filter by destination port */ 3749 if (is_l4) { 3750 rxudp = PTP_EV_PORT; 3751 cpu_to_be16s(&rxudp); 3752 } 3753 ew32(RXUDP, rxudp); 3754 3755 e1e_flush(); 3756 3757 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ 3758 er32(RXSTMPH); 3759 er32(TXSTMPH); 3760 3761 return 0; 3762 } 3763 3764 /** 3765 * e1000_configure - configure the hardware for Rx and Tx 3766 * @adapter: private board structure 3767 **/ 3768 static void e1000_configure(struct e1000_adapter *adapter) 3769 { 3770 struct e1000_ring *rx_ring = adapter->rx_ring; 3771 3772 e1000e_set_rx_mode(adapter->netdev); 3773 3774 e1000_restore_vlan(adapter); 3775 e1000_init_manageability_pt(adapter); 3776 3777 e1000_configure_tx(adapter); 3778 3779 if (adapter->netdev->features & NETIF_F_RXHASH) 3780 e1000e_setup_rss_hash(adapter); 3781 e1000_setup_rctl(adapter); 3782 e1000_configure_rx(adapter); 3783 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); 3784 } 3785 3786 /** 3787 * e1000e_power_up_phy - restore link in case the phy was powered down 3788 * @adapter: address of board private structure 3789 * 3790 * The phy may be powered down to save power and turn off link when the 3791 * driver is unloaded and wake on lan is not enabled (among others) 3792 * *** this routine MUST be followed by a call to e1000e_reset *** 3793 **/ 3794 void e1000e_power_up_phy(struct e1000_adapter *adapter) 3795 { 3796 if (adapter->hw.phy.ops.power_up) 3797 adapter->hw.phy.ops.power_up(&adapter->hw); 3798 3799 adapter->hw.mac.ops.setup_link(&adapter->hw); 3800 } 3801 3802 /** 3803 * e1000_power_down_phy - Power down the PHY 3804 * 3805 * Power down the PHY so no link is implied when interface is down. 3806 * The PHY cannot be powered down if management or WoL is active. 3807 */ 3808 static void e1000_power_down_phy(struct e1000_adapter *adapter) 3809 { 3810 if (adapter->hw.phy.ops.power_down) 3811 adapter->hw.phy.ops.power_down(&adapter->hw); 3812 } 3813 3814 /** 3815 * e1000_flush_tx_ring - remove all descriptors from the tx_ring 3816 * 3817 * We want to clear all pending descriptors from the TX ring. 3818 * zeroing happens when the HW reads the regs. We assign the ring itself as 3819 * the data of the next descriptor. We don't care about the data we are about 3820 * to reset the HW. 3821 */ 3822 static void e1000_flush_tx_ring(struct e1000_adapter *adapter) 3823 { 3824 struct e1000_hw *hw = &adapter->hw; 3825 struct e1000_ring *tx_ring = adapter->tx_ring; 3826 struct e1000_tx_desc *tx_desc = NULL; 3827 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; 3828 u16 size = 512; 3829 3830 tctl = er32(TCTL); 3831 ew32(TCTL, tctl | E1000_TCTL_EN); 3832 tdt = er32(TDT(0)); 3833 BUG_ON(tdt != tx_ring->next_to_use); 3834 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); 3835 tx_desc->buffer_addr = tx_ring->dma; 3836 3837 tx_desc->lower.data = cpu_to_le32(txd_lower | size); 3838 tx_desc->upper.data = 0; 3839 /* flush descriptors to memory before notifying the HW */ 3840 wmb(); 3841 tx_ring->next_to_use++; 3842 if (tx_ring->next_to_use == tx_ring->count) 3843 tx_ring->next_to_use = 0; 3844 ew32(TDT(0), tx_ring->next_to_use); 3845 mmiowb(); 3846 usleep_range(200, 250); 3847 } 3848 3849 /** 3850 * e1000_flush_rx_ring - remove all descriptors from the rx_ring 3851 * 3852 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3853 */ 3854 static void e1000_flush_rx_ring(struct e1000_adapter *adapter) 3855 { 3856 u32 rctl, rxdctl; 3857 struct e1000_hw *hw = &adapter->hw; 3858 3859 rctl = er32(RCTL); 3860 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3861 e1e_flush(); 3862 usleep_range(100, 150); 3863 3864 rxdctl = er32(RXDCTL(0)); 3865 /* zero the lower 14 bits (prefetch and host thresholds) */ 3866 rxdctl &= 0xffffc000; 3867 3868 /* update thresholds: prefetch threshold to 31, host threshold to 1 3869 * and make sure the granularity is "descriptors" and not "cache lines" 3870 */ 3871 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3872 3873 ew32(RXDCTL(0), rxdctl); 3874 /* momentarily enable the RX ring for the changes to take effect */ 3875 ew32(RCTL, rctl | E1000_RCTL_EN); 3876 e1e_flush(); 3877 usleep_range(100, 150); 3878 ew32(RCTL, rctl & ~E1000_RCTL_EN); 3879 } 3880 3881 /** 3882 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings 3883 * 3884 * In i219, the descriptor rings must be emptied before resetting the HW 3885 * or before changing the device state to D3 during runtime (runtime PM). 3886 * 3887 * Failure to do this will cause the HW to enter a unit hang state which can 3888 * only be released by PCI reset on the device 3889 * 3890 */ 3891 3892 static void e1000_flush_desc_rings(struct e1000_adapter *adapter) 3893 { 3894 u16 hang_state; 3895 u32 fext_nvm11, tdlen; 3896 struct e1000_hw *hw = &adapter->hw; 3897 3898 /* First, disable MULR fix in FEXTNVM11 */ 3899 fext_nvm11 = er32(FEXTNVM11); 3900 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3901 ew32(FEXTNVM11, fext_nvm11); 3902 /* do nothing if we're not in faulty state, or if the queue is empty */ 3903 tdlen = er32(TDLEN(0)); 3904 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3905 &hang_state); 3906 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3907 return; 3908 e1000_flush_tx_ring(adapter); 3909 /* recheck, maybe the fault is caused by the rx ring */ 3910 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, 3911 &hang_state); 3912 if (hang_state & FLUSH_DESC_REQUIRED) 3913 e1000_flush_rx_ring(adapter); 3914 } 3915 3916 /** 3917 * e1000e_systim_reset - reset the timesync registers after a hardware reset 3918 * @adapter: board private structure 3919 * 3920 * When the MAC is reset, all hardware bits for timesync will be reset to the 3921 * default values. This function will restore the settings last in place. 3922 * Since the clock SYSTIME registers are reset, we will simply restore the 3923 * cyclecounter to the kernel real clock time. 3924 **/ 3925 static void e1000e_systim_reset(struct e1000_adapter *adapter) 3926 { 3927 struct ptp_clock_info *info = &adapter->ptp_clock_info; 3928 struct e1000_hw *hw = &adapter->hw; 3929 unsigned long flags; 3930 u32 timinca; 3931 s32 ret_val; 3932 3933 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 3934 return; 3935 3936 if (info->adjfreq) { 3937 /* restore the previous ptp frequency delta */ 3938 ret_val = info->adjfreq(info, adapter->ptp_delta); 3939 } else { 3940 /* set the default base frequency if no adjustment possible */ 3941 ret_val = e1000e_get_base_timinca(adapter, &timinca); 3942 if (!ret_val) 3943 ew32(TIMINCA, timinca); 3944 } 3945 3946 if (ret_val) { 3947 dev_warn(&adapter->pdev->dev, 3948 "Failed to restore TIMINCA clock rate delta: %d\n", 3949 ret_val); 3950 return; 3951 } 3952 3953 /* reset the systim ns time counter */ 3954 spin_lock_irqsave(&adapter->systim_lock, flags); 3955 timecounter_init(&adapter->tc, &adapter->cc, 3956 ktime_to_ns(ktime_get_real())); 3957 spin_unlock_irqrestore(&adapter->systim_lock, flags); 3958 3959 /* restore the previous hwtstamp configuration settings */ 3960 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); 3961 } 3962 3963 /** 3964 * e1000e_reset - bring the hardware into a known good state 3965 * 3966 * This function boots the hardware and enables some settings that 3967 * require a configuration cycle of the hardware - those cannot be 3968 * set/changed during runtime. After reset the device needs to be 3969 * properly configured for Rx, Tx etc. 3970 */ 3971 void e1000e_reset(struct e1000_adapter *adapter) 3972 { 3973 struct e1000_mac_info *mac = &adapter->hw.mac; 3974 struct e1000_fc_info *fc = &adapter->hw.fc; 3975 struct e1000_hw *hw = &adapter->hw; 3976 u32 tx_space, min_tx_space, min_rx_space; 3977 u32 pba = adapter->pba; 3978 u16 hwm; 3979 3980 /* reset Packet Buffer Allocation to default */ 3981 ew32(PBA, pba); 3982 3983 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { 3984 /* To maintain wire speed transmits, the Tx FIFO should be 3985 * large enough to accommodate two full transmit packets, 3986 * rounded up to the next 1KB and expressed in KB. Likewise, 3987 * the Rx FIFO should be large enough to accommodate at least 3988 * one full receive packet and is similarly rounded up and 3989 * expressed in KB. 3990 */ 3991 pba = er32(PBA); 3992 /* upper 16 bits has Tx packet buffer allocation size in KB */ 3993 tx_space = pba >> 16; 3994 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3995 pba &= 0xffff; 3996 /* the Tx fifo also stores 16 bytes of information about the Tx 3997 * but don't include ethernet FCS because hardware appends it 3998 */ 3999 min_tx_space = (adapter->max_frame_size + 4000 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; 4001 min_tx_space = ALIGN(min_tx_space, 1024); 4002 min_tx_space >>= 10; 4003 /* software strips receive CRC, so leave room for it */ 4004 min_rx_space = adapter->max_frame_size; 4005 min_rx_space = ALIGN(min_rx_space, 1024); 4006 min_rx_space >>= 10; 4007 4008 /* If current Tx allocation is less than the min Tx FIFO size, 4009 * and the min Tx FIFO size is less than the current Rx FIFO 4010 * allocation, take space away from current Rx allocation 4011 */ 4012 if ((tx_space < min_tx_space) && 4013 ((min_tx_space - tx_space) < pba)) { 4014 pba -= min_tx_space - tx_space; 4015 4016 /* if short on Rx space, Rx wins and must trump Tx 4017 * adjustment 4018 */ 4019 if (pba < min_rx_space) 4020 pba = min_rx_space; 4021 } 4022 4023 ew32(PBA, pba); 4024 } 4025 4026 /* flow control settings 4027 * 4028 * The high water mark must be low enough to fit one full frame 4029 * (or the size used for early receive) above it in the Rx FIFO. 4030 * Set it to the lower of: 4031 * - 90% of the Rx FIFO size, and 4032 * - the full Rx FIFO size minus one full frame 4033 */ 4034 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) 4035 fc->pause_time = 0xFFFF; 4036 else 4037 fc->pause_time = E1000_FC_PAUSE_TIME; 4038 fc->send_xon = true; 4039 fc->current_mode = fc->requested_mode; 4040 4041 switch (hw->mac.type) { 4042 case e1000_ich9lan: 4043 case e1000_ich10lan: 4044 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4045 pba = 14; 4046 ew32(PBA, pba); 4047 fc->high_water = 0x2800; 4048 fc->low_water = fc->high_water - 8; 4049 break; 4050 } 4051 /* fall-through */ 4052 default: 4053 hwm = min(((pba << 10) * 9 / 10), 4054 ((pba << 10) - adapter->max_frame_size)); 4055 4056 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ 4057 fc->low_water = fc->high_water - 8; 4058 break; 4059 case e1000_pchlan: 4060 /* Workaround PCH LOM adapter hangs with certain network 4061 * loads. If hangs persist, try disabling Tx flow control. 4062 */ 4063 if (adapter->netdev->mtu > ETH_DATA_LEN) { 4064 fc->high_water = 0x3500; 4065 fc->low_water = 0x1500; 4066 } else { 4067 fc->high_water = 0x5000; 4068 fc->low_water = 0x3000; 4069 } 4070 fc->refresh_time = 0x1000; 4071 break; 4072 case e1000_pch2lan: 4073 case e1000_pch_lpt: 4074 case e1000_pch_spt: 4075 case e1000_pch_cnp: 4076 fc->refresh_time = 0x0400; 4077 4078 if (adapter->netdev->mtu <= ETH_DATA_LEN) { 4079 fc->high_water = 0x05C20; 4080 fc->low_water = 0x05048; 4081 fc->pause_time = 0x0650; 4082 break; 4083 } 4084 4085 pba = 14; 4086 ew32(PBA, pba); 4087 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; 4088 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; 4089 break; 4090 } 4091 4092 /* Alignment of Tx data is on an arbitrary byte boundary with the 4093 * maximum size per Tx descriptor limited only to the transmit 4094 * allocation of the packet buffer minus 96 bytes with an upper 4095 * limit of 24KB due to receive synchronization limitations. 4096 */ 4097 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 4098 24 << 10); 4099 4100 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot 4101 * fit in receive buffer. 4102 */ 4103 if (adapter->itr_setting & 0x3) { 4104 if ((adapter->max_frame_size * 2) > (pba << 10)) { 4105 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { 4106 dev_info(&adapter->pdev->dev, 4107 "Interrupt Throttle Rate off\n"); 4108 adapter->flags2 |= FLAG2_DISABLE_AIM; 4109 e1000e_write_itr(adapter, 0); 4110 } 4111 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { 4112 dev_info(&adapter->pdev->dev, 4113 "Interrupt Throttle Rate on\n"); 4114 adapter->flags2 &= ~FLAG2_DISABLE_AIM; 4115 adapter->itr = 20000; 4116 e1000e_write_itr(adapter, adapter->itr); 4117 } 4118 } 4119 4120 if (hw->mac.type >= e1000_pch_spt) 4121 e1000_flush_desc_rings(adapter); 4122 /* Allow time for pending master requests to run */ 4123 mac->ops.reset_hw(hw); 4124 4125 /* For parts with AMT enabled, let the firmware know 4126 * that the network interface is in control 4127 */ 4128 if (adapter->flags & FLAG_HAS_AMT) 4129 e1000e_get_hw_control(adapter); 4130 4131 ew32(WUC, 0); 4132 4133 if (mac->ops.init_hw(hw)) 4134 e_err("Hardware Error\n"); 4135 4136 e1000_update_mng_vlan(adapter); 4137 4138 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 4139 ew32(VET, ETH_P_8021Q); 4140 4141 e1000e_reset_adaptive(hw); 4142 4143 /* restore systim and hwtstamp settings */ 4144 e1000e_systim_reset(adapter); 4145 4146 /* Set EEE advertisement as appropriate */ 4147 if (adapter->flags2 & FLAG2_HAS_EEE) { 4148 s32 ret_val; 4149 u16 adv_addr; 4150 4151 switch (hw->phy.type) { 4152 case e1000_phy_82579: 4153 adv_addr = I82579_EEE_ADVERTISEMENT; 4154 break; 4155 case e1000_phy_i217: 4156 adv_addr = I217_EEE_ADVERTISEMENT; 4157 break; 4158 default: 4159 dev_err(&adapter->pdev->dev, 4160 "Invalid PHY type setting EEE advertisement\n"); 4161 return; 4162 } 4163 4164 ret_val = hw->phy.ops.acquire(hw); 4165 if (ret_val) { 4166 dev_err(&adapter->pdev->dev, 4167 "EEE advertisement - unable to acquire PHY\n"); 4168 return; 4169 } 4170 4171 e1000_write_emi_reg_locked(hw, adv_addr, 4172 hw->dev_spec.ich8lan.eee_disable ? 4173 0 : adapter->eee_advert); 4174 4175 hw->phy.ops.release(hw); 4176 } 4177 4178 if (!netif_running(adapter->netdev) && 4179 !test_bit(__E1000_TESTING, &adapter->state)) 4180 e1000_power_down_phy(adapter); 4181 4182 e1000_get_phy_info(hw); 4183 4184 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 4185 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 4186 u16 phy_data = 0; 4187 /* speed up time to link by disabling smart power down, ignore 4188 * the return value of this function because there is nothing 4189 * different we would do if it failed 4190 */ 4191 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 4192 phy_data &= ~IGP02E1000_PM_SPD; 4193 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 4194 } 4195 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { 4196 u32 reg; 4197 4198 /* Fextnvm7 @ 0xe4[2] = 1 */ 4199 reg = er32(FEXTNVM7); 4200 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 4201 ew32(FEXTNVM7, reg); 4202 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ 4203 reg = er32(FEXTNVM9); 4204 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 4205 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 4206 ew32(FEXTNVM9, reg); 4207 } 4208 4209 } 4210 4211 /** 4212 * e1000e_trigger_lsc - trigger an LSC interrupt 4213 * @adapter: 4214 * 4215 * Fire a link status change interrupt to start the watchdog. 4216 **/ 4217 static void e1000e_trigger_lsc(struct e1000_adapter *adapter) 4218 { 4219 struct e1000_hw *hw = &adapter->hw; 4220 4221 if (adapter->msix_entries) 4222 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); 4223 else 4224 ew32(ICS, E1000_ICS_LSC); 4225 } 4226 4227 void e1000e_up(struct e1000_adapter *adapter) 4228 { 4229 /* hardware has been reset, we need to reload some things */ 4230 e1000_configure(adapter); 4231 4232 clear_bit(__E1000_DOWN, &adapter->state); 4233 4234 if (adapter->msix_entries) 4235 e1000_configure_msix(adapter); 4236 e1000_irq_enable(adapter); 4237 4238 netif_start_queue(adapter->netdev); 4239 4240 e1000e_trigger_lsc(adapter); 4241 } 4242 4243 static void e1000e_flush_descriptors(struct e1000_adapter *adapter) 4244 { 4245 struct e1000_hw *hw = &adapter->hw; 4246 4247 if (!(adapter->flags2 & FLAG2_DMA_BURST)) 4248 return; 4249 4250 /* flush pending descriptor writebacks to memory */ 4251 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4252 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4253 4254 /* execute the writes immediately */ 4255 e1e_flush(); 4256 4257 /* due to rare timing issues, write to TIDV/RDTR again to ensure the 4258 * write is successful 4259 */ 4260 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 4261 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); 4262 4263 /* execute the writes immediately */ 4264 e1e_flush(); 4265 } 4266 4267 static void e1000e_update_stats(struct e1000_adapter *adapter); 4268 4269 /** 4270 * e1000e_down - quiesce the device and optionally reset the hardware 4271 * @adapter: board private structure 4272 * @reset: boolean flag to reset the hardware or not 4273 */ 4274 void e1000e_down(struct e1000_adapter *adapter, bool reset) 4275 { 4276 struct net_device *netdev = adapter->netdev; 4277 struct e1000_hw *hw = &adapter->hw; 4278 u32 tctl, rctl; 4279 4280 /* signal that we're down so the interrupt handler does not 4281 * reschedule our watchdog timer 4282 */ 4283 set_bit(__E1000_DOWN, &adapter->state); 4284 4285 netif_carrier_off(netdev); 4286 4287 /* disable receives in the hardware */ 4288 rctl = er32(RCTL); 4289 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) 4290 ew32(RCTL, rctl & ~E1000_RCTL_EN); 4291 /* flush and sleep below */ 4292 4293 netif_stop_queue(netdev); 4294 4295 /* disable transmits in the hardware */ 4296 tctl = er32(TCTL); 4297 tctl &= ~E1000_TCTL_EN; 4298 ew32(TCTL, tctl); 4299 4300 /* flush both disables and wait for them to finish */ 4301 e1e_flush(); 4302 usleep_range(10000, 20000); 4303 4304 e1000_irq_disable(adapter); 4305 4306 napi_synchronize(&adapter->napi); 4307 4308 del_timer_sync(&adapter->watchdog_timer); 4309 del_timer_sync(&adapter->phy_info_timer); 4310 4311 spin_lock(&adapter->stats64_lock); 4312 e1000e_update_stats(adapter); 4313 spin_unlock(&adapter->stats64_lock); 4314 4315 e1000e_flush_descriptors(adapter); 4316 4317 adapter->link_speed = 0; 4318 adapter->link_duplex = 0; 4319 4320 /* Disable Si errata workaround on PCHx for jumbo frame flow */ 4321 if ((hw->mac.type >= e1000_pch2lan) && 4322 (adapter->netdev->mtu > ETH_DATA_LEN) && 4323 e1000_lv_jumbo_workaround_ich8lan(hw, false)) 4324 e_dbg("failed to disable jumbo frame workaround mode\n"); 4325 4326 if (!pci_channel_offline(adapter->pdev)) { 4327 if (reset) 4328 e1000e_reset(adapter); 4329 else if (hw->mac.type >= e1000_pch_spt) 4330 e1000_flush_desc_rings(adapter); 4331 } 4332 e1000_clean_tx_ring(adapter->tx_ring); 4333 e1000_clean_rx_ring(adapter->rx_ring); 4334 } 4335 4336 void e1000e_reinit_locked(struct e1000_adapter *adapter) 4337 { 4338 might_sleep(); 4339 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 4340 usleep_range(1000, 2000); 4341 e1000e_down(adapter, true); 4342 e1000e_up(adapter); 4343 clear_bit(__E1000_RESETTING, &adapter->state); 4344 } 4345 4346 /** 4347 * e1000e_sanitize_systim - sanitize raw cycle counter reads 4348 * @hw: pointer to the HW structure 4349 * @systim: time value read, sanitized and returned 4350 * 4351 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: 4352 * check to see that the time is incrementing at a reasonable 4353 * rate and is a multiple of incvalue. 4354 **/ 4355 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim) 4356 { 4357 u64 time_delta, rem, temp; 4358 u64 systim_next; 4359 u32 incvalue; 4360 int i; 4361 4362 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; 4363 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { 4364 /* latch SYSTIMH on read of SYSTIML */ 4365 systim_next = (u64)er32(SYSTIML); 4366 systim_next |= (u64)er32(SYSTIMH) << 32; 4367 4368 time_delta = systim_next - systim; 4369 temp = time_delta; 4370 /* VMWare users have seen incvalue of zero, don't div / 0 */ 4371 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); 4372 4373 systim = systim_next; 4374 4375 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) 4376 break; 4377 } 4378 4379 return systim; 4380 } 4381 4382 /** 4383 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) 4384 * @cc: cyclecounter structure 4385 **/ 4386 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) 4387 { 4388 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, 4389 cc); 4390 struct e1000_hw *hw = &adapter->hw; 4391 u32 systimel, systimeh; 4392 u64 systim; 4393 /* SYSTIMH latching upon SYSTIML read does not work well. 4394 * This means that if SYSTIML overflows after we read it but before 4395 * we read SYSTIMH, the value of SYSTIMH has been incremented and we 4396 * will experience a huge non linear increment in the systime value 4397 * to fix that we test for overflow and if true, we re-read systime. 4398 */ 4399 systimel = er32(SYSTIML); 4400 systimeh = er32(SYSTIMH); 4401 /* Is systimel is so large that overflow is possible? */ 4402 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { 4403 u32 systimel_2 = er32(SYSTIML); 4404 if (systimel > systimel_2) { 4405 /* There was an overflow, read again SYSTIMH, and use 4406 * systimel_2 4407 */ 4408 systimeh = er32(SYSTIMH); 4409 systimel = systimel_2; 4410 } 4411 } 4412 systim = (u64)systimel; 4413 systim |= (u64)systimeh << 32; 4414 4415 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) 4416 systim = e1000e_sanitize_systim(hw, systim); 4417 4418 return systim; 4419 } 4420 4421 /** 4422 * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 4423 * @adapter: board private structure to initialize 4424 * 4425 * e1000_sw_init initializes the Adapter private data structure. 4426 * Fields are initialized based on PCI device information and 4427 * OS network device settings (MTU size). 4428 **/ 4429 static int e1000_sw_init(struct e1000_adapter *adapter) 4430 { 4431 struct net_device *netdev = adapter->netdev; 4432 4433 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 4434 adapter->rx_ps_bsize0 = 128; 4435 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 4436 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4437 adapter->tx_ring_count = E1000_DEFAULT_TXD; 4438 adapter->rx_ring_count = E1000_DEFAULT_RXD; 4439 4440 spin_lock_init(&adapter->stats64_lock); 4441 4442 e1000e_set_interrupt_capability(adapter); 4443 4444 if (e1000_alloc_queues(adapter)) 4445 return -ENOMEM; 4446 4447 /* Setup hardware time stamping cyclecounter */ 4448 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 4449 adapter->cc.read = e1000e_cyclecounter_read; 4450 adapter->cc.mask = CYCLECOUNTER_MASK(64); 4451 adapter->cc.mult = 1; 4452 /* cc.shift set in e1000e_get_base_tininca() */ 4453 4454 spin_lock_init(&adapter->systim_lock); 4455 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); 4456 } 4457 4458 /* Explicitly disable IRQ since the NIC can be in any state. */ 4459 e1000_irq_disable(adapter); 4460 4461 set_bit(__E1000_DOWN, &adapter->state); 4462 return 0; 4463 } 4464 4465 /** 4466 * e1000_intr_msi_test - Interrupt Handler 4467 * @irq: interrupt number 4468 * @data: pointer to a network interface device structure 4469 **/ 4470 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) 4471 { 4472 struct net_device *netdev = data; 4473 struct e1000_adapter *adapter = netdev_priv(netdev); 4474 struct e1000_hw *hw = &adapter->hw; 4475 u32 icr = er32(ICR); 4476 4477 e_dbg("icr is %08X\n", icr); 4478 if (icr & E1000_ICR_RXSEQ) { 4479 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 4480 /* Force memory writes to complete before acknowledging the 4481 * interrupt is handled. 4482 */ 4483 wmb(); 4484 } 4485 4486 return IRQ_HANDLED; 4487 } 4488 4489 /** 4490 * e1000_test_msi_interrupt - Returns 0 for successful test 4491 * @adapter: board private struct 4492 * 4493 * code flow taken from tg3.c 4494 **/ 4495 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) 4496 { 4497 struct net_device *netdev = adapter->netdev; 4498 struct e1000_hw *hw = &adapter->hw; 4499 int err; 4500 4501 /* poll_enable hasn't been called yet, so don't need disable */ 4502 /* clear any pending events */ 4503 er32(ICR); 4504 4505 /* free the real vector and request a test handler */ 4506 e1000_free_irq(adapter); 4507 e1000e_reset_interrupt_capability(adapter); 4508 4509 /* Assume that the test fails, if it succeeds then the test 4510 * MSI irq handler will unset this flag 4511 */ 4512 adapter->flags |= FLAG_MSI_TEST_FAILED; 4513 4514 err = pci_enable_msi(adapter->pdev); 4515 if (err) 4516 goto msi_test_failed; 4517 4518 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, 4519 netdev->name, netdev); 4520 if (err) { 4521 pci_disable_msi(adapter->pdev); 4522 goto msi_test_failed; 4523 } 4524 4525 /* Force memory writes to complete before enabling and firing an 4526 * interrupt. 4527 */ 4528 wmb(); 4529 4530 e1000_irq_enable(adapter); 4531 4532 /* fire an unusual interrupt on the test handler */ 4533 ew32(ICS, E1000_ICS_RXSEQ); 4534 e1e_flush(); 4535 msleep(100); 4536 4537 e1000_irq_disable(adapter); 4538 4539 rmb(); /* read flags after interrupt has been fired */ 4540 4541 if (adapter->flags & FLAG_MSI_TEST_FAILED) { 4542 adapter->int_mode = E1000E_INT_MODE_LEGACY; 4543 e_info("MSI interrupt test failed, using legacy interrupt.\n"); 4544 } else { 4545 e_dbg("MSI interrupt test succeeded!\n"); 4546 } 4547 4548 free_irq(adapter->pdev->irq, netdev); 4549 pci_disable_msi(adapter->pdev); 4550 4551 msi_test_failed: 4552 e1000e_set_interrupt_capability(adapter); 4553 return e1000_request_irq(adapter); 4554 } 4555 4556 /** 4557 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored 4558 * @adapter: board private struct 4559 * 4560 * code flow taken from tg3.c, called with e1000 interrupts disabled. 4561 **/ 4562 static int e1000_test_msi(struct e1000_adapter *adapter) 4563 { 4564 int err; 4565 u16 pci_cmd; 4566 4567 if (!(adapter->flags & FLAG_MSI_ENABLED)) 4568 return 0; 4569 4570 /* disable SERR in case the MSI write causes a master abort */ 4571 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4572 if (pci_cmd & PCI_COMMAND_SERR) 4573 pci_write_config_word(adapter->pdev, PCI_COMMAND, 4574 pci_cmd & ~PCI_COMMAND_SERR); 4575 4576 err = e1000_test_msi_interrupt(adapter); 4577 4578 /* re-enable SERR */ 4579 if (pci_cmd & PCI_COMMAND_SERR) { 4580 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); 4581 pci_cmd |= PCI_COMMAND_SERR; 4582 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); 4583 } 4584 4585 return err; 4586 } 4587 4588 /** 4589 * e1000e_open - Called when a network interface is made active 4590 * @netdev: network interface device structure 4591 * 4592 * Returns 0 on success, negative value on failure 4593 * 4594 * The open entry point is called when a network interface is made 4595 * active by the system (IFF_UP). At this point all resources needed 4596 * for transmit and receive operations are allocated, the interrupt 4597 * handler is registered with the OS, the watchdog timer is started, 4598 * and the stack is notified that the interface is ready. 4599 **/ 4600 int e1000e_open(struct net_device *netdev) 4601 { 4602 struct e1000_adapter *adapter = netdev_priv(netdev); 4603 struct e1000_hw *hw = &adapter->hw; 4604 struct pci_dev *pdev = adapter->pdev; 4605 int err; 4606 4607 /* disallow open during test */ 4608 if (test_bit(__E1000_TESTING, &adapter->state)) 4609 return -EBUSY; 4610 4611 pm_runtime_get_sync(&pdev->dev); 4612 4613 netif_carrier_off(netdev); 4614 4615 /* allocate transmit descriptors */ 4616 err = e1000e_setup_tx_resources(adapter->tx_ring); 4617 if (err) 4618 goto err_setup_tx; 4619 4620 /* allocate receive descriptors */ 4621 err = e1000e_setup_rx_resources(adapter->rx_ring); 4622 if (err) 4623 goto err_setup_rx; 4624 4625 /* If AMT is enabled, let the firmware know that the network 4626 * interface is now open and reset the part to a known state. 4627 */ 4628 if (adapter->flags & FLAG_HAS_AMT) { 4629 e1000e_get_hw_control(adapter); 4630 e1000e_reset(adapter); 4631 } 4632 4633 e1000e_power_up_phy(adapter); 4634 4635 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4636 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) 4637 e1000_update_mng_vlan(adapter); 4638 4639 /* DMA latency requirement to workaround jumbo issue */ 4640 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 4641 PM_QOS_DEFAULT_VALUE); 4642 4643 /* before we allocate an interrupt, we must be ready to handle it. 4644 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4645 * as soon as we call pci_request_irq, so we have to setup our 4646 * clean_rx handler before we do so. 4647 */ 4648 e1000_configure(adapter); 4649 4650 err = e1000_request_irq(adapter); 4651 if (err) 4652 goto err_req_irq; 4653 4654 /* Work around PCIe errata with MSI interrupts causing some chipsets to 4655 * ignore e1000e MSI messages, which means we need to test our MSI 4656 * interrupt now 4657 */ 4658 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { 4659 err = e1000_test_msi(adapter); 4660 if (err) { 4661 e_err("Interrupt allocation failed\n"); 4662 goto err_req_irq; 4663 } 4664 } 4665 4666 /* From here on the code is the same as e1000e_up() */ 4667 clear_bit(__E1000_DOWN, &adapter->state); 4668 4669 napi_enable(&adapter->napi); 4670 4671 e1000_irq_enable(adapter); 4672 4673 adapter->tx_hang_recheck = false; 4674 netif_start_queue(netdev); 4675 4676 hw->mac.get_link_status = true; 4677 pm_runtime_put(&pdev->dev); 4678 4679 e1000e_trigger_lsc(adapter); 4680 4681 return 0; 4682 4683 err_req_irq: 4684 pm_qos_remove_request(&adapter->pm_qos_req); 4685 e1000e_release_hw_control(adapter); 4686 e1000_power_down_phy(adapter); 4687 e1000e_free_rx_resources(adapter->rx_ring); 4688 err_setup_rx: 4689 e1000e_free_tx_resources(adapter->tx_ring); 4690 err_setup_tx: 4691 e1000e_reset(adapter); 4692 pm_runtime_put_sync(&pdev->dev); 4693 4694 return err; 4695 } 4696 4697 /** 4698 * e1000e_close - Disables a network interface 4699 * @netdev: network interface device structure 4700 * 4701 * Returns 0, this is not allowed to fail 4702 * 4703 * The close entry point is called when an interface is de-activated 4704 * by the OS. The hardware is still under the drivers control, but 4705 * needs to be disabled. A global MAC reset is issued to stop the 4706 * hardware, and all transmit and receive resources are freed. 4707 **/ 4708 int e1000e_close(struct net_device *netdev) 4709 { 4710 struct e1000_adapter *adapter = netdev_priv(netdev); 4711 struct pci_dev *pdev = adapter->pdev; 4712 int count = E1000_CHECK_RESET_COUNT; 4713 4714 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 4715 usleep_range(10000, 20000); 4716 4717 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 4718 4719 pm_runtime_get_sync(&pdev->dev); 4720 4721 if (!test_bit(__E1000_DOWN, &adapter->state)) { 4722 e1000e_down(adapter, true); 4723 e1000_free_irq(adapter); 4724 4725 /* Link status message must follow this format */ 4726 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 4727 } 4728 4729 napi_disable(&adapter->napi); 4730 4731 e1000e_free_tx_resources(adapter->tx_ring); 4732 e1000e_free_rx_resources(adapter->rx_ring); 4733 4734 /* kill manageability vlan ID if supported, but not if a vlan with 4735 * the same ID is registered on the host OS (let 8021q kill it) 4736 */ 4737 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 4738 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), 4739 adapter->mng_vlan_id); 4740 4741 /* If AMT is enabled, let the firmware know that the network 4742 * interface is now closed 4743 */ 4744 if ((adapter->flags & FLAG_HAS_AMT) && 4745 !test_bit(__E1000_TESTING, &adapter->state)) 4746 e1000e_release_hw_control(adapter); 4747 4748 pm_qos_remove_request(&adapter->pm_qos_req); 4749 4750 pm_runtime_put_sync(&pdev->dev); 4751 4752 return 0; 4753 } 4754 4755 /** 4756 * e1000_set_mac - Change the Ethernet Address of the NIC 4757 * @netdev: network interface device structure 4758 * @p: pointer to an address structure 4759 * 4760 * Returns 0 on success, negative on failure 4761 **/ 4762 static int e1000_set_mac(struct net_device *netdev, void *p) 4763 { 4764 struct e1000_adapter *adapter = netdev_priv(netdev); 4765 struct e1000_hw *hw = &adapter->hw; 4766 struct sockaddr *addr = p; 4767 4768 if (!is_valid_ether_addr(addr->sa_data)) 4769 return -EADDRNOTAVAIL; 4770 4771 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 4772 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); 4773 4774 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 4775 4776 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { 4777 /* activate the work around */ 4778 e1000e_set_laa_state_82571(&adapter->hw, 1); 4779 4780 /* Hold a copy of the LAA in RAR[14] This is done so that 4781 * between the time RAR[0] gets clobbered and the time it 4782 * gets fixed (in e1000_watchdog), the actual LAA is in one 4783 * of the RARs and no incoming packets directed to this port 4784 * are dropped. Eventually the LAA will be in RAR[0] and 4785 * RAR[14] 4786 */ 4787 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 4788 adapter->hw.mac.rar_entry_count - 1); 4789 } 4790 4791 return 0; 4792 } 4793 4794 /** 4795 * e1000e_update_phy_task - work thread to update phy 4796 * @work: pointer to our work struct 4797 * 4798 * this worker thread exists because we must acquire a 4799 * semaphore to read the phy, which we could msleep while 4800 * waiting for it, and we can't msleep in a timer. 4801 **/ 4802 static void e1000e_update_phy_task(struct work_struct *work) 4803 { 4804 struct e1000_adapter *adapter = container_of(work, 4805 struct e1000_adapter, 4806 update_phy_task); 4807 struct e1000_hw *hw = &adapter->hw; 4808 4809 if (test_bit(__E1000_DOWN, &adapter->state)) 4810 return; 4811 4812 e1000_get_phy_info(hw); 4813 4814 /* Enable EEE on 82579 after link up */ 4815 if (hw->phy.type >= e1000_phy_82579) 4816 e1000_set_eee_pchlan(hw); 4817 } 4818 4819 /** 4820 * e1000_update_phy_info - timre call-back to update PHY info 4821 * @data: pointer to adapter cast into an unsigned long 4822 * 4823 * Need to wait a few seconds after link up to get diagnostic information from 4824 * the phy 4825 **/ 4826 static void e1000_update_phy_info(struct timer_list *t) 4827 { 4828 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); 4829 4830 if (test_bit(__E1000_DOWN, &adapter->state)) 4831 return; 4832 4833 schedule_work(&adapter->update_phy_task); 4834 } 4835 4836 /** 4837 * e1000e_update_phy_stats - Update the PHY statistics counters 4838 * @adapter: board private structure 4839 * 4840 * Read/clear the upper 16-bit PHY registers and read/accumulate lower 4841 **/ 4842 static void e1000e_update_phy_stats(struct e1000_adapter *adapter) 4843 { 4844 struct e1000_hw *hw = &adapter->hw; 4845 s32 ret_val; 4846 u16 phy_data; 4847 4848 ret_val = hw->phy.ops.acquire(hw); 4849 if (ret_val) 4850 return; 4851 4852 /* A page set is expensive so check if already on desired page. 4853 * If not, set to the page with the PHY status registers. 4854 */ 4855 hw->phy.addr = 1; 4856 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4857 &phy_data); 4858 if (ret_val) 4859 goto release; 4860 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { 4861 ret_val = hw->phy.ops.set_page(hw, 4862 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4863 if (ret_val) 4864 goto release; 4865 } 4866 4867 /* Single Collision Count */ 4868 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4869 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4870 if (!ret_val) 4871 adapter->stats.scc += phy_data; 4872 4873 /* Excessive Collision Count */ 4874 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4875 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4876 if (!ret_val) 4877 adapter->stats.ecol += phy_data; 4878 4879 /* Multiple Collision Count */ 4880 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4881 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4882 if (!ret_val) 4883 adapter->stats.mcc += phy_data; 4884 4885 /* Late Collision Count */ 4886 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4887 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4888 if (!ret_val) 4889 adapter->stats.latecol += phy_data; 4890 4891 /* Collision Count - also used for adaptive IFS */ 4892 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4893 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4894 if (!ret_val) 4895 hw->mac.collision_delta = phy_data; 4896 4897 /* Defer Count */ 4898 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4899 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4900 if (!ret_val) 4901 adapter->stats.dc += phy_data; 4902 4903 /* Transmit with no CRS */ 4904 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4905 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4906 if (!ret_val) 4907 adapter->stats.tncrs += phy_data; 4908 4909 release: 4910 hw->phy.ops.release(hw); 4911 } 4912 4913 /** 4914 * e1000e_update_stats - Update the board statistics counters 4915 * @adapter: board private structure 4916 **/ 4917 static void e1000e_update_stats(struct e1000_adapter *adapter) 4918 { 4919 struct net_device *netdev = adapter->netdev; 4920 struct e1000_hw *hw = &adapter->hw; 4921 struct pci_dev *pdev = adapter->pdev; 4922 4923 /* Prevent stats update while adapter is being reset, or if the pci 4924 * connection is down. 4925 */ 4926 if (adapter->link_speed == 0) 4927 return; 4928 if (pci_channel_offline(pdev)) 4929 return; 4930 4931 adapter->stats.crcerrs += er32(CRCERRS); 4932 adapter->stats.gprc += er32(GPRC); 4933 adapter->stats.gorc += er32(GORCL); 4934 er32(GORCH); /* Clear gorc */ 4935 adapter->stats.bprc += er32(BPRC); 4936 adapter->stats.mprc += er32(MPRC); 4937 adapter->stats.roc += er32(ROC); 4938 4939 adapter->stats.mpc += er32(MPC); 4940 4941 /* Half-duplex statistics */ 4942 if (adapter->link_duplex == HALF_DUPLEX) { 4943 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { 4944 e1000e_update_phy_stats(adapter); 4945 } else { 4946 adapter->stats.scc += er32(SCC); 4947 adapter->stats.ecol += er32(ECOL); 4948 adapter->stats.mcc += er32(MCC); 4949 adapter->stats.latecol += er32(LATECOL); 4950 adapter->stats.dc += er32(DC); 4951 4952 hw->mac.collision_delta = er32(COLC); 4953 4954 if ((hw->mac.type != e1000_82574) && 4955 (hw->mac.type != e1000_82583)) 4956 adapter->stats.tncrs += er32(TNCRS); 4957 } 4958 adapter->stats.colc += hw->mac.collision_delta; 4959 } 4960 4961 adapter->stats.xonrxc += er32(XONRXC); 4962 adapter->stats.xontxc += er32(XONTXC); 4963 adapter->stats.xoffrxc += er32(XOFFRXC); 4964 adapter->stats.xofftxc += er32(XOFFTXC); 4965 adapter->stats.gptc += er32(GPTC); 4966 adapter->stats.gotc += er32(GOTCL); 4967 er32(GOTCH); /* Clear gotc */ 4968 adapter->stats.rnbc += er32(RNBC); 4969 adapter->stats.ruc += er32(RUC); 4970 4971 adapter->stats.mptc += er32(MPTC); 4972 adapter->stats.bptc += er32(BPTC); 4973 4974 /* used for adaptive IFS */ 4975 4976 hw->mac.tx_packet_delta = er32(TPT); 4977 adapter->stats.tpt += hw->mac.tx_packet_delta; 4978 4979 adapter->stats.algnerrc += er32(ALGNERRC); 4980 adapter->stats.rxerrc += er32(RXERRC); 4981 adapter->stats.cexterr += er32(CEXTERR); 4982 adapter->stats.tsctc += er32(TSCTC); 4983 adapter->stats.tsctfc += er32(TSCTFC); 4984 4985 /* Fill out the OS statistics structure */ 4986 netdev->stats.multicast = adapter->stats.mprc; 4987 netdev->stats.collisions = adapter->stats.colc; 4988 4989 /* Rx Errors */ 4990 4991 /* RLEC on some newer hardware can be incorrect so build 4992 * our own version based on RUC and ROC 4993 */ 4994 netdev->stats.rx_errors = adapter->stats.rxerrc + 4995 adapter->stats.crcerrs + adapter->stats.algnerrc + 4996 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 4997 netdev->stats.rx_length_errors = adapter->stats.ruc + 4998 adapter->stats.roc; 4999 netdev->stats.rx_crc_errors = adapter->stats.crcerrs; 5000 netdev->stats.rx_frame_errors = adapter->stats.algnerrc; 5001 netdev->stats.rx_missed_errors = adapter->stats.mpc; 5002 5003 /* Tx Errors */ 5004 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5005 netdev->stats.tx_aborted_errors = adapter->stats.ecol; 5006 netdev->stats.tx_window_errors = adapter->stats.latecol; 5007 netdev->stats.tx_carrier_errors = adapter->stats.tncrs; 5008 5009 /* Tx Dropped needs to be maintained elsewhere */ 5010 5011 /* Management Stats */ 5012 adapter->stats.mgptc += er32(MGTPTC); 5013 adapter->stats.mgprc += er32(MGTPRC); 5014 adapter->stats.mgpdc += er32(MGTPDC); 5015 5016 /* Correctable ECC Errors */ 5017 if (hw->mac.type >= e1000_pch_lpt) { 5018 u32 pbeccsts = er32(PBECCSTS); 5019 5020 adapter->corr_errors += 5021 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5022 adapter->uncorr_errors += 5023 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5024 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5025 } 5026 } 5027 5028 /** 5029 * e1000_phy_read_status - Update the PHY register status snapshot 5030 * @adapter: board private structure 5031 **/ 5032 static void e1000_phy_read_status(struct e1000_adapter *adapter) 5033 { 5034 struct e1000_hw *hw = &adapter->hw; 5035 struct e1000_phy_regs *phy = &adapter->phy_regs; 5036 5037 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && 5038 (er32(STATUS) & E1000_STATUS_LU) && 5039 (adapter->hw.phy.media_type == e1000_media_type_copper)) { 5040 int ret_val; 5041 5042 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); 5043 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); 5044 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); 5045 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); 5046 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); 5047 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); 5048 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); 5049 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); 5050 if (ret_val) 5051 e_warn("Error reading PHY register\n"); 5052 } else { 5053 /* Do not read PHY registers if link is not up 5054 * Set values to typical power-on defaults 5055 */ 5056 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 5057 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | 5058 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | 5059 BMSR_ERCAP); 5060 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | 5061 ADVERTISE_ALL | ADVERTISE_CSMA); 5062 phy->lpa = 0; 5063 phy->expansion = EXPANSION_ENABLENPAGE; 5064 phy->ctrl1000 = ADVERTISE_1000FULL; 5065 phy->stat1000 = 0; 5066 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); 5067 } 5068 } 5069 5070 static void e1000_print_link_info(struct e1000_adapter *adapter) 5071 { 5072 struct e1000_hw *hw = &adapter->hw; 5073 u32 ctrl = er32(CTRL); 5074 5075 /* Link status message must follow this format for user tools */ 5076 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5077 adapter->netdev->name, adapter->link_speed, 5078 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", 5079 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : 5080 (ctrl & E1000_CTRL_RFCE) ? "Rx" : 5081 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); 5082 } 5083 5084 static bool e1000e_has_link(struct e1000_adapter *adapter) 5085 { 5086 struct e1000_hw *hw = &adapter->hw; 5087 bool link_active = false; 5088 s32 ret_val = 0; 5089 5090 /* get_link_status is set on LSC (link status) interrupt or 5091 * Rx sequence error interrupt. get_link_status will stay 5092 * true until the check_for_link establishes link 5093 * for copper adapters ONLY 5094 */ 5095 switch (hw->phy.media_type) { 5096 case e1000_media_type_copper: 5097 if (hw->mac.get_link_status) { 5098 ret_val = hw->mac.ops.check_for_link(hw); 5099 link_active = ret_val > 0; 5100 } else { 5101 link_active = true; 5102 } 5103 break; 5104 case e1000_media_type_fiber: 5105 ret_val = hw->mac.ops.check_for_link(hw); 5106 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 5107 break; 5108 case e1000_media_type_internal_serdes: 5109 ret_val = hw->mac.ops.check_for_link(hw); 5110 link_active = hw->mac.serdes_has_link; 5111 break; 5112 default: 5113 case e1000_media_type_unknown: 5114 break; 5115 } 5116 5117 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && 5118 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { 5119 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ 5120 e_info("Gigabit has been disabled, downgrading speed\n"); 5121 } 5122 5123 return link_active; 5124 } 5125 5126 static void e1000e_enable_receives(struct e1000_adapter *adapter) 5127 { 5128 /* make sure the receive unit is started */ 5129 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && 5130 (adapter->flags & FLAG_RESTART_NOW)) { 5131 struct e1000_hw *hw = &adapter->hw; 5132 u32 rctl = er32(RCTL); 5133 5134 ew32(RCTL, rctl | E1000_RCTL_EN); 5135 adapter->flags &= ~FLAG_RESTART_NOW; 5136 } 5137 } 5138 5139 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) 5140 { 5141 struct e1000_hw *hw = &adapter->hw; 5142 5143 /* With 82574 controllers, PHY needs to be checked periodically 5144 * for hung state and reset, if two calls return true 5145 */ 5146 if (e1000_check_phy_82574(hw)) 5147 adapter->phy_hang_count++; 5148 else 5149 adapter->phy_hang_count = 0; 5150 5151 if (adapter->phy_hang_count > 1) { 5152 adapter->phy_hang_count = 0; 5153 e_dbg("PHY appears hung - resetting\n"); 5154 schedule_work(&adapter->reset_task); 5155 } 5156 } 5157 5158 /** 5159 * e1000_watchdog - Timer Call-back 5160 * @data: pointer to adapter cast into an unsigned long 5161 **/ 5162 static void e1000_watchdog(struct timer_list *t) 5163 { 5164 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5165 5166 /* Do the rest outside of interrupt context */ 5167 schedule_work(&adapter->watchdog_task); 5168 5169 /* TODO: make this use queue_delayed_work() */ 5170 } 5171 5172 static void e1000_watchdog_task(struct work_struct *work) 5173 { 5174 struct e1000_adapter *adapter = container_of(work, 5175 struct e1000_adapter, 5176 watchdog_task); 5177 struct net_device *netdev = adapter->netdev; 5178 struct e1000_mac_info *mac = &adapter->hw.mac; 5179 struct e1000_phy_info *phy = &adapter->hw.phy; 5180 struct e1000_ring *tx_ring = adapter->tx_ring; 5181 struct e1000_hw *hw = &adapter->hw; 5182 u32 link, tctl; 5183 5184 if (test_bit(__E1000_DOWN, &adapter->state)) 5185 return; 5186 5187 link = e1000e_has_link(adapter); 5188 if ((netif_carrier_ok(netdev)) && link) { 5189 /* Cancel scheduled suspend requests. */ 5190 pm_runtime_resume(netdev->dev.parent); 5191 5192 e1000e_enable_receives(adapter); 5193 goto link_up; 5194 } 5195 5196 if ((e1000e_enable_tx_pkt_filtering(hw)) && 5197 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) 5198 e1000_update_mng_vlan(adapter); 5199 5200 if (link) { 5201 if (!netif_carrier_ok(netdev)) { 5202 bool txb2b = true; 5203 5204 /* Cancel scheduled suspend requests. */ 5205 pm_runtime_resume(netdev->dev.parent); 5206 5207 /* update snapshot of PHY registers on LSC */ 5208 e1000_phy_read_status(adapter); 5209 mac->ops.get_link_up_info(&adapter->hw, 5210 &adapter->link_speed, 5211 &adapter->link_duplex); 5212 e1000_print_link_info(adapter); 5213 5214 /* check if SmartSpeed worked */ 5215 e1000e_check_downshift(hw); 5216 if (phy->speed_downgraded) 5217 netdev_warn(netdev, 5218 "Link Speed was downgraded by SmartSpeed\n"); 5219 5220 /* On supported PHYs, check for duplex mismatch only 5221 * if link has autonegotiated at 10/100 half 5222 */ 5223 if ((hw->phy.type == e1000_phy_igp_3 || 5224 hw->phy.type == e1000_phy_bm) && 5225 hw->mac.autoneg && 5226 (adapter->link_speed == SPEED_10 || 5227 adapter->link_speed == SPEED_100) && 5228 (adapter->link_duplex == HALF_DUPLEX)) { 5229 u16 autoneg_exp; 5230 5231 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); 5232 5233 if (!(autoneg_exp & EXPANSION_NWAY)) 5234 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); 5235 } 5236 5237 /* adjust timeout factor according to speed/duplex */ 5238 adapter->tx_timeout_factor = 1; 5239 switch (adapter->link_speed) { 5240 case SPEED_10: 5241 txb2b = false; 5242 adapter->tx_timeout_factor = 16; 5243 break; 5244 case SPEED_100: 5245 txb2b = false; 5246 adapter->tx_timeout_factor = 10; 5247 break; 5248 } 5249 5250 /* workaround: re-program speed mode bit after 5251 * link-up event 5252 */ 5253 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 5254 !txb2b) { 5255 u32 tarc0; 5256 5257 tarc0 = er32(TARC(0)); 5258 tarc0 &= ~SPEED_MODE_BIT; 5259 ew32(TARC(0), tarc0); 5260 } 5261 5262 /* disable TSO for pcie and 10/100 speeds, to avoid 5263 * some hardware issues 5264 */ 5265 if (!(adapter->flags & FLAG_TSO_FORCE)) { 5266 switch (adapter->link_speed) { 5267 case SPEED_10: 5268 case SPEED_100: 5269 e_info("10/100 speed: disabling TSO\n"); 5270 netdev->features &= ~NETIF_F_TSO; 5271 netdev->features &= ~NETIF_F_TSO6; 5272 break; 5273 case SPEED_1000: 5274 netdev->features |= NETIF_F_TSO; 5275 netdev->features |= NETIF_F_TSO6; 5276 break; 5277 default: 5278 /* oops */ 5279 break; 5280 } 5281 } 5282 5283 /* enable transmits in the hardware, need to do this 5284 * after setting TARC(0) 5285 */ 5286 tctl = er32(TCTL); 5287 tctl |= E1000_TCTL_EN; 5288 ew32(TCTL, tctl); 5289 5290 /* Perform any post-link-up configuration before 5291 * reporting link up. 5292 */ 5293 if (phy->ops.cfg_on_link_up) 5294 phy->ops.cfg_on_link_up(hw); 5295 5296 netif_carrier_on(netdev); 5297 5298 if (!test_bit(__E1000_DOWN, &adapter->state)) 5299 mod_timer(&adapter->phy_info_timer, 5300 round_jiffies(jiffies + 2 * HZ)); 5301 } 5302 } else { 5303 if (netif_carrier_ok(netdev)) { 5304 adapter->link_speed = 0; 5305 adapter->link_duplex = 0; 5306 /* Link status message must follow this format */ 5307 pr_info("%s NIC Link is Down\n", adapter->netdev->name); 5308 netif_carrier_off(netdev); 5309 if (!test_bit(__E1000_DOWN, &adapter->state)) 5310 mod_timer(&adapter->phy_info_timer, 5311 round_jiffies(jiffies + 2 * HZ)); 5312 5313 /* 8000ES2LAN requires a Rx packet buffer work-around 5314 * on link down event; reset the controller to flush 5315 * the Rx packet buffer. 5316 */ 5317 if (adapter->flags & FLAG_RX_NEEDS_RESTART) 5318 adapter->flags |= FLAG_RESTART_NOW; 5319 else 5320 pm_schedule_suspend(netdev->dev.parent, 5321 LINK_TIMEOUT); 5322 } 5323 } 5324 5325 link_up: 5326 spin_lock(&adapter->stats64_lock); 5327 e1000e_update_stats(adapter); 5328 5329 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; 5330 adapter->tpt_old = adapter->stats.tpt; 5331 mac->collision_delta = adapter->stats.colc - adapter->colc_old; 5332 adapter->colc_old = adapter->stats.colc; 5333 5334 adapter->gorc = adapter->stats.gorc - adapter->gorc_old; 5335 adapter->gorc_old = adapter->stats.gorc; 5336 adapter->gotc = adapter->stats.gotc - adapter->gotc_old; 5337 adapter->gotc_old = adapter->stats.gotc; 5338 spin_unlock(&adapter->stats64_lock); 5339 5340 /* If the link is lost the controller stops DMA, but 5341 * if there is queued Tx work it cannot be done. So 5342 * reset the controller to flush the Tx packet buffers. 5343 */ 5344 if (!netif_carrier_ok(netdev) && 5345 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) 5346 adapter->flags |= FLAG_RESTART_NOW; 5347 5348 /* If reset is necessary, do it outside of interrupt context. */ 5349 if (adapter->flags & FLAG_RESTART_NOW) { 5350 schedule_work(&adapter->reset_task); 5351 /* return immediately since reset is imminent */ 5352 return; 5353 } 5354 5355 e1000e_update_adaptive(&adapter->hw); 5356 5357 /* Simple mode for Interrupt Throttle Rate (ITR) */ 5358 if (adapter->itr_setting == 4) { 5359 /* Symmetric Tx/Rx gets a reduced ITR=2000; 5360 * Total asymmetrical Tx or Rx gets ITR=8000; 5361 * everyone else is between 2000-8000. 5362 */ 5363 u32 goc = (adapter->gotc + adapter->gorc) / 10000; 5364 u32 dif = (adapter->gotc > adapter->gorc ? 5365 adapter->gotc - adapter->gorc : 5366 adapter->gorc - adapter->gotc) / 10000; 5367 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; 5368 5369 e1000e_write_itr(adapter, itr); 5370 } 5371 5372 /* Cause software interrupt to ensure Rx ring is cleaned */ 5373 if (adapter->msix_entries) 5374 ew32(ICS, adapter->rx_ring->ims_val); 5375 else 5376 ew32(ICS, E1000_ICS_RXDMT0); 5377 5378 /* flush pending descriptors to memory before detecting Tx hang */ 5379 e1000e_flush_descriptors(adapter); 5380 5381 /* Force detection of hung controller every watchdog period */ 5382 adapter->detect_tx_hung = true; 5383 5384 /* With 82571 controllers, LAA may be overwritten due to controller 5385 * reset from the other port. Set the appropriate LAA in RAR[0] 5386 */ 5387 if (e1000e_get_laa_state_82571(hw)) 5388 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); 5389 5390 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) 5391 e1000e_check_82574_phy_workaround(adapter); 5392 5393 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ 5394 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { 5395 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && 5396 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { 5397 er32(RXSTMPH); 5398 adapter->rx_hwtstamp_cleared++; 5399 } else { 5400 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; 5401 } 5402 } 5403 5404 /* Reset the timer */ 5405 if (!test_bit(__E1000_DOWN, &adapter->state)) 5406 mod_timer(&adapter->watchdog_timer, 5407 round_jiffies(jiffies + 2 * HZ)); 5408 } 5409 5410 #define E1000_TX_FLAGS_CSUM 0x00000001 5411 #define E1000_TX_FLAGS_VLAN 0x00000002 5412 #define E1000_TX_FLAGS_TSO 0x00000004 5413 #define E1000_TX_FLAGS_IPV4 0x00000008 5414 #define E1000_TX_FLAGS_NO_FCS 0x00000010 5415 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 5416 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 5417 #define E1000_TX_FLAGS_VLAN_SHIFT 16 5418 5419 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, 5420 __be16 protocol) 5421 { 5422 struct e1000_context_desc *context_desc; 5423 struct e1000_buffer *buffer_info; 5424 unsigned int i; 5425 u32 cmd_length = 0; 5426 u16 ipcse = 0, mss; 5427 u8 ipcss, ipcso, tucss, tucso, hdr_len; 5428 int err; 5429 5430 if (!skb_is_gso(skb)) 5431 return 0; 5432 5433 err = skb_cow_head(skb, 0); 5434 if (err < 0) 5435 return err; 5436 5437 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5438 mss = skb_shinfo(skb)->gso_size; 5439 if (protocol == htons(ETH_P_IP)) { 5440 struct iphdr *iph = ip_hdr(skb); 5441 iph->tot_len = 0; 5442 iph->check = 0; 5443 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 5444 0, IPPROTO_TCP, 0); 5445 cmd_length = E1000_TXD_CMD_IP; 5446 ipcse = skb_transport_offset(skb) - 1; 5447 } else if (skb_is_gso_v6(skb)) { 5448 ipv6_hdr(skb)->payload_len = 0; 5449 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 5450 &ipv6_hdr(skb)->daddr, 5451 0, IPPROTO_TCP, 0); 5452 ipcse = 0; 5453 } 5454 ipcss = skb_network_offset(skb); 5455 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; 5456 tucss = skb_transport_offset(skb); 5457 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; 5458 5459 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 5460 E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); 5461 5462 i = tx_ring->next_to_use; 5463 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5464 buffer_info = &tx_ring->buffer_info[i]; 5465 5466 context_desc->lower_setup.ip_fields.ipcss = ipcss; 5467 context_desc->lower_setup.ip_fields.ipcso = ipcso; 5468 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); 5469 context_desc->upper_setup.tcp_fields.tucss = tucss; 5470 context_desc->upper_setup.tcp_fields.tucso = tucso; 5471 context_desc->upper_setup.tcp_fields.tucse = 0; 5472 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); 5473 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; 5474 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 5475 5476 buffer_info->time_stamp = jiffies; 5477 buffer_info->next_to_watch = i; 5478 5479 i++; 5480 if (i == tx_ring->count) 5481 i = 0; 5482 tx_ring->next_to_use = i; 5483 5484 return 1; 5485 } 5486 5487 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, 5488 __be16 protocol) 5489 { 5490 struct e1000_adapter *adapter = tx_ring->adapter; 5491 struct e1000_context_desc *context_desc; 5492 struct e1000_buffer *buffer_info; 5493 unsigned int i; 5494 u8 css; 5495 u32 cmd_len = E1000_TXD_CMD_DEXT; 5496 5497 if (skb->ip_summed != CHECKSUM_PARTIAL) 5498 return false; 5499 5500 switch (protocol) { 5501 case cpu_to_be16(ETH_P_IP): 5502 if (ip_hdr(skb)->protocol == IPPROTO_TCP) 5503 cmd_len |= E1000_TXD_CMD_TCP; 5504 break; 5505 case cpu_to_be16(ETH_P_IPV6): 5506 /* XXX not handling all IPV6 headers */ 5507 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) 5508 cmd_len |= E1000_TXD_CMD_TCP; 5509 break; 5510 default: 5511 if (unlikely(net_ratelimit())) 5512 e_warn("checksum_partial proto=%x!\n", 5513 be16_to_cpu(protocol)); 5514 break; 5515 } 5516 5517 css = skb_checksum_start_offset(skb); 5518 5519 i = tx_ring->next_to_use; 5520 buffer_info = &tx_ring->buffer_info[i]; 5521 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 5522 5523 context_desc->lower_setup.ip_config = 0; 5524 context_desc->upper_setup.tcp_fields.tucss = css; 5525 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; 5526 context_desc->upper_setup.tcp_fields.tucse = 0; 5527 context_desc->tcp_seg_setup.data = 0; 5528 context_desc->cmd_and_length = cpu_to_le32(cmd_len); 5529 5530 buffer_info->time_stamp = jiffies; 5531 buffer_info->next_to_watch = i; 5532 5533 i++; 5534 if (i == tx_ring->count) 5535 i = 0; 5536 tx_ring->next_to_use = i; 5537 5538 return true; 5539 } 5540 5541 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, 5542 unsigned int first, unsigned int max_per_txd, 5543 unsigned int nr_frags) 5544 { 5545 struct e1000_adapter *adapter = tx_ring->adapter; 5546 struct pci_dev *pdev = adapter->pdev; 5547 struct e1000_buffer *buffer_info; 5548 unsigned int len = skb_headlen(skb); 5549 unsigned int offset = 0, size, count = 0, i; 5550 unsigned int f, bytecount, segs; 5551 5552 i = tx_ring->next_to_use; 5553 5554 while (len) { 5555 buffer_info = &tx_ring->buffer_info[i]; 5556 size = min(len, max_per_txd); 5557 5558 buffer_info->length = size; 5559 buffer_info->time_stamp = jiffies; 5560 buffer_info->next_to_watch = i; 5561 buffer_info->dma = dma_map_single(&pdev->dev, 5562 skb->data + offset, 5563 size, DMA_TO_DEVICE); 5564 buffer_info->mapped_as_page = false; 5565 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5566 goto dma_error; 5567 5568 len -= size; 5569 offset += size; 5570 count++; 5571 5572 if (len) { 5573 i++; 5574 if (i == tx_ring->count) 5575 i = 0; 5576 } 5577 } 5578 5579 for (f = 0; f < nr_frags; f++) { 5580 const struct skb_frag_struct *frag; 5581 5582 frag = &skb_shinfo(skb)->frags[f]; 5583 len = skb_frag_size(frag); 5584 offset = 0; 5585 5586 while (len) { 5587 i++; 5588 if (i == tx_ring->count) 5589 i = 0; 5590 5591 buffer_info = &tx_ring->buffer_info[i]; 5592 size = min(len, max_per_txd); 5593 5594 buffer_info->length = size; 5595 buffer_info->time_stamp = jiffies; 5596 buffer_info->next_to_watch = i; 5597 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, 5598 offset, size, 5599 DMA_TO_DEVICE); 5600 buffer_info->mapped_as_page = true; 5601 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) 5602 goto dma_error; 5603 5604 len -= size; 5605 offset += size; 5606 count++; 5607 } 5608 } 5609 5610 segs = skb_shinfo(skb)->gso_segs ? : 1; 5611 /* multiply data chunks by size of headers */ 5612 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; 5613 5614 tx_ring->buffer_info[i].skb = skb; 5615 tx_ring->buffer_info[i].segs = segs; 5616 tx_ring->buffer_info[i].bytecount = bytecount; 5617 tx_ring->buffer_info[first].next_to_watch = i; 5618 5619 return count; 5620 5621 dma_error: 5622 dev_err(&pdev->dev, "Tx DMA map failed\n"); 5623 buffer_info->dma = 0; 5624 if (count) 5625 count--; 5626 5627 while (count--) { 5628 if (i == 0) 5629 i += tx_ring->count; 5630 i--; 5631 buffer_info = &tx_ring->buffer_info[i]; 5632 e1000_put_txbuf(tx_ring, buffer_info, true); 5633 } 5634 5635 return 0; 5636 } 5637 5638 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) 5639 { 5640 struct e1000_adapter *adapter = tx_ring->adapter; 5641 struct e1000_tx_desc *tx_desc = NULL; 5642 struct e1000_buffer *buffer_info; 5643 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; 5644 unsigned int i; 5645 5646 if (tx_flags & E1000_TX_FLAGS_TSO) { 5647 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 5648 E1000_TXD_CMD_TSE; 5649 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5650 5651 if (tx_flags & E1000_TX_FLAGS_IPV4) 5652 txd_upper |= E1000_TXD_POPTS_IXSM << 8; 5653 } 5654 5655 if (tx_flags & E1000_TX_FLAGS_CSUM) { 5656 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5657 txd_upper |= E1000_TXD_POPTS_TXSM << 8; 5658 } 5659 5660 if (tx_flags & E1000_TX_FLAGS_VLAN) { 5661 txd_lower |= E1000_TXD_CMD_VLE; 5662 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); 5663 } 5664 5665 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5666 txd_lower &= ~(E1000_TXD_CMD_IFCS); 5667 5668 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { 5669 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 5670 txd_upper |= E1000_TXD_EXTCMD_TSTAMP; 5671 } 5672 5673 i = tx_ring->next_to_use; 5674 5675 do { 5676 buffer_info = &tx_ring->buffer_info[i]; 5677 tx_desc = E1000_TX_DESC(*tx_ring, i); 5678 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 5679 tx_desc->lower.data = cpu_to_le32(txd_lower | 5680 buffer_info->length); 5681 tx_desc->upper.data = cpu_to_le32(txd_upper); 5682 5683 i++; 5684 if (i == tx_ring->count) 5685 i = 0; 5686 } while (--count > 0); 5687 5688 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); 5689 5690 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ 5691 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 5692 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 5693 5694 /* Force memory writes to complete before letting h/w 5695 * know there are new descriptors to fetch. (Only 5696 * applicable for weak-ordered memory model archs, 5697 * such as IA-64). 5698 */ 5699 wmb(); 5700 5701 tx_ring->next_to_use = i; 5702 } 5703 5704 #define MINIMUM_DHCP_PACKET_SIZE 282 5705 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, 5706 struct sk_buff *skb) 5707 { 5708 struct e1000_hw *hw = &adapter->hw; 5709 u16 length, offset; 5710 5711 if (skb_vlan_tag_present(skb) && 5712 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && 5713 (adapter->hw.mng_cookie.status & 5714 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) 5715 return 0; 5716 5717 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) 5718 return 0; 5719 5720 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) 5721 return 0; 5722 5723 { 5724 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); 5725 struct udphdr *udp; 5726 5727 if (ip->protocol != IPPROTO_UDP) 5728 return 0; 5729 5730 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); 5731 if (ntohs(udp->dest) != 67) 5732 return 0; 5733 5734 offset = (u8 *)udp + 8 - skb->data; 5735 length = skb->len - offset; 5736 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); 5737 } 5738 5739 return 0; 5740 } 5741 5742 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5743 { 5744 struct e1000_adapter *adapter = tx_ring->adapter; 5745 5746 netif_stop_queue(adapter->netdev); 5747 /* Herbert's original patch had: 5748 * smp_mb__after_netif_stop_queue(); 5749 * but since that doesn't exist yet, just open code it. 5750 */ 5751 smp_mb(); 5752 5753 /* We need to check again in a case another CPU has just 5754 * made room available. 5755 */ 5756 if (e1000_desc_unused(tx_ring) < size) 5757 return -EBUSY; 5758 5759 /* A reprieve! */ 5760 netif_start_queue(adapter->netdev); 5761 ++adapter->restart_queue; 5762 return 0; 5763 } 5764 5765 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) 5766 { 5767 BUG_ON(size > tx_ring->count); 5768 5769 if (e1000_desc_unused(tx_ring) >= size) 5770 return 0; 5771 return __e1000_maybe_stop_tx(tx_ring, size); 5772 } 5773 5774 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, 5775 struct net_device *netdev) 5776 { 5777 struct e1000_adapter *adapter = netdev_priv(netdev); 5778 struct e1000_ring *tx_ring = adapter->tx_ring; 5779 unsigned int first; 5780 unsigned int tx_flags = 0; 5781 unsigned int len = skb_headlen(skb); 5782 unsigned int nr_frags; 5783 unsigned int mss; 5784 int count = 0; 5785 int tso; 5786 unsigned int f; 5787 __be16 protocol = vlan_get_protocol(skb); 5788 5789 if (test_bit(__E1000_DOWN, &adapter->state)) { 5790 dev_kfree_skb_any(skb); 5791 return NETDEV_TX_OK; 5792 } 5793 5794 if (skb->len <= 0) { 5795 dev_kfree_skb_any(skb); 5796 return NETDEV_TX_OK; 5797 } 5798 5799 /* The minimum packet size with TCTL.PSP set is 17 bytes so 5800 * pad skb in order to meet this minimum size requirement 5801 */ 5802 if (skb_put_padto(skb, 17)) 5803 return NETDEV_TX_OK; 5804 5805 mss = skb_shinfo(skb)->gso_size; 5806 if (mss) { 5807 u8 hdr_len; 5808 5809 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 5810 * points to just header, pull a few bytes of payload from 5811 * frags into skb->data 5812 */ 5813 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5814 /* we do this workaround for ES2LAN, but it is un-necessary, 5815 * avoiding it could save a lot of cycles 5816 */ 5817 if (skb->data_len && (hdr_len == len)) { 5818 unsigned int pull_size; 5819 5820 pull_size = min_t(unsigned int, 4, skb->data_len); 5821 if (!__pskb_pull_tail(skb, pull_size)) { 5822 e_err("__pskb_pull_tail failed.\n"); 5823 dev_kfree_skb_any(skb); 5824 return NETDEV_TX_OK; 5825 } 5826 len = skb_headlen(skb); 5827 } 5828 } 5829 5830 /* reserve a descriptor for the offload context */ 5831 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) 5832 count++; 5833 count++; 5834 5835 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); 5836 5837 nr_frags = skb_shinfo(skb)->nr_frags; 5838 for (f = 0; f < nr_frags; f++) 5839 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), 5840 adapter->tx_fifo_limit); 5841 5842 if (adapter->hw.mac.tx_pkt_filtering) 5843 e1000_transfer_dhcp_info(adapter, skb); 5844 5845 /* need: count + 2 desc gap to keep tail from touching 5846 * head, otherwise try next time 5847 */ 5848 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5849 return NETDEV_TX_BUSY; 5850 5851 if (skb_vlan_tag_present(skb)) { 5852 tx_flags |= E1000_TX_FLAGS_VLAN; 5853 tx_flags |= (skb_vlan_tag_get(skb) << 5854 E1000_TX_FLAGS_VLAN_SHIFT); 5855 } 5856 5857 first = tx_ring->next_to_use; 5858 5859 tso = e1000_tso(tx_ring, skb, protocol); 5860 if (tso < 0) { 5861 dev_kfree_skb_any(skb); 5862 return NETDEV_TX_OK; 5863 } 5864 5865 if (tso) 5866 tx_flags |= E1000_TX_FLAGS_TSO; 5867 else if (e1000_tx_csum(tx_ring, skb, protocol)) 5868 tx_flags |= E1000_TX_FLAGS_CSUM; 5869 5870 /* Old method was to assume IPv4 packet by default if TSO was enabled. 5871 * 82571 hardware supports TSO capabilities for IPv6 as well... 5872 * no longer assume, we must. 5873 */ 5874 if (protocol == htons(ETH_P_IP)) 5875 tx_flags |= E1000_TX_FLAGS_IPV4; 5876 5877 if (unlikely(skb->no_fcs)) 5878 tx_flags |= E1000_TX_FLAGS_NO_FCS; 5879 5880 /* if count is 0 then mapping error has occurred */ 5881 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, 5882 nr_frags); 5883 if (count) { 5884 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 5885 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { 5886 if (!adapter->tx_hwtstamp_skb) { 5887 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 5888 tx_flags |= E1000_TX_FLAGS_HWTSTAMP; 5889 adapter->tx_hwtstamp_skb = skb_get(skb); 5890 adapter->tx_hwtstamp_start = jiffies; 5891 schedule_work(&adapter->tx_hwtstamp_work); 5892 } else { 5893 adapter->tx_hwtstamp_skipped++; 5894 } 5895 } 5896 5897 skb_tx_timestamp(skb); 5898 5899 netdev_sent_queue(netdev, skb->len); 5900 e1000_tx_queue(tx_ring, tx_flags, count); 5901 /* Make sure there is space in the ring for the next send. */ 5902 e1000_maybe_stop_tx(tx_ring, 5903 (MAX_SKB_FRAGS * 5904 DIV_ROUND_UP(PAGE_SIZE, 5905 adapter->tx_fifo_limit) + 2)); 5906 5907 if (!skb->xmit_more || 5908 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { 5909 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 5910 e1000e_update_tdt_wa(tx_ring, 5911 tx_ring->next_to_use); 5912 else 5913 writel(tx_ring->next_to_use, tx_ring->tail); 5914 5915 /* we need this if more than one processor can write 5916 * to our tail at a time, it synchronizes IO on 5917 *IA64/Altix systems 5918 */ 5919 mmiowb(); 5920 } 5921 } else { 5922 dev_kfree_skb_any(skb); 5923 tx_ring->buffer_info[first].time_stamp = 0; 5924 tx_ring->next_to_use = first; 5925 } 5926 5927 return NETDEV_TX_OK; 5928 } 5929 5930 /** 5931 * e1000_tx_timeout - Respond to a Tx Hang 5932 * @netdev: network interface device structure 5933 **/ 5934 static void e1000_tx_timeout(struct net_device *netdev) 5935 { 5936 struct e1000_adapter *adapter = netdev_priv(netdev); 5937 5938 /* Do the reset outside of interrupt context */ 5939 adapter->tx_timeout_count++; 5940 schedule_work(&adapter->reset_task); 5941 } 5942 5943 static void e1000_reset_task(struct work_struct *work) 5944 { 5945 struct e1000_adapter *adapter; 5946 adapter = container_of(work, struct e1000_adapter, reset_task); 5947 5948 /* don't run the task if already down */ 5949 if (test_bit(__E1000_DOWN, &adapter->state)) 5950 return; 5951 5952 if (!(adapter->flags & FLAG_RESTART_NOW)) { 5953 e1000e_dump(adapter); 5954 e_err("Reset adapter unexpectedly\n"); 5955 } 5956 e1000e_reinit_locked(adapter); 5957 } 5958 5959 /** 5960 * e1000_get_stats64 - Get System Network Statistics 5961 * @netdev: network interface device structure 5962 * @stats: rtnl_link_stats64 pointer 5963 * 5964 * Returns the address of the device statistics structure. 5965 **/ 5966 void e1000e_get_stats64(struct net_device *netdev, 5967 struct rtnl_link_stats64 *stats) 5968 { 5969 struct e1000_adapter *adapter = netdev_priv(netdev); 5970 5971 spin_lock(&adapter->stats64_lock); 5972 e1000e_update_stats(adapter); 5973 /* Fill out the OS statistics structure */ 5974 stats->rx_bytes = adapter->stats.gorc; 5975 stats->rx_packets = adapter->stats.gprc; 5976 stats->tx_bytes = adapter->stats.gotc; 5977 stats->tx_packets = adapter->stats.gptc; 5978 stats->multicast = adapter->stats.mprc; 5979 stats->collisions = adapter->stats.colc; 5980 5981 /* Rx Errors */ 5982 5983 /* RLEC on some newer hardware can be incorrect so build 5984 * our own version based on RUC and ROC 5985 */ 5986 stats->rx_errors = adapter->stats.rxerrc + 5987 adapter->stats.crcerrs + adapter->stats.algnerrc + 5988 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; 5989 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; 5990 stats->rx_crc_errors = adapter->stats.crcerrs; 5991 stats->rx_frame_errors = adapter->stats.algnerrc; 5992 stats->rx_missed_errors = adapter->stats.mpc; 5993 5994 /* Tx Errors */ 5995 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; 5996 stats->tx_aborted_errors = adapter->stats.ecol; 5997 stats->tx_window_errors = adapter->stats.latecol; 5998 stats->tx_carrier_errors = adapter->stats.tncrs; 5999 6000 /* Tx Dropped needs to be maintained elsewhere */ 6001 6002 spin_unlock(&adapter->stats64_lock); 6003 } 6004 6005 /** 6006 * e1000_change_mtu - Change the Maximum Transfer Unit 6007 * @netdev: network interface device structure 6008 * @new_mtu: new value for maximum frame size 6009 * 6010 * Returns 0 on success, negative on failure 6011 **/ 6012 static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 6013 { 6014 struct e1000_adapter *adapter = netdev_priv(netdev); 6015 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 6016 6017 /* Jumbo frame support */ 6018 if ((new_mtu > ETH_DATA_LEN) && 6019 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { 6020 e_err("Jumbo Frames not supported.\n"); 6021 return -EINVAL; 6022 } 6023 6024 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6025 if ((adapter->hw.mac.type >= e1000_pch2lan) && 6026 !(adapter->flags2 & FLAG2_CRC_STRIPPING) && 6027 (new_mtu > ETH_DATA_LEN)) { 6028 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); 6029 return -EINVAL; 6030 } 6031 6032 while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) 6033 usleep_range(1000, 2000); 6034 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ 6035 adapter->max_frame_size = max_frame; 6036 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6037 netdev->mtu = new_mtu; 6038 6039 pm_runtime_get_sync(netdev->dev.parent); 6040 6041 if (netif_running(netdev)) 6042 e1000e_down(adapter, true); 6043 6044 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 6045 * means we reserve 2 more, this pushes us to allocate from the next 6046 * larger slab size. 6047 * i.e. RXBUFFER_2048 --> size-4096 slab 6048 * However with the new *_jumbo_rx* routines, jumbo receives will use 6049 * fragmented skbs 6050 */ 6051 6052 if (max_frame <= 2048) 6053 adapter->rx_buffer_len = 2048; 6054 else 6055 adapter->rx_buffer_len = 4096; 6056 6057 /* adjust allocation if LPE protects us, and we aren't using SBP */ 6058 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) 6059 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 6060 6061 if (netif_running(netdev)) 6062 e1000e_up(adapter); 6063 else 6064 e1000e_reset(adapter); 6065 6066 pm_runtime_put_sync(netdev->dev.parent); 6067 6068 clear_bit(__E1000_RESETTING, &adapter->state); 6069 6070 return 0; 6071 } 6072 6073 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 6074 int cmd) 6075 { 6076 struct e1000_adapter *adapter = netdev_priv(netdev); 6077 struct mii_ioctl_data *data = if_mii(ifr); 6078 6079 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6080 return -EOPNOTSUPP; 6081 6082 switch (cmd) { 6083 case SIOCGMIIPHY: 6084 data->phy_id = adapter->hw.phy.addr; 6085 break; 6086 case SIOCGMIIREG: 6087 e1000_phy_read_status(adapter); 6088 6089 switch (data->reg_num & 0x1F) { 6090 case MII_BMCR: 6091 data->val_out = adapter->phy_regs.bmcr; 6092 break; 6093 case MII_BMSR: 6094 data->val_out = adapter->phy_regs.bmsr; 6095 break; 6096 case MII_PHYSID1: 6097 data->val_out = (adapter->hw.phy.id >> 16); 6098 break; 6099 case MII_PHYSID2: 6100 data->val_out = (adapter->hw.phy.id & 0xFFFF); 6101 break; 6102 case MII_ADVERTISE: 6103 data->val_out = adapter->phy_regs.advertise; 6104 break; 6105 case MII_LPA: 6106 data->val_out = adapter->phy_regs.lpa; 6107 break; 6108 case MII_EXPANSION: 6109 data->val_out = adapter->phy_regs.expansion; 6110 break; 6111 case MII_CTRL1000: 6112 data->val_out = adapter->phy_regs.ctrl1000; 6113 break; 6114 case MII_STAT1000: 6115 data->val_out = adapter->phy_regs.stat1000; 6116 break; 6117 case MII_ESTATUS: 6118 data->val_out = adapter->phy_regs.estatus; 6119 break; 6120 default: 6121 return -EIO; 6122 } 6123 break; 6124 case SIOCSMIIREG: 6125 default: 6126 return -EOPNOTSUPP; 6127 } 6128 return 0; 6129 } 6130 6131 /** 6132 * e1000e_hwtstamp_ioctl - control hardware time stamping 6133 * @netdev: network interface device structure 6134 * @ifreq: interface request 6135 * 6136 * Outgoing time stamping can be enabled and disabled. Play nice and 6137 * disable it when requested, although it shouldn't cause any overhead 6138 * when no packet needs it. At most one packet in the queue may be 6139 * marked for time stamping, otherwise it would be impossible to tell 6140 * for sure to which packet the hardware time stamp belongs. 6141 * 6142 * Incoming time stamping has to be configured via the hardware filters. 6143 * Not all combinations are supported, in particular event type has to be 6144 * specified. Matching the kind of event packet is not supported, with the 6145 * exception of "all V2 events regardless of level 2 or 4". 6146 **/ 6147 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 6148 { 6149 struct e1000_adapter *adapter = netdev_priv(netdev); 6150 struct hwtstamp_config config; 6151 int ret_val; 6152 6153 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 6154 return -EFAULT; 6155 6156 ret_val = e1000e_config_hwtstamp(adapter, &config); 6157 if (ret_val) 6158 return ret_val; 6159 6160 switch (config.rx_filter) { 6161 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 6162 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 6163 case HWTSTAMP_FILTER_PTP_V2_SYNC: 6164 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 6165 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 6166 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 6167 /* With V2 type filters which specify a Sync or Delay Request, 6168 * Path Delay Request/Response messages are also time stamped 6169 * by hardware so notify the caller the requested packets plus 6170 * some others are time stamped. 6171 */ 6172 config.rx_filter = HWTSTAMP_FILTER_SOME; 6173 break; 6174 default: 6175 break; 6176 } 6177 6178 return copy_to_user(ifr->ifr_data, &config, 6179 sizeof(config)) ? -EFAULT : 0; 6180 } 6181 6182 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 6183 { 6184 struct e1000_adapter *adapter = netdev_priv(netdev); 6185 6186 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, 6187 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; 6188 } 6189 6190 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6191 { 6192 switch (cmd) { 6193 case SIOCGMIIPHY: 6194 case SIOCGMIIREG: 6195 case SIOCSMIIREG: 6196 return e1000_mii_ioctl(netdev, ifr, cmd); 6197 case SIOCSHWTSTAMP: 6198 return e1000e_hwtstamp_set(netdev, ifr); 6199 case SIOCGHWTSTAMP: 6200 return e1000e_hwtstamp_get(netdev, ifr); 6201 default: 6202 return -EOPNOTSUPP; 6203 } 6204 } 6205 6206 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) 6207 { 6208 struct e1000_hw *hw = &adapter->hw; 6209 u32 i, mac_reg, wuc; 6210 u16 phy_reg, wuc_enable; 6211 int retval; 6212 6213 /* copy MAC RARs to PHY RARs */ 6214 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 6215 6216 retval = hw->phy.ops.acquire(hw); 6217 if (retval) { 6218 e_err("Could not acquire PHY\n"); 6219 return retval; 6220 } 6221 6222 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ 6223 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6224 if (retval) 6225 goto release; 6226 6227 /* copy MAC MTA to PHY MTA - only needed for pchlan */ 6228 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 6229 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 6230 hw->phy.ops.write_reg_page(hw, BM_MTA(i), 6231 (u16)(mac_reg & 0xFFFF)); 6232 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, 6233 (u16)((mac_reg >> 16) & 0xFFFF)); 6234 } 6235 6236 /* configure PHY Rx Control register */ 6237 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); 6238 mac_reg = er32(RCTL); 6239 if (mac_reg & E1000_RCTL_UPE) 6240 phy_reg |= BM_RCTL_UPE; 6241 if (mac_reg & E1000_RCTL_MPE) 6242 phy_reg |= BM_RCTL_MPE; 6243 phy_reg &= ~(BM_RCTL_MO_MASK); 6244 if (mac_reg & E1000_RCTL_MO_3) 6245 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6246 << BM_RCTL_MO_SHIFT); 6247 if (mac_reg & E1000_RCTL_BAM) 6248 phy_reg |= BM_RCTL_BAM; 6249 if (mac_reg & E1000_RCTL_PMCF) 6250 phy_reg |= BM_RCTL_PMCF; 6251 mac_reg = er32(CTRL); 6252 if (mac_reg & E1000_CTRL_RFCE) 6253 phy_reg |= BM_RCTL_RFCE; 6254 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); 6255 6256 wuc = E1000_WUC_PME_EN; 6257 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) 6258 wuc |= E1000_WUC_APME; 6259 6260 /* enable PHY wakeup in MAC register */ 6261 ew32(WUFC, wufc); 6262 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | 6263 E1000_WUC_PME_STATUS | wuc)); 6264 6265 /* configure and enable PHY wakeup in PHY registers */ 6266 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); 6267 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); 6268 6269 /* activate PHY wakeup */ 6270 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 6271 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); 6272 if (retval) 6273 e_err("Could not set PHY Host Wakeup bit\n"); 6274 release: 6275 hw->phy.ops.release(hw); 6276 6277 return retval; 6278 } 6279 6280 static void e1000e_flush_lpic(struct pci_dev *pdev) 6281 { 6282 struct net_device *netdev = pci_get_drvdata(pdev); 6283 struct e1000_adapter *adapter = netdev_priv(netdev); 6284 struct e1000_hw *hw = &adapter->hw; 6285 u32 ret_val; 6286 6287 pm_runtime_get_sync(netdev->dev.parent); 6288 6289 ret_val = hw->phy.ops.acquire(hw); 6290 if (ret_val) 6291 goto fl_out; 6292 6293 pr_info("EEE TX LPI TIMER: %08X\n", 6294 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); 6295 6296 hw->phy.ops.release(hw); 6297 6298 fl_out: 6299 pm_runtime_put_sync(netdev->dev.parent); 6300 } 6301 6302 static int e1000e_pm_freeze(struct device *dev) 6303 { 6304 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6305 struct e1000_adapter *adapter = netdev_priv(netdev); 6306 6307 netif_device_detach(netdev); 6308 6309 if (netif_running(netdev)) { 6310 int count = E1000_CHECK_RESET_COUNT; 6311 6312 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6313 usleep_range(10000, 20000); 6314 6315 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6316 6317 /* Quiesce the device without resetting the hardware */ 6318 e1000e_down(adapter, false); 6319 e1000_free_irq(adapter); 6320 } 6321 e1000e_reset_interrupt_capability(adapter); 6322 6323 /* Allow time for pending master requests to run */ 6324 e1000e_disable_pcie_master(&adapter->hw); 6325 6326 return 0; 6327 } 6328 6329 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) 6330 { 6331 struct net_device *netdev = pci_get_drvdata(pdev); 6332 struct e1000_adapter *adapter = netdev_priv(netdev); 6333 struct e1000_hw *hw = &adapter->hw; 6334 u32 ctrl, ctrl_ext, rctl, status; 6335 /* Runtime suspend should only enable wakeup for link changes */ 6336 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6337 int retval = 0; 6338 6339 status = er32(STATUS); 6340 if (status & E1000_STATUS_LU) 6341 wufc &= ~E1000_WUFC_LNKC; 6342 6343 if (wufc) { 6344 e1000_setup_rctl(adapter); 6345 e1000e_set_rx_mode(netdev); 6346 6347 /* turn on all-multi mode if wake on multicast is enabled */ 6348 if (wufc & E1000_WUFC_MC) { 6349 rctl = er32(RCTL); 6350 rctl |= E1000_RCTL_MPE; 6351 ew32(RCTL, rctl); 6352 } 6353 6354 ctrl = er32(CTRL); 6355 ctrl |= E1000_CTRL_ADVD3WUC; 6356 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) 6357 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; 6358 ew32(CTRL, ctrl); 6359 6360 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 6361 adapter->hw.phy.media_type == 6362 e1000_media_type_internal_serdes) { 6363 /* keep the laser running in D3 */ 6364 ctrl_ext = er32(CTRL_EXT); 6365 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 6366 ew32(CTRL_EXT, ctrl_ext); 6367 } 6368 6369 if (!runtime) 6370 e1000e_power_up_phy(adapter); 6371 6372 if (adapter->flags & FLAG_IS_ICH) 6373 e1000_suspend_workarounds_ich8lan(&adapter->hw); 6374 6375 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6376 /* enable wakeup by the PHY */ 6377 retval = e1000_init_phy_wakeup(adapter, wufc); 6378 if (retval) 6379 return retval; 6380 } else { 6381 /* enable wakeup by the MAC */ 6382 ew32(WUFC, wufc); 6383 ew32(WUC, E1000_WUC_PME_EN); 6384 } 6385 } else { 6386 ew32(WUC, 0); 6387 ew32(WUFC, 0); 6388 6389 e1000_power_down_phy(adapter); 6390 } 6391 6392 if (adapter->hw.phy.type == e1000_phy_igp_3) { 6393 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 6394 } else if (hw->mac.type >= e1000_pch_lpt) { 6395 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) 6396 /* ULP does not support wake from unicast, multicast 6397 * or broadcast. 6398 */ 6399 retval = e1000_enable_ulp_lpt_lp(hw, !runtime); 6400 6401 if (retval) 6402 return retval; 6403 } 6404 6405 /* Ensure that the appropriate bits are set in LPI_CTRL 6406 * for EEE in Sx 6407 */ 6408 if ((hw->phy.type >= e1000_phy_i217) && 6409 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { 6410 u16 lpi_ctrl = 0; 6411 6412 retval = hw->phy.ops.acquire(hw); 6413 if (!retval) { 6414 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, 6415 &lpi_ctrl); 6416 if (!retval) { 6417 if (adapter->eee_advert & 6418 hw->dev_spec.ich8lan.eee_lp_ability & 6419 I82579_EEE_100_SUPPORTED) 6420 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 6421 if (adapter->eee_advert & 6422 hw->dev_spec.ich8lan.eee_lp_ability & 6423 I82579_EEE_1000_SUPPORTED) 6424 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 6425 6426 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, 6427 lpi_ctrl); 6428 } 6429 } 6430 hw->phy.ops.release(hw); 6431 } 6432 6433 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6434 * would have already happened in close and is redundant. 6435 */ 6436 e1000e_release_hw_control(adapter); 6437 6438 pci_clear_master(pdev); 6439 6440 /* The pci-e switch on some quad port adapters will report a 6441 * correctable error when the MAC transitions from D0 to D3. To 6442 * prevent this we need to mask off the correctable errors on the 6443 * downstream port of the pci-e switch. 6444 * 6445 * We don't have the associated upstream bridge while assigning 6446 * the PCI device into guest. For example, the KVM on power is 6447 * one of the cases. 6448 */ 6449 if (adapter->flags & FLAG_IS_QUAD_PORT) { 6450 struct pci_dev *us_dev = pdev->bus->self; 6451 u16 devctl; 6452 6453 if (!us_dev) 6454 return 0; 6455 6456 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); 6457 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, 6458 (devctl & ~PCI_EXP_DEVCTL_CERE)); 6459 6460 pci_save_state(pdev); 6461 pci_prepare_to_sleep(pdev); 6462 6463 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); 6464 } 6465 6466 return 0; 6467 } 6468 6469 /** 6470 * __e1000e_disable_aspm - Disable ASPM states 6471 * @pdev: pointer to PCI device struct 6472 * @state: bit-mask of ASPM states to disable 6473 * @locked: indication if this context holds pci_bus_sem locked. 6474 * 6475 * Some devices *must* have certain ASPM states disabled per hardware errata. 6476 **/ 6477 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) 6478 { 6479 struct pci_dev *parent = pdev->bus->self; 6480 u16 aspm_dis_mask = 0; 6481 u16 pdev_aspmc, parent_aspmc; 6482 6483 switch (state) { 6484 case PCIE_LINK_STATE_L0S: 6485 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: 6486 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; 6487 /* fall-through - can't have L1 without L0s */ 6488 case PCIE_LINK_STATE_L1: 6489 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; 6490 break; 6491 default: 6492 return; 6493 } 6494 6495 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6496 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6497 6498 if (parent) { 6499 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, 6500 &parent_aspmc); 6501 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6502 } 6503 6504 /* Nothing to do if the ASPM states to be disabled already are */ 6505 if (!(pdev_aspmc & aspm_dis_mask) && 6506 (!parent || !(parent_aspmc & aspm_dis_mask))) 6507 return; 6508 6509 dev_info(&pdev->dev, "Disabling ASPM %s %s\n", 6510 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? 6511 "L0s" : "", 6512 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? 6513 "L1" : ""); 6514 6515 #ifdef CONFIG_PCIEASPM 6516 if (locked) 6517 pci_disable_link_state_locked(pdev, state); 6518 else 6519 pci_disable_link_state(pdev, state); 6520 6521 /* Double-check ASPM control. If not disabled by the above, the 6522 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is 6523 * not enabled); override by writing PCI config space directly. 6524 */ 6525 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); 6526 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; 6527 6528 if (!(aspm_dis_mask & pdev_aspmc)) 6529 return; 6530 #endif 6531 6532 /* Both device and parent should have the same ASPM setting. 6533 * Disable ASPM in downstream component first and then upstream. 6534 */ 6535 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); 6536 6537 if (parent) 6538 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 6539 aspm_dis_mask); 6540 } 6541 6542 /** 6543 * e1000e_disable_aspm - Disable ASPM states. 6544 * @pdev: pointer to PCI device struct 6545 * @state: bit-mask of ASPM states to disable 6546 * 6547 * This function acquires the pci_bus_sem! 6548 * Some devices *must* have certain ASPM states disabled per hardware errata. 6549 **/ 6550 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 6551 { 6552 __e1000e_disable_aspm(pdev, state, 0); 6553 } 6554 6555 /** 6556 * e1000e_disable_aspm_locked Disable ASPM states. 6557 * @pdev: pointer to PCI device struct 6558 * @state: bit-mask of ASPM states to disable 6559 * 6560 * This function must be called with pci_bus_sem acquired! 6561 * Some devices *must* have certain ASPM states disabled per hardware errata. 6562 **/ 6563 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) 6564 { 6565 __e1000e_disable_aspm(pdev, state, 1); 6566 } 6567 6568 #ifdef CONFIG_PM 6569 static int __e1000_resume(struct pci_dev *pdev) 6570 { 6571 struct net_device *netdev = pci_get_drvdata(pdev); 6572 struct e1000_adapter *adapter = netdev_priv(netdev); 6573 struct e1000_hw *hw = &adapter->hw; 6574 u16 aspm_disable_flag = 0; 6575 6576 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6577 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6578 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6579 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6580 if (aspm_disable_flag) 6581 e1000e_disable_aspm(pdev, aspm_disable_flag); 6582 6583 pci_set_master(pdev); 6584 6585 if (hw->mac.type >= e1000_pch2lan) 6586 e1000_resume_workarounds_pchlan(&adapter->hw); 6587 6588 e1000e_power_up_phy(adapter); 6589 6590 /* report the system wakeup cause from S3/S4 */ 6591 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { 6592 u16 phy_data; 6593 6594 e1e_rphy(&adapter->hw, BM_WUS, &phy_data); 6595 if (phy_data) { 6596 e_info("PHY Wakeup cause - %s\n", 6597 phy_data & E1000_WUS_EX ? "Unicast Packet" : 6598 phy_data & E1000_WUS_MC ? "Multicast Packet" : 6599 phy_data & E1000_WUS_BC ? "Broadcast Packet" : 6600 phy_data & E1000_WUS_MAG ? "Magic Packet" : 6601 phy_data & E1000_WUS_LNKC ? 6602 "Link Status Change" : "other"); 6603 } 6604 e1e_wphy(&adapter->hw, BM_WUS, ~0); 6605 } else { 6606 u32 wus = er32(WUS); 6607 6608 if (wus) { 6609 e_info("MAC Wakeup cause - %s\n", 6610 wus & E1000_WUS_EX ? "Unicast Packet" : 6611 wus & E1000_WUS_MC ? "Multicast Packet" : 6612 wus & E1000_WUS_BC ? "Broadcast Packet" : 6613 wus & E1000_WUS_MAG ? "Magic Packet" : 6614 wus & E1000_WUS_LNKC ? "Link Status Change" : 6615 "other"); 6616 } 6617 ew32(WUS, ~0); 6618 } 6619 6620 e1000e_reset(adapter); 6621 6622 e1000_init_manageability_pt(adapter); 6623 6624 /* If the controller has AMT, do not set DRV_LOAD until the interface 6625 * is up. For all other cases, let the f/w know that the h/w is now 6626 * under the control of the driver. 6627 */ 6628 if (!(adapter->flags & FLAG_HAS_AMT)) 6629 e1000e_get_hw_control(adapter); 6630 6631 return 0; 6632 } 6633 6634 #ifdef CONFIG_PM_SLEEP 6635 static int e1000e_pm_thaw(struct device *dev) 6636 { 6637 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6638 struct e1000_adapter *adapter = netdev_priv(netdev); 6639 6640 e1000e_set_interrupt_capability(adapter); 6641 if (netif_running(netdev)) { 6642 u32 err = e1000_request_irq(adapter); 6643 6644 if (err) 6645 return err; 6646 6647 e1000e_up(adapter); 6648 } 6649 6650 netif_device_attach(netdev); 6651 6652 return 0; 6653 } 6654 6655 static int e1000e_pm_suspend(struct device *dev) 6656 { 6657 struct pci_dev *pdev = to_pci_dev(dev); 6658 int rc; 6659 6660 e1000e_flush_lpic(pdev); 6661 6662 e1000e_pm_freeze(dev); 6663 6664 rc = __e1000_shutdown(pdev, false); 6665 if (rc) 6666 e1000e_pm_thaw(dev); 6667 6668 return rc; 6669 } 6670 6671 static int e1000e_pm_resume(struct device *dev) 6672 { 6673 struct pci_dev *pdev = to_pci_dev(dev); 6674 int rc; 6675 6676 rc = __e1000_resume(pdev); 6677 if (rc) 6678 return rc; 6679 6680 return e1000e_pm_thaw(dev); 6681 } 6682 #endif /* CONFIG_PM_SLEEP */ 6683 6684 static int e1000e_pm_runtime_idle(struct device *dev) 6685 { 6686 struct pci_dev *pdev = to_pci_dev(dev); 6687 struct net_device *netdev = pci_get_drvdata(pdev); 6688 struct e1000_adapter *adapter = netdev_priv(netdev); 6689 u16 eee_lp; 6690 6691 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; 6692 6693 if (!e1000e_has_link(adapter)) { 6694 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; 6695 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); 6696 } 6697 6698 return -EBUSY; 6699 } 6700 6701 static int e1000e_pm_runtime_resume(struct device *dev) 6702 { 6703 struct pci_dev *pdev = to_pci_dev(dev); 6704 struct net_device *netdev = pci_get_drvdata(pdev); 6705 struct e1000_adapter *adapter = netdev_priv(netdev); 6706 int rc; 6707 6708 rc = __e1000_resume(pdev); 6709 if (rc) 6710 return rc; 6711 6712 if (netdev->flags & IFF_UP) 6713 e1000e_up(adapter); 6714 6715 return rc; 6716 } 6717 6718 static int e1000e_pm_runtime_suspend(struct device *dev) 6719 { 6720 struct pci_dev *pdev = to_pci_dev(dev); 6721 struct net_device *netdev = pci_get_drvdata(pdev); 6722 struct e1000_adapter *adapter = netdev_priv(netdev); 6723 6724 if (netdev->flags & IFF_UP) { 6725 int count = E1000_CHECK_RESET_COUNT; 6726 6727 while (test_bit(__E1000_RESETTING, &adapter->state) && count--) 6728 usleep_range(10000, 20000); 6729 6730 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); 6731 6732 /* Down the device without resetting the hardware */ 6733 e1000e_down(adapter, false); 6734 } 6735 6736 if (__e1000_shutdown(pdev, true)) { 6737 e1000e_pm_runtime_resume(dev); 6738 return -EBUSY; 6739 } 6740 6741 return 0; 6742 } 6743 #endif /* CONFIG_PM */ 6744 6745 static void e1000_shutdown(struct pci_dev *pdev) 6746 { 6747 e1000e_flush_lpic(pdev); 6748 6749 e1000e_pm_freeze(&pdev->dev); 6750 6751 __e1000_shutdown(pdev, false); 6752 } 6753 6754 #ifdef CONFIG_NET_POLL_CONTROLLER 6755 6756 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) 6757 { 6758 struct net_device *netdev = data; 6759 struct e1000_adapter *adapter = netdev_priv(netdev); 6760 6761 if (adapter->msix_entries) { 6762 int vector, msix_irq; 6763 6764 vector = 0; 6765 msix_irq = adapter->msix_entries[vector].vector; 6766 if (disable_hardirq(msix_irq)) 6767 e1000_intr_msix_rx(msix_irq, netdev); 6768 enable_irq(msix_irq); 6769 6770 vector++; 6771 msix_irq = adapter->msix_entries[vector].vector; 6772 if (disable_hardirq(msix_irq)) 6773 e1000_intr_msix_tx(msix_irq, netdev); 6774 enable_irq(msix_irq); 6775 6776 vector++; 6777 msix_irq = adapter->msix_entries[vector].vector; 6778 if (disable_hardirq(msix_irq)) 6779 e1000_msix_other(msix_irq, netdev); 6780 enable_irq(msix_irq); 6781 } 6782 6783 return IRQ_HANDLED; 6784 } 6785 6786 /** 6787 * e1000_netpoll 6788 * @netdev: network interface device structure 6789 * 6790 * Polling 'interrupt' - used by things like netconsole to send skbs 6791 * without having to re-enable interrupts. It's not called while 6792 * the interrupt routine is executing. 6793 */ 6794 static void e1000_netpoll(struct net_device *netdev) 6795 { 6796 struct e1000_adapter *adapter = netdev_priv(netdev); 6797 6798 switch (adapter->int_mode) { 6799 case E1000E_INT_MODE_MSIX: 6800 e1000_intr_msix(adapter->pdev->irq, netdev); 6801 break; 6802 case E1000E_INT_MODE_MSI: 6803 if (disable_hardirq(adapter->pdev->irq)) 6804 e1000_intr_msi(adapter->pdev->irq, netdev); 6805 enable_irq(adapter->pdev->irq); 6806 break; 6807 default: /* E1000E_INT_MODE_LEGACY */ 6808 if (disable_hardirq(adapter->pdev->irq)) 6809 e1000_intr(adapter->pdev->irq, netdev); 6810 enable_irq(adapter->pdev->irq); 6811 break; 6812 } 6813 } 6814 #endif 6815 6816 /** 6817 * e1000_io_error_detected - called when PCI error is detected 6818 * @pdev: Pointer to PCI device 6819 * @state: The current pci connection state 6820 * 6821 * This function is called after a PCI bus error affecting 6822 * this device has been detected. 6823 */ 6824 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, 6825 pci_channel_state_t state) 6826 { 6827 struct net_device *netdev = pci_get_drvdata(pdev); 6828 struct e1000_adapter *adapter = netdev_priv(netdev); 6829 6830 netif_device_detach(netdev); 6831 6832 if (state == pci_channel_io_perm_failure) 6833 return PCI_ERS_RESULT_DISCONNECT; 6834 6835 if (netif_running(netdev)) 6836 e1000e_down(adapter, true); 6837 pci_disable_device(pdev); 6838 6839 /* Request a slot slot reset. */ 6840 return PCI_ERS_RESULT_NEED_RESET; 6841 } 6842 6843 /** 6844 * e1000_io_slot_reset - called after the pci bus has been reset. 6845 * @pdev: Pointer to PCI device 6846 * 6847 * Restart the card from scratch, as if from a cold-boot. Implementation 6848 * resembles the first-half of the e1000e_pm_resume routine. 6849 */ 6850 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) 6851 { 6852 struct net_device *netdev = pci_get_drvdata(pdev); 6853 struct e1000_adapter *adapter = netdev_priv(netdev); 6854 struct e1000_hw *hw = &adapter->hw; 6855 u16 aspm_disable_flag = 0; 6856 int err; 6857 pci_ers_result_t result; 6858 6859 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) 6860 aspm_disable_flag = PCIE_LINK_STATE_L0S; 6861 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) 6862 aspm_disable_flag |= PCIE_LINK_STATE_L1; 6863 if (aspm_disable_flag) 6864 e1000e_disable_aspm_locked(pdev, aspm_disable_flag); 6865 6866 err = pci_enable_device_mem(pdev); 6867 if (err) { 6868 dev_err(&pdev->dev, 6869 "Cannot re-enable PCI device after reset.\n"); 6870 result = PCI_ERS_RESULT_DISCONNECT; 6871 } else { 6872 pdev->state_saved = true; 6873 pci_restore_state(pdev); 6874 pci_set_master(pdev); 6875 6876 pci_enable_wake(pdev, PCI_D3hot, 0); 6877 pci_enable_wake(pdev, PCI_D3cold, 0); 6878 6879 e1000e_reset(adapter); 6880 ew32(WUS, ~0); 6881 result = PCI_ERS_RESULT_RECOVERED; 6882 } 6883 6884 pci_cleanup_aer_uncorrect_error_status(pdev); 6885 6886 return result; 6887 } 6888 6889 /** 6890 * e1000_io_resume - called when traffic can start flowing again. 6891 * @pdev: Pointer to PCI device 6892 * 6893 * This callback is called when the error recovery driver tells us that 6894 * its OK to resume normal operation. Implementation resembles the 6895 * second-half of the e1000e_pm_resume routine. 6896 */ 6897 static void e1000_io_resume(struct pci_dev *pdev) 6898 { 6899 struct net_device *netdev = pci_get_drvdata(pdev); 6900 struct e1000_adapter *adapter = netdev_priv(netdev); 6901 6902 e1000_init_manageability_pt(adapter); 6903 6904 if (netif_running(netdev)) 6905 e1000e_up(adapter); 6906 6907 netif_device_attach(netdev); 6908 6909 /* If the controller has AMT, do not set DRV_LOAD until the interface 6910 * is up. For all other cases, let the f/w know that the h/w is now 6911 * under the control of the driver. 6912 */ 6913 if (!(adapter->flags & FLAG_HAS_AMT)) 6914 e1000e_get_hw_control(adapter); 6915 } 6916 6917 static void e1000_print_device_info(struct e1000_adapter *adapter) 6918 { 6919 struct e1000_hw *hw = &adapter->hw; 6920 struct net_device *netdev = adapter->netdev; 6921 u32 ret_val; 6922 u8 pba_str[E1000_PBANUM_LENGTH]; 6923 6924 /* print bus type/speed/width info */ 6925 e_info("(PCI Express:2.5GT/s:%s) %pM\n", 6926 /* bus width */ 6927 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 6928 "Width x1"), 6929 /* MAC address */ 6930 netdev->dev_addr); 6931 e_info("Intel(R) PRO/%s Network Connection\n", 6932 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); 6933 ret_val = e1000_read_pba_string_generic(hw, pba_str, 6934 E1000_PBANUM_LENGTH); 6935 if (ret_val) 6936 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); 6937 e_info("MAC: %d, PHY: %d, PBA No: %s\n", 6938 hw->mac.type, hw->phy.type, pba_str); 6939 } 6940 6941 static void e1000_eeprom_checks(struct e1000_adapter *adapter) 6942 { 6943 struct e1000_hw *hw = &adapter->hw; 6944 int ret_val; 6945 u16 buf = 0; 6946 6947 if (hw->mac.type != e1000_82573) 6948 return; 6949 6950 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); 6951 le16_to_cpus(&buf); 6952 if (!ret_val && (!(buf & BIT(0)))) { 6953 /* Deep Smart Power Down (DSPD) */ 6954 dev_warn(&adapter->pdev->dev, 6955 "Warning: detected DSPD enabled in EEPROM\n"); 6956 } 6957 } 6958 6959 static netdev_features_t e1000_fix_features(struct net_device *netdev, 6960 netdev_features_t features) 6961 { 6962 struct e1000_adapter *adapter = netdev_priv(netdev); 6963 struct e1000_hw *hw = &adapter->hw; 6964 6965 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ 6966 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) 6967 features &= ~NETIF_F_RXFCS; 6968 6969 /* Since there is no support for separate Rx/Tx vlan accel 6970 * enable/disable make sure Tx flag is always in same state as Rx. 6971 */ 6972 if (features & NETIF_F_HW_VLAN_CTAG_RX) 6973 features |= NETIF_F_HW_VLAN_CTAG_TX; 6974 else 6975 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 6976 6977 return features; 6978 } 6979 6980 static int e1000_set_features(struct net_device *netdev, 6981 netdev_features_t features) 6982 { 6983 struct e1000_adapter *adapter = netdev_priv(netdev); 6984 netdev_features_t changed = features ^ netdev->features; 6985 6986 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) 6987 adapter->flags |= FLAG_TSO_FORCE; 6988 6989 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | 6990 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | 6991 NETIF_F_RXALL))) 6992 return 0; 6993 6994 if (changed & NETIF_F_RXFCS) { 6995 if (features & NETIF_F_RXFCS) { 6996 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 6997 } else { 6998 /* We need to take it back to defaults, which might mean 6999 * stripping is still disabled at the adapter level. 7000 */ 7001 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) 7002 adapter->flags2 |= FLAG2_CRC_STRIPPING; 7003 else 7004 adapter->flags2 &= ~FLAG2_CRC_STRIPPING; 7005 } 7006 } 7007 7008 netdev->features = features; 7009 7010 if (netif_running(netdev)) 7011 e1000e_reinit_locked(adapter); 7012 else 7013 e1000e_reset(adapter); 7014 7015 return 0; 7016 } 7017 7018 static const struct net_device_ops e1000e_netdev_ops = { 7019 .ndo_open = e1000e_open, 7020 .ndo_stop = e1000e_close, 7021 .ndo_start_xmit = e1000_xmit_frame, 7022 .ndo_get_stats64 = e1000e_get_stats64, 7023 .ndo_set_rx_mode = e1000e_set_rx_mode, 7024 .ndo_set_mac_address = e1000_set_mac, 7025 .ndo_change_mtu = e1000_change_mtu, 7026 .ndo_do_ioctl = e1000_ioctl, 7027 .ndo_tx_timeout = e1000_tx_timeout, 7028 .ndo_validate_addr = eth_validate_addr, 7029 7030 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, 7031 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, 7032 #ifdef CONFIG_NET_POLL_CONTROLLER 7033 .ndo_poll_controller = e1000_netpoll, 7034 #endif 7035 .ndo_set_features = e1000_set_features, 7036 .ndo_fix_features = e1000_fix_features, 7037 .ndo_features_check = passthru_features_check, 7038 }; 7039 7040 /** 7041 * e1000_probe - Device Initialization Routine 7042 * @pdev: PCI device information struct 7043 * @ent: entry in e1000_pci_tbl 7044 * 7045 * Returns 0 on success, negative on failure 7046 * 7047 * e1000_probe initializes an adapter identified by a pci_dev structure. 7048 * The OS initialization, configuring of the adapter private structure, 7049 * and a hardware reset occur. 7050 **/ 7051 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 7052 { 7053 struct net_device *netdev; 7054 struct e1000_adapter *adapter; 7055 struct e1000_hw *hw; 7056 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; 7057 resource_size_t mmio_start, mmio_len; 7058 resource_size_t flash_start, flash_len; 7059 static int cards_found; 7060 u16 aspm_disable_flag = 0; 7061 int bars, i, err, pci_using_dac; 7062 u16 eeprom_data = 0; 7063 u16 eeprom_apme_mask = E1000_EEPROM_APME; 7064 s32 ret_val = 0; 7065 7066 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) 7067 aspm_disable_flag = PCIE_LINK_STATE_L0S; 7068 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) 7069 aspm_disable_flag |= PCIE_LINK_STATE_L1; 7070 if (aspm_disable_flag) 7071 e1000e_disable_aspm(pdev, aspm_disable_flag); 7072 7073 err = pci_enable_device_mem(pdev); 7074 if (err) 7075 return err; 7076 7077 pci_using_dac = 0; 7078 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 7079 if (!err) { 7080 pci_using_dac = 1; 7081 } else { 7082 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 7083 if (err) { 7084 dev_err(&pdev->dev, 7085 "No usable DMA configuration, aborting\n"); 7086 goto err_dma; 7087 } 7088 } 7089 7090 bars = pci_select_bars(pdev, IORESOURCE_MEM); 7091 err = pci_request_selected_regions_exclusive(pdev, bars, 7092 e1000e_driver_name); 7093 if (err) 7094 goto err_pci_reg; 7095 7096 /* AER (Advanced Error Reporting) hooks */ 7097 pci_enable_pcie_error_reporting(pdev); 7098 7099 pci_set_master(pdev); 7100 /* PCI config space info */ 7101 err = pci_save_state(pdev); 7102 if (err) 7103 goto err_alloc_etherdev; 7104 7105 err = -ENOMEM; 7106 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 7107 if (!netdev) 7108 goto err_alloc_etherdev; 7109 7110 SET_NETDEV_DEV(netdev, &pdev->dev); 7111 7112 netdev->irq = pdev->irq; 7113 7114 pci_set_drvdata(pdev, netdev); 7115 adapter = netdev_priv(netdev); 7116 hw = &adapter->hw; 7117 adapter->netdev = netdev; 7118 adapter->pdev = pdev; 7119 adapter->ei = ei; 7120 adapter->pba = ei->pba; 7121 adapter->flags = ei->flags; 7122 adapter->flags2 = ei->flags2; 7123 adapter->hw.adapter = adapter; 7124 adapter->hw.mac.type = ei->mac; 7125 adapter->max_hw_frame_size = ei->max_hw_frame_size; 7126 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 7127 7128 mmio_start = pci_resource_start(pdev, 0); 7129 mmio_len = pci_resource_len(pdev, 0); 7130 7131 err = -EIO; 7132 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 7133 if (!adapter->hw.hw_addr) 7134 goto err_ioremap; 7135 7136 if ((adapter->flags & FLAG_HAS_FLASH) && 7137 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && 7138 (hw->mac.type < e1000_pch_spt)) { 7139 flash_start = pci_resource_start(pdev, 1); 7140 flash_len = pci_resource_len(pdev, 1); 7141 adapter->hw.flash_address = ioremap(flash_start, flash_len); 7142 if (!adapter->hw.flash_address) 7143 goto err_flashmap; 7144 } 7145 7146 /* Set default EEE advertisement */ 7147 if (adapter->flags2 & FLAG2_HAS_EEE) 7148 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 7149 7150 /* construct the net_device struct */ 7151 netdev->netdev_ops = &e1000e_netdev_ops; 7152 e1000e_set_ethtool_ops(netdev); 7153 netdev->watchdog_timeo = 5 * HZ; 7154 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); 7155 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 7156 7157 netdev->mem_start = mmio_start; 7158 netdev->mem_end = mmio_start + mmio_len; 7159 7160 adapter->bd_number = cards_found++; 7161 7162 e1000e_check_options(adapter); 7163 7164 /* setup adapter struct */ 7165 err = e1000_sw_init(adapter); 7166 if (err) 7167 goto err_sw_init; 7168 7169 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 7170 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 7171 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 7172 7173 err = ei->get_variants(adapter); 7174 if (err) 7175 goto err_hw_init; 7176 7177 if ((adapter->flags & FLAG_IS_ICH) && 7178 (adapter->flags & FLAG_READ_ONLY_NVM) && 7179 (hw->mac.type < e1000_pch_spt)) 7180 e1000e_write_protect_nvm_ich8lan(&adapter->hw); 7181 7182 hw->mac.ops.get_bus_info(&adapter->hw); 7183 7184 adapter->hw.phy.autoneg_wait_to_complete = 0; 7185 7186 /* Copper options */ 7187 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 7188 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7189 adapter->hw.phy.disable_polarity_correction = 0; 7190 adapter->hw.phy.ms_type = e1000_ms_hw_default; 7191 } 7192 7193 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 7194 dev_info(&pdev->dev, 7195 "PHY reset is blocked due to SOL/IDER session.\n"); 7196 7197 /* Set initial default active device features */ 7198 netdev->features = (NETIF_F_SG | 7199 NETIF_F_HW_VLAN_CTAG_RX | 7200 NETIF_F_HW_VLAN_CTAG_TX | 7201 NETIF_F_TSO | 7202 NETIF_F_TSO6 | 7203 NETIF_F_RXHASH | 7204 NETIF_F_RXCSUM | 7205 NETIF_F_HW_CSUM); 7206 7207 /* Set user-changeable features (subset of all device features) */ 7208 netdev->hw_features = netdev->features; 7209 netdev->hw_features |= NETIF_F_RXFCS; 7210 netdev->priv_flags |= IFF_SUPP_NOFCS; 7211 netdev->hw_features |= NETIF_F_RXALL; 7212 7213 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) 7214 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7215 7216 netdev->vlan_features |= (NETIF_F_SG | 7217 NETIF_F_TSO | 7218 NETIF_F_TSO6 | 7219 NETIF_F_HW_CSUM); 7220 7221 netdev->priv_flags |= IFF_UNICAST_FLT; 7222 7223 if (pci_using_dac) { 7224 netdev->features |= NETIF_F_HIGHDMA; 7225 netdev->vlan_features |= NETIF_F_HIGHDMA; 7226 } 7227 7228 /* MTU range: 68 - max_hw_frame_size */ 7229 netdev->min_mtu = ETH_MIN_MTU; 7230 netdev->max_mtu = adapter->max_hw_frame_size - 7231 (VLAN_ETH_HLEN + ETH_FCS_LEN); 7232 7233 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 7234 adapter->flags |= FLAG_MNG_PT_ENABLED; 7235 7236 /* before reading the NVM, reset the controller to 7237 * put the device in a known good starting state 7238 */ 7239 adapter->hw.mac.ops.reset_hw(&adapter->hw); 7240 7241 /* systems with ASPM and others may see the checksum fail on the first 7242 * attempt. Let's give it a few tries 7243 */ 7244 for (i = 0;; i++) { 7245 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) 7246 break; 7247 if (i == 2) { 7248 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 7249 err = -EIO; 7250 goto err_eeprom; 7251 } 7252 } 7253 7254 e1000_eeprom_checks(adapter); 7255 7256 /* copy the MAC address */ 7257 if (e1000e_read_mac_addr(&adapter->hw)) 7258 dev_err(&pdev->dev, 7259 "NVM Read Error while reading MAC address\n"); 7260 7261 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 7262 7263 if (!is_valid_ether_addr(netdev->dev_addr)) { 7264 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", 7265 netdev->dev_addr); 7266 err = -EIO; 7267 goto err_eeprom; 7268 } 7269 7270 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); 7271 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); 7272 7273 INIT_WORK(&adapter->reset_task, e1000_reset_task); 7274 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); 7275 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); 7276 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); 7277 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); 7278 7279 /* Initialize link parameters. User can change them with ethtool */ 7280 adapter->hw.mac.autoneg = 1; 7281 adapter->fc_autoneg = true; 7282 adapter->hw.fc.requested_mode = e1000_fc_default; 7283 adapter->hw.fc.current_mode = e1000_fc_default; 7284 adapter->hw.phy.autoneg_advertised = 0x2f; 7285 7286 /* Initial Wake on LAN setting - If APM wake is enabled in 7287 * the EEPROM, enable the ACPI Magic Packet filter 7288 */ 7289 if (adapter->flags & FLAG_APME_IN_WUC) { 7290 /* APME bit in EEPROM is mapped to WUC.APME */ 7291 eeprom_data = er32(WUC); 7292 eeprom_apme_mask = E1000_WUC_APME; 7293 if ((hw->mac.type > e1000_ich10lan) && 7294 (eeprom_data & E1000_WUC_PHY_WAKE)) 7295 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; 7296 } else if (adapter->flags & FLAG_APME_IN_CTRL3) { 7297 if (adapter->flags & FLAG_APME_CHECK_PORT_B && 7298 (adapter->hw.bus.func == 1)) 7299 ret_val = e1000_read_nvm(&adapter->hw, 7300 NVM_INIT_CONTROL3_PORT_B, 7301 1, &eeprom_data); 7302 else 7303 ret_val = e1000_read_nvm(&adapter->hw, 7304 NVM_INIT_CONTROL3_PORT_A, 7305 1, &eeprom_data); 7306 } 7307 7308 /* fetch WoL from EEPROM */ 7309 if (ret_val) 7310 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); 7311 else if (eeprom_data & eeprom_apme_mask) 7312 adapter->eeprom_wol |= E1000_WUFC_MAG; 7313 7314 /* now that we have the eeprom settings, apply the special cases 7315 * where the eeprom may be wrong or the board simply won't support 7316 * wake on lan on a particular port 7317 */ 7318 if (!(adapter->flags & FLAG_HAS_WOL)) 7319 adapter->eeprom_wol = 0; 7320 7321 /* initialize the wol settings based on the eeprom settings */ 7322 adapter->wol = adapter->eeprom_wol; 7323 7324 /* make sure adapter isn't asleep if manageability is enabled */ 7325 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || 7326 (hw->mac.ops.check_mng_mode(hw))) 7327 device_wakeup_enable(&pdev->dev); 7328 7329 /* save off EEPROM version number */ 7330 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); 7331 7332 if (ret_val) { 7333 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); 7334 adapter->eeprom_vers = 0; 7335 } 7336 7337 /* init PTP hardware clock */ 7338 e1000e_ptp_init(adapter); 7339 7340 /* reset the hardware with the new settings */ 7341 e1000e_reset(adapter); 7342 7343 /* If the controller has AMT, do not set DRV_LOAD until the interface 7344 * is up. For all other cases, let the f/w know that the h/w is now 7345 * under the control of the driver. 7346 */ 7347 if (!(adapter->flags & FLAG_HAS_AMT)) 7348 e1000e_get_hw_control(adapter); 7349 7350 strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); 7351 err = register_netdev(netdev); 7352 if (err) 7353 goto err_register; 7354 7355 /* carrier off reporting is important to ethtool even BEFORE open */ 7356 netif_carrier_off(netdev); 7357 7358 e1000_print_device_info(adapter); 7359 7360 if (pci_dev_run_wake(pdev)) 7361 pm_runtime_put_noidle(&pdev->dev); 7362 7363 return 0; 7364 7365 err_register: 7366 if (!(adapter->flags & FLAG_HAS_AMT)) 7367 e1000e_release_hw_control(adapter); 7368 err_eeprom: 7369 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) 7370 e1000_phy_hw_reset(&adapter->hw); 7371 err_hw_init: 7372 kfree(adapter->tx_ring); 7373 kfree(adapter->rx_ring); 7374 err_sw_init: 7375 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) 7376 iounmap(adapter->hw.flash_address); 7377 e1000e_reset_interrupt_capability(adapter); 7378 err_flashmap: 7379 iounmap(adapter->hw.hw_addr); 7380 err_ioremap: 7381 free_netdev(netdev); 7382 err_alloc_etherdev: 7383 pci_release_mem_regions(pdev); 7384 err_pci_reg: 7385 err_dma: 7386 pci_disable_device(pdev); 7387 return err; 7388 } 7389 7390 /** 7391 * e1000_remove - Device Removal Routine 7392 * @pdev: PCI device information struct 7393 * 7394 * e1000_remove is called by the PCI subsystem to alert the driver 7395 * that it should release a PCI device. The could be caused by a 7396 * Hot-Plug event, or because the driver is going to be removed from 7397 * memory. 7398 **/ 7399 static void e1000_remove(struct pci_dev *pdev) 7400 { 7401 struct net_device *netdev = pci_get_drvdata(pdev); 7402 struct e1000_adapter *adapter = netdev_priv(netdev); 7403 bool down = test_bit(__E1000_DOWN, &adapter->state); 7404 7405 e1000e_ptp_remove(adapter); 7406 7407 /* The timers may be rescheduled, so explicitly disable them 7408 * from being rescheduled. 7409 */ 7410 if (!down) 7411 set_bit(__E1000_DOWN, &adapter->state); 7412 del_timer_sync(&adapter->watchdog_timer); 7413 del_timer_sync(&adapter->phy_info_timer); 7414 7415 cancel_work_sync(&adapter->reset_task); 7416 cancel_work_sync(&adapter->watchdog_task); 7417 cancel_work_sync(&adapter->downshift_task); 7418 cancel_work_sync(&adapter->update_phy_task); 7419 cancel_work_sync(&adapter->print_hang_task); 7420 7421 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { 7422 cancel_work_sync(&adapter->tx_hwtstamp_work); 7423 if (adapter->tx_hwtstamp_skb) { 7424 dev_consume_skb_any(adapter->tx_hwtstamp_skb); 7425 adapter->tx_hwtstamp_skb = NULL; 7426 } 7427 } 7428 7429 /* Don't lie to e1000_close() down the road. */ 7430 if (!down) 7431 clear_bit(__E1000_DOWN, &adapter->state); 7432 unregister_netdev(netdev); 7433 7434 if (pci_dev_run_wake(pdev)) 7435 pm_runtime_get_noresume(&pdev->dev); 7436 7437 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7438 * would have already happened in close and is redundant. 7439 */ 7440 e1000e_release_hw_control(adapter); 7441 7442 e1000e_reset_interrupt_capability(adapter); 7443 kfree(adapter->tx_ring); 7444 kfree(adapter->rx_ring); 7445 7446 iounmap(adapter->hw.hw_addr); 7447 if ((adapter->hw.flash_address) && 7448 (adapter->hw.mac.type < e1000_pch_spt)) 7449 iounmap(adapter->hw.flash_address); 7450 pci_release_mem_regions(pdev); 7451 7452 free_netdev(netdev); 7453 7454 /* AER disable */ 7455 pci_disable_pcie_error_reporting(pdev); 7456 7457 pci_disable_device(pdev); 7458 } 7459 7460 /* PCI Error Recovery (ERS) */ 7461 static const struct pci_error_handlers e1000_err_handler = { 7462 .error_detected = e1000_io_error_detected, 7463 .slot_reset = e1000_io_slot_reset, 7464 .resume = e1000_io_resume, 7465 }; 7466 7467 static const struct pci_device_id e1000_pci_tbl[] = { 7468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, 7469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, 7470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, 7471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), 7472 board_82571 }, 7473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, 7474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, 7475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, 7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, 7477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, 7478 7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, 7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, 7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, 7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, 7483 7484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, 7485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, 7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, 7487 7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, 7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, 7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, 7491 7492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), 7493 board_80003es2lan }, 7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), 7495 board_80003es2lan }, 7496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), 7497 board_80003es2lan }, 7498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), 7499 board_80003es2lan }, 7500 7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, 7502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, 7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, 7504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, 7505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, 7506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, 7507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, 7508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, 7509 7510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, 7511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, 7512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, 7513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, 7514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, 7515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, 7516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, 7517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, 7518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, 7519 7520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, 7521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, 7522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, 7523 7524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, 7525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, 7526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, 7527 7528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, 7529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, 7530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, 7531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, 7532 7533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, 7534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, 7535 7536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, 7537 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, 7538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, 7539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, 7540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, 7541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, 7542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, 7543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, 7544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, 7545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, 7546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, 7547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, 7548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, 7549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, 7550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, 7551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, 7552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, 7553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, 7554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, 7555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, 7556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, 7557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, 7558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, 7559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, 7560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, 7561 7562 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ 7563 }; 7564 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7565 7566 static const struct dev_pm_ops e1000_pm_ops = { 7567 #ifdef CONFIG_PM_SLEEP 7568 .suspend = e1000e_pm_suspend, 7569 .resume = e1000e_pm_resume, 7570 .freeze = e1000e_pm_freeze, 7571 .thaw = e1000e_pm_thaw, 7572 .poweroff = e1000e_pm_suspend, 7573 .restore = e1000e_pm_resume, 7574 #endif 7575 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7576 e1000e_pm_runtime_idle) 7577 }; 7578 7579 /* PCI Device API Driver */ 7580 static struct pci_driver e1000_driver = { 7581 .name = e1000e_driver_name, 7582 .id_table = e1000_pci_tbl, 7583 .probe = e1000_probe, 7584 .remove = e1000_remove, 7585 .driver = { 7586 .pm = &e1000_pm_ops, 7587 }, 7588 .shutdown = e1000_shutdown, 7589 .err_handler = &e1000_err_handler 7590 }; 7591 7592 /** 7593 * e1000_init_module - Driver Registration Routine 7594 * 7595 * e1000_init_module is the first routine called when the driver is 7596 * loaded. All it does is register with the PCI subsystem. 7597 **/ 7598 static int __init e1000_init_module(void) 7599 { 7600 pr_info("Intel(R) PRO/1000 Network Driver - %s\n", 7601 e1000e_driver_version); 7602 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); 7603 7604 return pci_register_driver(&e1000_driver); 7605 } 7606 module_init(e1000_init_module); 7607 7608 /** 7609 * e1000_exit_module - Driver Exit Cleanup Routine 7610 * 7611 * e1000_exit_module is called just before the driver is removed 7612 * from memory. 7613 **/ 7614 static void __exit e1000_exit_module(void) 7615 { 7616 pci_unregister_driver(&e1000_driver); 7617 } 7618 module_exit(e1000_exit_module); 7619 7620 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 7621 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); 7622 MODULE_LICENSE("GPL"); 7623 MODULE_VERSION(DRV_VERSION); 7624 7625 /* netdev.c */ 7626