1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5 
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/aer.h>
27 #include <linux/prefetch.h>
28 
29 #include "e1000.h"
30 
31 #define DRV_EXTRAVERSION "-k"
32 
33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
34 char e1000e_driver_name[] = "e1000e";
35 const char e1000e_driver_version[] = DRV_VERSION;
36 
37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
38 static int debug = -1;
39 module_param(debug, int, 0);
40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
41 
42 static const struct e1000_info *e1000_info_tbl[] = {
43 	[board_82571]		= &e1000_82571_info,
44 	[board_82572]		= &e1000_82572_info,
45 	[board_82573]		= &e1000_82573_info,
46 	[board_82574]		= &e1000_82574_info,
47 	[board_82583]		= &e1000_82583_info,
48 	[board_80003es2lan]	= &e1000_es2_info,
49 	[board_ich8lan]		= &e1000_ich8_info,
50 	[board_ich9lan]		= &e1000_ich9_info,
51 	[board_ich10lan]	= &e1000_ich10_info,
52 	[board_pchlan]		= &e1000_pch_info,
53 	[board_pch2lan]		= &e1000_pch2_info,
54 	[board_pch_lpt]		= &e1000_pch_lpt_info,
55 	[board_pch_spt]		= &e1000_pch_spt_info,
56 	[board_pch_cnp]		= &e1000_pch_cnp_info,
57 };
58 
59 struct e1000_reg_info {
60 	u32 ofs;
61 	char *name;
62 };
63 
64 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
65 	/* General Registers */
66 	{E1000_CTRL, "CTRL"},
67 	{E1000_STATUS, "STATUS"},
68 	{E1000_CTRL_EXT, "CTRL_EXT"},
69 
70 	/* Interrupt Registers */
71 	{E1000_ICR, "ICR"},
72 
73 	/* Rx Registers */
74 	{E1000_RCTL, "RCTL"},
75 	{E1000_RDLEN(0), "RDLEN"},
76 	{E1000_RDH(0), "RDH"},
77 	{E1000_RDT(0), "RDT"},
78 	{E1000_RDTR, "RDTR"},
79 	{E1000_RXDCTL(0), "RXDCTL"},
80 	{E1000_ERT, "ERT"},
81 	{E1000_RDBAL(0), "RDBAL"},
82 	{E1000_RDBAH(0), "RDBAH"},
83 	{E1000_RDFH, "RDFH"},
84 	{E1000_RDFT, "RDFT"},
85 	{E1000_RDFHS, "RDFHS"},
86 	{E1000_RDFTS, "RDFTS"},
87 	{E1000_RDFPC, "RDFPC"},
88 
89 	/* Tx Registers */
90 	{E1000_TCTL, "TCTL"},
91 	{E1000_TDBAL(0), "TDBAL"},
92 	{E1000_TDBAH(0), "TDBAH"},
93 	{E1000_TDLEN(0), "TDLEN"},
94 	{E1000_TDH(0), "TDH"},
95 	{E1000_TDT(0), "TDT"},
96 	{E1000_TIDV, "TIDV"},
97 	{E1000_TXDCTL(0), "TXDCTL"},
98 	{E1000_TADV, "TADV"},
99 	{E1000_TARC(0), "TARC"},
100 	{E1000_TDFH, "TDFH"},
101 	{E1000_TDFT, "TDFT"},
102 	{E1000_TDFHS, "TDFHS"},
103 	{E1000_TDFTS, "TDFTS"},
104 	{E1000_TDFPC, "TDFPC"},
105 
106 	/* List Terminator */
107 	{0, NULL}
108 };
109 
110 /**
111  * __ew32_prepare - prepare to write to MAC CSR register on certain parts
112  * @hw: pointer to the HW structure
113  *
114  * When updating the MAC CSR registers, the Manageability Engine (ME) could
115  * be accessing the registers at the same time.  Normally, this is handled in
116  * h/w by an arbiter but on some parts there is a bug that acknowledges Host
117  * accesses later than it should which could result in the register to have
118  * an incorrect value.  Workaround this by checking the FWSM register which
119  * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
120  * and try again a number of times.
121  **/
122 s32 __ew32_prepare(struct e1000_hw *hw)
123 {
124 	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
125 
126 	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
127 		udelay(50);
128 
129 	return i;
130 }
131 
132 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
133 {
134 	if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
135 		__ew32_prepare(hw);
136 
137 	writel(val, hw->hw_addr + reg);
138 }
139 
140 /**
141  * e1000_regdump - register printout routine
142  * @hw: pointer to the HW structure
143  * @reginfo: pointer to the register info table
144  **/
145 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
146 {
147 	int n = 0;
148 	char rname[16];
149 	u32 regs[8];
150 
151 	switch (reginfo->ofs) {
152 	case E1000_RXDCTL(0):
153 		for (n = 0; n < 2; n++)
154 			regs[n] = __er32(hw, E1000_RXDCTL(n));
155 		break;
156 	case E1000_TXDCTL(0):
157 		for (n = 0; n < 2; n++)
158 			regs[n] = __er32(hw, E1000_TXDCTL(n));
159 		break;
160 	case E1000_TARC(0):
161 		for (n = 0; n < 2; n++)
162 			regs[n] = __er32(hw, E1000_TARC(n));
163 		break;
164 	default:
165 		pr_info("%-15s %08x\n",
166 			reginfo->name, __er32(hw, reginfo->ofs));
167 		return;
168 	}
169 
170 	snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
171 	pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
172 }
173 
174 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
175 				 struct e1000_buffer *bi)
176 {
177 	int i;
178 	struct e1000_ps_page *ps_page;
179 
180 	for (i = 0; i < adapter->rx_ps_pages; i++) {
181 		ps_page = &bi->ps_pages[i];
182 
183 		if (ps_page->page) {
184 			pr_info("packet dump for ps_page %d:\n", i);
185 			print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
186 				       16, 1, page_address(ps_page->page),
187 				       PAGE_SIZE, true);
188 		}
189 	}
190 }
191 
192 /**
193  * e1000e_dump - Print registers, Tx-ring and Rx-ring
194  * @adapter: board private structure
195  **/
196 static void e1000e_dump(struct e1000_adapter *adapter)
197 {
198 	struct net_device *netdev = adapter->netdev;
199 	struct e1000_hw *hw = &adapter->hw;
200 	struct e1000_reg_info *reginfo;
201 	struct e1000_ring *tx_ring = adapter->tx_ring;
202 	struct e1000_tx_desc *tx_desc;
203 	struct my_u0 {
204 		__le64 a;
205 		__le64 b;
206 	} *u0;
207 	struct e1000_buffer *buffer_info;
208 	struct e1000_ring *rx_ring = adapter->rx_ring;
209 	union e1000_rx_desc_packet_split *rx_desc_ps;
210 	union e1000_rx_desc_extended *rx_desc;
211 	struct my_u1 {
212 		__le64 a;
213 		__le64 b;
214 		__le64 c;
215 		__le64 d;
216 	} *u1;
217 	u32 staterr;
218 	int i = 0;
219 
220 	if (!netif_msg_hw(adapter))
221 		return;
222 
223 	/* Print netdevice Info */
224 	if (netdev) {
225 		dev_info(&adapter->pdev->dev, "Net device Info\n");
226 		pr_info("Device Name     state            trans_start\n");
227 		pr_info("%-15s %016lX %016lX\n", netdev->name,
228 			netdev->state, dev_trans_start(netdev));
229 	}
230 
231 	/* Print Registers */
232 	dev_info(&adapter->pdev->dev, "Register Dump\n");
233 	pr_info(" Register Name   Value\n");
234 	for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
235 	     reginfo->name; reginfo++) {
236 		e1000_regdump(hw, reginfo);
237 	}
238 
239 	/* Print Tx Ring Summary */
240 	if (!netdev || !netif_running(netdev))
241 		return;
242 
243 	dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
244 	pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
245 	buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
246 	pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
247 		0, tx_ring->next_to_use, tx_ring->next_to_clean,
248 		(unsigned long long)buffer_info->dma,
249 		buffer_info->length,
250 		buffer_info->next_to_watch,
251 		(unsigned long long)buffer_info->time_stamp);
252 
253 	/* Print Tx Ring */
254 	if (!netif_msg_tx_done(adapter))
255 		goto rx_ring_summary;
256 
257 	dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
258 
259 	/* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
260 	 *
261 	 * Legacy Transmit Descriptor
262 	 *   +--------------------------------------------------------------+
263 	 * 0 |         Buffer Address [63:0] (Reserved on Write Back)       |
264 	 *   +--------------------------------------------------------------+
265 	 * 8 | Special  |    CSS     | Status |  CMD    |  CSO   |  Length  |
266 	 *   +--------------------------------------------------------------+
267 	 *   63       48 47        36 35    32 31     24 23    16 15        0
268 	 *
269 	 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
270 	 *   63      48 47    40 39       32 31             16 15    8 7      0
271 	 *   +----------------------------------------------------------------+
272 	 * 0 |  TUCSE  | TUCS0  |   TUCSS   |     IPCSE       | IPCS0 | IPCSS |
273 	 *   +----------------------------------------------------------------+
274 	 * 8 |   MSS   | HDRLEN | RSV | STA | TUCMD | DTYP |      PAYLEN      |
275 	 *   +----------------------------------------------------------------+
276 	 *   63      48 47    40 39 36 35 32 31   24 23  20 19                0
277 	 *
278 	 * Extended Data Descriptor (DTYP=0x1)
279 	 *   +----------------------------------------------------------------+
280 	 * 0 |                     Buffer Address [63:0]                      |
281 	 *   +----------------------------------------------------------------+
282 	 * 8 | VLAN tag |  POPTS  | Rsvd | Status | Command | DTYP |  DTALEN  |
283 	 *   +----------------------------------------------------------------+
284 	 *   63       48 47     40 39  36 35    32 31     24 23  20 19        0
285 	 */
286 	pr_info("Tl[desc]     [address 63:0  ] [SpeCssSCmCsLen] [bi->dma       ] leng  ntw timestamp        bi->skb <-- Legacy format\n");
287 	pr_info("Tc[desc]     [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma       ] leng  ntw timestamp        bi->skb <-- Ext Context format\n");
288 	pr_info("Td[desc]     [address 63:0  ] [VlaPoRSCm1Dlen] [bi->dma       ] leng  ntw timestamp        bi->skb <-- Ext Data format\n");
289 	for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
290 		const char *next_desc;
291 		tx_desc = E1000_TX_DESC(*tx_ring, i);
292 		buffer_info = &tx_ring->buffer_info[i];
293 		u0 = (struct my_u0 *)tx_desc;
294 		if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
295 			next_desc = " NTC/U";
296 		else if (i == tx_ring->next_to_use)
297 			next_desc = " NTU";
298 		else if (i == tx_ring->next_to_clean)
299 			next_desc = " NTC";
300 		else
301 			next_desc = "";
302 		pr_info("T%c[0x%03X]    %016llX %016llX %016llX %04X  %3X %016llX %p%s\n",
303 			(!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
304 			 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
305 			i,
306 			(unsigned long long)le64_to_cpu(u0->a),
307 			(unsigned long long)le64_to_cpu(u0->b),
308 			(unsigned long long)buffer_info->dma,
309 			buffer_info->length, buffer_info->next_to_watch,
310 			(unsigned long long)buffer_info->time_stamp,
311 			buffer_info->skb, next_desc);
312 
313 		if (netif_msg_pktdata(adapter) && buffer_info->skb)
314 			print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
315 				       16, 1, buffer_info->skb->data,
316 				       buffer_info->skb->len, true);
317 	}
318 
319 	/* Print Rx Ring Summary */
320 rx_ring_summary:
321 	dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
322 	pr_info("Queue [NTU] [NTC]\n");
323 	pr_info(" %5d %5X %5X\n",
324 		0, rx_ring->next_to_use, rx_ring->next_to_clean);
325 
326 	/* Print Rx Ring */
327 	if (!netif_msg_rx_status(adapter))
328 		return;
329 
330 	dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
331 	switch (adapter->rx_ps_pages) {
332 	case 1:
333 	case 2:
334 	case 3:
335 		/* [Extended] Packet Split Receive Descriptor Format
336 		 *
337 		 *    +-----------------------------------------------------+
338 		 *  0 |                Buffer Address 0 [63:0]              |
339 		 *    +-----------------------------------------------------+
340 		 *  8 |                Buffer Address 1 [63:0]              |
341 		 *    +-----------------------------------------------------+
342 		 * 16 |                Buffer Address 2 [63:0]              |
343 		 *    +-----------------------------------------------------+
344 		 * 24 |                Buffer Address 3 [63:0]              |
345 		 *    +-----------------------------------------------------+
346 		 */
347 		pr_info("R  [desc]      [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma       ] [bi->skb] <-- Ext Pkt Split format\n");
348 		/* [Extended] Receive Descriptor (Write-Back) Format
349 		 *
350 		 *   63       48 47    32 31     13 12    8 7    4 3        0
351 		 *   +------------------------------------------------------+
352 		 * 0 | Packet   | IP     |  Rsvd   | MRQ   | Rsvd | MRQ RSS |
353 		 *   | Checksum | Ident  |         | Queue |      |  Type   |
354 		 *   +------------------------------------------------------+
355 		 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
356 		 *   +------------------------------------------------------+
357 		 *   63       48 47    32 31            20 19               0
358 		 */
359 		pr_info("RWB[desc]      [ck ipid mrqhsh] [vl   l0 ee  es] [ l3  l2  l1 hs] [reserved      ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 		for (i = 0; i < rx_ring->count; i++) {
361 			const char *next_desc;
362 			buffer_info = &rx_ring->buffer_info[i];
363 			rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
364 			u1 = (struct my_u1 *)rx_desc_ps;
365 			staterr =
366 			    le32_to_cpu(rx_desc_ps->wb.middle.status_error);
367 
368 			if (i == rx_ring->next_to_use)
369 				next_desc = " NTU";
370 			else if (i == rx_ring->next_to_clean)
371 				next_desc = " NTC";
372 			else
373 				next_desc = "";
374 
375 			if (staterr & E1000_RXD_STAT_DD) {
376 				/* Descriptor Done */
377 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %016llX ---------------- %p%s\n",
378 					"RWB", i,
379 					(unsigned long long)le64_to_cpu(u1->a),
380 					(unsigned long long)le64_to_cpu(u1->b),
381 					(unsigned long long)le64_to_cpu(u1->c),
382 					(unsigned long long)le64_to_cpu(u1->d),
383 					buffer_info->skb, next_desc);
384 			} else {
385 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %016llX %016llX %p%s\n",
386 					"R  ", i,
387 					(unsigned long long)le64_to_cpu(u1->a),
388 					(unsigned long long)le64_to_cpu(u1->b),
389 					(unsigned long long)le64_to_cpu(u1->c),
390 					(unsigned long long)le64_to_cpu(u1->d),
391 					(unsigned long long)buffer_info->dma,
392 					buffer_info->skb, next_desc);
393 
394 				if (netif_msg_pktdata(adapter))
395 					e1000e_dump_ps_pages(adapter,
396 							     buffer_info);
397 			}
398 		}
399 		break;
400 	default:
401 	case 0:
402 		/* Extended Receive Descriptor (Read) Format
403 		 *
404 		 *   +-----------------------------------------------------+
405 		 * 0 |                Buffer Address [63:0]                |
406 		 *   +-----------------------------------------------------+
407 		 * 8 |                      Reserved                       |
408 		 *   +-----------------------------------------------------+
409 		 */
410 		pr_info("R  [desc]      [buf addr 63:0 ] [reserved 63:0 ] [bi->dma       ] [bi->skb] <-- Ext (Read) format\n");
411 		/* Extended Receive Descriptor (Write-Back) Format
412 		 *
413 		 *   63       48 47    32 31    24 23            4 3        0
414 		 *   +------------------------------------------------------+
415 		 *   |     RSS Hash      |        |               |         |
416 		 * 0 +-------------------+  Rsvd  |   Reserved    | MRQ RSS |
417 		 *   | Packet   | IP     |        |               |  Type   |
418 		 *   | Checksum | Ident  |        |               |         |
419 		 *   +------------------------------------------------------+
420 		 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
421 		 *   +------------------------------------------------------+
422 		 *   63       48 47    32 31            20 19               0
423 		 */
424 		pr_info("RWB[desc]      [cs ipid    mrq] [vt   ln xe  xs] [bi->skb] <-- Ext (Write-Back) format\n");
425 
426 		for (i = 0; i < rx_ring->count; i++) {
427 			const char *next_desc;
428 
429 			buffer_info = &rx_ring->buffer_info[i];
430 			rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
431 			u1 = (struct my_u1 *)rx_desc;
432 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
433 
434 			if (i == rx_ring->next_to_use)
435 				next_desc = " NTU";
436 			else if (i == rx_ring->next_to_clean)
437 				next_desc = " NTC";
438 			else
439 				next_desc = "";
440 
441 			if (staterr & E1000_RXD_STAT_DD) {
442 				/* Descriptor Done */
443 				pr_info("%s[0x%03X]     %016llX %016llX ---------------- %p%s\n",
444 					"RWB", i,
445 					(unsigned long long)le64_to_cpu(u1->a),
446 					(unsigned long long)le64_to_cpu(u1->b),
447 					buffer_info->skb, next_desc);
448 			} else {
449 				pr_info("%s[0x%03X]     %016llX %016llX %016llX %p%s\n",
450 					"R  ", i,
451 					(unsigned long long)le64_to_cpu(u1->a),
452 					(unsigned long long)le64_to_cpu(u1->b),
453 					(unsigned long long)buffer_info->dma,
454 					buffer_info->skb, next_desc);
455 
456 				if (netif_msg_pktdata(adapter) &&
457 				    buffer_info->skb)
458 					print_hex_dump(KERN_INFO, "",
459 						       DUMP_PREFIX_ADDRESS, 16,
460 						       1,
461 						       buffer_info->skb->data,
462 						       adapter->rx_buffer_len,
463 						       true);
464 			}
465 		}
466 	}
467 }
468 
469 /**
470  * e1000_desc_unused - calculate if we have unused descriptors
471  **/
472 static int e1000_desc_unused(struct e1000_ring *ring)
473 {
474 	if (ring->next_to_clean > ring->next_to_use)
475 		return ring->next_to_clean - ring->next_to_use - 1;
476 
477 	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478 }
479 
480 /**
481  * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482  * @adapter: board private structure
483  * @hwtstamps: time stamp structure to update
484  * @systim: unsigned 64bit system time value.
485  *
486  * Convert the system time value stored in the RX/TXSTMP registers into a
487  * hwtstamp which can be used by the upper level time stamping functions.
488  *
489  * The 'systim_lock' spinlock is used to protect the consistency of the
490  * system time value. This is needed because reading the 64 bit time
491  * value involves reading two 32 bit registers. The first read latches the
492  * value.
493  **/
494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 				      struct skb_shared_hwtstamps *hwtstamps,
496 				      u64 systim)
497 {
498 	u64 ns;
499 	unsigned long flags;
500 
501 	spin_lock_irqsave(&adapter->systim_lock, flags);
502 	ns = timecounter_cyc2time(&adapter->tc, systim);
503 	spin_unlock_irqrestore(&adapter->systim_lock, flags);
504 
505 	memset(hwtstamps, 0, sizeof(*hwtstamps));
506 	hwtstamps->hwtstamp = ns_to_ktime(ns);
507 }
508 
509 /**
510  * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511  * @adapter: board private structure
512  * @status: descriptor extended error and status field
513  * @skb: particular skb to include time stamp
514  *
515  * If the time stamp is valid, convert it into the timecounter ns value
516  * and store that result into the shhwtstamps structure which is passed
517  * up the network stack.
518  **/
519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 			       struct sk_buff *skb)
521 {
522 	struct e1000_hw *hw = &adapter->hw;
523 	u64 rxstmp;
524 
525 	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 	    !(status & E1000_RXDEXT_STATERR_TST) ||
527 	    !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 		return;
529 
530 	/* The Rx time stamp registers contain the time stamp.  No other
531 	 * received packet will be time stamped until the Rx time stamp
532 	 * registers are read.  Because only one packet can be time stamped
533 	 * at a time, the register values must belong to this packet and
534 	 * therefore none of the other additional attributes need to be
535 	 * compared.
536 	 */
537 	rxstmp = (u64)er32(RXSTMPL);
538 	rxstmp |= (u64)er32(RXSTMPH) << 32;
539 	e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540 
541 	adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542 }
543 
544 /**
545  * e1000_receive_skb - helper function to handle Rx indications
546  * @adapter: board private structure
547  * @staterr: descriptor extended error and status field as written by hardware
548  * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
549  * @skb: pointer to sk_buff to be indicated to stack
550  **/
551 static void e1000_receive_skb(struct e1000_adapter *adapter,
552 			      struct net_device *netdev, struct sk_buff *skb,
553 			      u32 staterr, __le16 vlan)
554 {
555 	u16 tag = le16_to_cpu(vlan);
556 
557 	e1000e_rx_hwtstamp(adapter, staterr, skb);
558 
559 	skb->protocol = eth_type_trans(skb, netdev);
560 
561 	if (staterr & E1000_RXD_STAT_VP)
562 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
563 
564 	napi_gro_receive(&adapter->napi, skb);
565 }
566 
567 /**
568  * e1000_rx_checksum - Receive Checksum Offload
569  * @adapter: board private structure
570  * @status_err: receive descriptor status and error fields
571  * @csum: receive descriptor csum field
572  * @sk_buff: socket buffer with received data
573  **/
574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 			      struct sk_buff *skb)
576 {
577 	u16 status = (u16)status_err;
578 	u8 errors = (u8)(status_err >> 24);
579 
580 	skb_checksum_none_assert(skb);
581 
582 	/* Rx checksum disabled */
583 	if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 		return;
585 
586 	/* Ignore Checksum bit is set */
587 	if (status & E1000_RXD_STAT_IXSM)
588 		return;
589 
590 	/* TCP/UDP checksum error bit or IP checksum error bit is set */
591 	if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 		/* let the stack verify checksum errors */
593 		adapter->hw_csum_err++;
594 		return;
595 	}
596 
597 	/* TCP/UDP Checksum has not been calculated */
598 	if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 		return;
600 
601 	/* It must be a TCP or UDP packet with a valid checksum */
602 	skb->ip_summed = CHECKSUM_UNNECESSARY;
603 	adapter->hw_csum_good++;
604 }
605 
606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607 {
608 	struct e1000_adapter *adapter = rx_ring->adapter;
609 	struct e1000_hw *hw = &adapter->hw;
610 	s32 ret_val = __ew32_prepare(hw);
611 
612 	writel(i, rx_ring->tail);
613 
614 	if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
615 		u32 rctl = er32(RCTL);
616 
617 		ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 		e_err("ME firmware caused invalid RDT - resetting\n");
619 		schedule_work(&adapter->reset_task);
620 	}
621 }
622 
623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624 {
625 	struct e1000_adapter *adapter = tx_ring->adapter;
626 	struct e1000_hw *hw = &adapter->hw;
627 	s32 ret_val = __ew32_prepare(hw);
628 
629 	writel(i, tx_ring->tail);
630 
631 	if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
632 		u32 tctl = er32(TCTL);
633 
634 		ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 		e_err("ME firmware caused invalid TDT - resetting\n");
636 		schedule_work(&adapter->reset_task);
637 	}
638 }
639 
640 /**
641  * e1000_alloc_rx_buffers - Replace used receive buffers
642  * @rx_ring: Rx descriptor ring
643  **/
644 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
645 				   int cleaned_count, gfp_t gfp)
646 {
647 	struct e1000_adapter *adapter = rx_ring->adapter;
648 	struct net_device *netdev = adapter->netdev;
649 	struct pci_dev *pdev = adapter->pdev;
650 	union e1000_rx_desc_extended *rx_desc;
651 	struct e1000_buffer *buffer_info;
652 	struct sk_buff *skb;
653 	unsigned int i;
654 	unsigned int bufsz = adapter->rx_buffer_len;
655 
656 	i = rx_ring->next_to_use;
657 	buffer_info = &rx_ring->buffer_info[i];
658 
659 	while (cleaned_count--) {
660 		skb = buffer_info->skb;
661 		if (skb) {
662 			skb_trim(skb, 0);
663 			goto map_skb;
664 		}
665 
666 		skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
667 		if (!skb) {
668 			/* Better luck next round */
669 			adapter->alloc_rx_buff_failed++;
670 			break;
671 		}
672 
673 		buffer_info->skb = skb;
674 map_skb:
675 		buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
676 						  adapter->rx_buffer_len,
677 						  DMA_FROM_DEVICE);
678 		if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
679 			dev_err(&pdev->dev, "Rx DMA map failed\n");
680 			adapter->rx_dma_failed++;
681 			break;
682 		}
683 
684 		rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
685 		rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
686 
687 		if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
688 			/* Force memory writes to complete before letting h/w
689 			 * know there are new descriptors to fetch.  (Only
690 			 * applicable for weak-ordered memory model archs,
691 			 * such as IA-64).
692 			 */
693 			wmb();
694 			if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
695 				e1000e_update_rdt_wa(rx_ring, i);
696 			else
697 				writel(i, rx_ring->tail);
698 		}
699 		i++;
700 		if (i == rx_ring->count)
701 			i = 0;
702 		buffer_info = &rx_ring->buffer_info[i];
703 	}
704 
705 	rx_ring->next_to_use = i;
706 }
707 
708 /**
709  * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
710  * @rx_ring: Rx descriptor ring
711  **/
712 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
713 				      int cleaned_count, gfp_t gfp)
714 {
715 	struct e1000_adapter *adapter = rx_ring->adapter;
716 	struct net_device *netdev = adapter->netdev;
717 	struct pci_dev *pdev = adapter->pdev;
718 	union e1000_rx_desc_packet_split *rx_desc;
719 	struct e1000_buffer *buffer_info;
720 	struct e1000_ps_page *ps_page;
721 	struct sk_buff *skb;
722 	unsigned int i, j;
723 
724 	i = rx_ring->next_to_use;
725 	buffer_info = &rx_ring->buffer_info[i];
726 
727 	while (cleaned_count--) {
728 		rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
729 
730 		for (j = 0; j < PS_PAGE_BUFFERS; j++) {
731 			ps_page = &buffer_info->ps_pages[j];
732 			if (j >= adapter->rx_ps_pages) {
733 				/* all unused desc entries get hw null ptr */
734 				rx_desc->read.buffer_addr[j + 1] =
735 				    ~cpu_to_le64(0);
736 				continue;
737 			}
738 			if (!ps_page->page) {
739 				ps_page->page = alloc_page(gfp);
740 				if (!ps_page->page) {
741 					adapter->alloc_rx_buff_failed++;
742 					goto no_buffers;
743 				}
744 				ps_page->dma = dma_map_page(&pdev->dev,
745 							    ps_page->page,
746 							    0, PAGE_SIZE,
747 							    DMA_FROM_DEVICE);
748 				if (dma_mapping_error(&pdev->dev,
749 						      ps_page->dma)) {
750 					dev_err(&adapter->pdev->dev,
751 						"Rx DMA page map failed\n");
752 					adapter->rx_dma_failed++;
753 					goto no_buffers;
754 				}
755 			}
756 			/* Refresh the desc even if buffer_addrs
757 			 * didn't change because each write-back
758 			 * erases this info.
759 			 */
760 			rx_desc->read.buffer_addr[j + 1] =
761 			    cpu_to_le64(ps_page->dma);
762 		}
763 
764 		skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
765 						  gfp);
766 
767 		if (!skb) {
768 			adapter->alloc_rx_buff_failed++;
769 			break;
770 		}
771 
772 		buffer_info->skb = skb;
773 		buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
774 						  adapter->rx_ps_bsize0,
775 						  DMA_FROM_DEVICE);
776 		if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
777 			dev_err(&pdev->dev, "Rx DMA map failed\n");
778 			adapter->rx_dma_failed++;
779 			/* cleanup skb */
780 			dev_kfree_skb_any(skb);
781 			buffer_info->skb = NULL;
782 			break;
783 		}
784 
785 		rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
786 
787 		if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
788 			/* Force memory writes to complete before letting h/w
789 			 * know there are new descriptors to fetch.  (Only
790 			 * applicable for weak-ordered memory model archs,
791 			 * such as IA-64).
792 			 */
793 			wmb();
794 			if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
795 				e1000e_update_rdt_wa(rx_ring, i << 1);
796 			else
797 				writel(i << 1, rx_ring->tail);
798 		}
799 
800 		i++;
801 		if (i == rx_ring->count)
802 			i = 0;
803 		buffer_info = &rx_ring->buffer_info[i];
804 	}
805 
806 no_buffers:
807 	rx_ring->next_to_use = i;
808 }
809 
810 /**
811  * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
812  * @rx_ring: Rx descriptor ring
813  * @cleaned_count: number of buffers to allocate this pass
814  **/
815 
816 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
817 					 int cleaned_count, gfp_t gfp)
818 {
819 	struct e1000_adapter *adapter = rx_ring->adapter;
820 	struct net_device *netdev = adapter->netdev;
821 	struct pci_dev *pdev = adapter->pdev;
822 	union e1000_rx_desc_extended *rx_desc;
823 	struct e1000_buffer *buffer_info;
824 	struct sk_buff *skb;
825 	unsigned int i;
826 	unsigned int bufsz = 256 - 16;	/* for skb_reserve */
827 
828 	i = rx_ring->next_to_use;
829 	buffer_info = &rx_ring->buffer_info[i];
830 
831 	while (cleaned_count--) {
832 		skb = buffer_info->skb;
833 		if (skb) {
834 			skb_trim(skb, 0);
835 			goto check_page;
836 		}
837 
838 		skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
839 		if (unlikely(!skb)) {
840 			/* Better luck next round */
841 			adapter->alloc_rx_buff_failed++;
842 			break;
843 		}
844 
845 		buffer_info->skb = skb;
846 check_page:
847 		/* allocate a new page if necessary */
848 		if (!buffer_info->page) {
849 			buffer_info->page = alloc_page(gfp);
850 			if (unlikely(!buffer_info->page)) {
851 				adapter->alloc_rx_buff_failed++;
852 				break;
853 			}
854 		}
855 
856 		if (!buffer_info->dma) {
857 			buffer_info->dma = dma_map_page(&pdev->dev,
858 							buffer_info->page, 0,
859 							PAGE_SIZE,
860 							DMA_FROM_DEVICE);
861 			if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
862 				adapter->alloc_rx_buff_failed++;
863 				break;
864 			}
865 		}
866 
867 		rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
868 		rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
869 
870 		if (unlikely(++i == rx_ring->count))
871 			i = 0;
872 		buffer_info = &rx_ring->buffer_info[i];
873 	}
874 
875 	if (likely(rx_ring->next_to_use != i)) {
876 		rx_ring->next_to_use = i;
877 		if (unlikely(i-- == 0))
878 			i = (rx_ring->count - 1);
879 
880 		/* Force memory writes to complete before letting h/w
881 		 * know there are new descriptors to fetch.  (Only
882 		 * applicable for weak-ordered memory model archs,
883 		 * such as IA-64).
884 		 */
885 		wmb();
886 		if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
887 			e1000e_update_rdt_wa(rx_ring, i);
888 		else
889 			writel(i, rx_ring->tail);
890 	}
891 }
892 
893 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
894 				 struct sk_buff *skb)
895 {
896 	if (netdev->features & NETIF_F_RXHASH)
897 		skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
898 }
899 
900 /**
901  * e1000_clean_rx_irq - Send received data up the network stack
902  * @rx_ring: Rx descriptor ring
903  *
904  * the return value indicates whether actual cleaning was done, there
905  * is no guarantee that everything was cleaned
906  **/
907 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
908 			       int work_to_do)
909 {
910 	struct e1000_adapter *adapter = rx_ring->adapter;
911 	struct net_device *netdev = adapter->netdev;
912 	struct pci_dev *pdev = adapter->pdev;
913 	struct e1000_hw *hw = &adapter->hw;
914 	union e1000_rx_desc_extended *rx_desc, *next_rxd;
915 	struct e1000_buffer *buffer_info, *next_buffer;
916 	u32 length, staterr;
917 	unsigned int i;
918 	int cleaned_count = 0;
919 	bool cleaned = false;
920 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
921 
922 	i = rx_ring->next_to_clean;
923 	rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
924 	staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
925 	buffer_info = &rx_ring->buffer_info[i];
926 
927 	while (staterr & E1000_RXD_STAT_DD) {
928 		struct sk_buff *skb;
929 
930 		if (*work_done >= work_to_do)
931 			break;
932 		(*work_done)++;
933 		dma_rmb();	/* read descriptor and rx_buffer_info after status DD */
934 
935 		skb = buffer_info->skb;
936 		buffer_info->skb = NULL;
937 
938 		prefetch(skb->data - NET_IP_ALIGN);
939 
940 		i++;
941 		if (i == rx_ring->count)
942 			i = 0;
943 		next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
944 		prefetch(next_rxd);
945 
946 		next_buffer = &rx_ring->buffer_info[i];
947 
948 		cleaned = true;
949 		cleaned_count++;
950 		dma_unmap_single(&pdev->dev, buffer_info->dma,
951 				 adapter->rx_buffer_len, DMA_FROM_DEVICE);
952 		buffer_info->dma = 0;
953 
954 		length = le16_to_cpu(rx_desc->wb.upper.length);
955 
956 		/* !EOP means multiple descriptors were used to store a single
957 		 * packet, if that's the case we need to toss it.  In fact, we
958 		 * need to toss every packet with the EOP bit clear and the
959 		 * next frame that _does_ have the EOP bit set, as it is by
960 		 * definition only a frame fragment
961 		 */
962 		if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
963 			adapter->flags2 |= FLAG2_IS_DISCARDING;
964 
965 		if (adapter->flags2 & FLAG2_IS_DISCARDING) {
966 			/* All receives must fit into a single buffer */
967 			e_dbg("Receive packet consumed multiple buffers\n");
968 			/* recycle */
969 			buffer_info->skb = skb;
970 			if (staterr & E1000_RXD_STAT_EOP)
971 				adapter->flags2 &= ~FLAG2_IS_DISCARDING;
972 			goto next_desc;
973 		}
974 
975 		if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
976 			     !(netdev->features & NETIF_F_RXALL))) {
977 			/* recycle */
978 			buffer_info->skb = skb;
979 			goto next_desc;
980 		}
981 
982 		/* adjust length to remove Ethernet CRC */
983 		if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
984 			/* If configured to store CRC, don't subtract FCS,
985 			 * but keep the FCS bytes out of the total_rx_bytes
986 			 * counter
987 			 */
988 			if (netdev->features & NETIF_F_RXFCS)
989 				total_rx_bytes -= 4;
990 			else
991 				length -= 4;
992 		}
993 
994 		total_rx_bytes += length;
995 		total_rx_packets++;
996 
997 		/* code added for copybreak, this should improve
998 		 * performance for small packets with large amounts
999 		 * of reassembly being done in the stack
1000 		 */
1001 		if (length < copybreak) {
1002 			struct sk_buff *new_skb =
1003 				napi_alloc_skb(&adapter->napi, length);
1004 			if (new_skb) {
1005 				skb_copy_to_linear_data_offset(new_skb,
1006 							       -NET_IP_ALIGN,
1007 							       (skb->data -
1008 								NET_IP_ALIGN),
1009 							       (length +
1010 								NET_IP_ALIGN));
1011 				/* save the skb in buffer_info as good */
1012 				buffer_info->skb = skb;
1013 				skb = new_skb;
1014 			}
1015 			/* else just continue with the old one */
1016 		}
1017 		/* end copybreak code */
1018 		skb_put(skb, length);
1019 
1020 		/* Receive Checksum Offload */
1021 		e1000_rx_checksum(adapter, staterr, skb);
1022 
1023 		e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1024 
1025 		e1000_receive_skb(adapter, netdev, skb, staterr,
1026 				  rx_desc->wb.upper.vlan);
1027 
1028 next_desc:
1029 		rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1030 
1031 		/* return some buffers to hardware, one at a time is too slow */
1032 		if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1033 			adapter->alloc_rx_buf(rx_ring, cleaned_count,
1034 					      GFP_ATOMIC);
1035 			cleaned_count = 0;
1036 		}
1037 
1038 		/* use prefetched values */
1039 		rx_desc = next_rxd;
1040 		buffer_info = next_buffer;
1041 
1042 		staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1043 	}
1044 	rx_ring->next_to_clean = i;
1045 
1046 	cleaned_count = e1000_desc_unused(rx_ring);
1047 	if (cleaned_count)
1048 		adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1049 
1050 	adapter->total_rx_bytes += total_rx_bytes;
1051 	adapter->total_rx_packets += total_rx_packets;
1052 	return cleaned;
1053 }
1054 
1055 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1056 			    struct e1000_buffer *buffer_info,
1057 			    bool drop)
1058 {
1059 	struct e1000_adapter *adapter = tx_ring->adapter;
1060 
1061 	if (buffer_info->dma) {
1062 		if (buffer_info->mapped_as_page)
1063 			dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1064 				       buffer_info->length, DMA_TO_DEVICE);
1065 		else
1066 			dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1067 					 buffer_info->length, DMA_TO_DEVICE);
1068 		buffer_info->dma = 0;
1069 	}
1070 	if (buffer_info->skb) {
1071 		if (drop)
1072 			dev_kfree_skb_any(buffer_info->skb);
1073 		else
1074 			dev_consume_skb_any(buffer_info->skb);
1075 		buffer_info->skb = NULL;
1076 	}
1077 	buffer_info->time_stamp = 0;
1078 }
1079 
1080 static void e1000_print_hw_hang(struct work_struct *work)
1081 {
1082 	struct e1000_adapter *adapter = container_of(work,
1083 						     struct e1000_adapter,
1084 						     print_hang_task);
1085 	struct net_device *netdev = adapter->netdev;
1086 	struct e1000_ring *tx_ring = adapter->tx_ring;
1087 	unsigned int i = tx_ring->next_to_clean;
1088 	unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1089 	struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1090 	struct e1000_hw *hw = &adapter->hw;
1091 	u16 phy_status, phy_1000t_status, phy_ext_status;
1092 	u16 pci_status;
1093 
1094 	if (test_bit(__E1000_DOWN, &adapter->state))
1095 		return;
1096 
1097 	if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1098 		/* May be block on write-back, flush and detect again
1099 		 * flush pending descriptor writebacks to memory
1100 		 */
1101 		ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1102 		/* execute the writes immediately */
1103 		e1e_flush();
1104 		/* Due to rare timing issues, write to TIDV again to ensure
1105 		 * the write is successful
1106 		 */
1107 		ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1108 		/* execute the writes immediately */
1109 		e1e_flush();
1110 		adapter->tx_hang_recheck = true;
1111 		return;
1112 	}
1113 	adapter->tx_hang_recheck = false;
1114 
1115 	if (er32(TDH(0)) == er32(TDT(0))) {
1116 		e_dbg("false hang detected, ignoring\n");
1117 		return;
1118 	}
1119 
1120 	/* Real hang detected */
1121 	netif_stop_queue(netdev);
1122 
1123 	e1e_rphy(hw, MII_BMSR, &phy_status);
1124 	e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1125 	e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1126 
1127 	pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1128 
1129 	/* detected Hardware unit hang */
1130 	e_err("Detected Hardware Unit Hang:\n"
1131 	      "  TDH                  <%x>\n"
1132 	      "  TDT                  <%x>\n"
1133 	      "  next_to_use          <%x>\n"
1134 	      "  next_to_clean        <%x>\n"
1135 	      "buffer_info[next_to_clean]:\n"
1136 	      "  time_stamp           <%lx>\n"
1137 	      "  next_to_watch        <%x>\n"
1138 	      "  jiffies              <%lx>\n"
1139 	      "  next_to_watch.status <%x>\n"
1140 	      "MAC Status             <%x>\n"
1141 	      "PHY Status             <%x>\n"
1142 	      "PHY 1000BASE-T Status  <%x>\n"
1143 	      "PHY Extended Status    <%x>\n"
1144 	      "PCI Status             <%x>\n",
1145 	      readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1146 	      tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1147 	      eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1148 	      phy_status, phy_1000t_status, phy_ext_status, pci_status);
1149 
1150 	e1000e_dump(adapter);
1151 
1152 	/* Suggest workaround for known h/w issue */
1153 	if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1154 		e_err("Try turning off Tx pause (flow control) via ethtool\n");
1155 }
1156 
1157 /**
1158  * e1000e_tx_hwtstamp_work - check for Tx time stamp
1159  * @work: pointer to work struct
1160  *
1161  * This work function polls the TSYNCTXCTL valid bit to determine when a
1162  * timestamp has been taken for the current stored skb.  The timestamp must
1163  * be for this skb because only one such packet is allowed in the queue.
1164  */
1165 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1166 {
1167 	struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1168 						     tx_hwtstamp_work);
1169 	struct e1000_hw *hw = &adapter->hw;
1170 
1171 	if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1172 		struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1173 		struct skb_shared_hwtstamps shhwtstamps;
1174 		u64 txstmp;
1175 
1176 		txstmp = er32(TXSTMPL);
1177 		txstmp |= (u64)er32(TXSTMPH) << 32;
1178 
1179 		e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1180 
1181 		/* Clear the global tx_hwtstamp_skb pointer and force writes
1182 		 * prior to notifying the stack of a Tx timestamp.
1183 		 */
1184 		adapter->tx_hwtstamp_skb = NULL;
1185 		wmb(); /* force write prior to skb_tstamp_tx */
1186 
1187 		skb_tstamp_tx(skb, &shhwtstamps);
1188 		dev_consume_skb_any(skb);
1189 	} else if (time_after(jiffies, adapter->tx_hwtstamp_start
1190 			      + adapter->tx_timeout_factor * HZ)) {
1191 		dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1192 		adapter->tx_hwtstamp_skb = NULL;
1193 		adapter->tx_hwtstamp_timeouts++;
1194 		e_warn("clearing Tx timestamp hang\n");
1195 	} else {
1196 		/* reschedule to check later */
1197 		schedule_work(&adapter->tx_hwtstamp_work);
1198 	}
1199 }
1200 
1201 /**
1202  * e1000_clean_tx_irq - Reclaim resources after transmit completes
1203  * @tx_ring: Tx descriptor ring
1204  *
1205  * the return value indicates whether actual cleaning was done, there
1206  * is no guarantee that everything was cleaned
1207  **/
1208 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1209 {
1210 	struct e1000_adapter *adapter = tx_ring->adapter;
1211 	struct net_device *netdev = adapter->netdev;
1212 	struct e1000_hw *hw = &adapter->hw;
1213 	struct e1000_tx_desc *tx_desc, *eop_desc;
1214 	struct e1000_buffer *buffer_info;
1215 	unsigned int i, eop;
1216 	unsigned int count = 0;
1217 	unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1218 	unsigned int bytes_compl = 0, pkts_compl = 0;
1219 
1220 	i = tx_ring->next_to_clean;
1221 	eop = tx_ring->buffer_info[i].next_to_watch;
1222 	eop_desc = E1000_TX_DESC(*tx_ring, eop);
1223 
1224 	while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1225 	       (count < tx_ring->count)) {
1226 		bool cleaned = false;
1227 
1228 		dma_rmb();		/* read buffer_info after eop_desc */
1229 		for (; !cleaned; count++) {
1230 			tx_desc = E1000_TX_DESC(*tx_ring, i);
1231 			buffer_info = &tx_ring->buffer_info[i];
1232 			cleaned = (i == eop);
1233 
1234 			if (cleaned) {
1235 				total_tx_packets += buffer_info->segs;
1236 				total_tx_bytes += buffer_info->bytecount;
1237 				if (buffer_info->skb) {
1238 					bytes_compl += buffer_info->skb->len;
1239 					pkts_compl++;
1240 				}
1241 			}
1242 
1243 			e1000_put_txbuf(tx_ring, buffer_info, false);
1244 			tx_desc->upper.data = 0;
1245 
1246 			i++;
1247 			if (i == tx_ring->count)
1248 				i = 0;
1249 		}
1250 
1251 		if (i == tx_ring->next_to_use)
1252 			break;
1253 		eop = tx_ring->buffer_info[i].next_to_watch;
1254 		eop_desc = E1000_TX_DESC(*tx_ring, eop);
1255 	}
1256 
1257 	tx_ring->next_to_clean = i;
1258 
1259 	netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1260 
1261 #define TX_WAKE_THRESHOLD 32
1262 	if (count && netif_carrier_ok(netdev) &&
1263 	    e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1264 		/* Make sure that anybody stopping the queue after this
1265 		 * sees the new next_to_clean.
1266 		 */
1267 		smp_mb();
1268 
1269 		if (netif_queue_stopped(netdev) &&
1270 		    !(test_bit(__E1000_DOWN, &adapter->state))) {
1271 			netif_wake_queue(netdev);
1272 			++adapter->restart_queue;
1273 		}
1274 	}
1275 
1276 	if (adapter->detect_tx_hung) {
1277 		/* Detect a transmit hang in hardware, this serializes the
1278 		 * check with the clearing of time_stamp and movement of i
1279 		 */
1280 		adapter->detect_tx_hung = false;
1281 		if (tx_ring->buffer_info[i].time_stamp &&
1282 		    time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1283 			       + (adapter->tx_timeout_factor * HZ)) &&
1284 		    !(er32(STATUS) & E1000_STATUS_TXOFF))
1285 			schedule_work(&adapter->print_hang_task);
1286 		else
1287 			adapter->tx_hang_recheck = false;
1288 	}
1289 	adapter->total_tx_bytes += total_tx_bytes;
1290 	adapter->total_tx_packets += total_tx_packets;
1291 	return count < tx_ring->count;
1292 }
1293 
1294 /**
1295  * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1296  * @rx_ring: Rx descriptor ring
1297  *
1298  * the return value indicates whether actual cleaning was done, there
1299  * is no guarantee that everything was cleaned
1300  **/
1301 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1302 				  int work_to_do)
1303 {
1304 	struct e1000_adapter *adapter = rx_ring->adapter;
1305 	struct e1000_hw *hw = &adapter->hw;
1306 	union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1307 	struct net_device *netdev = adapter->netdev;
1308 	struct pci_dev *pdev = adapter->pdev;
1309 	struct e1000_buffer *buffer_info, *next_buffer;
1310 	struct e1000_ps_page *ps_page;
1311 	struct sk_buff *skb;
1312 	unsigned int i, j;
1313 	u32 length, staterr;
1314 	int cleaned_count = 0;
1315 	bool cleaned = false;
1316 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1317 
1318 	i = rx_ring->next_to_clean;
1319 	rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1320 	staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1321 	buffer_info = &rx_ring->buffer_info[i];
1322 
1323 	while (staterr & E1000_RXD_STAT_DD) {
1324 		if (*work_done >= work_to_do)
1325 			break;
1326 		(*work_done)++;
1327 		skb = buffer_info->skb;
1328 		dma_rmb();	/* read descriptor and rx_buffer_info after status DD */
1329 
1330 		/* in the packet split case this is header only */
1331 		prefetch(skb->data - NET_IP_ALIGN);
1332 
1333 		i++;
1334 		if (i == rx_ring->count)
1335 			i = 0;
1336 		next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1337 		prefetch(next_rxd);
1338 
1339 		next_buffer = &rx_ring->buffer_info[i];
1340 
1341 		cleaned = true;
1342 		cleaned_count++;
1343 		dma_unmap_single(&pdev->dev, buffer_info->dma,
1344 				 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1345 		buffer_info->dma = 0;
1346 
1347 		/* see !EOP comment in other Rx routine */
1348 		if (!(staterr & E1000_RXD_STAT_EOP))
1349 			adapter->flags2 |= FLAG2_IS_DISCARDING;
1350 
1351 		if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1352 			e_dbg("Packet Split buffers didn't pick up the full packet\n");
1353 			dev_kfree_skb_irq(skb);
1354 			if (staterr & E1000_RXD_STAT_EOP)
1355 				adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1356 			goto next_desc;
1357 		}
1358 
1359 		if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1360 			     !(netdev->features & NETIF_F_RXALL))) {
1361 			dev_kfree_skb_irq(skb);
1362 			goto next_desc;
1363 		}
1364 
1365 		length = le16_to_cpu(rx_desc->wb.middle.length0);
1366 
1367 		if (!length) {
1368 			e_dbg("Last part of the packet spanning multiple descriptors\n");
1369 			dev_kfree_skb_irq(skb);
1370 			goto next_desc;
1371 		}
1372 
1373 		/* Good Receive */
1374 		skb_put(skb, length);
1375 
1376 		{
1377 			/* this looks ugly, but it seems compiler issues make
1378 			 * it more efficient than reusing j
1379 			 */
1380 			int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1381 
1382 			/* page alloc/put takes too long and effects small
1383 			 * packet throughput, so unsplit small packets and
1384 			 * save the alloc/put only valid in softirq (napi)
1385 			 * context to call kmap_*
1386 			 */
1387 			if (l1 && (l1 <= copybreak) &&
1388 			    ((length + l1) <= adapter->rx_ps_bsize0)) {
1389 				u8 *vaddr;
1390 
1391 				ps_page = &buffer_info->ps_pages[0];
1392 
1393 				/* there is no documentation about how to call
1394 				 * kmap_atomic, so we can't hold the mapping
1395 				 * very long
1396 				 */
1397 				dma_sync_single_for_cpu(&pdev->dev,
1398 							ps_page->dma,
1399 							PAGE_SIZE,
1400 							DMA_FROM_DEVICE);
1401 				vaddr = kmap_atomic(ps_page->page);
1402 				memcpy(skb_tail_pointer(skb), vaddr, l1);
1403 				kunmap_atomic(vaddr);
1404 				dma_sync_single_for_device(&pdev->dev,
1405 							   ps_page->dma,
1406 							   PAGE_SIZE,
1407 							   DMA_FROM_DEVICE);
1408 
1409 				/* remove the CRC */
1410 				if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 					if (!(netdev->features & NETIF_F_RXFCS))
1412 						l1 -= 4;
1413 				}
1414 
1415 				skb_put(skb, l1);
1416 				goto copydone;
1417 			}	/* if */
1418 		}
1419 
1420 		for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1421 			length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1422 			if (!length)
1423 				break;
1424 
1425 			ps_page = &buffer_info->ps_pages[j];
1426 			dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1427 				       DMA_FROM_DEVICE);
1428 			ps_page->dma = 0;
1429 			skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1430 			ps_page->page = NULL;
1431 			skb->len += length;
1432 			skb->data_len += length;
1433 			skb->truesize += PAGE_SIZE;
1434 		}
1435 
1436 		/* strip the ethernet crc, problem is we're using pages now so
1437 		 * this whole operation can get a little cpu intensive
1438 		 */
1439 		if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1440 			if (!(netdev->features & NETIF_F_RXFCS))
1441 				pskb_trim(skb, skb->len - 4);
1442 		}
1443 
1444 copydone:
1445 		total_rx_bytes += skb->len;
1446 		total_rx_packets++;
1447 
1448 		e1000_rx_checksum(adapter, staterr, skb);
1449 
1450 		e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1451 
1452 		if (rx_desc->wb.upper.header_status &
1453 		    cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1454 			adapter->rx_hdr_split++;
1455 
1456 		e1000_receive_skb(adapter, netdev, skb, staterr,
1457 				  rx_desc->wb.middle.vlan);
1458 
1459 next_desc:
1460 		rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1461 		buffer_info->skb = NULL;
1462 
1463 		/* return some buffers to hardware, one at a time is too slow */
1464 		if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1465 			adapter->alloc_rx_buf(rx_ring, cleaned_count,
1466 					      GFP_ATOMIC);
1467 			cleaned_count = 0;
1468 		}
1469 
1470 		/* use prefetched values */
1471 		rx_desc = next_rxd;
1472 		buffer_info = next_buffer;
1473 
1474 		staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1475 	}
1476 	rx_ring->next_to_clean = i;
1477 
1478 	cleaned_count = e1000_desc_unused(rx_ring);
1479 	if (cleaned_count)
1480 		adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1481 
1482 	adapter->total_rx_bytes += total_rx_bytes;
1483 	adapter->total_rx_packets += total_rx_packets;
1484 	return cleaned;
1485 }
1486 
1487 /**
1488  * e1000_consume_page - helper function
1489  **/
1490 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1491 			       u16 length)
1492 {
1493 	bi->page = NULL;
1494 	skb->len += length;
1495 	skb->data_len += length;
1496 	skb->truesize += PAGE_SIZE;
1497 }
1498 
1499 /**
1500  * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1501  * @adapter: board private structure
1502  *
1503  * the return value indicates whether actual cleaning was done, there
1504  * is no guarantee that everything was cleaned
1505  **/
1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 				     int work_to_do)
1508 {
1509 	struct e1000_adapter *adapter = rx_ring->adapter;
1510 	struct net_device *netdev = adapter->netdev;
1511 	struct pci_dev *pdev = adapter->pdev;
1512 	union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 	struct e1000_buffer *buffer_info, *next_buffer;
1514 	u32 length, staterr;
1515 	unsigned int i;
1516 	int cleaned_count = 0;
1517 	bool cleaned = false;
1518 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 	struct skb_shared_info *shinfo;
1520 
1521 	i = rx_ring->next_to_clean;
1522 	rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 	staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 	buffer_info = &rx_ring->buffer_info[i];
1525 
1526 	while (staterr & E1000_RXD_STAT_DD) {
1527 		struct sk_buff *skb;
1528 
1529 		if (*work_done >= work_to_do)
1530 			break;
1531 		(*work_done)++;
1532 		dma_rmb();	/* read descriptor and rx_buffer_info after status DD */
1533 
1534 		skb = buffer_info->skb;
1535 		buffer_info->skb = NULL;
1536 
1537 		++i;
1538 		if (i == rx_ring->count)
1539 			i = 0;
1540 		next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 		prefetch(next_rxd);
1542 
1543 		next_buffer = &rx_ring->buffer_info[i];
1544 
1545 		cleaned = true;
1546 		cleaned_count++;
1547 		dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 			       DMA_FROM_DEVICE);
1549 		buffer_info->dma = 0;
1550 
1551 		length = le16_to_cpu(rx_desc->wb.upper.length);
1552 
1553 		/* errors is only valid for DD + EOP descriptors */
1554 		if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 			     ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 			      !(netdev->features & NETIF_F_RXALL)))) {
1557 			/* recycle both page and skb */
1558 			buffer_info->skb = skb;
1559 			/* an error means any chain goes out the window too */
1560 			if (rx_ring->rx_skb_top)
1561 				dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 			rx_ring->rx_skb_top = NULL;
1563 			goto next_desc;
1564 		}
1565 #define rxtop (rx_ring->rx_skb_top)
1566 		if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 			/* this descriptor is only the beginning (or middle) */
1568 			if (!rxtop) {
1569 				/* this is the beginning of a chain */
1570 				rxtop = skb;
1571 				skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 						   0, length);
1573 			} else {
1574 				/* this is the middle of a chain */
1575 				shinfo = skb_shinfo(rxtop);
1576 				skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 						   buffer_info->page, 0,
1578 						   length);
1579 				/* re-use the skb, only consumed the page */
1580 				buffer_info->skb = skb;
1581 			}
1582 			e1000_consume_page(buffer_info, rxtop, length);
1583 			goto next_desc;
1584 		} else {
1585 			if (rxtop) {
1586 				/* end of the chain */
1587 				shinfo = skb_shinfo(rxtop);
1588 				skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 						   buffer_info->page, 0,
1590 						   length);
1591 				/* re-use the current skb, we only consumed the
1592 				 * page
1593 				 */
1594 				buffer_info->skb = skb;
1595 				skb = rxtop;
1596 				rxtop = NULL;
1597 				e1000_consume_page(buffer_info, skb, length);
1598 			} else {
1599 				/* no chain, got EOP, this buf is the packet
1600 				 * copybreak to save the put_page/alloc_page
1601 				 */
1602 				if (length <= copybreak &&
1603 				    skb_tailroom(skb) >= length) {
1604 					u8 *vaddr;
1605 					vaddr = kmap_atomic(buffer_info->page);
1606 					memcpy(skb_tail_pointer(skb), vaddr,
1607 					       length);
1608 					kunmap_atomic(vaddr);
1609 					/* re-use the page, so don't erase
1610 					 * buffer_info->page
1611 					 */
1612 					skb_put(skb, length);
1613 				} else {
1614 					skb_fill_page_desc(skb, 0,
1615 							   buffer_info->page, 0,
1616 							   length);
1617 					e1000_consume_page(buffer_info, skb,
1618 							   length);
1619 				}
1620 			}
1621 		}
1622 
1623 		/* Receive Checksum Offload */
1624 		e1000_rx_checksum(adapter, staterr, skb);
1625 
1626 		e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1627 
1628 		/* probably a little skewed due to removing CRC */
1629 		total_rx_bytes += skb->len;
1630 		total_rx_packets++;
1631 
1632 		/* eth type trans needs skb->data to point to something */
1633 		if (!pskb_may_pull(skb, ETH_HLEN)) {
1634 			e_err("pskb_may_pull failed.\n");
1635 			dev_kfree_skb_irq(skb);
1636 			goto next_desc;
1637 		}
1638 
1639 		e1000_receive_skb(adapter, netdev, skb, staterr,
1640 				  rx_desc->wb.upper.vlan);
1641 
1642 next_desc:
1643 		rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1644 
1645 		/* return some buffers to hardware, one at a time is too slow */
1646 		if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1647 			adapter->alloc_rx_buf(rx_ring, cleaned_count,
1648 					      GFP_ATOMIC);
1649 			cleaned_count = 0;
1650 		}
1651 
1652 		/* use prefetched values */
1653 		rx_desc = next_rxd;
1654 		buffer_info = next_buffer;
1655 
1656 		staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1657 	}
1658 	rx_ring->next_to_clean = i;
1659 
1660 	cleaned_count = e1000_desc_unused(rx_ring);
1661 	if (cleaned_count)
1662 		adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1663 
1664 	adapter->total_rx_bytes += total_rx_bytes;
1665 	adapter->total_rx_packets += total_rx_packets;
1666 	return cleaned;
1667 }
1668 
1669 /**
1670  * e1000_clean_rx_ring - Free Rx Buffers per Queue
1671  * @rx_ring: Rx descriptor ring
1672  **/
1673 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1674 {
1675 	struct e1000_adapter *adapter = rx_ring->adapter;
1676 	struct e1000_buffer *buffer_info;
1677 	struct e1000_ps_page *ps_page;
1678 	struct pci_dev *pdev = adapter->pdev;
1679 	unsigned int i, j;
1680 
1681 	/* Free all the Rx ring sk_buffs */
1682 	for (i = 0; i < rx_ring->count; i++) {
1683 		buffer_info = &rx_ring->buffer_info[i];
1684 		if (buffer_info->dma) {
1685 			if (adapter->clean_rx == e1000_clean_rx_irq)
1686 				dma_unmap_single(&pdev->dev, buffer_info->dma,
1687 						 adapter->rx_buffer_len,
1688 						 DMA_FROM_DEVICE);
1689 			else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1690 				dma_unmap_page(&pdev->dev, buffer_info->dma,
1691 					       PAGE_SIZE, DMA_FROM_DEVICE);
1692 			else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1693 				dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 						 adapter->rx_ps_bsize0,
1695 						 DMA_FROM_DEVICE);
1696 			buffer_info->dma = 0;
1697 		}
1698 
1699 		if (buffer_info->page) {
1700 			put_page(buffer_info->page);
1701 			buffer_info->page = NULL;
1702 		}
1703 
1704 		if (buffer_info->skb) {
1705 			dev_kfree_skb(buffer_info->skb);
1706 			buffer_info->skb = NULL;
1707 		}
1708 
1709 		for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1710 			ps_page = &buffer_info->ps_pages[j];
1711 			if (!ps_page->page)
1712 				break;
1713 			dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1714 				       DMA_FROM_DEVICE);
1715 			ps_page->dma = 0;
1716 			put_page(ps_page->page);
1717 			ps_page->page = NULL;
1718 		}
1719 	}
1720 
1721 	/* there also may be some cached data from a chained receive */
1722 	if (rx_ring->rx_skb_top) {
1723 		dev_kfree_skb(rx_ring->rx_skb_top);
1724 		rx_ring->rx_skb_top = NULL;
1725 	}
1726 
1727 	/* Zero out the descriptor ring */
1728 	memset(rx_ring->desc, 0, rx_ring->size);
1729 
1730 	rx_ring->next_to_clean = 0;
1731 	rx_ring->next_to_use = 0;
1732 	adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1733 }
1734 
1735 static void e1000e_downshift_workaround(struct work_struct *work)
1736 {
1737 	struct e1000_adapter *adapter = container_of(work,
1738 						     struct e1000_adapter,
1739 						     downshift_task);
1740 
1741 	if (test_bit(__E1000_DOWN, &adapter->state))
1742 		return;
1743 
1744 	e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1745 }
1746 
1747 /**
1748  * e1000_intr_msi - Interrupt Handler
1749  * @irq: interrupt number
1750  * @data: pointer to a network interface device structure
1751  **/
1752 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1753 {
1754 	struct net_device *netdev = data;
1755 	struct e1000_adapter *adapter = netdev_priv(netdev);
1756 	struct e1000_hw *hw = &adapter->hw;
1757 	u32 icr = er32(ICR);
1758 
1759 	/* read ICR disables interrupts using IAM */
1760 	if (icr & E1000_ICR_LSC) {
1761 		hw->mac.get_link_status = true;
1762 		/* ICH8 workaround-- Call gig speed drop workaround on cable
1763 		 * disconnect (LSC) before accessing any PHY registers
1764 		 */
1765 		if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1766 		    (!(er32(STATUS) & E1000_STATUS_LU)))
1767 			schedule_work(&adapter->downshift_task);
1768 
1769 		/* 80003ES2LAN workaround-- For packet buffer work-around on
1770 		 * link down event; disable receives here in the ISR and reset
1771 		 * adapter in watchdog
1772 		 */
1773 		if (netif_carrier_ok(netdev) &&
1774 		    adapter->flags & FLAG_RX_NEEDS_RESTART) {
1775 			/* disable receives */
1776 			u32 rctl = er32(RCTL);
1777 
1778 			ew32(RCTL, rctl & ~E1000_RCTL_EN);
1779 			adapter->flags |= FLAG_RESTART_NOW;
1780 		}
1781 		/* guard against interrupt when we're going down */
1782 		if (!test_bit(__E1000_DOWN, &adapter->state))
1783 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
1784 	}
1785 
1786 	/* Reset on uncorrectable ECC error */
1787 	if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1788 		u32 pbeccsts = er32(PBECCSTS);
1789 
1790 		adapter->corr_errors +=
1791 		    pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1792 		adapter->uncorr_errors +=
1793 		    (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1794 		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1795 
1796 		/* Do the reset outside of interrupt context */
1797 		schedule_work(&adapter->reset_task);
1798 
1799 		/* return immediately since reset is imminent */
1800 		return IRQ_HANDLED;
1801 	}
1802 
1803 	if (napi_schedule_prep(&adapter->napi)) {
1804 		adapter->total_tx_bytes = 0;
1805 		adapter->total_tx_packets = 0;
1806 		adapter->total_rx_bytes = 0;
1807 		adapter->total_rx_packets = 0;
1808 		__napi_schedule(&adapter->napi);
1809 	}
1810 
1811 	return IRQ_HANDLED;
1812 }
1813 
1814 /**
1815  * e1000_intr - Interrupt Handler
1816  * @irq: interrupt number
1817  * @data: pointer to a network interface device structure
1818  **/
1819 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1820 {
1821 	struct net_device *netdev = data;
1822 	struct e1000_adapter *adapter = netdev_priv(netdev);
1823 	struct e1000_hw *hw = &adapter->hw;
1824 	u32 rctl, icr = er32(ICR);
1825 
1826 	if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1827 		return IRQ_NONE;	/* Not our interrupt */
1828 
1829 	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1830 	 * not set, then the adapter didn't send an interrupt
1831 	 */
1832 	if (!(icr & E1000_ICR_INT_ASSERTED))
1833 		return IRQ_NONE;
1834 
1835 	/* Interrupt Auto-Mask...upon reading ICR,
1836 	 * interrupts are masked.  No need for the
1837 	 * IMC write
1838 	 */
1839 
1840 	if (icr & E1000_ICR_LSC) {
1841 		hw->mac.get_link_status = true;
1842 		/* ICH8 workaround-- Call gig speed drop workaround on cable
1843 		 * disconnect (LSC) before accessing any PHY registers
1844 		 */
1845 		if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1846 		    (!(er32(STATUS) & E1000_STATUS_LU)))
1847 			schedule_work(&adapter->downshift_task);
1848 
1849 		/* 80003ES2LAN workaround--
1850 		 * For packet buffer work-around on link down event;
1851 		 * disable receives here in the ISR and
1852 		 * reset adapter in watchdog
1853 		 */
1854 		if (netif_carrier_ok(netdev) &&
1855 		    (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1856 			/* disable receives */
1857 			rctl = er32(RCTL);
1858 			ew32(RCTL, rctl & ~E1000_RCTL_EN);
1859 			adapter->flags |= FLAG_RESTART_NOW;
1860 		}
1861 		/* guard against interrupt when we're going down */
1862 		if (!test_bit(__E1000_DOWN, &adapter->state))
1863 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
1864 	}
1865 
1866 	/* Reset on uncorrectable ECC error */
1867 	if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1868 		u32 pbeccsts = er32(PBECCSTS);
1869 
1870 		adapter->corr_errors +=
1871 		    pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1872 		adapter->uncorr_errors +=
1873 		    (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1874 		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1875 
1876 		/* Do the reset outside of interrupt context */
1877 		schedule_work(&adapter->reset_task);
1878 
1879 		/* return immediately since reset is imminent */
1880 		return IRQ_HANDLED;
1881 	}
1882 
1883 	if (napi_schedule_prep(&adapter->napi)) {
1884 		adapter->total_tx_bytes = 0;
1885 		adapter->total_tx_packets = 0;
1886 		adapter->total_rx_bytes = 0;
1887 		adapter->total_rx_packets = 0;
1888 		__napi_schedule(&adapter->napi);
1889 	}
1890 
1891 	return IRQ_HANDLED;
1892 }
1893 
1894 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1895 {
1896 	struct net_device *netdev = data;
1897 	struct e1000_adapter *adapter = netdev_priv(netdev);
1898 	struct e1000_hw *hw = &adapter->hw;
1899 	u32 icr = er32(ICR);
1900 
1901 	if (icr & adapter->eiac_mask)
1902 		ew32(ICS, (icr & adapter->eiac_mask));
1903 
1904 	if (icr & E1000_ICR_LSC) {
1905 		hw->mac.get_link_status = true;
1906 		/* guard against interrupt when we're going down */
1907 		if (!test_bit(__E1000_DOWN, &adapter->state))
1908 			mod_timer(&adapter->watchdog_timer, jiffies + 1);
1909 	}
1910 
1911 	if (!test_bit(__E1000_DOWN, &adapter->state))
1912 		ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1913 
1914 	return IRQ_HANDLED;
1915 }
1916 
1917 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1918 {
1919 	struct net_device *netdev = data;
1920 	struct e1000_adapter *adapter = netdev_priv(netdev);
1921 	struct e1000_hw *hw = &adapter->hw;
1922 	struct e1000_ring *tx_ring = adapter->tx_ring;
1923 
1924 	adapter->total_tx_bytes = 0;
1925 	adapter->total_tx_packets = 0;
1926 
1927 	if (!e1000_clean_tx_irq(tx_ring))
1928 		/* Ring was not completely cleaned, so fire another interrupt */
1929 		ew32(ICS, tx_ring->ims_val);
1930 
1931 	if (!test_bit(__E1000_DOWN, &adapter->state))
1932 		ew32(IMS, adapter->tx_ring->ims_val);
1933 
1934 	return IRQ_HANDLED;
1935 }
1936 
1937 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1938 {
1939 	struct net_device *netdev = data;
1940 	struct e1000_adapter *adapter = netdev_priv(netdev);
1941 	struct e1000_ring *rx_ring = adapter->rx_ring;
1942 
1943 	/* Write the ITR value calculated at the end of the
1944 	 * previous interrupt.
1945 	 */
1946 	if (rx_ring->set_itr) {
1947 		u32 itr = rx_ring->itr_val ?
1948 			  1000000000 / (rx_ring->itr_val * 256) : 0;
1949 
1950 		writel(itr, rx_ring->itr_register);
1951 		rx_ring->set_itr = 0;
1952 	}
1953 
1954 	if (napi_schedule_prep(&adapter->napi)) {
1955 		adapter->total_rx_bytes = 0;
1956 		adapter->total_rx_packets = 0;
1957 		__napi_schedule(&adapter->napi);
1958 	}
1959 	return IRQ_HANDLED;
1960 }
1961 
1962 /**
1963  * e1000_configure_msix - Configure MSI-X hardware
1964  *
1965  * e1000_configure_msix sets up the hardware to properly
1966  * generate MSI-X interrupts.
1967  **/
1968 static void e1000_configure_msix(struct e1000_adapter *adapter)
1969 {
1970 	struct e1000_hw *hw = &adapter->hw;
1971 	struct e1000_ring *rx_ring = adapter->rx_ring;
1972 	struct e1000_ring *tx_ring = adapter->tx_ring;
1973 	int vector = 0;
1974 	u32 ctrl_ext, ivar = 0;
1975 
1976 	adapter->eiac_mask = 0;
1977 
1978 	/* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1979 	if (hw->mac.type == e1000_82574) {
1980 		u32 rfctl = er32(RFCTL);
1981 
1982 		rfctl |= E1000_RFCTL_ACK_DIS;
1983 		ew32(RFCTL, rfctl);
1984 	}
1985 
1986 	/* Configure Rx vector */
1987 	rx_ring->ims_val = E1000_IMS_RXQ0;
1988 	adapter->eiac_mask |= rx_ring->ims_val;
1989 	if (rx_ring->itr_val)
1990 		writel(1000000000 / (rx_ring->itr_val * 256),
1991 		       rx_ring->itr_register);
1992 	else
1993 		writel(1, rx_ring->itr_register);
1994 	ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1995 
1996 	/* Configure Tx vector */
1997 	tx_ring->ims_val = E1000_IMS_TXQ0;
1998 	vector++;
1999 	if (tx_ring->itr_val)
2000 		writel(1000000000 / (tx_ring->itr_val * 256),
2001 		       tx_ring->itr_register);
2002 	else
2003 		writel(1, tx_ring->itr_register);
2004 	adapter->eiac_mask |= tx_ring->ims_val;
2005 	ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2006 
2007 	/* set vector for Other Causes, e.g. link changes */
2008 	vector++;
2009 	ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2010 	if (rx_ring->itr_val)
2011 		writel(1000000000 / (rx_ring->itr_val * 256),
2012 		       hw->hw_addr + E1000_EITR_82574(vector));
2013 	else
2014 		writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2015 
2016 	/* Cause Tx interrupts on every write back */
2017 	ivar |= BIT(31);
2018 
2019 	ew32(IVAR, ivar);
2020 
2021 	/* enable MSI-X PBA support */
2022 	ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2023 	ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2024 	ew32(CTRL_EXT, ctrl_ext);
2025 	e1e_flush();
2026 }
2027 
2028 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2029 {
2030 	if (adapter->msix_entries) {
2031 		pci_disable_msix(adapter->pdev);
2032 		kfree(adapter->msix_entries);
2033 		adapter->msix_entries = NULL;
2034 	} else if (adapter->flags & FLAG_MSI_ENABLED) {
2035 		pci_disable_msi(adapter->pdev);
2036 		adapter->flags &= ~FLAG_MSI_ENABLED;
2037 	}
2038 }
2039 
2040 /**
2041  * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2042  *
2043  * Attempt to configure interrupts using the best available
2044  * capabilities of the hardware and kernel.
2045  **/
2046 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2047 {
2048 	int err;
2049 	int i;
2050 
2051 	switch (adapter->int_mode) {
2052 	case E1000E_INT_MODE_MSIX:
2053 		if (adapter->flags & FLAG_HAS_MSIX) {
2054 			adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2055 			adapter->msix_entries = kcalloc(adapter->num_vectors,
2056 							sizeof(struct
2057 							       msix_entry),
2058 							GFP_KERNEL);
2059 			if (adapter->msix_entries) {
2060 				struct e1000_adapter *a = adapter;
2061 
2062 				for (i = 0; i < adapter->num_vectors; i++)
2063 					adapter->msix_entries[i].entry = i;
2064 
2065 				err = pci_enable_msix_range(a->pdev,
2066 							    a->msix_entries,
2067 							    a->num_vectors,
2068 							    a->num_vectors);
2069 				if (err > 0)
2070 					return;
2071 			}
2072 			/* MSI-X failed, so fall through and try MSI */
2073 			e_err("Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts.\n");
2074 			e1000e_reset_interrupt_capability(adapter);
2075 		}
2076 		adapter->int_mode = E1000E_INT_MODE_MSI;
2077 		/* Fall through */
2078 	case E1000E_INT_MODE_MSI:
2079 		if (!pci_enable_msi(adapter->pdev)) {
2080 			adapter->flags |= FLAG_MSI_ENABLED;
2081 		} else {
2082 			adapter->int_mode = E1000E_INT_MODE_LEGACY;
2083 			e_err("Failed to initialize MSI interrupts.  Falling back to legacy interrupts.\n");
2084 		}
2085 		/* Fall through */
2086 	case E1000E_INT_MODE_LEGACY:
2087 		/* Don't do anything; this is the system default */
2088 		break;
2089 	}
2090 
2091 	/* store the number of vectors being used */
2092 	adapter->num_vectors = 1;
2093 }
2094 
2095 /**
2096  * e1000_request_msix - Initialize MSI-X interrupts
2097  *
2098  * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2099  * kernel.
2100  **/
2101 static int e1000_request_msix(struct e1000_adapter *adapter)
2102 {
2103 	struct net_device *netdev = adapter->netdev;
2104 	int err = 0, vector = 0;
2105 
2106 	if (strlen(netdev->name) < (IFNAMSIZ - 5))
2107 		snprintf(adapter->rx_ring->name,
2108 			 sizeof(adapter->rx_ring->name) - 1,
2109 			 "%.14s-rx-0", netdev->name);
2110 	else
2111 		memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2112 	err = request_irq(adapter->msix_entries[vector].vector,
2113 			  e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2114 			  netdev);
2115 	if (err)
2116 		return err;
2117 	adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2118 	    E1000_EITR_82574(vector);
2119 	adapter->rx_ring->itr_val = adapter->itr;
2120 	vector++;
2121 
2122 	if (strlen(netdev->name) < (IFNAMSIZ - 5))
2123 		snprintf(adapter->tx_ring->name,
2124 			 sizeof(adapter->tx_ring->name) - 1,
2125 			 "%.14s-tx-0", netdev->name);
2126 	else
2127 		memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2128 	err = request_irq(adapter->msix_entries[vector].vector,
2129 			  e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2130 			  netdev);
2131 	if (err)
2132 		return err;
2133 	adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2134 	    E1000_EITR_82574(vector);
2135 	adapter->tx_ring->itr_val = adapter->itr;
2136 	vector++;
2137 
2138 	err = request_irq(adapter->msix_entries[vector].vector,
2139 			  e1000_msix_other, 0, netdev->name, netdev);
2140 	if (err)
2141 		return err;
2142 
2143 	e1000_configure_msix(adapter);
2144 
2145 	return 0;
2146 }
2147 
2148 /**
2149  * e1000_request_irq - initialize interrupts
2150  *
2151  * Attempts to configure interrupts using the best available
2152  * capabilities of the hardware and kernel.
2153  **/
2154 static int e1000_request_irq(struct e1000_adapter *adapter)
2155 {
2156 	struct net_device *netdev = adapter->netdev;
2157 	int err;
2158 
2159 	if (adapter->msix_entries) {
2160 		err = e1000_request_msix(adapter);
2161 		if (!err)
2162 			return err;
2163 		/* fall back to MSI */
2164 		e1000e_reset_interrupt_capability(adapter);
2165 		adapter->int_mode = E1000E_INT_MODE_MSI;
2166 		e1000e_set_interrupt_capability(adapter);
2167 	}
2168 	if (adapter->flags & FLAG_MSI_ENABLED) {
2169 		err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 				  netdev->name, netdev);
2171 		if (!err)
2172 			return err;
2173 
2174 		/* fall back to legacy interrupt */
2175 		e1000e_reset_interrupt_capability(adapter);
2176 		adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 	}
2178 
2179 	err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 			  netdev->name, netdev);
2181 	if (err)
2182 		e_err("Unable to allocate interrupt, Error: %d\n", err);
2183 
2184 	return err;
2185 }
2186 
2187 static void e1000_free_irq(struct e1000_adapter *adapter)
2188 {
2189 	struct net_device *netdev = adapter->netdev;
2190 
2191 	if (adapter->msix_entries) {
2192 		int vector = 0;
2193 
2194 		free_irq(adapter->msix_entries[vector].vector, netdev);
2195 		vector++;
2196 
2197 		free_irq(adapter->msix_entries[vector].vector, netdev);
2198 		vector++;
2199 
2200 		/* Other Causes interrupt vector */
2201 		free_irq(adapter->msix_entries[vector].vector, netdev);
2202 		return;
2203 	}
2204 
2205 	free_irq(adapter->pdev->irq, netdev);
2206 }
2207 
2208 /**
2209  * e1000_irq_disable - Mask off interrupt generation on the NIC
2210  **/
2211 static void e1000_irq_disable(struct e1000_adapter *adapter)
2212 {
2213 	struct e1000_hw *hw = &adapter->hw;
2214 
2215 	ew32(IMC, ~0);
2216 	if (adapter->msix_entries)
2217 		ew32(EIAC_82574, 0);
2218 	e1e_flush();
2219 
2220 	if (adapter->msix_entries) {
2221 		int i;
2222 
2223 		for (i = 0; i < adapter->num_vectors; i++)
2224 			synchronize_irq(adapter->msix_entries[i].vector);
2225 	} else {
2226 		synchronize_irq(adapter->pdev->irq);
2227 	}
2228 }
2229 
2230 /**
2231  * e1000_irq_enable - Enable default interrupt generation settings
2232  **/
2233 static void e1000_irq_enable(struct e1000_adapter *adapter)
2234 {
2235 	struct e1000_hw *hw = &adapter->hw;
2236 
2237 	if (adapter->msix_entries) {
2238 		ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2239 		ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2240 		     IMS_OTHER_MASK);
2241 	} else if (hw->mac.type >= e1000_pch_lpt) {
2242 		ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2243 	} else {
2244 		ew32(IMS, IMS_ENABLE_MASK);
2245 	}
2246 	e1e_flush();
2247 }
2248 
2249 /**
2250  * e1000e_get_hw_control - get control of the h/w from f/w
2251  * @adapter: address of board private structure
2252  *
2253  * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2254  * For ASF and Pass Through versions of f/w this means that
2255  * the driver is loaded. For AMT version (only with 82573)
2256  * of the f/w this means that the network i/f is open.
2257  **/
2258 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2259 {
2260 	struct e1000_hw *hw = &adapter->hw;
2261 	u32 ctrl_ext;
2262 	u32 swsm;
2263 
2264 	/* Let firmware know the driver has taken over */
2265 	if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2266 		swsm = er32(SWSM);
2267 		ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2268 	} else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2269 		ctrl_ext = er32(CTRL_EXT);
2270 		ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2271 	}
2272 }
2273 
2274 /**
2275  * e1000e_release_hw_control - release control of the h/w to f/w
2276  * @adapter: address of board private structure
2277  *
2278  * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2279  * For ASF and Pass Through versions of f/w this means that the
2280  * driver is no longer loaded. For AMT version (only with 82573) i
2281  * of the f/w this means that the network i/f is closed.
2282  *
2283  **/
2284 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2285 {
2286 	struct e1000_hw *hw = &adapter->hw;
2287 	u32 ctrl_ext;
2288 	u32 swsm;
2289 
2290 	/* Let firmware taken over control of h/w */
2291 	if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2292 		swsm = er32(SWSM);
2293 		ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2294 	} else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2295 		ctrl_ext = er32(CTRL_EXT);
2296 		ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2297 	}
2298 }
2299 
2300 /**
2301  * e1000_alloc_ring_dma - allocate memory for a ring structure
2302  **/
2303 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2304 				struct e1000_ring *ring)
2305 {
2306 	struct pci_dev *pdev = adapter->pdev;
2307 
2308 	ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2309 					GFP_KERNEL);
2310 	if (!ring->desc)
2311 		return -ENOMEM;
2312 
2313 	return 0;
2314 }
2315 
2316 /**
2317  * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2318  * @tx_ring: Tx descriptor ring
2319  *
2320  * Return 0 on success, negative on failure
2321  **/
2322 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2323 {
2324 	struct e1000_adapter *adapter = tx_ring->adapter;
2325 	int err = -ENOMEM, size;
2326 
2327 	size = sizeof(struct e1000_buffer) * tx_ring->count;
2328 	tx_ring->buffer_info = vzalloc(size);
2329 	if (!tx_ring->buffer_info)
2330 		goto err;
2331 
2332 	/* round up to nearest 4K */
2333 	tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2334 	tx_ring->size = ALIGN(tx_ring->size, 4096);
2335 
2336 	err = e1000_alloc_ring_dma(adapter, tx_ring);
2337 	if (err)
2338 		goto err;
2339 
2340 	tx_ring->next_to_use = 0;
2341 	tx_ring->next_to_clean = 0;
2342 
2343 	return 0;
2344 err:
2345 	vfree(tx_ring->buffer_info);
2346 	e_err("Unable to allocate memory for the transmit descriptor ring\n");
2347 	return err;
2348 }
2349 
2350 /**
2351  * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2352  * @rx_ring: Rx descriptor ring
2353  *
2354  * Returns 0 on success, negative on failure
2355  **/
2356 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2357 {
2358 	struct e1000_adapter *adapter = rx_ring->adapter;
2359 	struct e1000_buffer *buffer_info;
2360 	int i, size, desc_len, err = -ENOMEM;
2361 
2362 	size = sizeof(struct e1000_buffer) * rx_ring->count;
2363 	rx_ring->buffer_info = vzalloc(size);
2364 	if (!rx_ring->buffer_info)
2365 		goto err;
2366 
2367 	for (i = 0; i < rx_ring->count; i++) {
2368 		buffer_info = &rx_ring->buffer_info[i];
2369 		buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2370 						sizeof(struct e1000_ps_page),
2371 						GFP_KERNEL);
2372 		if (!buffer_info->ps_pages)
2373 			goto err_pages;
2374 	}
2375 
2376 	desc_len = sizeof(union e1000_rx_desc_packet_split);
2377 
2378 	/* Round up to nearest 4K */
2379 	rx_ring->size = rx_ring->count * desc_len;
2380 	rx_ring->size = ALIGN(rx_ring->size, 4096);
2381 
2382 	err = e1000_alloc_ring_dma(adapter, rx_ring);
2383 	if (err)
2384 		goto err_pages;
2385 
2386 	rx_ring->next_to_clean = 0;
2387 	rx_ring->next_to_use = 0;
2388 	rx_ring->rx_skb_top = NULL;
2389 
2390 	return 0;
2391 
2392 err_pages:
2393 	for (i = 0; i < rx_ring->count; i++) {
2394 		buffer_info = &rx_ring->buffer_info[i];
2395 		kfree(buffer_info->ps_pages);
2396 	}
2397 err:
2398 	vfree(rx_ring->buffer_info);
2399 	e_err("Unable to allocate memory for the receive descriptor ring\n");
2400 	return err;
2401 }
2402 
2403 /**
2404  * e1000_clean_tx_ring - Free Tx Buffers
2405  * @tx_ring: Tx descriptor ring
2406  **/
2407 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2408 {
2409 	struct e1000_adapter *adapter = tx_ring->adapter;
2410 	struct e1000_buffer *buffer_info;
2411 	unsigned long size;
2412 	unsigned int i;
2413 
2414 	for (i = 0; i < tx_ring->count; i++) {
2415 		buffer_info = &tx_ring->buffer_info[i];
2416 		e1000_put_txbuf(tx_ring, buffer_info, false);
2417 	}
2418 
2419 	netdev_reset_queue(adapter->netdev);
2420 	size = sizeof(struct e1000_buffer) * tx_ring->count;
2421 	memset(tx_ring->buffer_info, 0, size);
2422 
2423 	memset(tx_ring->desc, 0, tx_ring->size);
2424 
2425 	tx_ring->next_to_use = 0;
2426 	tx_ring->next_to_clean = 0;
2427 }
2428 
2429 /**
2430  * e1000e_free_tx_resources - Free Tx Resources per Queue
2431  * @tx_ring: Tx descriptor ring
2432  *
2433  * Free all transmit software resources
2434  **/
2435 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2436 {
2437 	struct e1000_adapter *adapter = tx_ring->adapter;
2438 	struct pci_dev *pdev = adapter->pdev;
2439 
2440 	e1000_clean_tx_ring(tx_ring);
2441 
2442 	vfree(tx_ring->buffer_info);
2443 	tx_ring->buffer_info = NULL;
2444 
2445 	dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2446 			  tx_ring->dma);
2447 	tx_ring->desc = NULL;
2448 }
2449 
2450 /**
2451  * e1000e_free_rx_resources - Free Rx Resources
2452  * @rx_ring: Rx descriptor ring
2453  *
2454  * Free all receive software resources
2455  **/
2456 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2457 {
2458 	struct e1000_adapter *adapter = rx_ring->adapter;
2459 	struct pci_dev *pdev = adapter->pdev;
2460 	int i;
2461 
2462 	e1000_clean_rx_ring(rx_ring);
2463 
2464 	for (i = 0; i < rx_ring->count; i++)
2465 		kfree(rx_ring->buffer_info[i].ps_pages);
2466 
2467 	vfree(rx_ring->buffer_info);
2468 	rx_ring->buffer_info = NULL;
2469 
2470 	dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2471 			  rx_ring->dma);
2472 	rx_ring->desc = NULL;
2473 }
2474 
2475 /**
2476  * e1000_update_itr - update the dynamic ITR value based on statistics
2477  * @adapter: pointer to adapter
2478  * @itr_setting: current adapter->itr
2479  * @packets: the number of packets during this measurement interval
2480  * @bytes: the number of bytes during this measurement interval
2481  *
2482  *      Stores a new ITR value based on packets and byte
2483  *      counts during the last interrupt.  The advantage of per interrupt
2484  *      computation is faster updates and more accurate ITR for the current
2485  *      traffic pattern.  Constants in this function were computed
2486  *      based on theoretical maximum wire speed and thresholds were set based
2487  *      on testing data as well as attempting to minimize response time
2488  *      while increasing bulk throughput.  This functionality is controlled
2489  *      by the InterruptThrottleRate module parameter.
2490  **/
2491 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2492 {
2493 	unsigned int retval = itr_setting;
2494 
2495 	if (packets == 0)
2496 		return itr_setting;
2497 
2498 	switch (itr_setting) {
2499 	case lowest_latency:
2500 		/* handle TSO and jumbo frames */
2501 		if (bytes / packets > 8000)
2502 			retval = bulk_latency;
2503 		else if ((packets < 5) && (bytes > 512))
2504 			retval = low_latency;
2505 		break;
2506 	case low_latency:	/* 50 usec aka 20000 ints/s */
2507 		if (bytes > 10000) {
2508 			/* this if handles the TSO accounting */
2509 			if (bytes / packets > 8000)
2510 				retval = bulk_latency;
2511 			else if ((packets < 10) || ((bytes / packets) > 1200))
2512 				retval = bulk_latency;
2513 			else if ((packets > 35))
2514 				retval = lowest_latency;
2515 		} else if (bytes / packets > 2000) {
2516 			retval = bulk_latency;
2517 		} else if (packets <= 2 && bytes < 512) {
2518 			retval = lowest_latency;
2519 		}
2520 		break;
2521 	case bulk_latency:	/* 250 usec aka 4000 ints/s */
2522 		if (bytes > 25000) {
2523 			if (packets > 35)
2524 				retval = low_latency;
2525 		} else if (bytes < 6000) {
2526 			retval = low_latency;
2527 		}
2528 		break;
2529 	}
2530 
2531 	return retval;
2532 }
2533 
2534 static void e1000_set_itr(struct e1000_adapter *adapter)
2535 {
2536 	u16 current_itr;
2537 	u32 new_itr = adapter->itr;
2538 
2539 	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2540 	if (adapter->link_speed != SPEED_1000) {
2541 		current_itr = 0;
2542 		new_itr = 4000;
2543 		goto set_itr_now;
2544 	}
2545 
2546 	if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2547 		new_itr = 0;
2548 		goto set_itr_now;
2549 	}
2550 
2551 	adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2552 					   adapter->total_tx_packets,
2553 					   adapter->total_tx_bytes);
2554 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
2555 	if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2556 		adapter->tx_itr = low_latency;
2557 
2558 	adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2559 					   adapter->total_rx_packets,
2560 					   adapter->total_rx_bytes);
2561 	/* conservative mode (itr 3) eliminates the lowest_latency setting */
2562 	if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2563 		adapter->rx_itr = low_latency;
2564 
2565 	current_itr = max(adapter->rx_itr, adapter->tx_itr);
2566 
2567 	/* counts and packets in update_itr are dependent on these numbers */
2568 	switch (current_itr) {
2569 	case lowest_latency:
2570 		new_itr = 70000;
2571 		break;
2572 	case low_latency:
2573 		new_itr = 20000;	/* aka hwitr = ~200 */
2574 		break;
2575 	case bulk_latency:
2576 		new_itr = 4000;
2577 		break;
2578 	default:
2579 		break;
2580 	}
2581 
2582 set_itr_now:
2583 	if (new_itr != adapter->itr) {
2584 		/* this attempts to bias the interrupt rate towards Bulk
2585 		 * by adding intermediate steps when interrupt rate is
2586 		 * increasing
2587 		 */
2588 		new_itr = new_itr > adapter->itr ?
2589 		    min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2590 		adapter->itr = new_itr;
2591 		adapter->rx_ring->itr_val = new_itr;
2592 		if (adapter->msix_entries)
2593 			adapter->rx_ring->set_itr = 1;
2594 		else
2595 			e1000e_write_itr(adapter, new_itr);
2596 	}
2597 }
2598 
2599 /**
2600  * e1000e_write_itr - write the ITR value to the appropriate registers
2601  * @adapter: address of board private structure
2602  * @itr: new ITR value to program
2603  *
2604  * e1000e_write_itr determines if the adapter is in MSI-X mode
2605  * and, if so, writes the EITR registers with the ITR value.
2606  * Otherwise, it writes the ITR value into the ITR register.
2607  **/
2608 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2609 {
2610 	struct e1000_hw *hw = &adapter->hw;
2611 	u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2612 
2613 	if (adapter->msix_entries) {
2614 		int vector;
2615 
2616 		for (vector = 0; vector < adapter->num_vectors; vector++)
2617 			writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2618 	} else {
2619 		ew32(ITR, new_itr);
2620 	}
2621 }
2622 
2623 /**
2624  * e1000_alloc_queues - Allocate memory for all rings
2625  * @adapter: board private structure to initialize
2626  **/
2627 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2628 {
2629 	int size = sizeof(struct e1000_ring);
2630 
2631 	adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2632 	if (!adapter->tx_ring)
2633 		goto err;
2634 	adapter->tx_ring->count = adapter->tx_ring_count;
2635 	adapter->tx_ring->adapter = adapter;
2636 
2637 	adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2638 	if (!adapter->rx_ring)
2639 		goto err;
2640 	adapter->rx_ring->count = adapter->rx_ring_count;
2641 	adapter->rx_ring->adapter = adapter;
2642 
2643 	return 0;
2644 err:
2645 	e_err("Unable to allocate memory for queues\n");
2646 	kfree(adapter->rx_ring);
2647 	kfree(adapter->tx_ring);
2648 	return -ENOMEM;
2649 }
2650 
2651 /**
2652  * e1000e_poll - NAPI Rx polling callback
2653  * @napi: struct associated with this polling callback
2654  * @budget: number of packets driver is allowed to process this poll
2655  **/
2656 static int e1000e_poll(struct napi_struct *napi, int budget)
2657 {
2658 	struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2659 						     napi);
2660 	struct e1000_hw *hw = &adapter->hw;
2661 	struct net_device *poll_dev = adapter->netdev;
2662 	int tx_cleaned = 1, work_done = 0;
2663 
2664 	adapter = netdev_priv(poll_dev);
2665 
2666 	if (!adapter->msix_entries ||
2667 	    (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2668 		tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2669 
2670 	adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2671 
2672 	if (!tx_cleaned || work_done == budget)
2673 		return budget;
2674 
2675 	/* Exit the polling mode, but don't re-enable interrupts if stack might
2676 	 * poll us due to busy-polling
2677 	 */
2678 	if (likely(napi_complete_done(napi, work_done))) {
2679 		if (adapter->itr_setting & 3)
2680 			e1000_set_itr(adapter);
2681 		if (!test_bit(__E1000_DOWN, &adapter->state)) {
2682 			if (adapter->msix_entries)
2683 				ew32(IMS, adapter->rx_ring->ims_val);
2684 			else
2685 				e1000_irq_enable(adapter);
2686 		}
2687 	}
2688 
2689 	return work_done;
2690 }
2691 
2692 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2693 				 __always_unused __be16 proto, u16 vid)
2694 {
2695 	struct e1000_adapter *adapter = netdev_priv(netdev);
2696 	struct e1000_hw *hw = &adapter->hw;
2697 	u32 vfta, index;
2698 
2699 	/* don't update vlan cookie if already programmed */
2700 	if ((adapter->hw.mng_cookie.status &
2701 	     E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2702 	    (vid == adapter->mng_vlan_id))
2703 		return 0;
2704 
2705 	/* add VID to filter table */
2706 	if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2707 		index = (vid >> 5) & 0x7F;
2708 		vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2709 		vfta |= BIT((vid & 0x1F));
2710 		hw->mac.ops.write_vfta(hw, index, vfta);
2711 	}
2712 
2713 	set_bit(vid, adapter->active_vlans);
2714 
2715 	return 0;
2716 }
2717 
2718 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2719 				  __always_unused __be16 proto, u16 vid)
2720 {
2721 	struct e1000_adapter *adapter = netdev_priv(netdev);
2722 	struct e1000_hw *hw = &adapter->hw;
2723 	u32 vfta, index;
2724 
2725 	if ((adapter->hw.mng_cookie.status &
2726 	     E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2727 	    (vid == adapter->mng_vlan_id)) {
2728 		/* release control to f/w */
2729 		e1000e_release_hw_control(adapter);
2730 		return 0;
2731 	}
2732 
2733 	/* remove VID from filter table */
2734 	if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2735 		index = (vid >> 5) & 0x7F;
2736 		vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2737 		vfta &= ~BIT((vid & 0x1F));
2738 		hw->mac.ops.write_vfta(hw, index, vfta);
2739 	}
2740 
2741 	clear_bit(vid, adapter->active_vlans);
2742 
2743 	return 0;
2744 }
2745 
2746 /**
2747  * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2748  * @adapter: board private structure to initialize
2749  **/
2750 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2751 {
2752 	struct net_device *netdev = adapter->netdev;
2753 	struct e1000_hw *hw = &adapter->hw;
2754 	u32 rctl;
2755 
2756 	if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2757 		/* disable VLAN receive filtering */
2758 		rctl = er32(RCTL);
2759 		rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2760 		ew32(RCTL, rctl);
2761 
2762 		if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2763 			e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2764 					       adapter->mng_vlan_id);
2765 			adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2766 		}
2767 	}
2768 }
2769 
2770 /**
2771  * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2772  * @adapter: board private structure to initialize
2773  **/
2774 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2775 {
2776 	struct e1000_hw *hw = &adapter->hw;
2777 	u32 rctl;
2778 
2779 	if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2780 		/* enable VLAN receive filtering */
2781 		rctl = er32(RCTL);
2782 		rctl |= E1000_RCTL_VFE;
2783 		rctl &= ~E1000_RCTL_CFIEN;
2784 		ew32(RCTL, rctl);
2785 	}
2786 }
2787 
2788 /**
2789  * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2790  * @adapter: board private structure to initialize
2791  **/
2792 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2793 {
2794 	struct e1000_hw *hw = &adapter->hw;
2795 	u32 ctrl;
2796 
2797 	/* disable VLAN tag insert/strip */
2798 	ctrl = er32(CTRL);
2799 	ctrl &= ~E1000_CTRL_VME;
2800 	ew32(CTRL, ctrl);
2801 }
2802 
2803 /**
2804  * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2805  * @adapter: board private structure to initialize
2806  **/
2807 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2808 {
2809 	struct e1000_hw *hw = &adapter->hw;
2810 	u32 ctrl;
2811 
2812 	/* enable VLAN tag insert/strip */
2813 	ctrl = er32(CTRL);
2814 	ctrl |= E1000_CTRL_VME;
2815 	ew32(CTRL, ctrl);
2816 }
2817 
2818 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2819 {
2820 	struct net_device *netdev = adapter->netdev;
2821 	u16 vid = adapter->hw.mng_cookie.vlan_id;
2822 	u16 old_vid = adapter->mng_vlan_id;
2823 
2824 	if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2825 		e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2826 		adapter->mng_vlan_id = vid;
2827 	}
2828 
2829 	if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2830 		e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2831 }
2832 
2833 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2834 {
2835 	u16 vid;
2836 
2837 	e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2838 
2839 	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2840 	    e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2841 }
2842 
2843 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2844 {
2845 	struct e1000_hw *hw = &adapter->hw;
2846 	u32 manc, manc2h, mdef, i, j;
2847 
2848 	if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2849 		return;
2850 
2851 	manc = er32(MANC);
2852 
2853 	/* enable receiving management packets to the host. this will probably
2854 	 * generate destination unreachable messages from the host OS, but
2855 	 * the packets will be handled on SMBUS
2856 	 */
2857 	manc |= E1000_MANC_EN_MNG2HOST;
2858 	manc2h = er32(MANC2H);
2859 
2860 	switch (hw->mac.type) {
2861 	default:
2862 		manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2863 		break;
2864 	case e1000_82574:
2865 	case e1000_82583:
2866 		/* Check if IPMI pass-through decision filter already exists;
2867 		 * if so, enable it.
2868 		 */
2869 		for (i = 0, j = 0; i < 8; i++) {
2870 			mdef = er32(MDEF(i));
2871 
2872 			/* Ignore filters with anything other than IPMI ports */
2873 			if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2874 				continue;
2875 
2876 			/* Enable this decision filter in MANC2H */
2877 			if (mdef)
2878 				manc2h |= BIT(i);
2879 
2880 			j |= mdef;
2881 		}
2882 
2883 		if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2884 			break;
2885 
2886 		/* Create new decision filter in an empty filter */
2887 		for (i = 0, j = 0; i < 8; i++)
2888 			if (er32(MDEF(i)) == 0) {
2889 				ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2890 					       E1000_MDEF_PORT_664));
2891 				manc2h |= BIT(1);
2892 				j++;
2893 				break;
2894 			}
2895 
2896 		if (!j)
2897 			e_warn("Unable to create IPMI pass-through filter\n");
2898 		break;
2899 	}
2900 
2901 	ew32(MANC2H, manc2h);
2902 	ew32(MANC, manc);
2903 }
2904 
2905 /**
2906  * e1000_configure_tx - Configure Transmit Unit after Reset
2907  * @adapter: board private structure
2908  *
2909  * Configure the Tx unit of the MAC after a reset.
2910  **/
2911 static void e1000_configure_tx(struct e1000_adapter *adapter)
2912 {
2913 	struct e1000_hw *hw = &adapter->hw;
2914 	struct e1000_ring *tx_ring = adapter->tx_ring;
2915 	u64 tdba;
2916 	u32 tdlen, tctl, tarc;
2917 
2918 	/* Setup the HW Tx Head and Tail descriptor pointers */
2919 	tdba = tx_ring->dma;
2920 	tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2921 	ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2922 	ew32(TDBAH(0), (tdba >> 32));
2923 	ew32(TDLEN(0), tdlen);
2924 	ew32(TDH(0), 0);
2925 	ew32(TDT(0), 0);
2926 	tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2927 	tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2928 
2929 	writel(0, tx_ring->head);
2930 	if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2931 		e1000e_update_tdt_wa(tx_ring, 0);
2932 	else
2933 		writel(0, tx_ring->tail);
2934 
2935 	/* Set the Tx Interrupt Delay register */
2936 	ew32(TIDV, adapter->tx_int_delay);
2937 	/* Tx irq moderation */
2938 	ew32(TADV, adapter->tx_abs_int_delay);
2939 
2940 	if (adapter->flags2 & FLAG2_DMA_BURST) {
2941 		u32 txdctl = er32(TXDCTL(0));
2942 
2943 		txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2944 			    E1000_TXDCTL_WTHRESH);
2945 		/* set up some performance related parameters to encourage the
2946 		 * hardware to use the bus more efficiently in bursts, depends
2947 		 * on the tx_int_delay to be enabled,
2948 		 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2949 		 * hthresh = 1 ==> prefetch when one or more available
2950 		 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2951 		 * BEWARE: this seems to work but should be considered first if
2952 		 * there are Tx hangs or other Tx related bugs
2953 		 */
2954 		txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2955 		ew32(TXDCTL(0), txdctl);
2956 	}
2957 	/* erratum work around: set txdctl the same for both queues */
2958 	ew32(TXDCTL(1), er32(TXDCTL(0)));
2959 
2960 	/* Program the Transmit Control Register */
2961 	tctl = er32(TCTL);
2962 	tctl &= ~E1000_TCTL_CT;
2963 	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2964 		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2965 
2966 	if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2967 		tarc = er32(TARC(0));
2968 		/* set the speed mode bit, we'll clear it if we're not at
2969 		 * gigabit link later
2970 		 */
2971 #define SPEED_MODE_BIT BIT(21)
2972 		tarc |= SPEED_MODE_BIT;
2973 		ew32(TARC(0), tarc);
2974 	}
2975 
2976 	/* errata: program both queues to unweighted RR */
2977 	if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2978 		tarc = er32(TARC(0));
2979 		tarc |= 1;
2980 		ew32(TARC(0), tarc);
2981 		tarc = er32(TARC(1));
2982 		tarc |= 1;
2983 		ew32(TARC(1), tarc);
2984 	}
2985 
2986 	/* Setup Transmit Descriptor Settings for eop descriptor */
2987 	adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2988 
2989 	/* only set IDE if we are delaying interrupts using the timers */
2990 	if (adapter->tx_int_delay)
2991 		adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2992 
2993 	/* enable Report Status bit */
2994 	adapter->txd_cmd |= E1000_TXD_CMD_RS;
2995 
2996 	ew32(TCTL, tctl);
2997 
2998 	hw->mac.ops.config_collision_dist(hw);
2999 
3000 	/* SPT and KBL Si errata workaround to avoid data corruption */
3001 	if (hw->mac.type == e1000_pch_spt) {
3002 		u32 reg_val;
3003 
3004 		reg_val = er32(IOSFPC);
3005 		reg_val |= E1000_RCTL_RDMTS_HEX;
3006 		ew32(IOSFPC, reg_val);
3007 
3008 		reg_val = er32(TARC(0));
3009 		/* SPT and KBL Si errata workaround to avoid Tx hang.
3010 		 * Dropping the number of outstanding requests from
3011 		 * 3 to 2 in order to avoid a buffer overrun.
3012 		 */
3013 		reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3014 		reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3015 		ew32(TARC(0), reg_val);
3016 	}
3017 }
3018 
3019 /**
3020  * e1000_setup_rctl - configure the receive control registers
3021  * @adapter: Board private structure
3022  **/
3023 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3024 			   (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3025 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026 {
3027 	struct e1000_hw *hw = &adapter->hw;
3028 	u32 rctl, rfctl;
3029 	u32 pages = 0;
3030 
3031 	/* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 	 * If jumbo frames not set, program related MAC/PHY registers
3033 	 * to h/w defaults
3034 	 */
3035 	if (hw->mac.type >= e1000_pch2lan) {
3036 		s32 ret_val;
3037 
3038 		if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 			ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 		else
3041 			ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042 
3043 		if (ret_val)
3044 			e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 	}
3046 
3047 	/* Program MC offset vector base */
3048 	rctl = er32(RCTL);
3049 	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3051 	    E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 	    (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053 
3054 	/* Do not Store bad packets */
3055 	rctl &= ~E1000_RCTL_SBP;
3056 
3057 	/* Enable Long Packet receive */
3058 	if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 		rctl &= ~E1000_RCTL_LPE;
3060 	else
3061 		rctl |= E1000_RCTL_LPE;
3062 
3063 	/* Some systems expect that the CRC is included in SMBUS traffic. The
3064 	 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 	 * host memory when this is enabled
3066 	 */
3067 	if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 		rctl |= E1000_RCTL_SECRC;
3069 
3070 	/* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3071 	if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 		u16 phy_data;
3073 
3074 		e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 		phy_data &= 0xfff8;
3076 		phy_data |= BIT(2);
3077 		e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078 
3079 		e1e_rphy(hw, 22, &phy_data);
3080 		phy_data &= 0x0fff;
3081 		phy_data |= BIT(14);
3082 		e1e_wphy(hw, 0x10, 0x2823);
3083 		e1e_wphy(hw, 0x11, 0x0003);
3084 		e1e_wphy(hw, 22, phy_data);
3085 	}
3086 
3087 	/* Setup buffer sizes */
3088 	rctl &= ~E1000_RCTL_SZ_4096;
3089 	rctl |= E1000_RCTL_BSEX;
3090 	switch (adapter->rx_buffer_len) {
3091 	case 2048:
3092 	default:
3093 		rctl |= E1000_RCTL_SZ_2048;
3094 		rctl &= ~E1000_RCTL_BSEX;
3095 		break;
3096 	case 4096:
3097 		rctl |= E1000_RCTL_SZ_4096;
3098 		break;
3099 	case 8192:
3100 		rctl |= E1000_RCTL_SZ_8192;
3101 		break;
3102 	case 16384:
3103 		rctl |= E1000_RCTL_SZ_16384;
3104 		break;
3105 	}
3106 
3107 	/* Enable Extended Status in all Receive Descriptors */
3108 	rfctl = er32(RFCTL);
3109 	rfctl |= E1000_RFCTL_EXTEN;
3110 	ew32(RFCTL, rfctl);
3111 
3112 	/* 82571 and greater support packet-split where the protocol
3113 	 * header is placed in skb->data and the packet data is
3114 	 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 	 * In the case of a non-split, skb->data is linearly filled,
3116 	 * followed by the page buffers.  Therefore, skb->data is
3117 	 * sized to hold the largest protocol header.
3118 	 *
3119 	 * allocations using alloc_page take too long for regular MTU
3120 	 * so only enable packet split for jumbo frames
3121 	 *
3122 	 * Using pages when the page size is greater than 16k wastes
3123 	 * a lot of memory, since we allocate 3 pages at all times
3124 	 * per packet.
3125 	 */
3126 	pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3127 	if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3128 		adapter->rx_ps_pages = pages;
3129 	else
3130 		adapter->rx_ps_pages = 0;
3131 
3132 	if (adapter->rx_ps_pages) {
3133 		u32 psrctl = 0;
3134 
3135 		/* Enable Packet split descriptors */
3136 		rctl |= E1000_RCTL_DTYP_PS;
3137 
3138 		psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3139 
3140 		switch (adapter->rx_ps_pages) {
3141 		case 3:
3142 			psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3143 			/* fall-through */
3144 		case 2:
3145 			psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3146 			/* fall-through */
3147 		case 1:
3148 			psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3149 			break;
3150 		}
3151 
3152 		ew32(PSRCTL, psrctl);
3153 	}
3154 
3155 	/* This is useful for sniffing bad packets. */
3156 	if (adapter->netdev->features & NETIF_F_RXALL) {
3157 		/* UPE and MPE will be handled by normal PROMISC logic
3158 		 * in e1000e_set_rx_mode
3159 		 */
3160 		rctl |= (E1000_RCTL_SBP |	/* Receive bad packets */
3161 			 E1000_RCTL_BAM |	/* RX All Bcast Pkts */
3162 			 E1000_RCTL_PMCF);	/* RX All MAC Ctrl Pkts */
3163 
3164 		rctl &= ~(E1000_RCTL_VFE |	/* Disable VLAN filter */
3165 			  E1000_RCTL_DPF |	/* Allow filtered pause */
3166 			  E1000_RCTL_CFIEN);	/* Dis VLAN CFIEN Filter */
3167 		/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 		 * and that breaks VLANs.
3169 		 */
3170 	}
3171 
3172 	ew32(RCTL, rctl);
3173 	/* just started the receive unit, no need to restart */
3174 	adapter->flags &= ~FLAG_RESTART_NOW;
3175 }
3176 
3177 /**
3178  * e1000_configure_rx - Configure Receive Unit after Reset
3179  * @adapter: board private structure
3180  *
3181  * Configure the Rx unit of the MAC after a reset.
3182  **/
3183 static void e1000_configure_rx(struct e1000_adapter *adapter)
3184 {
3185 	struct e1000_hw *hw = &adapter->hw;
3186 	struct e1000_ring *rx_ring = adapter->rx_ring;
3187 	u64 rdba;
3188 	u32 rdlen, rctl, rxcsum, ctrl_ext;
3189 
3190 	if (adapter->rx_ps_pages) {
3191 		/* this is a 32 byte descriptor */
3192 		rdlen = rx_ring->count *
3193 		    sizeof(union e1000_rx_desc_packet_split);
3194 		adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 		adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3196 	} else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3197 		rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3198 		adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 		adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3200 	} else {
3201 		rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3202 		adapter->clean_rx = e1000_clean_rx_irq;
3203 		adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 	}
3205 
3206 	/* disable receives while setting up the descriptors */
3207 	rctl = er32(RCTL);
3208 	if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 		ew32(RCTL, rctl & ~E1000_RCTL_EN);
3210 	e1e_flush();
3211 	usleep_range(10000, 20000);
3212 
3213 	if (adapter->flags2 & FLAG2_DMA_BURST) {
3214 		/* set the writeback threshold (only takes effect if the RDTR
3215 		 * is set). set GRAN=1 and write back up to 0x4 worth, and
3216 		 * enable prefetching of 0x20 Rx descriptors
3217 		 * granularity = 01
3218 		 * wthresh = 04,
3219 		 * hthresh = 04,
3220 		 * pthresh = 0x20
3221 		 */
3222 		ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 		ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3224 	}
3225 
3226 	/* set the Receive Delay Timer Register */
3227 	ew32(RDTR, adapter->rx_int_delay);
3228 
3229 	/* irq moderation */
3230 	ew32(RADV, adapter->rx_abs_int_delay);
3231 	if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3232 		e1000e_write_itr(adapter, adapter->itr);
3233 
3234 	ctrl_ext = er32(CTRL_EXT);
3235 	/* Auto-Mask interrupts upon ICR access */
3236 	ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 	ew32(IAM, 0xffffffff);
3238 	ew32(CTRL_EXT, ctrl_ext);
3239 	e1e_flush();
3240 
3241 	/* Setup the HW Rx Head and Tail Descriptor Pointers and
3242 	 * the Base and Length of the Rx Descriptor Ring
3243 	 */
3244 	rdba = rx_ring->dma;
3245 	ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 	ew32(RDBAH(0), (rdba >> 32));
3247 	ew32(RDLEN(0), rdlen);
3248 	ew32(RDH(0), 0);
3249 	ew32(RDT(0), 0);
3250 	rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 	rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3252 
3253 	writel(0, rx_ring->head);
3254 	if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3255 		e1000e_update_rdt_wa(rx_ring, 0);
3256 	else
3257 		writel(0, rx_ring->tail);
3258 
3259 	/* Enable Receive Checksum Offload for TCP and UDP */
3260 	rxcsum = er32(RXCSUM);
3261 	if (adapter->netdev->features & NETIF_F_RXCSUM)
3262 		rxcsum |= E1000_RXCSUM_TUOFL;
3263 	else
3264 		rxcsum &= ~E1000_RXCSUM_TUOFL;
3265 	ew32(RXCSUM, rxcsum);
3266 
3267 	/* With jumbo frames, excessive C-state transition latencies result
3268 	 * in dropped transactions.
3269 	 */
3270 	if (adapter->netdev->mtu > ETH_DATA_LEN) {
3271 		u32 lat =
3272 		    ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3273 		     adapter->max_frame_size) * 8 / 1000;
3274 
3275 		if (adapter->flags & FLAG_IS_ICH) {
3276 			u32 rxdctl = er32(RXDCTL(0));
3277 
3278 			ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3279 		}
3280 
3281 		dev_info(&adapter->pdev->dev,
3282 			 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3283 		pm_qos_update_request(&adapter->pm_qos_req, lat);
3284 	} else {
3285 		pm_qos_update_request(&adapter->pm_qos_req,
3286 				      PM_QOS_DEFAULT_VALUE);
3287 	}
3288 
3289 	/* Enable Receives */
3290 	ew32(RCTL, rctl);
3291 }
3292 
3293 /**
3294  * e1000e_write_mc_addr_list - write multicast addresses to MTA
3295  * @netdev: network interface device structure
3296  *
3297  * Writes multicast address list to the MTA hash table.
3298  * Returns: -ENOMEM on failure
3299  *                0 on no addresses written
3300  *                X on writing X addresses to MTA
3301  */
3302 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3303 {
3304 	struct e1000_adapter *adapter = netdev_priv(netdev);
3305 	struct e1000_hw *hw = &adapter->hw;
3306 	struct netdev_hw_addr *ha;
3307 	u8 *mta_list;
3308 	int i;
3309 
3310 	if (netdev_mc_empty(netdev)) {
3311 		/* nothing to program, so clear mc list */
3312 		hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3313 		return 0;
3314 	}
3315 
3316 	mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3317 	if (!mta_list)
3318 		return -ENOMEM;
3319 
3320 	/* update_mc_addr_list expects a packed array of only addresses. */
3321 	i = 0;
3322 	netdev_for_each_mc_addr(ha, netdev)
3323 	    memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3324 
3325 	hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3326 	kfree(mta_list);
3327 
3328 	return netdev_mc_count(netdev);
3329 }
3330 
3331 /**
3332  * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3333  * @netdev: network interface device structure
3334  *
3335  * Writes unicast address list to the RAR table.
3336  * Returns: -ENOMEM on failure/insufficient address space
3337  *                0 on no addresses written
3338  *                X on writing X addresses to the RAR table
3339  **/
3340 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3341 {
3342 	struct e1000_adapter *adapter = netdev_priv(netdev);
3343 	struct e1000_hw *hw = &adapter->hw;
3344 	unsigned int rar_entries;
3345 	int count = 0;
3346 
3347 	rar_entries = hw->mac.ops.rar_get_count(hw);
3348 
3349 	/* save a rar entry for our hardware address */
3350 	rar_entries--;
3351 
3352 	/* save a rar entry for the LAA workaround */
3353 	if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3354 		rar_entries--;
3355 
3356 	/* return ENOMEM indicating insufficient memory for addresses */
3357 	if (netdev_uc_count(netdev) > rar_entries)
3358 		return -ENOMEM;
3359 
3360 	if (!netdev_uc_empty(netdev) && rar_entries) {
3361 		struct netdev_hw_addr *ha;
3362 
3363 		/* write the addresses in reverse order to avoid write
3364 		 * combining
3365 		 */
3366 		netdev_for_each_uc_addr(ha, netdev) {
3367 			int ret_val;
3368 
3369 			if (!rar_entries)
3370 				break;
3371 			ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3372 			if (ret_val < 0)
3373 				return -ENOMEM;
3374 			count++;
3375 		}
3376 	}
3377 
3378 	/* zero out the remaining RAR entries not used above */
3379 	for (; rar_entries > 0; rar_entries--) {
3380 		ew32(RAH(rar_entries), 0);
3381 		ew32(RAL(rar_entries), 0);
3382 	}
3383 	e1e_flush();
3384 
3385 	return count;
3386 }
3387 
3388 /**
3389  * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3390  * @netdev: network interface device structure
3391  *
3392  * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3393  * address list or the network interface flags are updated.  This routine is
3394  * responsible for configuring the hardware for proper unicast, multicast,
3395  * promiscuous mode, and all-multi behavior.
3396  **/
3397 static void e1000e_set_rx_mode(struct net_device *netdev)
3398 {
3399 	struct e1000_adapter *adapter = netdev_priv(netdev);
3400 	struct e1000_hw *hw = &adapter->hw;
3401 	u32 rctl;
3402 
3403 	if (pm_runtime_suspended(netdev->dev.parent))
3404 		return;
3405 
3406 	/* Check for Promiscuous and All Multicast modes */
3407 	rctl = er32(RCTL);
3408 
3409 	/* clear the affected bits */
3410 	rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3411 
3412 	if (netdev->flags & IFF_PROMISC) {
3413 		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3414 		/* Do not hardware filter VLANs in promisc mode */
3415 		e1000e_vlan_filter_disable(adapter);
3416 	} else {
3417 		int count;
3418 
3419 		if (netdev->flags & IFF_ALLMULTI) {
3420 			rctl |= E1000_RCTL_MPE;
3421 		} else {
3422 			/* Write addresses to the MTA, if the attempt fails
3423 			 * then we should just turn on promiscuous mode so
3424 			 * that we can at least receive multicast traffic
3425 			 */
3426 			count = e1000e_write_mc_addr_list(netdev);
3427 			if (count < 0)
3428 				rctl |= E1000_RCTL_MPE;
3429 		}
3430 		e1000e_vlan_filter_enable(adapter);
3431 		/* Write addresses to available RAR registers, if there is not
3432 		 * sufficient space to store all the addresses then enable
3433 		 * unicast promiscuous mode
3434 		 */
3435 		count = e1000e_write_uc_addr_list(netdev);
3436 		if (count < 0)
3437 			rctl |= E1000_RCTL_UPE;
3438 	}
3439 
3440 	ew32(RCTL, rctl);
3441 
3442 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3443 		e1000e_vlan_strip_enable(adapter);
3444 	else
3445 		e1000e_vlan_strip_disable(adapter);
3446 }
3447 
3448 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3449 {
3450 	struct e1000_hw *hw = &adapter->hw;
3451 	u32 mrqc, rxcsum;
3452 	u32 rss_key[10];
3453 	int i;
3454 
3455 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
3456 	for (i = 0; i < 10; i++)
3457 		ew32(RSSRK(i), rss_key[i]);
3458 
3459 	/* Direct all traffic to queue 0 */
3460 	for (i = 0; i < 32; i++)
3461 		ew32(RETA(i), 0);
3462 
3463 	/* Disable raw packet checksumming so that RSS hash is placed in
3464 	 * descriptor on writeback.
3465 	 */
3466 	rxcsum = er32(RXCSUM);
3467 	rxcsum |= E1000_RXCSUM_PCSD;
3468 
3469 	ew32(RXCSUM, rxcsum);
3470 
3471 	mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3472 		E1000_MRQC_RSS_FIELD_IPV4_TCP |
3473 		E1000_MRQC_RSS_FIELD_IPV6 |
3474 		E1000_MRQC_RSS_FIELD_IPV6_TCP |
3475 		E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3476 
3477 	ew32(MRQC, mrqc);
3478 }
3479 
3480 /**
3481  * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3482  * @adapter: board private structure
3483  * @timinca: pointer to returned time increment attributes
3484  *
3485  * Get attributes for incrementing the System Time Register SYSTIML/H at
3486  * the default base frequency, and set the cyclecounter shift value.
3487  **/
3488 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3489 {
3490 	struct e1000_hw *hw = &adapter->hw;
3491 	u32 incvalue, incperiod, shift;
3492 
3493 	/* Make sure clock is enabled on I217/I218/I219  before checking
3494 	 * the frequency
3495 	 */
3496 	if ((hw->mac.type >= e1000_pch_lpt) &&
3497 	    !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3498 	    !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3499 		u32 fextnvm7 = er32(FEXTNVM7);
3500 
3501 		if (!(fextnvm7 & BIT(0))) {
3502 			ew32(FEXTNVM7, fextnvm7 | BIT(0));
3503 			e1e_flush();
3504 		}
3505 	}
3506 
3507 	switch (hw->mac.type) {
3508 	case e1000_pch2lan:
3509 		/* Stable 96MHz frequency */
3510 		incperiod = INCPERIOD_96MHZ;
3511 		incvalue = INCVALUE_96MHZ;
3512 		shift = INCVALUE_SHIFT_96MHZ;
3513 		adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3514 		break;
3515 	case e1000_pch_lpt:
3516 		if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3517 			/* Stable 96MHz frequency */
3518 			incperiod = INCPERIOD_96MHZ;
3519 			incvalue = INCVALUE_96MHZ;
3520 			shift = INCVALUE_SHIFT_96MHZ;
3521 			adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3522 		} else {
3523 			/* Stable 25MHz frequency */
3524 			incperiod = INCPERIOD_25MHZ;
3525 			incvalue = INCVALUE_25MHZ;
3526 			shift = INCVALUE_SHIFT_25MHZ;
3527 			adapter->cc.shift = shift;
3528 		}
3529 		break;
3530 	case e1000_pch_spt:
3531 		/* Stable 24MHz frequency */
3532 		incperiod = INCPERIOD_24MHZ;
3533 		incvalue = INCVALUE_24MHZ;
3534 		shift = INCVALUE_SHIFT_24MHZ;
3535 		adapter->cc.shift = shift;
3536 		break;
3537 	case e1000_pch_cnp:
3538 		if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3539 			/* Stable 24MHz frequency */
3540 			incperiod = INCPERIOD_24MHZ;
3541 			incvalue = INCVALUE_24MHZ;
3542 			shift = INCVALUE_SHIFT_24MHZ;
3543 			adapter->cc.shift = shift;
3544 		} else {
3545 			/* Stable 38400KHz frequency */
3546 			incperiod = INCPERIOD_38400KHZ;
3547 			incvalue = INCVALUE_38400KHZ;
3548 			shift = INCVALUE_SHIFT_38400KHZ;
3549 			adapter->cc.shift = shift;
3550 		}
3551 		break;
3552 	case e1000_82574:
3553 	case e1000_82583:
3554 		/* Stable 25MHz frequency */
3555 		incperiod = INCPERIOD_25MHZ;
3556 		incvalue = INCVALUE_25MHZ;
3557 		shift = INCVALUE_SHIFT_25MHZ;
3558 		adapter->cc.shift = shift;
3559 		break;
3560 	default:
3561 		return -EINVAL;
3562 	}
3563 
3564 	*timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3565 		    ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3566 
3567 	return 0;
3568 }
3569 
3570 /**
3571  * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3572  * @adapter: board private structure
3573  *
3574  * Outgoing time stamping can be enabled and disabled. Play nice and
3575  * disable it when requested, although it shouldn't cause any overhead
3576  * when no packet needs it. At most one packet in the queue may be
3577  * marked for time stamping, otherwise it would be impossible to tell
3578  * for sure to which packet the hardware time stamp belongs.
3579  *
3580  * Incoming time stamping has to be configured via the hardware filters.
3581  * Not all combinations are supported, in particular event type has to be
3582  * specified. Matching the kind of event packet is not supported, with the
3583  * exception of "all V2 events regardless of level 2 or 4".
3584  **/
3585 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3586 				  struct hwtstamp_config *config)
3587 {
3588 	struct e1000_hw *hw = &adapter->hw;
3589 	u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3590 	u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3591 	u32 rxmtrl = 0;
3592 	u16 rxudp = 0;
3593 	bool is_l4 = false;
3594 	bool is_l2 = false;
3595 	u32 regval;
3596 
3597 	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3598 		return -EINVAL;
3599 
3600 	/* flags reserved for future extensions - must be zero */
3601 	if (config->flags)
3602 		return -EINVAL;
3603 
3604 	switch (config->tx_type) {
3605 	case HWTSTAMP_TX_OFF:
3606 		tsync_tx_ctl = 0;
3607 		break;
3608 	case HWTSTAMP_TX_ON:
3609 		break;
3610 	default:
3611 		return -ERANGE;
3612 	}
3613 
3614 	switch (config->rx_filter) {
3615 	case HWTSTAMP_FILTER_NONE:
3616 		tsync_rx_ctl = 0;
3617 		break;
3618 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3619 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3620 		rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3621 		is_l4 = true;
3622 		break;
3623 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3624 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3625 		rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3626 		is_l4 = true;
3627 		break;
3628 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3629 		/* Also time stamps V2 L2 Path Delay Request/Response */
3630 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3631 		rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3632 		is_l2 = true;
3633 		break;
3634 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3635 		/* Also time stamps V2 L2 Path Delay Request/Response. */
3636 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3637 		rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3638 		is_l2 = true;
3639 		break;
3640 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3641 		/* Hardware cannot filter just V2 L4 Sync messages;
3642 		 * fall-through to V2 (both L2 and L4) Sync.
3643 		 */
3644 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
3645 		/* Also time stamps V2 Path Delay Request/Response. */
3646 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3647 		rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3648 		is_l2 = true;
3649 		is_l4 = true;
3650 		break;
3651 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3652 		/* Hardware cannot filter just V2 L4 Delay Request messages;
3653 		 * fall-through to V2 (both L2 and L4) Delay Request.
3654 		 */
3655 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3656 		/* Also time stamps V2 Path Delay Request/Response. */
3657 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3658 		rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3659 		is_l2 = true;
3660 		is_l4 = true;
3661 		break;
3662 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3663 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3664 		/* Hardware cannot filter just V2 L4 or L2 Event messages;
3665 		 * fall-through to all V2 (both L2 and L4) Events.
3666 		 */
3667 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
3668 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3669 		config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3670 		is_l2 = true;
3671 		is_l4 = true;
3672 		break;
3673 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3674 		/* For V1, the hardware can only filter Sync messages or
3675 		 * Delay Request messages but not both so fall-through to
3676 		 * time stamp all packets.
3677 		 */
3678 	case HWTSTAMP_FILTER_NTP_ALL:
3679 	case HWTSTAMP_FILTER_ALL:
3680 		is_l2 = true;
3681 		is_l4 = true;
3682 		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3683 		config->rx_filter = HWTSTAMP_FILTER_ALL;
3684 		break;
3685 	default:
3686 		return -ERANGE;
3687 	}
3688 
3689 	adapter->hwtstamp_config = *config;
3690 
3691 	/* enable/disable Tx h/w time stamping */
3692 	regval = er32(TSYNCTXCTL);
3693 	regval &= ~E1000_TSYNCTXCTL_ENABLED;
3694 	regval |= tsync_tx_ctl;
3695 	ew32(TSYNCTXCTL, regval);
3696 	if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3697 	    (regval & E1000_TSYNCTXCTL_ENABLED)) {
3698 		e_err("Timesync Tx Control register not set as expected\n");
3699 		return -EAGAIN;
3700 	}
3701 
3702 	/* enable/disable Rx h/w time stamping */
3703 	regval = er32(TSYNCRXCTL);
3704 	regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3705 	regval |= tsync_rx_ctl;
3706 	ew32(TSYNCRXCTL, regval);
3707 	if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3708 				 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3709 	    (regval & (E1000_TSYNCRXCTL_ENABLED |
3710 		       E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 		e_err("Timesync Rx Control register not set as expected\n");
3712 		return -EAGAIN;
3713 	}
3714 
3715 	/* L2: define ethertype filter for time stamped packets */
3716 	if (is_l2)
3717 		rxmtrl |= ETH_P_1588;
3718 
3719 	/* define which PTP packets get time stamped */
3720 	ew32(RXMTRL, rxmtrl);
3721 
3722 	/* Filter by destination port */
3723 	if (is_l4) {
3724 		rxudp = PTP_EV_PORT;
3725 		cpu_to_be16s(&rxudp);
3726 	}
3727 	ew32(RXUDP, rxudp);
3728 
3729 	e1e_flush();
3730 
3731 	/* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3732 	er32(RXSTMPH);
3733 	er32(TXSTMPH);
3734 
3735 	return 0;
3736 }
3737 
3738 /**
3739  * e1000_configure - configure the hardware for Rx and Tx
3740  * @adapter: private board structure
3741  **/
3742 static void e1000_configure(struct e1000_adapter *adapter)
3743 {
3744 	struct e1000_ring *rx_ring = adapter->rx_ring;
3745 
3746 	e1000e_set_rx_mode(adapter->netdev);
3747 
3748 	e1000_restore_vlan(adapter);
3749 	e1000_init_manageability_pt(adapter);
3750 
3751 	e1000_configure_tx(adapter);
3752 
3753 	if (adapter->netdev->features & NETIF_F_RXHASH)
3754 		e1000e_setup_rss_hash(adapter);
3755 	e1000_setup_rctl(adapter);
3756 	e1000_configure_rx(adapter);
3757 	adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3758 }
3759 
3760 /**
3761  * e1000e_power_up_phy - restore link in case the phy was powered down
3762  * @adapter: address of board private structure
3763  *
3764  * The phy may be powered down to save power and turn off link when the
3765  * driver is unloaded and wake on lan is not enabled (among others)
3766  * *** this routine MUST be followed by a call to e1000e_reset ***
3767  **/
3768 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3769 {
3770 	if (adapter->hw.phy.ops.power_up)
3771 		adapter->hw.phy.ops.power_up(&adapter->hw);
3772 
3773 	adapter->hw.mac.ops.setup_link(&adapter->hw);
3774 }
3775 
3776 /**
3777  * e1000_power_down_phy - Power down the PHY
3778  *
3779  * Power down the PHY so no link is implied when interface is down.
3780  * The PHY cannot be powered down if management or WoL is active.
3781  */
3782 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3783 {
3784 	if (adapter->hw.phy.ops.power_down)
3785 		adapter->hw.phy.ops.power_down(&adapter->hw);
3786 }
3787 
3788 /**
3789  * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3790  *
3791  * We want to clear all pending descriptors from the TX ring.
3792  * zeroing happens when the HW reads the regs. We  assign the ring itself as
3793  * the data of the next descriptor. We don't care about the data we are about
3794  * to reset the HW.
3795  */
3796 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3797 {
3798 	struct e1000_hw *hw = &adapter->hw;
3799 	struct e1000_ring *tx_ring = adapter->tx_ring;
3800 	struct e1000_tx_desc *tx_desc = NULL;
3801 	u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3802 	u16 size = 512;
3803 
3804 	tctl = er32(TCTL);
3805 	ew32(TCTL, tctl | E1000_TCTL_EN);
3806 	tdt = er32(TDT(0));
3807 	BUG_ON(tdt != tx_ring->next_to_use);
3808 	tx_desc =  E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3809 	tx_desc->buffer_addr = tx_ring->dma;
3810 
3811 	tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3812 	tx_desc->upper.data = 0;
3813 	/* flush descriptors to memory before notifying the HW */
3814 	wmb();
3815 	tx_ring->next_to_use++;
3816 	if (tx_ring->next_to_use == tx_ring->count)
3817 		tx_ring->next_to_use = 0;
3818 	ew32(TDT(0), tx_ring->next_to_use);
3819 	usleep_range(200, 250);
3820 }
3821 
3822 /**
3823  * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3824  *
3825  * Mark all descriptors in the RX ring as consumed and disable the rx ring
3826  */
3827 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3828 {
3829 	u32 rctl, rxdctl;
3830 	struct e1000_hw *hw = &adapter->hw;
3831 
3832 	rctl = er32(RCTL);
3833 	ew32(RCTL, rctl & ~E1000_RCTL_EN);
3834 	e1e_flush();
3835 	usleep_range(100, 150);
3836 
3837 	rxdctl = er32(RXDCTL(0));
3838 	/* zero the lower 14 bits (prefetch and host thresholds) */
3839 	rxdctl &= 0xffffc000;
3840 
3841 	/* update thresholds: prefetch threshold to 31, host threshold to 1
3842 	 * and make sure the granularity is "descriptors" and not "cache lines"
3843 	 */
3844 	rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3845 
3846 	ew32(RXDCTL(0), rxdctl);
3847 	/* momentarily enable the RX ring for the changes to take effect */
3848 	ew32(RCTL, rctl | E1000_RCTL_EN);
3849 	e1e_flush();
3850 	usleep_range(100, 150);
3851 	ew32(RCTL, rctl & ~E1000_RCTL_EN);
3852 }
3853 
3854 /**
3855  * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3856  *
3857  * In i219, the descriptor rings must be emptied before resetting the HW
3858  * or before changing the device state to D3 during runtime (runtime PM).
3859  *
3860  * Failure to do this will cause the HW to enter a unit hang state which can
3861  * only be released by PCI reset on the device
3862  *
3863  */
3864 
3865 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3866 {
3867 	u16 hang_state;
3868 	u32 fext_nvm11, tdlen;
3869 	struct e1000_hw *hw = &adapter->hw;
3870 
3871 	/* First, disable MULR fix in FEXTNVM11 */
3872 	fext_nvm11 = er32(FEXTNVM11);
3873 	fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3874 	ew32(FEXTNVM11, fext_nvm11);
3875 	/* do nothing if we're not in faulty state, or if the queue is empty */
3876 	tdlen = er32(TDLEN(0));
3877 	pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3878 			     &hang_state);
3879 	if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3880 		return;
3881 	e1000_flush_tx_ring(adapter);
3882 	/* recheck, maybe the fault is caused by the rx ring */
3883 	pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3884 			     &hang_state);
3885 	if (hang_state & FLUSH_DESC_REQUIRED)
3886 		e1000_flush_rx_ring(adapter);
3887 }
3888 
3889 /**
3890  * e1000e_systim_reset - reset the timesync registers after a hardware reset
3891  * @adapter: board private structure
3892  *
3893  * When the MAC is reset, all hardware bits for timesync will be reset to the
3894  * default values. This function will restore the settings last in place.
3895  * Since the clock SYSTIME registers are reset, we will simply restore the
3896  * cyclecounter to the kernel real clock time.
3897  **/
3898 static void e1000e_systim_reset(struct e1000_adapter *adapter)
3899 {
3900 	struct ptp_clock_info *info = &adapter->ptp_clock_info;
3901 	struct e1000_hw *hw = &adapter->hw;
3902 	unsigned long flags;
3903 	u32 timinca;
3904 	s32 ret_val;
3905 
3906 	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3907 		return;
3908 
3909 	if (info->adjfreq) {
3910 		/* restore the previous ptp frequency delta */
3911 		ret_val = info->adjfreq(info, adapter->ptp_delta);
3912 	} else {
3913 		/* set the default base frequency if no adjustment possible */
3914 		ret_val = e1000e_get_base_timinca(adapter, &timinca);
3915 		if (!ret_val)
3916 			ew32(TIMINCA, timinca);
3917 	}
3918 
3919 	if (ret_val) {
3920 		dev_warn(&adapter->pdev->dev,
3921 			 "Failed to restore TIMINCA clock rate delta: %d\n",
3922 			 ret_val);
3923 		return;
3924 	}
3925 
3926 	/* reset the systim ns time counter */
3927 	spin_lock_irqsave(&adapter->systim_lock, flags);
3928 	timecounter_init(&adapter->tc, &adapter->cc,
3929 			 ktime_to_ns(ktime_get_real()));
3930 	spin_unlock_irqrestore(&adapter->systim_lock, flags);
3931 
3932 	/* restore the previous hwtstamp configuration settings */
3933 	e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3934 }
3935 
3936 /**
3937  * e1000e_reset - bring the hardware into a known good state
3938  *
3939  * This function boots the hardware and enables some settings that
3940  * require a configuration cycle of the hardware - those cannot be
3941  * set/changed during runtime. After reset the device needs to be
3942  * properly configured for Rx, Tx etc.
3943  */
3944 void e1000e_reset(struct e1000_adapter *adapter)
3945 {
3946 	struct e1000_mac_info *mac = &adapter->hw.mac;
3947 	struct e1000_fc_info *fc = &adapter->hw.fc;
3948 	struct e1000_hw *hw = &adapter->hw;
3949 	u32 tx_space, min_tx_space, min_rx_space;
3950 	u32 pba = adapter->pba;
3951 	u16 hwm;
3952 
3953 	/* reset Packet Buffer Allocation to default */
3954 	ew32(PBA, pba);
3955 
3956 	if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3957 		/* To maintain wire speed transmits, the Tx FIFO should be
3958 		 * large enough to accommodate two full transmit packets,
3959 		 * rounded up to the next 1KB and expressed in KB.  Likewise,
3960 		 * the Rx FIFO should be large enough to accommodate at least
3961 		 * one full receive packet and is similarly rounded up and
3962 		 * expressed in KB.
3963 		 */
3964 		pba = er32(PBA);
3965 		/* upper 16 bits has Tx packet buffer allocation size in KB */
3966 		tx_space = pba >> 16;
3967 		/* lower 16 bits has Rx packet buffer allocation size in KB */
3968 		pba &= 0xffff;
3969 		/* the Tx fifo also stores 16 bytes of information about the Tx
3970 		 * but don't include ethernet FCS because hardware appends it
3971 		 */
3972 		min_tx_space = (adapter->max_frame_size +
3973 				sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3974 		min_tx_space = ALIGN(min_tx_space, 1024);
3975 		min_tx_space >>= 10;
3976 		/* software strips receive CRC, so leave room for it */
3977 		min_rx_space = adapter->max_frame_size;
3978 		min_rx_space = ALIGN(min_rx_space, 1024);
3979 		min_rx_space >>= 10;
3980 
3981 		/* If current Tx allocation is less than the min Tx FIFO size,
3982 		 * and the min Tx FIFO size is less than the current Rx FIFO
3983 		 * allocation, take space away from current Rx allocation
3984 		 */
3985 		if ((tx_space < min_tx_space) &&
3986 		    ((min_tx_space - tx_space) < pba)) {
3987 			pba -= min_tx_space - tx_space;
3988 
3989 			/* if short on Rx space, Rx wins and must trump Tx
3990 			 * adjustment
3991 			 */
3992 			if (pba < min_rx_space)
3993 				pba = min_rx_space;
3994 		}
3995 
3996 		ew32(PBA, pba);
3997 	}
3998 
3999 	/* flow control settings
4000 	 *
4001 	 * The high water mark must be low enough to fit one full frame
4002 	 * (or the size used for early receive) above it in the Rx FIFO.
4003 	 * Set it to the lower of:
4004 	 * - 90% of the Rx FIFO size, and
4005 	 * - the full Rx FIFO size minus one full frame
4006 	 */
4007 	if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4008 		fc->pause_time = 0xFFFF;
4009 	else
4010 		fc->pause_time = E1000_FC_PAUSE_TIME;
4011 	fc->send_xon = true;
4012 	fc->current_mode = fc->requested_mode;
4013 
4014 	switch (hw->mac.type) {
4015 	case e1000_ich9lan:
4016 	case e1000_ich10lan:
4017 		if (adapter->netdev->mtu > ETH_DATA_LEN) {
4018 			pba = 14;
4019 			ew32(PBA, pba);
4020 			fc->high_water = 0x2800;
4021 			fc->low_water = fc->high_water - 8;
4022 			break;
4023 		}
4024 		/* fall-through */
4025 	default:
4026 		hwm = min(((pba << 10) * 9 / 10),
4027 			  ((pba << 10) - adapter->max_frame_size));
4028 
4029 		fc->high_water = hwm & E1000_FCRTH_RTH;	/* 8-byte granularity */
4030 		fc->low_water = fc->high_water - 8;
4031 		break;
4032 	case e1000_pchlan:
4033 		/* Workaround PCH LOM adapter hangs with certain network
4034 		 * loads.  If hangs persist, try disabling Tx flow control.
4035 		 */
4036 		if (adapter->netdev->mtu > ETH_DATA_LEN) {
4037 			fc->high_water = 0x3500;
4038 			fc->low_water = 0x1500;
4039 		} else {
4040 			fc->high_water = 0x5000;
4041 			fc->low_water = 0x3000;
4042 		}
4043 		fc->refresh_time = 0x1000;
4044 		break;
4045 	case e1000_pch2lan:
4046 	case e1000_pch_lpt:
4047 	case e1000_pch_spt:
4048 	case e1000_pch_cnp:
4049 		fc->refresh_time = 0x0400;
4050 
4051 		if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4052 			fc->high_water = 0x05C20;
4053 			fc->low_water = 0x05048;
4054 			fc->pause_time = 0x0650;
4055 			break;
4056 		}
4057 
4058 		pba = 14;
4059 		ew32(PBA, pba);
4060 		fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4061 		fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4062 		break;
4063 	}
4064 
4065 	/* Alignment of Tx data is on an arbitrary byte boundary with the
4066 	 * maximum size per Tx descriptor limited only to the transmit
4067 	 * allocation of the packet buffer minus 96 bytes with an upper
4068 	 * limit of 24KB due to receive synchronization limitations.
4069 	 */
4070 	adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4071 				       24 << 10);
4072 
4073 	/* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4074 	 * fit in receive buffer.
4075 	 */
4076 	if (adapter->itr_setting & 0x3) {
4077 		if ((adapter->max_frame_size * 2) > (pba << 10)) {
4078 			if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4079 				dev_info(&adapter->pdev->dev,
4080 					 "Interrupt Throttle Rate off\n");
4081 				adapter->flags2 |= FLAG2_DISABLE_AIM;
4082 				e1000e_write_itr(adapter, 0);
4083 			}
4084 		} else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4085 			dev_info(&adapter->pdev->dev,
4086 				 "Interrupt Throttle Rate on\n");
4087 			adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4088 			adapter->itr = 20000;
4089 			e1000e_write_itr(adapter, adapter->itr);
4090 		}
4091 	}
4092 
4093 	if (hw->mac.type >= e1000_pch_spt)
4094 		e1000_flush_desc_rings(adapter);
4095 	/* Allow time for pending master requests to run */
4096 	mac->ops.reset_hw(hw);
4097 
4098 	/* For parts with AMT enabled, let the firmware know
4099 	 * that the network interface is in control
4100 	 */
4101 	if (adapter->flags & FLAG_HAS_AMT)
4102 		e1000e_get_hw_control(adapter);
4103 
4104 	ew32(WUC, 0);
4105 
4106 	if (mac->ops.init_hw(hw))
4107 		e_err("Hardware Error\n");
4108 
4109 	e1000_update_mng_vlan(adapter);
4110 
4111 	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4112 	ew32(VET, ETH_P_8021Q);
4113 
4114 	e1000e_reset_adaptive(hw);
4115 
4116 	/* restore systim and hwtstamp settings */
4117 	e1000e_systim_reset(adapter);
4118 
4119 	/* Set EEE advertisement as appropriate */
4120 	if (adapter->flags2 & FLAG2_HAS_EEE) {
4121 		s32 ret_val;
4122 		u16 adv_addr;
4123 
4124 		switch (hw->phy.type) {
4125 		case e1000_phy_82579:
4126 			adv_addr = I82579_EEE_ADVERTISEMENT;
4127 			break;
4128 		case e1000_phy_i217:
4129 			adv_addr = I217_EEE_ADVERTISEMENT;
4130 			break;
4131 		default:
4132 			dev_err(&adapter->pdev->dev,
4133 				"Invalid PHY type setting EEE advertisement\n");
4134 			return;
4135 		}
4136 
4137 		ret_val = hw->phy.ops.acquire(hw);
4138 		if (ret_val) {
4139 			dev_err(&adapter->pdev->dev,
4140 				"EEE advertisement - unable to acquire PHY\n");
4141 			return;
4142 		}
4143 
4144 		e1000_write_emi_reg_locked(hw, adv_addr,
4145 					   hw->dev_spec.ich8lan.eee_disable ?
4146 					   0 : adapter->eee_advert);
4147 
4148 		hw->phy.ops.release(hw);
4149 	}
4150 
4151 	if (!netif_running(adapter->netdev) &&
4152 	    !test_bit(__E1000_TESTING, &adapter->state))
4153 		e1000_power_down_phy(adapter);
4154 
4155 	e1000_get_phy_info(hw);
4156 
4157 	if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4158 	    !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4159 		u16 phy_data = 0;
4160 		/* speed up time to link by disabling smart power down, ignore
4161 		 * the return value of this function because there is nothing
4162 		 * different we would do if it failed
4163 		 */
4164 		e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4165 		phy_data &= ~IGP02E1000_PM_SPD;
4166 		e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4167 	}
4168 	if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4169 		u32 reg;
4170 
4171 		/* Fextnvm7 @ 0xe4[2] = 1 */
4172 		reg = er32(FEXTNVM7);
4173 		reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4174 		ew32(FEXTNVM7, reg);
4175 		/* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4176 		reg = er32(FEXTNVM9);
4177 		reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4178 		       E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4179 		ew32(FEXTNVM9, reg);
4180 	}
4181 
4182 }
4183 
4184 /**
4185  * e1000e_trigger_lsc - trigger an LSC interrupt
4186  * @adapter:
4187  *
4188  * Fire a link status change interrupt to start the watchdog.
4189  **/
4190 static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4191 {
4192 	struct e1000_hw *hw = &adapter->hw;
4193 
4194 	if (adapter->msix_entries)
4195 		ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4196 	else
4197 		ew32(ICS, E1000_ICS_LSC);
4198 }
4199 
4200 void e1000e_up(struct e1000_adapter *adapter)
4201 {
4202 	/* hardware has been reset, we need to reload some things */
4203 	e1000_configure(adapter);
4204 
4205 	clear_bit(__E1000_DOWN, &adapter->state);
4206 
4207 	if (adapter->msix_entries)
4208 		e1000_configure_msix(adapter);
4209 	e1000_irq_enable(adapter);
4210 
4211 	netif_start_queue(adapter->netdev);
4212 
4213 	e1000e_trigger_lsc(adapter);
4214 }
4215 
4216 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4217 {
4218 	struct e1000_hw *hw = &adapter->hw;
4219 
4220 	if (!(adapter->flags2 & FLAG2_DMA_BURST))
4221 		return;
4222 
4223 	/* flush pending descriptor writebacks to memory */
4224 	ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4225 	ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4226 
4227 	/* execute the writes immediately */
4228 	e1e_flush();
4229 
4230 	/* due to rare timing issues, write to TIDV/RDTR again to ensure the
4231 	 * write is successful
4232 	 */
4233 	ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4234 	ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4235 
4236 	/* execute the writes immediately */
4237 	e1e_flush();
4238 }
4239 
4240 static void e1000e_update_stats(struct e1000_adapter *adapter);
4241 
4242 /**
4243  * e1000e_down - quiesce the device and optionally reset the hardware
4244  * @adapter: board private structure
4245  * @reset: boolean flag to reset the hardware or not
4246  */
4247 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4248 {
4249 	struct net_device *netdev = adapter->netdev;
4250 	struct e1000_hw *hw = &adapter->hw;
4251 	u32 tctl, rctl;
4252 
4253 	/* signal that we're down so the interrupt handler does not
4254 	 * reschedule our watchdog timer
4255 	 */
4256 	set_bit(__E1000_DOWN, &adapter->state);
4257 
4258 	netif_carrier_off(netdev);
4259 
4260 	/* disable receives in the hardware */
4261 	rctl = er32(RCTL);
4262 	if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4263 		ew32(RCTL, rctl & ~E1000_RCTL_EN);
4264 	/* flush and sleep below */
4265 
4266 	netif_stop_queue(netdev);
4267 
4268 	/* disable transmits in the hardware */
4269 	tctl = er32(TCTL);
4270 	tctl &= ~E1000_TCTL_EN;
4271 	ew32(TCTL, tctl);
4272 
4273 	/* flush both disables and wait for them to finish */
4274 	e1e_flush();
4275 	usleep_range(10000, 20000);
4276 
4277 	e1000_irq_disable(adapter);
4278 
4279 	napi_synchronize(&adapter->napi);
4280 
4281 	del_timer_sync(&adapter->watchdog_timer);
4282 	del_timer_sync(&adapter->phy_info_timer);
4283 
4284 	spin_lock(&adapter->stats64_lock);
4285 	e1000e_update_stats(adapter);
4286 	spin_unlock(&adapter->stats64_lock);
4287 
4288 	e1000e_flush_descriptors(adapter);
4289 
4290 	adapter->link_speed = 0;
4291 	adapter->link_duplex = 0;
4292 
4293 	/* Disable Si errata workaround on PCHx for jumbo frame flow */
4294 	if ((hw->mac.type >= e1000_pch2lan) &&
4295 	    (adapter->netdev->mtu > ETH_DATA_LEN) &&
4296 	    e1000_lv_jumbo_workaround_ich8lan(hw, false))
4297 		e_dbg("failed to disable jumbo frame workaround mode\n");
4298 
4299 	if (!pci_channel_offline(adapter->pdev)) {
4300 		if (reset)
4301 			e1000e_reset(adapter);
4302 		else if (hw->mac.type >= e1000_pch_spt)
4303 			e1000_flush_desc_rings(adapter);
4304 	}
4305 	e1000_clean_tx_ring(adapter->tx_ring);
4306 	e1000_clean_rx_ring(adapter->rx_ring);
4307 }
4308 
4309 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4310 {
4311 	might_sleep();
4312 	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4313 		usleep_range(1000, 2000);
4314 	e1000e_down(adapter, true);
4315 	e1000e_up(adapter);
4316 	clear_bit(__E1000_RESETTING, &adapter->state);
4317 }
4318 
4319 /**
4320  * e1000e_sanitize_systim - sanitize raw cycle counter reads
4321  * @hw: pointer to the HW structure
4322  * @systim: PHC time value read, sanitized and returned
4323  * @sts: structure to hold system time before and after reading SYSTIML,
4324  * may be NULL
4325  *
4326  * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4327  * check to see that the time is incrementing at a reasonable
4328  * rate and is a multiple of incvalue.
4329  **/
4330 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4331 				  struct ptp_system_timestamp *sts)
4332 {
4333 	u64 time_delta, rem, temp;
4334 	u64 systim_next;
4335 	u32 incvalue;
4336 	int i;
4337 
4338 	incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4339 	for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4340 		/* latch SYSTIMH on read of SYSTIML */
4341 		ptp_read_system_prets(sts);
4342 		systim_next = (u64)er32(SYSTIML);
4343 		ptp_read_system_postts(sts);
4344 		systim_next |= (u64)er32(SYSTIMH) << 32;
4345 
4346 		time_delta = systim_next - systim;
4347 		temp = time_delta;
4348 		/* VMWare users have seen incvalue of zero, don't div / 0 */
4349 		rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4350 
4351 		systim = systim_next;
4352 
4353 		if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4354 			break;
4355 	}
4356 
4357 	return systim;
4358 }
4359 
4360 /**
4361  * e1000e_read_systim - read SYSTIM register
4362  * @adapter: board private structure
4363  * @sts: structure which will contain system time before and after reading
4364  * SYSTIML, may be NULL
4365  **/
4366 u64 e1000e_read_systim(struct e1000_adapter *adapter,
4367 		       struct ptp_system_timestamp *sts)
4368 {
4369 	struct e1000_hw *hw = &adapter->hw;
4370 	u32 systimel, systimel_2, systimeh;
4371 	u64 systim;
4372 	/* SYSTIMH latching upon SYSTIML read does not work well.
4373 	 * This means that if SYSTIML overflows after we read it but before
4374 	 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4375 	 * will experience a huge non linear increment in the systime value
4376 	 * to fix that we test for overflow and if true, we re-read systime.
4377 	 */
4378 	ptp_read_system_prets(sts);
4379 	systimel = er32(SYSTIML);
4380 	ptp_read_system_postts(sts);
4381 	systimeh = er32(SYSTIMH);
4382 	/* Is systimel is so large that overflow is possible? */
4383 	if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4384 		ptp_read_system_prets(sts);
4385 		systimel_2 = er32(SYSTIML);
4386 		ptp_read_system_postts(sts);
4387 		if (systimel > systimel_2) {
4388 			/* There was an overflow, read again SYSTIMH, and use
4389 			 * systimel_2
4390 			 */
4391 			systimeh = er32(SYSTIMH);
4392 			systimel = systimel_2;
4393 		}
4394 	}
4395 	systim = (u64)systimel;
4396 	systim |= (u64)systimeh << 32;
4397 
4398 	if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4399 		systim = e1000e_sanitize_systim(hw, systim, sts);
4400 
4401 	return systim;
4402 }
4403 
4404 /**
4405  * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4406  * @cc: cyclecounter structure
4407  **/
4408 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4409 {
4410 	struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4411 						     cc);
4412 
4413 	return e1000e_read_systim(adapter, NULL);
4414 }
4415 
4416 /**
4417  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4418  * @adapter: board private structure to initialize
4419  *
4420  * e1000_sw_init initializes the Adapter private data structure.
4421  * Fields are initialized based on PCI device information and
4422  * OS network device settings (MTU size).
4423  **/
4424 static int e1000_sw_init(struct e1000_adapter *adapter)
4425 {
4426 	struct net_device *netdev = adapter->netdev;
4427 
4428 	adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4429 	adapter->rx_ps_bsize0 = 128;
4430 	adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4431 	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4432 	adapter->tx_ring_count = E1000_DEFAULT_TXD;
4433 	adapter->rx_ring_count = E1000_DEFAULT_RXD;
4434 
4435 	spin_lock_init(&adapter->stats64_lock);
4436 
4437 	e1000e_set_interrupt_capability(adapter);
4438 
4439 	if (e1000_alloc_queues(adapter))
4440 		return -ENOMEM;
4441 
4442 	/* Setup hardware time stamping cyclecounter */
4443 	if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4444 		adapter->cc.read = e1000e_cyclecounter_read;
4445 		adapter->cc.mask = CYCLECOUNTER_MASK(64);
4446 		adapter->cc.mult = 1;
4447 		/* cc.shift set in e1000e_get_base_tininca() */
4448 
4449 		spin_lock_init(&adapter->systim_lock);
4450 		INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4451 	}
4452 
4453 	/* Explicitly disable IRQ since the NIC can be in any state. */
4454 	e1000_irq_disable(adapter);
4455 
4456 	set_bit(__E1000_DOWN, &adapter->state);
4457 	return 0;
4458 }
4459 
4460 /**
4461  * e1000_intr_msi_test - Interrupt Handler
4462  * @irq: interrupt number
4463  * @data: pointer to a network interface device structure
4464  **/
4465 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4466 {
4467 	struct net_device *netdev = data;
4468 	struct e1000_adapter *adapter = netdev_priv(netdev);
4469 	struct e1000_hw *hw = &adapter->hw;
4470 	u32 icr = er32(ICR);
4471 
4472 	e_dbg("icr is %08X\n", icr);
4473 	if (icr & E1000_ICR_RXSEQ) {
4474 		adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4475 		/* Force memory writes to complete before acknowledging the
4476 		 * interrupt is handled.
4477 		 */
4478 		wmb();
4479 	}
4480 
4481 	return IRQ_HANDLED;
4482 }
4483 
4484 /**
4485  * e1000_test_msi_interrupt - Returns 0 for successful test
4486  * @adapter: board private struct
4487  *
4488  * code flow taken from tg3.c
4489  **/
4490 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4491 {
4492 	struct net_device *netdev = adapter->netdev;
4493 	struct e1000_hw *hw = &adapter->hw;
4494 	int err;
4495 
4496 	/* poll_enable hasn't been called yet, so don't need disable */
4497 	/* clear any pending events */
4498 	er32(ICR);
4499 
4500 	/* free the real vector and request a test handler */
4501 	e1000_free_irq(adapter);
4502 	e1000e_reset_interrupt_capability(adapter);
4503 
4504 	/* Assume that the test fails, if it succeeds then the test
4505 	 * MSI irq handler will unset this flag
4506 	 */
4507 	adapter->flags |= FLAG_MSI_TEST_FAILED;
4508 
4509 	err = pci_enable_msi(adapter->pdev);
4510 	if (err)
4511 		goto msi_test_failed;
4512 
4513 	err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4514 			  netdev->name, netdev);
4515 	if (err) {
4516 		pci_disable_msi(adapter->pdev);
4517 		goto msi_test_failed;
4518 	}
4519 
4520 	/* Force memory writes to complete before enabling and firing an
4521 	 * interrupt.
4522 	 */
4523 	wmb();
4524 
4525 	e1000_irq_enable(adapter);
4526 
4527 	/* fire an unusual interrupt on the test handler */
4528 	ew32(ICS, E1000_ICS_RXSEQ);
4529 	e1e_flush();
4530 	msleep(100);
4531 
4532 	e1000_irq_disable(adapter);
4533 
4534 	rmb();			/* read flags after interrupt has been fired */
4535 
4536 	if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4537 		adapter->int_mode = E1000E_INT_MODE_LEGACY;
4538 		e_info("MSI interrupt test failed, using legacy interrupt.\n");
4539 	} else {
4540 		e_dbg("MSI interrupt test succeeded!\n");
4541 	}
4542 
4543 	free_irq(adapter->pdev->irq, netdev);
4544 	pci_disable_msi(adapter->pdev);
4545 
4546 msi_test_failed:
4547 	e1000e_set_interrupt_capability(adapter);
4548 	return e1000_request_irq(adapter);
4549 }
4550 
4551 /**
4552  * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4553  * @adapter: board private struct
4554  *
4555  * code flow taken from tg3.c, called with e1000 interrupts disabled.
4556  **/
4557 static int e1000_test_msi(struct e1000_adapter *adapter)
4558 {
4559 	int err;
4560 	u16 pci_cmd;
4561 
4562 	if (!(adapter->flags & FLAG_MSI_ENABLED))
4563 		return 0;
4564 
4565 	/* disable SERR in case the MSI write causes a master abort */
4566 	pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4567 	if (pci_cmd & PCI_COMMAND_SERR)
4568 		pci_write_config_word(adapter->pdev, PCI_COMMAND,
4569 				      pci_cmd & ~PCI_COMMAND_SERR);
4570 
4571 	err = e1000_test_msi_interrupt(adapter);
4572 
4573 	/* re-enable SERR */
4574 	if (pci_cmd & PCI_COMMAND_SERR) {
4575 		pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4576 		pci_cmd |= PCI_COMMAND_SERR;
4577 		pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4578 	}
4579 
4580 	return err;
4581 }
4582 
4583 /**
4584  * e1000e_open - Called when a network interface is made active
4585  * @netdev: network interface device structure
4586  *
4587  * Returns 0 on success, negative value on failure
4588  *
4589  * The open entry point is called when a network interface is made
4590  * active by the system (IFF_UP).  At this point all resources needed
4591  * for transmit and receive operations are allocated, the interrupt
4592  * handler is registered with the OS, the watchdog timer is started,
4593  * and the stack is notified that the interface is ready.
4594  **/
4595 int e1000e_open(struct net_device *netdev)
4596 {
4597 	struct e1000_adapter *adapter = netdev_priv(netdev);
4598 	struct e1000_hw *hw = &adapter->hw;
4599 	struct pci_dev *pdev = adapter->pdev;
4600 	int err;
4601 
4602 	/* disallow open during test */
4603 	if (test_bit(__E1000_TESTING, &adapter->state))
4604 		return -EBUSY;
4605 
4606 	pm_runtime_get_sync(&pdev->dev);
4607 
4608 	netif_carrier_off(netdev);
4609 
4610 	/* allocate transmit descriptors */
4611 	err = e1000e_setup_tx_resources(adapter->tx_ring);
4612 	if (err)
4613 		goto err_setup_tx;
4614 
4615 	/* allocate receive descriptors */
4616 	err = e1000e_setup_rx_resources(adapter->rx_ring);
4617 	if (err)
4618 		goto err_setup_rx;
4619 
4620 	/* If AMT is enabled, let the firmware know that the network
4621 	 * interface is now open and reset the part to a known state.
4622 	 */
4623 	if (adapter->flags & FLAG_HAS_AMT) {
4624 		e1000e_get_hw_control(adapter);
4625 		e1000e_reset(adapter);
4626 	}
4627 
4628 	e1000e_power_up_phy(adapter);
4629 
4630 	adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4631 	if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4632 		e1000_update_mng_vlan(adapter);
4633 
4634 	/* DMA latency requirement to workaround jumbo issue */
4635 	pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4636 			   PM_QOS_DEFAULT_VALUE);
4637 
4638 	/* before we allocate an interrupt, we must be ready to handle it.
4639 	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4640 	 * as soon as we call pci_request_irq, so we have to setup our
4641 	 * clean_rx handler before we do so.
4642 	 */
4643 	e1000_configure(adapter);
4644 
4645 	err = e1000_request_irq(adapter);
4646 	if (err)
4647 		goto err_req_irq;
4648 
4649 	/* Work around PCIe errata with MSI interrupts causing some chipsets to
4650 	 * ignore e1000e MSI messages, which means we need to test our MSI
4651 	 * interrupt now
4652 	 */
4653 	if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4654 		err = e1000_test_msi(adapter);
4655 		if (err) {
4656 			e_err("Interrupt allocation failed\n");
4657 			goto err_req_irq;
4658 		}
4659 	}
4660 
4661 	/* From here on the code is the same as e1000e_up() */
4662 	clear_bit(__E1000_DOWN, &adapter->state);
4663 
4664 	napi_enable(&adapter->napi);
4665 
4666 	e1000_irq_enable(adapter);
4667 
4668 	adapter->tx_hang_recheck = false;
4669 	netif_start_queue(netdev);
4670 
4671 	hw->mac.get_link_status = true;
4672 	pm_runtime_put(&pdev->dev);
4673 
4674 	e1000e_trigger_lsc(adapter);
4675 
4676 	return 0;
4677 
4678 err_req_irq:
4679 	pm_qos_remove_request(&adapter->pm_qos_req);
4680 	e1000e_release_hw_control(adapter);
4681 	e1000_power_down_phy(adapter);
4682 	e1000e_free_rx_resources(adapter->rx_ring);
4683 err_setup_rx:
4684 	e1000e_free_tx_resources(adapter->tx_ring);
4685 err_setup_tx:
4686 	e1000e_reset(adapter);
4687 	pm_runtime_put_sync(&pdev->dev);
4688 
4689 	return err;
4690 }
4691 
4692 /**
4693  * e1000e_close - Disables a network interface
4694  * @netdev: network interface device structure
4695  *
4696  * Returns 0, this is not allowed to fail
4697  *
4698  * The close entry point is called when an interface is de-activated
4699  * by the OS.  The hardware is still under the drivers control, but
4700  * needs to be disabled.  A global MAC reset is issued to stop the
4701  * hardware, and all transmit and receive resources are freed.
4702  **/
4703 int e1000e_close(struct net_device *netdev)
4704 {
4705 	struct e1000_adapter *adapter = netdev_priv(netdev);
4706 	struct pci_dev *pdev = adapter->pdev;
4707 	int count = E1000_CHECK_RESET_COUNT;
4708 
4709 	while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4710 		usleep_range(10000, 20000);
4711 
4712 	WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4713 
4714 	pm_runtime_get_sync(&pdev->dev);
4715 
4716 	if (!test_bit(__E1000_DOWN, &adapter->state)) {
4717 		e1000e_down(adapter, true);
4718 		e1000_free_irq(adapter);
4719 
4720 		/* Link status message must follow this format */
4721 		pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4722 	}
4723 
4724 	napi_disable(&adapter->napi);
4725 
4726 	e1000e_free_tx_resources(adapter->tx_ring);
4727 	e1000e_free_rx_resources(adapter->rx_ring);
4728 
4729 	/* kill manageability vlan ID if supported, but not if a vlan with
4730 	 * the same ID is registered on the host OS (let 8021q kill it)
4731 	 */
4732 	if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4733 		e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4734 				       adapter->mng_vlan_id);
4735 
4736 	/* If AMT is enabled, let the firmware know that the network
4737 	 * interface is now closed
4738 	 */
4739 	if ((adapter->flags & FLAG_HAS_AMT) &&
4740 	    !test_bit(__E1000_TESTING, &adapter->state))
4741 		e1000e_release_hw_control(adapter);
4742 
4743 	pm_qos_remove_request(&adapter->pm_qos_req);
4744 
4745 	pm_runtime_put_sync(&pdev->dev);
4746 
4747 	return 0;
4748 }
4749 
4750 /**
4751  * e1000_set_mac - Change the Ethernet Address of the NIC
4752  * @netdev: network interface device structure
4753  * @p: pointer to an address structure
4754  *
4755  * Returns 0 on success, negative on failure
4756  **/
4757 static int e1000_set_mac(struct net_device *netdev, void *p)
4758 {
4759 	struct e1000_adapter *adapter = netdev_priv(netdev);
4760 	struct e1000_hw *hw = &adapter->hw;
4761 	struct sockaddr *addr = p;
4762 
4763 	if (!is_valid_ether_addr(addr->sa_data))
4764 		return -EADDRNOTAVAIL;
4765 
4766 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4767 	memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4768 
4769 	hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4770 
4771 	if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4772 		/* activate the work around */
4773 		e1000e_set_laa_state_82571(&adapter->hw, 1);
4774 
4775 		/* Hold a copy of the LAA in RAR[14] This is done so that
4776 		 * between the time RAR[0] gets clobbered  and the time it
4777 		 * gets fixed (in e1000_watchdog), the actual LAA is in one
4778 		 * of the RARs and no incoming packets directed to this port
4779 		 * are dropped. Eventually the LAA will be in RAR[0] and
4780 		 * RAR[14]
4781 		 */
4782 		hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4783 				    adapter->hw.mac.rar_entry_count - 1);
4784 	}
4785 
4786 	return 0;
4787 }
4788 
4789 /**
4790  * e1000e_update_phy_task - work thread to update phy
4791  * @work: pointer to our work struct
4792  *
4793  * this worker thread exists because we must acquire a
4794  * semaphore to read the phy, which we could msleep while
4795  * waiting for it, and we can't msleep in a timer.
4796  **/
4797 static void e1000e_update_phy_task(struct work_struct *work)
4798 {
4799 	struct e1000_adapter *adapter = container_of(work,
4800 						     struct e1000_adapter,
4801 						     update_phy_task);
4802 	struct e1000_hw *hw = &adapter->hw;
4803 
4804 	if (test_bit(__E1000_DOWN, &adapter->state))
4805 		return;
4806 
4807 	e1000_get_phy_info(hw);
4808 
4809 	/* Enable EEE on 82579 after link up */
4810 	if (hw->phy.type >= e1000_phy_82579)
4811 		e1000_set_eee_pchlan(hw);
4812 }
4813 
4814 /**
4815  * e1000_update_phy_info - timre call-back to update PHY info
4816  * @data: pointer to adapter cast into an unsigned long
4817  *
4818  * Need to wait a few seconds after link up to get diagnostic information from
4819  * the phy
4820  **/
4821 static void e1000_update_phy_info(struct timer_list *t)
4822 {
4823 	struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4824 
4825 	if (test_bit(__E1000_DOWN, &adapter->state))
4826 		return;
4827 
4828 	schedule_work(&adapter->update_phy_task);
4829 }
4830 
4831 /**
4832  * e1000e_update_phy_stats - Update the PHY statistics counters
4833  * @adapter: board private structure
4834  *
4835  * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4836  **/
4837 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4838 {
4839 	struct e1000_hw *hw = &adapter->hw;
4840 	s32 ret_val;
4841 	u16 phy_data;
4842 
4843 	ret_val = hw->phy.ops.acquire(hw);
4844 	if (ret_val)
4845 		return;
4846 
4847 	/* A page set is expensive so check if already on desired page.
4848 	 * If not, set to the page with the PHY status registers.
4849 	 */
4850 	hw->phy.addr = 1;
4851 	ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4852 					   &phy_data);
4853 	if (ret_val)
4854 		goto release;
4855 	if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4856 		ret_val = hw->phy.ops.set_page(hw,
4857 					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
4858 		if (ret_val)
4859 			goto release;
4860 	}
4861 
4862 	/* Single Collision Count */
4863 	hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4864 	ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4865 	if (!ret_val)
4866 		adapter->stats.scc += phy_data;
4867 
4868 	/* Excessive Collision Count */
4869 	hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4870 	ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4871 	if (!ret_val)
4872 		adapter->stats.ecol += phy_data;
4873 
4874 	/* Multiple Collision Count */
4875 	hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4876 	ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4877 	if (!ret_val)
4878 		adapter->stats.mcc += phy_data;
4879 
4880 	/* Late Collision Count */
4881 	hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4882 	ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4883 	if (!ret_val)
4884 		adapter->stats.latecol += phy_data;
4885 
4886 	/* Collision Count - also used for adaptive IFS */
4887 	hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4888 	ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4889 	if (!ret_val)
4890 		hw->mac.collision_delta = phy_data;
4891 
4892 	/* Defer Count */
4893 	hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4894 	ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4895 	if (!ret_val)
4896 		adapter->stats.dc += phy_data;
4897 
4898 	/* Transmit with no CRS */
4899 	hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4900 	ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4901 	if (!ret_val)
4902 		adapter->stats.tncrs += phy_data;
4903 
4904 release:
4905 	hw->phy.ops.release(hw);
4906 }
4907 
4908 /**
4909  * e1000e_update_stats - Update the board statistics counters
4910  * @adapter: board private structure
4911  **/
4912 static void e1000e_update_stats(struct e1000_adapter *adapter)
4913 {
4914 	struct net_device *netdev = adapter->netdev;
4915 	struct e1000_hw *hw = &adapter->hw;
4916 	struct pci_dev *pdev = adapter->pdev;
4917 
4918 	/* Prevent stats update while adapter is being reset, or if the pci
4919 	 * connection is down.
4920 	 */
4921 	if (adapter->link_speed == 0)
4922 		return;
4923 	if (pci_channel_offline(pdev))
4924 		return;
4925 
4926 	adapter->stats.crcerrs += er32(CRCERRS);
4927 	adapter->stats.gprc += er32(GPRC);
4928 	adapter->stats.gorc += er32(GORCL);
4929 	er32(GORCH);		/* Clear gorc */
4930 	adapter->stats.bprc += er32(BPRC);
4931 	adapter->stats.mprc += er32(MPRC);
4932 	adapter->stats.roc += er32(ROC);
4933 
4934 	adapter->stats.mpc += er32(MPC);
4935 
4936 	/* Half-duplex statistics */
4937 	if (adapter->link_duplex == HALF_DUPLEX) {
4938 		if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4939 			e1000e_update_phy_stats(adapter);
4940 		} else {
4941 			adapter->stats.scc += er32(SCC);
4942 			adapter->stats.ecol += er32(ECOL);
4943 			adapter->stats.mcc += er32(MCC);
4944 			adapter->stats.latecol += er32(LATECOL);
4945 			adapter->stats.dc += er32(DC);
4946 
4947 			hw->mac.collision_delta = er32(COLC);
4948 
4949 			if ((hw->mac.type != e1000_82574) &&
4950 			    (hw->mac.type != e1000_82583))
4951 				adapter->stats.tncrs += er32(TNCRS);
4952 		}
4953 		adapter->stats.colc += hw->mac.collision_delta;
4954 	}
4955 
4956 	adapter->stats.xonrxc += er32(XONRXC);
4957 	adapter->stats.xontxc += er32(XONTXC);
4958 	adapter->stats.xoffrxc += er32(XOFFRXC);
4959 	adapter->stats.xofftxc += er32(XOFFTXC);
4960 	adapter->stats.gptc += er32(GPTC);
4961 	adapter->stats.gotc += er32(GOTCL);
4962 	er32(GOTCH);		/* Clear gotc */
4963 	adapter->stats.rnbc += er32(RNBC);
4964 	adapter->stats.ruc += er32(RUC);
4965 
4966 	adapter->stats.mptc += er32(MPTC);
4967 	adapter->stats.bptc += er32(BPTC);
4968 
4969 	/* used for adaptive IFS */
4970 
4971 	hw->mac.tx_packet_delta = er32(TPT);
4972 	adapter->stats.tpt += hw->mac.tx_packet_delta;
4973 
4974 	adapter->stats.algnerrc += er32(ALGNERRC);
4975 	adapter->stats.rxerrc += er32(RXERRC);
4976 	adapter->stats.cexterr += er32(CEXTERR);
4977 	adapter->stats.tsctc += er32(TSCTC);
4978 	adapter->stats.tsctfc += er32(TSCTFC);
4979 
4980 	/* Fill out the OS statistics structure */
4981 	netdev->stats.multicast = adapter->stats.mprc;
4982 	netdev->stats.collisions = adapter->stats.colc;
4983 
4984 	/* Rx Errors */
4985 
4986 	/* RLEC on some newer hardware can be incorrect so build
4987 	 * our own version based on RUC and ROC
4988 	 */
4989 	netdev->stats.rx_errors = adapter->stats.rxerrc +
4990 	    adapter->stats.crcerrs + adapter->stats.algnerrc +
4991 	    adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4992 	netdev->stats.rx_length_errors = adapter->stats.ruc +
4993 	    adapter->stats.roc;
4994 	netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4995 	netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4996 	netdev->stats.rx_missed_errors = adapter->stats.mpc;
4997 
4998 	/* Tx Errors */
4999 	netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5000 	netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5001 	netdev->stats.tx_window_errors = adapter->stats.latecol;
5002 	netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5003 
5004 	/* Tx Dropped needs to be maintained elsewhere */
5005 
5006 	/* Management Stats */
5007 	adapter->stats.mgptc += er32(MGTPTC);
5008 	adapter->stats.mgprc += er32(MGTPRC);
5009 	adapter->stats.mgpdc += er32(MGTPDC);
5010 
5011 	/* Correctable ECC Errors */
5012 	if (hw->mac.type >= e1000_pch_lpt) {
5013 		u32 pbeccsts = er32(PBECCSTS);
5014 
5015 		adapter->corr_errors +=
5016 		    pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5017 		adapter->uncorr_errors +=
5018 		    (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5019 		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5020 	}
5021 }
5022 
5023 /**
5024  * e1000_phy_read_status - Update the PHY register status snapshot
5025  * @adapter: board private structure
5026  **/
5027 static void e1000_phy_read_status(struct e1000_adapter *adapter)
5028 {
5029 	struct e1000_hw *hw = &adapter->hw;
5030 	struct e1000_phy_regs *phy = &adapter->phy_regs;
5031 
5032 	if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5033 	    (er32(STATUS) & E1000_STATUS_LU) &&
5034 	    (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5035 		int ret_val;
5036 
5037 		ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5038 		ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5039 		ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5040 		ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5041 		ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5042 		ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5043 		ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5044 		ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5045 		if (ret_val)
5046 			e_warn("Error reading PHY register\n");
5047 	} else {
5048 		/* Do not read PHY registers if link is not up
5049 		 * Set values to typical power-on defaults
5050 		 */
5051 		phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5052 		phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5053 			     BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5054 			     BMSR_ERCAP);
5055 		phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5056 				  ADVERTISE_ALL | ADVERTISE_CSMA);
5057 		phy->lpa = 0;
5058 		phy->expansion = EXPANSION_ENABLENPAGE;
5059 		phy->ctrl1000 = ADVERTISE_1000FULL;
5060 		phy->stat1000 = 0;
5061 		phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5062 	}
5063 }
5064 
5065 static void e1000_print_link_info(struct e1000_adapter *adapter)
5066 {
5067 	struct e1000_hw *hw = &adapter->hw;
5068 	u32 ctrl = er32(CTRL);
5069 
5070 	/* Link status message must follow this format for user tools */
5071 	pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5072 		adapter->netdev->name, adapter->link_speed,
5073 		adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5074 		(ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5075 		(ctrl & E1000_CTRL_RFCE) ? "Rx" :
5076 		(ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5077 }
5078 
5079 static bool e1000e_has_link(struct e1000_adapter *adapter)
5080 {
5081 	struct e1000_hw *hw = &adapter->hw;
5082 	bool link_active = false;
5083 	s32 ret_val = 0;
5084 
5085 	/* get_link_status is set on LSC (link status) interrupt or
5086 	 * Rx sequence error interrupt.  get_link_status will stay
5087 	 * true until the check_for_link establishes link
5088 	 * for copper adapters ONLY
5089 	 */
5090 	switch (hw->phy.media_type) {
5091 	case e1000_media_type_copper:
5092 		if (hw->mac.get_link_status) {
5093 			ret_val = hw->mac.ops.check_for_link(hw);
5094 			link_active = !hw->mac.get_link_status;
5095 		} else {
5096 			link_active = true;
5097 		}
5098 		break;
5099 	case e1000_media_type_fiber:
5100 		ret_val = hw->mac.ops.check_for_link(hw);
5101 		link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5102 		break;
5103 	case e1000_media_type_internal_serdes:
5104 		ret_val = hw->mac.ops.check_for_link(hw);
5105 		link_active = hw->mac.serdes_has_link;
5106 		break;
5107 	default:
5108 	case e1000_media_type_unknown:
5109 		break;
5110 	}
5111 
5112 	if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5113 	    (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5114 		/* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5115 		e_info("Gigabit has been disabled, downgrading speed\n");
5116 	}
5117 
5118 	return link_active;
5119 }
5120 
5121 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5122 {
5123 	/* make sure the receive unit is started */
5124 	if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5125 	    (adapter->flags & FLAG_RESTART_NOW)) {
5126 		struct e1000_hw *hw = &adapter->hw;
5127 		u32 rctl = er32(RCTL);
5128 
5129 		ew32(RCTL, rctl | E1000_RCTL_EN);
5130 		adapter->flags &= ~FLAG_RESTART_NOW;
5131 	}
5132 }
5133 
5134 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5135 {
5136 	struct e1000_hw *hw = &adapter->hw;
5137 
5138 	/* With 82574 controllers, PHY needs to be checked periodically
5139 	 * for hung state and reset, if two calls return true
5140 	 */
5141 	if (e1000_check_phy_82574(hw))
5142 		adapter->phy_hang_count++;
5143 	else
5144 		adapter->phy_hang_count = 0;
5145 
5146 	if (adapter->phy_hang_count > 1) {
5147 		adapter->phy_hang_count = 0;
5148 		e_dbg("PHY appears hung - resetting\n");
5149 		schedule_work(&adapter->reset_task);
5150 	}
5151 }
5152 
5153 /**
5154  * e1000_watchdog - Timer Call-back
5155  * @data: pointer to adapter cast into an unsigned long
5156  **/
5157 static void e1000_watchdog(struct timer_list *t)
5158 {
5159 	struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5160 
5161 	/* Do the rest outside of interrupt context */
5162 	schedule_work(&adapter->watchdog_task);
5163 
5164 	/* TODO: make this use queue_delayed_work() */
5165 }
5166 
5167 static void e1000_watchdog_task(struct work_struct *work)
5168 {
5169 	struct e1000_adapter *adapter = container_of(work,
5170 						     struct e1000_adapter,
5171 						     watchdog_task);
5172 	struct net_device *netdev = adapter->netdev;
5173 	struct e1000_mac_info *mac = &adapter->hw.mac;
5174 	struct e1000_phy_info *phy = &adapter->hw.phy;
5175 	struct e1000_ring *tx_ring = adapter->tx_ring;
5176 	struct e1000_hw *hw = &adapter->hw;
5177 	u32 link, tctl;
5178 
5179 	if (test_bit(__E1000_DOWN, &adapter->state))
5180 		return;
5181 
5182 	link = e1000e_has_link(adapter);
5183 	if ((netif_carrier_ok(netdev)) && link) {
5184 		/* Cancel scheduled suspend requests. */
5185 		pm_runtime_resume(netdev->dev.parent);
5186 
5187 		e1000e_enable_receives(adapter);
5188 		goto link_up;
5189 	}
5190 
5191 	if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5192 	    (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5193 		e1000_update_mng_vlan(adapter);
5194 
5195 	if (link) {
5196 		if (!netif_carrier_ok(netdev)) {
5197 			bool txb2b = true;
5198 
5199 			/* Cancel scheduled suspend requests. */
5200 			pm_runtime_resume(netdev->dev.parent);
5201 
5202 			/* update snapshot of PHY registers on LSC */
5203 			e1000_phy_read_status(adapter);
5204 			mac->ops.get_link_up_info(&adapter->hw,
5205 						  &adapter->link_speed,
5206 						  &adapter->link_duplex);
5207 			e1000_print_link_info(adapter);
5208 
5209 			/* check if SmartSpeed worked */
5210 			e1000e_check_downshift(hw);
5211 			if (phy->speed_downgraded)
5212 				netdev_warn(netdev,
5213 					    "Link Speed was downgraded by SmartSpeed\n");
5214 
5215 			/* On supported PHYs, check for duplex mismatch only
5216 			 * if link has autonegotiated at 10/100 half
5217 			 */
5218 			if ((hw->phy.type == e1000_phy_igp_3 ||
5219 			     hw->phy.type == e1000_phy_bm) &&
5220 			    hw->mac.autoneg &&
5221 			    (adapter->link_speed == SPEED_10 ||
5222 			     adapter->link_speed == SPEED_100) &&
5223 			    (adapter->link_duplex == HALF_DUPLEX)) {
5224 				u16 autoneg_exp;
5225 
5226 				e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5227 
5228 				if (!(autoneg_exp & EXPANSION_NWAY))
5229 					e_info("Autonegotiated half duplex but link partner cannot autoneg.  Try forcing full duplex if link gets many collisions.\n");
5230 			}
5231 
5232 			/* adjust timeout factor according to speed/duplex */
5233 			adapter->tx_timeout_factor = 1;
5234 			switch (adapter->link_speed) {
5235 			case SPEED_10:
5236 				txb2b = false;
5237 				adapter->tx_timeout_factor = 16;
5238 				break;
5239 			case SPEED_100:
5240 				txb2b = false;
5241 				adapter->tx_timeout_factor = 10;
5242 				break;
5243 			}
5244 
5245 			/* workaround: re-program speed mode bit after
5246 			 * link-up event
5247 			 */
5248 			if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5249 			    !txb2b) {
5250 				u32 tarc0;
5251 
5252 				tarc0 = er32(TARC(0));
5253 				tarc0 &= ~SPEED_MODE_BIT;
5254 				ew32(TARC(0), tarc0);
5255 			}
5256 
5257 			/* disable TSO for pcie and 10/100 speeds, to avoid
5258 			 * some hardware issues
5259 			 */
5260 			if (!(adapter->flags & FLAG_TSO_FORCE)) {
5261 				switch (adapter->link_speed) {
5262 				case SPEED_10:
5263 				case SPEED_100:
5264 					e_info("10/100 speed: disabling TSO\n");
5265 					netdev->features &= ~NETIF_F_TSO;
5266 					netdev->features &= ~NETIF_F_TSO6;
5267 					break;
5268 				case SPEED_1000:
5269 					netdev->features |= NETIF_F_TSO;
5270 					netdev->features |= NETIF_F_TSO6;
5271 					break;
5272 				default:
5273 					/* oops */
5274 					break;
5275 				}
5276 			}
5277 
5278 			/* enable transmits in the hardware, need to do this
5279 			 * after setting TARC(0)
5280 			 */
5281 			tctl = er32(TCTL);
5282 			tctl |= E1000_TCTL_EN;
5283 			ew32(TCTL, tctl);
5284 
5285 			/* Perform any post-link-up configuration before
5286 			 * reporting link up.
5287 			 */
5288 			if (phy->ops.cfg_on_link_up)
5289 				phy->ops.cfg_on_link_up(hw);
5290 
5291 			netif_carrier_on(netdev);
5292 
5293 			if (!test_bit(__E1000_DOWN, &adapter->state))
5294 				mod_timer(&adapter->phy_info_timer,
5295 					  round_jiffies(jiffies + 2 * HZ));
5296 		}
5297 	} else {
5298 		if (netif_carrier_ok(netdev)) {
5299 			adapter->link_speed = 0;
5300 			adapter->link_duplex = 0;
5301 			/* Link status message must follow this format */
5302 			pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5303 			netif_carrier_off(netdev);
5304 			if (!test_bit(__E1000_DOWN, &adapter->state))
5305 				mod_timer(&adapter->phy_info_timer,
5306 					  round_jiffies(jiffies + 2 * HZ));
5307 
5308 			/* 8000ES2LAN requires a Rx packet buffer work-around
5309 			 * on link down event; reset the controller to flush
5310 			 * the Rx packet buffer.
5311 			 *
5312 			 * If the link is lost the controller stops DMA, but
5313 			 * if there is queued Tx work it cannot be done.  So
5314 			 * reset the controller to flush the Tx packet buffers.
5315 			 */
5316 			if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
5317 			    e1000_desc_unused(tx_ring) + 1 < tx_ring->count)
5318 				adapter->flags |= FLAG_RESTART_NOW;
5319 			else
5320 				pm_schedule_suspend(netdev->dev.parent,
5321 						    LINK_TIMEOUT);
5322 		}
5323 	}
5324 
5325 link_up:
5326 	spin_lock(&adapter->stats64_lock);
5327 	e1000e_update_stats(adapter);
5328 
5329 	mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5330 	adapter->tpt_old = adapter->stats.tpt;
5331 	mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5332 	adapter->colc_old = adapter->stats.colc;
5333 
5334 	adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5335 	adapter->gorc_old = adapter->stats.gorc;
5336 	adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5337 	adapter->gotc_old = adapter->stats.gotc;
5338 	spin_unlock(&adapter->stats64_lock);
5339 
5340 	/* If reset is necessary, do it outside of interrupt context. */
5341 	if (adapter->flags & FLAG_RESTART_NOW) {
5342 		schedule_work(&adapter->reset_task);
5343 		/* return immediately since reset is imminent */
5344 		return;
5345 	}
5346 
5347 	e1000e_update_adaptive(&adapter->hw);
5348 
5349 	/* Simple mode for Interrupt Throttle Rate (ITR) */
5350 	if (adapter->itr_setting == 4) {
5351 		/* Symmetric Tx/Rx gets a reduced ITR=2000;
5352 		 * Total asymmetrical Tx or Rx gets ITR=8000;
5353 		 * everyone else is between 2000-8000.
5354 		 */
5355 		u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5356 		u32 dif = (adapter->gotc > adapter->gorc ?
5357 			   adapter->gotc - adapter->gorc :
5358 			   adapter->gorc - adapter->gotc) / 10000;
5359 		u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5360 
5361 		e1000e_write_itr(adapter, itr);
5362 	}
5363 
5364 	/* Cause software interrupt to ensure Rx ring is cleaned */
5365 	if (adapter->msix_entries)
5366 		ew32(ICS, adapter->rx_ring->ims_val);
5367 	else
5368 		ew32(ICS, E1000_ICS_RXDMT0);
5369 
5370 	/* flush pending descriptors to memory before detecting Tx hang */
5371 	e1000e_flush_descriptors(adapter);
5372 
5373 	/* Force detection of hung controller every watchdog period */
5374 	adapter->detect_tx_hung = true;
5375 
5376 	/* With 82571 controllers, LAA may be overwritten due to controller
5377 	 * reset from the other port. Set the appropriate LAA in RAR[0]
5378 	 */
5379 	if (e1000e_get_laa_state_82571(hw))
5380 		hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5381 
5382 	if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5383 		e1000e_check_82574_phy_workaround(adapter);
5384 
5385 	/* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5386 	if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5387 		if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5388 		    (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5389 			er32(RXSTMPH);
5390 			adapter->rx_hwtstamp_cleared++;
5391 		} else {
5392 			adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5393 		}
5394 	}
5395 
5396 	/* Reset the timer */
5397 	if (!test_bit(__E1000_DOWN, &adapter->state))
5398 		mod_timer(&adapter->watchdog_timer,
5399 			  round_jiffies(jiffies + 2 * HZ));
5400 }
5401 
5402 #define E1000_TX_FLAGS_CSUM		0x00000001
5403 #define E1000_TX_FLAGS_VLAN		0x00000002
5404 #define E1000_TX_FLAGS_TSO		0x00000004
5405 #define E1000_TX_FLAGS_IPV4		0x00000008
5406 #define E1000_TX_FLAGS_NO_FCS		0x00000010
5407 #define E1000_TX_FLAGS_HWTSTAMP		0x00000020
5408 #define E1000_TX_FLAGS_VLAN_MASK	0xffff0000
5409 #define E1000_TX_FLAGS_VLAN_SHIFT	16
5410 
5411 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5412 		     __be16 protocol)
5413 {
5414 	struct e1000_context_desc *context_desc;
5415 	struct e1000_buffer *buffer_info;
5416 	unsigned int i;
5417 	u32 cmd_length = 0;
5418 	u16 ipcse = 0, mss;
5419 	u8 ipcss, ipcso, tucss, tucso, hdr_len;
5420 	int err;
5421 
5422 	if (!skb_is_gso(skb))
5423 		return 0;
5424 
5425 	err = skb_cow_head(skb, 0);
5426 	if (err < 0)
5427 		return err;
5428 
5429 	hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5430 	mss = skb_shinfo(skb)->gso_size;
5431 	if (protocol == htons(ETH_P_IP)) {
5432 		struct iphdr *iph = ip_hdr(skb);
5433 		iph->tot_len = 0;
5434 		iph->check = 0;
5435 		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5436 							 0, IPPROTO_TCP, 0);
5437 		cmd_length = E1000_TXD_CMD_IP;
5438 		ipcse = skb_transport_offset(skb) - 1;
5439 	} else if (skb_is_gso_v6(skb)) {
5440 		ipv6_hdr(skb)->payload_len = 0;
5441 		tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5442 						       &ipv6_hdr(skb)->daddr,
5443 						       0, IPPROTO_TCP, 0);
5444 		ipcse = 0;
5445 	}
5446 	ipcss = skb_network_offset(skb);
5447 	ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5448 	tucss = skb_transport_offset(skb);
5449 	tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5450 
5451 	cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5452 		       E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5453 
5454 	i = tx_ring->next_to_use;
5455 	context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5456 	buffer_info = &tx_ring->buffer_info[i];
5457 
5458 	context_desc->lower_setup.ip_fields.ipcss = ipcss;
5459 	context_desc->lower_setup.ip_fields.ipcso = ipcso;
5460 	context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5461 	context_desc->upper_setup.tcp_fields.tucss = tucss;
5462 	context_desc->upper_setup.tcp_fields.tucso = tucso;
5463 	context_desc->upper_setup.tcp_fields.tucse = 0;
5464 	context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5465 	context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5466 	context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5467 
5468 	buffer_info->time_stamp = jiffies;
5469 	buffer_info->next_to_watch = i;
5470 
5471 	i++;
5472 	if (i == tx_ring->count)
5473 		i = 0;
5474 	tx_ring->next_to_use = i;
5475 
5476 	return 1;
5477 }
5478 
5479 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5480 			  __be16 protocol)
5481 {
5482 	struct e1000_adapter *adapter = tx_ring->adapter;
5483 	struct e1000_context_desc *context_desc;
5484 	struct e1000_buffer *buffer_info;
5485 	unsigned int i;
5486 	u8 css;
5487 	u32 cmd_len = E1000_TXD_CMD_DEXT;
5488 
5489 	if (skb->ip_summed != CHECKSUM_PARTIAL)
5490 		return false;
5491 
5492 	switch (protocol) {
5493 	case cpu_to_be16(ETH_P_IP):
5494 		if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5495 			cmd_len |= E1000_TXD_CMD_TCP;
5496 		break;
5497 	case cpu_to_be16(ETH_P_IPV6):
5498 		/* XXX not handling all IPV6 headers */
5499 		if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5500 			cmd_len |= E1000_TXD_CMD_TCP;
5501 		break;
5502 	default:
5503 		if (unlikely(net_ratelimit()))
5504 			e_warn("checksum_partial proto=%x!\n",
5505 			       be16_to_cpu(protocol));
5506 		break;
5507 	}
5508 
5509 	css = skb_checksum_start_offset(skb);
5510 
5511 	i = tx_ring->next_to_use;
5512 	buffer_info = &tx_ring->buffer_info[i];
5513 	context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5514 
5515 	context_desc->lower_setup.ip_config = 0;
5516 	context_desc->upper_setup.tcp_fields.tucss = css;
5517 	context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5518 	context_desc->upper_setup.tcp_fields.tucse = 0;
5519 	context_desc->tcp_seg_setup.data = 0;
5520 	context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5521 
5522 	buffer_info->time_stamp = jiffies;
5523 	buffer_info->next_to_watch = i;
5524 
5525 	i++;
5526 	if (i == tx_ring->count)
5527 		i = 0;
5528 	tx_ring->next_to_use = i;
5529 
5530 	return true;
5531 }
5532 
5533 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5534 			unsigned int first, unsigned int max_per_txd,
5535 			unsigned int nr_frags)
5536 {
5537 	struct e1000_adapter *adapter = tx_ring->adapter;
5538 	struct pci_dev *pdev = adapter->pdev;
5539 	struct e1000_buffer *buffer_info;
5540 	unsigned int len = skb_headlen(skb);
5541 	unsigned int offset = 0, size, count = 0, i;
5542 	unsigned int f, bytecount, segs;
5543 
5544 	i = tx_ring->next_to_use;
5545 
5546 	while (len) {
5547 		buffer_info = &tx_ring->buffer_info[i];
5548 		size = min(len, max_per_txd);
5549 
5550 		buffer_info->length = size;
5551 		buffer_info->time_stamp = jiffies;
5552 		buffer_info->next_to_watch = i;
5553 		buffer_info->dma = dma_map_single(&pdev->dev,
5554 						  skb->data + offset,
5555 						  size, DMA_TO_DEVICE);
5556 		buffer_info->mapped_as_page = false;
5557 		if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5558 			goto dma_error;
5559 
5560 		len -= size;
5561 		offset += size;
5562 		count++;
5563 
5564 		if (len) {
5565 			i++;
5566 			if (i == tx_ring->count)
5567 				i = 0;
5568 		}
5569 	}
5570 
5571 	for (f = 0; f < nr_frags; f++) {
5572 		const struct skb_frag_struct *frag;
5573 
5574 		frag = &skb_shinfo(skb)->frags[f];
5575 		len = skb_frag_size(frag);
5576 		offset = 0;
5577 
5578 		while (len) {
5579 			i++;
5580 			if (i == tx_ring->count)
5581 				i = 0;
5582 
5583 			buffer_info = &tx_ring->buffer_info[i];
5584 			size = min(len, max_per_txd);
5585 
5586 			buffer_info->length = size;
5587 			buffer_info->time_stamp = jiffies;
5588 			buffer_info->next_to_watch = i;
5589 			buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5590 							    offset, size,
5591 							    DMA_TO_DEVICE);
5592 			buffer_info->mapped_as_page = true;
5593 			if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5594 				goto dma_error;
5595 
5596 			len -= size;
5597 			offset += size;
5598 			count++;
5599 		}
5600 	}
5601 
5602 	segs = skb_shinfo(skb)->gso_segs ? : 1;
5603 	/* multiply data chunks by size of headers */
5604 	bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5605 
5606 	tx_ring->buffer_info[i].skb = skb;
5607 	tx_ring->buffer_info[i].segs = segs;
5608 	tx_ring->buffer_info[i].bytecount = bytecount;
5609 	tx_ring->buffer_info[first].next_to_watch = i;
5610 
5611 	return count;
5612 
5613 dma_error:
5614 	dev_err(&pdev->dev, "Tx DMA map failed\n");
5615 	buffer_info->dma = 0;
5616 	if (count)
5617 		count--;
5618 
5619 	while (count--) {
5620 		if (i == 0)
5621 			i += tx_ring->count;
5622 		i--;
5623 		buffer_info = &tx_ring->buffer_info[i];
5624 		e1000_put_txbuf(tx_ring, buffer_info, true);
5625 	}
5626 
5627 	return 0;
5628 }
5629 
5630 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5631 {
5632 	struct e1000_adapter *adapter = tx_ring->adapter;
5633 	struct e1000_tx_desc *tx_desc = NULL;
5634 	struct e1000_buffer *buffer_info;
5635 	u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5636 	unsigned int i;
5637 
5638 	if (tx_flags & E1000_TX_FLAGS_TSO) {
5639 		txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5640 		    E1000_TXD_CMD_TSE;
5641 		txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5642 
5643 		if (tx_flags & E1000_TX_FLAGS_IPV4)
5644 			txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5645 	}
5646 
5647 	if (tx_flags & E1000_TX_FLAGS_CSUM) {
5648 		txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5649 		txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5650 	}
5651 
5652 	if (tx_flags & E1000_TX_FLAGS_VLAN) {
5653 		txd_lower |= E1000_TXD_CMD_VLE;
5654 		txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5655 	}
5656 
5657 	if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5658 		txd_lower &= ~(E1000_TXD_CMD_IFCS);
5659 
5660 	if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5661 		txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5662 		txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5663 	}
5664 
5665 	i = tx_ring->next_to_use;
5666 
5667 	do {
5668 		buffer_info = &tx_ring->buffer_info[i];
5669 		tx_desc = E1000_TX_DESC(*tx_ring, i);
5670 		tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5671 		tx_desc->lower.data = cpu_to_le32(txd_lower |
5672 						  buffer_info->length);
5673 		tx_desc->upper.data = cpu_to_le32(txd_upper);
5674 
5675 		i++;
5676 		if (i == tx_ring->count)
5677 			i = 0;
5678 	} while (--count > 0);
5679 
5680 	tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5681 
5682 	/* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5683 	if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5684 		tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5685 
5686 	/* Force memory writes to complete before letting h/w
5687 	 * know there are new descriptors to fetch.  (Only
5688 	 * applicable for weak-ordered memory model archs,
5689 	 * such as IA-64).
5690 	 */
5691 	wmb();
5692 
5693 	tx_ring->next_to_use = i;
5694 }
5695 
5696 #define MINIMUM_DHCP_PACKET_SIZE 282
5697 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5698 				    struct sk_buff *skb)
5699 {
5700 	struct e1000_hw *hw = &adapter->hw;
5701 	u16 length, offset;
5702 
5703 	if (skb_vlan_tag_present(skb) &&
5704 	    !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5705 	      (adapter->hw.mng_cookie.status &
5706 	       E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5707 		return 0;
5708 
5709 	if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5710 		return 0;
5711 
5712 	if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5713 		return 0;
5714 
5715 	{
5716 		const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5717 		struct udphdr *udp;
5718 
5719 		if (ip->protocol != IPPROTO_UDP)
5720 			return 0;
5721 
5722 		udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5723 		if (ntohs(udp->dest) != 67)
5724 			return 0;
5725 
5726 		offset = (u8 *)udp + 8 - skb->data;
5727 		length = skb->len - offset;
5728 		return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5729 	}
5730 
5731 	return 0;
5732 }
5733 
5734 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5735 {
5736 	struct e1000_adapter *adapter = tx_ring->adapter;
5737 
5738 	netif_stop_queue(adapter->netdev);
5739 	/* Herbert's original patch had:
5740 	 *  smp_mb__after_netif_stop_queue();
5741 	 * but since that doesn't exist yet, just open code it.
5742 	 */
5743 	smp_mb();
5744 
5745 	/* We need to check again in a case another CPU has just
5746 	 * made room available.
5747 	 */
5748 	if (e1000_desc_unused(tx_ring) < size)
5749 		return -EBUSY;
5750 
5751 	/* A reprieve! */
5752 	netif_start_queue(adapter->netdev);
5753 	++adapter->restart_queue;
5754 	return 0;
5755 }
5756 
5757 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5758 {
5759 	BUG_ON(size > tx_ring->count);
5760 
5761 	if (e1000_desc_unused(tx_ring) >= size)
5762 		return 0;
5763 	return __e1000_maybe_stop_tx(tx_ring, size);
5764 }
5765 
5766 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5767 				    struct net_device *netdev)
5768 {
5769 	struct e1000_adapter *adapter = netdev_priv(netdev);
5770 	struct e1000_ring *tx_ring = adapter->tx_ring;
5771 	unsigned int first;
5772 	unsigned int tx_flags = 0;
5773 	unsigned int len = skb_headlen(skb);
5774 	unsigned int nr_frags;
5775 	unsigned int mss;
5776 	int count = 0;
5777 	int tso;
5778 	unsigned int f;
5779 	__be16 protocol = vlan_get_protocol(skb);
5780 
5781 	if (test_bit(__E1000_DOWN, &adapter->state)) {
5782 		dev_kfree_skb_any(skb);
5783 		return NETDEV_TX_OK;
5784 	}
5785 
5786 	if (skb->len <= 0) {
5787 		dev_kfree_skb_any(skb);
5788 		return NETDEV_TX_OK;
5789 	}
5790 
5791 	/* The minimum packet size with TCTL.PSP set is 17 bytes so
5792 	 * pad skb in order to meet this minimum size requirement
5793 	 */
5794 	if (skb_put_padto(skb, 17))
5795 		return NETDEV_TX_OK;
5796 
5797 	mss = skb_shinfo(skb)->gso_size;
5798 	if (mss) {
5799 		u8 hdr_len;
5800 
5801 		/* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5802 		 * points to just header, pull a few bytes of payload from
5803 		 * frags into skb->data
5804 		 */
5805 		hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5806 		/* we do this workaround for ES2LAN, but it is un-necessary,
5807 		 * avoiding it could save a lot of cycles
5808 		 */
5809 		if (skb->data_len && (hdr_len == len)) {
5810 			unsigned int pull_size;
5811 
5812 			pull_size = min_t(unsigned int, 4, skb->data_len);
5813 			if (!__pskb_pull_tail(skb, pull_size)) {
5814 				e_err("__pskb_pull_tail failed.\n");
5815 				dev_kfree_skb_any(skb);
5816 				return NETDEV_TX_OK;
5817 			}
5818 			len = skb_headlen(skb);
5819 		}
5820 	}
5821 
5822 	/* reserve a descriptor for the offload context */
5823 	if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5824 		count++;
5825 	count++;
5826 
5827 	count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5828 
5829 	nr_frags = skb_shinfo(skb)->nr_frags;
5830 	for (f = 0; f < nr_frags; f++)
5831 		count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5832 				      adapter->tx_fifo_limit);
5833 
5834 	if (adapter->hw.mac.tx_pkt_filtering)
5835 		e1000_transfer_dhcp_info(adapter, skb);
5836 
5837 	/* need: count + 2 desc gap to keep tail from touching
5838 	 * head, otherwise try next time
5839 	 */
5840 	if (e1000_maybe_stop_tx(tx_ring, count + 2))
5841 		return NETDEV_TX_BUSY;
5842 
5843 	if (skb_vlan_tag_present(skb)) {
5844 		tx_flags |= E1000_TX_FLAGS_VLAN;
5845 		tx_flags |= (skb_vlan_tag_get(skb) <<
5846 			     E1000_TX_FLAGS_VLAN_SHIFT);
5847 	}
5848 
5849 	first = tx_ring->next_to_use;
5850 
5851 	tso = e1000_tso(tx_ring, skb, protocol);
5852 	if (tso < 0) {
5853 		dev_kfree_skb_any(skb);
5854 		return NETDEV_TX_OK;
5855 	}
5856 
5857 	if (tso)
5858 		tx_flags |= E1000_TX_FLAGS_TSO;
5859 	else if (e1000_tx_csum(tx_ring, skb, protocol))
5860 		tx_flags |= E1000_TX_FLAGS_CSUM;
5861 
5862 	/* Old method was to assume IPv4 packet by default if TSO was enabled.
5863 	 * 82571 hardware supports TSO capabilities for IPv6 as well...
5864 	 * no longer assume, we must.
5865 	 */
5866 	if (protocol == htons(ETH_P_IP))
5867 		tx_flags |= E1000_TX_FLAGS_IPV4;
5868 
5869 	if (unlikely(skb->no_fcs))
5870 		tx_flags |= E1000_TX_FLAGS_NO_FCS;
5871 
5872 	/* if count is 0 then mapping error has occurred */
5873 	count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5874 			     nr_frags);
5875 	if (count) {
5876 		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5877 		    (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5878 			if (!adapter->tx_hwtstamp_skb) {
5879 				skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5880 				tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5881 				adapter->tx_hwtstamp_skb = skb_get(skb);
5882 				adapter->tx_hwtstamp_start = jiffies;
5883 				schedule_work(&adapter->tx_hwtstamp_work);
5884 			} else {
5885 				adapter->tx_hwtstamp_skipped++;
5886 			}
5887 		}
5888 
5889 		skb_tx_timestamp(skb);
5890 
5891 		netdev_sent_queue(netdev, skb->len);
5892 		e1000_tx_queue(tx_ring, tx_flags, count);
5893 		/* Make sure there is space in the ring for the next send. */
5894 		e1000_maybe_stop_tx(tx_ring,
5895 				    (MAX_SKB_FRAGS *
5896 				     DIV_ROUND_UP(PAGE_SIZE,
5897 						  adapter->tx_fifo_limit) + 2));
5898 
5899 		if (!netdev_xmit_more() ||
5900 		    netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5901 			if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5902 				e1000e_update_tdt_wa(tx_ring,
5903 						     tx_ring->next_to_use);
5904 			else
5905 				writel(tx_ring->next_to_use, tx_ring->tail);
5906 		}
5907 	} else {
5908 		dev_kfree_skb_any(skb);
5909 		tx_ring->buffer_info[first].time_stamp = 0;
5910 		tx_ring->next_to_use = first;
5911 	}
5912 
5913 	return NETDEV_TX_OK;
5914 }
5915 
5916 /**
5917  * e1000_tx_timeout - Respond to a Tx Hang
5918  * @netdev: network interface device structure
5919  **/
5920 static void e1000_tx_timeout(struct net_device *netdev)
5921 {
5922 	struct e1000_adapter *adapter = netdev_priv(netdev);
5923 
5924 	/* Do the reset outside of interrupt context */
5925 	adapter->tx_timeout_count++;
5926 	schedule_work(&adapter->reset_task);
5927 }
5928 
5929 static void e1000_reset_task(struct work_struct *work)
5930 {
5931 	struct e1000_adapter *adapter;
5932 	adapter = container_of(work, struct e1000_adapter, reset_task);
5933 
5934 	/* don't run the task if already down */
5935 	if (test_bit(__E1000_DOWN, &adapter->state))
5936 		return;
5937 
5938 	if (!(adapter->flags & FLAG_RESTART_NOW)) {
5939 		e1000e_dump(adapter);
5940 		e_err("Reset adapter unexpectedly\n");
5941 	}
5942 	e1000e_reinit_locked(adapter);
5943 }
5944 
5945 /**
5946  * e1000_get_stats64 - Get System Network Statistics
5947  * @netdev: network interface device structure
5948  * @stats: rtnl_link_stats64 pointer
5949  *
5950  * Returns the address of the device statistics structure.
5951  **/
5952 void e1000e_get_stats64(struct net_device *netdev,
5953 			struct rtnl_link_stats64 *stats)
5954 {
5955 	struct e1000_adapter *adapter = netdev_priv(netdev);
5956 
5957 	spin_lock(&adapter->stats64_lock);
5958 	e1000e_update_stats(adapter);
5959 	/* Fill out the OS statistics structure */
5960 	stats->rx_bytes = adapter->stats.gorc;
5961 	stats->rx_packets = adapter->stats.gprc;
5962 	stats->tx_bytes = adapter->stats.gotc;
5963 	stats->tx_packets = adapter->stats.gptc;
5964 	stats->multicast = adapter->stats.mprc;
5965 	stats->collisions = adapter->stats.colc;
5966 
5967 	/* Rx Errors */
5968 
5969 	/* RLEC on some newer hardware can be incorrect so build
5970 	 * our own version based on RUC and ROC
5971 	 */
5972 	stats->rx_errors = adapter->stats.rxerrc +
5973 	    adapter->stats.crcerrs + adapter->stats.algnerrc +
5974 	    adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5975 	stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5976 	stats->rx_crc_errors = adapter->stats.crcerrs;
5977 	stats->rx_frame_errors = adapter->stats.algnerrc;
5978 	stats->rx_missed_errors = adapter->stats.mpc;
5979 
5980 	/* Tx Errors */
5981 	stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5982 	stats->tx_aborted_errors = adapter->stats.ecol;
5983 	stats->tx_window_errors = adapter->stats.latecol;
5984 	stats->tx_carrier_errors = adapter->stats.tncrs;
5985 
5986 	/* Tx Dropped needs to be maintained elsewhere */
5987 
5988 	spin_unlock(&adapter->stats64_lock);
5989 }
5990 
5991 /**
5992  * e1000_change_mtu - Change the Maximum Transfer Unit
5993  * @netdev: network interface device structure
5994  * @new_mtu: new value for maximum frame size
5995  *
5996  * Returns 0 on success, negative on failure
5997  **/
5998 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5999 {
6000 	struct e1000_adapter *adapter = netdev_priv(netdev);
6001 	int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6002 
6003 	/* Jumbo frame support */
6004 	if ((new_mtu > ETH_DATA_LEN) &&
6005 	    !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6006 		e_err("Jumbo Frames not supported.\n");
6007 		return -EINVAL;
6008 	}
6009 
6010 	/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6011 	if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6012 	    !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6013 	    (new_mtu > ETH_DATA_LEN)) {
6014 		e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6015 		return -EINVAL;
6016 	}
6017 
6018 	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6019 		usleep_range(1000, 2000);
6020 	/* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6021 	adapter->max_frame_size = max_frame;
6022 	e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6023 	netdev->mtu = new_mtu;
6024 
6025 	pm_runtime_get_sync(netdev->dev.parent);
6026 
6027 	if (netif_running(netdev))
6028 		e1000e_down(adapter, true);
6029 
6030 	/* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6031 	 * means we reserve 2 more, this pushes us to allocate from the next
6032 	 * larger slab size.
6033 	 * i.e. RXBUFFER_2048 --> size-4096 slab
6034 	 * However with the new *_jumbo_rx* routines, jumbo receives will use
6035 	 * fragmented skbs
6036 	 */
6037 
6038 	if (max_frame <= 2048)
6039 		adapter->rx_buffer_len = 2048;
6040 	else
6041 		adapter->rx_buffer_len = 4096;
6042 
6043 	/* adjust allocation if LPE protects us, and we aren't using SBP */
6044 	if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6045 		adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6046 
6047 	if (netif_running(netdev))
6048 		e1000e_up(adapter);
6049 	else
6050 		e1000e_reset(adapter);
6051 
6052 	pm_runtime_put_sync(netdev->dev.parent);
6053 
6054 	clear_bit(__E1000_RESETTING, &adapter->state);
6055 
6056 	return 0;
6057 }
6058 
6059 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6060 			   int cmd)
6061 {
6062 	struct e1000_adapter *adapter = netdev_priv(netdev);
6063 	struct mii_ioctl_data *data = if_mii(ifr);
6064 
6065 	if (adapter->hw.phy.media_type != e1000_media_type_copper)
6066 		return -EOPNOTSUPP;
6067 
6068 	switch (cmd) {
6069 	case SIOCGMIIPHY:
6070 		data->phy_id = adapter->hw.phy.addr;
6071 		break;
6072 	case SIOCGMIIREG:
6073 		e1000_phy_read_status(adapter);
6074 
6075 		switch (data->reg_num & 0x1F) {
6076 		case MII_BMCR:
6077 			data->val_out = adapter->phy_regs.bmcr;
6078 			break;
6079 		case MII_BMSR:
6080 			data->val_out = adapter->phy_regs.bmsr;
6081 			break;
6082 		case MII_PHYSID1:
6083 			data->val_out = (adapter->hw.phy.id >> 16);
6084 			break;
6085 		case MII_PHYSID2:
6086 			data->val_out = (adapter->hw.phy.id & 0xFFFF);
6087 			break;
6088 		case MII_ADVERTISE:
6089 			data->val_out = adapter->phy_regs.advertise;
6090 			break;
6091 		case MII_LPA:
6092 			data->val_out = adapter->phy_regs.lpa;
6093 			break;
6094 		case MII_EXPANSION:
6095 			data->val_out = adapter->phy_regs.expansion;
6096 			break;
6097 		case MII_CTRL1000:
6098 			data->val_out = adapter->phy_regs.ctrl1000;
6099 			break;
6100 		case MII_STAT1000:
6101 			data->val_out = adapter->phy_regs.stat1000;
6102 			break;
6103 		case MII_ESTATUS:
6104 			data->val_out = adapter->phy_regs.estatus;
6105 			break;
6106 		default:
6107 			return -EIO;
6108 		}
6109 		break;
6110 	case SIOCSMIIREG:
6111 	default:
6112 		return -EOPNOTSUPP;
6113 	}
6114 	return 0;
6115 }
6116 
6117 /**
6118  * e1000e_hwtstamp_ioctl - control hardware time stamping
6119  * @netdev: network interface device structure
6120  * @ifreq: interface request
6121  *
6122  * Outgoing time stamping can be enabled and disabled. Play nice and
6123  * disable it when requested, although it shouldn't cause any overhead
6124  * when no packet needs it. At most one packet in the queue may be
6125  * marked for time stamping, otherwise it would be impossible to tell
6126  * for sure to which packet the hardware time stamp belongs.
6127  *
6128  * Incoming time stamping has to be configured via the hardware filters.
6129  * Not all combinations are supported, in particular event type has to be
6130  * specified. Matching the kind of event packet is not supported, with the
6131  * exception of "all V2 events regardless of level 2 or 4".
6132  **/
6133 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6134 {
6135 	struct e1000_adapter *adapter = netdev_priv(netdev);
6136 	struct hwtstamp_config config;
6137 	int ret_val;
6138 
6139 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6140 		return -EFAULT;
6141 
6142 	ret_val = e1000e_config_hwtstamp(adapter, &config);
6143 	if (ret_val)
6144 		return ret_val;
6145 
6146 	switch (config.rx_filter) {
6147 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6148 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6149 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
6150 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6151 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6152 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6153 		/* With V2 type filters which specify a Sync or Delay Request,
6154 		 * Path Delay Request/Response messages are also time stamped
6155 		 * by hardware so notify the caller the requested packets plus
6156 		 * some others are time stamped.
6157 		 */
6158 		config.rx_filter = HWTSTAMP_FILTER_SOME;
6159 		break;
6160 	default:
6161 		break;
6162 	}
6163 
6164 	return copy_to_user(ifr->ifr_data, &config,
6165 			    sizeof(config)) ? -EFAULT : 0;
6166 }
6167 
6168 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6169 {
6170 	struct e1000_adapter *adapter = netdev_priv(netdev);
6171 
6172 	return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6173 			    sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6174 }
6175 
6176 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6177 {
6178 	switch (cmd) {
6179 	case SIOCGMIIPHY:
6180 	case SIOCGMIIREG:
6181 	case SIOCSMIIREG:
6182 		return e1000_mii_ioctl(netdev, ifr, cmd);
6183 	case SIOCSHWTSTAMP:
6184 		return e1000e_hwtstamp_set(netdev, ifr);
6185 	case SIOCGHWTSTAMP:
6186 		return e1000e_hwtstamp_get(netdev, ifr);
6187 	default:
6188 		return -EOPNOTSUPP;
6189 	}
6190 }
6191 
6192 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6193 {
6194 	struct e1000_hw *hw = &adapter->hw;
6195 	u32 i, mac_reg, wuc;
6196 	u16 phy_reg, wuc_enable;
6197 	int retval;
6198 
6199 	/* copy MAC RARs to PHY RARs */
6200 	e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6201 
6202 	retval = hw->phy.ops.acquire(hw);
6203 	if (retval) {
6204 		e_err("Could not acquire PHY\n");
6205 		return retval;
6206 	}
6207 
6208 	/* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6209 	retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6210 	if (retval)
6211 		goto release;
6212 
6213 	/* copy MAC MTA to PHY MTA - only needed for pchlan */
6214 	for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6215 		mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6216 		hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6217 					   (u16)(mac_reg & 0xFFFF));
6218 		hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6219 					   (u16)((mac_reg >> 16) & 0xFFFF));
6220 	}
6221 
6222 	/* configure PHY Rx Control register */
6223 	hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6224 	mac_reg = er32(RCTL);
6225 	if (mac_reg & E1000_RCTL_UPE)
6226 		phy_reg |= BM_RCTL_UPE;
6227 	if (mac_reg & E1000_RCTL_MPE)
6228 		phy_reg |= BM_RCTL_MPE;
6229 	phy_reg &= ~(BM_RCTL_MO_MASK);
6230 	if (mac_reg & E1000_RCTL_MO_3)
6231 		phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6232 			    << BM_RCTL_MO_SHIFT);
6233 	if (mac_reg & E1000_RCTL_BAM)
6234 		phy_reg |= BM_RCTL_BAM;
6235 	if (mac_reg & E1000_RCTL_PMCF)
6236 		phy_reg |= BM_RCTL_PMCF;
6237 	mac_reg = er32(CTRL);
6238 	if (mac_reg & E1000_CTRL_RFCE)
6239 		phy_reg |= BM_RCTL_RFCE;
6240 	hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6241 
6242 	wuc = E1000_WUC_PME_EN;
6243 	if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6244 		wuc |= E1000_WUC_APME;
6245 
6246 	/* enable PHY wakeup in MAC register */
6247 	ew32(WUFC, wufc);
6248 	ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6249 		   E1000_WUC_PME_STATUS | wuc));
6250 
6251 	/* configure and enable PHY wakeup in PHY registers */
6252 	hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6253 	hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6254 
6255 	/* activate PHY wakeup */
6256 	wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6257 	retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6258 	if (retval)
6259 		e_err("Could not set PHY Host Wakeup bit\n");
6260 release:
6261 	hw->phy.ops.release(hw);
6262 
6263 	return retval;
6264 }
6265 
6266 static void e1000e_flush_lpic(struct pci_dev *pdev)
6267 {
6268 	struct net_device *netdev = pci_get_drvdata(pdev);
6269 	struct e1000_adapter *adapter = netdev_priv(netdev);
6270 	struct e1000_hw *hw = &adapter->hw;
6271 	u32 ret_val;
6272 
6273 	pm_runtime_get_sync(netdev->dev.parent);
6274 
6275 	ret_val = hw->phy.ops.acquire(hw);
6276 	if (ret_val)
6277 		goto fl_out;
6278 
6279 	pr_info("EEE TX LPI TIMER: %08X\n",
6280 		er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6281 
6282 	hw->phy.ops.release(hw);
6283 
6284 fl_out:
6285 	pm_runtime_put_sync(netdev->dev.parent);
6286 }
6287 
6288 static int e1000e_pm_freeze(struct device *dev)
6289 {
6290 	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6291 	struct e1000_adapter *adapter = netdev_priv(netdev);
6292 
6293 	netif_device_detach(netdev);
6294 
6295 	if (netif_running(netdev)) {
6296 		int count = E1000_CHECK_RESET_COUNT;
6297 
6298 		while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6299 			usleep_range(10000, 20000);
6300 
6301 		WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6302 
6303 		/* Quiesce the device without resetting the hardware */
6304 		e1000e_down(adapter, false);
6305 		e1000_free_irq(adapter);
6306 	}
6307 	e1000e_reset_interrupt_capability(adapter);
6308 
6309 	/* Allow time for pending master requests to run */
6310 	e1000e_disable_pcie_master(&adapter->hw);
6311 
6312 	return 0;
6313 }
6314 
6315 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6316 {
6317 	struct net_device *netdev = pci_get_drvdata(pdev);
6318 	struct e1000_adapter *adapter = netdev_priv(netdev);
6319 	struct e1000_hw *hw = &adapter->hw;
6320 	u32 ctrl, ctrl_ext, rctl, status;
6321 	/* Runtime suspend should only enable wakeup for link changes */
6322 	u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6323 	int retval = 0;
6324 
6325 	status = er32(STATUS);
6326 	if (status & E1000_STATUS_LU)
6327 		wufc &= ~E1000_WUFC_LNKC;
6328 
6329 	if (wufc) {
6330 		e1000_setup_rctl(adapter);
6331 		e1000e_set_rx_mode(netdev);
6332 
6333 		/* turn on all-multi mode if wake on multicast is enabled */
6334 		if (wufc & E1000_WUFC_MC) {
6335 			rctl = er32(RCTL);
6336 			rctl |= E1000_RCTL_MPE;
6337 			ew32(RCTL, rctl);
6338 		}
6339 
6340 		ctrl = er32(CTRL);
6341 		ctrl |= E1000_CTRL_ADVD3WUC;
6342 		if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6343 			ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6344 		ew32(CTRL, ctrl);
6345 
6346 		if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6347 		    adapter->hw.phy.media_type ==
6348 		    e1000_media_type_internal_serdes) {
6349 			/* keep the laser running in D3 */
6350 			ctrl_ext = er32(CTRL_EXT);
6351 			ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6352 			ew32(CTRL_EXT, ctrl_ext);
6353 		}
6354 
6355 		if (!runtime)
6356 			e1000e_power_up_phy(adapter);
6357 
6358 		if (adapter->flags & FLAG_IS_ICH)
6359 			e1000_suspend_workarounds_ich8lan(&adapter->hw);
6360 
6361 		if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6362 			/* enable wakeup by the PHY */
6363 			retval = e1000_init_phy_wakeup(adapter, wufc);
6364 			if (retval)
6365 				return retval;
6366 		} else {
6367 			/* enable wakeup by the MAC */
6368 			ew32(WUFC, wufc);
6369 			ew32(WUC, E1000_WUC_PME_EN);
6370 		}
6371 	} else {
6372 		ew32(WUC, 0);
6373 		ew32(WUFC, 0);
6374 
6375 		e1000_power_down_phy(adapter);
6376 	}
6377 
6378 	if (adapter->hw.phy.type == e1000_phy_igp_3) {
6379 		e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6380 	} else if (hw->mac.type >= e1000_pch_lpt) {
6381 		if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6382 			/* ULP does not support wake from unicast, multicast
6383 			 * or broadcast.
6384 			 */
6385 			retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6386 
6387 		if (retval)
6388 			return retval;
6389 	}
6390 
6391 	/* Ensure that the appropriate bits are set in LPI_CTRL
6392 	 * for EEE in Sx
6393 	 */
6394 	if ((hw->phy.type >= e1000_phy_i217) &&
6395 	    adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6396 		u16 lpi_ctrl = 0;
6397 
6398 		retval = hw->phy.ops.acquire(hw);
6399 		if (!retval) {
6400 			retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6401 						 &lpi_ctrl);
6402 			if (!retval) {
6403 				if (adapter->eee_advert &
6404 				    hw->dev_spec.ich8lan.eee_lp_ability &
6405 				    I82579_EEE_100_SUPPORTED)
6406 					lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6407 				if (adapter->eee_advert &
6408 				    hw->dev_spec.ich8lan.eee_lp_ability &
6409 				    I82579_EEE_1000_SUPPORTED)
6410 					lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6411 
6412 				retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6413 							 lpi_ctrl);
6414 			}
6415 		}
6416 		hw->phy.ops.release(hw);
6417 	}
6418 
6419 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
6420 	 * would have already happened in close and is redundant.
6421 	 */
6422 	e1000e_release_hw_control(adapter);
6423 
6424 	pci_clear_master(pdev);
6425 
6426 	/* The pci-e switch on some quad port adapters will report a
6427 	 * correctable error when the MAC transitions from D0 to D3.  To
6428 	 * prevent this we need to mask off the correctable errors on the
6429 	 * downstream port of the pci-e switch.
6430 	 *
6431 	 * We don't have the associated upstream bridge while assigning
6432 	 * the PCI device into guest. For example, the KVM on power is
6433 	 * one of the cases.
6434 	 */
6435 	if (adapter->flags & FLAG_IS_QUAD_PORT) {
6436 		struct pci_dev *us_dev = pdev->bus->self;
6437 		u16 devctl;
6438 
6439 		if (!us_dev)
6440 			return 0;
6441 
6442 		pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6443 		pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6444 					   (devctl & ~PCI_EXP_DEVCTL_CERE));
6445 
6446 		pci_save_state(pdev);
6447 		pci_prepare_to_sleep(pdev);
6448 
6449 		pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6450 	}
6451 
6452 	return 0;
6453 }
6454 
6455 /**
6456  * __e1000e_disable_aspm - Disable ASPM states
6457  * @pdev: pointer to PCI device struct
6458  * @state: bit-mask of ASPM states to disable
6459  * @locked: indication if this context holds pci_bus_sem locked.
6460  *
6461  * Some devices *must* have certain ASPM states disabled per hardware errata.
6462  **/
6463 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6464 {
6465 	struct pci_dev *parent = pdev->bus->self;
6466 	u16 aspm_dis_mask = 0;
6467 	u16 pdev_aspmc, parent_aspmc;
6468 
6469 	switch (state) {
6470 	case PCIE_LINK_STATE_L0S:
6471 	case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6472 		aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6473 		/* fall-through - can't have L1 without L0s */
6474 	case PCIE_LINK_STATE_L1:
6475 		aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6476 		break;
6477 	default:
6478 		return;
6479 	}
6480 
6481 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6482 	pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6483 
6484 	if (parent) {
6485 		pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6486 					  &parent_aspmc);
6487 		parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6488 	}
6489 
6490 	/* Nothing to do if the ASPM states to be disabled already are */
6491 	if (!(pdev_aspmc & aspm_dis_mask) &&
6492 	    (!parent || !(parent_aspmc & aspm_dis_mask)))
6493 		return;
6494 
6495 	dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6496 		 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6497 		 "L0s" : "",
6498 		 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6499 		 "L1" : "");
6500 
6501 #ifdef CONFIG_PCIEASPM
6502 	if (locked)
6503 		pci_disable_link_state_locked(pdev, state);
6504 	else
6505 		pci_disable_link_state(pdev, state);
6506 
6507 	/* Double-check ASPM control.  If not disabled by the above, the
6508 	 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6509 	 * not enabled); override by writing PCI config space directly.
6510 	 */
6511 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6512 	pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6513 
6514 	if (!(aspm_dis_mask & pdev_aspmc))
6515 		return;
6516 #endif
6517 
6518 	/* Both device and parent should have the same ASPM setting.
6519 	 * Disable ASPM in downstream component first and then upstream.
6520 	 */
6521 	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6522 
6523 	if (parent)
6524 		pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6525 					   aspm_dis_mask);
6526 }
6527 
6528 /**
6529  * e1000e_disable_aspm - Disable ASPM states.
6530  * @pdev: pointer to PCI device struct
6531  * @state: bit-mask of ASPM states to disable
6532  *
6533  * This function acquires the pci_bus_sem!
6534  * Some devices *must* have certain ASPM states disabled per hardware errata.
6535  **/
6536 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6537 {
6538 	__e1000e_disable_aspm(pdev, state, 0);
6539 }
6540 
6541 /**
6542  * e1000e_disable_aspm_locked   Disable ASPM states.
6543  * @pdev: pointer to PCI device struct
6544  * @state: bit-mask of ASPM states to disable
6545  *
6546  * This function must be called with pci_bus_sem acquired!
6547  * Some devices *must* have certain ASPM states disabled per hardware errata.
6548  **/
6549 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6550 {
6551 	__e1000e_disable_aspm(pdev, state, 1);
6552 }
6553 
6554 #ifdef CONFIG_PM
6555 static int __e1000_resume(struct pci_dev *pdev)
6556 {
6557 	struct net_device *netdev = pci_get_drvdata(pdev);
6558 	struct e1000_adapter *adapter = netdev_priv(netdev);
6559 	struct e1000_hw *hw = &adapter->hw;
6560 	u16 aspm_disable_flag = 0;
6561 
6562 	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6563 		aspm_disable_flag = PCIE_LINK_STATE_L0S;
6564 	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6565 		aspm_disable_flag |= PCIE_LINK_STATE_L1;
6566 	if (aspm_disable_flag)
6567 		e1000e_disable_aspm(pdev, aspm_disable_flag);
6568 
6569 	pci_set_master(pdev);
6570 
6571 	if (hw->mac.type >= e1000_pch2lan)
6572 		e1000_resume_workarounds_pchlan(&adapter->hw);
6573 
6574 	e1000e_power_up_phy(adapter);
6575 
6576 	/* report the system wakeup cause from S3/S4 */
6577 	if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6578 		u16 phy_data;
6579 
6580 		e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6581 		if (phy_data) {
6582 			e_info("PHY Wakeup cause - %s\n",
6583 			       phy_data & E1000_WUS_EX ? "Unicast Packet" :
6584 			       phy_data & E1000_WUS_MC ? "Multicast Packet" :
6585 			       phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6586 			       phy_data & E1000_WUS_MAG ? "Magic Packet" :
6587 			       phy_data & E1000_WUS_LNKC ?
6588 			       "Link Status Change" : "other");
6589 		}
6590 		e1e_wphy(&adapter->hw, BM_WUS, ~0);
6591 	} else {
6592 		u32 wus = er32(WUS);
6593 
6594 		if (wus) {
6595 			e_info("MAC Wakeup cause - %s\n",
6596 			       wus & E1000_WUS_EX ? "Unicast Packet" :
6597 			       wus & E1000_WUS_MC ? "Multicast Packet" :
6598 			       wus & E1000_WUS_BC ? "Broadcast Packet" :
6599 			       wus & E1000_WUS_MAG ? "Magic Packet" :
6600 			       wus & E1000_WUS_LNKC ? "Link Status Change" :
6601 			       "other");
6602 		}
6603 		ew32(WUS, ~0);
6604 	}
6605 
6606 	e1000e_reset(adapter);
6607 
6608 	e1000_init_manageability_pt(adapter);
6609 
6610 	/* If the controller has AMT, do not set DRV_LOAD until the interface
6611 	 * is up.  For all other cases, let the f/w know that the h/w is now
6612 	 * under the control of the driver.
6613 	 */
6614 	if (!(adapter->flags & FLAG_HAS_AMT))
6615 		e1000e_get_hw_control(adapter);
6616 
6617 	return 0;
6618 }
6619 
6620 #ifdef CONFIG_PM_SLEEP
6621 static int e1000e_pm_thaw(struct device *dev)
6622 {
6623 	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6624 	struct e1000_adapter *adapter = netdev_priv(netdev);
6625 
6626 	e1000e_set_interrupt_capability(adapter);
6627 	if (netif_running(netdev)) {
6628 		u32 err = e1000_request_irq(adapter);
6629 
6630 		if (err)
6631 			return err;
6632 
6633 		e1000e_up(adapter);
6634 	}
6635 
6636 	netif_device_attach(netdev);
6637 
6638 	return 0;
6639 }
6640 
6641 static int e1000e_pm_suspend(struct device *dev)
6642 {
6643 	struct pci_dev *pdev = to_pci_dev(dev);
6644 	int rc;
6645 
6646 	e1000e_flush_lpic(pdev);
6647 
6648 	e1000e_pm_freeze(dev);
6649 
6650 	rc = __e1000_shutdown(pdev, false);
6651 	if (rc)
6652 		e1000e_pm_thaw(dev);
6653 
6654 	return rc;
6655 }
6656 
6657 static int e1000e_pm_resume(struct device *dev)
6658 {
6659 	struct pci_dev *pdev = to_pci_dev(dev);
6660 	int rc;
6661 
6662 	rc = __e1000_resume(pdev);
6663 	if (rc)
6664 		return rc;
6665 
6666 	return e1000e_pm_thaw(dev);
6667 }
6668 #endif /* CONFIG_PM_SLEEP */
6669 
6670 static int e1000e_pm_runtime_idle(struct device *dev)
6671 {
6672 	struct pci_dev *pdev = to_pci_dev(dev);
6673 	struct net_device *netdev = pci_get_drvdata(pdev);
6674 	struct e1000_adapter *adapter = netdev_priv(netdev);
6675 	u16 eee_lp;
6676 
6677 	eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6678 
6679 	if (!e1000e_has_link(adapter)) {
6680 		adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6681 		pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6682 	}
6683 
6684 	return -EBUSY;
6685 }
6686 
6687 static int e1000e_pm_runtime_resume(struct device *dev)
6688 {
6689 	struct pci_dev *pdev = to_pci_dev(dev);
6690 	struct net_device *netdev = pci_get_drvdata(pdev);
6691 	struct e1000_adapter *adapter = netdev_priv(netdev);
6692 	int rc;
6693 
6694 	rc = __e1000_resume(pdev);
6695 	if (rc)
6696 		return rc;
6697 
6698 	if (netdev->flags & IFF_UP)
6699 		e1000e_up(adapter);
6700 
6701 	return rc;
6702 }
6703 
6704 static int e1000e_pm_runtime_suspend(struct device *dev)
6705 {
6706 	struct pci_dev *pdev = to_pci_dev(dev);
6707 	struct net_device *netdev = pci_get_drvdata(pdev);
6708 	struct e1000_adapter *adapter = netdev_priv(netdev);
6709 
6710 	if (netdev->flags & IFF_UP) {
6711 		int count = E1000_CHECK_RESET_COUNT;
6712 
6713 		while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6714 			usleep_range(10000, 20000);
6715 
6716 		WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6717 
6718 		/* Down the device without resetting the hardware */
6719 		e1000e_down(adapter, false);
6720 	}
6721 
6722 	if (__e1000_shutdown(pdev, true)) {
6723 		e1000e_pm_runtime_resume(dev);
6724 		return -EBUSY;
6725 	}
6726 
6727 	return 0;
6728 }
6729 #endif /* CONFIG_PM */
6730 
6731 static void e1000_shutdown(struct pci_dev *pdev)
6732 {
6733 	e1000e_flush_lpic(pdev);
6734 
6735 	e1000e_pm_freeze(&pdev->dev);
6736 
6737 	__e1000_shutdown(pdev, false);
6738 }
6739 
6740 #ifdef CONFIG_NET_POLL_CONTROLLER
6741 
6742 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6743 {
6744 	struct net_device *netdev = data;
6745 	struct e1000_adapter *adapter = netdev_priv(netdev);
6746 
6747 	if (adapter->msix_entries) {
6748 		int vector, msix_irq;
6749 
6750 		vector = 0;
6751 		msix_irq = adapter->msix_entries[vector].vector;
6752 		if (disable_hardirq(msix_irq))
6753 			e1000_intr_msix_rx(msix_irq, netdev);
6754 		enable_irq(msix_irq);
6755 
6756 		vector++;
6757 		msix_irq = adapter->msix_entries[vector].vector;
6758 		if (disable_hardirq(msix_irq))
6759 			e1000_intr_msix_tx(msix_irq, netdev);
6760 		enable_irq(msix_irq);
6761 
6762 		vector++;
6763 		msix_irq = adapter->msix_entries[vector].vector;
6764 		if (disable_hardirq(msix_irq))
6765 			e1000_msix_other(msix_irq, netdev);
6766 		enable_irq(msix_irq);
6767 	}
6768 
6769 	return IRQ_HANDLED;
6770 }
6771 
6772 /**
6773  * e1000_netpoll
6774  * @netdev: network interface device structure
6775  *
6776  * Polling 'interrupt' - used by things like netconsole to send skbs
6777  * without having to re-enable interrupts. It's not called while
6778  * the interrupt routine is executing.
6779  */
6780 static void e1000_netpoll(struct net_device *netdev)
6781 {
6782 	struct e1000_adapter *adapter = netdev_priv(netdev);
6783 
6784 	switch (adapter->int_mode) {
6785 	case E1000E_INT_MODE_MSIX:
6786 		e1000_intr_msix(adapter->pdev->irq, netdev);
6787 		break;
6788 	case E1000E_INT_MODE_MSI:
6789 		if (disable_hardirq(adapter->pdev->irq))
6790 			e1000_intr_msi(adapter->pdev->irq, netdev);
6791 		enable_irq(adapter->pdev->irq);
6792 		break;
6793 	default:		/* E1000E_INT_MODE_LEGACY */
6794 		if (disable_hardirq(adapter->pdev->irq))
6795 			e1000_intr(adapter->pdev->irq, netdev);
6796 		enable_irq(adapter->pdev->irq);
6797 		break;
6798 	}
6799 }
6800 #endif
6801 
6802 /**
6803  * e1000_io_error_detected - called when PCI error is detected
6804  * @pdev: Pointer to PCI device
6805  * @state: The current pci connection state
6806  *
6807  * This function is called after a PCI bus error affecting
6808  * this device has been detected.
6809  */
6810 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6811 						pci_channel_state_t state)
6812 {
6813 	struct net_device *netdev = pci_get_drvdata(pdev);
6814 	struct e1000_adapter *adapter = netdev_priv(netdev);
6815 
6816 	netif_device_detach(netdev);
6817 
6818 	if (state == pci_channel_io_perm_failure)
6819 		return PCI_ERS_RESULT_DISCONNECT;
6820 
6821 	if (netif_running(netdev))
6822 		e1000e_down(adapter, true);
6823 	pci_disable_device(pdev);
6824 
6825 	/* Request a slot slot reset. */
6826 	return PCI_ERS_RESULT_NEED_RESET;
6827 }
6828 
6829 /**
6830  * e1000_io_slot_reset - called after the pci bus has been reset.
6831  * @pdev: Pointer to PCI device
6832  *
6833  * Restart the card from scratch, as if from a cold-boot. Implementation
6834  * resembles the first-half of the e1000e_pm_resume routine.
6835  */
6836 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6837 {
6838 	struct net_device *netdev = pci_get_drvdata(pdev);
6839 	struct e1000_adapter *adapter = netdev_priv(netdev);
6840 	struct e1000_hw *hw = &adapter->hw;
6841 	u16 aspm_disable_flag = 0;
6842 	int err;
6843 	pci_ers_result_t result;
6844 
6845 	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6846 		aspm_disable_flag = PCIE_LINK_STATE_L0S;
6847 	if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6848 		aspm_disable_flag |= PCIE_LINK_STATE_L1;
6849 	if (aspm_disable_flag)
6850 		e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6851 
6852 	err = pci_enable_device_mem(pdev);
6853 	if (err) {
6854 		dev_err(&pdev->dev,
6855 			"Cannot re-enable PCI device after reset.\n");
6856 		result = PCI_ERS_RESULT_DISCONNECT;
6857 	} else {
6858 		pdev->state_saved = true;
6859 		pci_restore_state(pdev);
6860 		pci_set_master(pdev);
6861 
6862 		pci_enable_wake(pdev, PCI_D3hot, 0);
6863 		pci_enable_wake(pdev, PCI_D3cold, 0);
6864 
6865 		e1000e_reset(adapter);
6866 		ew32(WUS, ~0);
6867 		result = PCI_ERS_RESULT_RECOVERED;
6868 	}
6869 
6870 	return result;
6871 }
6872 
6873 /**
6874  * e1000_io_resume - called when traffic can start flowing again.
6875  * @pdev: Pointer to PCI device
6876  *
6877  * This callback is called when the error recovery driver tells us that
6878  * its OK to resume normal operation. Implementation resembles the
6879  * second-half of the e1000e_pm_resume routine.
6880  */
6881 static void e1000_io_resume(struct pci_dev *pdev)
6882 {
6883 	struct net_device *netdev = pci_get_drvdata(pdev);
6884 	struct e1000_adapter *adapter = netdev_priv(netdev);
6885 
6886 	e1000_init_manageability_pt(adapter);
6887 
6888 	if (netif_running(netdev))
6889 		e1000e_up(adapter);
6890 
6891 	netif_device_attach(netdev);
6892 
6893 	/* If the controller has AMT, do not set DRV_LOAD until the interface
6894 	 * is up.  For all other cases, let the f/w know that the h/w is now
6895 	 * under the control of the driver.
6896 	 */
6897 	if (!(adapter->flags & FLAG_HAS_AMT))
6898 		e1000e_get_hw_control(adapter);
6899 }
6900 
6901 static void e1000_print_device_info(struct e1000_adapter *adapter)
6902 {
6903 	struct e1000_hw *hw = &adapter->hw;
6904 	struct net_device *netdev = adapter->netdev;
6905 	u32 ret_val;
6906 	u8 pba_str[E1000_PBANUM_LENGTH];
6907 
6908 	/* print bus type/speed/width info */
6909 	e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6910 	       /* bus width */
6911 	       ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6912 		"Width x1"),
6913 	       /* MAC address */
6914 	       netdev->dev_addr);
6915 	e_info("Intel(R) PRO/%s Network Connection\n",
6916 	       (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6917 	ret_val = e1000_read_pba_string_generic(hw, pba_str,
6918 						E1000_PBANUM_LENGTH);
6919 	if (ret_val)
6920 		strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6921 	e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6922 	       hw->mac.type, hw->phy.type, pba_str);
6923 }
6924 
6925 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6926 {
6927 	struct e1000_hw *hw = &adapter->hw;
6928 	int ret_val;
6929 	u16 buf = 0;
6930 
6931 	if (hw->mac.type != e1000_82573)
6932 		return;
6933 
6934 	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6935 	le16_to_cpus(&buf);
6936 	if (!ret_val && (!(buf & BIT(0)))) {
6937 		/* Deep Smart Power Down (DSPD) */
6938 		dev_warn(&adapter->pdev->dev,
6939 			 "Warning: detected DSPD enabled in EEPROM\n");
6940 	}
6941 }
6942 
6943 static netdev_features_t e1000_fix_features(struct net_device *netdev,
6944 					    netdev_features_t features)
6945 {
6946 	struct e1000_adapter *adapter = netdev_priv(netdev);
6947 	struct e1000_hw *hw = &adapter->hw;
6948 
6949 	/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6950 	if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6951 		features &= ~NETIF_F_RXFCS;
6952 
6953 	/* Since there is no support for separate Rx/Tx vlan accel
6954 	 * enable/disable make sure Tx flag is always in same state as Rx.
6955 	 */
6956 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
6957 		features |= NETIF_F_HW_VLAN_CTAG_TX;
6958 	else
6959 		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
6960 
6961 	return features;
6962 }
6963 
6964 static int e1000_set_features(struct net_device *netdev,
6965 			      netdev_features_t features)
6966 {
6967 	struct e1000_adapter *adapter = netdev_priv(netdev);
6968 	netdev_features_t changed = features ^ netdev->features;
6969 
6970 	if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6971 		adapter->flags |= FLAG_TSO_FORCE;
6972 
6973 	if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6974 			 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6975 			 NETIF_F_RXALL)))
6976 		return 0;
6977 
6978 	if (changed & NETIF_F_RXFCS) {
6979 		if (features & NETIF_F_RXFCS) {
6980 			adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6981 		} else {
6982 			/* We need to take it back to defaults, which might mean
6983 			 * stripping is still disabled at the adapter level.
6984 			 */
6985 			if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6986 				adapter->flags2 |= FLAG2_CRC_STRIPPING;
6987 			else
6988 				adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6989 		}
6990 	}
6991 
6992 	netdev->features = features;
6993 
6994 	if (netif_running(netdev))
6995 		e1000e_reinit_locked(adapter);
6996 	else
6997 		e1000e_reset(adapter);
6998 
6999 	return 1;
7000 }
7001 
7002 static const struct net_device_ops e1000e_netdev_ops = {
7003 	.ndo_open		= e1000e_open,
7004 	.ndo_stop		= e1000e_close,
7005 	.ndo_start_xmit		= e1000_xmit_frame,
7006 	.ndo_get_stats64	= e1000e_get_stats64,
7007 	.ndo_set_rx_mode	= e1000e_set_rx_mode,
7008 	.ndo_set_mac_address	= e1000_set_mac,
7009 	.ndo_change_mtu		= e1000_change_mtu,
7010 	.ndo_do_ioctl		= e1000_ioctl,
7011 	.ndo_tx_timeout		= e1000_tx_timeout,
7012 	.ndo_validate_addr	= eth_validate_addr,
7013 
7014 	.ndo_vlan_rx_add_vid	= e1000_vlan_rx_add_vid,
7015 	.ndo_vlan_rx_kill_vid	= e1000_vlan_rx_kill_vid,
7016 #ifdef CONFIG_NET_POLL_CONTROLLER
7017 	.ndo_poll_controller	= e1000_netpoll,
7018 #endif
7019 	.ndo_set_features = e1000_set_features,
7020 	.ndo_fix_features = e1000_fix_features,
7021 	.ndo_features_check	= passthru_features_check,
7022 };
7023 
7024 /**
7025  * e1000_probe - Device Initialization Routine
7026  * @pdev: PCI device information struct
7027  * @ent: entry in e1000_pci_tbl
7028  *
7029  * Returns 0 on success, negative on failure
7030  *
7031  * e1000_probe initializes an adapter identified by a pci_dev structure.
7032  * The OS initialization, configuring of the adapter private structure,
7033  * and a hardware reset occur.
7034  **/
7035 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7036 {
7037 	struct net_device *netdev;
7038 	struct e1000_adapter *adapter;
7039 	struct e1000_hw *hw;
7040 	const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7041 	resource_size_t mmio_start, mmio_len;
7042 	resource_size_t flash_start, flash_len;
7043 	static int cards_found;
7044 	u16 aspm_disable_flag = 0;
7045 	int bars, i, err, pci_using_dac;
7046 	u16 eeprom_data = 0;
7047 	u16 eeprom_apme_mask = E1000_EEPROM_APME;
7048 	s32 ret_val = 0;
7049 
7050 	if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7051 		aspm_disable_flag = PCIE_LINK_STATE_L0S;
7052 	if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7053 		aspm_disable_flag |= PCIE_LINK_STATE_L1;
7054 	if (aspm_disable_flag)
7055 		e1000e_disable_aspm(pdev, aspm_disable_flag);
7056 
7057 	err = pci_enable_device_mem(pdev);
7058 	if (err)
7059 		return err;
7060 
7061 	pci_using_dac = 0;
7062 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7063 	if (!err) {
7064 		pci_using_dac = 1;
7065 	} else {
7066 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7067 		if (err) {
7068 			dev_err(&pdev->dev,
7069 				"No usable DMA configuration, aborting\n");
7070 			goto err_dma;
7071 		}
7072 	}
7073 
7074 	bars = pci_select_bars(pdev, IORESOURCE_MEM);
7075 	err = pci_request_selected_regions_exclusive(pdev, bars,
7076 						     e1000e_driver_name);
7077 	if (err)
7078 		goto err_pci_reg;
7079 
7080 	/* AER (Advanced Error Reporting) hooks */
7081 	pci_enable_pcie_error_reporting(pdev);
7082 
7083 	pci_set_master(pdev);
7084 	/* PCI config space info */
7085 	err = pci_save_state(pdev);
7086 	if (err)
7087 		goto err_alloc_etherdev;
7088 
7089 	err = -ENOMEM;
7090 	netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7091 	if (!netdev)
7092 		goto err_alloc_etherdev;
7093 
7094 	SET_NETDEV_DEV(netdev, &pdev->dev);
7095 
7096 	netdev->irq = pdev->irq;
7097 
7098 	pci_set_drvdata(pdev, netdev);
7099 	adapter = netdev_priv(netdev);
7100 	hw = &adapter->hw;
7101 	adapter->netdev = netdev;
7102 	adapter->pdev = pdev;
7103 	adapter->ei = ei;
7104 	adapter->pba = ei->pba;
7105 	adapter->flags = ei->flags;
7106 	adapter->flags2 = ei->flags2;
7107 	adapter->hw.adapter = adapter;
7108 	adapter->hw.mac.type = ei->mac;
7109 	adapter->max_hw_frame_size = ei->max_hw_frame_size;
7110 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7111 
7112 	mmio_start = pci_resource_start(pdev, 0);
7113 	mmio_len = pci_resource_len(pdev, 0);
7114 
7115 	err = -EIO;
7116 	adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7117 	if (!adapter->hw.hw_addr)
7118 		goto err_ioremap;
7119 
7120 	if ((adapter->flags & FLAG_HAS_FLASH) &&
7121 	    (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7122 	    (hw->mac.type < e1000_pch_spt)) {
7123 		flash_start = pci_resource_start(pdev, 1);
7124 		flash_len = pci_resource_len(pdev, 1);
7125 		adapter->hw.flash_address = ioremap(flash_start, flash_len);
7126 		if (!adapter->hw.flash_address)
7127 			goto err_flashmap;
7128 	}
7129 
7130 	/* Set default EEE advertisement */
7131 	if (adapter->flags2 & FLAG2_HAS_EEE)
7132 		adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7133 
7134 	/* construct the net_device struct */
7135 	netdev->netdev_ops = &e1000e_netdev_ops;
7136 	e1000e_set_ethtool_ops(netdev);
7137 	netdev->watchdog_timeo = 5 * HZ;
7138 	netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7139 	strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7140 
7141 	netdev->mem_start = mmio_start;
7142 	netdev->mem_end = mmio_start + mmio_len;
7143 
7144 	adapter->bd_number = cards_found++;
7145 
7146 	e1000e_check_options(adapter);
7147 
7148 	/* setup adapter struct */
7149 	err = e1000_sw_init(adapter);
7150 	if (err)
7151 		goto err_sw_init;
7152 
7153 	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7154 	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7155 	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7156 
7157 	err = ei->get_variants(adapter);
7158 	if (err)
7159 		goto err_hw_init;
7160 
7161 	if ((adapter->flags & FLAG_IS_ICH) &&
7162 	    (adapter->flags & FLAG_READ_ONLY_NVM) &&
7163 	    (hw->mac.type < e1000_pch_spt))
7164 		e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7165 
7166 	hw->mac.ops.get_bus_info(&adapter->hw);
7167 
7168 	adapter->hw.phy.autoneg_wait_to_complete = 0;
7169 
7170 	/* Copper options */
7171 	if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7172 		adapter->hw.phy.mdix = AUTO_ALL_MODES;
7173 		adapter->hw.phy.disable_polarity_correction = 0;
7174 		adapter->hw.phy.ms_type = e1000_ms_hw_default;
7175 	}
7176 
7177 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7178 		dev_info(&pdev->dev,
7179 			 "PHY reset is blocked due to SOL/IDER session.\n");
7180 
7181 	/* Set initial default active device features */
7182 	netdev->features = (NETIF_F_SG |
7183 			    NETIF_F_HW_VLAN_CTAG_RX |
7184 			    NETIF_F_HW_VLAN_CTAG_TX |
7185 			    NETIF_F_TSO |
7186 			    NETIF_F_TSO6 |
7187 			    NETIF_F_RXHASH |
7188 			    NETIF_F_RXCSUM |
7189 			    NETIF_F_HW_CSUM);
7190 
7191 	/* Set user-changeable features (subset of all device features) */
7192 	netdev->hw_features = netdev->features;
7193 	netdev->hw_features |= NETIF_F_RXFCS;
7194 	netdev->priv_flags |= IFF_SUPP_NOFCS;
7195 	netdev->hw_features |= NETIF_F_RXALL;
7196 
7197 	if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7198 		netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7199 
7200 	netdev->vlan_features |= (NETIF_F_SG |
7201 				  NETIF_F_TSO |
7202 				  NETIF_F_TSO6 |
7203 				  NETIF_F_HW_CSUM);
7204 
7205 	netdev->priv_flags |= IFF_UNICAST_FLT;
7206 
7207 	if (pci_using_dac) {
7208 		netdev->features |= NETIF_F_HIGHDMA;
7209 		netdev->vlan_features |= NETIF_F_HIGHDMA;
7210 	}
7211 
7212 	/* MTU range: 68 - max_hw_frame_size */
7213 	netdev->min_mtu = ETH_MIN_MTU;
7214 	netdev->max_mtu = adapter->max_hw_frame_size -
7215 			  (VLAN_ETH_HLEN + ETH_FCS_LEN);
7216 
7217 	if (e1000e_enable_mng_pass_thru(&adapter->hw))
7218 		adapter->flags |= FLAG_MNG_PT_ENABLED;
7219 
7220 	/* before reading the NVM, reset the controller to
7221 	 * put the device in a known good starting state
7222 	 */
7223 	adapter->hw.mac.ops.reset_hw(&adapter->hw);
7224 
7225 	/* systems with ASPM and others may see the checksum fail on the first
7226 	 * attempt. Let's give it a few tries
7227 	 */
7228 	for (i = 0;; i++) {
7229 		if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7230 			break;
7231 		if (i == 2) {
7232 			dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7233 			err = -EIO;
7234 			goto err_eeprom;
7235 		}
7236 	}
7237 
7238 	e1000_eeprom_checks(adapter);
7239 
7240 	/* copy the MAC address */
7241 	if (e1000e_read_mac_addr(&adapter->hw))
7242 		dev_err(&pdev->dev,
7243 			"NVM Read Error while reading MAC address\n");
7244 
7245 	memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7246 
7247 	if (!is_valid_ether_addr(netdev->dev_addr)) {
7248 		dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7249 			netdev->dev_addr);
7250 		err = -EIO;
7251 		goto err_eeprom;
7252 	}
7253 
7254 	timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7255 	timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7256 
7257 	INIT_WORK(&adapter->reset_task, e1000_reset_task);
7258 	INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7259 	INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7260 	INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7261 	INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7262 
7263 	/* Initialize link parameters. User can change them with ethtool */
7264 	adapter->hw.mac.autoneg = 1;
7265 	adapter->fc_autoneg = true;
7266 	adapter->hw.fc.requested_mode = e1000_fc_default;
7267 	adapter->hw.fc.current_mode = e1000_fc_default;
7268 	adapter->hw.phy.autoneg_advertised = 0x2f;
7269 
7270 	/* Initial Wake on LAN setting - If APM wake is enabled in
7271 	 * the EEPROM, enable the ACPI Magic Packet filter
7272 	 */
7273 	if (adapter->flags & FLAG_APME_IN_WUC) {
7274 		/* APME bit in EEPROM is mapped to WUC.APME */
7275 		eeprom_data = er32(WUC);
7276 		eeprom_apme_mask = E1000_WUC_APME;
7277 		if ((hw->mac.type > e1000_ich10lan) &&
7278 		    (eeprom_data & E1000_WUC_PHY_WAKE))
7279 			adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7280 	} else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7281 		if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7282 		    (adapter->hw.bus.func == 1))
7283 			ret_val = e1000_read_nvm(&adapter->hw,
7284 					      NVM_INIT_CONTROL3_PORT_B,
7285 					      1, &eeprom_data);
7286 		else
7287 			ret_val = e1000_read_nvm(&adapter->hw,
7288 					      NVM_INIT_CONTROL3_PORT_A,
7289 					      1, &eeprom_data);
7290 	}
7291 
7292 	/* fetch WoL from EEPROM */
7293 	if (ret_val)
7294 		e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7295 	else if (eeprom_data & eeprom_apme_mask)
7296 		adapter->eeprom_wol |= E1000_WUFC_MAG;
7297 
7298 	/* now that we have the eeprom settings, apply the special cases
7299 	 * where the eeprom may be wrong or the board simply won't support
7300 	 * wake on lan on a particular port
7301 	 */
7302 	if (!(adapter->flags & FLAG_HAS_WOL))
7303 		adapter->eeprom_wol = 0;
7304 
7305 	/* initialize the wol settings based on the eeprom settings */
7306 	adapter->wol = adapter->eeprom_wol;
7307 
7308 	/* make sure adapter isn't asleep if manageability is enabled */
7309 	if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7310 	    (hw->mac.ops.check_mng_mode(hw)))
7311 		device_wakeup_enable(&pdev->dev);
7312 
7313 	/* save off EEPROM version number */
7314 	ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7315 
7316 	if (ret_val) {
7317 		e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7318 		adapter->eeprom_vers = 0;
7319 	}
7320 
7321 	/* init PTP hardware clock */
7322 	e1000e_ptp_init(adapter);
7323 
7324 	/* reset the hardware with the new settings */
7325 	e1000e_reset(adapter);
7326 
7327 	/* If the controller has AMT, do not set DRV_LOAD until the interface
7328 	 * is up.  For all other cases, let the f/w know that the h/w is now
7329 	 * under the control of the driver.
7330 	 */
7331 	if (!(adapter->flags & FLAG_HAS_AMT))
7332 		e1000e_get_hw_control(adapter);
7333 
7334 	strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7335 	err = register_netdev(netdev);
7336 	if (err)
7337 		goto err_register;
7338 
7339 	/* carrier off reporting is important to ethtool even BEFORE open */
7340 	netif_carrier_off(netdev);
7341 
7342 	e1000_print_device_info(adapter);
7343 
7344 	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
7345 
7346 	if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp)
7347 		pm_runtime_put_noidle(&pdev->dev);
7348 
7349 	return 0;
7350 
7351 err_register:
7352 	if (!(adapter->flags & FLAG_HAS_AMT))
7353 		e1000e_release_hw_control(adapter);
7354 err_eeprom:
7355 	if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7356 		e1000_phy_hw_reset(&adapter->hw);
7357 err_hw_init:
7358 	kfree(adapter->tx_ring);
7359 	kfree(adapter->rx_ring);
7360 err_sw_init:
7361 	if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7362 		iounmap(adapter->hw.flash_address);
7363 	e1000e_reset_interrupt_capability(adapter);
7364 err_flashmap:
7365 	iounmap(adapter->hw.hw_addr);
7366 err_ioremap:
7367 	free_netdev(netdev);
7368 err_alloc_etherdev:
7369 	pci_release_mem_regions(pdev);
7370 err_pci_reg:
7371 err_dma:
7372 	pci_disable_device(pdev);
7373 	return err;
7374 }
7375 
7376 /**
7377  * e1000_remove - Device Removal Routine
7378  * @pdev: PCI device information struct
7379  *
7380  * e1000_remove is called by the PCI subsystem to alert the driver
7381  * that it should release a PCI device.  The could be caused by a
7382  * Hot-Plug event, or because the driver is going to be removed from
7383  * memory.
7384  **/
7385 static void e1000_remove(struct pci_dev *pdev)
7386 {
7387 	struct net_device *netdev = pci_get_drvdata(pdev);
7388 	struct e1000_adapter *adapter = netdev_priv(netdev);
7389 	bool down = test_bit(__E1000_DOWN, &adapter->state);
7390 
7391 	e1000e_ptp_remove(adapter);
7392 
7393 	/* The timers may be rescheduled, so explicitly disable them
7394 	 * from being rescheduled.
7395 	 */
7396 	if (!down)
7397 		set_bit(__E1000_DOWN, &adapter->state);
7398 	del_timer_sync(&adapter->watchdog_timer);
7399 	del_timer_sync(&adapter->phy_info_timer);
7400 
7401 	cancel_work_sync(&adapter->reset_task);
7402 	cancel_work_sync(&adapter->watchdog_task);
7403 	cancel_work_sync(&adapter->downshift_task);
7404 	cancel_work_sync(&adapter->update_phy_task);
7405 	cancel_work_sync(&adapter->print_hang_task);
7406 
7407 	if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7408 		cancel_work_sync(&adapter->tx_hwtstamp_work);
7409 		if (adapter->tx_hwtstamp_skb) {
7410 			dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7411 			adapter->tx_hwtstamp_skb = NULL;
7412 		}
7413 	}
7414 
7415 	/* Don't lie to e1000_close() down the road. */
7416 	if (!down)
7417 		clear_bit(__E1000_DOWN, &adapter->state);
7418 	unregister_netdev(netdev);
7419 
7420 	if (pci_dev_run_wake(pdev))
7421 		pm_runtime_get_noresume(&pdev->dev);
7422 
7423 	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
7424 	 * would have already happened in close and is redundant.
7425 	 */
7426 	e1000e_release_hw_control(adapter);
7427 
7428 	e1000e_reset_interrupt_capability(adapter);
7429 	kfree(adapter->tx_ring);
7430 	kfree(adapter->rx_ring);
7431 
7432 	iounmap(adapter->hw.hw_addr);
7433 	if ((adapter->hw.flash_address) &&
7434 	    (adapter->hw.mac.type < e1000_pch_spt))
7435 		iounmap(adapter->hw.flash_address);
7436 	pci_release_mem_regions(pdev);
7437 
7438 	free_netdev(netdev);
7439 
7440 	/* AER disable */
7441 	pci_disable_pcie_error_reporting(pdev);
7442 
7443 	pci_disable_device(pdev);
7444 }
7445 
7446 /* PCI Error Recovery (ERS) */
7447 static const struct pci_error_handlers e1000_err_handler = {
7448 	.error_detected = e1000_io_error_detected,
7449 	.slot_reset = e1000_io_slot_reset,
7450 	.resume = e1000_io_resume,
7451 };
7452 
7453 static const struct pci_device_id e1000_pci_tbl[] = {
7454 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7455 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7456 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7457 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7458 	  board_82571 },
7459 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7460 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7461 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7462 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7463 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7464 
7465 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7466 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7467 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7468 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7469 
7470 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7471 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7472 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7473 
7474 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7475 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7476 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7477 
7478 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7479 	  board_80003es2lan },
7480 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7481 	  board_80003es2lan },
7482 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7483 	  board_80003es2lan },
7484 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7485 	  board_80003es2lan },
7486 
7487 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7488 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7489 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7490 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7491 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7492 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7493 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7494 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7495 
7496 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7497 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7498 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7499 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7500 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7501 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7502 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7503 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7504 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7505 
7506 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7507 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7508 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7509 
7510 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7511 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7512 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7513 
7514 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7515 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7516 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7517 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7518 
7519 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7520 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7521 
7522 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7523 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7524 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7525 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7526 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7527 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7528 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7529 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7530 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7531 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7532 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7533 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7534 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7535 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7536 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7537 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7538 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7539 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7540 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7541 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7542 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7543 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7544 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7545 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7546 	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7547 
7548 	{ 0, 0, 0, 0, 0, 0, 0 }	/* terminate list */
7549 };
7550 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7551 
7552 static const struct dev_pm_ops e1000_pm_ops = {
7553 #ifdef CONFIG_PM_SLEEP
7554 	.suspend	= e1000e_pm_suspend,
7555 	.resume		= e1000e_pm_resume,
7556 	.freeze		= e1000e_pm_freeze,
7557 	.thaw		= e1000e_pm_thaw,
7558 	.poweroff	= e1000e_pm_suspend,
7559 	.restore	= e1000e_pm_resume,
7560 #endif
7561 	SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7562 			   e1000e_pm_runtime_idle)
7563 };
7564 
7565 /* PCI Device API Driver */
7566 static struct pci_driver e1000_driver = {
7567 	.name     = e1000e_driver_name,
7568 	.id_table = e1000_pci_tbl,
7569 	.probe    = e1000_probe,
7570 	.remove   = e1000_remove,
7571 	.driver   = {
7572 		.pm = &e1000_pm_ops,
7573 	},
7574 	.shutdown = e1000_shutdown,
7575 	.err_handler = &e1000_err_handler
7576 };
7577 
7578 /**
7579  * e1000_init_module - Driver Registration Routine
7580  *
7581  * e1000_init_module is the first routine called when the driver is
7582  * loaded. All it does is register with the PCI subsystem.
7583  **/
7584 static int __init e1000_init_module(void)
7585 {
7586 	pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7587 		e1000e_driver_version);
7588 	pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7589 
7590 	return pci_register_driver(&e1000_driver);
7591 }
7592 module_init(e1000_init_module);
7593 
7594 /**
7595  * e1000_exit_module - Driver Exit Cleanup Routine
7596  *
7597  * e1000_exit_module is called just before the driver is removed
7598  * from memory.
7599  **/
7600 static void __exit e1000_exit_module(void)
7601 {
7602 	pci_unregister_driver(&e1000_driver);
7603 }
7604 module_exit(e1000_exit_module);
7605 
7606 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7607 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7608 MODULE_LICENSE("GPL v2");
7609 MODULE_VERSION(DRV_VERSION);
7610 
7611 /* netdev.c */
7612