1 // SPDX-License-Identifier: GPL-2.0
2 /* Intel PRO/1000 Linux driver
3  * Copyright(c) 1999 - 2015 Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in
15  * the file called "COPYING".
16  *
17  * Contact Information:
18  * Linux NICS <linux.nics@intel.com>
19  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21  */
22 
23 #include "e1000.h"
24 
25 /**
26  *  e1000e_get_bus_info_pcie - Get PCIe bus information
27  *  @hw: pointer to the HW structure
28  *
29  *  Determines and stores the system bus information for a particular
30  *  network interface.  The following bus information is determined and stored:
31  *  bus speed, bus width, type (PCIe), and PCIe function.
32  **/
33 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
34 {
35 	struct e1000_mac_info *mac = &hw->mac;
36 	struct e1000_bus_info *bus = &hw->bus;
37 	struct e1000_adapter *adapter = hw->adapter;
38 	u16 pcie_link_status, cap_offset;
39 
40 	cap_offset = adapter->pdev->pcie_cap;
41 	if (!cap_offset) {
42 		bus->width = e1000_bus_width_unknown;
43 	} else {
44 		pci_read_config_word(adapter->pdev,
45 				     cap_offset + PCIE_LINK_STATUS,
46 				     &pcie_link_status);
47 		bus->width = (enum e1000_bus_width)((pcie_link_status &
48 						     PCIE_LINK_WIDTH_MASK) >>
49 						    PCIE_LINK_WIDTH_SHIFT);
50 	}
51 
52 	mac->ops.set_lan_id(hw);
53 
54 	return 0;
55 }
56 
57 /**
58  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
59  *
60  *  @hw: pointer to the HW structure
61  *
62  *  Determines the LAN function id by reading memory-mapped registers
63  *  and swaps the port value if requested.
64  **/
65 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
66 {
67 	struct e1000_bus_info *bus = &hw->bus;
68 	u32 reg;
69 
70 	/* The status register reports the correct function number
71 	 * for the device regardless of function swap state.
72 	 */
73 	reg = er32(STATUS);
74 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
75 }
76 
77 /**
78  *  e1000_set_lan_id_single_port - Set LAN id for a single port device
79  *  @hw: pointer to the HW structure
80  *
81  *  Sets the LAN function id to zero for a single port device.
82  **/
83 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
84 {
85 	struct e1000_bus_info *bus = &hw->bus;
86 
87 	bus->func = 0;
88 }
89 
90 /**
91  *  e1000_clear_vfta_generic - Clear VLAN filter table
92  *  @hw: pointer to the HW structure
93  *
94  *  Clears the register array which contains the VLAN filter table by
95  *  setting all the values to 0.
96  **/
97 void e1000_clear_vfta_generic(struct e1000_hw *hw)
98 {
99 	u32 offset;
100 
101 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
102 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
103 		e1e_flush();
104 	}
105 }
106 
107 /**
108  *  e1000_write_vfta_generic - Write value to VLAN filter table
109  *  @hw: pointer to the HW structure
110  *  @offset: register offset in VLAN filter table
111  *  @value: register value written to VLAN filter table
112  *
113  *  Writes value at the given offset in the register array which stores
114  *  the VLAN filter table.
115  **/
116 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
117 {
118 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
119 	e1e_flush();
120 }
121 
122 /**
123  *  e1000e_init_rx_addrs - Initialize receive address's
124  *  @hw: pointer to the HW structure
125  *  @rar_count: receive address registers
126  *
127  *  Setup the receive address registers by setting the base receive address
128  *  register to the devices MAC address and clearing all the other receive
129  *  address registers to 0.
130  **/
131 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
132 {
133 	u32 i;
134 	u8 mac_addr[ETH_ALEN] = { 0 };
135 
136 	/* Setup the receive address */
137 	e_dbg("Programming MAC Address into RAR[0]\n");
138 
139 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
140 
141 	/* Zero out the other (rar_entry_count - 1) receive addresses */
142 	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
143 	for (i = 1; i < rar_count; i++)
144 		hw->mac.ops.rar_set(hw, mac_addr, i);
145 }
146 
147 /**
148  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
149  *  @hw: pointer to the HW structure
150  *
151  *  Checks the nvm for an alternate MAC address.  An alternate MAC address
152  *  can be setup by pre-boot software and must be treated like a permanent
153  *  address and must override the actual permanent MAC address. If an
154  *  alternate MAC address is found it is programmed into RAR0, replacing
155  *  the permanent address that was installed into RAR0 by the Si on reset.
156  *  This function will return SUCCESS unless it encounters an error while
157  *  reading the EEPROM.
158  **/
159 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
160 {
161 	u32 i;
162 	s32 ret_val;
163 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
164 	u8 alt_mac_addr[ETH_ALEN];
165 
166 	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
167 	if (ret_val)
168 		return ret_val;
169 
170 	/* not supported on 82573 */
171 	if (hw->mac.type == e1000_82573)
172 		return 0;
173 
174 	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
175 				 &nvm_alt_mac_addr_offset);
176 	if (ret_val) {
177 		e_dbg("NVM Read Error\n");
178 		return ret_val;
179 	}
180 
181 	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
182 	    (nvm_alt_mac_addr_offset == 0x0000))
183 		/* There is no Alternate MAC Address */
184 		return 0;
185 
186 	if (hw->bus.func == E1000_FUNC_1)
187 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
188 	for (i = 0; i < ETH_ALEN; i += 2) {
189 		offset = nvm_alt_mac_addr_offset + (i >> 1);
190 		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
191 		if (ret_val) {
192 			e_dbg("NVM Read Error\n");
193 			return ret_val;
194 		}
195 
196 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
197 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
198 	}
199 
200 	/* if multicast bit is set, the alternate address will not be used */
201 	if (is_multicast_ether_addr(alt_mac_addr)) {
202 		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
203 		return 0;
204 	}
205 
206 	/* We have a valid alternate MAC address, and we want to treat it the
207 	 * same as the normal permanent MAC address stored by the HW into the
208 	 * RAR. Do this by mapping this address into RAR0.
209 	 */
210 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
211 
212 	return 0;
213 }
214 
215 u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)
216 {
217 	return hw->mac.rar_entry_count;
218 }
219 
220 /**
221  *  e1000e_rar_set_generic - Set receive address register
222  *  @hw: pointer to the HW structure
223  *  @addr: pointer to the receive address
224  *  @index: receive address array register
225  *
226  *  Sets the receive address array register at index to the address passed
227  *  in by addr.
228  **/
229 int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
230 {
231 	u32 rar_low, rar_high;
232 
233 	/* HW expects these in little endian so we reverse the byte order
234 	 * from network order (big endian) to little endian
235 	 */
236 	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
237 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
238 
239 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
240 
241 	/* If MAC address zero, no need to set the AV bit */
242 	if (rar_low || rar_high)
243 		rar_high |= E1000_RAH_AV;
244 
245 	/* Some bridges will combine consecutive 32-bit writes into
246 	 * a single burst write, which will malfunction on some parts.
247 	 * The flushes avoid this.
248 	 */
249 	ew32(RAL(index), rar_low);
250 	e1e_flush();
251 	ew32(RAH(index), rar_high);
252 	e1e_flush();
253 
254 	return 0;
255 }
256 
257 /**
258  *  e1000_hash_mc_addr - Generate a multicast hash value
259  *  @hw: pointer to the HW structure
260  *  @mc_addr: pointer to a multicast address
261  *
262  *  Generates a multicast address hash value which is used to determine
263  *  the multicast filter table array address and new table value.
264  **/
265 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
266 {
267 	u32 hash_value, hash_mask;
268 	u8 bit_shift = 0;
269 
270 	/* Register count multiplied by bits per register */
271 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
272 
273 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts
274 	 * where 0xFF would still fall within the hash mask.
275 	 */
276 	while (hash_mask >> bit_shift != 0xFF)
277 		bit_shift++;
278 
279 	/* The portion of the address that is used for the hash table
280 	 * is determined by the mc_filter_type setting.
281 	 * The algorithm is such that there is a total of 8 bits of shifting.
282 	 * The bit_shift for a mc_filter_type of 0 represents the number of
283 	 * left-shifts where the MSB of mc_addr[5] would still fall within
284 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
285 	 * of 8 bits of shifting, then mc_addr[4] will shift right the
286 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
287 	 * cases are a variation of this algorithm...essentially raising the
288 	 * number of bits to shift mc_addr[5] left, while still keeping the
289 	 * 8-bit shifting total.
290 	 *
291 	 * For example, given the following Destination MAC Address and an
292 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
293 	 * we can see that the bit_shift for case 0 is 4.  These are the hash
294 	 * values resulting from each mc_filter_type...
295 	 * [0] [1] [2] [3] [4] [5]
296 	 * 01  AA  00  12  34  56
297 	 * LSB           MSB
298 	 *
299 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
300 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
301 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
302 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
303 	 */
304 	switch (hw->mac.mc_filter_type) {
305 	default:
306 	case 0:
307 		break;
308 	case 1:
309 		bit_shift += 1;
310 		break;
311 	case 2:
312 		bit_shift += 2;
313 		break;
314 	case 3:
315 		bit_shift += 4;
316 		break;
317 	}
318 
319 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
320 				   (((u16)mc_addr[5]) << bit_shift)));
321 
322 	return hash_value;
323 }
324 
325 /**
326  *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
327  *  @hw: pointer to the HW structure
328  *  @mc_addr_list: array of multicast addresses to program
329  *  @mc_addr_count: number of multicast addresses to program
330  *
331  *  Updates entire Multicast Table Array.
332  *  The caller must have a packed mc_addr_list of multicast addresses.
333  **/
334 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
335 					u8 *mc_addr_list, u32 mc_addr_count)
336 {
337 	u32 hash_value, hash_bit, hash_reg;
338 	int i;
339 
340 	/* clear mta_shadow */
341 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
342 
343 	/* update mta_shadow from mc_addr_list */
344 	for (i = 0; (u32)i < mc_addr_count; i++) {
345 		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
346 
347 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
348 		hash_bit = hash_value & 0x1F;
349 
350 		hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
351 		mc_addr_list += (ETH_ALEN);
352 	}
353 
354 	/* replace the entire MTA table */
355 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
356 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
357 	e1e_flush();
358 }
359 
360 /**
361  *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
362  *  @hw: pointer to the HW structure
363  *
364  *  Clears the base hardware counters by reading the counter registers.
365  **/
366 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
367 {
368 	er32(CRCERRS);
369 	er32(SYMERRS);
370 	er32(MPC);
371 	er32(SCC);
372 	er32(ECOL);
373 	er32(MCC);
374 	er32(LATECOL);
375 	er32(COLC);
376 	er32(DC);
377 	er32(SEC);
378 	er32(RLEC);
379 	er32(XONRXC);
380 	er32(XONTXC);
381 	er32(XOFFRXC);
382 	er32(XOFFTXC);
383 	er32(FCRUC);
384 	er32(GPRC);
385 	er32(BPRC);
386 	er32(MPRC);
387 	er32(GPTC);
388 	er32(GORCL);
389 	er32(GORCH);
390 	er32(GOTCL);
391 	er32(GOTCH);
392 	er32(RNBC);
393 	er32(RUC);
394 	er32(RFC);
395 	er32(ROC);
396 	er32(RJC);
397 	er32(TORL);
398 	er32(TORH);
399 	er32(TOTL);
400 	er32(TOTH);
401 	er32(TPR);
402 	er32(TPT);
403 	er32(MPTC);
404 	er32(BPTC);
405 }
406 
407 /**
408  *  e1000e_check_for_copper_link - Check for link (Copper)
409  *  @hw: pointer to the HW structure
410  *
411  *  Checks to see of the link status of the hardware has changed.  If a
412  *  change in link status has been detected, then we read the PHY registers
413  *  to get the current speed/duplex if link exists.
414  **/
415 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
416 {
417 	struct e1000_mac_info *mac = &hw->mac;
418 	s32 ret_val;
419 	bool link;
420 
421 	/* We only want to go out to the PHY registers to see if Auto-Neg
422 	 * has completed and/or if our link status has changed.  The
423 	 * get_link_status flag is set upon receiving a Link Status
424 	 * Change or Rx Sequence Error interrupt.
425 	 */
426 	if (!mac->get_link_status)
427 		return 0;
428 	mac->get_link_status = false;
429 
430 	/* First we want to see if the MII Status Register reports
431 	 * link.  If so, then we want to get the current speed/duplex
432 	 * of the PHY.
433 	 */
434 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
435 	if (ret_val || !link)
436 		goto out;
437 
438 	/* Check if there was DownShift, must be checked
439 	 * immediately after link-up
440 	 */
441 	e1000e_check_downshift(hw);
442 
443 	/* If we are forcing speed/duplex, then we simply return since
444 	 * we have already determined whether we have link or not.
445 	 */
446 	if (!mac->autoneg)
447 		return -E1000_ERR_CONFIG;
448 
449 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
450 	 * of MAC speed/duplex configuration.  So we only need to
451 	 * configure Collision Distance in the MAC.
452 	 */
453 	mac->ops.config_collision_dist(hw);
454 
455 	/* Configure Flow Control now that Auto-Neg has completed.
456 	 * First, we need to restore the desired flow control
457 	 * settings because we may have had to re-autoneg with a
458 	 * different link partner.
459 	 */
460 	ret_val = e1000e_config_fc_after_link_up(hw);
461 	if (ret_val)
462 		e_dbg("Error configuring flow control\n");
463 
464 	return ret_val;
465 
466 out:
467 	mac->get_link_status = true;
468 	return ret_val;
469 }
470 
471 /**
472  *  e1000e_check_for_fiber_link - Check for link (Fiber)
473  *  @hw: pointer to the HW structure
474  *
475  *  Checks for link up on the hardware.  If link is not up and we have
476  *  a signal, then we need to force link up.
477  **/
478 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
479 {
480 	struct e1000_mac_info *mac = &hw->mac;
481 	u32 rxcw;
482 	u32 ctrl;
483 	u32 status;
484 	s32 ret_val;
485 
486 	ctrl = er32(CTRL);
487 	status = er32(STATUS);
488 	rxcw = er32(RXCW);
489 
490 	/* If we don't have link (auto-negotiation failed or link partner
491 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
492 	 * and our link partner is not trying to auto-negotiate with us (we
493 	 * are receiving idles or data), we need to force link up. We also
494 	 * need to give auto-negotiation time to complete, in case the cable
495 	 * was just plugged in. The autoneg_failed flag does this.
496 	 */
497 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
498 	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
499 	    !(rxcw & E1000_RXCW_C)) {
500 		if (!mac->autoneg_failed) {
501 			mac->autoneg_failed = true;
502 			return 0;
503 		}
504 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
505 
506 		/* Disable auto-negotiation in the TXCW register */
507 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
508 
509 		/* Force link-up and also force full-duplex. */
510 		ctrl = er32(CTRL);
511 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
512 		ew32(CTRL, ctrl);
513 
514 		/* Configure Flow Control after forcing link up. */
515 		ret_val = e1000e_config_fc_after_link_up(hw);
516 		if (ret_val) {
517 			e_dbg("Error configuring flow control\n");
518 			return ret_val;
519 		}
520 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
521 		/* If we are forcing link and we are receiving /C/ ordered
522 		 * sets, re-enable auto-negotiation in the TXCW register
523 		 * and disable forced link in the Device Control register
524 		 * in an attempt to auto-negotiate with our link partner.
525 		 */
526 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
527 		ew32(TXCW, mac->txcw);
528 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
529 
530 		mac->serdes_has_link = true;
531 	}
532 
533 	return 0;
534 }
535 
536 /**
537  *  e1000e_check_for_serdes_link - Check for link (Serdes)
538  *  @hw: pointer to the HW structure
539  *
540  *  Checks for link up on the hardware.  If link is not up and we have
541  *  a signal, then we need to force link up.
542  **/
543 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
544 {
545 	struct e1000_mac_info *mac = &hw->mac;
546 	u32 rxcw;
547 	u32 ctrl;
548 	u32 status;
549 	s32 ret_val;
550 
551 	ctrl = er32(CTRL);
552 	status = er32(STATUS);
553 	rxcw = er32(RXCW);
554 
555 	/* If we don't have link (auto-negotiation failed or link partner
556 	 * cannot auto-negotiate), and our link partner is not trying to
557 	 * auto-negotiate with us (we are receiving idles or data),
558 	 * we need to force link up. We also need to give auto-negotiation
559 	 * time to complete.
560 	 */
561 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
562 	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
563 		if (!mac->autoneg_failed) {
564 			mac->autoneg_failed = true;
565 			return 0;
566 		}
567 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
568 
569 		/* Disable auto-negotiation in the TXCW register */
570 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
571 
572 		/* Force link-up and also force full-duplex. */
573 		ctrl = er32(CTRL);
574 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
575 		ew32(CTRL, ctrl);
576 
577 		/* Configure Flow Control after forcing link up. */
578 		ret_val = e1000e_config_fc_after_link_up(hw);
579 		if (ret_val) {
580 			e_dbg("Error configuring flow control\n");
581 			return ret_val;
582 		}
583 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
584 		/* If we are forcing link and we are receiving /C/ ordered
585 		 * sets, re-enable auto-negotiation in the TXCW register
586 		 * and disable forced link in the Device Control register
587 		 * in an attempt to auto-negotiate with our link partner.
588 		 */
589 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
590 		ew32(TXCW, mac->txcw);
591 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
592 
593 		mac->serdes_has_link = true;
594 	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
595 		/* If we force link for non-auto-negotiation switch, check
596 		 * link status based on MAC synchronization for internal
597 		 * serdes media type.
598 		 */
599 		/* SYNCH bit and IV bit are sticky. */
600 		usleep_range(10, 20);
601 		rxcw = er32(RXCW);
602 		if (rxcw & E1000_RXCW_SYNCH) {
603 			if (!(rxcw & E1000_RXCW_IV)) {
604 				mac->serdes_has_link = true;
605 				e_dbg("SERDES: Link up - forced.\n");
606 			}
607 		} else {
608 			mac->serdes_has_link = false;
609 			e_dbg("SERDES: Link down - force failed.\n");
610 		}
611 	}
612 
613 	if (E1000_TXCW_ANE & er32(TXCW)) {
614 		status = er32(STATUS);
615 		if (status & E1000_STATUS_LU) {
616 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
617 			usleep_range(10, 20);
618 			rxcw = er32(RXCW);
619 			if (rxcw & E1000_RXCW_SYNCH) {
620 				if (!(rxcw & E1000_RXCW_IV)) {
621 					mac->serdes_has_link = true;
622 					e_dbg("SERDES: Link up - autoneg completed successfully.\n");
623 				} else {
624 					mac->serdes_has_link = false;
625 					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");
626 				}
627 			} else {
628 				mac->serdes_has_link = false;
629 				e_dbg("SERDES: Link down - no sync.\n");
630 			}
631 		} else {
632 			mac->serdes_has_link = false;
633 			e_dbg("SERDES: Link down - autoneg failed\n");
634 		}
635 	}
636 
637 	return 0;
638 }
639 
640 /**
641  *  e1000_set_default_fc_generic - Set flow control default values
642  *  @hw: pointer to the HW structure
643  *
644  *  Read the EEPROM for the default values for flow control and store the
645  *  values.
646  **/
647 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
648 {
649 	s32 ret_val;
650 	u16 nvm_data;
651 
652 	/* Read and store word 0x0F of the EEPROM. This word contains bits
653 	 * that determine the hardware's default PAUSE (flow control) mode,
654 	 * a bit that determines whether the HW defaults to enabling or
655 	 * disabling auto-negotiation, and the direction of the
656 	 * SW defined pins. If there is no SW over-ride of the flow
657 	 * control setting, then the variable hw->fc will
658 	 * be initialized based on a value in the EEPROM.
659 	 */
660 	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
661 
662 	if (ret_val) {
663 		e_dbg("NVM Read Error\n");
664 		return ret_val;
665 	}
666 
667 	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
668 		hw->fc.requested_mode = e1000_fc_none;
669 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
670 		hw->fc.requested_mode = e1000_fc_tx_pause;
671 	else
672 		hw->fc.requested_mode = e1000_fc_full;
673 
674 	return 0;
675 }
676 
677 /**
678  *  e1000e_setup_link_generic - Setup flow control and link settings
679  *  @hw: pointer to the HW structure
680  *
681  *  Determines which flow control settings to use, then configures flow
682  *  control.  Calls the appropriate media-specific link configuration
683  *  function.  Assuming the adapter has a valid link partner, a valid link
684  *  should be established.  Assumes the hardware has previously been reset
685  *  and the transmitter and receiver are not enabled.
686  **/
687 s32 e1000e_setup_link_generic(struct e1000_hw *hw)
688 {
689 	s32 ret_val;
690 
691 	/* In the case of the phy reset being blocked, we already have a link.
692 	 * We do not need to set it up again.
693 	 */
694 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
695 		return 0;
696 
697 	/* If requested flow control is set to default, set flow control
698 	 * based on the EEPROM flow control settings.
699 	 */
700 	if (hw->fc.requested_mode == e1000_fc_default) {
701 		ret_val = e1000_set_default_fc_generic(hw);
702 		if (ret_val)
703 			return ret_val;
704 	}
705 
706 	/* Save off the requested flow control mode for use later.  Depending
707 	 * on the link partner's capabilities, we may or may not use this mode.
708 	 */
709 	hw->fc.current_mode = hw->fc.requested_mode;
710 
711 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
712 
713 	/* Call the necessary media_type subroutine to configure the link. */
714 	ret_val = hw->mac.ops.setup_physical_interface(hw);
715 	if (ret_val)
716 		return ret_val;
717 
718 	/* Initialize the flow control address, type, and PAUSE timer
719 	 * registers to their default values.  This is done even if flow
720 	 * control is disabled, because it does not hurt anything to
721 	 * initialize these registers.
722 	 */
723 	e_dbg("Initializing the Flow Control address, type and timer regs\n");
724 	ew32(FCT, FLOW_CONTROL_TYPE);
725 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
726 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
727 
728 	ew32(FCTTV, hw->fc.pause_time);
729 
730 	return e1000e_set_fc_watermarks(hw);
731 }
732 
733 /**
734  *  e1000_commit_fc_settings_generic - Configure flow control
735  *  @hw: pointer to the HW structure
736  *
737  *  Write the flow control settings to the Transmit Config Word Register (TXCW)
738  *  base on the flow control settings in e1000_mac_info.
739  **/
740 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
741 {
742 	struct e1000_mac_info *mac = &hw->mac;
743 	u32 txcw;
744 
745 	/* Check for a software override of the flow control settings, and
746 	 * setup the device accordingly.  If auto-negotiation is enabled, then
747 	 * software will have to set the "PAUSE" bits to the correct value in
748 	 * the Transmit Config Word Register (TXCW) and re-start auto-
749 	 * negotiation.  However, if auto-negotiation is disabled, then
750 	 * software will have to manually configure the two flow control enable
751 	 * bits in the CTRL register.
752 	 *
753 	 * The possible values of the "fc" parameter are:
754 	 *      0:  Flow control is completely disabled
755 	 *      1:  Rx flow control is enabled (we can receive pause frames,
756 	 *          but not send pause frames).
757 	 *      2:  Tx flow control is enabled (we can send pause frames but we
758 	 *          do not support receiving pause frames).
759 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
760 	 */
761 	switch (hw->fc.current_mode) {
762 	case e1000_fc_none:
763 		/* Flow control completely disabled by a software over-ride. */
764 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
765 		break;
766 	case e1000_fc_rx_pause:
767 		/* Rx Flow control is enabled and Tx Flow control is disabled
768 		 * by a software over-ride. Since there really isn't a way to
769 		 * advertise that we are capable of Rx Pause ONLY, we will
770 		 * advertise that we support both symmetric and asymmetric Rx
771 		 * PAUSE.  Later, we will disable the adapter's ability to send
772 		 * PAUSE frames.
773 		 */
774 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
775 		break;
776 	case e1000_fc_tx_pause:
777 		/* Tx Flow control is enabled, and Rx Flow control is disabled,
778 		 * by a software over-ride.
779 		 */
780 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
781 		break;
782 	case e1000_fc_full:
783 		/* Flow control (both Rx and Tx) is enabled by a software
784 		 * over-ride.
785 		 */
786 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
787 		break;
788 	default:
789 		e_dbg("Flow control param set incorrectly\n");
790 		return -E1000_ERR_CONFIG;
791 	}
792 
793 	ew32(TXCW, txcw);
794 	mac->txcw = txcw;
795 
796 	return 0;
797 }
798 
799 /**
800  *  e1000_poll_fiber_serdes_link_generic - Poll for link up
801  *  @hw: pointer to the HW structure
802  *
803  *  Polls for link up by reading the status register, if link fails to come
804  *  up with auto-negotiation, then the link is forced if a signal is detected.
805  **/
806 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
807 {
808 	struct e1000_mac_info *mac = &hw->mac;
809 	u32 i, status;
810 	s32 ret_val;
811 
812 	/* If we have a signal (the cable is plugged in, or assumed true for
813 	 * serdes media) then poll for a "Link-Up" indication in the Device
814 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
815 	 * seconds (Auto-negotiation should complete in less than 500
816 	 * milliseconds even if the other end is doing it in SW).
817 	 */
818 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
819 		usleep_range(10000, 20000);
820 		status = er32(STATUS);
821 		if (status & E1000_STATUS_LU)
822 			break;
823 	}
824 	if (i == FIBER_LINK_UP_LIMIT) {
825 		e_dbg("Never got a valid link from auto-neg!!!\n");
826 		mac->autoneg_failed = true;
827 		/* AutoNeg failed to achieve a link, so we'll call
828 		 * mac->check_for_link. This routine will force the
829 		 * link up if we detect a signal. This will allow us to
830 		 * communicate with non-autonegotiating link partners.
831 		 */
832 		ret_val = mac->ops.check_for_link(hw);
833 		if (ret_val) {
834 			e_dbg("Error while checking for link\n");
835 			return ret_val;
836 		}
837 		mac->autoneg_failed = false;
838 	} else {
839 		mac->autoneg_failed = false;
840 		e_dbg("Valid Link Found\n");
841 	}
842 
843 	return 0;
844 }
845 
846 /**
847  *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
848  *  @hw: pointer to the HW structure
849  *
850  *  Configures collision distance and flow control for fiber and serdes
851  *  links.  Upon successful setup, poll for link.
852  **/
853 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
854 {
855 	u32 ctrl;
856 	s32 ret_val;
857 
858 	ctrl = er32(CTRL);
859 
860 	/* Take the link out of reset */
861 	ctrl &= ~E1000_CTRL_LRST;
862 
863 	hw->mac.ops.config_collision_dist(hw);
864 
865 	ret_val = e1000_commit_fc_settings_generic(hw);
866 	if (ret_val)
867 		return ret_val;
868 
869 	/* Since auto-negotiation is enabled, take the link out of reset (the
870 	 * link will be in reset, because we previously reset the chip). This
871 	 * will restart auto-negotiation.  If auto-negotiation is successful
872 	 * then the link-up status bit will be set and the flow control enable
873 	 * bits (RFCE and TFCE) will be set according to their negotiated value.
874 	 */
875 	e_dbg("Auto-negotiation enabled\n");
876 
877 	ew32(CTRL, ctrl);
878 	e1e_flush();
879 	usleep_range(1000, 2000);
880 
881 	/* For these adapters, the SW definable pin 1 is set when the optics
882 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
883 	 * indication.
884 	 */
885 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
886 	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
887 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
888 	} else {
889 		e_dbg("No signal detected\n");
890 	}
891 
892 	return ret_val;
893 }
894 
895 /**
896  *  e1000e_config_collision_dist_generic - Configure collision distance
897  *  @hw: pointer to the HW structure
898  *
899  *  Configures the collision distance to the default value and is used
900  *  during link setup.
901  **/
902 void e1000e_config_collision_dist_generic(struct e1000_hw *hw)
903 {
904 	u32 tctl;
905 
906 	tctl = er32(TCTL);
907 
908 	tctl &= ~E1000_TCTL_COLD;
909 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
910 
911 	ew32(TCTL, tctl);
912 	e1e_flush();
913 }
914 
915 /**
916  *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
917  *  @hw: pointer to the HW structure
918  *
919  *  Sets the flow control high/low threshold (watermark) registers.  If
920  *  flow control XON frame transmission is enabled, then set XON frame
921  *  transmission as well.
922  **/
923 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
924 {
925 	u32 fcrtl = 0, fcrth = 0;
926 
927 	/* Set the flow control receive threshold registers.  Normally,
928 	 * these registers will be set to a default threshold that may be
929 	 * adjusted later by the driver's runtime code.  However, if the
930 	 * ability to transmit pause frames is not enabled, then these
931 	 * registers will be set to 0.
932 	 */
933 	if (hw->fc.current_mode & e1000_fc_tx_pause) {
934 		/* We need to set up the Receive Threshold high and low water
935 		 * marks as well as (optionally) enabling the transmission of
936 		 * XON frames.
937 		 */
938 		fcrtl = hw->fc.low_water;
939 		if (hw->fc.send_xon)
940 			fcrtl |= E1000_FCRTL_XONE;
941 
942 		fcrth = hw->fc.high_water;
943 	}
944 	ew32(FCRTL, fcrtl);
945 	ew32(FCRTH, fcrth);
946 
947 	return 0;
948 }
949 
950 /**
951  *  e1000e_force_mac_fc - Force the MAC's flow control settings
952  *  @hw: pointer to the HW structure
953  *
954  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
955  *  device control register to reflect the adapter settings.  TFCE and RFCE
956  *  need to be explicitly set by software when a copper PHY is used because
957  *  autonegotiation is managed by the PHY rather than the MAC.  Software must
958  *  also configure these bits when link is forced on a fiber connection.
959  **/
960 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
961 {
962 	u32 ctrl;
963 
964 	ctrl = er32(CTRL);
965 
966 	/* Because we didn't get link via the internal auto-negotiation
967 	 * mechanism (we either forced link or we got link via PHY
968 	 * auto-neg), we have to manually enable/disable transmit an
969 	 * receive flow control.
970 	 *
971 	 * The "Case" statement below enables/disable flow control
972 	 * according to the "hw->fc.current_mode" parameter.
973 	 *
974 	 * The possible values of the "fc" parameter are:
975 	 *      0:  Flow control is completely disabled
976 	 *      1:  Rx flow control is enabled (we can receive pause
977 	 *          frames but not send pause frames).
978 	 *      2:  Tx flow control is enabled (we can send pause frames
979 	 *          frames but we do not receive pause frames).
980 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
981 	 *  other:  No other values should be possible at this point.
982 	 */
983 	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
984 
985 	switch (hw->fc.current_mode) {
986 	case e1000_fc_none:
987 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
988 		break;
989 	case e1000_fc_rx_pause:
990 		ctrl &= (~E1000_CTRL_TFCE);
991 		ctrl |= E1000_CTRL_RFCE;
992 		break;
993 	case e1000_fc_tx_pause:
994 		ctrl &= (~E1000_CTRL_RFCE);
995 		ctrl |= E1000_CTRL_TFCE;
996 		break;
997 	case e1000_fc_full:
998 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
999 		break;
1000 	default:
1001 		e_dbg("Flow control param set incorrectly\n");
1002 		return -E1000_ERR_CONFIG;
1003 	}
1004 
1005 	ew32(CTRL, ctrl);
1006 
1007 	return 0;
1008 }
1009 
1010 /**
1011  *  e1000e_config_fc_after_link_up - Configures flow control after link
1012  *  @hw: pointer to the HW structure
1013  *
1014  *  Checks the status of auto-negotiation after link up to ensure that the
1015  *  speed and duplex were not forced.  If the link needed to be forced, then
1016  *  flow control needs to be forced also.  If auto-negotiation is enabled
1017  *  and did not fail, then we configure flow control based on our link
1018  *  partner.
1019  **/
1020 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1021 {
1022 	struct e1000_mac_info *mac = &hw->mac;
1023 	s32 ret_val = 0;
1024 	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1025 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1026 	u16 speed, duplex;
1027 
1028 	/* Check for the case where we have fiber media and auto-neg failed
1029 	 * so we had to force link.  In this case, we need to force the
1030 	 * configuration of the MAC to match the "fc" parameter.
1031 	 */
1032 	if (mac->autoneg_failed) {
1033 		if (hw->phy.media_type == e1000_media_type_fiber ||
1034 		    hw->phy.media_type == e1000_media_type_internal_serdes)
1035 			ret_val = e1000e_force_mac_fc(hw);
1036 	} else {
1037 		if (hw->phy.media_type == e1000_media_type_copper)
1038 			ret_val = e1000e_force_mac_fc(hw);
1039 	}
1040 
1041 	if (ret_val) {
1042 		e_dbg("Error forcing flow control settings\n");
1043 		return ret_val;
1044 	}
1045 
1046 	/* Check for the case where we have copper media and auto-neg is
1047 	 * enabled.  In this case, we need to check and see if Auto-Neg
1048 	 * has completed, and if so, how the PHY and link partner has
1049 	 * flow control configured.
1050 	 */
1051 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1052 		/* Read the MII Status Register and check to see if AutoNeg
1053 		 * has completed.  We read this twice because this reg has
1054 		 * some "sticky" (latched) bits.
1055 		 */
1056 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1057 		if (ret_val)
1058 			return ret_val;
1059 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);
1060 		if (ret_val)
1061 			return ret_val;
1062 
1063 		if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) {
1064 			e_dbg("Copper PHY and Auto Neg has not completed.\n");
1065 			return ret_val;
1066 		}
1067 
1068 		/* The AutoNeg process has completed, so we now need to
1069 		 * read both the Auto Negotiation Advertisement
1070 		 * Register (Address 4) and the Auto_Negotiation Base
1071 		 * Page Ability Register (Address 5) to determine how
1072 		 * flow control was negotiated.
1073 		 */
1074 		ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg);
1075 		if (ret_val)
1076 			return ret_val;
1077 		ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg);
1078 		if (ret_val)
1079 			return ret_val;
1080 
1081 		/* Two bits in the Auto Negotiation Advertisement Register
1082 		 * (Address 4) and two bits in the Auto Negotiation Base
1083 		 * Page Ability Register (Address 5) determine flow control
1084 		 * for both the PHY and the link partner.  The following
1085 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1086 		 * 1999, describes these PAUSE resolution bits and how flow
1087 		 * control is determined based upon these settings.
1088 		 * NOTE:  DC = Don't Care
1089 		 *
1090 		 *   LOCAL DEVICE  |   LINK PARTNER
1091 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1092 		 *-------|---------|-------|---------|--------------------
1093 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1094 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1095 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1096 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1097 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1098 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1099 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1100 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1101 		 *
1102 		 * Are both PAUSE bits set to 1?  If so, this implies
1103 		 * Symmetric Flow Control is enabled at both ends.  The
1104 		 * ASM_DIR bits are irrelevant per the spec.
1105 		 *
1106 		 * For Symmetric Flow Control:
1107 		 *
1108 		 *   LOCAL DEVICE  |   LINK PARTNER
1109 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1110 		 *-------|---------|-------|---------|--------------------
1111 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
1112 		 *
1113 		 */
1114 		if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1115 		    (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) {
1116 			/* Now we need to check if the user selected Rx ONLY
1117 			 * of pause frames.  In this case, we had to advertise
1118 			 * FULL flow control because we could not advertise Rx
1119 			 * ONLY. Hence, we must now check to see if we need to
1120 			 * turn OFF the TRANSMISSION of PAUSE frames.
1121 			 */
1122 			if (hw->fc.requested_mode == e1000_fc_full) {
1123 				hw->fc.current_mode = e1000_fc_full;
1124 				e_dbg("Flow Control = FULL.\n");
1125 			} else {
1126 				hw->fc.current_mode = e1000_fc_rx_pause;
1127 				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1128 			}
1129 		}
1130 		/* For receiving PAUSE frames ONLY.
1131 		 *
1132 		 *   LOCAL DEVICE  |   LINK PARTNER
1133 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1134 		 *-------|---------|-------|---------|--------------------
1135 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1136 		 */
1137 		else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1138 			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1139 			 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1140 			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1141 			hw->fc.current_mode = e1000_fc_tx_pause;
1142 			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1143 		}
1144 		/* For transmitting PAUSE frames ONLY.
1145 		 *
1146 		 *   LOCAL DEVICE  |   LINK PARTNER
1147 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1148 		 *-------|---------|-------|---------|--------------------
1149 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1150 		 */
1151 		else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&
1152 			 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) &&
1153 			 !(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) &&
1154 			 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) {
1155 			hw->fc.current_mode = e1000_fc_rx_pause;
1156 			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1157 		} else {
1158 			/* Per the IEEE spec, at this point flow control
1159 			 * should be disabled.
1160 			 */
1161 			hw->fc.current_mode = e1000_fc_none;
1162 			e_dbg("Flow Control = NONE.\n");
1163 		}
1164 
1165 		/* Now we need to do one last check...  If we auto-
1166 		 * negotiated to HALF DUPLEX, flow control should not be
1167 		 * enabled per IEEE 802.3 spec.
1168 		 */
1169 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1170 		if (ret_val) {
1171 			e_dbg("Error getting link speed and duplex\n");
1172 			return ret_val;
1173 		}
1174 
1175 		if (duplex == HALF_DUPLEX)
1176 			hw->fc.current_mode = e1000_fc_none;
1177 
1178 		/* Now we call a subroutine to actually force the MAC
1179 		 * controller to use the correct flow control settings.
1180 		 */
1181 		ret_val = e1000e_force_mac_fc(hw);
1182 		if (ret_val) {
1183 			e_dbg("Error forcing flow control settings\n");
1184 			return ret_val;
1185 		}
1186 	}
1187 
1188 	/* Check for the case where we have SerDes media and auto-neg is
1189 	 * enabled.  In this case, we need to check and see if Auto-Neg
1190 	 * has completed, and if so, how the PHY and link partner has
1191 	 * flow control configured.
1192 	 */
1193 	if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1194 	    mac->autoneg) {
1195 		/* Read the PCS_LSTS and check to see if AutoNeg
1196 		 * has completed.
1197 		 */
1198 		pcs_status_reg = er32(PCS_LSTAT);
1199 
1200 		if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1201 			e_dbg("PCS Auto Neg has not completed.\n");
1202 			return ret_val;
1203 		}
1204 
1205 		/* The AutoNeg process has completed, so we now need to
1206 		 * read both the Auto Negotiation Advertisement
1207 		 * Register (PCS_ANADV) and the Auto_Negotiation Base
1208 		 * Page Ability Register (PCS_LPAB) to determine how
1209 		 * flow control was negotiated.
1210 		 */
1211 		pcs_adv_reg = er32(PCS_ANADV);
1212 		pcs_lp_ability_reg = er32(PCS_LPAB);
1213 
1214 		/* Two bits in the Auto Negotiation Advertisement Register
1215 		 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1216 		 * Page Ability Register (PCS_LPAB) determine flow control
1217 		 * for both the PHY and the link partner.  The following
1218 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1219 		 * 1999, describes these PAUSE resolution bits and how flow
1220 		 * control is determined based upon these settings.
1221 		 * NOTE:  DC = Don't Care
1222 		 *
1223 		 *   LOCAL DEVICE  |   LINK PARTNER
1224 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1225 		 *-------|---------|-------|---------|--------------------
1226 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1227 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
1228 		 *   0   |    1    |   1   |    0    | e1000_fc_none
1229 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1230 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
1231 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1232 		 *   1   |    1    |   0   |    0    | e1000_fc_none
1233 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1234 		 *
1235 		 * Are both PAUSE bits set to 1?  If so, this implies
1236 		 * Symmetric Flow Control is enabled at both ends.  The
1237 		 * ASM_DIR bits are irrelevant per the spec.
1238 		 *
1239 		 * For Symmetric Flow Control:
1240 		 *
1241 		 *   LOCAL DEVICE  |   LINK PARTNER
1242 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1243 		 *-------|---------|-------|---------|--------------------
1244 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1245 		 *
1246 		 */
1247 		if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1248 		    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1249 			/* Now we need to check if the user selected Rx ONLY
1250 			 * of pause frames.  In this case, we had to advertise
1251 			 * FULL flow control because we could not advertise Rx
1252 			 * ONLY. Hence, we must now check to see if we need to
1253 			 * turn OFF the TRANSMISSION of PAUSE frames.
1254 			 */
1255 			if (hw->fc.requested_mode == e1000_fc_full) {
1256 				hw->fc.current_mode = e1000_fc_full;
1257 				e_dbg("Flow Control = FULL.\n");
1258 			} else {
1259 				hw->fc.current_mode = e1000_fc_rx_pause;
1260 				e_dbg("Flow Control = Rx PAUSE frames only.\n");
1261 			}
1262 		}
1263 		/* For receiving PAUSE frames ONLY.
1264 		 *
1265 		 *   LOCAL DEVICE  |   LINK PARTNER
1266 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1267 		 *-------|---------|-------|---------|--------------------
1268 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1269 		 */
1270 		else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1271 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1272 			 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1273 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1274 			hw->fc.current_mode = e1000_fc_tx_pause;
1275 			e_dbg("Flow Control = Tx PAUSE frames only.\n");
1276 		}
1277 		/* For transmitting PAUSE frames ONLY.
1278 		 *
1279 		 *   LOCAL DEVICE  |   LINK PARTNER
1280 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1281 		 *-------|---------|-------|---------|--------------------
1282 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1283 		 */
1284 		else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1285 			 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1286 			 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1287 			 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1288 			hw->fc.current_mode = e1000_fc_rx_pause;
1289 			e_dbg("Flow Control = Rx PAUSE frames only.\n");
1290 		} else {
1291 			/* Per the IEEE spec, at this point flow control
1292 			 * should be disabled.
1293 			 */
1294 			hw->fc.current_mode = e1000_fc_none;
1295 			e_dbg("Flow Control = NONE.\n");
1296 		}
1297 
1298 		/* Now we call a subroutine to actually force the MAC
1299 		 * controller to use the correct flow control settings.
1300 		 */
1301 		pcs_ctrl_reg = er32(PCS_LCTL);
1302 		pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1303 		ew32(PCS_LCTL, pcs_ctrl_reg);
1304 
1305 		ret_val = e1000e_force_mac_fc(hw);
1306 		if (ret_val) {
1307 			e_dbg("Error forcing flow control settings\n");
1308 			return ret_val;
1309 		}
1310 	}
1311 
1312 	return 0;
1313 }
1314 
1315 /**
1316  *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1317  *  @hw: pointer to the HW structure
1318  *  @speed: stores the current speed
1319  *  @duplex: stores the current duplex
1320  *
1321  *  Read the status register for the current speed/duplex and store the current
1322  *  speed and duplex for copper connections.
1323  **/
1324 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1325 				       u16 *duplex)
1326 {
1327 	u32 status;
1328 
1329 	status = er32(STATUS);
1330 	if (status & E1000_STATUS_SPEED_1000)
1331 		*speed = SPEED_1000;
1332 	else if (status & E1000_STATUS_SPEED_100)
1333 		*speed = SPEED_100;
1334 	else
1335 		*speed = SPEED_10;
1336 
1337 	if (status & E1000_STATUS_FD)
1338 		*duplex = FULL_DUPLEX;
1339 	else
1340 		*duplex = HALF_DUPLEX;
1341 
1342 	e_dbg("%u Mbps, %s Duplex\n",
1343 	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1344 	      *duplex == FULL_DUPLEX ? "Full" : "Half");
1345 
1346 	return 0;
1347 }
1348 
1349 /**
1350  *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1351  *  @hw: pointer to the HW structure
1352  *  @speed: stores the current speed
1353  *  @duplex: stores the current duplex
1354  *
1355  *  Sets the speed and duplex to gigabit full duplex (the only possible option)
1356  *  for fiber/serdes links.
1357  **/
1358 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused
1359 					     *hw, u16 *speed, u16 *duplex)
1360 {
1361 	*speed = SPEED_1000;
1362 	*duplex = FULL_DUPLEX;
1363 
1364 	return 0;
1365 }
1366 
1367 /**
1368  *  e1000e_get_hw_semaphore - Acquire hardware semaphore
1369  *  @hw: pointer to the HW structure
1370  *
1371  *  Acquire the HW semaphore to access the PHY or NVM
1372  **/
1373 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1374 {
1375 	u32 swsm;
1376 	s32 timeout = hw->nvm.word_size + 1;
1377 	s32 i = 0;
1378 
1379 	/* Get the SW semaphore */
1380 	while (i < timeout) {
1381 		swsm = er32(SWSM);
1382 		if (!(swsm & E1000_SWSM_SMBI))
1383 			break;
1384 
1385 		usleep_range(50, 100);
1386 		i++;
1387 	}
1388 
1389 	if (i == timeout) {
1390 		e_dbg("Driver can't access device - SMBI bit is set.\n");
1391 		return -E1000_ERR_NVM;
1392 	}
1393 
1394 	/* Get the FW semaphore. */
1395 	for (i = 0; i < timeout; i++) {
1396 		swsm = er32(SWSM);
1397 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1398 
1399 		/* Semaphore acquired if bit latched */
1400 		if (er32(SWSM) & E1000_SWSM_SWESMBI)
1401 			break;
1402 
1403 		usleep_range(50, 100);
1404 	}
1405 
1406 	if (i == timeout) {
1407 		/* Release semaphores */
1408 		e1000e_put_hw_semaphore(hw);
1409 		e_dbg("Driver can't access the NVM\n");
1410 		return -E1000_ERR_NVM;
1411 	}
1412 
1413 	return 0;
1414 }
1415 
1416 /**
1417  *  e1000e_put_hw_semaphore - Release hardware semaphore
1418  *  @hw: pointer to the HW structure
1419  *
1420  *  Release hardware semaphore used to access the PHY or NVM
1421  **/
1422 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1423 {
1424 	u32 swsm;
1425 
1426 	swsm = er32(SWSM);
1427 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1428 	ew32(SWSM, swsm);
1429 }
1430 
1431 /**
1432  *  e1000e_get_auto_rd_done - Check for auto read completion
1433  *  @hw: pointer to the HW structure
1434  *
1435  *  Check EEPROM for Auto Read done bit.
1436  **/
1437 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1438 {
1439 	s32 i = 0;
1440 
1441 	while (i < AUTO_READ_DONE_TIMEOUT) {
1442 		if (er32(EECD) & E1000_EECD_AUTO_RD)
1443 			break;
1444 		usleep_range(1000, 2000);
1445 		i++;
1446 	}
1447 
1448 	if (i == AUTO_READ_DONE_TIMEOUT) {
1449 		e_dbg("Auto read by HW from NVM has not completed.\n");
1450 		return -E1000_ERR_RESET;
1451 	}
1452 
1453 	return 0;
1454 }
1455 
1456 /**
1457  *  e1000e_valid_led_default - Verify a valid default LED config
1458  *  @hw: pointer to the HW structure
1459  *  @data: pointer to the NVM (EEPROM)
1460  *
1461  *  Read the EEPROM for the current default LED configuration.  If the
1462  *  LED configuration is not valid, set to a valid LED configuration.
1463  **/
1464 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1465 {
1466 	s32 ret_val;
1467 
1468 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1469 	if (ret_val) {
1470 		e_dbg("NVM Read Error\n");
1471 		return ret_val;
1472 	}
1473 
1474 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1475 		*data = ID_LED_DEFAULT;
1476 
1477 	return 0;
1478 }
1479 
1480 /**
1481  *  e1000e_id_led_init_generic -
1482  *  @hw: pointer to the HW structure
1483  *
1484  **/
1485 s32 e1000e_id_led_init_generic(struct e1000_hw *hw)
1486 {
1487 	struct e1000_mac_info *mac = &hw->mac;
1488 	s32 ret_val;
1489 	const u32 ledctl_mask = 0x000000FF;
1490 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1491 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1492 	u16 data, i, temp;
1493 	const u16 led_mask = 0x0F;
1494 
1495 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1496 	if (ret_val)
1497 		return ret_val;
1498 
1499 	mac->ledctl_default = er32(LEDCTL);
1500 	mac->ledctl_mode1 = mac->ledctl_default;
1501 	mac->ledctl_mode2 = mac->ledctl_default;
1502 
1503 	for (i = 0; i < 4; i++) {
1504 		temp = (data >> (i << 2)) & led_mask;
1505 		switch (temp) {
1506 		case ID_LED_ON1_DEF2:
1507 		case ID_LED_ON1_ON2:
1508 		case ID_LED_ON1_OFF2:
1509 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1510 			mac->ledctl_mode1 |= ledctl_on << (i << 3);
1511 			break;
1512 		case ID_LED_OFF1_DEF2:
1513 		case ID_LED_OFF1_ON2:
1514 		case ID_LED_OFF1_OFF2:
1515 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1516 			mac->ledctl_mode1 |= ledctl_off << (i << 3);
1517 			break;
1518 		default:
1519 			/* Do nothing */
1520 			break;
1521 		}
1522 		switch (temp) {
1523 		case ID_LED_DEF1_ON2:
1524 		case ID_LED_ON1_ON2:
1525 		case ID_LED_OFF1_ON2:
1526 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1527 			mac->ledctl_mode2 |= ledctl_on << (i << 3);
1528 			break;
1529 		case ID_LED_DEF1_OFF2:
1530 		case ID_LED_ON1_OFF2:
1531 		case ID_LED_OFF1_OFF2:
1532 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1533 			mac->ledctl_mode2 |= ledctl_off << (i << 3);
1534 			break;
1535 		default:
1536 			/* Do nothing */
1537 			break;
1538 		}
1539 	}
1540 
1541 	return 0;
1542 }
1543 
1544 /**
1545  *  e1000e_setup_led_generic - Configures SW controllable LED
1546  *  @hw: pointer to the HW structure
1547  *
1548  *  This prepares the SW controllable LED for use and saves the current state
1549  *  of the LED so it can be later restored.
1550  **/
1551 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1552 {
1553 	u32 ledctl;
1554 
1555 	if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1556 		return -E1000_ERR_CONFIG;
1557 
1558 	if (hw->phy.media_type == e1000_media_type_fiber) {
1559 		ledctl = er32(LEDCTL);
1560 		hw->mac.ledctl_default = ledctl;
1561 		/* Turn off LED0 */
1562 		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1563 			    E1000_LEDCTL_LED0_MODE_MASK);
1564 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1565 			   E1000_LEDCTL_LED0_MODE_SHIFT);
1566 		ew32(LEDCTL, ledctl);
1567 	} else if (hw->phy.media_type == e1000_media_type_copper) {
1568 		ew32(LEDCTL, hw->mac.ledctl_mode1);
1569 	}
1570 
1571 	return 0;
1572 }
1573 
1574 /**
1575  *  e1000e_cleanup_led_generic - Set LED config to default operation
1576  *  @hw: pointer to the HW structure
1577  *
1578  *  Remove the current LED configuration and set the LED configuration
1579  *  to the default value, saved from the EEPROM.
1580  **/
1581 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1582 {
1583 	ew32(LEDCTL, hw->mac.ledctl_default);
1584 	return 0;
1585 }
1586 
1587 /**
1588  *  e1000e_blink_led_generic - Blink LED
1589  *  @hw: pointer to the HW structure
1590  *
1591  *  Blink the LEDs which are set to be on.
1592  **/
1593 s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1594 {
1595 	u32 ledctl_blink = 0;
1596 	u32 i;
1597 
1598 	if (hw->phy.media_type == e1000_media_type_fiber) {
1599 		/* always blink LED0 for PCI-E fiber */
1600 		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1601 		    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1602 	} else {
1603 		/* Set the blink bit for each LED that's "on" (0x0E)
1604 		 * (or "off" if inverted) in ledctl_mode2.  The blink
1605 		 * logic in hardware only works when mode is set to "on"
1606 		 * so it must be changed accordingly when the mode is
1607 		 * "off" and inverted.
1608 		 */
1609 		ledctl_blink = hw->mac.ledctl_mode2;
1610 		for (i = 0; i < 32; i += 8) {
1611 			u32 mode = (hw->mac.ledctl_mode2 >> i) &
1612 			    E1000_LEDCTL_LED0_MODE_MASK;
1613 			u32 led_default = hw->mac.ledctl_default >> i;
1614 
1615 			if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1616 			     (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1617 			    ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1618 			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1619 				ledctl_blink &=
1620 				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1621 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1622 						 E1000_LEDCTL_MODE_LED_ON) << i;
1623 			}
1624 		}
1625 	}
1626 
1627 	ew32(LEDCTL, ledctl_blink);
1628 
1629 	return 0;
1630 }
1631 
1632 /**
1633  *  e1000e_led_on_generic - Turn LED on
1634  *  @hw: pointer to the HW structure
1635  *
1636  *  Turn LED on.
1637  **/
1638 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1639 {
1640 	u32 ctrl;
1641 
1642 	switch (hw->phy.media_type) {
1643 	case e1000_media_type_fiber:
1644 		ctrl = er32(CTRL);
1645 		ctrl &= ~E1000_CTRL_SWDPIN0;
1646 		ctrl |= E1000_CTRL_SWDPIO0;
1647 		ew32(CTRL, ctrl);
1648 		break;
1649 	case e1000_media_type_copper:
1650 		ew32(LEDCTL, hw->mac.ledctl_mode2);
1651 		break;
1652 	default:
1653 		break;
1654 	}
1655 
1656 	return 0;
1657 }
1658 
1659 /**
1660  *  e1000e_led_off_generic - Turn LED off
1661  *  @hw: pointer to the HW structure
1662  *
1663  *  Turn LED off.
1664  **/
1665 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1666 {
1667 	u32 ctrl;
1668 
1669 	switch (hw->phy.media_type) {
1670 	case e1000_media_type_fiber:
1671 		ctrl = er32(CTRL);
1672 		ctrl |= E1000_CTRL_SWDPIN0;
1673 		ctrl |= E1000_CTRL_SWDPIO0;
1674 		ew32(CTRL, ctrl);
1675 		break;
1676 	case e1000_media_type_copper:
1677 		ew32(LEDCTL, hw->mac.ledctl_mode1);
1678 		break;
1679 	default:
1680 		break;
1681 	}
1682 
1683 	return 0;
1684 }
1685 
1686 /**
1687  *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1688  *  @hw: pointer to the HW structure
1689  *  @no_snoop: bitmap of snoop events
1690  *
1691  *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1692  **/
1693 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1694 {
1695 	u32 gcr;
1696 
1697 	if (no_snoop) {
1698 		gcr = er32(GCR);
1699 		gcr &= ~(PCIE_NO_SNOOP_ALL);
1700 		gcr |= no_snoop;
1701 		ew32(GCR, gcr);
1702 	}
1703 }
1704 
1705 /**
1706  *  e1000e_disable_pcie_master - Disables PCI-express master access
1707  *  @hw: pointer to the HW structure
1708  *
1709  *  Returns 0 if successful, else returns -10
1710  *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1711  *  the master requests to be disabled.
1712  *
1713  *  Disables PCI-Express master access and verifies there are no pending
1714  *  requests.
1715  **/
1716 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1717 {
1718 	u32 ctrl;
1719 	s32 timeout = MASTER_DISABLE_TIMEOUT;
1720 
1721 	ctrl = er32(CTRL);
1722 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1723 	ew32(CTRL, ctrl);
1724 
1725 	while (timeout) {
1726 		if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1727 			break;
1728 		usleep_range(100, 200);
1729 		timeout--;
1730 	}
1731 
1732 	if (!timeout) {
1733 		e_dbg("Master requests are pending.\n");
1734 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
1735 	}
1736 
1737 	return 0;
1738 }
1739 
1740 /**
1741  *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1742  *  @hw: pointer to the HW structure
1743  *
1744  *  Reset the Adaptive Interframe Spacing throttle to default values.
1745  **/
1746 void e1000e_reset_adaptive(struct e1000_hw *hw)
1747 {
1748 	struct e1000_mac_info *mac = &hw->mac;
1749 
1750 	if (!mac->adaptive_ifs) {
1751 		e_dbg("Not in Adaptive IFS mode!\n");
1752 		return;
1753 	}
1754 
1755 	mac->current_ifs_val = 0;
1756 	mac->ifs_min_val = IFS_MIN;
1757 	mac->ifs_max_val = IFS_MAX;
1758 	mac->ifs_step_size = IFS_STEP;
1759 	mac->ifs_ratio = IFS_RATIO;
1760 
1761 	mac->in_ifs_mode = false;
1762 	ew32(AIT, 0);
1763 }
1764 
1765 /**
1766  *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
1767  *  @hw: pointer to the HW structure
1768  *
1769  *  Update the Adaptive Interframe Spacing Throttle value based on the
1770  *  time between transmitted packets and time between collisions.
1771  **/
1772 void e1000e_update_adaptive(struct e1000_hw *hw)
1773 {
1774 	struct e1000_mac_info *mac = &hw->mac;
1775 
1776 	if (!mac->adaptive_ifs) {
1777 		e_dbg("Not in Adaptive IFS mode!\n");
1778 		return;
1779 	}
1780 
1781 	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1782 		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1783 			mac->in_ifs_mode = true;
1784 			if (mac->current_ifs_val < mac->ifs_max_val) {
1785 				if (!mac->current_ifs_val)
1786 					mac->current_ifs_val = mac->ifs_min_val;
1787 				else
1788 					mac->current_ifs_val +=
1789 					    mac->ifs_step_size;
1790 				ew32(AIT, mac->current_ifs_val);
1791 			}
1792 		}
1793 	} else {
1794 		if (mac->in_ifs_mode &&
1795 		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1796 			mac->current_ifs_val = 0;
1797 			mac->in_ifs_mode = false;
1798 			ew32(AIT, 0);
1799 		}
1800 	}
1801 }
1802