1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #include "e1000.h" 23 24 /** 25 * e1000e_get_bus_info_pcie - Get PCIe bus information 26 * @hw: pointer to the HW structure 27 * 28 * Determines and stores the system bus information for a particular 29 * network interface. The following bus information is determined and stored: 30 * bus speed, bus width, type (PCIe), and PCIe function. 31 **/ 32 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) 33 { 34 struct e1000_mac_info *mac = &hw->mac; 35 struct e1000_bus_info *bus = &hw->bus; 36 struct e1000_adapter *adapter = hw->adapter; 37 u16 pcie_link_status, cap_offset; 38 39 cap_offset = adapter->pdev->pcie_cap; 40 if (!cap_offset) { 41 bus->width = e1000_bus_width_unknown; 42 } else { 43 pci_read_config_word(adapter->pdev, 44 cap_offset + PCIE_LINK_STATUS, 45 &pcie_link_status); 46 bus->width = (enum e1000_bus_width)((pcie_link_status & 47 PCIE_LINK_WIDTH_MASK) >> 48 PCIE_LINK_WIDTH_SHIFT); 49 } 50 51 mac->ops.set_lan_id(hw); 52 53 return 0; 54 } 55 56 /** 57 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 58 * 59 * @hw: pointer to the HW structure 60 * 61 * Determines the LAN function id by reading memory-mapped registers 62 * and swaps the port value if requested. 63 **/ 64 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 65 { 66 struct e1000_bus_info *bus = &hw->bus; 67 u32 reg; 68 69 /* The status register reports the correct function number 70 * for the device regardless of function swap state. 71 */ 72 reg = er32(STATUS); 73 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 74 } 75 76 /** 77 * e1000_set_lan_id_single_port - Set LAN id for a single port device 78 * @hw: pointer to the HW structure 79 * 80 * Sets the LAN function id to zero for a single port device. 81 **/ 82 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 83 { 84 struct e1000_bus_info *bus = &hw->bus; 85 86 bus->func = 0; 87 } 88 89 /** 90 * e1000_clear_vfta_generic - Clear VLAN filter table 91 * @hw: pointer to the HW structure 92 * 93 * Clears the register array which contains the VLAN filter table by 94 * setting all the values to 0. 95 **/ 96 void e1000_clear_vfta_generic(struct e1000_hw *hw) 97 { 98 u32 offset; 99 100 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 101 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 102 e1e_flush(); 103 } 104 } 105 106 /** 107 * e1000_write_vfta_generic - Write value to VLAN filter table 108 * @hw: pointer to the HW structure 109 * @offset: register offset in VLAN filter table 110 * @value: register value written to VLAN filter table 111 * 112 * Writes value at the given offset in the register array which stores 113 * the VLAN filter table. 114 **/ 115 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 116 { 117 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 118 e1e_flush(); 119 } 120 121 /** 122 * e1000e_init_rx_addrs - Initialize receive address's 123 * @hw: pointer to the HW structure 124 * @rar_count: receive address registers 125 * 126 * Setup the receive address registers by setting the base receive address 127 * register to the devices MAC address and clearing all the other receive 128 * address registers to 0. 129 **/ 130 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 131 { 132 u32 i; 133 u8 mac_addr[ETH_ALEN] = { 0 }; 134 135 /* Setup the receive address */ 136 e_dbg("Programming MAC Address into RAR[0]\n"); 137 138 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 139 140 /* Zero out the other (rar_entry_count - 1) receive addresses */ 141 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 142 for (i = 1; i < rar_count; i++) 143 hw->mac.ops.rar_set(hw, mac_addr, i); 144 } 145 146 /** 147 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 148 * @hw: pointer to the HW structure 149 * 150 * Checks the nvm for an alternate MAC address. An alternate MAC address 151 * can be setup by pre-boot software and must be treated like a permanent 152 * address and must override the actual permanent MAC address. If an 153 * alternate MAC address is found it is programmed into RAR0, replacing 154 * the permanent address that was installed into RAR0 by the Si on reset. 155 * This function will return SUCCESS unless it encounters an error while 156 * reading the EEPROM. 157 **/ 158 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 159 { 160 u32 i; 161 s32 ret_val; 162 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 163 u8 alt_mac_addr[ETH_ALEN]; 164 165 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); 166 if (ret_val) 167 return ret_val; 168 169 /* not supported on 82573 */ 170 if (hw->mac.type == e1000_82573) 171 return 0; 172 173 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 174 &nvm_alt_mac_addr_offset); 175 if (ret_val) { 176 e_dbg("NVM Read Error\n"); 177 return ret_val; 178 } 179 180 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 181 (nvm_alt_mac_addr_offset == 0x0000)) 182 /* There is no Alternate MAC Address */ 183 return 0; 184 185 if (hw->bus.func == E1000_FUNC_1) 186 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 187 for (i = 0; i < ETH_ALEN; i += 2) { 188 offset = nvm_alt_mac_addr_offset + (i >> 1); 189 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 190 if (ret_val) { 191 e_dbg("NVM Read Error\n"); 192 return ret_val; 193 } 194 195 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 196 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 197 } 198 199 /* if multicast bit is set, the alternate address will not be used */ 200 if (is_multicast_ether_addr(alt_mac_addr)) { 201 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 202 return 0; 203 } 204 205 /* We have a valid alternate MAC address, and we want to treat it the 206 * same as the normal permanent MAC address stored by the HW into the 207 * RAR. Do this by mapping this address into RAR0. 208 */ 209 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 210 211 return 0; 212 } 213 214 /** 215 * e1000e_rar_set_generic - Set receive address register 216 * @hw: pointer to the HW structure 217 * @addr: pointer to the receive address 218 * @index: receive address array register 219 * 220 * Sets the receive address array register at index to the address passed 221 * in by addr. 222 **/ 223 void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 224 { 225 u32 rar_low, rar_high; 226 227 /* HW expects these in little endian so we reverse the byte order 228 * from network order (big endian) to little endian 229 */ 230 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 231 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 232 233 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 234 235 /* If MAC address zero, no need to set the AV bit */ 236 if (rar_low || rar_high) 237 rar_high |= E1000_RAH_AV; 238 239 /* Some bridges will combine consecutive 32-bit writes into 240 * a single burst write, which will malfunction on some parts. 241 * The flushes avoid this. 242 */ 243 ew32(RAL(index), rar_low); 244 e1e_flush(); 245 ew32(RAH(index), rar_high); 246 e1e_flush(); 247 } 248 249 /** 250 * e1000_hash_mc_addr - Generate a multicast hash value 251 * @hw: pointer to the HW structure 252 * @mc_addr: pointer to a multicast address 253 * 254 * Generates a multicast address hash value which is used to determine 255 * the multicast filter table array address and new table value. 256 **/ 257 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 258 { 259 u32 hash_value, hash_mask; 260 u8 bit_shift = 0; 261 262 /* Register count multiplied by bits per register */ 263 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 264 265 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 266 * where 0xFF would still fall within the hash mask. 267 */ 268 while (hash_mask >> bit_shift != 0xFF) 269 bit_shift++; 270 271 /* The portion of the address that is used for the hash table 272 * is determined by the mc_filter_type setting. 273 * The algorithm is such that there is a total of 8 bits of shifting. 274 * The bit_shift for a mc_filter_type of 0 represents the number of 275 * left-shifts where the MSB of mc_addr[5] would still fall within 276 * the hash_mask. Case 0 does this exactly. Since there are a total 277 * of 8 bits of shifting, then mc_addr[4] will shift right the 278 * remaining number of bits. Thus 8 - bit_shift. The rest of the 279 * cases are a variation of this algorithm...essentially raising the 280 * number of bits to shift mc_addr[5] left, while still keeping the 281 * 8-bit shifting total. 282 * 283 * For example, given the following Destination MAC Address and an 284 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 285 * we can see that the bit_shift for case 0 is 4. These are the hash 286 * values resulting from each mc_filter_type... 287 * [0] [1] [2] [3] [4] [5] 288 * 01 AA 00 12 34 56 289 * LSB MSB 290 * 291 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 292 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 293 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 294 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 295 */ 296 switch (hw->mac.mc_filter_type) { 297 default: 298 case 0: 299 break; 300 case 1: 301 bit_shift += 1; 302 break; 303 case 2: 304 bit_shift += 2; 305 break; 306 case 3: 307 bit_shift += 4; 308 break; 309 } 310 311 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 312 (((u16)mc_addr[5]) << bit_shift))); 313 314 return hash_value; 315 } 316 317 /** 318 * e1000e_update_mc_addr_list_generic - Update Multicast addresses 319 * @hw: pointer to the HW structure 320 * @mc_addr_list: array of multicast addresses to program 321 * @mc_addr_count: number of multicast addresses to program 322 * 323 * Updates entire Multicast Table Array. 324 * The caller must have a packed mc_addr_list of multicast addresses. 325 **/ 326 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 327 u8 *mc_addr_list, u32 mc_addr_count) 328 { 329 u32 hash_value, hash_bit, hash_reg; 330 int i; 331 332 /* clear mta_shadow */ 333 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 334 335 /* update mta_shadow from mc_addr_list */ 336 for (i = 0; (u32)i < mc_addr_count; i++) { 337 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 338 339 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 340 hash_bit = hash_value & 0x1F; 341 342 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 343 mc_addr_list += (ETH_ALEN); 344 } 345 346 /* replace the entire MTA table */ 347 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 348 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 349 e1e_flush(); 350 } 351 352 /** 353 * e1000e_clear_hw_cntrs_base - Clear base hardware counters 354 * @hw: pointer to the HW structure 355 * 356 * Clears the base hardware counters by reading the counter registers. 357 **/ 358 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) 359 { 360 er32(CRCERRS); 361 er32(SYMERRS); 362 er32(MPC); 363 er32(SCC); 364 er32(ECOL); 365 er32(MCC); 366 er32(LATECOL); 367 er32(COLC); 368 er32(DC); 369 er32(SEC); 370 er32(RLEC); 371 er32(XONRXC); 372 er32(XONTXC); 373 er32(XOFFRXC); 374 er32(XOFFTXC); 375 er32(FCRUC); 376 er32(GPRC); 377 er32(BPRC); 378 er32(MPRC); 379 er32(GPTC); 380 er32(GORCL); 381 er32(GORCH); 382 er32(GOTCL); 383 er32(GOTCH); 384 er32(RNBC); 385 er32(RUC); 386 er32(RFC); 387 er32(ROC); 388 er32(RJC); 389 er32(TORL); 390 er32(TORH); 391 er32(TOTL); 392 er32(TOTH); 393 er32(TPR); 394 er32(TPT); 395 er32(MPTC); 396 er32(BPTC); 397 } 398 399 /** 400 * e1000e_check_for_copper_link - Check for link (Copper) 401 * @hw: pointer to the HW structure 402 * 403 * Checks to see of the link status of the hardware has changed. If a 404 * change in link status has been detected, then we read the PHY registers 405 * to get the current speed/duplex if link exists. 406 **/ 407 s32 e1000e_check_for_copper_link(struct e1000_hw *hw) 408 { 409 struct e1000_mac_info *mac = &hw->mac; 410 s32 ret_val; 411 bool link; 412 413 /* We only want to go out to the PHY registers to see if Auto-Neg 414 * has completed and/or if our link status has changed. The 415 * get_link_status flag is set upon receiving a Link Status 416 * Change or Rx Sequence Error interrupt. 417 */ 418 if (!mac->get_link_status) 419 return 0; 420 421 /* First we want to see if the MII Status Register reports 422 * link. If so, then we want to get the current speed/duplex 423 * of the PHY. 424 */ 425 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 426 if (ret_val) 427 return ret_val; 428 429 if (!link) 430 return 0; /* No link detected */ 431 432 mac->get_link_status = false; 433 434 /* Check if there was DownShift, must be checked 435 * immediately after link-up 436 */ 437 e1000e_check_downshift(hw); 438 439 /* If we are forcing speed/duplex, then we simply return since 440 * we have already determined whether we have link or not. 441 */ 442 if (!mac->autoneg) 443 return -E1000_ERR_CONFIG; 444 445 /* Auto-Neg is enabled. Auto Speed Detection takes care 446 * of MAC speed/duplex configuration. So we only need to 447 * configure Collision Distance in the MAC. 448 */ 449 mac->ops.config_collision_dist(hw); 450 451 /* Configure Flow Control now that Auto-Neg has completed. 452 * First, we need to restore the desired flow control 453 * settings because we may have had to re-autoneg with a 454 * different link partner. 455 */ 456 ret_val = e1000e_config_fc_after_link_up(hw); 457 if (ret_val) 458 e_dbg("Error configuring flow control\n"); 459 460 return ret_val; 461 } 462 463 /** 464 * e1000e_check_for_fiber_link - Check for link (Fiber) 465 * @hw: pointer to the HW structure 466 * 467 * Checks for link up on the hardware. If link is not up and we have 468 * a signal, then we need to force link up. 469 **/ 470 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) 471 { 472 struct e1000_mac_info *mac = &hw->mac; 473 u32 rxcw; 474 u32 ctrl; 475 u32 status; 476 s32 ret_val; 477 478 ctrl = er32(CTRL); 479 status = er32(STATUS); 480 rxcw = er32(RXCW); 481 482 /* If we don't have link (auto-negotiation failed or link partner 483 * cannot auto-negotiate), the cable is plugged in (we have signal), 484 * and our link partner is not trying to auto-negotiate with us (we 485 * are receiving idles or data), we need to force link up. We also 486 * need to give auto-negotiation time to complete, in case the cable 487 * was just plugged in. The autoneg_failed flag does this. 488 */ 489 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 490 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 491 !(rxcw & E1000_RXCW_C)) { 492 if (!mac->autoneg_failed) { 493 mac->autoneg_failed = true; 494 return 0; 495 } 496 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 497 498 /* Disable auto-negotiation in the TXCW register */ 499 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 500 501 /* Force link-up and also force full-duplex. */ 502 ctrl = er32(CTRL); 503 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 504 ew32(CTRL, ctrl); 505 506 /* Configure Flow Control after forcing link up. */ 507 ret_val = e1000e_config_fc_after_link_up(hw); 508 if (ret_val) { 509 e_dbg("Error configuring flow control\n"); 510 return ret_val; 511 } 512 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 513 /* If we are forcing link and we are receiving /C/ ordered 514 * sets, re-enable auto-negotiation in the TXCW register 515 * and disable forced link in the Device Control register 516 * in an attempt to auto-negotiate with our link partner. 517 */ 518 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 519 ew32(TXCW, mac->txcw); 520 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 521 522 mac->serdes_has_link = true; 523 } 524 525 return 0; 526 } 527 528 /** 529 * e1000e_check_for_serdes_link - Check for link (Serdes) 530 * @hw: pointer to the HW structure 531 * 532 * Checks for link up on the hardware. If link is not up and we have 533 * a signal, then we need to force link up. 534 **/ 535 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) 536 { 537 struct e1000_mac_info *mac = &hw->mac; 538 u32 rxcw; 539 u32 ctrl; 540 u32 status; 541 s32 ret_val; 542 543 ctrl = er32(CTRL); 544 status = er32(STATUS); 545 rxcw = er32(RXCW); 546 547 /* If we don't have link (auto-negotiation failed or link partner 548 * cannot auto-negotiate), and our link partner is not trying to 549 * auto-negotiate with us (we are receiving idles or data), 550 * we need to force link up. We also need to give auto-negotiation 551 * time to complete. 552 */ 553 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 554 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 555 if (!mac->autoneg_failed) { 556 mac->autoneg_failed = true; 557 return 0; 558 } 559 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 560 561 /* Disable auto-negotiation in the TXCW register */ 562 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 563 564 /* Force link-up and also force full-duplex. */ 565 ctrl = er32(CTRL); 566 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 567 ew32(CTRL, ctrl); 568 569 /* Configure Flow Control after forcing link up. */ 570 ret_val = e1000e_config_fc_after_link_up(hw); 571 if (ret_val) { 572 e_dbg("Error configuring flow control\n"); 573 return ret_val; 574 } 575 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 576 /* If we are forcing link and we are receiving /C/ ordered 577 * sets, re-enable auto-negotiation in the TXCW register 578 * and disable forced link in the Device Control register 579 * in an attempt to auto-negotiate with our link partner. 580 */ 581 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 582 ew32(TXCW, mac->txcw); 583 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 584 585 mac->serdes_has_link = true; 586 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 587 /* If we force link for non-auto-negotiation switch, check 588 * link status based on MAC synchronization for internal 589 * serdes media type. 590 */ 591 /* SYNCH bit and IV bit are sticky. */ 592 usleep_range(10, 20); 593 rxcw = er32(RXCW); 594 if (rxcw & E1000_RXCW_SYNCH) { 595 if (!(rxcw & E1000_RXCW_IV)) { 596 mac->serdes_has_link = true; 597 e_dbg("SERDES: Link up - forced.\n"); 598 } 599 } else { 600 mac->serdes_has_link = false; 601 e_dbg("SERDES: Link down - force failed.\n"); 602 } 603 } 604 605 if (E1000_TXCW_ANE & er32(TXCW)) { 606 status = er32(STATUS); 607 if (status & E1000_STATUS_LU) { 608 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 609 usleep_range(10, 20); 610 rxcw = er32(RXCW); 611 if (rxcw & E1000_RXCW_SYNCH) { 612 if (!(rxcw & E1000_RXCW_IV)) { 613 mac->serdes_has_link = true; 614 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); 615 } else { 616 mac->serdes_has_link = false; 617 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); 618 } 619 } else { 620 mac->serdes_has_link = false; 621 e_dbg("SERDES: Link down - no sync.\n"); 622 } 623 } else { 624 mac->serdes_has_link = false; 625 e_dbg("SERDES: Link down - autoneg failed\n"); 626 } 627 } 628 629 return 0; 630 } 631 632 /** 633 * e1000_set_default_fc_generic - Set flow control default values 634 * @hw: pointer to the HW structure 635 * 636 * Read the EEPROM for the default values for flow control and store the 637 * values. 638 **/ 639 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 640 { 641 s32 ret_val; 642 u16 nvm_data; 643 644 /* Read and store word 0x0F of the EEPROM. This word contains bits 645 * that determine the hardware's default PAUSE (flow control) mode, 646 * a bit that determines whether the HW defaults to enabling or 647 * disabling auto-negotiation, and the direction of the 648 * SW defined pins. If there is no SW over-ride of the flow 649 * control setting, then the variable hw->fc will 650 * be initialized based on a value in the EEPROM. 651 */ 652 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 653 654 if (ret_val) { 655 e_dbg("NVM Read Error\n"); 656 return ret_val; 657 } 658 659 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 660 hw->fc.requested_mode = e1000_fc_none; 661 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) 662 hw->fc.requested_mode = e1000_fc_tx_pause; 663 else 664 hw->fc.requested_mode = e1000_fc_full; 665 666 return 0; 667 } 668 669 /** 670 * e1000e_setup_link_generic - Setup flow control and link settings 671 * @hw: pointer to the HW structure 672 * 673 * Determines which flow control settings to use, then configures flow 674 * control. Calls the appropriate media-specific link configuration 675 * function. Assuming the adapter has a valid link partner, a valid link 676 * should be established. Assumes the hardware has previously been reset 677 * and the transmitter and receiver are not enabled. 678 **/ 679 s32 e1000e_setup_link_generic(struct e1000_hw *hw) 680 { 681 s32 ret_val; 682 683 /* In the case of the phy reset being blocked, we already have a link. 684 * We do not need to set it up again. 685 */ 686 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 687 return 0; 688 689 /* If requested flow control is set to default, set flow control 690 * based on the EEPROM flow control settings. 691 */ 692 if (hw->fc.requested_mode == e1000_fc_default) { 693 ret_val = e1000_set_default_fc_generic(hw); 694 if (ret_val) 695 return ret_val; 696 } 697 698 /* Save off the requested flow control mode for use later. Depending 699 * on the link partner's capabilities, we may or may not use this mode. 700 */ 701 hw->fc.current_mode = hw->fc.requested_mode; 702 703 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 704 705 /* Call the necessary media_type subroutine to configure the link. */ 706 ret_val = hw->mac.ops.setup_physical_interface(hw); 707 if (ret_val) 708 return ret_val; 709 710 /* Initialize the flow control address, type, and PAUSE timer 711 * registers to their default values. This is done even if flow 712 * control is disabled, because it does not hurt anything to 713 * initialize these registers. 714 */ 715 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 716 ew32(FCT, FLOW_CONTROL_TYPE); 717 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 718 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 719 720 ew32(FCTTV, hw->fc.pause_time); 721 722 return e1000e_set_fc_watermarks(hw); 723 } 724 725 /** 726 * e1000_commit_fc_settings_generic - Configure flow control 727 * @hw: pointer to the HW structure 728 * 729 * Write the flow control settings to the Transmit Config Word Register (TXCW) 730 * base on the flow control settings in e1000_mac_info. 731 **/ 732 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 733 { 734 struct e1000_mac_info *mac = &hw->mac; 735 u32 txcw; 736 737 /* Check for a software override of the flow control settings, and 738 * setup the device accordingly. If auto-negotiation is enabled, then 739 * software will have to set the "PAUSE" bits to the correct value in 740 * the Transmit Config Word Register (TXCW) and re-start auto- 741 * negotiation. However, if auto-negotiation is disabled, then 742 * software will have to manually configure the two flow control enable 743 * bits in the CTRL register. 744 * 745 * The possible values of the "fc" parameter are: 746 * 0: Flow control is completely disabled 747 * 1: Rx flow control is enabled (we can receive pause frames, 748 * but not send pause frames). 749 * 2: Tx flow control is enabled (we can send pause frames but we 750 * do not support receiving pause frames). 751 * 3: Both Rx and Tx flow control (symmetric) are enabled. 752 */ 753 switch (hw->fc.current_mode) { 754 case e1000_fc_none: 755 /* Flow control completely disabled by a software over-ride. */ 756 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 757 break; 758 case e1000_fc_rx_pause: 759 /* Rx Flow control is enabled and Tx Flow control is disabled 760 * by a software over-ride. Since there really isn't a way to 761 * advertise that we are capable of Rx Pause ONLY, we will 762 * advertise that we support both symmetric and asymmetric Rx 763 * PAUSE. Later, we will disable the adapter's ability to send 764 * PAUSE frames. 765 */ 766 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 767 break; 768 case e1000_fc_tx_pause: 769 /* Tx Flow control is enabled, and Rx Flow control is disabled, 770 * by a software over-ride. 771 */ 772 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 773 break; 774 case e1000_fc_full: 775 /* Flow control (both Rx and Tx) is enabled by a software 776 * over-ride. 777 */ 778 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 779 break; 780 default: 781 e_dbg("Flow control param set incorrectly\n"); 782 return -E1000_ERR_CONFIG; 783 break; 784 } 785 786 ew32(TXCW, txcw); 787 mac->txcw = txcw; 788 789 return 0; 790 } 791 792 /** 793 * e1000_poll_fiber_serdes_link_generic - Poll for link up 794 * @hw: pointer to the HW structure 795 * 796 * Polls for link up by reading the status register, if link fails to come 797 * up with auto-negotiation, then the link is forced if a signal is detected. 798 **/ 799 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 800 { 801 struct e1000_mac_info *mac = &hw->mac; 802 u32 i, status; 803 s32 ret_val; 804 805 /* If we have a signal (the cable is plugged in, or assumed true for 806 * serdes media) then poll for a "Link-Up" indication in the Device 807 * Status Register. Time-out if a link isn't seen in 500 milliseconds 808 * seconds (Auto-negotiation should complete in less than 500 809 * milliseconds even if the other end is doing it in SW). 810 */ 811 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 812 usleep_range(10000, 20000); 813 status = er32(STATUS); 814 if (status & E1000_STATUS_LU) 815 break; 816 } 817 if (i == FIBER_LINK_UP_LIMIT) { 818 e_dbg("Never got a valid link from auto-neg!!!\n"); 819 mac->autoneg_failed = true; 820 /* AutoNeg failed to achieve a link, so we'll call 821 * mac->check_for_link. This routine will force the 822 * link up if we detect a signal. This will allow us to 823 * communicate with non-autonegotiating link partners. 824 */ 825 ret_val = mac->ops.check_for_link(hw); 826 if (ret_val) { 827 e_dbg("Error while checking for link\n"); 828 return ret_val; 829 } 830 mac->autoneg_failed = false; 831 } else { 832 mac->autoneg_failed = false; 833 e_dbg("Valid Link Found\n"); 834 } 835 836 return 0; 837 } 838 839 /** 840 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes 841 * @hw: pointer to the HW structure 842 * 843 * Configures collision distance and flow control for fiber and serdes 844 * links. Upon successful setup, poll for link. 845 **/ 846 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) 847 { 848 u32 ctrl; 849 s32 ret_val; 850 851 ctrl = er32(CTRL); 852 853 /* Take the link out of reset */ 854 ctrl &= ~E1000_CTRL_LRST; 855 856 hw->mac.ops.config_collision_dist(hw); 857 858 ret_val = e1000_commit_fc_settings_generic(hw); 859 if (ret_val) 860 return ret_val; 861 862 /* Since auto-negotiation is enabled, take the link out of reset (the 863 * link will be in reset, because we previously reset the chip). This 864 * will restart auto-negotiation. If auto-negotiation is successful 865 * then the link-up status bit will be set and the flow control enable 866 * bits (RFCE and TFCE) will be set according to their negotiated value. 867 */ 868 e_dbg("Auto-negotiation enabled\n"); 869 870 ew32(CTRL, ctrl); 871 e1e_flush(); 872 usleep_range(1000, 2000); 873 874 /* For these adapters, the SW definable pin 1 is set when the optics 875 * detect a signal. If we have a signal, then poll for a "Link-Up" 876 * indication. 877 */ 878 if (hw->phy.media_type == e1000_media_type_internal_serdes || 879 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 880 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 881 } else { 882 e_dbg("No signal detected\n"); 883 } 884 885 return ret_val; 886 } 887 888 /** 889 * e1000e_config_collision_dist_generic - Configure collision distance 890 * @hw: pointer to the HW structure 891 * 892 * Configures the collision distance to the default value and is used 893 * during link setup. 894 **/ 895 void e1000e_config_collision_dist_generic(struct e1000_hw *hw) 896 { 897 u32 tctl; 898 899 tctl = er32(TCTL); 900 901 tctl &= ~E1000_TCTL_COLD; 902 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 903 904 ew32(TCTL, tctl); 905 e1e_flush(); 906 } 907 908 /** 909 * e1000e_set_fc_watermarks - Set flow control high/low watermarks 910 * @hw: pointer to the HW structure 911 * 912 * Sets the flow control high/low threshold (watermark) registers. If 913 * flow control XON frame transmission is enabled, then set XON frame 914 * transmission as well. 915 **/ 916 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) 917 { 918 u32 fcrtl = 0, fcrth = 0; 919 920 /* Set the flow control receive threshold registers. Normally, 921 * these registers will be set to a default threshold that may be 922 * adjusted later by the driver's runtime code. However, if the 923 * ability to transmit pause frames is not enabled, then these 924 * registers will be set to 0. 925 */ 926 if (hw->fc.current_mode & e1000_fc_tx_pause) { 927 /* We need to set up the Receive Threshold high and low water 928 * marks as well as (optionally) enabling the transmission of 929 * XON frames. 930 */ 931 fcrtl = hw->fc.low_water; 932 if (hw->fc.send_xon) 933 fcrtl |= E1000_FCRTL_XONE; 934 935 fcrth = hw->fc.high_water; 936 } 937 ew32(FCRTL, fcrtl); 938 ew32(FCRTH, fcrth); 939 940 return 0; 941 } 942 943 /** 944 * e1000e_force_mac_fc - Force the MAC's flow control settings 945 * @hw: pointer to the HW structure 946 * 947 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 948 * device control register to reflect the adapter settings. TFCE and RFCE 949 * need to be explicitly set by software when a copper PHY is used because 950 * autonegotiation is managed by the PHY rather than the MAC. Software must 951 * also configure these bits when link is forced on a fiber connection. 952 **/ 953 s32 e1000e_force_mac_fc(struct e1000_hw *hw) 954 { 955 u32 ctrl; 956 957 ctrl = er32(CTRL); 958 959 /* Because we didn't get link via the internal auto-negotiation 960 * mechanism (we either forced link or we got link via PHY 961 * auto-neg), we have to manually enable/disable transmit an 962 * receive flow control. 963 * 964 * The "Case" statement below enables/disable flow control 965 * according to the "hw->fc.current_mode" parameter. 966 * 967 * The possible values of the "fc" parameter are: 968 * 0: Flow control is completely disabled 969 * 1: Rx flow control is enabled (we can receive pause 970 * frames but not send pause frames). 971 * 2: Tx flow control is enabled (we can send pause frames 972 * frames but we do not receive pause frames). 973 * 3: Both Rx and Tx flow control (symmetric) is enabled. 974 * other: No other values should be possible at this point. 975 */ 976 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 977 978 switch (hw->fc.current_mode) { 979 case e1000_fc_none: 980 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 981 break; 982 case e1000_fc_rx_pause: 983 ctrl &= (~E1000_CTRL_TFCE); 984 ctrl |= E1000_CTRL_RFCE; 985 break; 986 case e1000_fc_tx_pause: 987 ctrl &= (~E1000_CTRL_RFCE); 988 ctrl |= E1000_CTRL_TFCE; 989 break; 990 case e1000_fc_full: 991 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 992 break; 993 default: 994 e_dbg("Flow control param set incorrectly\n"); 995 return -E1000_ERR_CONFIG; 996 } 997 998 ew32(CTRL, ctrl); 999 1000 return 0; 1001 } 1002 1003 /** 1004 * e1000e_config_fc_after_link_up - Configures flow control after link 1005 * @hw: pointer to the HW structure 1006 * 1007 * Checks the status of auto-negotiation after link up to ensure that the 1008 * speed and duplex were not forced. If the link needed to be forced, then 1009 * flow control needs to be forced also. If auto-negotiation is enabled 1010 * and did not fail, then we configure flow control based on our link 1011 * partner. 1012 **/ 1013 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) 1014 { 1015 struct e1000_mac_info *mac = &hw->mac; 1016 s32 ret_val = 0; 1017 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1018 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1019 u16 speed, duplex; 1020 1021 /* Check for the case where we have fiber media and auto-neg failed 1022 * so we had to force link. In this case, we need to force the 1023 * configuration of the MAC to match the "fc" parameter. 1024 */ 1025 if (mac->autoneg_failed) { 1026 if (hw->phy.media_type == e1000_media_type_fiber || 1027 hw->phy.media_type == e1000_media_type_internal_serdes) 1028 ret_val = e1000e_force_mac_fc(hw); 1029 } else { 1030 if (hw->phy.media_type == e1000_media_type_copper) 1031 ret_val = e1000e_force_mac_fc(hw); 1032 } 1033 1034 if (ret_val) { 1035 e_dbg("Error forcing flow control settings\n"); 1036 return ret_val; 1037 } 1038 1039 /* Check for the case where we have copper media and auto-neg is 1040 * enabled. In this case, we need to check and see if Auto-Neg 1041 * has completed, and if so, how the PHY and link partner has 1042 * flow control configured. 1043 */ 1044 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1045 /* Read the MII Status Register and check to see if AutoNeg 1046 * has completed. We read this twice because this reg has 1047 * some "sticky" (latched) bits. 1048 */ 1049 ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg); 1050 if (ret_val) 1051 return ret_val; 1052 ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg); 1053 if (ret_val) 1054 return ret_val; 1055 1056 if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) { 1057 e_dbg("Copper PHY and Auto Neg has not completed.\n"); 1058 return ret_val; 1059 } 1060 1061 /* The AutoNeg process has completed, so we now need to 1062 * read both the Auto Negotiation Advertisement 1063 * Register (Address 4) and the Auto_Negotiation Base 1064 * Page Ability Register (Address 5) to determine how 1065 * flow control was negotiated. 1066 */ 1067 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg); 1068 if (ret_val) 1069 return ret_val; 1070 ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg); 1071 if (ret_val) 1072 return ret_val; 1073 1074 /* Two bits in the Auto Negotiation Advertisement Register 1075 * (Address 4) and two bits in the Auto Negotiation Base 1076 * Page Ability Register (Address 5) determine flow control 1077 * for both the PHY and the link partner. The following 1078 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1079 * 1999, describes these PAUSE resolution bits and how flow 1080 * control is determined based upon these settings. 1081 * NOTE: DC = Don't Care 1082 * 1083 * LOCAL DEVICE | LINK PARTNER 1084 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1085 *-------|---------|-------|---------|-------------------- 1086 * 0 | 0 | DC | DC | e1000_fc_none 1087 * 0 | 1 | 0 | DC | e1000_fc_none 1088 * 0 | 1 | 1 | 0 | e1000_fc_none 1089 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1090 * 1 | 0 | 0 | DC | e1000_fc_none 1091 * 1 | DC | 1 | DC | e1000_fc_full 1092 * 1 | 1 | 0 | 0 | e1000_fc_none 1093 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1094 * 1095 * Are both PAUSE bits set to 1? If so, this implies 1096 * Symmetric Flow Control is enabled at both ends. The 1097 * ASM_DIR bits are irrelevant per the spec. 1098 * 1099 * For Symmetric Flow Control: 1100 * 1101 * LOCAL DEVICE | LINK PARTNER 1102 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1103 *-------|---------|-------|---------|-------------------- 1104 * 1 | DC | 1 | DC | E1000_fc_full 1105 * 1106 */ 1107 if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1108 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) { 1109 /* Now we need to check if the user selected Rx ONLY 1110 * of pause frames. In this case, we had to advertise 1111 * FULL flow control because we could not advertise Rx 1112 * ONLY. Hence, we must now check to see if we need to 1113 * turn OFF the TRANSMISSION of PAUSE frames. 1114 */ 1115 if (hw->fc.requested_mode == e1000_fc_full) { 1116 hw->fc.current_mode = e1000_fc_full; 1117 e_dbg("Flow Control = FULL.\n"); 1118 } else { 1119 hw->fc.current_mode = e1000_fc_rx_pause; 1120 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1121 } 1122 } 1123 /* For receiving PAUSE frames ONLY. 1124 * 1125 * LOCAL DEVICE | LINK PARTNER 1126 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1127 *-------|---------|-------|---------|-------------------- 1128 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1129 */ 1130 else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1131 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) && 1132 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP) && 1133 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) { 1134 hw->fc.current_mode = e1000_fc_tx_pause; 1135 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1136 } 1137 /* For transmitting PAUSE frames ONLY. 1138 * 1139 * LOCAL DEVICE | LINK PARTNER 1140 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1141 *-------|---------|-------|---------|-------------------- 1142 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1143 */ 1144 else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1145 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) && 1146 !(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) && 1147 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) { 1148 hw->fc.current_mode = e1000_fc_rx_pause; 1149 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1150 } else { 1151 /* Per the IEEE spec, at this point flow control 1152 * should be disabled. 1153 */ 1154 hw->fc.current_mode = e1000_fc_none; 1155 e_dbg("Flow Control = NONE.\n"); 1156 } 1157 1158 /* Now we need to do one last check... If we auto- 1159 * negotiated to HALF DUPLEX, flow control should not be 1160 * enabled per IEEE 802.3 spec. 1161 */ 1162 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1163 if (ret_val) { 1164 e_dbg("Error getting link speed and duplex\n"); 1165 return ret_val; 1166 } 1167 1168 if (duplex == HALF_DUPLEX) 1169 hw->fc.current_mode = e1000_fc_none; 1170 1171 /* Now we call a subroutine to actually force the MAC 1172 * controller to use the correct flow control settings. 1173 */ 1174 ret_val = e1000e_force_mac_fc(hw); 1175 if (ret_val) { 1176 e_dbg("Error forcing flow control settings\n"); 1177 return ret_val; 1178 } 1179 } 1180 1181 /* Check for the case where we have SerDes media and auto-neg is 1182 * enabled. In this case, we need to check and see if Auto-Neg 1183 * has completed, and if so, how the PHY and link partner has 1184 * flow control configured. 1185 */ 1186 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1187 mac->autoneg) { 1188 /* Read the PCS_LSTS and check to see if AutoNeg 1189 * has completed. 1190 */ 1191 pcs_status_reg = er32(PCS_LSTAT); 1192 1193 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1194 e_dbg("PCS Auto Neg has not completed.\n"); 1195 return ret_val; 1196 } 1197 1198 /* The AutoNeg process has completed, so we now need to 1199 * read both the Auto Negotiation Advertisement 1200 * Register (PCS_ANADV) and the Auto_Negotiation Base 1201 * Page Ability Register (PCS_LPAB) to determine how 1202 * flow control was negotiated. 1203 */ 1204 pcs_adv_reg = er32(PCS_ANADV); 1205 pcs_lp_ability_reg = er32(PCS_LPAB); 1206 1207 /* Two bits in the Auto Negotiation Advertisement Register 1208 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1209 * Page Ability Register (PCS_LPAB) determine flow control 1210 * for both the PHY and the link partner. The following 1211 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1212 * 1999, describes these PAUSE resolution bits and how flow 1213 * control is determined based upon these settings. 1214 * NOTE: DC = Don't Care 1215 * 1216 * LOCAL DEVICE | LINK PARTNER 1217 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1218 *-------|---------|-------|---------|-------------------- 1219 * 0 | 0 | DC | DC | e1000_fc_none 1220 * 0 | 1 | 0 | DC | e1000_fc_none 1221 * 0 | 1 | 1 | 0 | e1000_fc_none 1222 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1223 * 1 | 0 | 0 | DC | e1000_fc_none 1224 * 1 | DC | 1 | DC | e1000_fc_full 1225 * 1 | 1 | 0 | 0 | e1000_fc_none 1226 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1227 * 1228 * Are both PAUSE bits set to 1? If so, this implies 1229 * Symmetric Flow Control is enabled at both ends. The 1230 * ASM_DIR bits are irrelevant per the spec. 1231 * 1232 * For Symmetric Flow Control: 1233 * 1234 * LOCAL DEVICE | LINK PARTNER 1235 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1236 *-------|---------|-------|---------|-------------------- 1237 * 1 | DC | 1 | DC | e1000_fc_full 1238 * 1239 */ 1240 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1241 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1242 /* Now we need to check if the user selected Rx ONLY 1243 * of pause frames. In this case, we had to advertise 1244 * FULL flow control because we could not advertise Rx 1245 * ONLY. Hence, we must now check to see if we need to 1246 * turn OFF the TRANSMISSION of PAUSE frames. 1247 */ 1248 if (hw->fc.requested_mode == e1000_fc_full) { 1249 hw->fc.current_mode = e1000_fc_full; 1250 e_dbg("Flow Control = FULL.\n"); 1251 } else { 1252 hw->fc.current_mode = e1000_fc_rx_pause; 1253 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1254 } 1255 } 1256 /* For receiving PAUSE frames ONLY. 1257 * 1258 * LOCAL DEVICE | LINK PARTNER 1259 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1260 *-------|---------|-------|---------|-------------------- 1261 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1262 */ 1263 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1264 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1265 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1266 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1267 hw->fc.current_mode = e1000_fc_tx_pause; 1268 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1269 } 1270 /* For transmitting PAUSE frames ONLY. 1271 * 1272 * LOCAL DEVICE | LINK PARTNER 1273 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1274 *-------|---------|-------|---------|-------------------- 1275 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1276 */ 1277 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1278 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1279 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1280 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1281 hw->fc.current_mode = e1000_fc_rx_pause; 1282 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1283 } else { 1284 /* Per the IEEE spec, at this point flow control 1285 * should be disabled. 1286 */ 1287 hw->fc.current_mode = e1000_fc_none; 1288 e_dbg("Flow Control = NONE.\n"); 1289 } 1290 1291 /* Now we call a subroutine to actually force the MAC 1292 * controller to use the correct flow control settings. 1293 */ 1294 pcs_ctrl_reg = er32(PCS_LCTL); 1295 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1296 ew32(PCS_LCTL, pcs_ctrl_reg); 1297 1298 ret_val = e1000e_force_mac_fc(hw); 1299 if (ret_val) { 1300 e_dbg("Error forcing flow control settings\n"); 1301 return ret_val; 1302 } 1303 } 1304 1305 return 0; 1306 } 1307 1308 /** 1309 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex 1310 * @hw: pointer to the HW structure 1311 * @speed: stores the current speed 1312 * @duplex: stores the current duplex 1313 * 1314 * Read the status register for the current speed/duplex and store the current 1315 * speed and duplex for copper connections. 1316 **/ 1317 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1318 u16 *duplex) 1319 { 1320 u32 status; 1321 1322 status = er32(STATUS); 1323 if (status & E1000_STATUS_SPEED_1000) 1324 *speed = SPEED_1000; 1325 else if (status & E1000_STATUS_SPEED_100) 1326 *speed = SPEED_100; 1327 else 1328 *speed = SPEED_10; 1329 1330 if (status & E1000_STATUS_FD) 1331 *duplex = FULL_DUPLEX; 1332 else 1333 *duplex = HALF_DUPLEX; 1334 1335 e_dbg("%u Mbps, %s Duplex\n", 1336 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, 1337 *duplex == FULL_DUPLEX ? "Full" : "Half"); 1338 1339 return 0; 1340 } 1341 1342 /** 1343 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex 1344 * @hw: pointer to the HW structure 1345 * @speed: stores the current speed 1346 * @duplex: stores the current duplex 1347 * 1348 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1349 * for fiber/serdes links. 1350 **/ 1351 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused 1352 *hw, u16 *speed, u16 *duplex) 1353 { 1354 *speed = SPEED_1000; 1355 *duplex = FULL_DUPLEX; 1356 1357 return 0; 1358 } 1359 1360 /** 1361 * e1000e_get_hw_semaphore - Acquire hardware semaphore 1362 * @hw: pointer to the HW structure 1363 * 1364 * Acquire the HW semaphore to access the PHY or NVM 1365 **/ 1366 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) 1367 { 1368 u32 swsm; 1369 s32 timeout = hw->nvm.word_size + 1; 1370 s32 i = 0; 1371 1372 /* Get the SW semaphore */ 1373 while (i < timeout) { 1374 swsm = er32(SWSM); 1375 if (!(swsm & E1000_SWSM_SMBI)) 1376 break; 1377 1378 usleep_range(50, 100); 1379 i++; 1380 } 1381 1382 if (i == timeout) { 1383 e_dbg("Driver can't access device - SMBI bit is set.\n"); 1384 return -E1000_ERR_NVM; 1385 } 1386 1387 /* Get the FW semaphore. */ 1388 for (i = 0; i < timeout; i++) { 1389 swsm = er32(SWSM); 1390 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 1391 1392 /* Semaphore acquired if bit latched */ 1393 if (er32(SWSM) & E1000_SWSM_SWESMBI) 1394 break; 1395 1396 usleep_range(50, 100); 1397 } 1398 1399 if (i == timeout) { 1400 /* Release semaphores */ 1401 e1000e_put_hw_semaphore(hw); 1402 e_dbg("Driver can't access the NVM\n"); 1403 return -E1000_ERR_NVM; 1404 } 1405 1406 return 0; 1407 } 1408 1409 /** 1410 * e1000e_put_hw_semaphore - Release hardware semaphore 1411 * @hw: pointer to the HW structure 1412 * 1413 * Release hardware semaphore used to access the PHY or NVM 1414 **/ 1415 void e1000e_put_hw_semaphore(struct e1000_hw *hw) 1416 { 1417 u32 swsm; 1418 1419 swsm = er32(SWSM); 1420 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1421 ew32(SWSM, swsm); 1422 } 1423 1424 /** 1425 * e1000e_get_auto_rd_done - Check for auto read completion 1426 * @hw: pointer to the HW structure 1427 * 1428 * Check EEPROM for Auto Read done bit. 1429 **/ 1430 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) 1431 { 1432 s32 i = 0; 1433 1434 while (i < AUTO_READ_DONE_TIMEOUT) { 1435 if (er32(EECD) & E1000_EECD_AUTO_RD) 1436 break; 1437 usleep_range(1000, 2000); 1438 i++; 1439 } 1440 1441 if (i == AUTO_READ_DONE_TIMEOUT) { 1442 e_dbg("Auto read by HW from NVM has not completed.\n"); 1443 return -E1000_ERR_RESET; 1444 } 1445 1446 return 0; 1447 } 1448 1449 /** 1450 * e1000e_valid_led_default - Verify a valid default LED config 1451 * @hw: pointer to the HW structure 1452 * @data: pointer to the NVM (EEPROM) 1453 * 1454 * Read the EEPROM for the current default LED configuration. If the 1455 * LED configuration is not valid, set to a valid LED configuration. 1456 **/ 1457 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) 1458 { 1459 s32 ret_val; 1460 1461 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1462 if (ret_val) { 1463 e_dbg("NVM Read Error\n"); 1464 return ret_val; 1465 } 1466 1467 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1468 *data = ID_LED_DEFAULT; 1469 1470 return 0; 1471 } 1472 1473 /** 1474 * e1000e_id_led_init_generic - 1475 * @hw: pointer to the HW structure 1476 * 1477 **/ 1478 s32 e1000e_id_led_init_generic(struct e1000_hw *hw) 1479 { 1480 struct e1000_mac_info *mac = &hw->mac; 1481 s32 ret_val; 1482 const u32 ledctl_mask = 0x000000FF; 1483 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1484 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1485 u16 data, i, temp; 1486 const u16 led_mask = 0x0F; 1487 1488 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1489 if (ret_val) 1490 return ret_val; 1491 1492 mac->ledctl_default = er32(LEDCTL); 1493 mac->ledctl_mode1 = mac->ledctl_default; 1494 mac->ledctl_mode2 = mac->ledctl_default; 1495 1496 for (i = 0; i < 4; i++) { 1497 temp = (data >> (i << 2)) & led_mask; 1498 switch (temp) { 1499 case ID_LED_ON1_DEF2: 1500 case ID_LED_ON1_ON2: 1501 case ID_LED_ON1_OFF2: 1502 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1503 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1504 break; 1505 case ID_LED_OFF1_DEF2: 1506 case ID_LED_OFF1_ON2: 1507 case ID_LED_OFF1_OFF2: 1508 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1509 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1510 break; 1511 default: 1512 /* Do nothing */ 1513 break; 1514 } 1515 switch (temp) { 1516 case ID_LED_DEF1_ON2: 1517 case ID_LED_ON1_ON2: 1518 case ID_LED_OFF1_ON2: 1519 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1520 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1521 break; 1522 case ID_LED_DEF1_OFF2: 1523 case ID_LED_ON1_OFF2: 1524 case ID_LED_OFF1_OFF2: 1525 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1526 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1527 break; 1528 default: 1529 /* Do nothing */ 1530 break; 1531 } 1532 } 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * e1000e_setup_led_generic - Configures SW controllable LED 1539 * @hw: pointer to the HW structure 1540 * 1541 * This prepares the SW controllable LED for use and saves the current state 1542 * of the LED so it can be later restored. 1543 **/ 1544 s32 e1000e_setup_led_generic(struct e1000_hw *hw) 1545 { 1546 u32 ledctl; 1547 1548 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) 1549 return -E1000_ERR_CONFIG; 1550 1551 if (hw->phy.media_type == e1000_media_type_fiber) { 1552 ledctl = er32(LEDCTL); 1553 hw->mac.ledctl_default = ledctl; 1554 /* Turn off LED0 */ 1555 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1556 E1000_LEDCTL_LED0_MODE_MASK); 1557 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1558 E1000_LEDCTL_LED0_MODE_SHIFT); 1559 ew32(LEDCTL, ledctl); 1560 } else if (hw->phy.media_type == e1000_media_type_copper) { 1561 ew32(LEDCTL, hw->mac.ledctl_mode1); 1562 } 1563 1564 return 0; 1565 } 1566 1567 /** 1568 * e1000e_cleanup_led_generic - Set LED config to default operation 1569 * @hw: pointer to the HW structure 1570 * 1571 * Remove the current LED configuration and set the LED configuration 1572 * to the default value, saved from the EEPROM. 1573 **/ 1574 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) 1575 { 1576 ew32(LEDCTL, hw->mac.ledctl_default); 1577 return 0; 1578 } 1579 1580 /** 1581 * e1000e_blink_led_generic - Blink LED 1582 * @hw: pointer to the HW structure 1583 * 1584 * Blink the LEDs which are set to be on. 1585 **/ 1586 s32 e1000e_blink_led_generic(struct e1000_hw *hw) 1587 { 1588 u32 ledctl_blink = 0; 1589 u32 i; 1590 1591 if (hw->phy.media_type == e1000_media_type_fiber) { 1592 /* always blink LED0 for PCI-E fiber */ 1593 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1594 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1595 } else { 1596 /* Set the blink bit for each LED that's "on" (0x0E) 1597 * (or "off" if inverted) in ledctl_mode2. The blink 1598 * logic in hardware only works when mode is set to "on" 1599 * so it must be changed accordingly when the mode is 1600 * "off" and inverted. 1601 */ 1602 ledctl_blink = hw->mac.ledctl_mode2; 1603 for (i = 0; i < 32; i += 8) { 1604 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1605 E1000_LEDCTL_LED0_MODE_MASK; 1606 u32 led_default = hw->mac.ledctl_default >> i; 1607 1608 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1609 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1610 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1611 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1612 ledctl_blink &= 1613 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1614 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1615 E1000_LEDCTL_MODE_LED_ON) << i; 1616 } 1617 } 1618 } 1619 1620 ew32(LEDCTL, ledctl_blink); 1621 1622 return 0; 1623 } 1624 1625 /** 1626 * e1000e_led_on_generic - Turn LED on 1627 * @hw: pointer to the HW structure 1628 * 1629 * Turn LED on. 1630 **/ 1631 s32 e1000e_led_on_generic(struct e1000_hw *hw) 1632 { 1633 u32 ctrl; 1634 1635 switch (hw->phy.media_type) { 1636 case e1000_media_type_fiber: 1637 ctrl = er32(CTRL); 1638 ctrl &= ~E1000_CTRL_SWDPIN0; 1639 ctrl |= E1000_CTRL_SWDPIO0; 1640 ew32(CTRL, ctrl); 1641 break; 1642 case e1000_media_type_copper: 1643 ew32(LEDCTL, hw->mac.ledctl_mode2); 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 return 0; 1650 } 1651 1652 /** 1653 * e1000e_led_off_generic - Turn LED off 1654 * @hw: pointer to the HW structure 1655 * 1656 * Turn LED off. 1657 **/ 1658 s32 e1000e_led_off_generic(struct e1000_hw *hw) 1659 { 1660 u32 ctrl; 1661 1662 switch (hw->phy.media_type) { 1663 case e1000_media_type_fiber: 1664 ctrl = er32(CTRL); 1665 ctrl |= E1000_CTRL_SWDPIN0; 1666 ctrl |= E1000_CTRL_SWDPIO0; 1667 ew32(CTRL, ctrl); 1668 break; 1669 case e1000_media_type_copper: 1670 ew32(LEDCTL, hw->mac.ledctl_mode1); 1671 break; 1672 default: 1673 break; 1674 } 1675 1676 return 0; 1677 } 1678 1679 /** 1680 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities 1681 * @hw: pointer to the HW structure 1682 * @no_snoop: bitmap of snoop events 1683 * 1684 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1685 **/ 1686 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) 1687 { 1688 u32 gcr; 1689 1690 if (no_snoop) { 1691 gcr = er32(GCR); 1692 gcr &= ~(PCIE_NO_SNOOP_ALL); 1693 gcr |= no_snoop; 1694 ew32(GCR, gcr); 1695 } 1696 } 1697 1698 /** 1699 * e1000e_disable_pcie_master - Disables PCI-express master access 1700 * @hw: pointer to the HW structure 1701 * 1702 * Returns 0 if successful, else returns -10 1703 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1704 * the master requests to be disabled. 1705 * 1706 * Disables PCI-Express master access and verifies there are no pending 1707 * requests. 1708 **/ 1709 s32 e1000e_disable_pcie_master(struct e1000_hw *hw) 1710 { 1711 u32 ctrl; 1712 s32 timeout = MASTER_DISABLE_TIMEOUT; 1713 1714 ctrl = er32(CTRL); 1715 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1716 ew32(CTRL, ctrl); 1717 1718 while (timeout) { 1719 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 1720 break; 1721 usleep_range(100, 200); 1722 timeout--; 1723 } 1724 1725 if (!timeout) { 1726 e_dbg("Master requests are pending.\n"); 1727 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1728 } 1729 1730 return 0; 1731 } 1732 1733 /** 1734 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing 1735 * @hw: pointer to the HW structure 1736 * 1737 * Reset the Adaptive Interframe Spacing throttle to default values. 1738 **/ 1739 void e1000e_reset_adaptive(struct e1000_hw *hw) 1740 { 1741 struct e1000_mac_info *mac = &hw->mac; 1742 1743 if (!mac->adaptive_ifs) { 1744 e_dbg("Not in Adaptive IFS mode!\n"); 1745 return; 1746 } 1747 1748 mac->current_ifs_val = 0; 1749 mac->ifs_min_val = IFS_MIN; 1750 mac->ifs_max_val = IFS_MAX; 1751 mac->ifs_step_size = IFS_STEP; 1752 mac->ifs_ratio = IFS_RATIO; 1753 1754 mac->in_ifs_mode = false; 1755 ew32(AIT, 0); 1756 } 1757 1758 /** 1759 * e1000e_update_adaptive - Update Adaptive Interframe Spacing 1760 * @hw: pointer to the HW structure 1761 * 1762 * Update the Adaptive Interframe Spacing Throttle value based on the 1763 * time between transmitted packets and time between collisions. 1764 **/ 1765 void e1000e_update_adaptive(struct e1000_hw *hw) 1766 { 1767 struct e1000_mac_info *mac = &hw->mac; 1768 1769 if (!mac->adaptive_ifs) { 1770 e_dbg("Not in Adaptive IFS mode!\n"); 1771 return; 1772 } 1773 1774 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1775 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1776 mac->in_ifs_mode = true; 1777 if (mac->current_ifs_val < mac->ifs_max_val) { 1778 if (!mac->current_ifs_val) 1779 mac->current_ifs_val = mac->ifs_min_val; 1780 else 1781 mac->current_ifs_val += 1782 mac->ifs_step_size; 1783 ew32(AIT, mac->current_ifs_val); 1784 } 1785 } 1786 } else { 1787 if (mac->in_ifs_mode && 1788 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1789 mac->current_ifs_val = 0; 1790 mac->in_ifs_mode = false; 1791 ew32(AIT, 0); 1792 } 1793 } 1794 } 1795