1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 #include "e1000.h" 23 24 /** 25 * e1000e_get_bus_info_pcie - Get PCIe bus information 26 * @hw: pointer to the HW structure 27 * 28 * Determines and stores the system bus information for a particular 29 * network interface. The following bus information is determined and stored: 30 * bus speed, bus width, type (PCIe), and PCIe function. 31 **/ 32 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) 33 { 34 struct e1000_mac_info *mac = &hw->mac; 35 struct e1000_bus_info *bus = &hw->bus; 36 struct e1000_adapter *adapter = hw->adapter; 37 u16 pcie_link_status, cap_offset; 38 39 cap_offset = adapter->pdev->pcie_cap; 40 if (!cap_offset) { 41 bus->width = e1000_bus_width_unknown; 42 } else { 43 pci_read_config_word(adapter->pdev, 44 cap_offset + PCIE_LINK_STATUS, 45 &pcie_link_status); 46 bus->width = (enum e1000_bus_width)((pcie_link_status & 47 PCIE_LINK_WIDTH_MASK) >> 48 PCIE_LINK_WIDTH_SHIFT); 49 } 50 51 mac->ops.set_lan_id(hw); 52 53 return 0; 54 } 55 56 /** 57 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 58 * 59 * @hw: pointer to the HW structure 60 * 61 * Determines the LAN function id by reading memory-mapped registers 62 * and swaps the port value if requested. 63 **/ 64 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 65 { 66 struct e1000_bus_info *bus = &hw->bus; 67 u32 reg; 68 69 /* The status register reports the correct function number 70 * for the device regardless of function swap state. 71 */ 72 reg = er32(STATUS); 73 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 74 } 75 76 /** 77 * e1000_set_lan_id_single_port - Set LAN id for a single port device 78 * @hw: pointer to the HW structure 79 * 80 * Sets the LAN function id to zero for a single port device. 81 **/ 82 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 83 { 84 struct e1000_bus_info *bus = &hw->bus; 85 86 bus->func = 0; 87 } 88 89 /** 90 * e1000_clear_vfta_generic - Clear VLAN filter table 91 * @hw: pointer to the HW structure 92 * 93 * Clears the register array which contains the VLAN filter table by 94 * setting all the values to 0. 95 **/ 96 void e1000_clear_vfta_generic(struct e1000_hw *hw) 97 { 98 u32 offset; 99 100 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 101 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 102 e1e_flush(); 103 } 104 } 105 106 /** 107 * e1000_write_vfta_generic - Write value to VLAN filter table 108 * @hw: pointer to the HW structure 109 * @offset: register offset in VLAN filter table 110 * @value: register value written to VLAN filter table 111 * 112 * Writes value at the given offset in the register array which stores 113 * the VLAN filter table. 114 **/ 115 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 116 { 117 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 118 e1e_flush(); 119 } 120 121 /** 122 * e1000e_init_rx_addrs - Initialize receive address's 123 * @hw: pointer to the HW structure 124 * @rar_count: receive address registers 125 * 126 * Setup the receive address registers by setting the base receive address 127 * register to the devices MAC address and clearing all the other receive 128 * address registers to 0. 129 **/ 130 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 131 { 132 u32 i; 133 u8 mac_addr[ETH_ALEN] = { 0 }; 134 135 /* Setup the receive address */ 136 e_dbg("Programming MAC Address into RAR[0]\n"); 137 138 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 139 140 /* Zero out the other (rar_entry_count - 1) receive addresses */ 141 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 142 for (i = 1; i < rar_count; i++) 143 hw->mac.ops.rar_set(hw, mac_addr, i); 144 } 145 146 /** 147 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 148 * @hw: pointer to the HW structure 149 * 150 * Checks the nvm for an alternate MAC address. An alternate MAC address 151 * can be setup by pre-boot software and must be treated like a permanent 152 * address and must override the actual permanent MAC address. If an 153 * alternate MAC address is found it is programmed into RAR0, replacing 154 * the permanent address that was installed into RAR0 by the Si on reset. 155 * This function will return SUCCESS unless it encounters an error while 156 * reading the EEPROM. 157 **/ 158 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 159 { 160 u32 i; 161 s32 ret_val; 162 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 163 u8 alt_mac_addr[ETH_ALEN]; 164 165 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); 166 if (ret_val) 167 return ret_val; 168 169 /* not supported on 82573 */ 170 if (hw->mac.type == e1000_82573) 171 return 0; 172 173 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 174 &nvm_alt_mac_addr_offset); 175 if (ret_val) { 176 e_dbg("NVM Read Error\n"); 177 return ret_val; 178 } 179 180 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 181 (nvm_alt_mac_addr_offset == 0x0000)) 182 /* There is no Alternate MAC Address */ 183 return 0; 184 185 if (hw->bus.func == E1000_FUNC_1) 186 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 187 for (i = 0; i < ETH_ALEN; i += 2) { 188 offset = nvm_alt_mac_addr_offset + (i >> 1); 189 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 190 if (ret_val) { 191 e_dbg("NVM Read Error\n"); 192 return ret_val; 193 } 194 195 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 196 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 197 } 198 199 /* if multicast bit is set, the alternate address will not be used */ 200 if (is_multicast_ether_addr(alt_mac_addr)) { 201 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 202 return 0; 203 } 204 205 /* We have a valid alternate MAC address, and we want to treat it the 206 * same as the normal permanent MAC address stored by the HW into the 207 * RAR. Do this by mapping this address into RAR0. 208 */ 209 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 210 211 return 0; 212 } 213 214 u32 e1000e_rar_get_count_generic(struct e1000_hw *hw) 215 { 216 return hw->mac.rar_entry_count; 217 } 218 219 /** 220 * e1000e_rar_set_generic - Set receive address register 221 * @hw: pointer to the HW structure 222 * @addr: pointer to the receive address 223 * @index: receive address array register 224 * 225 * Sets the receive address array register at index to the address passed 226 * in by addr. 227 **/ 228 int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 229 { 230 u32 rar_low, rar_high; 231 232 /* HW expects these in little endian so we reverse the byte order 233 * from network order (big endian) to little endian 234 */ 235 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 236 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 237 238 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 239 240 /* If MAC address zero, no need to set the AV bit */ 241 if (rar_low || rar_high) 242 rar_high |= E1000_RAH_AV; 243 244 /* Some bridges will combine consecutive 32-bit writes into 245 * a single burst write, which will malfunction on some parts. 246 * The flushes avoid this. 247 */ 248 ew32(RAL(index), rar_low); 249 e1e_flush(); 250 ew32(RAH(index), rar_high); 251 e1e_flush(); 252 253 return 0; 254 } 255 256 /** 257 * e1000_hash_mc_addr - Generate a multicast hash value 258 * @hw: pointer to the HW structure 259 * @mc_addr: pointer to a multicast address 260 * 261 * Generates a multicast address hash value which is used to determine 262 * the multicast filter table array address and new table value. 263 **/ 264 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 265 { 266 u32 hash_value, hash_mask; 267 u8 bit_shift = 0; 268 269 /* Register count multiplied by bits per register */ 270 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 271 272 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 273 * where 0xFF would still fall within the hash mask. 274 */ 275 while (hash_mask >> bit_shift != 0xFF) 276 bit_shift++; 277 278 /* The portion of the address that is used for the hash table 279 * is determined by the mc_filter_type setting. 280 * The algorithm is such that there is a total of 8 bits of shifting. 281 * The bit_shift for a mc_filter_type of 0 represents the number of 282 * left-shifts where the MSB of mc_addr[5] would still fall within 283 * the hash_mask. Case 0 does this exactly. Since there are a total 284 * of 8 bits of shifting, then mc_addr[4] will shift right the 285 * remaining number of bits. Thus 8 - bit_shift. The rest of the 286 * cases are a variation of this algorithm...essentially raising the 287 * number of bits to shift mc_addr[5] left, while still keeping the 288 * 8-bit shifting total. 289 * 290 * For example, given the following Destination MAC Address and an 291 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 292 * we can see that the bit_shift for case 0 is 4. These are the hash 293 * values resulting from each mc_filter_type... 294 * [0] [1] [2] [3] [4] [5] 295 * 01 AA 00 12 34 56 296 * LSB MSB 297 * 298 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 299 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 300 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 301 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 302 */ 303 switch (hw->mac.mc_filter_type) { 304 default: 305 case 0: 306 break; 307 case 1: 308 bit_shift += 1; 309 break; 310 case 2: 311 bit_shift += 2; 312 break; 313 case 3: 314 bit_shift += 4; 315 break; 316 } 317 318 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 319 (((u16)mc_addr[5]) << bit_shift))); 320 321 return hash_value; 322 } 323 324 /** 325 * e1000e_update_mc_addr_list_generic - Update Multicast addresses 326 * @hw: pointer to the HW structure 327 * @mc_addr_list: array of multicast addresses to program 328 * @mc_addr_count: number of multicast addresses to program 329 * 330 * Updates entire Multicast Table Array. 331 * The caller must have a packed mc_addr_list of multicast addresses. 332 **/ 333 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 334 u8 *mc_addr_list, u32 mc_addr_count) 335 { 336 u32 hash_value, hash_bit, hash_reg; 337 int i; 338 339 /* clear mta_shadow */ 340 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 341 342 /* update mta_shadow from mc_addr_list */ 343 for (i = 0; (u32)i < mc_addr_count; i++) { 344 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 345 346 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 347 hash_bit = hash_value & 0x1F; 348 349 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); 350 mc_addr_list += (ETH_ALEN); 351 } 352 353 /* replace the entire MTA table */ 354 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 355 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 356 e1e_flush(); 357 } 358 359 /** 360 * e1000e_clear_hw_cntrs_base - Clear base hardware counters 361 * @hw: pointer to the HW structure 362 * 363 * Clears the base hardware counters by reading the counter registers. 364 **/ 365 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) 366 { 367 er32(CRCERRS); 368 er32(SYMERRS); 369 er32(MPC); 370 er32(SCC); 371 er32(ECOL); 372 er32(MCC); 373 er32(LATECOL); 374 er32(COLC); 375 er32(DC); 376 er32(SEC); 377 er32(RLEC); 378 er32(XONRXC); 379 er32(XONTXC); 380 er32(XOFFRXC); 381 er32(XOFFTXC); 382 er32(FCRUC); 383 er32(GPRC); 384 er32(BPRC); 385 er32(MPRC); 386 er32(GPTC); 387 er32(GORCL); 388 er32(GORCH); 389 er32(GOTCL); 390 er32(GOTCH); 391 er32(RNBC); 392 er32(RUC); 393 er32(RFC); 394 er32(ROC); 395 er32(RJC); 396 er32(TORL); 397 er32(TORH); 398 er32(TOTL); 399 er32(TOTH); 400 er32(TPR); 401 er32(TPT); 402 er32(MPTC); 403 er32(BPTC); 404 } 405 406 /** 407 * e1000e_check_for_copper_link - Check for link (Copper) 408 * @hw: pointer to the HW structure 409 * 410 * Checks to see of the link status of the hardware has changed. If a 411 * change in link status has been detected, then we read the PHY registers 412 * to get the current speed/duplex if link exists. 413 * 414 * Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link 415 * up). 416 **/ 417 s32 e1000e_check_for_copper_link(struct e1000_hw *hw) 418 { 419 struct e1000_mac_info *mac = &hw->mac; 420 s32 ret_val; 421 bool link; 422 423 /* We only want to go out to the PHY registers to see if Auto-Neg 424 * has completed and/or if our link status has changed. The 425 * get_link_status flag is set upon receiving a Link Status 426 * Change or Rx Sequence Error interrupt. 427 */ 428 if (!mac->get_link_status) 429 return 1; 430 431 /* First we want to see if the MII Status Register reports 432 * link. If so, then we want to get the current speed/duplex 433 * of the PHY. 434 */ 435 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 436 if (ret_val) 437 return ret_val; 438 439 if (!link) 440 return 0; /* No link detected */ 441 442 mac->get_link_status = false; 443 444 /* Check if there was DownShift, must be checked 445 * immediately after link-up 446 */ 447 e1000e_check_downshift(hw); 448 449 /* If we are forcing speed/duplex, then we simply return since 450 * we have already determined whether we have link or not. 451 */ 452 if (!mac->autoneg) 453 return -E1000_ERR_CONFIG; 454 455 /* Auto-Neg is enabled. Auto Speed Detection takes care 456 * of MAC speed/duplex configuration. So we only need to 457 * configure Collision Distance in the MAC. 458 */ 459 mac->ops.config_collision_dist(hw); 460 461 /* Configure Flow Control now that Auto-Neg has completed. 462 * First, we need to restore the desired flow control 463 * settings because we may have had to re-autoneg with a 464 * different link partner. 465 */ 466 ret_val = e1000e_config_fc_after_link_up(hw); 467 if (ret_val) { 468 e_dbg("Error configuring flow control\n"); 469 return ret_val; 470 } 471 472 return 1; 473 } 474 475 /** 476 * e1000e_check_for_fiber_link - Check for link (Fiber) 477 * @hw: pointer to the HW structure 478 * 479 * Checks for link up on the hardware. If link is not up and we have 480 * a signal, then we need to force link up. 481 **/ 482 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) 483 { 484 struct e1000_mac_info *mac = &hw->mac; 485 u32 rxcw; 486 u32 ctrl; 487 u32 status; 488 s32 ret_val; 489 490 ctrl = er32(CTRL); 491 status = er32(STATUS); 492 rxcw = er32(RXCW); 493 494 /* If we don't have link (auto-negotiation failed or link partner 495 * cannot auto-negotiate), the cable is plugged in (we have signal), 496 * and our link partner is not trying to auto-negotiate with us (we 497 * are receiving idles or data), we need to force link up. We also 498 * need to give auto-negotiation time to complete, in case the cable 499 * was just plugged in. The autoneg_failed flag does this. 500 */ 501 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 502 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 503 !(rxcw & E1000_RXCW_C)) { 504 if (!mac->autoneg_failed) { 505 mac->autoneg_failed = true; 506 return 0; 507 } 508 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 509 510 /* Disable auto-negotiation in the TXCW register */ 511 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 512 513 /* Force link-up and also force full-duplex. */ 514 ctrl = er32(CTRL); 515 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 516 ew32(CTRL, ctrl); 517 518 /* Configure Flow Control after forcing link up. */ 519 ret_val = e1000e_config_fc_after_link_up(hw); 520 if (ret_val) { 521 e_dbg("Error configuring flow control\n"); 522 return ret_val; 523 } 524 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 525 /* If we are forcing link and we are receiving /C/ ordered 526 * sets, re-enable auto-negotiation in the TXCW register 527 * and disable forced link in the Device Control register 528 * in an attempt to auto-negotiate with our link partner. 529 */ 530 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 531 ew32(TXCW, mac->txcw); 532 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 533 534 mac->serdes_has_link = true; 535 } 536 537 return 0; 538 } 539 540 /** 541 * e1000e_check_for_serdes_link - Check for link (Serdes) 542 * @hw: pointer to the HW structure 543 * 544 * Checks for link up on the hardware. If link is not up and we have 545 * a signal, then we need to force link up. 546 **/ 547 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) 548 { 549 struct e1000_mac_info *mac = &hw->mac; 550 u32 rxcw; 551 u32 ctrl; 552 u32 status; 553 s32 ret_val; 554 555 ctrl = er32(CTRL); 556 status = er32(STATUS); 557 rxcw = er32(RXCW); 558 559 /* If we don't have link (auto-negotiation failed or link partner 560 * cannot auto-negotiate), and our link partner is not trying to 561 * auto-negotiate with us (we are receiving idles or data), 562 * we need to force link up. We also need to give auto-negotiation 563 * time to complete. 564 */ 565 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 566 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 567 if (!mac->autoneg_failed) { 568 mac->autoneg_failed = true; 569 return 0; 570 } 571 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 572 573 /* Disable auto-negotiation in the TXCW register */ 574 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 575 576 /* Force link-up and also force full-duplex. */ 577 ctrl = er32(CTRL); 578 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 579 ew32(CTRL, ctrl); 580 581 /* Configure Flow Control after forcing link up. */ 582 ret_val = e1000e_config_fc_after_link_up(hw); 583 if (ret_val) { 584 e_dbg("Error configuring flow control\n"); 585 return ret_val; 586 } 587 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 588 /* If we are forcing link and we are receiving /C/ ordered 589 * sets, re-enable auto-negotiation in the TXCW register 590 * and disable forced link in the Device Control register 591 * in an attempt to auto-negotiate with our link partner. 592 */ 593 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 594 ew32(TXCW, mac->txcw); 595 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 596 597 mac->serdes_has_link = true; 598 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 599 /* If we force link for non-auto-negotiation switch, check 600 * link status based on MAC synchronization for internal 601 * serdes media type. 602 */ 603 /* SYNCH bit and IV bit are sticky. */ 604 usleep_range(10, 20); 605 rxcw = er32(RXCW); 606 if (rxcw & E1000_RXCW_SYNCH) { 607 if (!(rxcw & E1000_RXCW_IV)) { 608 mac->serdes_has_link = true; 609 e_dbg("SERDES: Link up - forced.\n"); 610 } 611 } else { 612 mac->serdes_has_link = false; 613 e_dbg("SERDES: Link down - force failed.\n"); 614 } 615 } 616 617 if (E1000_TXCW_ANE & er32(TXCW)) { 618 status = er32(STATUS); 619 if (status & E1000_STATUS_LU) { 620 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 621 usleep_range(10, 20); 622 rxcw = er32(RXCW); 623 if (rxcw & E1000_RXCW_SYNCH) { 624 if (!(rxcw & E1000_RXCW_IV)) { 625 mac->serdes_has_link = true; 626 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); 627 } else { 628 mac->serdes_has_link = false; 629 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); 630 } 631 } else { 632 mac->serdes_has_link = false; 633 e_dbg("SERDES: Link down - no sync.\n"); 634 } 635 } else { 636 mac->serdes_has_link = false; 637 e_dbg("SERDES: Link down - autoneg failed\n"); 638 } 639 } 640 641 return 0; 642 } 643 644 /** 645 * e1000_set_default_fc_generic - Set flow control default values 646 * @hw: pointer to the HW structure 647 * 648 * Read the EEPROM for the default values for flow control and store the 649 * values. 650 **/ 651 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 652 { 653 s32 ret_val; 654 u16 nvm_data; 655 656 /* Read and store word 0x0F of the EEPROM. This word contains bits 657 * that determine the hardware's default PAUSE (flow control) mode, 658 * a bit that determines whether the HW defaults to enabling or 659 * disabling auto-negotiation, and the direction of the 660 * SW defined pins. If there is no SW over-ride of the flow 661 * control setting, then the variable hw->fc will 662 * be initialized based on a value in the EEPROM. 663 */ 664 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 665 666 if (ret_val) { 667 e_dbg("NVM Read Error\n"); 668 return ret_val; 669 } 670 671 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 672 hw->fc.requested_mode = e1000_fc_none; 673 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) 674 hw->fc.requested_mode = e1000_fc_tx_pause; 675 else 676 hw->fc.requested_mode = e1000_fc_full; 677 678 return 0; 679 } 680 681 /** 682 * e1000e_setup_link_generic - Setup flow control and link settings 683 * @hw: pointer to the HW structure 684 * 685 * Determines which flow control settings to use, then configures flow 686 * control. Calls the appropriate media-specific link configuration 687 * function. Assuming the adapter has a valid link partner, a valid link 688 * should be established. Assumes the hardware has previously been reset 689 * and the transmitter and receiver are not enabled. 690 **/ 691 s32 e1000e_setup_link_generic(struct e1000_hw *hw) 692 { 693 s32 ret_val; 694 695 /* In the case of the phy reset being blocked, we already have a link. 696 * We do not need to set it up again. 697 */ 698 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 699 return 0; 700 701 /* If requested flow control is set to default, set flow control 702 * based on the EEPROM flow control settings. 703 */ 704 if (hw->fc.requested_mode == e1000_fc_default) { 705 ret_val = e1000_set_default_fc_generic(hw); 706 if (ret_val) 707 return ret_val; 708 } 709 710 /* Save off the requested flow control mode for use later. Depending 711 * on the link partner's capabilities, we may or may not use this mode. 712 */ 713 hw->fc.current_mode = hw->fc.requested_mode; 714 715 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 716 717 /* Call the necessary media_type subroutine to configure the link. */ 718 ret_val = hw->mac.ops.setup_physical_interface(hw); 719 if (ret_val) 720 return ret_val; 721 722 /* Initialize the flow control address, type, and PAUSE timer 723 * registers to their default values. This is done even if flow 724 * control is disabled, because it does not hurt anything to 725 * initialize these registers. 726 */ 727 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 728 ew32(FCT, FLOW_CONTROL_TYPE); 729 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 730 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 731 732 ew32(FCTTV, hw->fc.pause_time); 733 734 return e1000e_set_fc_watermarks(hw); 735 } 736 737 /** 738 * e1000_commit_fc_settings_generic - Configure flow control 739 * @hw: pointer to the HW structure 740 * 741 * Write the flow control settings to the Transmit Config Word Register (TXCW) 742 * base on the flow control settings in e1000_mac_info. 743 **/ 744 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 745 { 746 struct e1000_mac_info *mac = &hw->mac; 747 u32 txcw; 748 749 /* Check for a software override of the flow control settings, and 750 * setup the device accordingly. If auto-negotiation is enabled, then 751 * software will have to set the "PAUSE" bits to the correct value in 752 * the Transmit Config Word Register (TXCW) and re-start auto- 753 * negotiation. However, if auto-negotiation is disabled, then 754 * software will have to manually configure the two flow control enable 755 * bits in the CTRL register. 756 * 757 * The possible values of the "fc" parameter are: 758 * 0: Flow control is completely disabled 759 * 1: Rx flow control is enabled (we can receive pause frames, 760 * but not send pause frames). 761 * 2: Tx flow control is enabled (we can send pause frames but we 762 * do not support receiving pause frames). 763 * 3: Both Rx and Tx flow control (symmetric) are enabled. 764 */ 765 switch (hw->fc.current_mode) { 766 case e1000_fc_none: 767 /* Flow control completely disabled by a software over-ride. */ 768 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 769 break; 770 case e1000_fc_rx_pause: 771 /* Rx Flow control is enabled and Tx Flow control is disabled 772 * by a software over-ride. Since there really isn't a way to 773 * advertise that we are capable of Rx Pause ONLY, we will 774 * advertise that we support both symmetric and asymmetric Rx 775 * PAUSE. Later, we will disable the adapter's ability to send 776 * PAUSE frames. 777 */ 778 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 779 break; 780 case e1000_fc_tx_pause: 781 /* Tx Flow control is enabled, and Rx Flow control is disabled, 782 * by a software over-ride. 783 */ 784 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 785 break; 786 case e1000_fc_full: 787 /* Flow control (both Rx and Tx) is enabled by a software 788 * over-ride. 789 */ 790 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 791 break; 792 default: 793 e_dbg("Flow control param set incorrectly\n"); 794 return -E1000_ERR_CONFIG; 795 } 796 797 ew32(TXCW, txcw); 798 mac->txcw = txcw; 799 800 return 0; 801 } 802 803 /** 804 * e1000_poll_fiber_serdes_link_generic - Poll for link up 805 * @hw: pointer to the HW structure 806 * 807 * Polls for link up by reading the status register, if link fails to come 808 * up with auto-negotiation, then the link is forced if a signal is detected. 809 **/ 810 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 811 { 812 struct e1000_mac_info *mac = &hw->mac; 813 u32 i, status; 814 s32 ret_val; 815 816 /* If we have a signal (the cable is plugged in, or assumed true for 817 * serdes media) then poll for a "Link-Up" indication in the Device 818 * Status Register. Time-out if a link isn't seen in 500 milliseconds 819 * seconds (Auto-negotiation should complete in less than 500 820 * milliseconds even if the other end is doing it in SW). 821 */ 822 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 823 usleep_range(10000, 20000); 824 status = er32(STATUS); 825 if (status & E1000_STATUS_LU) 826 break; 827 } 828 if (i == FIBER_LINK_UP_LIMIT) { 829 e_dbg("Never got a valid link from auto-neg!!!\n"); 830 mac->autoneg_failed = true; 831 /* AutoNeg failed to achieve a link, so we'll call 832 * mac->check_for_link. This routine will force the 833 * link up if we detect a signal. This will allow us to 834 * communicate with non-autonegotiating link partners. 835 */ 836 ret_val = mac->ops.check_for_link(hw); 837 if (ret_val) { 838 e_dbg("Error while checking for link\n"); 839 return ret_val; 840 } 841 mac->autoneg_failed = false; 842 } else { 843 mac->autoneg_failed = false; 844 e_dbg("Valid Link Found\n"); 845 } 846 847 return 0; 848 } 849 850 /** 851 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes 852 * @hw: pointer to the HW structure 853 * 854 * Configures collision distance and flow control for fiber and serdes 855 * links. Upon successful setup, poll for link. 856 **/ 857 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) 858 { 859 u32 ctrl; 860 s32 ret_val; 861 862 ctrl = er32(CTRL); 863 864 /* Take the link out of reset */ 865 ctrl &= ~E1000_CTRL_LRST; 866 867 hw->mac.ops.config_collision_dist(hw); 868 869 ret_val = e1000_commit_fc_settings_generic(hw); 870 if (ret_val) 871 return ret_val; 872 873 /* Since auto-negotiation is enabled, take the link out of reset (the 874 * link will be in reset, because we previously reset the chip). This 875 * will restart auto-negotiation. If auto-negotiation is successful 876 * then the link-up status bit will be set and the flow control enable 877 * bits (RFCE and TFCE) will be set according to their negotiated value. 878 */ 879 e_dbg("Auto-negotiation enabled\n"); 880 881 ew32(CTRL, ctrl); 882 e1e_flush(); 883 usleep_range(1000, 2000); 884 885 /* For these adapters, the SW definable pin 1 is set when the optics 886 * detect a signal. If we have a signal, then poll for a "Link-Up" 887 * indication. 888 */ 889 if (hw->phy.media_type == e1000_media_type_internal_serdes || 890 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 891 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 892 } else { 893 e_dbg("No signal detected\n"); 894 } 895 896 return ret_val; 897 } 898 899 /** 900 * e1000e_config_collision_dist_generic - Configure collision distance 901 * @hw: pointer to the HW structure 902 * 903 * Configures the collision distance to the default value and is used 904 * during link setup. 905 **/ 906 void e1000e_config_collision_dist_generic(struct e1000_hw *hw) 907 { 908 u32 tctl; 909 910 tctl = er32(TCTL); 911 912 tctl &= ~E1000_TCTL_COLD; 913 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 914 915 ew32(TCTL, tctl); 916 e1e_flush(); 917 } 918 919 /** 920 * e1000e_set_fc_watermarks - Set flow control high/low watermarks 921 * @hw: pointer to the HW structure 922 * 923 * Sets the flow control high/low threshold (watermark) registers. If 924 * flow control XON frame transmission is enabled, then set XON frame 925 * transmission as well. 926 **/ 927 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) 928 { 929 u32 fcrtl = 0, fcrth = 0; 930 931 /* Set the flow control receive threshold registers. Normally, 932 * these registers will be set to a default threshold that may be 933 * adjusted later by the driver's runtime code. However, if the 934 * ability to transmit pause frames is not enabled, then these 935 * registers will be set to 0. 936 */ 937 if (hw->fc.current_mode & e1000_fc_tx_pause) { 938 /* We need to set up the Receive Threshold high and low water 939 * marks as well as (optionally) enabling the transmission of 940 * XON frames. 941 */ 942 fcrtl = hw->fc.low_water; 943 if (hw->fc.send_xon) 944 fcrtl |= E1000_FCRTL_XONE; 945 946 fcrth = hw->fc.high_water; 947 } 948 ew32(FCRTL, fcrtl); 949 ew32(FCRTH, fcrth); 950 951 return 0; 952 } 953 954 /** 955 * e1000e_force_mac_fc - Force the MAC's flow control settings 956 * @hw: pointer to the HW structure 957 * 958 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 959 * device control register to reflect the adapter settings. TFCE and RFCE 960 * need to be explicitly set by software when a copper PHY is used because 961 * autonegotiation is managed by the PHY rather than the MAC. Software must 962 * also configure these bits when link is forced on a fiber connection. 963 **/ 964 s32 e1000e_force_mac_fc(struct e1000_hw *hw) 965 { 966 u32 ctrl; 967 968 ctrl = er32(CTRL); 969 970 /* Because we didn't get link via the internal auto-negotiation 971 * mechanism (we either forced link or we got link via PHY 972 * auto-neg), we have to manually enable/disable transmit an 973 * receive flow control. 974 * 975 * The "Case" statement below enables/disable flow control 976 * according to the "hw->fc.current_mode" parameter. 977 * 978 * The possible values of the "fc" parameter are: 979 * 0: Flow control is completely disabled 980 * 1: Rx flow control is enabled (we can receive pause 981 * frames but not send pause frames). 982 * 2: Tx flow control is enabled (we can send pause frames 983 * frames but we do not receive pause frames). 984 * 3: Both Rx and Tx flow control (symmetric) is enabled. 985 * other: No other values should be possible at this point. 986 */ 987 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 988 989 switch (hw->fc.current_mode) { 990 case e1000_fc_none: 991 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 992 break; 993 case e1000_fc_rx_pause: 994 ctrl &= (~E1000_CTRL_TFCE); 995 ctrl |= E1000_CTRL_RFCE; 996 break; 997 case e1000_fc_tx_pause: 998 ctrl &= (~E1000_CTRL_RFCE); 999 ctrl |= E1000_CTRL_TFCE; 1000 break; 1001 case e1000_fc_full: 1002 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1003 break; 1004 default: 1005 e_dbg("Flow control param set incorrectly\n"); 1006 return -E1000_ERR_CONFIG; 1007 } 1008 1009 ew32(CTRL, ctrl); 1010 1011 return 0; 1012 } 1013 1014 /** 1015 * e1000e_config_fc_after_link_up - Configures flow control after link 1016 * @hw: pointer to the HW structure 1017 * 1018 * Checks the status of auto-negotiation after link up to ensure that the 1019 * speed and duplex were not forced. If the link needed to be forced, then 1020 * flow control needs to be forced also. If auto-negotiation is enabled 1021 * and did not fail, then we configure flow control based on our link 1022 * partner. 1023 **/ 1024 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) 1025 { 1026 struct e1000_mac_info *mac = &hw->mac; 1027 s32 ret_val = 0; 1028 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1029 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1030 u16 speed, duplex; 1031 1032 /* Check for the case where we have fiber media and auto-neg failed 1033 * so we had to force link. In this case, we need to force the 1034 * configuration of the MAC to match the "fc" parameter. 1035 */ 1036 if (mac->autoneg_failed) { 1037 if (hw->phy.media_type == e1000_media_type_fiber || 1038 hw->phy.media_type == e1000_media_type_internal_serdes) 1039 ret_val = e1000e_force_mac_fc(hw); 1040 } else { 1041 if (hw->phy.media_type == e1000_media_type_copper) 1042 ret_val = e1000e_force_mac_fc(hw); 1043 } 1044 1045 if (ret_val) { 1046 e_dbg("Error forcing flow control settings\n"); 1047 return ret_val; 1048 } 1049 1050 /* Check for the case where we have copper media and auto-neg is 1051 * enabled. In this case, we need to check and see if Auto-Neg 1052 * has completed, and if so, how the PHY and link partner has 1053 * flow control configured. 1054 */ 1055 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1056 /* Read the MII Status Register and check to see if AutoNeg 1057 * has completed. We read this twice because this reg has 1058 * some "sticky" (latched) bits. 1059 */ 1060 ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg); 1061 if (ret_val) 1062 return ret_val; 1063 ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg); 1064 if (ret_val) 1065 return ret_val; 1066 1067 if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) { 1068 e_dbg("Copper PHY and Auto Neg has not completed.\n"); 1069 return ret_val; 1070 } 1071 1072 /* The AutoNeg process has completed, so we now need to 1073 * read both the Auto Negotiation Advertisement 1074 * Register (Address 4) and the Auto_Negotiation Base 1075 * Page Ability Register (Address 5) to determine how 1076 * flow control was negotiated. 1077 */ 1078 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg); 1079 if (ret_val) 1080 return ret_val; 1081 ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg); 1082 if (ret_val) 1083 return ret_val; 1084 1085 /* Two bits in the Auto Negotiation Advertisement Register 1086 * (Address 4) and two bits in the Auto Negotiation Base 1087 * Page Ability Register (Address 5) determine flow control 1088 * for both the PHY and the link partner. The following 1089 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1090 * 1999, describes these PAUSE resolution bits and how flow 1091 * control is determined based upon these settings. 1092 * NOTE: DC = Don't Care 1093 * 1094 * LOCAL DEVICE | LINK PARTNER 1095 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1096 *-------|---------|-------|---------|-------------------- 1097 * 0 | 0 | DC | DC | e1000_fc_none 1098 * 0 | 1 | 0 | DC | e1000_fc_none 1099 * 0 | 1 | 1 | 0 | e1000_fc_none 1100 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1101 * 1 | 0 | 0 | DC | e1000_fc_none 1102 * 1 | DC | 1 | DC | e1000_fc_full 1103 * 1 | 1 | 0 | 0 | e1000_fc_none 1104 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1105 * 1106 * Are both PAUSE bits set to 1? If so, this implies 1107 * Symmetric Flow Control is enabled at both ends. The 1108 * ASM_DIR bits are irrelevant per the spec. 1109 * 1110 * For Symmetric Flow Control: 1111 * 1112 * LOCAL DEVICE | LINK PARTNER 1113 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1114 *-------|---------|-------|---------|-------------------- 1115 * 1 | DC | 1 | DC | E1000_fc_full 1116 * 1117 */ 1118 if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1119 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) { 1120 /* Now we need to check if the user selected Rx ONLY 1121 * of pause frames. In this case, we had to advertise 1122 * FULL flow control because we could not advertise Rx 1123 * ONLY. Hence, we must now check to see if we need to 1124 * turn OFF the TRANSMISSION of PAUSE frames. 1125 */ 1126 if (hw->fc.requested_mode == e1000_fc_full) { 1127 hw->fc.current_mode = e1000_fc_full; 1128 e_dbg("Flow Control = FULL.\n"); 1129 } else { 1130 hw->fc.current_mode = e1000_fc_rx_pause; 1131 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1132 } 1133 } 1134 /* For receiving PAUSE frames ONLY. 1135 * 1136 * LOCAL DEVICE | LINK PARTNER 1137 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1138 *-------|---------|-------|---------|-------------------- 1139 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1140 */ 1141 else if (!(mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1142 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) && 1143 (mii_nway_lp_ability_reg & LPA_PAUSE_CAP) && 1144 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) { 1145 hw->fc.current_mode = e1000_fc_tx_pause; 1146 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1147 } 1148 /* For transmitting PAUSE frames ONLY. 1149 * 1150 * LOCAL DEVICE | LINK PARTNER 1151 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1152 *-------|---------|-------|---------|-------------------- 1153 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1154 */ 1155 else if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) && 1156 (mii_nway_adv_reg & ADVERTISE_PAUSE_ASYM) && 1157 !(mii_nway_lp_ability_reg & LPA_PAUSE_CAP) && 1158 (mii_nway_lp_ability_reg & LPA_PAUSE_ASYM)) { 1159 hw->fc.current_mode = e1000_fc_rx_pause; 1160 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1161 } else { 1162 /* Per the IEEE spec, at this point flow control 1163 * should be disabled. 1164 */ 1165 hw->fc.current_mode = e1000_fc_none; 1166 e_dbg("Flow Control = NONE.\n"); 1167 } 1168 1169 /* Now we need to do one last check... If we auto- 1170 * negotiated to HALF DUPLEX, flow control should not be 1171 * enabled per IEEE 802.3 spec. 1172 */ 1173 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1174 if (ret_val) { 1175 e_dbg("Error getting link speed and duplex\n"); 1176 return ret_val; 1177 } 1178 1179 if (duplex == HALF_DUPLEX) 1180 hw->fc.current_mode = e1000_fc_none; 1181 1182 /* Now we call a subroutine to actually force the MAC 1183 * controller to use the correct flow control settings. 1184 */ 1185 ret_val = e1000e_force_mac_fc(hw); 1186 if (ret_val) { 1187 e_dbg("Error forcing flow control settings\n"); 1188 return ret_val; 1189 } 1190 } 1191 1192 /* Check for the case where we have SerDes media and auto-neg is 1193 * enabled. In this case, we need to check and see if Auto-Neg 1194 * has completed, and if so, how the PHY and link partner has 1195 * flow control configured. 1196 */ 1197 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1198 mac->autoneg) { 1199 /* Read the PCS_LSTS and check to see if AutoNeg 1200 * has completed. 1201 */ 1202 pcs_status_reg = er32(PCS_LSTAT); 1203 1204 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1205 e_dbg("PCS Auto Neg has not completed.\n"); 1206 return ret_val; 1207 } 1208 1209 /* The AutoNeg process has completed, so we now need to 1210 * read both the Auto Negotiation Advertisement 1211 * Register (PCS_ANADV) and the Auto_Negotiation Base 1212 * Page Ability Register (PCS_LPAB) to determine how 1213 * flow control was negotiated. 1214 */ 1215 pcs_adv_reg = er32(PCS_ANADV); 1216 pcs_lp_ability_reg = er32(PCS_LPAB); 1217 1218 /* Two bits in the Auto Negotiation Advertisement Register 1219 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1220 * Page Ability Register (PCS_LPAB) determine flow control 1221 * for both the PHY and the link partner. The following 1222 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1223 * 1999, describes these PAUSE resolution bits and how flow 1224 * control is determined based upon these settings. 1225 * NOTE: DC = Don't Care 1226 * 1227 * LOCAL DEVICE | LINK PARTNER 1228 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1229 *-------|---------|-------|---------|-------------------- 1230 * 0 | 0 | DC | DC | e1000_fc_none 1231 * 0 | 1 | 0 | DC | e1000_fc_none 1232 * 0 | 1 | 1 | 0 | e1000_fc_none 1233 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1234 * 1 | 0 | 0 | DC | e1000_fc_none 1235 * 1 | DC | 1 | DC | e1000_fc_full 1236 * 1 | 1 | 0 | 0 | e1000_fc_none 1237 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1238 * 1239 * Are both PAUSE bits set to 1? If so, this implies 1240 * Symmetric Flow Control is enabled at both ends. The 1241 * ASM_DIR bits are irrelevant per the spec. 1242 * 1243 * For Symmetric Flow Control: 1244 * 1245 * LOCAL DEVICE | LINK PARTNER 1246 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1247 *-------|---------|-------|---------|-------------------- 1248 * 1 | DC | 1 | DC | e1000_fc_full 1249 * 1250 */ 1251 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1252 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1253 /* Now we need to check if the user selected Rx ONLY 1254 * of pause frames. In this case, we had to advertise 1255 * FULL flow control because we could not advertise Rx 1256 * ONLY. Hence, we must now check to see if we need to 1257 * turn OFF the TRANSMISSION of PAUSE frames. 1258 */ 1259 if (hw->fc.requested_mode == e1000_fc_full) { 1260 hw->fc.current_mode = e1000_fc_full; 1261 e_dbg("Flow Control = FULL.\n"); 1262 } else { 1263 hw->fc.current_mode = e1000_fc_rx_pause; 1264 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1265 } 1266 } 1267 /* For receiving PAUSE frames ONLY. 1268 * 1269 * LOCAL DEVICE | LINK PARTNER 1270 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1271 *-------|---------|-------|---------|-------------------- 1272 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1273 */ 1274 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1275 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1276 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1277 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1278 hw->fc.current_mode = e1000_fc_tx_pause; 1279 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1280 } 1281 /* For transmitting PAUSE frames ONLY. 1282 * 1283 * LOCAL DEVICE | LINK PARTNER 1284 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1285 *-------|---------|-------|---------|-------------------- 1286 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1287 */ 1288 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1289 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1290 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1291 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1292 hw->fc.current_mode = e1000_fc_rx_pause; 1293 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1294 } else { 1295 /* Per the IEEE spec, at this point flow control 1296 * should be disabled. 1297 */ 1298 hw->fc.current_mode = e1000_fc_none; 1299 e_dbg("Flow Control = NONE.\n"); 1300 } 1301 1302 /* Now we call a subroutine to actually force the MAC 1303 * controller to use the correct flow control settings. 1304 */ 1305 pcs_ctrl_reg = er32(PCS_LCTL); 1306 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1307 ew32(PCS_LCTL, pcs_ctrl_reg); 1308 1309 ret_val = e1000e_force_mac_fc(hw); 1310 if (ret_val) { 1311 e_dbg("Error forcing flow control settings\n"); 1312 return ret_val; 1313 } 1314 } 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex 1321 * @hw: pointer to the HW structure 1322 * @speed: stores the current speed 1323 * @duplex: stores the current duplex 1324 * 1325 * Read the status register for the current speed/duplex and store the current 1326 * speed and duplex for copper connections. 1327 **/ 1328 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1329 u16 *duplex) 1330 { 1331 u32 status; 1332 1333 status = er32(STATUS); 1334 if (status & E1000_STATUS_SPEED_1000) 1335 *speed = SPEED_1000; 1336 else if (status & E1000_STATUS_SPEED_100) 1337 *speed = SPEED_100; 1338 else 1339 *speed = SPEED_10; 1340 1341 if (status & E1000_STATUS_FD) 1342 *duplex = FULL_DUPLEX; 1343 else 1344 *duplex = HALF_DUPLEX; 1345 1346 e_dbg("%u Mbps, %s Duplex\n", 1347 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, 1348 *duplex == FULL_DUPLEX ? "Full" : "Half"); 1349 1350 return 0; 1351 } 1352 1353 /** 1354 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex 1355 * @hw: pointer to the HW structure 1356 * @speed: stores the current speed 1357 * @duplex: stores the current duplex 1358 * 1359 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1360 * for fiber/serdes links. 1361 **/ 1362 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw __always_unused 1363 *hw, u16 *speed, u16 *duplex) 1364 { 1365 *speed = SPEED_1000; 1366 *duplex = FULL_DUPLEX; 1367 1368 return 0; 1369 } 1370 1371 /** 1372 * e1000e_get_hw_semaphore - Acquire hardware semaphore 1373 * @hw: pointer to the HW structure 1374 * 1375 * Acquire the HW semaphore to access the PHY or NVM 1376 **/ 1377 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) 1378 { 1379 u32 swsm; 1380 s32 timeout = hw->nvm.word_size + 1; 1381 s32 i = 0; 1382 1383 /* Get the SW semaphore */ 1384 while (i < timeout) { 1385 swsm = er32(SWSM); 1386 if (!(swsm & E1000_SWSM_SMBI)) 1387 break; 1388 1389 usleep_range(50, 100); 1390 i++; 1391 } 1392 1393 if (i == timeout) { 1394 e_dbg("Driver can't access device - SMBI bit is set.\n"); 1395 return -E1000_ERR_NVM; 1396 } 1397 1398 /* Get the FW semaphore. */ 1399 for (i = 0; i < timeout; i++) { 1400 swsm = er32(SWSM); 1401 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 1402 1403 /* Semaphore acquired if bit latched */ 1404 if (er32(SWSM) & E1000_SWSM_SWESMBI) 1405 break; 1406 1407 usleep_range(50, 100); 1408 } 1409 1410 if (i == timeout) { 1411 /* Release semaphores */ 1412 e1000e_put_hw_semaphore(hw); 1413 e_dbg("Driver can't access the NVM\n"); 1414 return -E1000_ERR_NVM; 1415 } 1416 1417 return 0; 1418 } 1419 1420 /** 1421 * e1000e_put_hw_semaphore - Release hardware semaphore 1422 * @hw: pointer to the HW structure 1423 * 1424 * Release hardware semaphore used to access the PHY or NVM 1425 **/ 1426 void e1000e_put_hw_semaphore(struct e1000_hw *hw) 1427 { 1428 u32 swsm; 1429 1430 swsm = er32(SWSM); 1431 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1432 ew32(SWSM, swsm); 1433 } 1434 1435 /** 1436 * e1000e_get_auto_rd_done - Check for auto read completion 1437 * @hw: pointer to the HW structure 1438 * 1439 * Check EEPROM for Auto Read done bit. 1440 **/ 1441 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) 1442 { 1443 s32 i = 0; 1444 1445 while (i < AUTO_READ_DONE_TIMEOUT) { 1446 if (er32(EECD) & E1000_EECD_AUTO_RD) 1447 break; 1448 usleep_range(1000, 2000); 1449 i++; 1450 } 1451 1452 if (i == AUTO_READ_DONE_TIMEOUT) { 1453 e_dbg("Auto read by HW from NVM has not completed.\n"); 1454 return -E1000_ERR_RESET; 1455 } 1456 1457 return 0; 1458 } 1459 1460 /** 1461 * e1000e_valid_led_default - Verify a valid default LED config 1462 * @hw: pointer to the HW structure 1463 * @data: pointer to the NVM (EEPROM) 1464 * 1465 * Read the EEPROM for the current default LED configuration. If the 1466 * LED configuration is not valid, set to a valid LED configuration. 1467 **/ 1468 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) 1469 { 1470 s32 ret_val; 1471 1472 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1473 if (ret_val) { 1474 e_dbg("NVM Read Error\n"); 1475 return ret_val; 1476 } 1477 1478 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1479 *data = ID_LED_DEFAULT; 1480 1481 return 0; 1482 } 1483 1484 /** 1485 * e1000e_id_led_init_generic - 1486 * @hw: pointer to the HW structure 1487 * 1488 **/ 1489 s32 e1000e_id_led_init_generic(struct e1000_hw *hw) 1490 { 1491 struct e1000_mac_info *mac = &hw->mac; 1492 s32 ret_val; 1493 const u32 ledctl_mask = 0x000000FF; 1494 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1495 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1496 u16 data, i, temp; 1497 const u16 led_mask = 0x0F; 1498 1499 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1500 if (ret_val) 1501 return ret_val; 1502 1503 mac->ledctl_default = er32(LEDCTL); 1504 mac->ledctl_mode1 = mac->ledctl_default; 1505 mac->ledctl_mode2 = mac->ledctl_default; 1506 1507 for (i = 0; i < 4; i++) { 1508 temp = (data >> (i << 2)) & led_mask; 1509 switch (temp) { 1510 case ID_LED_ON1_DEF2: 1511 case ID_LED_ON1_ON2: 1512 case ID_LED_ON1_OFF2: 1513 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1514 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1515 break; 1516 case ID_LED_OFF1_DEF2: 1517 case ID_LED_OFF1_ON2: 1518 case ID_LED_OFF1_OFF2: 1519 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1520 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1521 break; 1522 default: 1523 /* Do nothing */ 1524 break; 1525 } 1526 switch (temp) { 1527 case ID_LED_DEF1_ON2: 1528 case ID_LED_ON1_ON2: 1529 case ID_LED_OFF1_ON2: 1530 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1531 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1532 break; 1533 case ID_LED_DEF1_OFF2: 1534 case ID_LED_ON1_OFF2: 1535 case ID_LED_OFF1_OFF2: 1536 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1537 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1538 break; 1539 default: 1540 /* Do nothing */ 1541 break; 1542 } 1543 } 1544 1545 return 0; 1546 } 1547 1548 /** 1549 * e1000e_setup_led_generic - Configures SW controllable LED 1550 * @hw: pointer to the HW structure 1551 * 1552 * This prepares the SW controllable LED for use and saves the current state 1553 * of the LED so it can be later restored. 1554 **/ 1555 s32 e1000e_setup_led_generic(struct e1000_hw *hw) 1556 { 1557 u32 ledctl; 1558 1559 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) 1560 return -E1000_ERR_CONFIG; 1561 1562 if (hw->phy.media_type == e1000_media_type_fiber) { 1563 ledctl = er32(LEDCTL); 1564 hw->mac.ledctl_default = ledctl; 1565 /* Turn off LED0 */ 1566 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1567 E1000_LEDCTL_LED0_MODE_MASK); 1568 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1569 E1000_LEDCTL_LED0_MODE_SHIFT); 1570 ew32(LEDCTL, ledctl); 1571 } else if (hw->phy.media_type == e1000_media_type_copper) { 1572 ew32(LEDCTL, hw->mac.ledctl_mode1); 1573 } 1574 1575 return 0; 1576 } 1577 1578 /** 1579 * e1000e_cleanup_led_generic - Set LED config to default operation 1580 * @hw: pointer to the HW structure 1581 * 1582 * Remove the current LED configuration and set the LED configuration 1583 * to the default value, saved from the EEPROM. 1584 **/ 1585 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) 1586 { 1587 ew32(LEDCTL, hw->mac.ledctl_default); 1588 return 0; 1589 } 1590 1591 /** 1592 * e1000e_blink_led_generic - Blink LED 1593 * @hw: pointer to the HW structure 1594 * 1595 * Blink the LEDs which are set to be on. 1596 **/ 1597 s32 e1000e_blink_led_generic(struct e1000_hw *hw) 1598 { 1599 u32 ledctl_blink = 0; 1600 u32 i; 1601 1602 if (hw->phy.media_type == e1000_media_type_fiber) { 1603 /* always blink LED0 for PCI-E fiber */ 1604 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1605 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1606 } else { 1607 /* Set the blink bit for each LED that's "on" (0x0E) 1608 * (or "off" if inverted) in ledctl_mode2. The blink 1609 * logic in hardware only works when mode is set to "on" 1610 * so it must be changed accordingly when the mode is 1611 * "off" and inverted. 1612 */ 1613 ledctl_blink = hw->mac.ledctl_mode2; 1614 for (i = 0; i < 32; i += 8) { 1615 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1616 E1000_LEDCTL_LED0_MODE_MASK; 1617 u32 led_default = hw->mac.ledctl_default >> i; 1618 1619 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1620 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1621 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1622 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1623 ledctl_blink &= 1624 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1625 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1626 E1000_LEDCTL_MODE_LED_ON) << i; 1627 } 1628 } 1629 } 1630 1631 ew32(LEDCTL, ledctl_blink); 1632 1633 return 0; 1634 } 1635 1636 /** 1637 * e1000e_led_on_generic - Turn LED on 1638 * @hw: pointer to the HW structure 1639 * 1640 * Turn LED on. 1641 **/ 1642 s32 e1000e_led_on_generic(struct e1000_hw *hw) 1643 { 1644 u32 ctrl; 1645 1646 switch (hw->phy.media_type) { 1647 case e1000_media_type_fiber: 1648 ctrl = er32(CTRL); 1649 ctrl &= ~E1000_CTRL_SWDPIN0; 1650 ctrl |= E1000_CTRL_SWDPIO0; 1651 ew32(CTRL, ctrl); 1652 break; 1653 case e1000_media_type_copper: 1654 ew32(LEDCTL, hw->mac.ledctl_mode2); 1655 break; 1656 default: 1657 break; 1658 } 1659 1660 return 0; 1661 } 1662 1663 /** 1664 * e1000e_led_off_generic - Turn LED off 1665 * @hw: pointer to the HW structure 1666 * 1667 * Turn LED off. 1668 **/ 1669 s32 e1000e_led_off_generic(struct e1000_hw *hw) 1670 { 1671 u32 ctrl; 1672 1673 switch (hw->phy.media_type) { 1674 case e1000_media_type_fiber: 1675 ctrl = er32(CTRL); 1676 ctrl |= E1000_CTRL_SWDPIN0; 1677 ctrl |= E1000_CTRL_SWDPIO0; 1678 ew32(CTRL, ctrl); 1679 break; 1680 case e1000_media_type_copper: 1681 ew32(LEDCTL, hw->mac.ledctl_mode1); 1682 break; 1683 default: 1684 break; 1685 } 1686 1687 return 0; 1688 } 1689 1690 /** 1691 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities 1692 * @hw: pointer to the HW structure 1693 * @no_snoop: bitmap of snoop events 1694 * 1695 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1696 **/ 1697 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) 1698 { 1699 u32 gcr; 1700 1701 if (no_snoop) { 1702 gcr = er32(GCR); 1703 gcr &= ~(PCIE_NO_SNOOP_ALL); 1704 gcr |= no_snoop; 1705 ew32(GCR, gcr); 1706 } 1707 } 1708 1709 /** 1710 * e1000e_disable_pcie_master - Disables PCI-express master access 1711 * @hw: pointer to the HW structure 1712 * 1713 * Returns 0 if successful, else returns -10 1714 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1715 * the master requests to be disabled. 1716 * 1717 * Disables PCI-Express master access and verifies there are no pending 1718 * requests. 1719 **/ 1720 s32 e1000e_disable_pcie_master(struct e1000_hw *hw) 1721 { 1722 u32 ctrl; 1723 s32 timeout = MASTER_DISABLE_TIMEOUT; 1724 1725 ctrl = er32(CTRL); 1726 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1727 ew32(CTRL, ctrl); 1728 1729 while (timeout) { 1730 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 1731 break; 1732 usleep_range(100, 200); 1733 timeout--; 1734 } 1735 1736 if (!timeout) { 1737 e_dbg("Master requests are pending.\n"); 1738 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1739 } 1740 1741 return 0; 1742 } 1743 1744 /** 1745 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing 1746 * @hw: pointer to the HW structure 1747 * 1748 * Reset the Adaptive Interframe Spacing throttle to default values. 1749 **/ 1750 void e1000e_reset_adaptive(struct e1000_hw *hw) 1751 { 1752 struct e1000_mac_info *mac = &hw->mac; 1753 1754 if (!mac->adaptive_ifs) { 1755 e_dbg("Not in Adaptive IFS mode!\n"); 1756 return; 1757 } 1758 1759 mac->current_ifs_val = 0; 1760 mac->ifs_min_val = IFS_MIN; 1761 mac->ifs_max_val = IFS_MAX; 1762 mac->ifs_step_size = IFS_STEP; 1763 mac->ifs_ratio = IFS_RATIO; 1764 1765 mac->in_ifs_mode = false; 1766 ew32(AIT, 0); 1767 } 1768 1769 /** 1770 * e1000e_update_adaptive - Update Adaptive Interframe Spacing 1771 * @hw: pointer to the HW structure 1772 * 1773 * Update the Adaptive Interframe Spacing Throttle value based on the 1774 * time between transmitted packets and time between collisions. 1775 **/ 1776 void e1000e_update_adaptive(struct e1000_hw *hw) 1777 { 1778 struct e1000_mac_info *mac = &hw->mac; 1779 1780 if (!mac->adaptive_ifs) { 1781 e_dbg("Not in Adaptive IFS mode!\n"); 1782 return; 1783 } 1784 1785 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1786 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1787 mac->in_ifs_mode = true; 1788 if (mac->current_ifs_val < mac->ifs_max_val) { 1789 if (!mac->current_ifs_val) 1790 mac->current_ifs_val = mac->ifs_min_val; 1791 else 1792 mac->current_ifs_val += 1793 mac->ifs_step_size; 1794 ew32(AIT, mac->current_ifs_val); 1795 } 1796 } 1797 } else { 1798 if (mac->in_ifs_mode && 1799 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1800 mac->current_ifs_val = 0; 1801 mac->in_ifs_mode = false; 1802 ew32(AIT, 0); 1803 } 1804 } 1805 } 1806