1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _E1000E_ICH8LAN_H_ 30 #define _E1000E_ICH8LAN_H_ 31 32 #define ICH_FLASH_GFPREG 0x0000 33 #define ICH_FLASH_HSFSTS 0x0004 34 #define ICH_FLASH_HSFCTL 0x0006 35 #define ICH_FLASH_FADDR 0x0008 36 #define ICH_FLASH_FDATA0 0x0010 37 #define ICH_FLASH_PR0 0x0074 38 39 /* Requires up to 10 seconds when MNG might be accessing part. */ 40 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 41 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 42 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 43 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 44 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 45 46 #define ICH_CYCLE_READ 0 47 #define ICH_CYCLE_WRITE 2 48 #define ICH_CYCLE_ERASE 3 49 50 #define FLASH_GFPREG_BASE_MASK 0x1FFF 51 #define FLASH_SECTOR_ADDR_SHIFT 12 52 53 #define ICH_FLASH_SEG_SIZE_256 256 54 #define ICH_FLASH_SEG_SIZE_4K 4096 55 #define ICH_FLASH_SEG_SIZE_8K 8192 56 #define ICH_FLASH_SEG_SIZE_64K 65536 57 58 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 59 /* FW established a valid mode */ 60 #define E1000_ICH_FWSM_FW_VALID 0x00008000 61 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 62 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 63 64 #define E1000_ICH_MNG_IAMT_MODE 0x2 65 66 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 67 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 68 69 /* Shared Receive Address Registers */ 70 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 71 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 72 73 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 74 (ID_LED_OFF1_OFF2 << 8) | \ 75 (ID_LED_OFF1_ON2 << 4) | \ 76 (ID_LED_DEF1_DEF2)) 77 78 #define E1000_ICH_NVM_SIG_WORD 0x13 79 #define E1000_ICH_NVM_SIG_MASK 0xC000 80 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 81 #define E1000_ICH_NVM_SIG_VALUE 0x80 82 83 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 84 85 #define E1000_FEXTNVM_SW_CONFIG 1 86 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 87 88 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 89 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 90 91 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 92 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 93 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 94 95 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 96 97 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 98 99 #define E1000_ICH_RAR_ENTRIES 7 100 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 101 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 102 103 #define PHY_PAGE_SHIFT 5 104 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 105 ((reg) & MAX_PHY_REG_ADDRESS)) 106 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 107 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 108 109 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 110 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 111 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 112 113 /* PHY Wakeup Registers and defines */ 114 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 115 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 116 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 117 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 118 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 119 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 120 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 121 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 122 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 123 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 124 125 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 126 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 127 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 128 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 129 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 130 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 131 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 132 133 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 134 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 135 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 136 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 137 #define HV_STATS_PAGE 778 138 /* Half-duplex collision counts */ 139 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 140 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 141 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 142 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 143 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 144 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 145 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 146 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 147 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 148 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 149 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 150 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 151 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 152 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 153 154 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 155 156 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 157 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 158 159 /* SMBus Control Phy Register */ 160 #define CV_SMB_CTRL PHY_REG(769, 23) 161 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 162 163 /* SMBus Address Phy Register */ 164 #define HV_SMB_ADDR PHY_REG(768, 26) 165 #define HV_SMB_ADDR_MASK 0x007F 166 #define HV_SMB_ADDR_PEC_EN 0x0200 167 #define HV_SMB_ADDR_VALID 0x0080 168 #define HV_SMB_ADDR_FREQ_MASK 0x1100 169 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 170 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 171 172 /* Strapping Option Register - RO */ 173 #define E1000_STRAP 0x0000C 174 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 175 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 176 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 177 #define E1000_STRAP_SMT_FREQ_SHIFT 12 178 179 /* OEM Bits Phy Register */ 180 #define HV_OEM_BITS PHY_REG(768, 25) 181 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 182 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 183 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 184 185 /* KMRN Mode Control */ 186 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 187 #define HV_KMRN_MDIO_SLOW 0x0400 188 189 /* KMRN FIFO Control and Status */ 190 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 191 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 192 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 193 194 /* PHY Power Management Control */ 195 #define HV_PM_CTRL PHY_REG(770, 17) 196 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 197 198 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 199 200 /* PHY Low Power Idle Control */ 201 #define I82579_LPI_CTRL PHY_REG(772, 20) 202 #define I82579_LPI_CTRL_100_ENABLE 0x2000 203 #define I82579_LPI_CTRL_1000_ENABLE 0x4000 204 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 205 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 206 207 /* Extended Management Interface (EMI) Registers */ 208 #define I82579_EMI_ADDR 0x10 209 #define I82579_EMI_DATA 0x11 210 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 211 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 212 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 213 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 214 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 215 #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 216 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 217 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 218 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 219 #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 220 #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 221 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 222 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 223 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 224 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 225 226 #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 227 #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 228 229 /* Intel Rapid Start Technology Support */ 230 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 231 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 232 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 233 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 234 #define I217_CGFREG PHY_REG(772, 29) 235 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 236 #define I217_MEMPWR PHY_REG(772, 26) 237 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 238 239 /* Receive Address Initial CRC Calculation */ 240 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 241 242 /* Latency Tolerance Reporting */ 243 #define E1000_LTRV 0x000F8 244 #define E1000_LTRV_SCALE_MAX 5 245 #define E1000_LTRV_SCALE_FACTOR 5 246 #define E1000_LTRV_REQ_SHIFT 15 247 #define E1000_LTRV_NOSNOOP_SHIFT 16 248 #define E1000_LTRV_SEND (1 << 30) 249 250 /* Proprietary Latency Tolerance Reporting PCI Capability */ 251 #define E1000_PCI_LTR_CAP_LPT 0xA8 252 253 /* OBFF Control & Threshold Defines */ 254 #define E1000_SVCR_OFF_EN 0x00000001 255 #define E1000_SVCR_OFF_MASKINT 0x00001000 256 #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 257 #define E1000_SVCR_OFF_TIMER_SHIFT 16 258 #define E1000_SVT_OFF_HWM_MASK 0x0000001F 259 260 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); 261 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 262 bool state); 263 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 264 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 265 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 266 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 267 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 268 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 269 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 270 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 271 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 272 #endif /* _E1000E_ICH8LAN_H_ */ 273