1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* 82562G 10/100 Network Connection 30 * 82562G-2 10/100 Network Connection 31 * 82562GT 10/100 Network Connection 32 * 82562GT-2 10/100 Network Connection 33 * 82562V 10/100 Network Connection 34 * 82562V-2 10/100 Network Connection 35 * 82566DC-2 Gigabit Network Connection 36 * 82566DC Gigabit Network Connection 37 * 82566DM-2 Gigabit Network Connection 38 * 82566DM Gigabit Network Connection 39 * 82566MC Gigabit Network Connection 40 * 82566MM Gigabit Network Connection 41 * 82567LM Gigabit Network Connection 42 * 82567LF Gigabit Network Connection 43 * 82567V Gigabit Network Connection 44 * 82567LM-2 Gigabit Network Connection 45 * 82567LF-2 Gigabit Network Connection 46 * 82567V-2 Gigabit Network Connection 47 * 82567LF-3 Gigabit Network Connection 48 * 82567LM-3 Gigabit Network Connection 49 * 82567LM-4 Gigabit Network Connection 50 * 82577LM Gigabit Network Connection 51 * 82577LC Gigabit Network Connection 52 * 82578DM Gigabit Network Connection 53 * 82578DC Gigabit Network Connection 54 * 82579LM Gigabit Network Connection 55 * 82579V Gigabit Network Connection 56 */ 57 58 #include "e1000.h" 59 60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 61 /* Offset 04h HSFSTS */ 62 union ich8_hws_flash_status { 63 struct ich8_hsfsts { 64 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 65 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 66 u16 dael:1; /* bit 2 Direct Access error Log */ 67 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 68 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 69 u16 reserved1:2; /* bit 13:6 Reserved */ 70 u16 reserved2:6; /* bit 13:6 Reserved */ 71 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 72 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 73 } hsf_status; 74 u16 regval; 75 }; 76 77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 78 /* Offset 06h FLCTL */ 79 union ich8_hws_flash_ctrl { 80 struct ich8_hsflctl { 81 u16 flcgo:1; /* 0 Flash Cycle Go */ 82 u16 flcycle:2; /* 2:1 Flash Cycle */ 83 u16 reserved:5; /* 7:3 Reserved */ 84 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 85 u16 flockdn:6; /* 15:10 Reserved */ 86 } hsf_ctrl; 87 u16 regval; 88 }; 89 90 /* ICH Flash Region Access Permissions */ 91 union ich8_hws_flash_regacc { 92 struct ich8_flracc { 93 u32 grra:8; /* 0:7 GbE region Read Access */ 94 u32 grwa:8; /* 8:15 GbE region Write Access */ 95 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 96 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 97 } hsf_flregacc; 98 u16 regval; 99 }; 100 101 /* ICH Flash Protected Region */ 102 union ich8_flash_protected_range { 103 struct ich8_pr { 104 u32 base:13; /* 0:12 Protected Range Base */ 105 u32 reserved1:2; /* 13:14 Reserved */ 106 u32 rpe:1; /* 15 Read Protection Enable */ 107 u32 limit:13; /* 16:28 Protected Range Limit */ 108 u32 reserved2:2; /* 29:30 Reserved */ 109 u32 wpe:1; /* 31 Write Protection Enable */ 110 } range; 111 u32 regval; 112 }; 113 114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 118 u32 offset, u8 byte); 119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 120 u8 *data); 121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 122 u16 *data); 123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 124 u8 size, u16 *data); 125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 145 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 146 147 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 148 { 149 return readw(hw->flash_address + reg); 150 } 151 152 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 153 { 154 return readl(hw->flash_address + reg); 155 } 156 157 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 158 { 159 writew(val, hw->flash_address + reg); 160 } 161 162 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 163 { 164 writel(val, hw->flash_address + reg); 165 } 166 167 #define er16flash(reg) __er16flash(hw, (reg)) 168 #define er32flash(reg) __er32flash(hw, (reg)) 169 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 170 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 171 172 /** 173 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 174 * @hw: pointer to the HW structure 175 * 176 * Test access to the PHY registers by reading the PHY ID registers. If 177 * the PHY ID is already known (e.g. resume path) compare it with known ID, 178 * otherwise assume the read PHY ID is correct if it is valid. 179 * 180 * Assumes the sw/fw/hw semaphore is already acquired. 181 **/ 182 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 183 { 184 u16 phy_reg = 0; 185 u32 phy_id = 0; 186 s32 ret_val; 187 u16 retry_count; 188 189 for (retry_count = 0; retry_count < 2; retry_count++) { 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) 192 continue; 193 phy_id = (u32)(phy_reg << 16); 194 195 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 196 if (ret_val || (phy_reg == 0xFFFF)) { 197 phy_id = 0; 198 continue; 199 } 200 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 201 break; 202 } 203 204 if (hw->phy.id) { 205 if (hw->phy.id == phy_id) 206 return true; 207 } else if (phy_id) { 208 hw->phy.id = phy_id; 209 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 210 return true; 211 } 212 213 /* In case the PHY needs to be in mdio slow mode, 214 * set slow mode and try to get the PHY id again. 215 */ 216 hw->phy.ops.release(hw); 217 ret_val = e1000_set_mdio_slow_mode_hv(hw); 218 if (!ret_val) 219 ret_val = e1000e_get_phy_id(hw); 220 hw->phy.ops.acquire(hw); 221 222 return !ret_val; 223 } 224 225 /** 226 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 227 * @hw: pointer to the HW structure 228 * 229 * Workarounds/flow necessary for PHY initialization during driver load 230 * and resume paths. 231 **/ 232 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 233 { 234 u32 mac_reg, fwsm = er32(FWSM); 235 s32 ret_val; 236 u16 phy_reg; 237 238 /* Gate automatic PHY configuration by hardware on managed and 239 * non-managed 82579 and newer adapters. 240 */ 241 e1000_gate_hw_phy_config_ich8lan(hw, true); 242 243 ret_val = hw->phy.ops.acquire(hw); 244 if (ret_val) { 245 e_dbg("Failed to initialize PHY flow\n"); 246 goto out; 247 } 248 249 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 250 * inaccessible and resetting the PHY is not blocked, toggle the 251 * LANPHYPC Value bit to force the interconnect to PCIe mode. 252 */ 253 switch (hw->mac.type) { 254 case e1000_pch_lpt: 255 if (e1000_phy_is_accessible_pchlan(hw)) 256 break; 257 258 /* Before toggling LANPHYPC, see if PHY is accessible by 259 * forcing MAC to SMBus mode first. 260 */ 261 mac_reg = er32(CTRL_EXT); 262 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 263 ew32(CTRL_EXT, mac_reg); 264 265 /* fall-through */ 266 case e1000_pch2lan: 267 if (e1000_phy_is_accessible_pchlan(hw)) { 268 if (hw->mac.type == e1000_pch_lpt) { 269 /* Unforce SMBus mode in PHY */ 270 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 271 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 272 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 273 274 /* Unforce SMBus mode in MAC */ 275 mac_reg = er32(CTRL_EXT); 276 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 277 ew32(CTRL_EXT, mac_reg); 278 } 279 break; 280 } 281 282 /* fall-through */ 283 case e1000_pchlan: 284 if ((hw->mac.type == e1000_pchlan) && 285 (fwsm & E1000_ICH_FWSM_FW_VALID)) 286 break; 287 288 if (hw->phy.ops.check_reset_block(hw)) { 289 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 290 break; 291 } 292 293 e_dbg("Toggling LANPHYPC\n"); 294 295 /* Set Phy Config Counter to 50msec */ 296 mac_reg = er32(FEXTNVM3); 297 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 298 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 299 ew32(FEXTNVM3, mac_reg); 300 301 if (hw->mac.type == e1000_pch_lpt) { 302 /* Toggling LANPHYPC brings the PHY out of SMBus mode 303 * So ensure that the MAC is also out of SMBus mode 304 */ 305 mac_reg = er32(CTRL_EXT); 306 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 307 ew32(CTRL_EXT, mac_reg); 308 } 309 310 /* Toggle LANPHYPC Value bit */ 311 mac_reg = er32(CTRL); 312 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 313 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 314 ew32(CTRL, mac_reg); 315 e1e_flush(); 316 usleep_range(10, 20); 317 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 318 ew32(CTRL, mac_reg); 319 e1e_flush(); 320 if (hw->mac.type < e1000_pch_lpt) { 321 msleep(50); 322 } else { 323 u16 count = 20; 324 do { 325 usleep_range(5000, 10000); 326 } while (!(er32(CTRL_EXT) & 327 E1000_CTRL_EXT_LPCD) && count--); 328 } 329 break; 330 default: 331 break; 332 } 333 334 hw->phy.ops.release(hw); 335 336 /* Reset the PHY before any access to it. Doing so, ensures 337 * that the PHY is in a known good state before we read/write 338 * PHY registers. The generic reset is sufficient here, 339 * because we haven't determined the PHY type yet. 340 */ 341 ret_val = e1000e_phy_hw_reset_generic(hw); 342 343 out: 344 /* Ungate automatic PHY configuration on non-managed 82579 */ 345 if ((hw->mac.type == e1000_pch2lan) && 346 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 347 usleep_range(10000, 20000); 348 e1000_gate_hw_phy_config_ich8lan(hw, false); 349 } 350 351 return ret_val; 352 } 353 354 /** 355 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 356 * @hw: pointer to the HW structure 357 * 358 * Initialize family-specific PHY parameters and function pointers. 359 **/ 360 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 361 { 362 struct e1000_phy_info *phy = &hw->phy; 363 s32 ret_val; 364 365 phy->addr = 1; 366 phy->reset_delay_us = 100; 367 368 phy->ops.set_page = e1000_set_page_igp; 369 phy->ops.read_reg = e1000_read_phy_reg_hv; 370 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 371 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 372 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 373 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 374 phy->ops.write_reg = e1000_write_phy_reg_hv; 375 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 376 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 377 phy->ops.power_up = e1000_power_up_phy_copper; 378 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 379 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 380 381 phy->id = e1000_phy_unknown; 382 383 ret_val = e1000_init_phy_workarounds_pchlan(hw); 384 if (ret_val) 385 return ret_val; 386 387 if (phy->id == e1000_phy_unknown) 388 switch (hw->mac.type) { 389 default: 390 ret_val = e1000e_get_phy_id(hw); 391 if (ret_val) 392 return ret_val; 393 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 394 break; 395 /* fall-through */ 396 case e1000_pch2lan: 397 case e1000_pch_lpt: 398 /* In case the PHY needs to be in mdio slow mode, 399 * set slow mode and try to get the PHY id again. 400 */ 401 ret_val = e1000_set_mdio_slow_mode_hv(hw); 402 if (ret_val) 403 return ret_val; 404 ret_val = e1000e_get_phy_id(hw); 405 if (ret_val) 406 return ret_val; 407 break; 408 } 409 phy->type = e1000e_get_phy_type_from_id(phy->id); 410 411 switch (phy->type) { 412 case e1000_phy_82577: 413 case e1000_phy_82579: 414 case e1000_phy_i217: 415 phy->ops.check_polarity = e1000_check_polarity_82577; 416 phy->ops.force_speed_duplex = 417 e1000_phy_force_speed_duplex_82577; 418 phy->ops.get_cable_length = e1000_get_cable_length_82577; 419 phy->ops.get_info = e1000_get_phy_info_82577; 420 phy->ops.commit = e1000e_phy_sw_reset; 421 break; 422 case e1000_phy_82578: 423 phy->ops.check_polarity = e1000_check_polarity_m88; 424 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 425 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 426 phy->ops.get_info = e1000e_get_phy_info_m88; 427 break; 428 default: 429 ret_val = -E1000_ERR_PHY; 430 break; 431 } 432 433 return ret_val; 434 } 435 436 /** 437 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 438 * @hw: pointer to the HW structure 439 * 440 * Initialize family-specific PHY parameters and function pointers. 441 **/ 442 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 443 { 444 struct e1000_phy_info *phy = &hw->phy; 445 s32 ret_val; 446 u16 i = 0; 447 448 phy->addr = 1; 449 phy->reset_delay_us = 100; 450 451 phy->ops.power_up = e1000_power_up_phy_copper; 452 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 453 454 /* We may need to do this twice - once for IGP and if that fails, 455 * we'll set BM func pointers and try again 456 */ 457 ret_val = e1000e_determine_phy_address(hw); 458 if (ret_val) { 459 phy->ops.write_reg = e1000e_write_phy_reg_bm; 460 phy->ops.read_reg = e1000e_read_phy_reg_bm; 461 ret_val = e1000e_determine_phy_address(hw); 462 if (ret_val) { 463 e_dbg("Cannot determine PHY addr. Erroring out\n"); 464 return ret_val; 465 } 466 } 467 468 phy->id = 0; 469 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 470 (i++ < 100)) { 471 usleep_range(1000, 2000); 472 ret_val = e1000e_get_phy_id(hw); 473 if (ret_val) 474 return ret_val; 475 } 476 477 /* Verify phy id */ 478 switch (phy->id) { 479 case IGP03E1000_E_PHY_ID: 480 phy->type = e1000_phy_igp_3; 481 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 482 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 483 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 484 phy->ops.get_info = e1000e_get_phy_info_igp; 485 phy->ops.check_polarity = e1000_check_polarity_igp; 486 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 487 break; 488 case IFE_E_PHY_ID: 489 case IFE_PLUS_E_PHY_ID: 490 case IFE_C_E_PHY_ID: 491 phy->type = e1000_phy_ife; 492 phy->autoneg_mask = E1000_ALL_NOT_GIG; 493 phy->ops.get_info = e1000_get_phy_info_ife; 494 phy->ops.check_polarity = e1000_check_polarity_ife; 495 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 496 break; 497 case BME1000_E_PHY_ID: 498 phy->type = e1000_phy_bm; 499 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 500 phy->ops.read_reg = e1000e_read_phy_reg_bm; 501 phy->ops.write_reg = e1000e_write_phy_reg_bm; 502 phy->ops.commit = e1000e_phy_sw_reset; 503 phy->ops.get_info = e1000e_get_phy_info_m88; 504 phy->ops.check_polarity = e1000_check_polarity_m88; 505 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 506 break; 507 default: 508 return -E1000_ERR_PHY; 509 break; 510 } 511 512 return 0; 513 } 514 515 /** 516 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 517 * @hw: pointer to the HW structure 518 * 519 * Initialize family-specific NVM parameters and function 520 * pointers. 521 **/ 522 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 523 { 524 struct e1000_nvm_info *nvm = &hw->nvm; 525 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 526 u32 gfpreg, sector_base_addr, sector_end_addr; 527 u16 i; 528 529 /* Can't read flash registers if the register set isn't mapped. */ 530 if (!hw->flash_address) { 531 e_dbg("ERROR: Flash registers not mapped\n"); 532 return -E1000_ERR_CONFIG; 533 } 534 535 nvm->type = e1000_nvm_flash_sw; 536 537 gfpreg = er32flash(ICH_FLASH_GFPREG); 538 539 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 540 * Add 1 to sector_end_addr since this sector is included in 541 * the overall size. 542 */ 543 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 544 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 545 546 /* flash_base_addr is byte-aligned */ 547 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 548 549 /* find total size of the NVM, then cut in half since the total 550 * size represents two separate NVM banks. 551 */ 552 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 553 << FLASH_SECTOR_ADDR_SHIFT); 554 nvm->flash_bank_size /= 2; 555 /* Adjust to word count */ 556 nvm->flash_bank_size /= sizeof(u16); 557 558 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 559 560 /* Clear shadow ram */ 561 for (i = 0; i < nvm->word_size; i++) { 562 dev_spec->shadow_ram[i].modified = false; 563 dev_spec->shadow_ram[i].value = 0xFFFF; 564 } 565 566 return 0; 567 } 568 569 /** 570 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 571 * @hw: pointer to the HW structure 572 * 573 * Initialize family-specific MAC parameters and function 574 * pointers. 575 **/ 576 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 577 { 578 struct e1000_mac_info *mac = &hw->mac; 579 580 /* Set media type function pointer */ 581 hw->phy.media_type = e1000_media_type_copper; 582 583 /* Set mta register count */ 584 mac->mta_reg_count = 32; 585 /* Set rar entry count */ 586 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 587 if (mac->type == e1000_ich8lan) 588 mac->rar_entry_count--; 589 /* FWSM register */ 590 mac->has_fwsm = true; 591 /* ARC subsystem not supported */ 592 mac->arc_subsystem_valid = false; 593 /* Adaptive IFS supported */ 594 mac->adaptive_ifs = true; 595 596 /* LED and other operations */ 597 switch (mac->type) { 598 case e1000_ich8lan: 599 case e1000_ich9lan: 600 case e1000_ich10lan: 601 /* check management mode */ 602 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 603 /* ID LED init */ 604 mac->ops.id_led_init = e1000e_id_led_init_generic; 605 /* blink LED */ 606 mac->ops.blink_led = e1000e_blink_led_generic; 607 /* setup LED */ 608 mac->ops.setup_led = e1000e_setup_led_generic; 609 /* cleanup LED */ 610 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 611 /* turn on/off LED */ 612 mac->ops.led_on = e1000_led_on_ich8lan; 613 mac->ops.led_off = e1000_led_off_ich8lan; 614 break; 615 case e1000_pch2lan: 616 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 617 mac->ops.rar_set = e1000_rar_set_pch2lan; 618 /* fall-through */ 619 case e1000_pch_lpt: 620 case e1000_pchlan: 621 /* check management mode */ 622 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 623 /* ID LED init */ 624 mac->ops.id_led_init = e1000_id_led_init_pchlan; 625 /* setup LED */ 626 mac->ops.setup_led = e1000_setup_led_pchlan; 627 /* cleanup LED */ 628 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 629 /* turn on/off LED */ 630 mac->ops.led_on = e1000_led_on_pchlan; 631 mac->ops.led_off = e1000_led_off_pchlan; 632 break; 633 default: 634 break; 635 } 636 637 if (mac->type == e1000_pch_lpt) { 638 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 639 mac->ops.rar_set = e1000_rar_set_pch_lpt; 640 mac->ops.setup_physical_interface = 641 e1000_setup_copper_link_pch_lpt; 642 } 643 644 /* Enable PCS Lock-loss workaround for ICH8 */ 645 if (mac->type == e1000_ich8lan) 646 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 647 648 return 0; 649 } 650 651 /** 652 * __e1000_access_emi_reg_locked - Read/write EMI register 653 * @hw: pointer to the HW structure 654 * @addr: EMI address to program 655 * @data: pointer to value to read/write from/to the EMI address 656 * @read: boolean flag to indicate read or write 657 * 658 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 659 **/ 660 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 661 u16 *data, bool read) 662 { 663 s32 ret_val; 664 665 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 666 if (ret_val) 667 return ret_val; 668 669 if (read) 670 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 671 else 672 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 673 674 return ret_val; 675 } 676 677 /** 678 * e1000_read_emi_reg_locked - Read Extended Management Interface register 679 * @hw: pointer to the HW structure 680 * @addr: EMI address to program 681 * @data: value to be read from the EMI address 682 * 683 * Assumes the SW/FW/HW Semaphore is already acquired. 684 **/ 685 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 686 { 687 return __e1000_access_emi_reg_locked(hw, addr, data, true); 688 } 689 690 /** 691 * e1000_write_emi_reg_locked - Write Extended Management Interface register 692 * @hw: pointer to the HW structure 693 * @addr: EMI address to program 694 * @data: value to be written to the EMI address 695 * 696 * Assumes the SW/FW/HW Semaphore is already acquired. 697 **/ 698 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 699 { 700 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 701 } 702 703 /** 704 * e1000_set_eee_pchlan - Enable/disable EEE support 705 * @hw: pointer to the HW structure 706 * 707 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 708 * the link and the EEE capabilities of the link partner. The LPI Control 709 * register bits will remain set only if/when link is up. 710 **/ 711 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 712 { 713 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 714 s32 ret_val; 715 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 716 717 switch (hw->phy.type) { 718 case e1000_phy_82579: 719 lpa = I82579_EEE_LP_ABILITY; 720 pcs_status = I82579_EEE_PCS_STATUS; 721 adv_addr = I82579_EEE_ADVERTISEMENT; 722 break; 723 case e1000_phy_i217: 724 lpa = I217_EEE_LP_ABILITY; 725 pcs_status = I217_EEE_PCS_STATUS; 726 adv_addr = I217_EEE_ADVERTISEMENT; 727 break; 728 default: 729 return 0; 730 } 731 732 ret_val = hw->phy.ops.acquire(hw); 733 if (ret_val) 734 return ret_val; 735 736 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 737 if (ret_val) 738 goto release; 739 740 /* Clear bits that enable EEE in various speeds */ 741 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 742 743 /* Enable EEE if not disabled by user */ 744 if (!dev_spec->eee_disable) { 745 /* Save off link partner's EEE ability */ 746 ret_val = e1000_read_emi_reg_locked(hw, lpa, 747 &dev_spec->eee_lp_ability); 748 if (ret_val) 749 goto release; 750 751 /* Read EEE advertisement */ 752 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 753 if (ret_val) 754 goto release; 755 756 /* Enable EEE only for speeds in which the link partner is 757 * EEE capable and for which we advertise EEE. 758 */ 759 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 760 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 761 762 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 763 e1e_rphy_locked(hw, MII_LPA, &data); 764 if (data & LPA_100FULL) 765 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 766 else 767 /* EEE is not supported in 100Half, so ignore 768 * partner's EEE in 100 ability if full-duplex 769 * is not advertised. 770 */ 771 dev_spec->eee_lp_ability &= 772 ~I82579_EEE_100_SUPPORTED; 773 } 774 } 775 776 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 777 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 778 if (ret_val) 779 goto release; 780 781 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 782 release: 783 hw->phy.ops.release(hw); 784 785 return ret_val; 786 } 787 788 /** 789 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 790 * @hw: pointer to the HW structure 791 * @link: link up bool flag 792 * 793 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 794 * preventing further DMA write requests. Workaround the issue by disabling 795 * the de-assertion of the clock request when in 1Gpbs mode. 796 **/ 797 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 798 { 799 u32 fextnvm6 = er32(FEXTNVM6); 800 s32 ret_val = 0; 801 802 if (link && (er32(STATUS) & E1000_STATUS_SPEED_1000)) { 803 u16 kmrn_reg; 804 805 ret_val = hw->phy.ops.acquire(hw); 806 if (ret_val) 807 return ret_val; 808 809 ret_val = 810 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 811 &kmrn_reg); 812 if (ret_val) 813 goto release; 814 815 ret_val = 816 e1000e_write_kmrn_reg_locked(hw, 817 E1000_KMRNCTRLSTA_K1_CONFIG, 818 kmrn_reg & 819 ~E1000_KMRNCTRLSTA_K1_ENABLE); 820 if (ret_val) 821 goto release; 822 823 usleep_range(10, 20); 824 825 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 826 827 ret_val = 828 e1000e_write_kmrn_reg_locked(hw, 829 E1000_KMRNCTRLSTA_K1_CONFIG, 830 kmrn_reg); 831 release: 832 hw->phy.ops.release(hw); 833 } else { 834 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 835 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 836 } 837 838 return ret_val; 839 } 840 841 /** 842 * e1000_platform_pm_pch_lpt - Set platform power management values 843 * @hw: pointer to the HW structure 844 * @link: bool indicating link status 845 * 846 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 847 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 848 * when link is up (which must not exceed the maximum latency supported 849 * by the platform), otherwise specify there is no LTR requirement. 850 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 851 * latencies in the LTR Extended Capability Structure in the PCIe Extended 852 * Capability register set, on this device LTR is set by writing the 853 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 854 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 855 * message to the PMC. 856 **/ 857 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 858 { 859 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 860 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 861 u16 lat_enc = 0; /* latency encoded */ 862 863 if (link) { 864 u16 speed, duplex, scale = 0; 865 u16 max_snoop, max_nosnoop; 866 u16 max_ltr_enc; /* max LTR latency encoded */ 867 s64 lat_ns; /* latency (ns) */ 868 s64 value; 869 u32 rxa; 870 871 if (!hw->adapter->max_frame_size) { 872 e_dbg("max_frame_size not set.\n"); 873 return -E1000_ERR_CONFIG; 874 } 875 876 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 877 if (!speed) { 878 e_dbg("Speed not set.\n"); 879 return -E1000_ERR_CONFIG; 880 } 881 882 /* Rx Packet Buffer Allocation size (KB) */ 883 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 884 885 /* Determine the maximum latency tolerated by the device. 886 * 887 * Per the PCIe spec, the tolerated latencies are encoded as 888 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 889 * a 10-bit value (0-1023) to provide a range from 1 ns to 890 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 891 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 892 */ 893 lat_ns = ((s64)rxa * 1024 - 894 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000; 895 if (lat_ns < 0) 896 lat_ns = 0; 897 else 898 do_div(lat_ns, speed); 899 900 value = lat_ns; 901 while (value > PCI_LTR_VALUE_MASK) { 902 scale++; 903 value = DIV_ROUND_UP(value, (1 << 5)); 904 } 905 if (scale > E1000_LTRV_SCALE_MAX) { 906 e_dbg("Invalid LTR latency scale %d\n", scale); 907 return -E1000_ERR_CONFIG; 908 } 909 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 910 911 /* Determine the maximum latency tolerated by the platform */ 912 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 913 &max_snoop); 914 pci_read_config_word(hw->adapter->pdev, 915 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 916 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 917 918 if (lat_enc > max_ltr_enc) 919 lat_enc = max_ltr_enc; 920 } 921 922 /* Set Snoop and No-Snoop latencies the same */ 923 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 924 ew32(LTRV, reg); 925 926 return 0; 927 } 928 929 /** 930 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 931 * @hw: pointer to the HW structure 932 * 933 * Checks to see of the link status of the hardware has changed. If a 934 * change in link status has been detected, then we read the PHY registers 935 * to get the current speed/duplex if link exists. 936 **/ 937 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 938 { 939 struct e1000_mac_info *mac = &hw->mac; 940 s32 ret_val; 941 bool link; 942 u16 phy_reg; 943 944 /* We only want to go out to the PHY registers to see if Auto-Neg 945 * has completed and/or if our link status has changed. The 946 * get_link_status flag is set upon receiving a Link Status 947 * Change or Rx Sequence Error interrupt. 948 */ 949 if (!mac->get_link_status) 950 return 0; 951 952 /* First we want to see if the MII Status Register reports 953 * link. If so, then we want to get the current speed/duplex 954 * of the PHY. 955 */ 956 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 957 if (ret_val) 958 return ret_val; 959 960 if (hw->mac.type == e1000_pchlan) { 961 ret_val = e1000_k1_gig_workaround_hv(hw, link); 962 if (ret_val) 963 return ret_val; 964 } 965 966 /* When connected at 10Mbps half-duplex, 82579 parts are excessively 967 * aggressive resulting in many collisions. To avoid this, increase 968 * the IPG and reduce Rx latency in the PHY. 969 */ 970 if ((hw->mac.type == e1000_pch2lan) && link) { 971 u32 reg; 972 reg = er32(STATUS); 973 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) { 974 reg = er32(TIPG); 975 reg &= ~E1000_TIPG_IPGT_MASK; 976 reg |= 0xFF; 977 ew32(TIPG, reg); 978 979 /* Reduce Rx latency in analog PHY */ 980 ret_val = hw->phy.ops.acquire(hw); 981 if (ret_val) 982 return ret_val; 983 984 ret_val = 985 e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0); 986 987 hw->phy.ops.release(hw); 988 989 if (ret_val) 990 return ret_val; 991 } 992 } 993 994 /* Work-around I218 hang issue */ 995 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 996 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V)) { 997 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 998 if (ret_val) 999 return ret_val; 1000 } 1001 1002 if (hw->mac.type == e1000_pch_lpt) { 1003 /* Set platform power management values for 1004 * Latency Tolerance Reporting (LTR) 1005 */ 1006 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1007 if (ret_val) 1008 return ret_val; 1009 } 1010 1011 /* Clear link partner's EEE ability */ 1012 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1013 1014 if (!link) 1015 return 0; /* No link detected */ 1016 1017 mac->get_link_status = false; 1018 1019 switch (hw->mac.type) { 1020 case e1000_pch2lan: 1021 ret_val = e1000_k1_workaround_lv(hw); 1022 if (ret_val) 1023 return ret_val; 1024 /* fall-thru */ 1025 case e1000_pchlan: 1026 if (hw->phy.type == e1000_phy_82578) { 1027 ret_val = e1000_link_stall_workaround_hv(hw); 1028 if (ret_val) 1029 return ret_val; 1030 } 1031 1032 /* Workaround for PCHx parts in half-duplex: 1033 * Set the number of preambles removed from the packet 1034 * when it is passed from the PHY to the MAC to prevent 1035 * the MAC from misinterpreting the packet type. 1036 */ 1037 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1038 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1039 1040 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1041 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1042 1043 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1044 break; 1045 default: 1046 break; 1047 } 1048 1049 /* Check if there was DownShift, must be checked 1050 * immediately after link-up 1051 */ 1052 e1000e_check_downshift(hw); 1053 1054 /* Enable/Disable EEE after link up */ 1055 ret_val = e1000_set_eee_pchlan(hw); 1056 if (ret_val) 1057 return ret_val; 1058 1059 /* If we are forcing speed/duplex, then we simply return since 1060 * we have already determined whether we have link or not. 1061 */ 1062 if (!mac->autoneg) 1063 return -E1000_ERR_CONFIG; 1064 1065 /* Auto-Neg is enabled. Auto Speed Detection takes care 1066 * of MAC speed/duplex configuration. So we only need to 1067 * configure Collision Distance in the MAC. 1068 */ 1069 mac->ops.config_collision_dist(hw); 1070 1071 /* Configure Flow Control now that Auto-Neg has completed. 1072 * First, we need to restore the desired flow control 1073 * settings because we may have had to re-autoneg with a 1074 * different link partner. 1075 */ 1076 ret_val = e1000e_config_fc_after_link_up(hw); 1077 if (ret_val) 1078 e_dbg("Error configuring flow control\n"); 1079 1080 return ret_val; 1081 } 1082 1083 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1084 { 1085 struct e1000_hw *hw = &adapter->hw; 1086 s32 rc; 1087 1088 rc = e1000_init_mac_params_ich8lan(hw); 1089 if (rc) 1090 return rc; 1091 1092 rc = e1000_init_nvm_params_ich8lan(hw); 1093 if (rc) 1094 return rc; 1095 1096 switch (hw->mac.type) { 1097 case e1000_ich8lan: 1098 case e1000_ich9lan: 1099 case e1000_ich10lan: 1100 rc = e1000_init_phy_params_ich8lan(hw); 1101 break; 1102 case e1000_pchlan: 1103 case e1000_pch2lan: 1104 case e1000_pch_lpt: 1105 rc = e1000_init_phy_params_pchlan(hw); 1106 break; 1107 default: 1108 break; 1109 } 1110 if (rc) 1111 return rc; 1112 1113 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1114 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1115 */ 1116 if ((adapter->hw.phy.type == e1000_phy_ife) || 1117 ((adapter->hw.mac.type >= e1000_pch2lan) && 1118 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1119 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1120 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; 1121 1122 hw->mac.ops.blink_led = NULL; 1123 } 1124 1125 if ((adapter->hw.mac.type == e1000_ich8lan) && 1126 (adapter->hw.phy.type != e1000_phy_ife)) 1127 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1128 1129 /* Enable workaround for 82579 w/ ME enabled */ 1130 if ((adapter->hw.mac.type == e1000_pch2lan) && 1131 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1132 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1133 1134 return 0; 1135 } 1136 1137 static DEFINE_MUTEX(nvm_mutex); 1138 1139 /** 1140 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1141 * @hw: pointer to the HW structure 1142 * 1143 * Acquires the mutex for performing NVM operations. 1144 **/ 1145 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1146 { 1147 mutex_lock(&nvm_mutex); 1148 1149 return 0; 1150 } 1151 1152 /** 1153 * e1000_release_nvm_ich8lan - Release NVM mutex 1154 * @hw: pointer to the HW structure 1155 * 1156 * Releases the mutex used while performing NVM operations. 1157 **/ 1158 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1159 { 1160 mutex_unlock(&nvm_mutex); 1161 } 1162 1163 /** 1164 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1165 * @hw: pointer to the HW structure 1166 * 1167 * Acquires the software control flag for performing PHY and select 1168 * MAC CSR accesses. 1169 **/ 1170 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1171 { 1172 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1173 s32 ret_val = 0; 1174 1175 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1176 &hw->adapter->state)) { 1177 e_dbg("contention for Phy access\n"); 1178 return -E1000_ERR_PHY; 1179 } 1180 1181 while (timeout) { 1182 extcnf_ctrl = er32(EXTCNF_CTRL); 1183 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1184 break; 1185 1186 mdelay(1); 1187 timeout--; 1188 } 1189 1190 if (!timeout) { 1191 e_dbg("SW has already locked the resource.\n"); 1192 ret_val = -E1000_ERR_CONFIG; 1193 goto out; 1194 } 1195 1196 timeout = SW_FLAG_TIMEOUT; 1197 1198 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1199 ew32(EXTCNF_CTRL, extcnf_ctrl); 1200 1201 while (timeout) { 1202 extcnf_ctrl = er32(EXTCNF_CTRL); 1203 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1204 break; 1205 1206 mdelay(1); 1207 timeout--; 1208 } 1209 1210 if (!timeout) { 1211 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1212 er32(FWSM), extcnf_ctrl); 1213 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1214 ew32(EXTCNF_CTRL, extcnf_ctrl); 1215 ret_val = -E1000_ERR_CONFIG; 1216 goto out; 1217 } 1218 1219 out: 1220 if (ret_val) 1221 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1222 1223 return ret_val; 1224 } 1225 1226 /** 1227 * e1000_release_swflag_ich8lan - Release software control flag 1228 * @hw: pointer to the HW structure 1229 * 1230 * Releases the software control flag for performing PHY and select 1231 * MAC CSR accesses. 1232 **/ 1233 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1234 { 1235 u32 extcnf_ctrl; 1236 1237 extcnf_ctrl = er32(EXTCNF_CTRL); 1238 1239 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1240 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1241 ew32(EXTCNF_CTRL, extcnf_ctrl); 1242 } else { 1243 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1244 } 1245 1246 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1247 } 1248 1249 /** 1250 * e1000_check_mng_mode_ich8lan - Checks management mode 1251 * @hw: pointer to the HW structure 1252 * 1253 * This checks if the adapter has any manageability enabled. 1254 * This is a function pointer entry point only called by read/write 1255 * routines for the PHY and NVM parts. 1256 **/ 1257 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1258 { 1259 u32 fwsm; 1260 1261 fwsm = er32(FWSM); 1262 return ((fwsm & E1000_ICH_FWSM_FW_VALID) && 1263 ((fwsm & E1000_FWSM_MODE_MASK) == 1264 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))); 1265 } 1266 1267 /** 1268 * e1000_check_mng_mode_pchlan - Checks management mode 1269 * @hw: pointer to the HW structure 1270 * 1271 * This checks if the adapter has iAMT enabled. 1272 * This is a function pointer entry point only called by read/write 1273 * routines for the PHY and NVM parts. 1274 **/ 1275 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1276 { 1277 u32 fwsm; 1278 1279 fwsm = er32(FWSM); 1280 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1281 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1282 } 1283 1284 /** 1285 * e1000_rar_set_pch2lan - Set receive address register 1286 * @hw: pointer to the HW structure 1287 * @addr: pointer to the receive address 1288 * @index: receive address array register 1289 * 1290 * Sets the receive address array register at index to the address passed 1291 * in by addr. For 82579, RAR[0] is the base address register that is to 1292 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1293 * Use SHRA[0-3] in place of those reserved for ME. 1294 **/ 1295 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1296 { 1297 u32 rar_low, rar_high; 1298 1299 /* HW expects these in little endian so we reverse the byte order 1300 * from network order (big endian) to little endian 1301 */ 1302 rar_low = ((u32)addr[0] | 1303 ((u32)addr[1] << 8) | 1304 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1305 1306 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1307 1308 /* If MAC address zero, no need to set the AV bit */ 1309 if (rar_low || rar_high) 1310 rar_high |= E1000_RAH_AV; 1311 1312 if (index == 0) { 1313 ew32(RAL(index), rar_low); 1314 e1e_flush(); 1315 ew32(RAH(index), rar_high); 1316 e1e_flush(); 1317 return; 1318 } 1319 1320 if (index < hw->mac.rar_entry_count) { 1321 s32 ret_val; 1322 1323 ret_val = e1000_acquire_swflag_ich8lan(hw); 1324 if (ret_val) 1325 goto out; 1326 1327 ew32(SHRAL(index - 1), rar_low); 1328 e1e_flush(); 1329 ew32(SHRAH(index - 1), rar_high); 1330 e1e_flush(); 1331 1332 e1000_release_swflag_ich8lan(hw); 1333 1334 /* verify the register updates */ 1335 if ((er32(SHRAL(index - 1)) == rar_low) && 1336 (er32(SHRAH(index - 1)) == rar_high)) 1337 return; 1338 1339 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1340 (index - 1), er32(FWSM)); 1341 } 1342 1343 out: 1344 e_dbg("Failed to write receive address at index %d\n", index); 1345 } 1346 1347 /** 1348 * e1000_rar_set_pch_lpt - Set receive address registers 1349 * @hw: pointer to the HW structure 1350 * @addr: pointer to the receive address 1351 * @index: receive address array register 1352 * 1353 * Sets the receive address register array at index to the address passed 1354 * in by addr. For LPT, RAR[0] is the base address register that is to 1355 * contain the MAC address. SHRA[0-10] are the shared receive address 1356 * registers that are shared between the Host and manageability engine (ME). 1357 **/ 1358 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1359 { 1360 u32 rar_low, rar_high; 1361 u32 wlock_mac; 1362 1363 /* HW expects these in little endian so we reverse the byte order 1364 * from network order (big endian) to little endian 1365 */ 1366 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1367 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1368 1369 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1370 1371 /* If MAC address zero, no need to set the AV bit */ 1372 if (rar_low || rar_high) 1373 rar_high |= E1000_RAH_AV; 1374 1375 if (index == 0) { 1376 ew32(RAL(index), rar_low); 1377 e1e_flush(); 1378 ew32(RAH(index), rar_high); 1379 e1e_flush(); 1380 return; 1381 } 1382 1383 /* The manageability engine (ME) can lock certain SHRAR registers that 1384 * it is using - those registers are unavailable for use. 1385 */ 1386 if (index < hw->mac.rar_entry_count) { 1387 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1388 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1389 1390 /* Check if all SHRAR registers are locked */ 1391 if (wlock_mac == 1) 1392 goto out; 1393 1394 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1395 s32 ret_val; 1396 1397 ret_val = e1000_acquire_swflag_ich8lan(hw); 1398 1399 if (ret_val) 1400 goto out; 1401 1402 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1403 e1e_flush(); 1404 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1405 e1e_flush(); 1406 1407 e1000_release_swflag_ich8lan(hw); 1408 1409 /* verify the register updates */ 1410 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1411 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1412 return; 1413 } 1414 } 1415 1416 out: 1417 e_dbg("Failed to write receive address at index %d\n", index); 1418 } 1419 1420 /** 1421 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 1422 * @hw: pointer to the HW structure 1423 * 1424 * Checks if firmware is blocking the reset of the PHY. 1425 * This is a function pointer entry point only called by 1426 * reset routines. 1427 **/ 1428 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 1429 { 1430 u32 fwsm; 1431 1432 fwsm = er32(FWSM); 1433 1434 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; 1435 } 1436 1437 /** 1438 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 1439 * @hw: pointer to the HW structure 1440 * 1441 * Assumes semaphore already acquired. 1442 * 1443 **/ 1444 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 1445 { 1446 u16 phy_data; 1447 u32 strap = er32(STRAP); 1448 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 1449 E1000_STRAP_SMT_FREQ_SHIFT; 1450 s32 ret_val; 1451 1452 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 1453 1454 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1455 if (ret_val) 1456 return ret_val; 1457 1458 phy_data &= ~HV_SMB_ADDR_MASK; 1459 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1460 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1461 1462 if (hw->phy.type == e1000_phy_i217) { 1463 /* Restore SMBus frequency */ 1464 if (freq--) { 1465 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 1466 phy_data |= (freq & (1 << 0)) << 1467 HV_SMB_ADDR_FREQ_LOW_SHIFT; 1468 phy_data |= (freq & (1 << 1)) << 1469 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 1470 } else { 1471 e_dbg("Unsupported SMB frequency in PHY\n"); 1472 } 1473 } 1474 1475 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 1476 } 1477 1478 /** 1479 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 1480 * @hw: pointer to the HW structure 1481 * 1482 * SW should configure the LCD from the NVM extended configuration region 1483 * as a workaround for certain parts. 1484 **/ 1485 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1486 { 1487 struct e1000_phy_info *phy = &hw->phy; 1488 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1489 s32 ret_val = 0; 1490 u16 word_addr, reg_data, reg_addr, phy_page = 0; 1491 1492 /* Initialize the PHY from the NVM on ICH platforms. This 1493 * is needed due to an issue where the NVM configuration is 1494 * not properly autoloaded after power transitions. 1495 * Therefore, after each PHY reset, we will load the 1496 * configuration data out of the NVM manually. 1497 */ 1498 switch (hw->mac.type) { 1499 case e1000_ich8lan: 1500 if (phy->type != e1000_phy_igp_3) 1501 return ret_val; 1502 1503 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 1504 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 1505 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1506 break; 1507 } 1508 /* Fall-thru */ 1509 case e1000_pchlan: 1510 case e1000_pch2lan: 1511 case e1000_pch_lpt: 1512 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1513 break; 1514 default: 1515 return ret_val; 1516 } 1517 1518 ret_val = hw->phy.ops.acquire(hw); 1519 if (ret_val) 1520 return ret_val; 1521 1522 data = er32(FEXTNVM); 1523 if (!(data & sw_cfg_mask)) 1524 goto release; 1525 1526 /* Make sure HW does not configure LCD from PHY 1527 * extended configuration before SW configuration 1528 */ 1529 data = er32(EXTCNF_CTRL); 1530 if ((hw->mac.type < e1000_pch2lan) && 1531 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 1532 goto release; 1533 1534 cnf_size = er32(EXTCNF_SIZE); 1535 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1536 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1537 if (!cnf_size) 1538 goto release; 1539 1540 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1541 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1542 1543 if (((hw->mac.type == e1000_pchlan) && 1544 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 1545 (hw->mac.type > e1000_pchlan)) { 1546 /* HW configures the SMBus address and LEDs when the 1547 * OEM and LCD Write Enable bits are set in the NVM. 1548 * When both NVM bits are cleared, SW will configure 1549 * them instead. 1550 */ 1551 ret_val = e1000_write_smbus_addr(hw); 1552 if (ret_val) 1553 goto release; 1554 1555 data = er32(LEDCTL); 1556 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1557 (u16)data); 1558 if (ret_val) 1559 goto release; 1560 } 1561 1562 /* Configure LCD from extended configuration region. */ 1563 1564 /* cnf_base_addr is in DWORD */ 1565 word_addr = (u16)(cnf_base_addr << 1); 1566 1567 for (i = 0; i < cnf_size; i++) { 1568 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 1569 if (ret_val) 1570 goto release; 1571 1572 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 1573 1, ®_addr); 1574 if (ret_val) 1575 goto release; 1576 1577 /* Save off the PHY page for future writes. */ 1578 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1579 phy_page = reg_data; 1580 continue; 1581 } 1582 1583 reg_addr &= PHY_REG_MASK; 1584 reg_addr |= phy_page; 1585 1586 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 1587 if (ret_val) 1588 goto release; 1589 } 1590 1591 release: 1592 hw->phy.ops.release(hw); 1593 return ret_val; 1594 } 1595 1596 /** 1597 * e1000_k1_gig_workaround_hv - K1 Si workaround 1598 * @hw: pointer to the HW structure 1599 * @link: link up bool flag 1600 * 1601 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 1602 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 1603 * If link is down, the function will restore the default K1 setting located 1604 * in the NVM. 1605 **/ 1606 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1607 { 1608 s32 ret_val = 0; 1609 u16 status_reg = 0; 1610 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1611 1612 if (hw->mac.type != e1000_pchlan) 1613 return 0; 1614 1615 /* Wrap the whole flow with the sw flag */ 1616 ret_val = hw->phy.ops.acquire(hw); 1617 if (ret_val) 1618 return ret_val; 1619 1620 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1621 if (link) { 1622 if (hw->phy.type == e1000_phy_82578) { 1623 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 1624 &status_reg); 1625 if (ret_val) 1626 goto release; 1627 1628 status_reg &= (BM_CS_STATUS_LINK_UP | 1629 BM_CS_STATUS_RESOLVED | 1630 BM_CS_STATUS_SPEED_MASK); 1631 1632 if (status_reg == (BM_CS_STATUS_LINK_UP | 1633 BM_CS_STATUS_RESOLVED | 1634 BM_CS_STATUS_SPEED_1000)) 1635 k1_enable = false; 1636 } 1637 1638 if (hw->phy.type == e1000_phy_82577) { 1639 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 1640 if (ret_val) 1641 goto release; 1642 1643 status_reg &= (HV_M_STATUS_LINK_UP | 1644 HV_M_STATUS_AUTONEG_COMPLETE | 1645 HV_M_STATUS_SPEED_MASK); 1646 1647 if (status_reg == (HV_M_STATUS_LINK_UP | 1648 HV_M_STATUS_AUTONEG_COMPLETE | 1649 HV_M_STATUS_SPEED_1000)) 1650 k1_enable = false; 1651 } 1652 1653 /* Link stall fix for link up */ 1654 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 1655 if (ret_val) 1656 goto release; 1657 1658 } else { 1659 /* Link stall fix for link down */ 1660 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 1661 if (ret_val) 1662 goto release; 1663 } 1664 1665 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1666 1667 release: 1668 hw->phy.ops.release(hw); 1669 1670 return ret_val; 1671 } 1672 1673 /** 1674 * e1000_configure_k1_ich8lan - Configure K1 power state 1675 * @hw: pointer to the HW structure 1676 * @enable: K1 state to configure 1677 * 1678 * Configure the K1 power state based on the provided parameter. 1679 * Assumes semaphore already acquired. 1680 * 1681 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1682 **/ 1683 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1684 { 1685 s32 ret_val; 1686 u32 ctrl_reg = 0; 1687 u32 ctrl_ext = 0; 1688 u32 reg = 0; 1689 u16 kmrn_reg = 0; 1690 1691 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1692 &kmrn_reg); 1693 if (ret_val) 1694 return ret_val; 1695 1696 if (k1_enable) 1697 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1698 else 1699 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1700 1701 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1702 kmrn_reg); 1703 if (ret_val) 1704 return ret_val; 1705 1706 usleep_range(20, 40); 1707 ctrl_ext = er32(CTRL_EXT); 1708 ctrl_reg = er32(CTRL); 1709 1710 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1711 reg |= E1000_CTRL_FRCSPD; 1712 ew32(CTRL, reg); 1713 1714 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1715 e1e_flush(); 1716 usleep_range(20, 40); 1717 ew32(CTRL, ctrl_reg); 1718 ew32(CTRL_EXT, ctrl_ext); 1719 e1e_flush(); 1720 usleep_range(20, 40); 1721 1722 return 0; 1723 } 1724 1725 /** 1726 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1727 * @hw: pointer to the HW structure 1728 * @d0_state: boolean if entering d0 or d3 device state 1729 * 1730 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1731 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1732 * in NVM determines whether HW should configure LPLU and Gbe Disable. 1733 **/ 1734 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1735 { 1736 s32 ret_val = 0; 1737 u32 mac_reg; 1738 u16 oem_reg; 1739 1740 if (hw->mac.type < e1000_pchlan) 1741 return ret_val; 1742 1743 ret_val = hw->phy.ops.acquire(hw); 1744 if (ret_val) 1745 return ret_val; 1746 1747 if (hw->mac.type == e1000_pchlan) { 1748 mac_reg = er32(EXTCNF_CTRL); 1749 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1750 goto release; 1751 } 1752 1753 mac_reg = er32(FEXTNVM); 1754 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1755 goto release; 1756 1757 mac_reg = er32(PHY_CTRL); 1758 1759 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 1760 if (ret_val) 1761 goto release; 1762 1763 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1764 1765 if (d0_state) { 1766 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1767 oem_reg |= HV_OEM_BITS_GBE_DIS; 1768 1769 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1770 oem_reg |= HV_OEM_BITS_LPLU; 1771 } else { 1772 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 1773 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 1774 oem_reg |= HV_OEM_BITS_GBE_DIS; 1775 1776 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 1777 E1000_PHY_CTRL_NOND0A_LPLU)) 1778 oem_reg |= HV_OEM_BITS_LPLU; 1779 } 1780 1781 /* Set Restart auto-neg to activate the bits */ 1782 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 1783 !hw->phy.ops.check_reset_block(hw)) 1784 oem_reg |= HV_OEM_BITS_RESTART_AN; 1785 1786 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 1787 1788 release: 1789 hw->phy.ops.release(hw); 1790 1791 return ret_val; 1792 } 1793 1794 /** 1795 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 1796 * @hw: pointer to the HW structure 1797 **/ 1798 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 1799 { 1800 s32 ret_val; 1801 u16 data; 1802 1803 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 1804 if (ret_val) 1805 return ret_val; 1806 1807 data |= HV_KMRN_MDIO_SLOW; 1808 1809 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 1810 1811 return ret_val; 1812 } 1813 1814 /** 1815 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1816 * done after every PHY reset. 1817 **/ 1818 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1819 { 1820 s32 ret_val = 0; 1821 u16 phy_data; 1822 1823 if (hw->mac.type != e1000_pchlan) 1824 return 0; 1825 1826 /* Set MDIO slow mode before any other MDIO access */ 1827 if (hw->phy.type == e1000_phy_82577) { 1828 ret_val = e1000_set_mdio_slow_mode_hv(hw); 1829 if (ret_val) 1830 return ret_val; 1831 } 1832 1833 if (((hw->phy.type == e1000_phy_82577) && 1834 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1835 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1836 /* Disable generation of early preamble */ 1837 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 1838 if (ret_val) 1839 return ret_val; 1840 1841 /* Preamble tuning for SSC */ 1842 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 1843 if (ret_val) 1844 return ret_val; 1845 } 1846 1847 if (hw->phy.type == e1000_phy_82578) { 1848 /* Return registers to default by doing a soft reset then 1849 * writing 0x3140 to the control register. 1850 */ 1851 if (hw->phy.revision < 2) { 1852 e1000e_phy_sw_reset(hw); 1853 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 1854 } 1855 } 1856 1857 /* Select page 0 */ 1858 ret_val = hw->phy.ops.acquire(hw); 1859 if (ret_val) 1860 return ret_val; 1861 1862 hw->phy.addr = 1; 1863 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1864 hw->phy.ops.release(hw); 1865 if (ret_val) 1866 return ret_val; 1867 1868 /* Configure the K1 Si workaround during phy reset assuming there is 1869 * link so that it disables K1 if link is in 1Gbps. 1870 */ 1871 ret_val = e1000_k1_gig_workaround_hv(hw, true); 1872 if (ret_val) 1873 return ret_val; 1874 1875 /* Workaround for link disconnects on a busy hub in half duplex */ 1876 ret_val = hw->phy.ops.acquire(hw); 1877 if (ret_val) 1878 return ret_val; 1879 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 1880 if (ret_val) 1881 goto release; 1882 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 1883 if (ret_val) 1884 goto release; 1885 1886 /* set MSE higher to enable link to stay up when noise is high */ 1887 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 1888 release: 1889 hw->phy.ops.release(hw); 1890 1891 return ret_val; 1892 } 1893 1894 /** 1895 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 1896 * @hw: pointer to the HW structure 1897 **/ 1898 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 1899 { 1900 u32 mac_reg; 1901 u16 i, phy_reg = 0; 1902 s32 ret_val; 1903 1904 ret_val = hw->phy.ops.acquire(hw); 1905 if (ret_val) 1906 return; 1907 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1908 if (ret_val) 1909 goto release; 1910 1911 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 1912 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1913 mac_reg = er32(RAL(i)); 1914 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 1915 (u16)(mac_reg & 0xFFFF)); 1916 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 1917 (u16)((mac_reg >> 16) & 0xFFFF)); 1918 1919 mac_reg = er32(RAH(i)); 1920 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 1921 (u16)(mac_reg & 0xFFFF)); 1922 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 1923 (u16)((mac_reg & E1000_RAH_AV) 1924 >> 16)); 1925 } 1926 1927 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1928 1929 release: 1930 hw->phy.ops.release(hw); 1931 } 1932 1933 /** 1934 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 1935 * with 82579 PHY 1936 * @hw: pointer to the HW structure 1937 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 1938 **/ 1939 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 1940 { 1941 s32 ret_val = 0; 1942 u16 phy_reg, data; 1943 u32 mac_reg; 1944 u16 i; 1945 1946 if (hw->mac.type < e1000_pch2lan) 1947 return 0; 1948 1949 /* disable Rx path while enabling/disabling workaround */ 1950 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 1951 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 1952 if (ret_val) 1953 return ret_val; 1954 1955 if (enable) { 1956 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for 1957 * SHRAL/H) and initial CRC values to the MAC 1958 */ 1959 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1960 u8 mac_addr[ETH_ALEN] = { 0 }; 1961 u32 addr_high, addr_low; 1962 1963 addr_high = er32(RAH(i)); 1964 if (!(addr_high & E1000_RAH_AV)) 1965 continue; 1966 addr_low = er32(RAL(i)); 1967 mac_addr[0] = (addr_low & 0xFF); 1968 mac_addr[1] = ((addr_low >> 8) & 0xFF); 1969 mac_addr[2] = ((addr_low >> 16) & 0xFF); 1970 mac_addr[3] = ((addr_low >> 24) & 0xFF); 1971 mac_addr[4] = (addr_high & 0xFF); 1972 mac_addr[5] = ((addr_high >> 8) & 0xFF); 1973 1974 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 1975 } 1976 1977 /* Write Rx addresses to the PHY */ 1978 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 1979 1980 /* Enable jumbo frame workaround in the MAC */ 1981 mac_reg = er32(FFLT_DBG); 1982 mac_reg &= ~(1 << 14); 1983 mac_reg |= (7 << 15); 1984 ew32(FFLT_DBG, mac_reg); 1985 1986 mac_reg = er32(RCTL); 1987 mac_reg |= E1000_RCTL_SECRC; 1988 ew32(RCTL, mac_reg); 1989 1990 ret_val = e1000e_read_kmrn_reg(hw, 1991 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1992 &data); 1993 if (ret_val) 1994 return ret_val; 1995 ret_val = e1000e_write_kmrn_reg(hw, 1996 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1997 data | (1 << 0)); 1998 if (ret_val) 1999 return ret_val; 2000 ret_val = e1000e_read_kmrn_reg(hw, 2001 E1000_KMRNCTRLSTA_HD_CTRL, 2002 &data); 2003 if (ret_val) 2004 return ret_val; 2005 data &= ~(0xF << 8); 2006 data |= (0xB << 8); 2007 ret_val = e1000e_write_kmrn_reg(hw, 2008 E1000_KMRNCTRLSTA_HD_CTRL, 2009 data); 2010 if (ret_val) 2011 return ret_val; 2012 2013 /* Enable jumbo frame workaround in the PHY */ 2014 e1e_rphy(hw, PHY_REG(769, 23), &data); 2015 data &= ~(0x7F << 5); 2016 data |= (0x37 << 5); 2017 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2018 if (ret_val) 2019 return ret_val; 2020 e1e_rphy(hw, PHY_REG(769, 16), &data); 2021 data &= ~(1 << 13); 2022 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2023 if (ret_val) 2024 return ret_val; 2025 e1e_rphy(hw, PHY_REG(776, 20), &data); 2026 data &= ~(0x3FF << 2); 2027 data |= (0x1A << 2); 2028 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2029 if (ret_val) 2030 return ret_val; 2031 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2032 if (ret_val) 2033 return ret_val; 2034 e1e_rphy(hw, HV_PM_CTRL, &data); 2035 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); 2036 if (ret_val) 2037 return ret_val; 2038 } else { 2039 /* Write MAC register values back to h/w defaults */ 2040 mac_reg = er32(FFLT_DBG); 2041 mac_reg &= ~(0xF << 14); 2042 ew32(FFLT_DBG, mac_reg); 2043 2044 mac_reg = er32(RCTL); 2045 mac_reg &= ~E1000_RCTL_SECRC; 2046 ew32(RCTL, mac_reg); 2047 2048 ret_val = e1000e_read_kmrn_reg(hw, 2049 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2050 &data); 2051 if (ret_val) 2052 return ret_val; 2053 ret_val = e1000e_write_kmrn_reg(hw, 2054 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2055 data & ~(1 << 0)); 2056 if (ret_val) 2057 return ret_val; 2058 ret_val = e1000e_read_kmrn_reg(hw, 2059 E1000_KMRNCTRLSTA_HD_CTRL, 2060 &data); 2061 if (ret_val) 2062 return ret_val; 2063 data &= ~(0xF << 8); 2064 data |= (0xB << 8); 2065 ret_val = e1000e_write_kmrn_reg(hw, 2066 E1000_KMRNCTRLSTA_HD_CTRL, 2067 data); 2068 if (ret_val) 2069 return ret_val; 2070 2071 /* Write PHY register values back to h/w defaults */ 2072 e1e_rphy(hw, PHY_REG(769, 23), &data); 2073 data &= ~(0x7F << 5); 2074 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2075 if (ret_val) 2076 return ret_val; 2077 e1e_rphy(hw, PHY_REG(769, 16), &data); 2078 data |= (1 << 13); 2079 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2080 if (ret_val) 2081 return ret_val; 2082 e1e_rphy(hw, PHY_REG(776, 20), &data); 2083 data &= ~(0x3FF << 2); 2084 data |= (0x8 << 2); 2085 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2086 if (ret_val) 2087 return ret_val; 2088 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2089 if (ret_val) 2090 return ret_val; 2091 e1e_rphy(hw, HV_PM_CTRL, &data); 2092 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); 2093 if (ret_val) 2094 return ret_val; 2095 } 2096 2097 /* re-enable Rx path after enabling/disabling workaround */ 2098 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 2099 } 2100 2101 /** 2102 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2103 * done after every PHY reset. 2104 **/ 2105 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2106 { 2107 s32 ret_val = 0; 2108 2109 if (hw->mac.type != e1000_pch2lan) 2110 return 0; 2111 2112 /* Set MDIO slow mode before any other MDIO access */ 2113 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2114 if (ret_val) 2115 return ret_val; 2116 2117 ret_val = hw->phy.ops.acquire(hw); 2118 if (ret_val) 2119 return ret_val; 2120 /* set MSE higher to enable link to stay up when noise is high */ 2121 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2122 if (ret_val) 2123 goto release; 2124 /* drop link after 5 times MSE threshold was reached */ 2125 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2126 release: 2127 hw->phy.ops.release(hw); 2128 2129 return ret_val; 2130 } 2131 2132 /** 2133 * e1000_k1_gig_workaround_lv - K1 Si workaround 2134 * @hw: pointer to the HW structure 2135 * 2136 * Workaround to set the K1 beacon duration for 82579 parts 2137 **/ 2138 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2139 { 2140 s32 ret_val = 0; 2141 u16 status_reg = 0; 2142 u32 mac_reg; 2143 u16 phy_reg; 2144 2145 if (hw->mac.type != e1000_pch2lan) 2146 return 0; 2147 2148 /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 2149 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2150 if (ret_val) 2151 return ret_val; 2152 2153 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2154 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2155 mac_reg = er32(FEXTNVM4); 2156 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2157 2158 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); 2159 if (ret_val) 2160 return ret_val; 2161 2162 if (status_reg & HV_M_STATUS_SPEED_1000) { 2163 u16 pm_phy_reg; 2164 2165 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 2166 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 2167 /* LV 1G Packet drop issue wa */ 2168 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2169 if (ret_val) 2170 return ret_val; 2171 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; 2172 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2173 if (ret_val) 2174 return ret_val; 2175 } else { 2176 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2177 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 2178 } 2179 ew32(FEXTNVM4, mac_reg); 2180 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); 2181 } 2182 2183 return ret_val; 2184 } 2185 2186 /** 2187 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2188 * @hw: pointer to the HW structure 2189 * @gate: boolean set to true to gate, false to ungate 2190 * 2191 * Gate/ungate the automatic PHY configuration via hardware; perform 2192 * the configuration via software instead. 2193 **/ 2194 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2195 { 2196 u32 extcnf_ctrl; 2197 2198 if (hw->mac.type < e1000_pch2lan) 2199 return; 2200 2201 extcnf_ctrl = er32(EXTCNF_CTRL); 2202 2203 if (gate) 2204 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2205 else 2206 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2207 2208 ew32(EXTCNF_CTRL, extcnf_ctrl); 2209 } 2210 2211 /** 2212 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2213 * @hw: pointer to the HW structure 2214 * 2215 * Check the appropriate indication the MAC has finished configuring the 2216 * PHY after a software reset. 2217 **/ 2218 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2219 { 2220 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2221 2222 /* Wait for basic configuration completes before proceeding */ 2223 do { 2224 data = er32(STATUS); 2225 data &= E1000_STATUS_LAN_INIT_DONE; 2226 usleep_range(100, 200); 2227 } while ((!data) && --loop); 2228 2229 /* If basic configuration is incomplete before the above loop 2230 * count reaches 0, loading the configuration from NVM will 2231 * leave the PHY in a bad state possibly resulting in no link. 2232 */ 2233 if (loop == 0) 2234 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2235 2236 /* Clear the Init Done bit for the next init event */ 2237 data = er32(STATUS); 2238 data &= ~E1000_STATUS_LAN_INIT_DONE; 2239 ew32(STATUS, data); 2240 } 2241 2242 /** 2243 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2244 * @hw: pointer to the HW structure 2245 **/ 2246 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2247 { 2248 s32 ret_val = 0; 2249 u16 reg; 2250 2251 if (hw->phy.ops.check_reset_block(hw)) 2252 return 0; 2253 2254 /* Allow time for h/w to get to quiescent state after reset */ 2255 usleep_range(10000, 20000); 2256 2257 /* Perform any necessary post-reset workarounds */ 2258 switch (hw->mac.type) { 2259 case e1000_pchlan: 2260 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2261 if (ret_val) 2262 return ret_val; 2263 break; 2264 case e1000_pch2lan: 2265 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2266 if (ret_val) 2267 return ret_val; 2268 break; 2269 default: 2270 break; 2271 } 2272 2273 /* Clear the host wakeup bit after lcd reset */ 2274 if (hw->mac.type >= e1000_pchlan) { 2275 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2276 reg &= ~BM_WUC_HOST_WU_BIT; 2277 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2278 } 2279 2280 /* Configure the LCD with the extended configuration region in NVM */ 2281 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2282 if (ret_val) 2283 return ret_val; 2284 2285 /* Configure the LCD with the OEM bits in NVM */ 2286 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2287 2288 if (hw->mac.type == e1000_pch2lan) { 2289 /* Ungate automatic PHY configuration on non-managed 82579 */ 2290 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2291 usleep_range(10000, 20000); 2292 e1000_gate_hw_phy_config_ich8lan(hw, false); 2293 } 2294 2295 /* Set EEE LPI Update Timer to 200usec */ 2296 ret_val = hw->phy.ops.acquire(hw); 2297 if (ret_val) 2298 return ret_val; 2299 ret_val = e1000_write_emi_reg_locked(hw, 2300 I82579_LPI_UPDATE_TIMER, 2301 0x1387); 2302 hw->phy.ops.release(hw); 2303 } 2304 2305 return ret_val; 2306 } 2307 2308 /** 2309 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2310 * @hw: pointer to the HW structure 2311 * 2312 * Resets the PHY 2313 * This is a function pointer entry point called by drivers 2314 * or other shared routines. 2315 **/ 2316 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2317 { 2318 s32 ret_val = 0; 2319 2320 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2321 if ((hw->mac.type == e1000_pch2lan) && 2322 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2323 e1000_gate_hw_phy_config_ich8lan(hw, true); 2324 2325 ret_val = e1000e_phy_hw_reset_generic(hw); 2326 if (ret_val) 2327 return ret_val; 2328 2329 return e1000_post_phy_reset_ich8lan(hw); 2330 } 2331 2332 /** 2333 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2334 * @hw: pointer to the HW structure 2335 * @active: true to enable LPLU, false to disable 2336 * 2337 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2338 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2339 * the phy speed. This function will manually set the LPLU bit and restart 2340 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2341 * since it configures the same bit. 2342 **/ 2343 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2344 { 2345 s32 ret_val; 2346 u16 oem_reg; 2347 2348 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2349 if (ret_val) 2350 return ret_val; 2351 2352 if (active) 2353 oem_reg |= HV_OEM_BITS_LPLU; 2354 else 2355 oem_reg &= ~HV_OEM_BITS_LPLU; 2356 2357 if (!hw->phy.ops.check_reset_block(hw)) 2358 oem_reg |= HV_OEM_BITS_RESTART_AN; 2359 2360 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2361 } 2362 2363 /** 2364 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2365 * @hw: pointer to the HW structure 2366 * @active: true to enable LPLU, false to disable 2367 * 2368 * Sets the LPLU D0 state according to the active flag. When 2369 * activating LPLU this function also disables smart speed 2370 * and vice versa. LPLU will not be activated unless the 2371 * device autonegotiation advertisement meets standards of 2372 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2373 * This is a function pointer entry point only called by 2374 * PHY setup routines. 2375 **/ 2376 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2377 { 2378 struct e1000_phy_info *phy = &hw->phy; 2379 u32 phy_ctrl; 2380 s32 ret_val = 0; 2381 u16 data; 2382 2383 if (phy->type == e1000_phy_ife) 2384 return 0; 2385 2386 phy_ctrl = er32(PHY_CTRL); 2387 2388 if (active) { 2389 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2390 ew32(PHY_CTRL, phy_ctrl); 2391 2392 if (phy->type != e1000_phy_igp_3) 2393 return 0; 2394 2395 /* Call gig speed drop workaround on LPLU before accessing 2396 * any PHY registers 2397 */ 2398 if (hw->mac.type == e1000_ich8lan) 2399 e1000e_gig_downshift_workaround_ich8lan(hw); 2400 2401 /* When LPLU is enabled, we should disable SmartSpeed */ 2402 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2403 if (ret_val) 2404 return ret_val; 2405 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2406 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2407 if (ret_val) 2408 return ret_val; 2409 } else { 2410 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2411 ew32(PHY_CTRL, phy_ctrl); 2412 2413 if (phy->type != e1000_phy_igp_3) 2414 return 0; 2415 2416 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2417 * during Dx states where the power conservation is most 2418 * important. During driver activity we should enable 2419 * SmartSpeed, so performance is maintained. 2420 */ 2421 if (phy->smart_speed == e1000_smart_speed_on) { 2422 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2423 &data); 2424 if (ret_val) 2425 return ret_val; 2426 2427 data |= IGP01E1000_PSCFR_SMART_SPEED; 2428 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2429 data); 2430 if (ret_val) 2431 return ret_val; 2432 } else if (phy->smart_speed == e1000_smart_speed_off) { 2433 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2434 &data); 2435 if (ret_val) 2436 return ret_val; 2437 2438 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2439 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2440 data); 2441 if (ret_val) 2442 return ret_val; 2443 } 2444 } 2445 2446 return 0; 2447 } 2448 2449 /** 2450 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2451 * @hw: pointer to the HW structure 2452 * @active: true to enable LPLU, false to disable 2453 * 2454 * Sets the LPLU D3 state according to the active flag. When 2455 * activating LPLU this function also disables smart speed 2456 * and vice versa. LPLU will not be activated unless the 2457 * device autonegotiation advertisement meets standards of 2458 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2459 * This is a function pointer entry point only called by 2460 * PHY setup routines. 2461 **/ 2462 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2463 { 2464 struct e1000_phy_info *phy = &hw->phy; 2465 u32 phy_ctrl; 2466 s32 ret_val = 0; 2467 u16 data; 2468 2469 phy_ctrl = er32(PHY_CTRL); 2470 2471 if (!active) { 2472 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2473 ew32(PHY_CTRL, phy_ctrl); 2474 2475 if (phy->type != e1000_phy_igp_3) 2476 return 0; 2477 2478 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2479 * during Dx states where the power conservation is most 2480 * important. During driver activity we should enable 2481 * SmartSpeed, so performance is maintained. 2482 */ 2483 if (phy->smart_speed == e1000_smart_speed_on) { 2484 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2485 &data); 2486 if (ret_val) 2487 return ret_val; 2488 2489 data |= IGP01E1000_PSCFR_SMART_SPEED; 2490 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2491 data); 2492 if (ret_val) 2493 return ret_val; 2494 } else if (phy->smart_speed == e1000_smart_speed_off) { 2495 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2496 &data); 2497 if (ret_val) 2498 return ret_val; 2499 2500 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2501 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2502 data); 2503 if (ret_val) 2504 return ret_val; 2505 } 2506 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2507 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2508 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2509 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2510 ew32(PHY_CTRL, phy_ctrl); 2511 2512 if (phy->type != e1000_phy_igp_3) 2513 return 0; 2514 2515 /* Call gig speed drop workaround on LPLU before accessing 2516 * any PHY registers 2517 */ 2518 if (hw->mac.type == e1000_ich8lan) 2519 e1000e_gig_downshift_workaround_ich8lan(hw); 2520 2521 /* When LPLU is enabled, we should disable SmartSpeed */ 2522 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2523 if (ret_val) 2524 return ret_val; 2525 2526 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2527 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2528 } 2529 2530 return ret_val; 2531 } 2532 2533 /** 2534 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 2535 * @hw: pointer to the HW structure 2536 * @bank: pointer to the variable that returns the active bank 2537 * 2538 * Reads signature byte from the NVM using the flash access registers. 2539 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 2540 **/ 2541 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 2542 { 2543 u32 eecd; 2544 struct e1000_nvm_info *nvm = &hw->nvm; 2545 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 2546 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 2547 u8 sig_byte = 0; 2548 s32 ret_val; 2549 2550 switch (hw->mac.type) { 2551 case e1000_ich8lan: 2552 case e1000_ich9lan: 2553 eecd = er32(EECD); 2554 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 2555 E1000_EECD_SEC1VAL_VALID_MASK) { 2556 if (eecd & E1000_EECD_SEC1VAL) 2557 *bank = 1; 2558 else 2559 *bank = 0; 2560 2561 return 0; 2562 } 2563 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 2564 /* fall-thru */ 2565 default: 2566 /* set bank to 0 in case flash read fails */ 2567 *bank = 0; 2568 2569 /* Check bank 0 */ 2570 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 2571 &sig_byte); 2572 if (ret_val) 2573 return ret_val; 2574 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2575 E1000_ICH_NVM_SIG_VALUE) { 2576 *bank = 0; 2577 return 0; 2578 } 2579 2580 /* Check bank 1 */ 2581 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 2582 bank1_offset, 2583 &sig_byte); 2584 if (ret_val) 2585 return ret_val; 2586 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2587 E1000_ICH_NVM_SIG_VALUE) { 2588 *bank = 1; 2589 return 0; 2590 } 2591 2592 e_dbg("ERROR: No valid NVM bank present\n"); 2593 return -E1000_ERR_NVM; 2594 } 2595 } 2596 2597 /** 2598 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2599 * @hw: pointer to the HW structure 2600 * @offset: The offset (in bytes) of the word(s) to read. 2601 * @words: Size of data to read in words 2602 * @data: Pointer to the word(s) to read at offset. 2603 * 2604 * Reads a word(s) from the NVM using the flash access registers. 2605 **/ 2606 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2607 u16 *data) 2608 { 2609 struct e1000_nvm_info *nvm = &hw->nvm; 2610 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2611 u32 act_offset; 2612 s32 ret_val = 0; 2613 u32 bank = 0; 2614 u16 i, word; 2615 2616 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2617 (words == 0)) { 2618 e_dbg("nvm parameter(s) out of bounds\n"); 2619 ret_val = -E1000_ERR_NVM; 2620 goto out; 2621 } 2622 2623 nvm->ops.acquire(hw); 2624 2625 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2626 if (ret_val) { 2627 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2628 bank = 0; 2629 } 2630 2631 act_offset = (bank) ? nvm->flash_bank_size : 0; 2632 act_offset += offset; 2633 2634 ret_val = 0; 2635 for (i = 0; i < words; i++) { 2636 if (dev_spec->shadow_ram[offset + i].modified) { 2637 data[i] = dev_spec->shadow_ram[offset + i].value; 2638 } else { 2639 ret_val = e1000_read_flash_word_ich8lan(hw, 2640 act_offset + i, 2641 &word); 2642 if (ret_val) 2643 break; 2644 data[i] = word; 2645 } 2646 } 2647 2648 nvm->ops.release(hw); 2649 2650 out: 2651 if (ret_val) 2652 e_dbg("NVM read error: %d\n", ret_val); 2653 2654 return ret_val; 2655 } 2656 2657 /** 2658 * e1000_flash_cycle_init_ich8lan - Initialize flash 2659 * @hw: pointer to the HW structure 2660 * 2661 * This function does initial flash setup so that a new read/write/erase cycle 2662 * can be started. 2663 **/ 2664 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2665 { 2666 union ich8_hws_flash_status hsfsts; 2667 s32 ret_val = -E1000_ERR_NVM; 2668 2669 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2670 2671 /* Check if the flash descriptor is valid */ 2672 if (!hsfsts.hsf_status.fldesvalid) { 2673 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 2674 return -E1000_ERR_NVM; 2675 } 2676 2677 /* Clear FCERR and DAEL in hw status by writing 1 */ 2678 hsfsts.hsf_status.flcerr = 1; 2679 hsfsts.hsf_status.dael = 1; 2680 2681 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2682 2683 /* Either we should have a hardware SPI cycle in progress 2684 * bit to check against, in order to start a new cycle or 2685 * FDONE bit should be changed in the hardware so that it 2686 * is 1 after hardware reset, which can then be used as an 2687 * indication whether a cycle is in progress or has been 2688 * completed. 2689 */ 2690 2691 if (!hsfsts.hsf_status.flcinprog) { 2692 /* There is no cycle running at present, 2693 * so we can start a cycle. 2694 * Begin by setting Flash Cycle Done. 2695 */ 2696 hsfsts.hsf_status.flcdone = 1; 2697 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2698 ret_val = 0; 2699 } else { 2700 s32 i; 2701 2702 /* Otherwise poll for sometime so the current 2703 * cycle has a chance to end before giving up. 2704 */ 2705 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2706 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2707 if (!hsfsts.hsf_status.flcinprog) { 2708 ret_val = 0; 2709 break; 2710 } 2711 udelay(1); 2712 } 2713 if (!ret_val) { 2714 /* Successful in waiting for previous cycle to timeout, 2715 * now set the Flash Cycle Done. 2716 */ 2717 hsfsts.hsf_status.flcdone = 1; 2718 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2719 } else { 2720 e_dbg("Flash controller busy, cannot get access\n"); 2721 } 2722 } 2723 2724 return ret_val; 2725 } 2726 2727 /** 2728 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 2729 * @hw: pointer to the HW structure 2730 * @timeout: maximum time to wait for completion 2731 * 2732 * This function starts a flash cycle and waits for its completion. 2733 **/ 2734 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 2735 { 2736 union ich8_hws_flash_ctrl hsflctl; 2737 union ich8_hws_flash_status hsfsts; 2738 u32 i = 0; 2739 2740 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 2741 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2742 hsflctl.hsf_ctrl.flcgo = 1; 2743 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2744 2745 /* wait till FDONE bit is set to 1 */ 2746 do { 2747 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2748 if (hsfsts.hsf_status.flcdone) 2749 break; 2750 udelay(1); 2751 } while (i++ < timeout); 2752 2753 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 2754 return 0; 2755 2756 return -E1000_ERR_NVM; 2757 } 2758 2759 /** 2760 * e1000_read_flash_word_ich8lan - Read word from flash 2761 * @hw: pointer to the HW structure 2762 * @offset: offset to data location 2763 * @data: pointer to the location for storing the data 2764 * 2765 * Reads the flash word at offset into data. Offset is converted 2766 * to bytes before read. 2767 **/ 2768 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 2769 u16 *data) 2770 { 2771 /* Must convert offset into bytes. */ 2772 offset <<= 1; 2773 2774 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 2775 } 2776 2777 /** 2778 * e1000_read_flash_byte_ich8lan - Read byte from flash 2779 * @hw: pointer to the HW structure 2780 * @offset: The offset of the byte to read. 2781 * @data: Pointer to a byte to store the value read. 2782 * 2783 * Reads a single byte from the NVM using the flash access registers. 2784 **/ 2785 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2786 u8 *data) 2787 { 2788 s32 ret_val; 2789 u16 word = 0; 2790 2791 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 2792 if (ret_val) 2793 return ret_val; 2794 2795 *data = (u8)word; 2796 2797 return 0; 2798 } 2799 2800 /** 2801 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 2802 * @hw: pointer to the HW structure 2803 * @offset: The offset (in bytes) of the byte or word to read. 2804 * @size: Size of data to read, 1=byte 2=word 2805 * @data: Pointer to the word to store the value read. 2806 * 2807 * Reads a byte or word from the NVM using the flash access registers. 2808 **/ 2809 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2810 u8 size, u16 *data) 2811 { 2812 union ich8_hws_flash_status hsfsts; 2813 union ich8_hws_flash_ctrl hsflctl; 2814 u32 flash_linear_addr; 2815 u32 flash_data = 0; 2816 s32 ret_val = -E1000_ERR_NVM; 2817 u8 count = 0; 2818 2819 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 2820 return -E1000_ERR_NVM; 2821 2822 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2823 hw->nvm.flash_base_addr); 2824 2825 do { 2826 udelay(1); 2827 /* Steps */ 2828 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2829 if (ret_val) 2830 break; 2831 2832 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2833 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2834 hsflctl.hsf_ctrl.fldbcount = size - 1; 2835 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 2836 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2837 2838 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 2839 2840 ret_val = 2841 e1000_flash_cycle_ich8lan(hw, 2842 ICH_FLASH_READ_COMMAND_TIMEOUT); 2843 2844 /* Check if FCERR is set to 1, if set to 1, clear it 2845 * and try the whole sequence a few more times, else 2846 * read in (shift in) the Flash Data0, the order is 2847 * least significant byte first msb to lsb 2848 */ 2849 if (!ret_val) { 2850 flash_data = er32flash(ICH_FLASH_FDATA0); 2851 if (size == 1) 2852 *data = (u8)(flash_data & 0x000000FF); 2853 else if (size == 2) 2854 *data = (u16)(flash_data & 0x0000FFFF); 2855 break; 2856 } else { 2857 /* If we've gotten here, then things are probably 2858 * completely hosed, but if the error condition is 2859 * detected, it won't hurt to give it another try... 2860 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2861 */ 2862 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2863 if (hsfsts.hsf_status.flcerr) { 2864 /* Repeat for some time before giving up. */ 2865 continue; 2866 } else if (!hsfsts.hsf_status.flcdone) { 2867 e_dbg("Timeout error - flash cycle did not complete.\n"); 2868 break; 2869 } 2870 } 2871 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2872 2873 return ret_val; 2874 } 2875 2876 /** 2877 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 2878 * @hw: pointer to the HW structure 2879 * @offset: The offset (in bytes) of the word(s) to write. 2880 * @words: Size of data to write in words 2881 * @data: Pointer to the word(s) to write at offset. 2882 * 2883 * Writes a byte or word to the NVM using the flash access registers. 2884 **/ 2885 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2886 u16 *data) 2887 { 2888 struct e1000_nvm_info *nvm = &hw->nvm; 2889 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2890 u16 i; 2891 2892 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2893 (words == 0)) { 2894 e_dbg("nvm parameter(s) out of bounds\n"); 2895 return -E1000_ERR_NVM; 2896 } 2897 2898 nvm->ops.acquire(hw); 2899 2900 for (i = 0; i < words; i++) { 2901 dev_spec->shadow_ram[offset + i].modified = true; 2902 dev_spec->shadow_ram[offset + i].value = data[i]; 2903 } 2904 2905 nvm->ops.release(hw); 2906 2907 return 0; 2908 } 2909 2910 /** 2911 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 2912 * @hw: pointer to the HW structure 2913 * 2914 * The NVM checksum is updated by calling the generic update_nvm_checksum, 2915 * which writes the checksum to the shadow ram. The changes in the shadow 2916 * ram are then committed to the EEPROM by processing each bank at a time 2917 * checking for the modified bit and writing only the pending changes. 2918 * After a successful commit, the shadow ram is cleared and is ready for 2919 * future writes. 2920 **/ 2921 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 2922 { 2923 struct e1000_nvm_info *nvm = &hw->nvm; 2924 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2925 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 2926 s32 ret_val; 2927 u16 data; 2928 2929 ret_val = e1000e_update_nvm_checksum_generic(hw); 2930 if (ret_val) 2931 goto out; 2932 2933 if (nvm->type != e1000_nvm_flash_sw) 2934 goto out; 2935 2936 nvm->ops.acquire(hw); 2937 2938 /* We're writing to the opposite bank so if we're on bank 1, 2939 * write to bank 0 etc. We also need to erase the segment that 2940 * is going to be written 2941 */ 2942 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2943 if (ret_val) { 2944 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2945 bank = 0; 2946 } 2947 2948 if (bank == 0) { 2949 new_bank_offset = nvm->flash_bank_size; 2950 old_bank_offset = 0; 2951 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2952 if (ret_val) 2953 goto release; 2954 } else { 2955 old_bank_offset = nvm->flash_bank_size; 2956 new_bank_offset = 0; 2957 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2958 if (ret_val) 2959 goto release; 2960 } 2961 2962 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2963 /* Determine whether to write the value stored 2964 * in the other NVM bank or a modified value stored 2965 * in the shadow RAM 2966 */ 2967 if (dev_spec->shadow_ram[i].modified) { 2968 data = dev_spec->shadow_ram[i].value; 2969 } else { 2970 ret_val = e1000_read_flash_word_ich8lan(hw, i + 2971 old_bank_offset, 2972 &data); 2973 if (ret_val) 2974 break; 2975 } 2976 2977 /* If the word is 0x13, then make sure the signature bits 2978 * (15:14) are 11b until the commit has completed. 2979 * This will allow us to write 10b which indicates the 2980 * signature is valid. We want to do this after the write 2981 * has completed so that we don't mark the segment valid 2982 * while the write is still in progress 2983 */ 2984 if (i == E1000_ICH_NVM_SIG_WORD) 2985 data |= E1000_ICH_NVM_SIG_MASK; 2986 2987 /* Convert offset to bytes. */ 2988 act_offset = (i + new_bank_offset) << 1; 2989 2990 usleep_range(100, 200); 2991 /* Write the bytes to the new bank. */ 2992 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2993 act_offset, 2994 (u8)data); 2995 if (ret_val) 2996 break; 2997 2998 usleep_range(100, 200); 2999 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3000 act_offset + 1, 3001 (u8)(data >> 8)); 3002 if (ret_val) 3003 break; 3004 } 3005 3006 /* Don't bother writing the segment valid bits if sector 3007 * programming failed. 3008 */ 3009 if (ret_val) { 3010 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3011 e_dbg("Flash commit failed.\n"); 3012 goto release; 3013 } 3014 3015 /* Finally validate the new segment by setting bit 15:14 3016 * to 10b in word 0x13 , this can be done without an 3017 * erase as well since these bits are 11 to start with 3018 * and we need to change bit 14 to 0b 3019 */ 3020 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3021 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 3022 if (ret_val) 3023 goto release; 3024 3025 data &= 0xBFFF; 3026 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3027 act_offset * 2 + 1, 3028 (u8)(data >> 8)); 3029 if (ret_val) 3030 goto release; 3031 3032 /* And invalidate the previously valid segment by setting 3033 * its signature word (0x13) high_byte to 0b. This can be 3034 * done without an erase because flash erase sets all bits 3035 * to 1's. We can write 1's to 0's without an erase 3036 */ 3037 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3038 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 3039 if (ret_val) 3040 goto release; 3041 3042 /* Great! Everything worked, we can now clear the cached entries. */ 3043 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3044 dev_spec->shadow_ram[i].modified = false; 3045 dev_spec->shadow_ram[i].value = 0xFFFF; 3046 } 3047 3048 release: 3049 nvm->ops.release(hw); 3050 3051 /* Reload the EEPROM, or else modifications will not appear 3052 * until after the next adapter reset. 3053 */ 3054 if (!ret_val) { 3055 nvm->ops.reload(hw); 3056 usleep_range(10000, 20000); 3057 } 3058 3059 out: 3060 if (ret_val) 3061 e_dbg("NVM update error: %d\n", ret_val); 3062 3063 return ret_val; 3064 } 3065 3066 /** 3067 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 3068 * @hw: pointer to the HW structure 3069 * 3070 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 3071 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 3072 * calculated, in which case we need to calculate the checksum and set bit 6. 3073 **/ 3074 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 3075 { 3076 s32 ret_val; 3077 u16 data; 3078 u16 word; 3079 u16 valid_csum_mask; 3080 3081 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 3082 * the checksum needs to be fixed. This bit is an indication that 3083 * the NVM was prepared by OEM software and did not calculate 3084 * the checksum...a likely scenario. 3085 */ 3086 switch (hw->mac.type) { 3087 case e1000_pch_lpt: 3088 word = NVM_COMPAT; 3089 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 3090 break; 3091 default: 3092 word = NVM_FUTURE_INIT_WORD1; 3093 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 3094 break; 3095 } 3096 3097 ret_val = e1000_read_nvm(hw, word, 1, &data); 3098 if (ret_val) 3099 return ret_val; 3100 3101 if (!(data & valid_csum_mask)) { 3102 data |= valid_csum_mask; 3103 ret_val = e1000_write_nvm(hw, word, 1, &data); 3104 if (ret_val) 3105 return ret_val; 3106 ret_val = e1000e_update_nvm_checksum(hw); 3107 if (ret_val) 3108 return ret_val; 3109 } 3110 3111 return e1000e_validate_nvm_checksum_generic(hw); 3112 } 3113 3114 /** 3115 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 3116 * @hw: pointer to the HW structure 3117 * 3118 * To prevent malicious write/erase of the NVM, set it to be read-only 3119 * so that the hardware ignores all write/erase cycles of the NVM via 3120 * the flash control registers. The shadow-ram copy of the NVM will 3121 * still be updated, however any updates to this copy will not stick 3122 * across driver reloads. 3123 **/ 3124 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 3125 { 3126 struct e1000_nvm_info *nvm = &hw->nvm; 3127 union ich8_flash_protected_range pr0; 3128 union ich8_hws_flash_status hsfsts; 3129 u32 gfpreg; 3130 3131 nvm->ops.acquire(hw); 3132 3133 gfpreg = er32flash(ICH_FLASH_GFPREG); 3134 3135 /* Write-protect GbE Sector of NVM */ 3136 pr0.regval = er32flash(ICH_FLASH_PR0); 3137 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 3138 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 3139 pr0.range.wpe = true; 3140 ew32flash(ICH_FLASH_PR0, pr0.regval); 3141 3142 /* Lock down a subset of GbE Flash Control Registers, e.g. 3143 * PR0 to prevent the write-protection from being lifted. 3144 * Once FLOCKDN is set, the registers protected by it cannot 3145 * be written until FLOCKDN is cleared by a hardware reset. 3146 */ 3147 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3148 hsfsts.hsf_status.flockdn = true; 3149 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3150 3151 nvm->ops.release(hw); 3152 } 3153 3154 /** 3155 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 3156 * @hw: pointer to the HW structure 3157 * @offset: The offset (in bytes) of the byte/word to read. 3158 * @size: Size of data to read, 1=byte 2=word 3159 * @data: The byte(s) to write to the NVM. 3160 * 3161 * Writes one/two bytes to the NVM using the flash access registers. 3162 **/ 3163 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3164 u8 size, u16 data) 3165 { 3166 union ich8_hws_flash_status hsfsts; 3167 union ich8_hws_flash_ctrl hsflctl; 3168 u32 flash_linear_addr; 3169 u32 flash_data = 0; 3170 s32 ret_val; 3171 u8 count = 0; 3172 3173 if (size < 1 || size > 2 || data > size * 0xff || 3174 offset > ICH_FLASH_LINEAR_ADDR_MASK) 3175 return -E1000_ERR_NVM; 3176 3177 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3178 hw->nvm.flash_base_addr); 3179 3180 do { 3181 udelay(1); 3182 /* Steps */ 3183 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3184 if (ret_val) 3185 break; 3186 3187 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3188 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3189 hsflctl.hsf_ctrl.fldbcount = size - 1; 3190 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 3191 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3192 3193 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3194 3195 if (size == 1) 3196 flash_data = (u32)data & 0x00FF; 3197 else 3198 flash_data = (u32)data; 3199 3200 ew32flash(ICH_FLASH_FDATA0, flash_data); 3201 3202 /* check if FCERR is set to 1 , if set to 1, clear it 3203 * and try the whole sequence a few more times else done 3204 */ 3205 ret_val = 3206 e1000_flash_cycle_ich8lan(hw, 3207 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 3208 if (!ret_val) 3209 break; 3210 3211 /* If we're here, then things are most likely 3212 * completely hosed, but if the error condition 3213 * is detected, it won't hurt to give it another 3214 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 3215 */ 3216 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3217 if (hsfsts.hsf_status.flcerr) 3218 /* Repeat for some time before giving up. */ 3219 continue; 3220 if (!hsfsts.hsf_status.flcdone) { 3221 e_dbg("Timeout error - flash cycle did not complete.\n"); 3222 break; 3223 } 3224 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3225 3226 return ret_val; 3227 } 3228 3229 /** 3230 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 3231 * @hw: pointer to the HW structure 3232 * @offset: The index of the byte to read. 3233 * @data: The byte to write to the NVM. 3234 * 3235 * Writes a single byte to the NVM using the flash access registers. 3236 **/ 3237 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3238 u8 data) 3239 { 3240 u16 word = (u16)data; 3241 3242 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 3243 } 3244 3245 /** 3246 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 3247 * @hw: pointer to the HW structure 3248 * @offset: The offset of the byte to write. 3249 * @byte: The byte to write to the NVM. 3250 * 3251 * Writes a single byte to the NVM using the flash access registers. 3252 * Goes through a retry algorithm before giving up. 3253 **/ 3254 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 3255 u32 offset, u8 byte) 3256 { 3257 s32 ret_val; 3258 u16 program_retries; 3259 3260 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3261 if (!ret_val) 3262 return ret_val; 3263 3264 for (program_retries = 0; program_retries < 100; program_retries++) { 3265 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 3266 usleep_range(100, 200); 3267 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3268 if (!ret_val) 3269 break; 3270 } 3271 if (program_retries == 100) 3272 return -E1000_ERR_NVM; 3273 3274 return 0; 3275 } 3276 3277 /** 3278 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 3279 * @hw: pointer to the HW structure 3280 * @bank: 0 for first bank, 1 for second bank, etc. 3281 * 3282 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 3283 * bank N is 4096 * N + flash_reg_addr. 3284 **/ 3285 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 3286 { 3287 struct e1000_nvm_info *nvm = &hw->nvm; 3288 union ich8_hws_flash_status hsfsts; 3289 union ich8_hws_flash_ctrl hsflctl; 3290 u32 flash_linear_addr; 3291 /* bank size is in 16bit words - adjust to bytes */ 3292 u32 flash_bank_size = nvm->flash_bank_size * 2; 3293 s32 ret_val; 3294 s32 count = 0; 3295 s32 j, iteration, sector_size; 3296 3297 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3298 3299 /* Determine HW Sector size: Read BERASE bits of hw flash status 3300 * register 3301 * 00: The Hw sector is 256 bytes, hence we need to erase 16 3302 * consecutive sectors. The start index for the nth Hw sector 3303 * can be calculated as = bank * 4096 + n * 256 3304 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 3305 * The start index for the nth Hw sector can be calculated 3306 * as = bank * 4096 3307 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 3308 * (ich9 only, otherwise error condition) 3309 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 3310 */ 3311 switch (hsfsts.hsf_status.berasesz) { 3312 case 0: 3313 /* Hw sector size 256 */ 3314 sector_size = ICH_FLASH_SEG_SIZE_256; 3315 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 3316 break; 3317 case 1: 3318 sector_size = ICH_FLASH_SEG_SIZE_4K; 3319 iteration = 1; 3320 break; 3321 case 2: 3322 sector_size = ICH_FLASH_SEG_SIZE_8K; 3323 iteration = 1; 3324 break; 3325 case 3: 3326 sector_size = ICH_FLASH_SEG_SIZE_64K; 3327 iteration = 1; 3328 break; 3329 default: 3330 return -E1000_ERR_NVM; 3331 } 3332 3333 /* Start with the base address, then add the sector offset. */ 3334 flash_linear_addr = hw->nvm.flash_base_addr; 3335 flash_linear_addr += (bank) ? flash_bank_size : 0; 3336 3337 for (j = 0; j < iteration; j++) { 3338 do { 3339 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 3340 3341 /* Steps */ 3342 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3343 if (ret_val) 3344 return ret_val; 3345 3346 /* Write a value 11 (block Erase) in Flash 3347 * Cycle field in hw flash control 3348 */ 3349 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3350 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3351 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3352 3353 /* Write the last 24 bits of an index within the 3354 * block into Flash Linear address field in Flash 3355 * Address. 3356 */ 3357 flash_linear_addr += (j * sector_size); 3358 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3359 3360 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 3361 if (!ret_val) 3362 break; 3363 3364 /* Check if FCERR is set to 1. If 1, 3365 * clear it and try the whole sequence 3366 * a few more times else Done 3367 */ 3368 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3369 if (hsfsts.hsf_status.flcerr) 3370 /* repeat for some time before giving up */ 3371 continue; 3372 else if (!hsfsts.hsf_status.flcdone) 3373 return ret_val; 3374 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 3375 } 3376 3377 return 0; 3378 } 3379 3380 /** 3381 * e1000_valid_led_default_ich8lan - Set the default LED settings 3382 * @hw: pointer to the HW structure 3383 * @data: Pointer to the LED settings 3384 * 3385 * Reads the LED default settings from the NVM to data. If the NVM LED 3386 * settings is all 0's or F's, set the LED default to a valid LED default 3387 * setting. 3388 **/ 3389 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 3390 { 3391 s32 ret_val; 3392 3393 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 3394 if (ret_val) { 3395 e_dbg("NVM Read Error\n"); 3396 return ret_val; 3397 } 3398 3399 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 3400 *data = ID_LED_DEFAULT_ICH8LAN; 3401 3402 return 0; 3403 } 3404 3405 /** 3406 * e1000_id_led_init_pchlan - store LED configurations 3407 * @hw: pointer to the HW structure 3408 * 3409 * PCH does not control LEDs via the LEDCTL register, rather it uses 3410 * the PHY LED configuration register. 3411 * 3412 * PCH also does not have an "always on" or "always off" mode which 3413 * complicates the ID feature. Instead of using the "on" mode to indicate 3414 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 3415 * use "link_up" mode. The LEDs will still ID on request if there is no 3416 * link based on logic in e1000_led_[on|off]_pchlan(). 3417 **/ 3418 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 3419 { 3420 struct e1000_mac_info *mac = &hw->mac; 3421 s32 ret_val; 3422 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 3423 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 3424 u16 data, i, temp, shift; 3425 3426 /* Get default ID LED modes */ 3427 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 3428 if (ret_val) 3429 return ret_val; 3430 3431 mac->ledctl_default = er32(LEDCTL); 3432 mac->ledctl_mode1 = mac->ledctl_default; 3433 mac->ledctl_mode2 = mac->ledctl_default; 3434 3435 for (i = 0; i < 4; i++) { 3436 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 3437 shift = (i * 5); 3438 switch (temp) { 3439 case ID_LED_ON1_DEF2: 3440 case ID_LED_ON1_ON2: 3441 case ID_LED_ON1_OFF2: 3442 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3443 mac->ledctl_mode1 |= (ledctl_on << shift); 3444 break; 3445 case ID_LED_OFF1_DEF2: 3446 case ID_LED_OFF1_ON2: 3447 case ID_LED_OFF1_OFF2: 3448 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3449 mac->ledctl_mode1 |= (ledctl_off << shift); 3450 break; 3451 default: 3452 /* Do nothing */ 3453 break; 3454 } 3455 switch (temp) { 3456 case ID_LED_DEF1_ON2: 3457 case ID_LED_ON1_ON2: 3458 case ID_LED_OFF1_ON2: 3459 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3460 mac->ledctl_mode2 |= (ledctl_on << shift); 3461 break; 3462 case ID_LED_DEF1_OFF2: 3463 case ID_LED_ON1_OFF2: 3464 case ID_LED_OFF1_OFF2: 3465 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3466 mac->ledctl_mode2 |= (ledctl_off << shift); 3467 break; 3468 default: 3469 /* Do nothing */ 3470 break; 3471 } 3472 } 3473 3474 return 0; 3475 } 3476 3477 /** 3478 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 3479 * @hw: pointer to the HW structure 3480 * 3481 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 3482 * register, so the the bus width is hard coded. 3483 **/ 3484 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 3485 { 3486 struct e1000_bus_info *bus = &hw->bus; 3487 s32 ret_val; 3488 3489 ret_val = e1000e_get_bus_info_pcie(hw); 3490 3491 /* ICH devices are "PCI Express"-ish. They have 3492 * a configuration space, but do not contain 3493 * PCI Express Capability registers, so bus width 3494 * must be hardcoded. 3495 */ 3496 if (bus->width == e1000_bus_width_unknown) 3497 bus->width = e1000_bus_width_pcie_x1; 3498 3499 return ret_val; 3500 } 3501 3502 /** 3503 * e1000_reset_hw_ich8lan - Reset the hardware 3504 * @hw: pointer to the HW structure 3505 * 3506 * Does a full reset of the hardware which includes a reset of the PHY and 3507 * MAC. 3508 **/ 3509 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 3510 { 3511 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3512 u16 kum_cfg; 3513 u32 ctrl, reg; 3514 s32 ret_val; 3515 3516 /* Prevent the PCI-E bus from sticking if there is no TLP connection 3517 * on the last TLP read/write transaction when MAC is reset. 3518 */ 3519 ret_val = e1000e_disable_pcie_master(hw); 3520 if (ret_val) 3521 e_dbg("PCI-E Master disable polling has failed.\n"); 3522 3523 e_dbg("Masking off all interrupts\n"); 3524 ew32(IMC, 0xffffffff); 3525 3526 /* Disable the Transmit and Receive units. Then delay to allow 3527 * any pending transactions to complete before we hit the MAC 3528 * with the global reset. 3529 */ 3530 ew32(RCTL, 0); 3531 ew32(TCTL, E1000_TCTL_PSP); 3532 e1e_flush(); 3533 3534 usleep_range(10000, 20000); 3535 3536 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 3537 if (hw->mac.type == e1000_ich8lan) { 3538 /* Set Tx and Rx buffer allocation to 8k apiece. */ 3539 ew32(PBA, E1000_PBA_8K); 3540 /* Set Packet Buffer Size to 16k. */ 3541 ew32(PBS, E1000_PBS_16K); 3542 } 3543 3544 if (hw->mac.type == e1000_pchlan) { 3545 /* Save the NVM K1 bit setting */ 3546 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 3547 if (ret_val) 3548 return ret_val; 3549 3550 if (kum_cfg & E1000_NVM_K1_ENABLE) 3551 dev_spec->nvm_k1_enabled = true; 3552 else 3553 dev_spec->nvm_k1_enabled = false; 3554 } 3555 3556 ctrl = er32(CTRL); 3557 3558 if (!hw->phy.ops.check_reset_block(hw)) { 3559 /* Full-chip reset requires MAC and PHY reset at the same 3560 * time to make sure the interface between MAC and the 3561 * external PHY is reset. 3562 */ 3563 ctrl |= E1000_CTRL_PHY_RST; 3564 3565 /* Gate automatic PHY configuration by hardware on 3566 * non-managed 82579 3567 */ 3568 if ((hw->mac.type == e1000_pch2lan) && 3569 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3570 e1000_gate_hw_phy_config_ich8lan(hw, true); 3571 } 3572 ret_val = e1000_acquire_swflag_ich8lan(hw); 3573 e_dbg("Issuing a global reset to ich8lan\n"); 3574 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 3575 /* cannot issue a flush here because it hangs the hardware */ 3576 msleep(20); 3577 3578 /* Set Phy Config Counter to 50msec */ 3579 if (hw->mac.type == e1000_pch2lan) { 3580 reg = er32(FEXTNVM3); 3581 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 3582 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 3583 ew32(FEXTNVM3, reg); 3584 } 3585 3586 if (!ret_val) 3587 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 3588 3589 if (ctrl & E1000_CTRL_PHY_RST) { 3590 ret_val = hw->phy.ops.get_cfg_done(hw); 3591 if (ret_val) 3592 return ret_val; 3593 3594 ret_val = e1000_post_phy_reset_ich8lan(hw); 3595 if (ret_val) 3596 return ret_val; 3597 } 3598 3599 /* For PCH, this write will make sure that any noise 3600 * will be detected as a CRC error and be dropped rather than show up 3601 * as a bad packet to the DMA engine. 3602 */ 3603 if (hw->mac.type == e1000_pchlan) 3604 ew32(CRC_OFFSET, 0x65656565); 3605 3606 ew32(IMC, 0xffffffff); 3607 er32(ICR); 3608 3609 reg = er32(KABGTXD); 3610 reg |= E1000_KABGTXD_BGSQLBIAS; 3611 ew32(KABGTXD, reg); 3612 3613 return 0; 3614 } 3615 3616 /** 3617 * e1000_init_hw_ich8lan - Initialize the hardware 3618 * @hw: pointer to the HW structure 3619 * 3620 * Prepares the hardware for transmit and receive by doing the following: 3621 * - initialize hardware bits 3622 * - initialize LED identification 3623 * - setup receive address registers 3624 * - setup flow control 3625 * - setup transmit descriptors 3626 * - clear statistics 3627 **/ 3628 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3629 { 3630 struct e1000_mac_info *mac = &hw->mac; 3631 u32 ctrl_ext, txdctl, snoop; 3632 s32 ret_val; 3633 u16 i; 3634 3635 e1000_initialize_hw_bits_ich8lan(hw); 3636 3637 /* Initialize identification LED */ 3638 ret_val = mac->ops.id_led_init(hw); 3639 /* An error is not fatal and we should not stop init due to this */ 3640 if (ret_val) 3641 e_dbg("Error initializing identification LED\n"); 3642 3643 /* Setup the receive address. */ 3644 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 3645 3646 /* Zero out the Multicast HASH table */ 3647 e_dbg("Zeroing the MTA\n"); 3648 for (i = 0; i < mac->mta_reg_count; i++) 3649 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3650 3651 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 3652 * the ME. Disable wakeup by clearing the host wakeup bit. 3653 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3654 */ 3655 if (hw->phy.type == e1000_phy_82578) { 3656 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 3657 i &= ~BM_WUC_HOST_WU_BIT; 3658 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 3659 ret_val = e1000_phy_hw_reset_ich8lan(hw); 3660 if (ret_val) 3661 return ret_val; 3662 } 3663 3664 /* Setup link and flow control */ 3665 ret_val = mac->ops.setup_link(hw); 3666 3667 /* Set the transmit descriptor write-back policy for both queues */ 3668 txdctl = er32(TXDCTL(0)); 3669 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 3670 E1000_TXDCTL_FULL_TX_DESC_WB); 3671 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 3672 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 3673 ew32(TXDCTL(0), txdctl); 3674 txdctl = er32(TXDCTL(1)); 3675 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 3676 E1000_TXDCTL_FULL_TX_DESC_WB); 3677 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 3678 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 3679 ew32(TXDCTL(1), txdctl); 3680 3681 /* ICH8 has opposite polarity of no_snoop bits. 3682 * By default, we should use snoop behavior. 3683 */ 3684 if (mac->type == e1000_ich8lan) 3685 snoop = PCIE_ICH8_SNOOP_ALL; 3686 else 3687 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 3688 e1000e_set_pcie_no_snoop(hw, snoop); 3689 3690 ctrl_ext = er32(CTRL_EXT); 3691 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3692 ew32(CTRL_EXT, ctrl_ext); 3693 3694 /* Clear all of the statistics registers (clear on read). It is 3695 * important that we do this after we have tried to establish link 3696 * because the symbol error count will increment wildly if there 3697 * is no link. 3698 */ 3699 e1000_clear_hw_cntrs_ich8lan(hw); 3700 3701 return ret_val; 3702 } 3703 3704 /** 3705 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3706 * @hw: pointer to the HW structure 3707 * 3708 * Sets/Clears required hardware bits necessary for correctly setting up the 3709 * hardware for transmit and receive. 3710 **/ 3711 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3712 { 3713 u32 reg; 3714 3715 /* Extended Device Control */ 3716 reg = er32(CTRL_EXT); 3717 reg |= (1 << 22); 3718 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 3719 if (hw->mac.type >= e1000_pchlan) 3720 reg |= E1000_CTRL_EXT_PHYPDEN; 3721 ew32(CTRL_EXT, reg); 3722 3723 /* Transmit Descriptor Control 0 */ 3724 reg = er32(TXDCTL(0)); 3725 reg |= (1 << 22); 3726 ew32(TXDCTL(0), reg); 3727 3728 /* Transmit Descriptor Control 1 */ 3729 reg = er32(TXDCTL(1)); 3730 reg |= (1 << 22); 3731 ew32(TXDCTL(1), reg); 3732 3733 /* Transmit Arbitration Control 0 */ 3734 reg = er32(TARC(0)); 3735 if (hw->mac.type == e1000_ich8lan) 3736 reg |= (1 << 28) | (1 << 29); 3737 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 3738 ew32(TARC(0), reg); 3739 3740 /* Transmit Arbitration Control 1 */ 3741 reg = er32(TARC(1)); 3742 if (er32(TCTL) & E1000_TCTL_MULR) 3743 reg &= ~(1 << 28); 3744 else 3745 reg |= (1 << 28); 3746 reg |= (1 << 24) | (1 << 26) | (1 << 30); 3747 ew32(TARC(1), reg); 3748 3749 /* Device Status */ 3750 if (hw->mac.type == e1000_ich8lan) { 3751 reg = er32(STATUS); 3752 reg &= ~(1 << 31); 3753 ew32(STATUS, reg); 3754 } 3755 3756 /* work-around descriptor data corruption issue during nfs v2 udp 3757 * traffic, just disable the nfs filtering capability 3758 */ 3759 reg = er32(RFCTL); 3760 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3761 3762 /* Disable IPv6 extension header parsing because some malformed 3763 * IPv6 headers can hang the Rx. 3764 */ 3765 if (hw->mac.type == e1000_ich8lan) 3766 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 3767 ew32(RFCTL, reg); 3768 3769 /* Enable ECC on Lynxpoint */ 3770 if (hw->mac.type == e1000_pch_lpt) { 3771 reg = er32(PBECCSTS); 3772 reg |= E1000_PBECCSTS_ECC_ENABLE; 3773 ew32(PBECCSTS, reg); 3774 3775 reg = er32(CTRL); 3776 reg |= E1000_CTRL_MEHE; 3777 ew32(CTRL, reg); 3778 } 3779 } 3780 3781 /** 3782 * e1000_setup_link_ich8lan - Setup flow control and link settings 3783 * @hw: pointer to the HW structure 3784 * 3785 * Determines which flow control settings to use, then configures flow 3786 * control. Calls the appropriate media-specific link configuration 3787 * function. Assuming the adapter has a valid link partner, a valid link 3788 * should be established. Assumes the hardware has previously been reset 3789 * and the transmitter and receiver are not enabled. 3790 **/ 3791 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 3792 { 3793 s32 ret_val; 3794 3795 if (hw->phy.ops.check_reset_block(hw)) 3796 return 0; 3797 3798 /* ICH parts do not have a word in the NVM to determine 3799 * the default flow control setting, so we explicitly 3800 * set it to full. 3801 */ 3802 if (hw->fc.requested_mode == e1000_fc_default) { 3803 /* Workaround h/w hang when Tx flow control enabled */ 3804 if (hw->mac.type == e1000_pchlan) 3805 hw->fc.requested_mode = e1000_fc_rx_pause; 3806 else 3807 hw->fc.requested_mode = e1000_fc_full; 3808 } 3809 3810 /* Save off the requested flow control mode for use later. Depending 3811 * on the link partner's capabilities, we may or may not use this mode. 3812 */ 3813 hw->fc.current_mode = hw->fc.requested_mode; 3814 3815 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 3816 3817 /* Continue to configure the copper link. */ 3818 ret_val = hw->mac.ops.setup_physical_interface(hw); 3819 if (ret_val) 3820 return ret_val; 3821 3822 ew32(FCTTV, hw->fc.pause_time); 3823 if ((hw->phy.type == e1000_phy_82578) || 3824 (hw->phy.type == e1000_phy_82579) || 3825 (hw->phy.type == e1000_phy_i217) || 3826 (hw->phy.type == e1000_phy_82577)) { 3827 ew32(FCRTV_PCH, hw->fc.refresh_time); 3828 3829 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 3830 hw->fc.pause_time); 3831 if (ret_val) 3832 return ret_val; 3833 } 3834 3835 return e1000e_set_fc_watermarks(hw); 3836 } 3837 3838 /** 3839 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 3840 * @hw: pointer to the HW structure 3841 * 3842 * Configures the kumeran interface to the PHY to wait the appropriate time 3843 * when polling the PHY, then call the generic setup_copper_link to finish 3844 * configuring the copper link. 3845 **/ 3846 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 3847 { 3848 u32 ctrl; 3849 s32 ret_val; 3850 u16 reg_data; 3851 3852 ctrl = er32(CTRL); 3853 ctrl |= E1000_CTRL_SLU; 3854 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3855 ew32(CTRL, ctrl); 3856 3857 /* Set the mac to wait the maximum time between each iteration 3858 * and increase the max iterations when polling the phy; 3859 * this fixes erroneous timeouts at 10Mbps. 3860 */ 3861 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 3862 if (ret_val) 3863 return ret_val; 3864 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3865 ®_data); 3866 if (ret_val) 3867 return ret_val; 3868 reg_data |= 0x3F; 3869 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3870 reg_data); 3871 if (ret_val) 3872 return ret_val; 3873 3874 switch (hw->phy.type) { 3875 case e1000_phy_igp_3: 3876 ret_val = e1000e_copper_link_setup_igp(hw); 3877 if (ret_val) 3878 return ret_val; 3879 break; 3880 case e1000_phy_bm: 3881 case e1000_phy_82578: 3882 ret_val = e1000e_copper_link_setup_m88(hw); 3883 if (ret_val) 3884 return ret_val; 3885 break; 3886 case e1000_phy_82577: 3887 case e1000_phy_82579: 3888 ret_val = e1000_copper_link_setup_82577(hw); 3889 if (ret_val) 3890 return ret_val; 3891 break; 3892 case e1000_phy_ife: 3893 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 3894 if (ret_val) 3895 return ret_val; 3896 3897 reg_data &= ~IFE_PMC_AUTO_MDIX; 3898 3899 switch (hw->phy.mdix) { 3900 case 1: 3901 reg_data &= ~IFE_PMC_FORCE_MDIX; 3902 break; 3903 case 2: 3904 reg_data |= IFE_PMC_FORCE_MDIX; 3905 break; 3906 case 0: 3907 default: 3908 reg_data |= IFE_PMC_AUTO_MDIX; 3909 break; 3910 } 3911 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 3912 if (ret_val) 3913 return ret_val; 3914 break; 3915 default: 3916 break; 3917 } 3918 3919 return e1000e_setup_copper_link(hw); 3920 } 3921 3922 /** 3923 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 3924 * @hw: pointer to the HW structure 3925 * 3926 * Calls the PHY specific link setup function and then calls the 3927 * generic setup_copper_link to finish configuring the link for 3928 * Lynxpoint PCH devices 3929 **/ 3930 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 3931 { 3932 u32 ctrl; 3933 s32 ret_val; 3934 3935 ctrl = er32(CTRL); 3936 ctrl |= E1000_CTRL_SLU; 3937 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3938 ew32(CTRL, ctrl); 3939 3940 ret_val = e1000_copper_link_setup_82577(hw); 3941 if (ret_val) 3942 return ret_val; 3943 3944 return e1000e_setup_copper_link(hw); 3945 } 3946 3947 /** 3948 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 3949 * @hw: pointer to the HW structure 3950 * @speed: pointer to store current link speed 3951 * @duplex: pointer to store the current link duplex 3952 * 3953 * Calls the generic get_speed_and_duplex to retrieve the current link 3954 * information and then calls the Kumeran lock loss workaround for links at 3955 * gigabit speeds. 3956 **/ 3957 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 3958 u16 *duplex) 3959 { 3960 s32 ret_val; 3961 3962 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 3963 if (ret_val) 3964 return ret_val; 3965 3966 if ((hw->mac.type == e1000_ich8lan) && 3967 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 3968 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 3969 } 3970 3971 return ret_val; 3972 } 3973 3974 /** 3975 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 3976 * @hw: pointer to the HW structure 3977 * 3978 * Work-around for 82566 Kumeran PCS lock loss: 3979 * On link status change (i.e. PCI reset, speed change) and link is up and 3980 * speed is gigabit- 3981 * 0) if workaround is optionally disabled do nothing 3982 * 1) wait 1ms for Kumeran link to come up 3983 * 2) check Kumeran Diagnostic register PCS lock loss bit 3984 * 3) if not set the link is locked (all is good), otherwise... 3985 * 4) reset the PHY 3986 * 5) repeat up to 10 times 3987 * Note: this is only called for IGP3 copper when speed is 1gb. 3988 **/ 3989 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3990 { 3991 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3992 u32 phy_ctrl; 3993 s32 ret_val; 3994 u16 i, data; 3995 bool link; 3996 3997 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 3998 return 0; 3999 4000 /* Make sure link is up before proceeding. If not just return. 4001 * Attempting this while link is negotiating fouled up link 4002 * stability 4003 */ 4004 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 4005 if (!link) 4006 return 0; 4007 4008 for (i = 0; i < 10; i++) { 4009 /* read once to clear */ 4010 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 4011 if (ret_val) 4012 return ret_val; 4013 /* and again to get new status */ 4014 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 4015 if (ret_val) 4016 return ret_val; 4017 4018 /* check for PCS lock */ 4019 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 4020 return 0; 4021 4022 /* Issue PHY reset */ 4023 e1000_phy_hw_reset(hw); 4024 mdelay(5); 4025 } 4026 /* Disable GigE link negotiation */ 4027 phy_ctrl = er32(PHY_CTRL); 4028 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 4029 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4030 ew32(PHY_CTRL, phy_ctrl); 4031 4032 /* Call gig speed drop workaround on Gig disable before accessing 4033 * any PHY registers 4034 */ 4035 e1000e_gig_downshift_workaround_ich8lan(hw); 4036 4037 /* unable to acquire PCS lock */ 4038 return -E1000_ERR_PHY; 4039 } 4040 4041 /** 4042 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 4043 * @hw: pointer to the HW structure 4044 * @state: boolean value used to set the current Kumeran workaround state 4045 * 4046 * If ICH8, set the current Kumeran workaround state (enabled - true 4047 * /disabled - false). 4048 **/ 4049 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 4050 bool state) 4051 { 4052 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4053 4054 if (hw->mac.type != e1000_ich8lan) { 4055 e_dbg("Workaround applies to ICH8 only.\n"); 4056 return; 4057 } 4058 4059 dev_spec->kmrn_lock_loss_workaround_enabled = state; 4060 } 4061 4062 /** 4063 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 4064 * @hw: pointer to the HW structure 4065 * 4066 * Workaround for 82566 power-down on D3 entry: 4067 * 1) disable gigabit link 4068 * 2) write VR power-down enable 4069 * 3) read it back 4070 * Continue if successful, else issue LCD reset and repeat 4071 **/ 4072 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 4073 { 4074 u32 reg; 4075 u16 data; 4076 u8 retry = 0; 4077 4078 if (hw->phy.type != e1000_phy_igp_3) 4079 return; 4080 4081 /* Try the workaround twice (if needed) */ 4082 do { 4083 /* Disable link */ 4084 reg = er32(PHY_CTRL); 4085 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 4086 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4087 ew32(PHY_CTRL, reg); 4088 4089 /* Call gig speed drop workaround on Gig disable before 4090 * accessing any PHY registers 4091 */ 4092 if (hw->mac.type == e1000_ich8lan) 4093 e1000e_gig_downshift_workaround_ich8lan(hw); 4094 4095 /* Write VR power-down enable */ 4096 e1e_rphy(hw, IGP3_VR_CTRL, &data); 4097 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 4098 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 4099 4100 /* Read it back and test */ 4101 e1e_rphy(hw, IGP3_VR_CTRL, &data); 4102 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 4103 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 4104 break; 4105 4106 /* Issue PHY reset and repeat at most one more time */ 4107 reg = er32(CTRL); 4108 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 4109 retry++; 4110 } while (retry); 4111 } 4112 4113 /** 4114 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 4115 * @hw: pointer to the HW structure 4116 * 4117 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 4118 * LPLU, Gig disable, MDIC PHY reset): 4119 * 1) Set Kumeran Near-end loopback 4120 * 2) Clear Kumeran Near-end loopback 4121 * Should only be called for ICH8[m] devices with any 1G Phy. 4122 **/ 4123 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 4124 { 4125 s32 ret_val; 4126 u16 reg_data; 4127 4128 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 4129 return; 4130 4131 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 4132 ®_data); 4133 if (ret_val) 4134 return; 4135 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 4136 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 4137 reg_data); 4138 if (ret_val) 4139 return; 4140 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 4141 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 4142 } 4143 4144 /** 4145 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 4146 * @hw: pointer to the HW structure 4147 * 4148 * During S0 to Sx transition, it is possible the link remains at gig 4149 * instead of negotiating to a lower speed. Before going to Sx, set 4150 * 'Gig Disable' to force link speed negotiation to a lower speed based on 4151 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 4152 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 4153 * needs to be written. 4154 * Parts that support (and are linked to a partner which support) EEE in 4155 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 4156 * than 10Mbps w/o EEE. 4157 **/ 4158 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 4159 { 4160 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4161 u32 phy_ctrl; 4162 s32 ret_val; 4163 4164 phy_ctrl = er32(PHY_CTRL); 4165 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 4166 4167 if (hw->phy.type == e1000_phy_i217) { 4168 u16 phy_reg, device_id = hw->adapter->pdev->device; 4169 4170 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4171 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) { 4172 u32 fextnvm6 = er32(FEXTNVM6); 4173 4174 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 4175 } 4176 4177 ret_val = hw->phy.ops.acquire(hw); 4178 if (ret_val) 4179 goto out; 4180 4181 if (!dev_spec->eee_disable) { 4182 u16 eee_advert; 4183 4184 ret_val = 4185 e1000_read_emi_reg_locked(hw, 4186 I217_EEE_ADVERTISEMENT, 4187 &eee_advert); 4188 if (ret_val) 4189 goto release; 4190 4191 /* Disable LPLU if both link partners support 100BaseT 4192 * EEE and 100Full is advertised on both ends of the 4193 * link. 4194 */ 4195 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 4196 (dev_spec->eee_lp_ability & 4197 I82579_EEE_100_SUPPORTED) && 4198 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) 4199 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 4200 E1000_PHY_CTRL_NOND0A_LPLU); 4201 } 4202 4203 /* For i217 Intel Rapid Start Technology support, 4204 * when the system is going into Sx and no manageability engine 4205 * is present, the driver must configure proxy to reset only on 4206 * power good. LPI (Low Power Idle) state must also reset only 4207 * on power good, as well as the MTA (Multicast table array). 4208 * The SMBus release must also be disabled on LCD reset. 4209 */ 4210 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 4211 /* Enable proxy to reset only on power good. */ 4212 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 4213 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 4214 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 4215 4216 /* Set bit enable LPI (EEE) to reset only on 4217 * power good. 4218 */ 4219 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 4220 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 4221 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 4222 4223 /* Disable the SMB release on LCD reset. */ 4224 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 4225 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 4226 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 4227 } 4228 4229 /* Enable MTA to reset for Intel Rapid Start Technology 4230 * Support 4231 */ 4232 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 4233 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 4234 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 4235 4236 release: 4237 hw->phy.ops.release(hw); 4238 } 4239 out: 4240 ew32(PHY_CTRL, phy_ctrl); 4241 4242 if (hw->mac.type == e1000_ich8lan) 4243 e1000e_gig_downshift_workaround_ich8lan(hw); 4244 4245 if (hw->mac.type >= e1000_pchlan) { 4246 e1000_oem_bits_config_ich8lan(hw, false); 4247 4248 /* Reset PHY to activate OEM bits on 82577/8 */ 4249 if (hw->mac.type == e1000_pchlan) 4250 e1000e_phy_hw_reset_generic(hw); 4251 4252 ret_val = hw->phy.ops.acquire(hw); 4253 if (ret_val) 4254 return; 4255 e1000_write_smbus_addr(hw); 4256 hw->phy.ops.release(hw); 4257 } 4258 } 4259 4260 /** 4261 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 4262 * @hw: pointer to the HW structure 4263 * 4264 * During Sx to S0 transitions on non-managed devices or managed devices 4265 * on which PHY resets are not blocked, if the PHY registers cannot be 4266 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 4267 * the PHY. 4268 * On i217, setup Intel Rapid Start Technology. 4269 **/ 4270 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 4271 { 4272 s32 ret_val; 4273 4274 if (hw->mac.type < e1000_pch2lan) 4275 return; 4276 4277 ret_val = e1000_init_phy_workarounds_pchlan(hw); 4278 if (ret_val) { 4279 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 4280 return; 4281 } 4282 4283 /* For i217 Intel Rapid Start Technology support when the system 4284 * is transitioning from Sx and no manageability engine is present 4285 * configure SMBus to restore on reset, disable proxy, and enable 4286 * the reset on MTA (Multicast table array). 4287 */ 4288 if (hw->phy.type == e1000_phy_i217) { 4289 u16 phy_reg; 4290 4291 ret_val = hw->phy.ops.acquire(hw); 4292 if (ret_val) { 4293 e_dbg("Failed to setup iRST\n"); 4294 return; 4295 } 4296 4297 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 4298 /* Restore clear on SMB if no manageability engine 4299 * is present 4300 */ 4301 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 4302 if (ret_val) 4303 goto release; 4304 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 4305 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 4306 4307 /* Disable Proxy */ 4308 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 4309 } 4310 /* Enable reset on MTA */ 4311 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 4312 if (ret_val) 4313 goto release; 4314 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 4315 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 4316 release: 4317 if (ret_val) 4318 e_dbg("Error %d in resume workarounds\n", ret_val); 4319 hw->phy.ops.release(hw); 4320 } 4321 } 4322 4323 /** 4324 * e1000_cleanup_led_ich8lan - Restore the default LED operation 4325 * @hw: pointer to the HW structure 4326 * 4327 * Return the LED back to the default configuration. 4328 **/ 4329 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 4330 { 4331 if (hw->phy.type == e1000_phy_ife) 4332 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 4333 4334 ew32(LEDCTL, hw->mac.ledctl_default); 4335 return 0; 4336 } 4337 4338 /** 4339 * e1000_led_on_ich8lan - Turn LEDs on 4340 * @hw: pointer to the HW structure 4341 * 4342 * Turn on the LEDs. 4343 **/ 4344 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 4345 { 4346 if (hw->phy.type == e1000_phy_ife) 4347 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4348 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 4349 4350 ew32(LEDCTL, hw->mac.ledctl_mode2); 4351 return 0; 4352 } 4353 4354 /** 4355 * e1000_led_off_ich8lan - Turn LEDs off 4356 * @hw: pointer to the HW structure 4357 * 4358 * Turn off the LEDs. 4359 **/ 4360 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 4361 { 4362 if (hw->phy.type == e1000_phy_ife) 4363 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4364 (IFE_PSCL_PROBE_MODE | 4365 IFE_PSCL_PROBE_LEDS_OFF)); 4366 4367 ew32(LEDCTL, hw->mac.ledctl_mode1); 4368 return 0; 4369 } 4370 4371 /** 4372 * e1000_setup_led_pchlan - Configures SW controllable LED 4373 * @hw: pointer to the HW structure 4374 * 4375 * This prepares the SW controllable LED for use. 4376 **/ 4377 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 4378 { 4379 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 4380 } 4381 4382 /** 4383 * e1000_cleanup_led_pchlan - Restore the default LED operation 4384 * @hw: pointer to the HW structure 4385 * 4386 * Return the LED back to the default configuration. 4387 **/ 4388 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 4389 { 4390 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 4391 } 4392 4393 /** 4394 * e1000_led_on_pchlan - Turn LEDs on 4395 * @hw: pointer to the HW structure 4396 * 4397 * Turn on the LEDs. 4398 **/ 4399 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 4400 { 4401 u16 data = (u16)hw->mac.ledctl_mode2; 4402 u32 i, led; 4403 4404 /* If no link, then turn LED on by setting the invert bit 4405 * for each LED that's mode is "link_up" in ledctl_mode2. 4406 */ 4407 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4408 for (i = 0; i < 3; i++) { 4409 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4410 if ((led & E1000_PHY_LED0_MODE_MASK) != 4411 E1000_LEDCTL_MODE_LINK_UP) 4412 continue; 4413 if (led & E1000_PHY_LED0_IVRT) 4414 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4415 else 4416 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4417 } 4418 } 4419 4420 return e1e_wphy(hw, HV_LED_CONFIG, data); 4421 } 4422 4423 /** 4424 * e1000_led_off_pchlan - Turn LEDs off 4425 * @hw: pointer to the HW structure 4426 * 4427 * Turn off the LEDs. 4428 **/ 4429 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 4430 { 4431 u16 data = (u16)hw->mac.ledctl_mode1; 4432 u32 i, led; 4433 4434 /* If no link, then turn LED off by clearing the invert bit 4435 * for each LED that's mode is "link_up" in ledctl_mode1. 4436 */ 4437 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4438 for (i = 0; i < 3; i++) { 4439 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4440 if ((led & E1000_PHY_LED0_MODE_MASK) != 4441 E1000_LEDCTL_MODE_LINK_UP) 4442 continue; 4443 if (led & E1000_PHY_LED0_IVRT) 4444 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4445 else 4446 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4447 } 4448 } 4449 4450 return e1e_wphy(hw, HV_LED_CONFIG, data); 4451 } 4452 4453 /** 4454 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 4455 * @hw: pointer to the HW structure 4456 * 4457 * Read appropriate register for the config done bit for completion status 4458 * and configure the PHY through s/w for EEPROM-less parts. 4459 * 4460 * NOTE: some silicon which is EEPROM-less will fail trying to read the 4461 * config done bit, so only an error is logged and continues. If we were 4462 * to return with error, EEPROM-less silicon would not be able to be reset 4463 * or change link. 4464 **/ 4465 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 4466 { 4467 s32 ret_val = 0; 4468 u32 bank = 0; 4469 u32 status; 4470 4471 e1000e_get_cfg_done_generic(hw); 4472 4473 /* Wait for indication from h/w that it has completed basic config */ 4474 if (hw->mac.type >= e1000_ich10lan) { 4475 e1000_lan_init_done_ich8lan(hw); 4476 } else { 4477 ret_val = e1000e_get_auto_rd_done(hw); 4478 if (ret_val) { 4479 /* When auto config read does not complete, do not 4480 * return with an error. This can happen in situations 4481 * where there is no eeprom and prevents getting link. 4482 */ 4483 e_dbg("Auto Read Done did not complete\n"); 4484 ret_val = 0; 4485 } 4486 } 4487 4488 /* Clear PHY Reset Asserted bit */ 4489 status = er32(STATUS); 4490 if (status & E1000_STATUS_PHYRA) 4491 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 4492 else 4493 e_dbg("PHY Reset Asserted not set - needs delay\n"); 4494 4495 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 4496 if (hw->mac.type <= e1000_ich9lan) { 4497 if (!(er32(EECD) & E1000_EECD_PRES) && 4498 (hw->phy.type == e1000_phy_igp_3)) { 4499 e1000e_phy_init_script_igp3(hw); 4500 } 4501 } else { 4502 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 4503 /* Maybe we should do a basic PHY config */ 4504 e_dbg("EEPROM not present\n"); 4505 ret_val = -E1000_ERR_CONFIG; 4506 } 4507 } 4508 4509 return ret_val; 4510 } 4511 4512 /** 4513 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 4514 * @hw: pointer to the HW structure 4515 * 4516 * In the case of a PHY power down to save power, or to turn off link during a 4517 * driver unload, or wake on lan is not enabled, remove the link. 4518 **/ 4519 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 4520 { 4521 /* If the management interface is not enabled, then power down */ 4522 if (!(hw->mac.ops.check_mng_mode(hw) || 4523 hw->phy.ops.check_reset_block(hw))) 4524 e1000_power_down_phy_copper(hw); 4525 } 4526 4527 /** 4528 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 4529 * @hw: pointer to the HW structure 4530 * 4531 * Clears hardware counters specific to the silicon family and calls 4532 * clear_hw_cntrs_generic to clear all general purpose counters. 4533 **/ 4534 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 4535 { 4536 u16 phy_data; 4537 s32 ret_val; 4538 4539 e1000e_clear_hw_cntrs_base(hw); 4540 4541 er32(ALGNERRC); 4542 er32(RXERRC); 4543 er32(TNCRS); 4544 er32(CEXTERR); 4545 er32(TSCTC); 4546 er32(TSCTFC); 4547 4548 er32(MGTPRC); 4549 er32(MGTPDC); 4550 er32(MGTPTC); 4551 4552 er32(IAC); 4553 er32(ICRXOC); 4554 4555 /* Clear PHY statistics registers */ 4556 if ((hw->phy.type == e1000_phy_82578) || 4557 (hw->phy.type == e1000_phy_82579) || 4558 (hw->phy.type == e1000_phy_i217) || 4559 (hw->phy.type == e1000_phy_82577)) { 4560 ret_val = hw->phy.ops.acquire(hw); 4561 if (ret_val) 4562 return; 4563 ret_val = hw->phy.ops.set_page(hw, 4564 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4565 if (ret_val) 4566 goto release; 4567 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4568 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4569 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4570 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4571 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4572 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4573 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4574 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4575 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4576 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4577 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4578 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4579 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4580 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4581 release: 4582 hw->phy.ops.release(hw); 4583 } 4584 } 4585 4586 static const struct e1000_mac_operations ich8_mac_ops = { 4587 /* check_mng_mode dependent on mac type */ 4588 .check_for_link = e1000_check_for_copper_link_ich8lan, 4589 /* cleanup_led dependent on mac type */ 4590 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 4591 .get_bus_info = e1000_get_bus_info_ich8lan, 4592 .set_lan_id = e1000_set_lan_id_single_port, 4593 .get_link_up_info = e1000_get_link_up_info_ich8lan, 4594 /* led_on dependent on mac type */ 4595 /* led_off dependent on mac type */ 4596 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 4597 .reset_hw = e1000_reset_hw_ich8lan, 4598 .init_hw = e1000_init_hw_ich8lan, 4599 .setup_link = e1000_setup_link_ich8lan, 4600 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 4601 /* id_led_init dependent on mac type */ 4602 .config_collision_dist = e1000e_config_collision_dist_generic, 4603 .rar_set = e1000e_rar_set_generic, 4604 }; 4605 4606 static const struct e1000_phy_operations ich8_phy_ops = { 4607 .acquire = e1000_acquire_swflag_ich8lan, 4608 .check_reset_block = e1000_check_reset_block_ich8lan, 4609 .commit = NULL, 4610 .get_cfg_done = e1000_get_cfg_done_ich8lan, 4611 .get_cable_length = e1000e_get_cable_length_igp_2, 4612 .read_reg = e1000e_read_phy_reg_igp, 4613 .release = e1000_release_swflag_ich8lan, 4614 .reset = e1000_phy_hw_reset_ich8lan, 4615 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 4616 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 4617 .write_reg = e1000e_write_phy_reg_igp, 4618 }; 4619 4620 static const struct e1000_nvm_operations ich8_nvm_ops = { 4621 .acquire = e1000_acquire_nvm_ich8lan, 4622 .read = e1000_read_nvm_ich8lan, 4623 .release = e1000_release_nvm_ich8lan, 4624 .reload = e1000e_reload_nvm_generic, 4625 .update = e1000_update_nvm_checksum_ich8lan, 4626 .valid_led_default = e1000_valid_led_default_ich8lan, 4627 .validate = e1000_validate_nvm_checksum_ich8lan, 4628 .write = e1000_write_nvm_ich8lan, 4629 }; 4630 4631 const struct e1000_info e1000_ich8_info = { 4632 .mac = e1000_ich8lan, 4633 .flags = FLAG_HAS_WOL 4634 | FLAG_IS_ICH 4635 | FLAG_HAS_CTRLEXT_ON_LOAD 4636 | FLAG_HAS_AMT 4637 | FLAG_HAS_FLASH 4638 | FLAG_APME_IN_WUC, 4639 .pba = 8, 4640 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 4641 .get_variants = e1000_get_variants_ich8lan, 4642 .mac_ops = &ich8_mac_ops, 4643 .phy_ops = &ich8_phy_ops, 4644 .nvm_ops = &ich8_nvm_ops, 4645 }; 4646 4647 const struct e1000_info e1000_ich9_info = { 4648 .mac = e1000_ich9lan, 4649 .flags = FLAG_HAS_JUMBO_FRAMES 4650 | FLAG_IS_ICH 4651 | FLAG_HAS_WOL 4652 | FLAG_HAS_CTRLEXT_ON_LOAD 4653 | FLAG_HAS_AMT 4654 | FLAG_HAS_FLASH 4655 | FLAG_APME_IN_WUC, 4656 .pba = 18, 4657 .max_hw_frame_size = DEFAULT_JUMBO, 4658 .get_variants = e1000_get_variants_ich8lan, 4659 .mac_ops = &ich8_mac_ops, 4660 .phy_ops = &ich8_phy_ops, 4661 .nvm_ops = &ich8_nvm_ops, 4662 }; 4663 4664 const struct e1000_info e1000_ich10_info = { 4665 .mac = e1000_ich10lan, 4666 .flags = FLAG_HAS_JUMBO_FRAMES 4667 | FLAG_IS_ICH 4668 | FLAG_HAS_WOL 4669 | FLAG_HAS_CTRLEXT_ON_LOAD 4670 | FLAG_HAS_AMT 4671 | FLAG_HAS_FLASH 4672 | FLAG_APME_IN_WUC, 4673 .pba = 18, 4674 .max_hw_frame_size = DEFAULT_JUMBO, 4675 .get_variants = e1000_get_variants_ich8lan, 4676 .mac_ops = &ich8_mac_ops, 4677 .phy_ops = &ich8_phy_ops, 4678 .nvm_ops = &ich8_nvm_ops, 4679 }; 4680 4681 const struct e1000_info e1000_pch_info = { 4682 .mac = e1000_pchlan, 4683 .flags = FLAG_IS_ICH 4684 | FLAG_HAS_WOL 4685 | FLAG_HAS_CTRLEXT_ON_LOAD 4686 | FLAG_HAS_AMT 4687 | FLAG_HAS_FLASH 4688 | FLAG_HAS_JUMBO_FRAMES 4689 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 4690 | FLAG_APME_IN_WUC, 4691 .flags2 = FLAG2_HAS_PHY_STATS, 4692 .pba = 26, 4693 .max_hw_frame_size = 4096, 4694 .get_variants = e1000_get_variants_ich8lan, 4695 .mac_ops = &ich8_mac_ops, 4696 .phy_ops = &ich8_phy_ops, 4697 .nvm_ops = &ich8_nvm_ops, 4698 }; 4699 4700 const struct e1000_info e1000_pch2_info = { 4701 .mac = e1000_pch2lan, 4702 .flags = FLAG_IS_ICH 4703 | FLAG_HAS_WOL 4704 | FLAG_HAS_HW_TIMESTAMP 4705 | FLAG_HAS_CTRLEXT_ON_LOAD 4706 | FLAG_HAS_AMT 4707 | FLAG_HAS_FLASH 4708 | FLAG_HAS_JUMBO_FRAMES 4709 | FLAG_APME_IN_WUC, 4710 .flags2 = FLAG2_HAS_PHY_STATS 4711 | FLAG2_HAS_EEE, 4712 .pba = 26, 4713 .max_hw_frame_size = 9018, 4714 .get_variants = e1000_get_variants_ich8lan, 4715 .mac_ops = &ich8_mac_ops, 4716 .phy_ops = &ich8_phy_ops, 4717 .nvm_ops = &ich8_nvm_ops, 4718 }; 4719 4720 const struct e1000_info e1000_pch_lpt_info = { 4721 .mac = e1000_pch_lpt, 4722 .flags = FLAG_IS_ICH 4723 | FLAG_HAS_WOL 4724 | FLAG_HAS_HW_TIMESTAMP 4725 | FLAG_HAS_CTRLEXT_ON_LOAD 4726 | FLAG_HAS_AMT 4727 | FLAG_HAS_FLASH 4728 | FLAG_HAS_JUMBO_FRAMES 4729 | FLAG_APME_IN_WUC, 4730 .flags2 = FLAG2_HAS_PHY_STATS 4731 | FLAG2_HAS_EEE, 4732 .pba = 26, 4733 .max_hw_frame_size = 9018, 4734 .get_variants = e1000_get_variants_ich8lan, 4735 .mac_ops = &ich8_mac_ops, 4736 .phy_ops = &ich8_phy_ops, 4737 .nvm_ops = &ich8_nvm_ops, 4738 }; 4739