1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Unforce SMBus mode in PHY */ 226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 229 230 /* Unforce SMBus mode in MAC */ 231 mac_reg = er32(CTRL_EXT); 232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 233 ew32(CTRL_EXT, mac_reg); 234 } 235 } 236 237 return true; 238 } 239 240 /** 241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 242 * @hw: pointer to the HW structure 243 * 244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 245 * used to reset the PHY to a quiescent state when necessary. 246 **/ 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 248 { 249 u32 mac_reg; 250 251 /* Set Phy Config Counter to 50msec */ 252 mac_reg = er32(FEXTNVM3); 253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 255 ew32(FEXTNVM3, mac_reg); 256 257 /* Toggle LANPHYPC Value bit */ 258 mac_reg = er32(CTRL); 259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 261 ew32(CTRL, mac_reg); 262 e1e_flush(); 263 usleep_range(10, 20); 264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 265 ew32(CTRL, mac_reg); 266 e1e_flush(); 267 268 if (hw->mac.type < e1000_pch_lpt) { 269 msleep(50); 270 } else { 271 u16 count = 20; 272 273 do { 274 usleep_range(5000, 6000); 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 276 277 msleep(30); 278 } 279 } 280 281 /** 282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 283 * @hw: pointer to the HW structure 284 * 285 * Workarounds/flow necessary for PHY initialization during driver load 286 * and resume paths. 287 **/ 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 289 { 290 struct e1000_adapter *adapter = hw->adapter; 291 u32 mac_reg, fwsm = er32(FWSM); 292 s32 ret_val; 293 294 /* Gate automatic PHY configuration by hardware on managed and 295 * non-managed 82579 and newer adapters. 296 */ 297 e1000_gate_hw_phy_config_ich8lan(hw, true); 298 299 /* It is not possible to be certain of the current state of ULP 300 * so forcibly disable it. 301 */ 302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 303 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 304 if (ret_val) 305 e_warn("Failed to disable ULP\n"); 306 307 ret_val = hw->phy.ops.acquire(hw); 308 if (ret_val) { 309 e_dbg("Failed to initialize PHY flow\n"); 310 goto out; 311 } 312 313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 314 * inaccessible and resetting the PHY is not blocked, toggle the 315 * LANPHYPC Value bit to force the interconnect to PCIe mode. 316 */ 317 switch (hw->mac.type) { 318 case e1000_pch_lpt: 319 case e1000_pch_spt: 320 case e1000_pch_cnp: 321 case e1000_pch_tgp: 322 case e1000_pch_adp: 323 case e1000_pch_mtp: 324 case e1000_pch_lnp: 325 if (e1000_phy_is_accessible_pchlan(hw)) 326 break; 327 328 /* Before toggling LANPHYPC, see if PHY is accessible by 329 * forcing MAC to SMBus mode first. 330 */ 331 mac_reg = er32(CTRL_EXT); 332 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 333 ew32(CTRL_EXT, mac_reg); 334 335 /* Wait 50 milliseconds for MAC to finish any retries 336 * that it might be trying to perform from previous 337 * attempts to acknowledge any phy read requests. 338 */ 339 msleep(50); 340 341 fallthrough; 342 case e1000_pch2lan: 343 if (e1000_phy_is_accessible_pchlan(hw)) 344 break; 345 346 fallthrough; 347 case e1000_pchlan: 348 if ((hw->mac.type == e1000_pchlan) && 349 (fwsm & E1000_ICH_FWSM_FW_VALID)) 350 break; 351 352 if (hw->phy.ops.check_reset_block(hw)) { 353 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 354 ret_val = -E1000_ERR_PHY; 355 break; 356 } 357 358 /* Toggle LANPHYPC Value bit */ 359 e1000_toggle_lanphypc_pch_lpt(hw); 360 if (hw->mac.type >= e1000_pch_lpt) { 361 if (e1000_phy_is_accessible_pchlan(hw)) 362 break; 363 364 /* Toggling LANPHYPC brings the PHY out of SMBus mode 365 * so ensure that the MAC is also out of SMBus mode 366 */ 367 mac_reg = er32(CTRL_EXT); 368 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 369 ew32(CTRL_EXT, mac_reg); 370 371 if (e1000_phy_is_accessible_pchlan(hw)) 372 break; 373 374 ret_val = -E1000_ERR_PHY; 375 } 376 break; 377 default: 378 break; 379 } 380 381 hw->phy.ops.release(hw); 382 if (!ret_val) { 383 384 /* Check to see if able to reset PHY. Print error if not */ 385 if (hw->phy.ops.check_reset_block(hw)) { 386 e_err("Reset blocked by ME\n"); 387 goto out; 388 } 389 390 /* Reset the PHY before any access to it. Doing so, ensures 391 * that the PHY is in a known good state before we read/write 392 * PHY registers. The generic reset is sufficient here, 393 * because we haven't determined the PHY type yet. 394 */ 395 ret_val = e1000e_phy_hw_reset_generic(hw); 396 if (ret_val) 397 goto out; 398 399 /* On a successful reset, possibly need to wait for the PHY 400 * to quiesce to an accessible state before returning control 401 * to the calling function. If the PHY does not quiesce, then 402 * return E1000E_BLK_PHY_RESET, as this is the condition that 403 * the PHY is in. 404 */ 405 ret_val = hw->phy.ops.check_reset_block(hw); 406 if (ret_val) 407 e_err("ME blocked access to PHY after reset\n"); 408 } 409 410 out: 411 /* Ungate automatic PHY configuration on non-managed 82579 */ 412 if ((hw->mac.type == e1000_pch2lan) && 413 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 414 usleep_range(10000, 11000); 415 e1000_gate_hw_phy_config_ich8lan(hw, false); 416 } 417 418 return ret_val; 419 } 420 421 /** 422 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 423 * @hw: pointer to the HW structure 424 * 425 * Initialize family-specific PHY parameters and function pointers. 426 **/ 427 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 428 { 429 struct e1000_phy_info *phy = &hw->phy; 430 s32 ret_val; 431 432 phy->addr = 1; 433 phy->reset_delay_us = 100; 434 435 phy->ops.set_page = e1000_set_page_igp; 436 phy->ops.read_reg = e1000_read_phy_reg_hv; 437 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 438 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 439 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 440 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 441 phy->ops.write_reg = e1000_write_phy_reg_hv; 442 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 443 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 444 phy->ops.power_up = e1000_power_up_phy_copper; 445 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 446 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 447 448 phy->id = e1000_phy_unknown; 449 450 ret_val = e1000_init_phy_workarounds_pchlan(hw); 451 if (ret_val) 452 return ret_val; 453 454 if (phy->id == e1000_phy_unknown) 455 switch (hw->mac.type) { 456 default: 457 ret_val = e1000e_get_phy_id(hw); 458 if (ret_val) 459 return ret_val; 460 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 461 break; 462 fallthrough; 463 case e1000_pch2lan: 464 case e1000_pch_lpt: 465 case e1000_pch_spt: 466 case e1000_pch_cnp: 467 case e1000_pch_tgp: 468 case e1000_pch_adp: 469 case e1000_pch_mtp: 470 case e1000_pch_lnp: 471 /* In case the PHY needs to be in mdio slow mode, 472 * set slow mode and try to get the PHY id again. 473 */ 474 ret_val = e1000_set_mdio_slow_mode_hv(hw); 475 if (ret_val) 476 return ret_val; 477 ret_val = e1000e_get_phy_id(hw); 478 if (ret_val) 479 return ret_val; 480 break; 481 } 482 phy->type = e1000e_get_phy_type_from_id(phy->id); 483 484 switch (phy->type) { 485 case e1000_phy_82577: 486 case e1000_phy_82579: 487 case e1000_phy_i217: 488 phy->ops.check_polarity = e1000_check_polarity_82577; 489 phy->ops.force_speed_duplex = 490 e1000_phy_force_speed_duplex_82577; 491 phy->ops.get_cable_length = e1000_get_cable_length_82577; 492 phy->ops.get_info = e1000_get_phy_info_82577; 493 phy->ops.commit = e1000e_phy_sw_reset; 494 break; 495 case e1000_phy_82578: 496 phy->ops.check_polarity = e1000_check_polarity_m88; 497 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 498 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 499 phy->ops.get_info = e1000e_get_phy_info_m88; 500 break; 501 default: 502 ret_val = -E1000_ERR_PHY; 503 break; 504 } 505 506 return ret_val; 507 } 508 509 /** 510 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 511 * @hw: pointer to the HW structure 512 * 513 * Initialize family-specific PHY parameters and function pointers. 514 **/ 515 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 516 { 517 struct e1000_phy_info *phy = &hw->phy; 518 s32 ret_val; 519 u16 i = 0; 520 521 phy->addr = 1; 522 phy->reset_delay_us = 100; 523 524 phy->ops.power_up = e1000_power_up_phy_copper; 525 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 526 527 /* We may need to do this twice - once for IGP and if that fails, 528 * we'll set BM func pointers and try again 529 */ 530 ret_val = e1000e_determine_phy_address(hw); 531 if (ret_val) { 532 phy->ops.write_reg = e1000e_write_phy_reg_bm; 533 phy->ops.read_reg = e1000e_read_phy_reg_bm; 534 ret_val = e1000e_determine_phy_address(hw); 535 if (ret_val) { 536 e_dbg("Cannot determine PHY addr. Erroring out\n"); 537 return ret_val; 538 } 539 } 540 541 phy->id = 0; 542 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 543 (i++ < 100)) { 544 usleep_range(1000, 1100); 545 ret_val = e1000e_get_phy_id(hw); 546 if (ret_val) 547 return ret_val; 548 } 549 550 /* Verify phy id */ 551 switch (phy->id) { 552 case IGP03E1000_E_PHY_ID: 553 phy->type = e1000_phy_igp_3; 554 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 555 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 556 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 557 phy->ops.get_info = e1000e_get_phy_info_igp; 558 phy->ops.check_polarity = e1000_check_polarity_igp; 559 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 560 break; 561 case IFE_E_PHY_ID: 562 case IFE_PLUS_E_PHY_ID: 563 case IFE_C_E_PHY_ID: 564 phy->type = e1000_phy_ife; 565 phy->autoneg_mask = E1000_ALL_NOT_GIG; 566 phy->ops.get_info = e1000_get_phy_info_ife; 567 phy->ops.check_polarity = e1000_check_polarity_ife; 568 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 569 break; 570 case BME1000_E_PHY_ID: 571 phy->type = e1000_phy_bm; 572 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 573 phy->ops.read_reg = e1000e_read_phy_reg_bm; 574 phy->ops.write_reg = e1000e_write_phy_reg_bm; 575 phy->ops.commit = e1000e_phy_sw_reset; 576 phy->ops.get_info = e1000e_get_phy_info_m88; 577 phy->ops.check_polarity = e1000_check_polarity_m88; 578 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 579 break; 580 default: 581 return -E1000_ERR_PHY; 582 } 583 584 return 0; 585 } 586 587 /** 588 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 589 * @hw: pointer to the HW structure 590 * 591 * Initialize family-specific NVM parameters and function 592 * pointers. 593 **/ 594 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 595 { 596 struct e1000_nvm_info *nvm = &hw->nvm; 597 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 598 u32 gfpreg, sector_base_addr, sector_end_addr; 599 u16 i; 600 u32 nvm_size; 601 602 nvm->type = e1000_nvm_flash_sw; 603 604 if (hw->mac.type >= e1000_pch_spt) { 605 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 606 * STRAP register. This is because in SPT the GbE Flash region 607 * is no longer accessed through the flash registers. Instead, 608 * the mechanism has changed, and the Flash region access 609 * registers are now implemented in GbE memory space. 610 */ 611 nvm->flash_base_addr = 0; 612 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 613 * NVM_SIZE_MULTIPLIER; 614 nvm->flash_bank_size = nvm_size / 2; 615 /* Adjust to word count */ 616 nvm->flash_bank_size /= sizeof(u16); 617 /* Set the base address for flash register access */ 618 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 619 } else { 620 /* Can't read flash registers if register set isn't mapped. */ 621 if (!hw->flash_address) { 622 e_dbg("ERROR: Flash registers not mapped\n"); 623 return -E1000_ERR_CONFIG; 624 } 625 626 gfpreg = er32flash(ICH_FLASH_GFPREG); 627 628 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 629 * Add 1 to sector_end_addr since this sector is included in 630 * the overall size. 631 */ 632 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 633 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 634 635 /* flash_base_addr is byte-aligned */ 636 nvm->flash_base_addr = sector_base_addr 637 << FLASH_SECTOR_ADDR_SHIFT; 638 639 /* find total size of the NVM, then cut in half since the total 640 * size represents two separate NVM banks. 641 */ 642 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 643 << FLASH_SECTOR_ADDR_SHIFT); 644 nvm->flash_bank_size /= 2; 645 /* Adjust to word count */ 646 nvm->flash_bank_size /= sizeof(u16); 647 } 648 649 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 650 651 /* Clear shadow ram */ 652 for (i = 0; i < nvm->word_size; i++) { 653 dev_spec->shadow_ram[i].modified = false; 654 dev_spec->shadow_ram[i].value = 0xFFFF; 655 } 656 657 return 0; 658 } 659 660 /** 661 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 662 * @hw: pointer to the HW structure 663 * 664 * Initialize family-specific MAC parameters and function 665 * pointers. 666 **/ 667 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 668 { 669 struct e1000_mac_info *mac = &hw->mac; 670 671 /* Set media type function pointer */ 672 hw->phy.media_type = e1000_media_type_copper; 673 674 /* Set mta register count */ 675 mac->mta_reg_count = 32; 676 /* Set rar entry count */ 677 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 678 if (mac->type == e1000_ich8lan) 679 mac->rar_entry_count--; 680 /* FWSM register */ 681 mac->has_fwsm = true; 682 /* ARC subsystem not supported */ 683 mac->arc_subsystem_valid = false; 684 /* Adaptive IFS supported */ 685 mac->adaptive_ifs = true; 686 687 /* LED and other operations */ 688 switch (mac->type) { 689 case e1000_ich8lan: 690 case e1000_ich9lan: 691 case e1000_ich10lan: 692 /* check management mode */ 693 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 694 /* ID LED init */ 695 mac->ops.id_led_init = e1000e_id_led_init_generic; 696 /* blink LED */ 697 mac->ops.blink_led = e1000e_blink_led_generic; 698 /* setup LED */ 699 mac->ops.setup_led = e1000e_setup_led_generic; 700 /* cleanup LED */ 701 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 702 /* turn on/off LED */ 703 mac->ops.led_on = e1000_led_on_ich8lan; 704 mac->ops.led_off = e1000_led_off_ich8lan; 705 break; 706 case e1000_pch2lan: 707 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 708 mac->ops.rar_set = e1000_rar_set_pch2lan; 709 fallthrough; 710 case e1000_pch_lpt: 711 case e1000_pch_spt: 712 case e1000_pch_cnp: 713 case e1000_pch_tgp: 714 case e1000_pch_adp: 715 case e1000_pch_mtp: 716 case e1000_pch_lnp: 717 case e1000_pchlan: 718 /* check management mode */ 719 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 720 /* ID LED init */ 721 mac->ops.id_led_init = e1000_id_led_init_pchlan; 722 /* setup LED */ 723 mac->ops.setup_led = e1000_setup_led_pchlan; 724 /* cleanup LED */ 725 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 726 /* turn on/off LED */ 727 mac->ops.led_on = e1000_led_on_pchlan; 728 mac->ops.led_off = e1000_led_off_pchlan; 729 break; 730 default: 731 break; 732 } 733 734 if (mac->type >= e1000_pch_lpt) { 735 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 736 mac->ops.rar_set = e1000_rar_set_pch_lpt; 737 mac->ops.setup_physical_interface = 738 e1000_setup_copper_link_pch_lpt; 739 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 740 } 741 742 /* Enable PCS Lock-loss workaround for ICH8 */ 743 if (mac->type == e1000_ich8lan) 744 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 745 746 return 0; 747 } 748 749 /** 750 * __e1000_access_emi_reg_locked - Read/write EMI register 751 * @hw: pointer to the HW structure 752 * @address: EMI address to program 753 * @data: pointer to value to read/write from/to the EMI address 754 * @read: boolean flag to indicate read or write 755 * 756 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 757 **/ 758 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 759 u16 *data, bool read) 760 { 761 s32 ret_val; 762 763 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 764 if (ret_val) 765 return ret_val; 766 767 if (read) 768 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 769 else 770 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 771 772 return ret_val; 773 } 774 775 /** 776 * e1000_read_emi_reg_locked - Read Extended Management Interface register 777 * @hw: pointer to the HW structure 778 * @addr: EMI address to program 779 * @data: value to be read from the EMI address 780 * 781 * Assumes the SW/FW/HW Semaphore is already acquired. 782 **/ 783 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 784 { 785 return __e1000_access_emi_reg_locked(hw, addr, data, true); 786 } 787 788 /** 789 * e1000_write_emi_reg_locked - Write Extended Management Interface register 790 * @hw: pointer to the HW structure 791 * @addr: EMI address to program 792 * @data: value to be written to the EMI address 793 * 794 * Assumes the SW/FW/HW Semaphore is already acquired. 795 **/ 796 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 797 { 798 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 799 } 800 801 /** 802 * e1000_set_eee_pchlan - Enable/disable EEE support 803 * @hw: pointer to the HW structure 804 * 805 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 806 * the link and the EEE capabilities of the link partner. The LPI Control 807 * register bits will remain set only if/when link is up. 808 * 809 * EEE LPI must not be asserted earlier than one second after link is up. 810 * On 82579, EEE LPI should not be enabled until such time otherwise there 811 * can be link issues with some switches. Other devices can have EEE LPI 812 * enabled immediately upon link up since they have a timer in hardware which 813 * prevents LPI from being asserted too early. 814 **/ 815 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 816 { 817 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 818 s32 ret_val; 819 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 820 821 switch (hw->phy.type) { 822 case e1000_phy_82579: 823 lpa = I82579_EEE_LP_ABILITY; 824 pcs_status = I82579_EEE_PCS_STATUS; 825 adv_addr = I82579_EEE_ADVERTISEMENT; 826 break; 827 case e1000_phy_i217: 828 lpa = I217_EEE_LP_ABILITY; 829 pcs_status = I217_EEE_PCS_STATUS; 830 adv_addr = I217_EEE_ADVERTISEMENT; 831 break; 832 default: 833 return 0; 834 } 835 836 ret_val = hw->phy.ops.acquire(hw); 837 if (ret_val) 838 return ret_val; 839 840 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 841 if (ret_val) 842 goto release; 843 844 /* Clear bits that enable EEE in various speeds */ 845 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 846 847 /* Enable EEE if not disabled by user */ 848 if (!dev_spec->eee_disable) { 849 /* Save off link partner's EEE ability */ 850 ret_val = e1000_read_emi_reg_locked(hw, lpa, 851 &dev_spec->eee_lp_ability); 852 if (ret_val) 853 goto release; 854 855 /* Read EEE advertisement */ 856 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 857 if (ret_val) 858 goto release; 859 860 /* Enable EEE only for speeds in which the link partner is 861 * EEE capable and for which we advertise EEE. 862 */ 863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 864 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 865 866 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 867 e1e_rphy_locked(hw, MII_LPA, &data); 868 if (data & LPA_100FULL) 869 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 870 else 871 /* EEE is not supported in 100Half, so ignore 872 * partner's EEE in 100 ability if full-duplex 873 * is not advertised. 874 */ 875 dev_spec->eee_lp_ability &= 876 ~I82579_EEE_100_SUPPORTED; 877 } 878 } 879 880 if (hw->phy.type == e1000_phy_82579) { 881 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 882 &data); 883 if (ret_val) 884 goto release; 885 886 data &= ~I82579_LPI_100_PLL_SHUT; 887 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 888 data); 889 } 890 891 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 892 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 893 if (ret_val) 894 goto release; 895 896 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 897 release: 898 hw->phy.ops.release(hw); 899 900 return ret_val; 901 } 902 903 /** 904 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 905 * @hw: pointer to the HW structure 906 * @link: link up bool flag 907 * 908 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 909 * preventing further DMA write requests. Workaround the issue by disabling 910 * the de-assertion of the clock request when in 1Gpbs mode. 911 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 912 * speeds in order to avoid Tx hangs. 913 **/ 914 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 915 { 916 u32 fextnvm6 = er32(FEXTNVM6); 917 u32 status = er32(STATUS); 918 s32 ret_val = 0; 919 u16 reg; 920 921 if (link && (status & E1000_STATUS_SPEED_1000)) { 922 ret_val = hw->phy.ops.acquire(hw); 923 if (ret_val) 924 return ret_val; 925 926 ret_val = 927 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 928 ®); 929 if (ret_val) 930 goto release; 931 932 ret_val = 933 e1000e_write_kmrn_reg_locked(hw, 934 E1000_KMRNCTRLSTA_K1_CONFIG, 935 reg & 936 ~E1000_KMRNCTRLSTA_K1_ENABLE); 937 if (ret_val) 938 goto release; 939 940 usleep_range(10, 20); 941 942 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 943 944 ret_val = 945 e1000e_write_kmrn_reg_locked(hw, 946 E1000_KMRNCTRLSTA_K1_CONFIG, 947 reg); 948 release: 949 hw->phy.ops.release(hw); 950 } else { 951 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 952 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 953 954 if ((hw->phy.revision > 5) || !link || 955 ((status & E1000_STATUS_SPEED_100) && 956 (status & E1000_STATUS_FD))) 957 goto update_fextnvm6; 958 959 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 960 if (ret_val) 961 return ret_val; 962 963 /* Clear link status transmit timeout */ 964 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 965 966 if (status & E1000_STATUS_SPEED_100) { 967 /* Set inband Tx timeout to 5x10us for 100Half */ 968 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 969 970 /* Do not extend the K1 entry latency for 100Half */ 971 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 972 } else { 973 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 974 reg |= 50 << 975 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 976 977 /* Extend the K1 entry latency for 10 Mbps */ 978 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 979 } 980 981 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 982 if (ret_val) 983 return ret_val; 984 985 update_fextnvm6: 986 ew32(FEXTNVM6, fextnvm6); 987 } 988 989 return ret_val; 990 } 991 992 /** 993 * e1000_platform_pm_pch_lpt - Set platform power management values 994 * @hw: pointer to the HW structure 995 * @link: bool indicating link status 996 * 997 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 998 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 999 * when link is up (which must not exceed the maximum latency supported 1000 * by the platform), otherwise specify there is no LTR requirement. 1001 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1002 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1003 * Capability register set, on this device LTR is set by writing the 1004 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1005 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1006 * message to the PMC. 1007 **/ 1008 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1009 { 1010 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1011 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1012 u16 lat_enc = 0; /* latency encoded */ 1013 1014 if (link) { 1015 u16 speed, duplex, scale = 0; 1016 u16 max_snoop, max_nosnoop; 1017 u16 max_ltr_enc; /* max LTR latency encoded */ 1018 u64 value; 1019 u32 rxa; 1020 1021 if (!hw->adapter->max_frame_size) { 1022 e_dbg("max_frame_size not set.\n"); 1023 return -E1000_ERR_CONFIG; 1024 } 1025 1026 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1027 if (!speed) { 1028 e_dbg("Speed not set.\n"); 1029 return -E1000_ERR_CONFIG; 1030 } 1031 1032 /* Rx Packet Buffer Allocation size (KB) */ 1033 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1034 1035 /* Determine the maximum latency tolerated by the device. 1036 * 1037 * Per the PCIe spec, the tolerated latencies are encoded as 1038 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1039 * a 10-bit value (0-1023) to provide a range from 1 ns to 1040 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1041 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1042 */ 1043 rxa *= 512; 1044 value = (rxa > hw->adapter->max_frame_size) ? 1045 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1046 0; 1047 1048 while (value > PCI_LTR_VALUE_MASK) { 1049 scale++; 1050 value = DIV_ROUND_UP(value, BIT(5)); 1051 } 1052 if (scale > E1000_LTRV_SCALE_MAX) { 1053 e_dbg("Invalid LTR latency scale %d\n", scale); 1054 return -E1000_ERR_CONFIG; 1055 } 1056 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1057 1058 /* Determine the maximum latency tolerated by the platform */ 1059 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1060 &max_snoop); 1061 pci_read_config_word(hw->adapter->pdev, 1062 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1063 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1064 1065 if (lat_enc > max_ltr_enc) 1066 lat_enc = max_ltr_enc; 1067 } 1068 1069 /* Set Snoop and No-Snoop latencies the same */ 1070 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1071 ew32(LTRV, reg); 1072 1073 return 0; 1074 } 1075 1076 /** 1077 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1078 * @hw: pointer to the HW structure 1079 * @to_sx: boolean indicating a system power state transition to Sx 1080 * 1081 * When link is down, configure ULP mode to significantly reduce the power 1082 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1083 * ME firmware to start the ULP configuration. If not on an ME enabled 1084 * system, configure the ULP mode by software. 1085 */ 1086 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1087 { 1088 u32 mac_reg; 1089 s32 ret_val = 0; 1090 u16 phy_reg; 1091 u16 oem_reg = 0; 1092 1093 if ((hw->mac.type < e1000_pch_lpt) || 1094 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1095 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1096 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1097 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1098 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1099 return 0; 1100 1101 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1102 /* Request ME configure ULP mode in the PHY */ 1103 mac_reg = er32(H2ME); 1104 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1105 ew32(H2ME, mac_reg); 1106 1107 goto out; 1108 } 1109 1110 if (!to_sx) { 1111 int i = 0; 1112 1113 /* Poll up to 5 seconds for Cable Disconnected indication */ 1114 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1115 /* Bail if link is re-acquired */ 1116 if (er32(STATUS) & E1000_STATUS_LU) 1117 return -E1000_ERR_PHY; 1118 1119 if (i++ == 100) 1120 break; 1121 1122 msleep(50); 1123 } 1124 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1125 (er32(FEXT) & 1126 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1127 } 1128 1129 ret_val = hw->phy.ops.acquire(hw); 1130 if (ret_val) 1131 goto out; 1132 1133 /* Force SMBus mode in PHY */ 1134 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1135 if (ret_val) 1136 goto release; 1137 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1138 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1139 1140 /* Force SMBus mode in MAC */ 1141 mac_reg = er32(CTRL_EXT); 1142 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1143 ew32(CTRL_EXT, mac_reg); 1144 1145 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1146 * LPLU and disable Gig speed when entering ULP 1147 */ 1148 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1149 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1150 &oem_reg); 1151 if (ret_val) 1152 goto release; 1153 1154 phy_reg = oem_reg; 1155 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1156 1157 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1158 phy_reg); 1159 1160 if (ret_val) 1161 goto release; 1162 } 1163 1164 /* Set Inband ULP Exit, Reset to SMBus mode and 1165 * Disable SMBus Release on PERST# in PHY 1166 */ 1167 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1168 if (ret_val) 1169 goto release; 1170 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1171 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1172 if (to_sx) { 1173 if (er32(WUFC) & E1000_WUFC_LNKC) 1174 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1175 else 1176 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1177 1178 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1179 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1180 } else { 1181 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1182 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1183 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1184 } 1185 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1186 1187 /* Set Disable SMBus Release on PERST# in MAC */ 1188 mac_reg = er32(FEXTNVM7); 1189 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1190 ew32(FEXTNVM7, mac_reg); 1191 1192 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1193 phy_reg |= I218_ULP_CONFIG1_START; 1194 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1195 1196 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1197 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1198 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1199 oem_reg); 1200 if (ret_val) 1201 goto release; 1202 } 1203 1204 release: 1205 hw->phy.ops.release(hw); 1206 out: 1207 if (ret_val) 1208 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1209 else 1210 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1211 1212 return ret_val; 1213 } 1214 1215 /** 1216 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1217 * @hw: pointer to the HW structure 1218 * @force: boolean indicating whether or not to force disabling ULP 1219 * 1220 * Un-configure ULP mode when link is up, the system is transitioned from 1221 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1222 * system, poll for an indication from ME that ULP has been un-configured. 1223 * If not on an ME enabled system, un-configure the ULP mode by software. 1224 * 1225 * During nominal operation, this function is called when link is acquired 1226 * to disable ULP mode (force=false); otherwise, for example when unloading 1227 * the driver or during Sx->S0 transitions, this is called with force=true 1228 * to forcibly disable ULP. 1229 */ 1230 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1231 { 1232 s32 ret_val = 0; 1233 u32 mac_reg; 1234 u16 phy_reg; 1235 int i = 0; 1236 1237 if ((hw->mac.type < e1000_pch_lpt) || 1238 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1239 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1240 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1241 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1242 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1243 return 0; 1244 1245 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1246 struct e1000_adapter *adapter = hw->adapter; 1247 bool firmware_bug = false; 1248 1249 if (force) { 1250 /* Request ME un-configure ULP mode in the PHY */ 1251 mac_reg = er32(H2ME); 1252 mac_reg &= ~E1000_H2ME_ULP; 1253 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1254 ew32(H2ME, mac_reg); 1255 } 1256 1257 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1258 * If this takes more than 1 second, show a warning indicating a 1259 * firmware bug 1260 */ 1261 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1262 if (i++ == 250) { 1263 ret_val = -E1000_ERR_PHY; 1264 goto out; 1265 } 1266 if (i > 100 && !firmware_bug) 1267 firmware_bug = true; 1268 1269 usleep_range(10000, 11000); 1270 } 1271 if (firmware_bug) 1272 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1273 i * 10); 1274 else 1275 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1276 i * 10); 1277 1278 if (force) { 1279 mac_reg = er32(H2ME); 1280 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1281 ew32(H2ME, mac_reg); 1282 } else { 1283 /* Clear H2ME.ULP after ME ULP configuration */ 1284 mac_reg = er32(H2ME); 1285 mac_reg &= ~E1000_H2ME_ULP; 1286 ew32(H2ME, mac_reg); 1287 } 1288 1289 goto out; 1290 } 1291 1292 ret_val = hw->phy.ops.acquire(hw); 1293 if (ret_val) 1294 goto out; 1295 1296 if (force) 1297 /* Toggle LANPHYPC Value bit */ 1298 e1000_toggle_lanphypc_pch_lpt(hw); 1299 1300 /* Unforce SMBus mode in PHY */ 1301 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1302 if (ret_val) { 1303 /* The MAC might be in PCIe mode, so temporarily force to 1304 * SMBus mode in order to access the PHY. 1305 */ 1306 mac_reg = er32(CTRL_EXT); 1307 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1308 ew32(CTRL_EXT, mac_reg); 1309 1310 msleep(50); 1311 1312 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1313 &phy_reg); 1314 if (ret_val) 1315 goto release; 1316 } 1317 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1318 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1319 1320 /* Unforce SMBus mode in MAC */ 1321 mac_reg = er32(CTRL_EXT); 1322 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1323 ew32(CTRL_EXT, mac_reg); 1324 1325 /* When ULP mode was previously entered, K1 was disabled by the 1326 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1327 */ 1328 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1329 if (ret_val) 1330 goto release; 1331 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1332 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1333 1334 /* Clear ULP enabled configuration */ 1335 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1336 if (ret_val) 1337 goto release; 1338 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1339 I218_ULP_CONFIG1_STICKY_ULP | 1340 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1341 I218_ULP_CONFIG1_WOL_HOST | 1342 I218_ULP_CONFIG1_INBAND_EXIT | 1343 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1344 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1345 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1346 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1347 1348 /* Commit ULP changes by starting auto ULP configuration */ 1349 phy_reg |= I218_ULP_CONFIG1_START; 1350 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1351 1352 /* Clear Disable SMBus Release on PERST# in MAC */ 1353 mac_reg = er32(FEXTNVM7); 1354 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1355 ew32(FEXTNVM7, mac_reg); 1356 1357 release: 1358 hw->phy.ops.release(hw); 1359 if (force) { 1360 e1000_phy_hw_reset(hw); 1361 msleep(50); 1362 } 1363 out: 1364 if (ret_val) 1365 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1366 else 1367 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1368 1369 return ret_val; 1370 } 1371 1372 /** 1373 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1374 * @hw: pointer to the HW structure 1375 * 1376 * Checks to see of the link status of the hardware has changed. If a 1377 * change in link status has been detected, then we read the PHY registers 1378 * to get the current speed/duplex if link exists. 1379 **/ 1380 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1381 { 1382 struct e1000_mac_info *mac = &hw->mac; 1383 s32 ret_val, tipg_reg = 0; 1384 u16 emi_addr, emi_val = 0; 1385 bool link; 1386 u16 phy_reg; 1387 1388 /* We only want to go out to the PHY registers to see if Auto-Neg 1389 * has completed and/or if our link status has changed. The 1390 * get_link_status flag is set upon receiving a Link Status 1391 * Change or Rx Sequence Error interrupt. 1392 */ 1393 if (!mac->get_link_status) 1394 return 0; 1395 mac->get_link_status = false; 1396 1397 /* First we want to see if the MII Status Register reports 1398 * link. If so, then we want to get the current speed/duplex 1399 * of the PHY. 1400 */ 1401 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1402 if (ret_val) 1403 goto out; 1404 1405 if (hw->mac.type == e1000_pchlan) { 1406 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1407 if (ret_val) 1408 goto out; 1409 } 1410 1411 /* When connected at 10Mbps half-duplex, some parts are excessively 1412 * aggressive resulting in many collisions. To avoid this, increase 1413 * the IPG and reduce Rx latency in the PHY. 1414 */ 1415 if ((hw->mac.type >= e1000_pch2lan) && link) { 1416 u16 speed, duplex; 1417 1418 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1419 tipg_reg = er32(TIPG); 1420 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1421 1422 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1423 tipg_reg |= 0xFF; 1424 /* Reduce Rx latency in analog PHY */ 1425 emi_val = 0; 1426 } else if (hw->mac.type >= e1000_pch_spt && 1427 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1428 tipg_reg |= 0xC; 1429 emi_val = 1; 1430 } else { 1431 1432 /* Roll back the default values */ 1433 tipg_reg |= 0x08; 1434 emi_val = 1; 1435 } 1436 1437 ew32(TIPG, tipg_reg); 1438 1439 ret_val = hw->phy.ops.acquire(hw); 1440 if (ret_val) 1441 goto out; 1442 1443 if (hw->mac.type == e1000_pch2lan) 1444 emi_addr = I82579_RX_CONFIG; 1445 else 1446 emi_addr = I217_RX_CONFIG; 1447 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1448 1449 if (hw->mac.type >= e1000_pch_lpt) { 1450 u16 phy_reg; 1451 1452 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1453 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1454 if (speed == SPEED_100 || speed == SPEED_10) 1455 phy_reg |= 0x3E8; 1456 else 1457 phy_reg |= 0xFA; 1458 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1459 1460 if (speed == SPEED_1000) { 1461 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1462 &phy_reg); 1463 1464 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1465 1466 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1467 phy_reg); 1468 } 1469 } 1470 hw->phy.ops.release(hw); 1471 1472 if (ret_val) 1473 goto out; 1474 1475 if (hw->mac.type >= e1000_pch_spt) { 1476 u16 data; 1477 u16 ptr_gap; 1478 1479 if (speed == SPEED_1000) { 1480 ret_val = hw->phy.ops.acquire(hw); 1481 if (ret_val) 1482 goto out; 1483 1484 ret_val = e1e_rphy_locked(hw, 1485 PHY_REG(776, 20), 1486 &data); 1487 if (ret_val) { 1488 hw->phy.ops.release(hw); 1489 goto out; 1490 } 1491 1492 ptr_gap = (data & (0x3FF << 2)) >> 2; 1493 if (ptr_gap < 0x18) { 1494 data &= ~(0x3FF << 2); 1495 data |= (0x18 << 2); 1496 ret_val = 1497 e1e_wphy_locked(hw, 1498 PHY_REG(776, 20), 1499 data); 1500 } 1501 hw->phy.ops.release(hw); 1502 if (ret_val) 1503 goto out; 1504 } else { 1505 ret_val = hw->phy.ops.acquire(hw); 1506 if (ret_val) 1507 goto out; 1508 1509 ret_val = e1e_wphy_locked(hw, 1510 PHY_REG(776, 20), 1511 0xC023); 1512 hw->phy.ops.release(hw); 1513 if (ret_val) 1514 goto out; 1515 1516 } 1517 } 1518 } 1519 1520 /* I217 Packet Loss issue: 1521 * ensure that FEXTNVM4 Beacon Duration is set correctly 1522 * on power up. 1523 * Set the Beacon Duration for I217 to 8 usec 1524 */ 1525 if (hw->mac.type >= e1000_pch_lpt) { 1526 u32 mac_reg; 1527 1528 mac_reg = er32(FEXTNVM4); 1529 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1530 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1531 ew32(FEXTNVM4, mac_reg); 1532 } 1533 1534 /* Work-around I218 hang issue */ 1535 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1536 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1537 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1538 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1539 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1540 if (ret_val) 1541 goto out; 1542 } 1543 if (hw->mac.type >= e1000_pch_lpt) { 1544 /* Set platform power management values for 1545 * Latency Tolerance Reporting (LTR) 1546 */ 1547 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1548 if (ret_val) 1549 goto out; 1550 } 1551 1552 /* Clear link partner's EEE ability */ 1553 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1554 1555 if (hw->mac.type >= e1000_pch_lpt) { 1556 u32 fextnvm6 = er32(FEXTNVM6); 1557 1558 if (hw->mac.type == e1000_pch_spt) { 1559 /* FEXTNVM6 K1-off workaround - for SPT only */ 1560 u32 pcieanacfg = er32(PCIEANACFG); 1561 1562 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1563 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1564 else 1565 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1566 } 1567 1568 ew32(FEXTNVM6, fextnvm6); 1569 } 1570 1571 if (!link) 1572 goto out; 1573 1574 switch (hw->mac.type) { 1575 case e1000_pch2lan: 1576 ret_val = e1000_k1_workaround_lv(hw); 1577 if (ret_val) 1578 return ret_val; 1579 fallthrough; 1580 case e1000_pchlan: 1581 if (hw->phy.type == e1000_phy_82578) { 1582 ret_val = e1000_link_stall_workaround_hv(hw); 1583 if (ret_val) 1584 return ret_val; 1585 } 1586 1587 /* Workaround for PCHx parts in half-duplex: 1588 * Set the number of preambles removed from the packet 1589 * when it is passed from the PHY to the MAC to prevent 1590 * the MAC from misinterpreting the packet type. 1591 */ 1592 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1593 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1594 1595 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1596 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1597 1598 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1599 break; 1600 default: 1601 break; 1602 } 1603 1604 /* Check if there was DownShift, must be checked 1605 * immediately after link-up 1606 */ 1607 e1000e_check_downshift(hw); 1608 1609 /* Enable/Disable EEE after link up */ 1610 if (hw->phy.type > e1000_phy_82579) { 1611 ret_val = e1000_set_eee_pchlan(hw); 1612 if (ret_val) 1613 return ret_val; 1614 } 1615 1616 /* If we are forcing speed/duplex, then we simply return since 1617 * we have already determined whether we have link or not. 1618 */ 1619 if (!mac->autoneg) 1620 return -E1000_ERR_CONFIG; 1621 1622 /* Auto-Neg is enabled. Auto Speed Detection takes care 1623 * of MAC speed/duplex configuration. So we only need to 1624 * configure Collision Distance in the MAC. 1625 */ 1626 mac->ops.config_collision_dist(hw); 1627 1628 /* Configure Flow Control now that Auto-Neg has completed. 1629 * First, we need to restore the desired flow control 1630 * settings because we may have had to re-autoneg with a 1631 * different link partner. 1632 */ 1633 ret_val = e1000e_config_fc_after_link_up(hw); 1634 if (ret_val) 1635 e_dbg("Error configuring flow control\n"); 1636 1637 return ret_val; 1638 1639 out: 1640 mac->get_link_status = true; 1641 return ret_val; 1642 } 1643 1644 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1645 { 1646 struct e1000_hw *hw = &adapter->hw; 1647 s32 rc; 1648 1649 rc = e1000_init_mac_params_ich8lan(hw); 1650 if (rc) 1651 return rc; 1652 1653 rc = e1000_init_nvm_params_ich8lan(hw); 1654 if (rc) 1655 return rc; 1656 1657 switch (hw->mac.type) { 1658 case e1000_ich8lan: 1659 case e1000_ich9lan: 1660 case e1000_ich10lan: 1661 rc = e1000_init_phy_params_ich8lan(hw); 1662 break; 1663 case e1000_pchlan: 1664 case e1000_pch2lan: 1665 case e1000_pch_lpt: 1666 case e1000_pch_spt: 1667 case e1000_pch_cnp: 1668 case e1000_pch_tgp: 1669 case e1000_pch_adp: 1670 case e1000_pch_mtp: 1671 case e1000_pch_lnp: 1672 rc = e1000_init_phy_params_pchlan(hw); 1673 break; 1674 default: 1675 break; 1676 } 1677 if (rc) 1678 return rc; 1679 1680 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1681 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1682 */ 1683 if ((adapter->hw.phy.type == e1000_phy_ife) || 1684 ((adapter->hw.mac.type >= e1000_pch2lan) && 1685 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1686 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1687 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1688 1689 hw->mac.ops.blink_led = NULL; 1690 } 1691 1692 if ((adapter->hw.mac.type == e1000_ich8lan) && 1693 (adapter->hw.phy.type != e1000_phy_ife)) 1694 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1695 1696 /* Enable workaround for 82579 w/ ME enabled */ 1697 if ((adapter->hw.mac.type == e1000_pch2lan) && 1698 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1699 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1700 1701 return 0; 1702 } 1703 1704 static DEFINE_MUTEX(nvm_mutex); 1705 1706 /** 1707 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1708 * @hw: pointer to the HW structure 1709 * 1710 * Acquires the mutex for performing NVM operations. 1711 **/ 1712 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1713 { 1714 mutex_lock(&nvm_mutex); 1715 1716 return 0; 1717 } 1718 1719 /** 1720 * e1000_release_nvm_ich8lan - Release NVM mutex 1721 * @hw: pointer to the HW structure 1722 * 1723 * Releases the mutex used while performing NVM operations. 1724 **/ 1725 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1726 { 1727 mutex_unlock(&nvm_mutex); 1728 } 1729 1730 /** 1731 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1732 * @hw: pointer to the HW structure 1733 * 1734 * Acquires the software control flag for performing PHY and select 1735 * MAC CSR accesses. 1736 **/ 1737 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1738 { 1739 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1740 s32 ret_val = 0; 1741 1742 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1743 &hw->adapter->state)) { 1744 e_dbg("contention for Phy access\n"); 1745 return -E1000_ERR_PHY; 1746 } 1747 1748 while (timeout) { 1749 extcnf_ctrl = er32(EXTCNF_CTRL); 1750 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1751 break; 1752 1753 mdelay(1); 1754 timeout--; 1755 } 1756 1757 if (!timeout) { 1758 e_dbg("SW has already locked the resource.\n"); 1759 ret_val = -E1000_ERR_CONFIG; 1760 goto out; 1761 } 1762 1763 timeout = SW_FLAG_TIMEOUT; 1764 1765 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1766 ew32(EXTCNF_CTRL, extcnf_ctrl); 1767 1768 while (timeout) { 1769 extcnf_ctrl = er32(EXTCNF_CTRL); 1770 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1771 break; 1772 1773 mdelay(1); 1774 timeout--; 1775 } 1776 1777 if (!timeout) { 1778 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1779 er32(FWSM), extcnf_ctrl); 1780 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1781 ew32(EXTCNF_CTRL, extcnf_ctrl); 1782 ret_val = -E1000_ERR_CONFIG; 1783 goto out; 1784 } 1785 1786 out: 1787 if (ret_val) 1788 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1789 1790 return ret_val; 1791 } 1792 1793 /** 1794 * e1000_release_swflag_ich8lan - Release software control flag 1795 * @hw: pointer to the HW structure 1796 * 1797 * Releases the software control flag for performing PHY and select 1798 * MAC CSR accesses. 1799 **/ 1800 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1801 { 1802 u32 extcnf_ctrl; 1803 1804 extcnf_ctrl = er32(EXTCNF_CTRL); 1805 1806 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1807 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1808 ew32(EXTCNF_CTRL, extcnf_ctrl); 1809 } else { 1810 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1811 } 1812 1813 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1814 } 1815 1816 /** 1817 * e1000_check_mng_mode_ich8lan - Checks management mode 1818 * @hw: pointer to the HW structure 1819 * 1820 * This checks if the adapter has any manageability enabled. 1821 * This is a function pointer entry point only called by read/write 1822 * routines for the PHY and NVM parts. 1823 **/ 1824 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1825 { 1826 u32 fwsm; 1827 1828 fwsm = er32(FWSM); 1829 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1830 ((fwsm & E1000_FWSM_MODE_MASK) == 1831 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1832 } 1833 1834 /** 1835 * e1000_check_mng_mode_pchlan - Checks management mode 1836 * @hw: pointer to the HW structure 1837 * 1838 * This checks if the adapter has iAMT enabled. 1839 * This is a function pointer entry point only called by read/write 1840 * routines for the PHY and NVM parts. 1841 **/ 1842 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1843 { 1844 u32 fwsm; 1845 1846 fwsm = er32(FWSM); 1847 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1848 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1849 } 1850 1851 /** 1852 * e1000_rar_set_pch2lan - Set receive address register 1853 * @hw: pointer to the HW structure 1854 * @addr: pointer to the receive address 1855 * @index: receive address array register 1856 * 1857 * Sets the receive address array register at index to the address passed 1858 * in by addr. For 82579, RAR[0] is the base address register that is to 1859 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1860 * Use SHRA[0-3] in place of those reserved for ME. 1861 **/ 1862 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1863 { 1864 u32 rar_low, rar_high; 1865 1866 /* HW expects these in little endian so we reverse the byte order 1867 * from network order (big endian) to little endian 1868 */ 1869 rar_low = ((u32)addr[0] | 1870 ((u32)addr[1] << 8) | 1871 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1872 1873 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1874 1875 /* If MAC address zero, no need to set the AV bit */ 1876 if (rar_low || rar_high) 1877 rar_high |= E1000_RAH_AV; 1878 1879 if (index == 0) { 1880 ew32(RAL(index), rar_low); 1881 e1e_flush(); 1882 ew32(RAH(index), rar_high); 1883 e1e_flush(); 1884 return 0; 1885 } 1886 1887 /* RAR[1-6] are owned by manageability. Skip those and program the 1888 * next address into the SHRA register array. 1889 */ 1890 if (index < (u32)(hw->mac.rar_entry_count)) { 1891 s32 ret_val; 1892 1893 ret_val = e1000_acquire_swflag_ich8lan(hw); 1894 if (ret_val) 1895 goto out; 1896 1897 ew32(SHRAL(index - 1), rar_low); 1898 e1e_flush(); 1899 ew32(SHRAH(index - 1), rar_high); 1900 e1e_flush(); 1901 1902 e1000_release_swflag_ich8lan(hw); 1903 1904 /* verify the register updates */ 1905 if ((er32(SHRAL(index - 1)) == rar_low) && 1906 (er32(SHRAH(index - 1)) == rar_high)) 1907 return 0; 1908 1909 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1910 (index - 1), er32(FWSM)); 1911 } 1912 1913 out: 1914 e_dbg("Failed to write receive address at index %d\n", index); 1915 return -E1000_ERR_CONFIG; 1916 } 1917 1918 /** 1919 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1920 * @hw: pointer to the HW structure 1921 * 1922 * Get the number of available receive registers that the Host can 1923 * program. SHRA[0-10] are the shared receive address registers 1924 * that are shared between the Host and manageability engine (ME). 1925 * ME can reserve any number of addresses and the host needs to be 1926 * able to tell how many available registers it has access to. 1927 **/ 1928 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1929 { 1930 u32 wlock_mac; 1931 u32 num_entries; 1932 1933 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1934 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1935 1936 switch (wlock_mac) { 1937 case 0: 1938 /* All SHRA[0..10] and RAR[0] available */ 1939 num_entries = hw->mac.rar_entry_count; 1940 break; 1941 case 1: 1942 /* Only RAR[0] available */ 1943 num_entries = 1; 1944 break; 1945 default: 1946 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1947 num_entries = wlock_mac + 1; 1948 break; 1949 } 1950 1951 return num_entries; 1952 } 1953 1954 /** 1955 * e1000_rar_set_pch_lpt - Set receive address registers 1956 * @hw: pointer to the HW structure 1957 * @addr: pointer to the receive address 1958 * @index: receive address array register 1959 * 1960 * Sets the receive address register array at index to the address passed 1961 * in by addr. For LPT, RAR[0] is the base address register that is to 1962 * contain the MAC address. SHRA[0-10] are the shared receive address 1963 * registers that are shared between the Host and manageability engine (ME). 1964 **/ 1965 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1966 { 1967 u32 rar_low, rar_high; 1968 u32 wlock_mac; 1969 1970 /* HW expects these in little endian so we reverse the byte order 1971 * from network order (big endian) to little endian 1972 */ 1973 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1974 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1975 1976 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1977 1978 /* If MAC address zero, no need to set the AV bit */ 1979 if (rar_low || rar_high) 1980 rar_high |= E1000_RAH_AV; 1981 1982 if (index == 0) { 1983 ew32(RAL(index), rar_low); 1984 e1e_flush(); 1985 ew32(RAH(index), rar_high); 1986 e1e_flush(); 1987 return 0; 1988 } 1989 1990 /* The manageability engine (ME) can lock certain SHRAR registers that 1991 * it is using - those registers are unavailable for use. 1992 */ 1993 if (index < hw->mac.rar_entry_count) { 1994 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1995 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1996 1997 /* Check if all SHRAR registers are locked */ 1998 if (wlock_mac == 1) 1999 goto out; 2000 2001 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2002 s32 ret_val; 2003 2004 ret_val = e1000_acquire_swflag_ich8lan(hw); 2005 2006 if (ret_val) 2007 goto out; 2008 2009 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2010 e1e_flush(); 2011 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2012 e1e_flush(); 2013 2014 e1000_release_swflag_ich8lan(hw); 2015 2016 /* verify the register updates */ 2017 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2018 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2019 return 0; 2020 } 2021 } 2022 2023 out: 2024 e_dbg("Failed to write receive address at index %d\n", index); 2025 return -E1000_ERR_CONFIG; 2026 } 2027 2028 /** 2029 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2030 * @hw: pointer to the HW structure 2031 * 2032 * Checks if firmware is blocking the reset of the PHY. 2033 * This is a function pointer entry point only called by 2034 * reset routines. 2035 **/ 2036 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2037 { 2038 bool blocked = false; 2039 int i = 0; 2040 2041 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2042 (i++ < 30)) 2043 usleep_range(10000, 11000); 2044 return blocked ? E1000_BLK_PHY_RESET : 0; 2045 } 2046 2047 /** 2048 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2049 * @hw: pointer to the HW structure 2050 * 2051 * Assumes semaphore already acquired. 2052 * 2053 **/ 2054 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2055 { 2056 u16 phy_data; 2057 u32 strap = er32(STRAP); 2058 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2059 E1000_STRAP_SMT_FREQ_SHIFT; 2060 s32 ret_val; 2061 2062 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2063 2064 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2065 if (ret_val) 2066 return ret_val; 2067 2068 phy_data &= ~HV_SMB_ADDR_MASK; 2069 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2070 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2071 2072 if (hw->phy.type == e1000_phy_i217) { 2073 /* Restore SMBus frequency */ 2074 if (freq--) { 2075 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2076 phy_data |= (freq & BIT(0)) << 2077 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2078 phy_data |= (freq & BIT(1)) << 2079 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2080 } else { 2081 e_dbg("Unsupported SMB frequency in PHY\n"); 2082 } 2083 } 2084 2085 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2086 } 2087 2088 /** 2089 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2090 * @hw: pointer to the HW structure 2091 * 2092 * SW should configure the LCD from the NVM extended configuration region 2093 * as a workaround for certain parts. 2094 **/ 2095 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2096 { 2097 struct e1000_phy_info *phy = &hw->phy; 2098 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2099 s32 ret_val = 0; 2100 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2101 2102 /* Initialize the PHY from the NVM on ICH platforms. This 2103 * is needed due to an issue where the NVM configuration is 2104 * not properly autoloaded after power transitions. 2105 * Therefore, after each PHY reset, we will load the 2106 * configuration data out of the NVM manually. 2107 */ 2108 switch (hw->mac.type) { 2109 case e1000_ich8lan: 2110 if (phy->type != e1000_phy_igp_3) 2111 return ret_val; 2112 2113 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2114 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2115 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2116 break; 2117 } 2118 fallthrough; 2119 case e1000_pchlan: 2120 case e1000_pch2lan: 2121 case e1000_pch_lpt: 2122 case e1000_pch_spt: 2123 case e1000_pch_cnp: 2124 case e1000_pch_tgp: 2125 case e1000_pch_adp: 2126 case e1000_pch_mtp: 2127 case e1000_pch_lnp: 2128 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2129 break; 2130 default: 2131 return ret_val; 2132 } 2133 2134 ret_val = hw->phy.ops.acquire(hw); 2135 if (ret_val) 2136 return ret_val; 2137 2138 data = er32(FEXTNVM); 2139 if (!(data & sw_cfg_mask)) 2140 goto release; 2141 2142 /* Make sure HW does not configure LCD from PHY 2143 * extended configuration before SW configuration 2144 */ 2145 data = er32(EXTCNF_CTRL); 2146 if ((hw->mac.type < e1000_pch2lan) && 2147 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2148 goto release; 2149 2150 cnf_size = er32(EXTCNF_SIZE); 2151 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2152 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2153 if (!cnf_size) 2154 goto release; 2155 2156 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2157 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2158 2159 if (((hw->mac.type == e1000_pchlan) && 2160 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2161 (hw->mac.type > e1000_pchlan)) { 2162 /* HW configures the SMBus address and LEDs when the 2163 * OEM and LCD Write Enable bits are set in the NVM. 2164 * When both NVM bits are cleared, SW will configure 2165 * them instead. 2166 */ 2167 ret_val = e1000_write_smbus_addr(hw); 2168 if (ret_val) 2169 goto release; 2170 2171 data = er32(LEDCTL); 2172 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2173 (u16)data); 2174 if (ret_val) 2175 goto release; 2176 } 2177 2178 /* Configure LCD from extended configuration region. */ 2179 2180 /* cnf_base_addr is in DWORD */ 2181 word_addr = (u16)(cnf_base_addr << 1); 2182 2183 for (i = 0; i < cnf_size; i++) { 2184 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2185 if (ret_val) 2186 goto release; 2187 2188 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2189 1, ®_addr); 2190 if (ret_val) 2191 goto release; 2192 2193 /* Save off the PHY page for future writes. */ 2194 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2195 phy_page = reg_data; 2196 continue; 2197 } 2198 2199 reg_addr &= PHY_REG_MASK; 2200 reg_addr |= phy_page; 2201 2202 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2203 if (ret_val) 2204 goto release; 2205 } 2206 2207 release: 2208 hw->phy.ops.release(hw); 2209 return ret_val; 2210 } 2211 2212 /** 2213 * e1000_k1_gig_workaround_hv - K1 Si workaround 2214 * @hw: pointer to the HW structure 2215 * @link: link up bool flag 2216 * 2217 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2218 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2219 * If link is down, the function will restore the default K1 setting located 2220 * in the NVM. 2221 **/ 2222 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2223 { 2224 s32 ret_val = 0; 2225 u16 status_reg = 0; 2226 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2227 2228 if (hw->mac.type != e1000_pchlan) 2229 return 0; 2230 2231 /* Wrap the whole flow with the sw flag */ 2232 ret_val = hw->phy.ops.acquire(hw); 2233 if (ret_val) 2234 return ret_val; 2235 2236 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2237 if (link) { 2238 if (hw->phy.type == e1000_phy_82578) { 2239 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2240 &status_reg); 2241 if (ret_val) 2242 goto release; 2243 2244 status_reg &= (BM_CS_STATUS_LINK_UP | 2245 BM_CS_STATUS_RESOLVED | 2246 BM_CS_STATUS_SPEED_MASK); 2247 2248 if (status_reg == (BM_CS_STATUS_LINK_UP | 2249 BM_CS_STATUS_RESOLVED | 2250 BM_CS_STATUS_SPEED_1000)) 2251 k1_enable = false; 2252 } 2253 2254 if (hw->phy.type == e1000_phy_82577) { 2255 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2256 if (ret_val) 2257 goto release; 2258 2259 status_reg &= (HV_M_STATUS_LINK_UP | 2260 HV_M_STATUS_AUTONEG_COMPLETE | 2261 HV_M_STATUS_SPEED_MASK); 2262 2263 if (status_reg == (HV_M_STATUS_LINK_UP | 2264 HV_M_STATUS_AUTONEG_COMPLETE | 2265 HV_M_STATUS_SPEED_1000)) 2266 k1_enable = false; 2267 } 2268 2269 /* Link stall fix for link up */ 2270 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2271 if (ret_val) 2272 goto release; 2273 2274 } else { 2275 /* Link stall fix for link down */ 2276 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2277 if (ret_val) 2278 goto release; 2279 } 2280 2281 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2282 2283 release: 2284 hw->phy.ops.release(hw); 2285 2286 return ret_val; 2287 } 2288 2289 /** 2290 * e1000_configure_k1_ich8lan - Configure K1 power state 2291 * @hw: pointer to the HW structure 2292 * @k1_enable: K1 state to configure 2293 * 2294 * Configure the K1 power state based on the provided parameter. 2295 * Assumes semaphore already acquired. 2296 * 2297 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2298 **/ 2299 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2300 { 2301 s32 ret_val; 2302 u32 ctrl_reg = 0; 2303 u32 ctrl_ext = 0; 2304 u32 reg = 0; 2305 u16 kmrn_reg = 0; 2306 2307 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2308 &kmrn_reg); 2309 if (ret_val) 2310 return ret_val; 2311 2312 if (k1_enable) 2313 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2314 else 2315 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2316 2317 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2318 kmrn_reg); 2319 if (ret_val) 2320 return ret_val; 2321 2322 usleep_range(20, 40); 2323 ctrl_ext = er32(CTRL_EXT); 2324 ctrl_reg = er32(CTRL); 2325 2326 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2327 reg |= E1000_CTRL_FRCSPD; 2328 ew32(CTRL, reg); 2329 2330 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2331 e1e_flush(); 2332 usleep_range(20, 40); 2333 ew32(CTRL, ctrl_reg); 2334 ew32(CTRL_EXT, ctrl_ext); 2335 e1e_flush(); 2336 usleep_range(20, 40); 2337 2338 return 0; 2339 } 2340 2341 /** 2342 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2343 * @hw: pointer to the HW structure 2344 * @d0_state: boolean if entering d0 or d3 device state 2345 * 2346 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2347 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2348 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2349 **/ 2350 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2351 { 2352 s32 ret_val = 0; 2353 u32 mac_reg; 2354 u16 oem_reg; 2355 2356 if (hw->mac.type < e1000_pchlan) 2357 return ret_val; 2358 2359 ret_val = hw->phy.ops.acquire(hw); 2360 if (ret_val) 2361 return ret_val; 2362 2363 if (hw->mac.type == e1000_pchlan) { 2364 mac_reg = er32(EXTCNF_CTRL); 2365 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2366 goto release; 2367 } 2368 2369 mac_reg = er32(FEXTNVM); 2370 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2371 goto release; 2372 2373 mac_reg = er32(PHY_CTRL); 2374 2375 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2376 if (ret_val) 2377 goto release; 2378 2379 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2380 2381 if (d0_state) { 2382 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2383 oem_reg |= HV_OEM_BITS_GBE_DIS; 2384 2385 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2386 oem_reg |= HV_OEM_BITS_LPLU; 2387 } else { 2388 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2389 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2390 oem_reg |= HV_OEM_BITS_GBE_DIS; 2391 2392 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2393 E1000_PHY_CTRL_NOND0A_LPLU)) 2394 oem_reg |= HV_OEM_BITS_LPLU; 2395 } 2396 2397 /* Set Restart auto-neg to activate the bits */ 2398 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2399 !hw->phy.ops.check_reset_block(hw)) 2400 oem_reg |= HV_OEM_BITS_RESTART_AN; 2401 2402 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2403 2404 release: 2405 hw->phy.ops.release(hw); 2406 2407 return ret_val; 2408 } 2409 2410 /** 2411 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2412 * @hw: pointer to the HW structure 2413 **/ 2414 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2415 { 2416 s32 ret_val; 2417 u16 data; 2418 2419 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2420 if (ret_val) 2421 return ret_val; 2422 2423 data |= HV_KMRN_MDIO_SLOW; 2424 2425 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2426 2427 return ret_val; 2428 } 2429 2430 /** 2431 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2432 * @hw: pointer to the HW structure 2433 * 2434 * A series of PHY workarounds to be done after every PHY reset. 2435 **/ 2436 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2437 { 2438 s32 ret_val = 0; 2439 u16 phy_data; 2440 2441 if (hw->mac.type != e1000_pchlan) 2442 return 0; 2443 2444 /* Set MDIO slow mode before any other MDIO access */ 2445 if (hw->phy.type == e1000_phy_82577) { 2446 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2447 if (ret_val) 2448 return ret_val; 2449 } 2450 2451 if (((hw->phy.type == e1000_phy_82577) && 2452 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2453 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2454 /* Disable generation of early preamble */ 2455 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2456 if (ret_val) 2457 return ret_val; 2458 2459 /* Preamble tuning for SSC */ 2460 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2461 if (ret_val) 2462 return ret_val; 2463 } 2464 2465 if (hw->phy.type == e1000_phy_82578) { 2466 /* Return registers to default by doing a soft reset then 2467 * writing 0x3140 to the control register. 2468 */ 2469 if (hw->phy.revision < 2) { 2470 e1000e_phy_sw_reset(hw); 2471 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2472 if (ret_val) 2473 return ret_val; 2474 } 2475 } 2476 2477 /* Select page 0 */ 2478 ret_val = hw->phy.ops.acquire(hw); 2479 if (ret_val) 2480 return ret_val; 2481 2482 hw->phy.addr = 1; 2483 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2484 hw->phy.ops.release(hw); 2485 if (ret_val) 2486 return ret_val; 2487 2488 /* Configure the K1 Si workaround during phy reset assuming there is 2489 * link so that it disables K1 if link is in 1Gbps. 2490 */ 2491 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2492 if (ret_val) 2493 return ret_val; 2494 2495 /* Workaround for link disconnects on a busy hub in half duplex */ 2496 ret_val = hw->phy.ops.acquire(hw); 2497 if (ret_val) 2498 return ret_val; 2499 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2500 if (ret_val) 2501 goto release; 2502 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2503 if (ret_val) 2504 goto release; 2505 2506 /* set MSE higher to enable link to stay up when noise is high */ 2507 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2508 release: 2509 hw->phy.ops.release(hw); 2510 2511 return ret_val; 2512 } 2513 2514 /** 2515 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2516 * @hw: pointer to the HW structure 2517 **/ 2518 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2519 { 2520 u32 mac_reg; 2521 u16 i, phy_reg = 0; 2522 s32 ret_val; 2523 2524 ret_val = hw->phy.ops.acquire(hw); 2525 if (ret_val) 2526 return; 2527 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2528 if (ret_val) 2529 goto release; 2530 2531 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2532 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2533 mac_reg = er32(RAL(i)); 2534 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2535 (u16)(mac_reg & 0xFFFF)); 2536 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2537 (u16)((mac_reg >> 16) & 0xFFFF)); 2538 2539 mac_reg = er32(RAH(i)); 2540 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2541 (u16)(mac_reg & 0xFFFF)); 2542 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2543 (u16)((mac_reg & E1000_RAH_AV) 2544 >> 16)); 2545 } 2546 2547 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2548 2549 release: 2550 hw->phy.ops.release(hw); 2551 } 2552 2553 /** 2554 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2555 * with 82579 PHY 2556 * @hw: pointer to the HW structure 2557 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2558 **/ 2559 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2560 { 2561 s32 ret_val = 0; 2562 u16 phy_reg, data; 2563 u32 mac_reg; 2564 u16 i; 2565 2566 if (hw->mac.type < e1000_pch2lan) 2567 return 0; 2568 2569 /* disable Rx path while enabling/disabling workaround */ 2570 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2571 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2572 if (ret_val) 2573 return ret_val; 2574 2575 if (enable) { 2576 /* Write Rx addresses (rar_entry_count for RAL/H, and 2577 * SHRAL/H) and initial CRC values to the MAC 2578 */ 2579 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2580 u8 mac_addr[ETH_ALEN] = { 0 }; 2581 u32 addr_high, addr_low; 2582 2583 addr_high = er32(RAH(i)); 2584 if (!(addr_high & E1000_RAH_AV)) 2585 continue; 2586 addr_low = er32(RAL(i)); 2587 mac_addr[0] = (addr_low & 0xFF); 2588 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2589 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2590 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2591 mac_addr[4] = (addr_high & 0xFF); 2592 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2593 2594 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2595 } 2596 2597 /* Write Rx addresses to the PHY */ 2598 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2599 2600 /* Enable jumbo frame workaround in the MAC */ 2601 mac_reg = er32(FFLT_DBG); 2602 mac_reg &= ~BIT(14); 2603 mac_reg |= (7 << 15); 2604 ew32(FFLT_DBG, mac_reg); 2605 2606 mac_reg = er32(RCTL); 2607 mac_reg |= E1000_RCTL_SECRC; 2608 ew32(RCTL, mac_reg); 2609 2610 ret_val = e1000e_read_kmrn_reg(hw, 2611 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2612 &data); 2613 if (ret_val) 2614 return ret_val; 2615 ret_val = e1000e_write_kmrn_reg(hw, 2616 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2617 data | BIT(0)); 2618 if (ret_val) 2619 return ret_val; 2620 ret_val = e1000e_read_kmrn_reg(hw, 2621 E1000_KMRNCTRLSTA_HD_CTRL, 2622 &data); 2623 if (ret_val) 2624 return ret_val; 2625 data &= ~(0xF << 8); 2626 data |= (0xB << 8); 2627 ret_val = e1000e_write_kmrn_reg(hw, 2628 E1000_KMRNCTRLSTA_HD_CTRL, 2629 data); 2630 if (ret_val) 2631 return ret_val; 2632 2633 /* Enable jumbo frame workaround in the PHY */ 2634 e1e_rphy(hw, PHY_REG(769, 23), &data); 2635 data &= ~(0x7F << 5); 2636 data |= (0x37 << 5); 2637 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2638 if (ret_val) 2639 return ret_val; 2640 e1e_rphy(hw, PHY_REG(769, 16), &data); 2641 data &= ~BIT(13); 2642 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2643 if (ret_val) 2644 return ret_val; 2645 e1e_rphy(hw, PHY_REG(776, 20), &data); 2646 data &= ~(0x3FF << 2); 2647 data |= (E1000_TX_PTR_GAP << 2); 2648 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2649 if (ret_val) 2650 return ret_val; 2651 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2652 if (ret_val) 2653 return ret_val; 2654 e1e_rphy(hw, HV_PM_CTRL, &data); 2655 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2656 if (ret_val) 2657 return ret_val; 2658 } else { 2659 /* Write MAC register values back to h/w defaults */ 2660 mac_reg = er32(FFLT_DBG); 2661 mac_reg &= ~(0xF << 14); 2662 ew32(FFLT_DBG, mac_reg); 2663 2664 mac_reg = er32(RCTL); 2665 mac_reg &= ~E1000_RCTL_SECRC; 2666 ew32(RCTL, mac_reg); 2667 2668 ret_val = e1000e_read_kmrn_reg(hw, 2669 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2670 &data); 2671 if (ret_val) 2672 return ret_val; 2673 ret_val = e1000e_write_kmrn_reg(hw, 2674 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2675 data & ~BIT(0)); 2676 if (ret_val) 2677 return ret_val; 2678 ret_val = e1000e_read_kmrn_reg(hw, 2679 E1000_KMRNCTRLSTA_HD_CTRL, 2680 &data); 2681 if (ret_val) 2682 return ret_val; 2683 data &= ~(0xF << 8); 2684 data |= (0xB << 8); 2685 ret_val = e1000e_write_kmrn_reg(hw, 2686 E1000_KMRNCTRLSTA_HD_CTRL, 2687 data); 2688 if (ret_val) 2689 return ret_val; 2690 2691 /* Write PHY register values back to h/w defaults */ 2692 e1e_rphy(hw, PHY_REG(769, 23), &data); 2693 data &= ~(0x7F << 5); 2694 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2695 if (ret_val) 2696 return ret_val; 2697 e1e_rphy(hw, PHY_REG(769, 16), &data); 2698 data |= BIT(13); 2699 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2700 if (ret_val) 2701 return ret_val; 2702 e1e_rphy(hw, PHY_REG(776, 20), &data); 2703 data &= ~(0x3FF << 2); 2704 data |= (0x8 << 2); 2705 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2706 if (ret_val) 2707 return ret_val; 2708 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2709 if (ret_val) 2710 return ret_val; 2711 e1e_rphy(hw, HV_PM_CTRL, &data); 2712 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2713 if (ret_val) 2714 return ret_val; 2715 } 2716 2717 /* re-enable Rx path after enabling/disabling workaround */ 2718 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2719 } 2720 2721 /** 2722 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2723 * @hw: pointer to the HW structure 2724 * 2725 * A series of PHY workarounds to be done after every PHY reset. 2726 **/ 2727 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2728 { 2729 s32 ret_val = 0; 2730 2731 if (hw->mac.type != e1000_pch2lan) 2732 return 0; 2733 2734 /* Set MDIO slow mode before any other MDIO access */ 2735 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2736 if (ret_val) 2737 return ret_val; 2738 2739 ret_val = hw->phy.ops.acquire(hw); 2740 if (ret_val) 2741 return ret_val; 2742 /* set MSE higher to enable link to stay up when noise is high */ 2743 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2744 if (ret_val) 2745 goto release; 2746 /* drop link after 5 times MSE threshold was reached */ 2747 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2748 release: 2749 hw->phy.ops.release(hw); 2750 2751 return ret_val; 2752 } 2753 2754 /** 2755 * e1000_k1_workaround_lv - K1 Si workaround 2756 * @hw: pointer to the HW structure 2757 * 2758 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2759 * Disable K1 in 1000Mbps and 100Mbps 2760 **/ 2761 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2762 { 2763 s32 ret_val = 0; 2764 u16 status_reg = 0; 2765 2766 if (hw->mac.type != e1000_pch2lan) 2767 return 0; 2768 2769 /* Set K1 beacon duration based on 10Mbs speed */ 2770 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2771 if (ret_val) 2772 return ret_val; 2773 2774 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2775 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2776 if (status_reg & 2777 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2778 u16 pm_phy_reg; 2779 2780 /* LV 1G/100 Packet drop issue wa */ 2781 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2782 if (ret_val) 2783 return ret_val; 2784 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2785 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2786 if (ret_val) 2787 return ret_val; 2788 } else { 2789 u32 mac_reg; 2790 2791 mac_reg = er32(FEXTNVM4); 2792 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2793 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2794 ew32(FEXTNVM4, mac_reg); 2795 } 2796 } 2797 2798 return ret_val; 2799 } 2800 2801 /** 2802 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2803 * @hw: pointer to the HW structure 2804 * @gate: boolean set to true to gate, false to ungate 2805 * 2806 * Gate/ungate the automatic PHY configuration via hardware; perform 2807 * the configuration via software instead. 2808 **/ 2809 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2810 { 2811 u32 extcnf_ctrl; 2812 2813 if (hw->mac.type < e1000_pch2lan) 2814 return; 2815 2816 extcnf_ctrl = er32(EXTCNF_CTRL); 2817 2818 if (gate) 2819 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2820 else 2821 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2822 2823 ew32(EXTCNF_CTRL, extcnf_ctrl); 2824 } 2825 2826 /** 2827 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2828 * @hw: pointer to the HW structure 2829 * 2830 * Check the appropriate indication the MAC has finished configuring the 2831 * PHY after a software reset. 2832 **/ 2833 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2834 { 2835 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2836 2837 /* Wait for basic configuration completes before proceeding */ 2838 do { 2839 data = er32(STATUS); 2840 data &= E1000_STATUS_LAN_INIT_DONE; 2841 usleep_range(100, 200); 2842 } while ((!data) && --loop); 2843 2844 /* If basic configuration is incomplete before the above loop 2845 * count reaches 0, loading the configuration from NVM will 2846 * leave the PHY in a bad state possibly resulting in no link. 2847 */ 2848 if (loop == 0) 2849 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2850 2851 /* Clear the Init Done bit for the next init event */ 2852 data = er32(STATUS); 2853 data &= ~E1000_STATUS_LAN_INIT_DONE; 2854 ew32(STATUS, data); 2855 } 2856 2857 /** 2858 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2859 * @hw: pointer to the HW structure 2860 **/ 2861 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2862 { 2863 s32 ret_val = 0; 2864 u16 reg; 2865 2866 if (hw->phy.ops.check_reset_block(hw)) 2867 return 0; 2868 2869 /* Allow time for h/w to get to quiescent state after reset */ 2870 usleep_range(10000, 11000); 2871 2872 /* Perform any necessary post-reset workarounds */ 2873 switch (hw->mac.type) { 2874 case e1000_pchlan: 2875 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2876 if (ret_val) 2877 return ret_val; 2878 break; 2879 case e1000_pch2lan: 2880 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2881 if (ret_val) 2882 return ret_val; 2883 break; 2884 default: 2885 break; 2886 } 2887 2888 /* Clear the host wakeup bit after lcd reset */ 2889 if (hw->mac.type >= e1000_pchlan) { 2890 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2891 reg &= ~BM_WUC_HOST_WU_BIT; 2892 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2893 } 2894 2895 /* Configure the LCD with the extended configuration region in NVM */ 2896 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2897 if (ret_val) 2898 return ret_val; 2899 2900 /* Configure the LCD with the OEM bits in NVM */ 2901 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2902 2903 if (hw->mac.type == e1000_pch2lan) { 2904 /* Ungate automatic PHY configuration on non-managed 82579 */ 2905 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2906 usleep_range(10000, 11000); 2907 e1000_gate_hw_phy_config_ich8lan(hw, false); 2908 } 2909 2910 /* Set EEE LPI Update Timer to 200usec */ 2911 ret_val = hw->phy.ops.acquire(hw); 2912 if (ret_val) 2913 return ret_val; 2914 ret_val = e1000_write_emi_reg_locked(hw, 2915 I82579_LPI_UPDATE_TIMER, 2916 0x1387); 2917 hw->phy.ops.release(hw); 2918 } 2919 2920 return ret_val; 2921 } 2922 2923 /** 2924 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2925 * @hw: pointer to the HW structure 2926 * 2927 * Resets the PHY 2928 * This is a function pointer entry point called by drivers 2929 * or other shared routines. 2930 **/ 2931 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2932 { 2933 s32 ret_val = 0; 2934 2935 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2936 if ((hw->mac.type == e1000_pch2lan) && 2937 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2938 e1000_gate_hw_phy_config_ich8lan(hw, true); 2939 2940 ret_val = e1000e_phy_hw_reset_generic(hw); 2941 if (ret_val) 2942 return ret_val; 2943 2944 return e1000_post_phy_reset_ich8lan(hw); 2945 } 2946 2947 /** 2948 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2949 * @hw: pointer to the HW structure 2950 * @active: true to enable LPLU, false to disable 2951 * 2952 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2953 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2954 * the phy speed. This function will manually set the LPLU bit and restart 2955 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2956 * since it configures the same bit. 2957 **/ 2958 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2959 { 2960 s32 ret_val; 2961 u16 oem_reg; 2962 2963 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2964 if (ret_val) 2965 return ret_val; 2966 2967 if (active) 2968 oem_reg |= HV_OEM_BITS_LPLU; 2969 else 2970 oem_reg &= ~HV_OEM_BITS_LPLU; 2971 2972 if (!hw->phy.ops.check_reset_block(hw)) 2973 oem_reg |= HV_OEM_BITS_RESTART_AN; 2974 2975 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2976 } 2977 2978 /** 2979 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2980 * @hw: pointer to the HW structure 2981 * @active: true to enable LPLU, false to disable 2982 * 2983 * Sets the LPLU D0 state according to the active flag. When 2984 * activating LPLU this function also disables smart speed 2985 * and vice versa. LPLU will not be activated unless the 2986 * device autonegotiation advertisement meets standards of 2987 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2988 * This is a function pointer entry point only called by 2989 * PHY setup routines. 2990 **/ 2991 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2992 { 2993 struct e1000_phy_info *phy = &hw->phy; 2994 u32 phy_ctrl; 2995 s32 ret_val = 0; 2996 u16 data; 2997 2998 if (phy->type == e1000_phy_ife) 2999 return 0; 3000 3001 phy_ctrl = er32(PHY_CTRL); 3002 3003 if (active) { 3004 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3005 ew32(PHY_CTRL, phy_ctrl); 3006 3007 if (phy->type != e1000_phy_igp_3) 3008 return 0; 3009 3010 /* Call gig speed drop workaround on LPLU before accessing 3011 * any PHY registers 3012 */ 3013 if (hw->mac.type == e1000_ich8lan) 3014 e1000e_gig_downshift_workaround_ich8lan(hw); 3015 3016 /* When LPLU is enabled, we should disable SmartSpeed */ 3017 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3018 if (ret_val) 3019 return ret_val; 3020 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3021 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3022 if (ret_val) 3023 return ret_val; 3024 } else { 3025 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3026 ew32(PHY_CTRL, phy_ctrl); 3027 3028 if (phy->type != e1000_phy_igp_3) 3029 return 0; 3030 3031 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3032 * during Dx states where the power conservation is most 3033 * important. During driver activity we should enable 3034 * SmartSpeed, so performance is maintained. 3035 */ 3036 if (phy->smart_speed == e1000_smart_speed_on) { 3037 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3038 &data); 3039 if (ret_val) 3040 return ret_val; 3041 3042 data |= IGP01E1000_PSCFR_SMART_SPEED; 3043 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3044 data); 3045 if (ret_val) 3046 return ret_val; 3047 } else if (phy->smart_speed == e1000_smart_speed_off) { 3048 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3049 &data); 3050 if (ret_val) 3051 return ret_val; 3052 3053 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3054 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3055 data); 3056 if (ret_val) 3057 return ret_val; 3058 } 3059 } 3060 3061 return 0; 3062 } 3063 3064 /** 3065 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3066 * @hw: pointer to the HW structure 3067 * @active: true to enable LPLU, false to disable 3068 * 3069 * Sets the LPLU D3 state according to the active flag. When 3070 * activating LPLU this function also disables smart speed 3071 * and vice versa. LPLU will not be activated unless the 3072 * device autonegotiation advertisement meets standards of 3073 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3074 * This is a function pointer entry point only called by 3075 * PHY setup routines. 3076 **/ 3077 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3078 { 3079 struct e1000_phy_info *phy = &hw->phy; 3080 u32 phy_ctrl; 3081 s32 ret_val = 0; 3082 u16 data; 3083 3084 phy_ctrl = er32(PHY_CTRL); 3085 3086 if (!active) { 3087 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3088 ew32(PHY_CTRL, phy_ctrl); 3089 3090 if (phy->type != e1000_phy_igp_3) 3091 return 0; 3092 3093 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3094 * during Dx states where the power conservation is most 3095 * important. During driver activity we should enable 3096 * SmartSpeed, so performance is maintained. 3097 */ 3098 if (phy->smart_speed == e1000_smart_speed_on) { 3099 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3100 &data); 3101 if (ret_val) 3102 return ret_val; 3103 3104 data |= IGP01E1000_PSCFR_SMART_SPEED; 3105 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3106 data); 3107 if (ret_val) 3108 return ret_val; 3109 } else if (phy->smart_speed == e1000_smart_speed_off) { 3110 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3111 &data); 3112 if (ret_val) 3113 return ret_val; 3114 3115 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3116 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3117 data); 3118 if (ret_val) 3119 return ret_val; 3120 } 3121 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3122 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3123 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3124 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3125 ew32(PHY_CTRL, phy_ctrl); 3126 3127 if (phy->type != e1000_phy_igp_3) 3128 return 0; 3129 3130 /* Call gig speed drop workaround on LPLU before accessing 3131 * any PHY registers 3132 */ 3133 if (hw->mac.type == e1000_ich8lan) 3134 e1000e_gig_downshift_workaround_ich8lan(hw); 3135 3136 /* When LPLU is enabled, we should disable SmartSpeed */ 3137 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3138 if (ret_val) 3139 return ret_val; 3140 3141 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3142 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3143 } 3144 3145 return ret_val; 3146 } 3147 3148 /** 3149 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3150 * @hw: pointer to the HW structure 3151 * @bank: pointer to the variable that returns the active bank 3152 * 3153 * Reads signature byte from the NVM using the flash access registers. 3154 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3155 **/ 3156 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3157 { 3158 u32 eecd; 3159 struct e1000_nvm_info *nvm = &hw->nvm; 3160 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3161 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3162 u32 nvm_dword = 0; 3163 u8 sig_byte = 0; 3164 s32 ret_val; 3165 3166 switch (hw->mac.type) { 3167 case e1000_pch_spt: 3168 case e1000_pch_cnp: 3169 case e1000_pch_tgp: 3170 case e1000_pch_adp: 3171 case e1000_pch_mtp: 3172 case e1000_pch_lnp: 3173 bank1_offset = nvm->flash_bank_size; 3174 act_offset = E1000_ICH_NVM_SIG_WORD; 3175 3176 /* set bank to 0 in case flash read fails */ 3177 *bank = 0; 3178 3179 /* Check bank 0 */ 3180 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3181 &nvm_dword); 3182 if (ret_val) 3183 return ret_val; 3184 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3185 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3186 E1000_ICH_NVM_SIG_VALUE) { 3187 *bank = 0; 3188 return 0; 3189 } 3190 3191 /* Check bank 1 */ 3192 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3193 bank1_offset, 3194 &nvm_dword); 3195 if (ret_val) 3196 return ret_val; 3197 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3198 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3199 E1000_ICH_NVM_SIG_VALUE) { 3200 *bank = 1; 3201 return 0; 3202 } 3203 3204 e_dbg("ERROR: No valid NVM bank present\n"); 3205 return -E1000_ERR_NVM; 3206 case e1000_ich8lan: 3207 case e1000_ich9lan: 3208 eecd = er32(EECD); 3209 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3210 E1000_EECD_SEC1VAL_VALID_MASK) { 3211 if (eecd & E1000_EECD_SEC1VAL) 3212 *bank = 1; 3213 else 3214 *bank = 0; 3215 3216 return 0; 3217 } 3218 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3219 fallthrough; 3220 default: 3221 /* set bank to 0 in case flash read fails */ 3222 *bank = 0; 3223 3224 /* Check bank 0 */ 3225 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3226 &sig_byte); 3227 if (ret_val) 3228 return ret_val; 3229 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3230 E1000_ICH_NVM_SIG_VALUE) { 3231 *bank = 0; 3232 return 0; 3233 } 3234 3235 /* Check bank 1 */ 3236 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3237 bank1_offset, 3238 &sig_byte); 3239 if (ret_val) 3240 return ret_val; 3241 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3242 E1000_ICH_NVM_SIG_VALUE) { 3243 *bank = 1; 3244 return 0; 3245 } 3246 3247 e_dbg("ERROR: No valid NVM bank present\n"); 3248 return -E1000_ERR_NVM; 3249 } 3250 } 3251 3252 /** 3253 * e1000_read_nvm_spt - NVM access for SPT 3254 * @hw: pointer to the HW structure 3255 * @offset: The offset (in bytes) of the word(s) to read. 3256 * @words: Size of data to read in words. 3257 * @data: pointer to the word(s) to read at offset. 3258 * 3259 * Reads a word(s) from the NVM 3260 **/ 3261 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3262 u16 *data) 3263 { 3264 struct e1000_nvm_info *nvm = &hw->nvm; 3265 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3266 u32 act_offset; 3267 s32 ret_val = 0; 3268 u32 bank = 0; 3269 u32 dword = 0; 3270 u16 offset_to_read; 3271 u16 i; 3272 3273 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3274 (words == 0)) { 3275 e_dbg("nvm parameter(s) out of bounds\n"); 3276 ret_val = -E1000_ERR_NVM; 3277 goto out; 3278 } 3279 3280 nvm->ops.acquire(hw); 3281 3282 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3283 if (ret_val) { 3284 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3285 bank = 0; 3286 } 3287 3288 act_offset = (bank) ? nvm->flash_bank_size : 0; 3289 act_offset += offset; 3290 3291 ret_val = 0; 3292 3293 for (i = 0; i < words; i += 2) { 3294 if (words - i == 1) { 3295 if (dev_spec->shadow_ram[offset + i].modified) { 3296 data[i] = 3297 dev_spec->shadow_ram[offset + i].value; 3298 } else { 3299 offset_to_read = act_offset + i - 3300 ((act_offset + i) % 2); 3301 ret_val = 3302 e1000_read_flash_dword_ich8lan(hw, 3303 offset_to_read, 3304 &dword); 3305 if (ret_val) 3306 break; 3307 if ((act_offset + i) % 2 == 0) 3308 data[i] = (u16)(dword & 0xFFFF); 3309 else 3310 data[i] = (u16)((dword >> 16) & 0xFFFF); 3311 } 3312 } else { 3313 offset_to_read = act_offset + i; 3314 if (!(dev_spec->shadow_ram[offset + i].modified) || 3315 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3316 ret_val = 3317 e1000_read_flash_dword_ich8lan(hw, 3318 offset_to_read, 3319 &dword); 3320 if (ret_val) 3321 break; 3322 } 3323 if (dev_spec->shadow_ram[offset + i].modified) 3324 data[i] = 3325 dev_spec->shadow_ram[offset + i].value; 3326 else 3327 data[i] = (u16)(dword & 0xFFFF); 3328 if (dev_spec->shadow_ram[offset + i].modified) 3329 data[i + 1] = 3330 dev_spec->shadow_ram[offset + i + 1].value; 3331 else 3332 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3333 } 3334 } 3335 3336 nvm->ops.release(hw); 3337 3338 out: 3339 if (ret_val) 3340 e_dbg("NVM read error: %d\n", ret_val); 3341 3342 return ret_val; 3343 } 3344 3345 /** 3346 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3347 * @hw: pointer to the HW structure 3348 * @offset: The offset (in bytes) of the word(s) to read. 3349 * @words: Size of data to read in words 3350 * @data: Pointer to the word(s) to read at offset. 3351 * 3352 * Reads a word(s) from the NVM using the flash access registers. 3353 **/ 3354 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3355 u16 *data) 3356 { 3357 struct e1000_nvm_info *nvm = &hw->nvm; 3358 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3359 u32 act_offset; 3360 s32 ret_val = 0; 3361 u32 bank = 0; 3362 u16 i, word; 3363 3364 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3365 (words == 0)) { 3366 e_dbg("nvm parameter(s) out of bounds\n"); 3367 ret_val = -E1000_ERR_NVM; 3368 goto out; 3369 } 3370 3371 nvm->ops.acquire(hw); 3372 3373 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3374 if (ret_val) { 3375 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3376 bank = 0; 3377 } 3378 3379 act_offset = (bank) ? nvm->flash_bank_size : 0; 3380 act_offset += offset; 3381 3382 ret_val = 0; 3383 for (i = 0; i < words; i++) { 3384 if (dev_spec->shadow_ram[offset + i].modified) { 3385 data[i] = dev_spec->shadow_ram[offset + i].value; 3386 } else { 3387 ret_val = e1000_read_flash_word_ich8lan(hw, 3388 act_offset + i, 3389 &word); 3390 if (ret_val) 3391 break; 3392 data[i] = word; 3393 } 3394 } 3395 3396 nvm->ops.release(hw); 3397 3398 out: 3399 if (ret_val) 3400 e_dbg("NVM read error: %d\n", ret_val); 3401 3402 return ret_val; 3403 } 3404 3405 /** 3406 * e1000_flash_cycle_init_ich8lan - Initialize flash 3407 * @hw: pointer to the HW structure 3408 * 3409 * This function does initial flash setup so that a new read/write/erase cycle 3410 * can be started. 3411 **/ 3412 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3413 { 3414 union ich8_hws_flash_status hsfsts; 3415 s32 ret_val = -E1000_ERR_NVM; 3416 3417 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3418 3419 /* Check if the flash descriptor is valid */ 3420 if (!hsfsts.hsf_status.fldesvalid) { 3421 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3422 return -E1000_ERR_NVM; 3423 } 3424 3425 /* Clear FCERR and DAEL in hw status by writing 1 */ 3426 hsfsts.hsf_status.flcerr = 1; 3427 hsfsts.hsf_status.dael = 1; 3428 if (hw->mac.type >= e1000_pch_spt) 3429 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3430 else 3431 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3432 3433 /* Either we should have a hardware SPI cycle in progress 3434 * bit to check against, in order to start a new cycle or 3435 * FDONE bit should be changed in the hardware so that it 3436 * is 1 after hardware reset, which can then be used as an 3437 * indication whether a cycle is in progress or has been 3438 * completed. 3439 */ 3440 3441 if (!hsfsts.hsf_status.flcinprog) { 3442 /* There is no cycle running at present, 3443 * so we can start a cycle. 3444 * Begin by setting Flash Cycle Done. 3445 */ 3446 hsfsts.hsf_status.flcdone = 1; 3447 if (hw->mac.type >= e1000_pch_spt) 3448 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3449 else 3450 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3451 ret_val = 0; 3452 } else { 3453 s32 i; 3454 3455 /* Otherwise poll for sometime so the current 3456 * cycle has a chance to end before giving up. 3457 */ 3458 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3459 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3460 if (!hsfsts.hsf_status.flcinprog) { 3461 ret_val = 0; 3462 break; 3463 } 3464 udelay(1); 3465 } 3466 if (!ret_val) { 3467 /* Successful in waiting for previous cycle to timeout, 3468 * now set the Flash Cycle Done. 3469 */ 3470 hsfsts.hsf_status.flcdone = 1; 3471 if (hw->mac.type >= e1000_pch_spt) 3472 ew32flash(ICH_FLASH_HSFSTS, 3473 hsfsts.regval & 0xFFFF); 3474 else 3475 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3476 } else { 3477 e_dbg("Flash controller busy, cannot get access\n"); 3478 } 3479 } 3480 3481 return ret_val; 3482 } 3483 3484 /** 3485 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3486 * @hw: pointer to the HW structure 3487 * @timeout: maximum time to wait for completion 3488 * 3489 * This function starts a flash cycle and waits for its completion. 3490 **/ 3491 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3492 { 3493 union ich8_hws_flash_ctrl hsflctl; 3494 union ich8_hws_flash_status hsfsts; 3495 u32 i = 0; 3496 3497 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3498 if (hw->mac.type >= e1000_pch_spt) 3499 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3500 else 3501 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3502 hsflctl.hsf_ctrl.flcgo = 1; 3503 3504 if (hw->mac.type >= e1000_pch_spt) 3505 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3506 else 3507 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3508 3509 /* wait till FDONE bit is set to 1 */ 3510 do { 3511 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3512 if (hsfsts.hsf_status.flcdone) 3513 break; 3514 udelay(1); 3515 } while (i++ < timeout); 3516 3517 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3518 return 0; 3519 3520 return -E1000_ERR_NVM; 3521 } 3522 3523 /** 3524 * e1000_read_flash_dword_ich8lan - Read dword from flash 3525 * @hw: pointer to the HW structure 3526 * @offset: offset to data location 3527 * @data: pointer to the location for storing the data 3528 * 3529 * Reads the flash dword at offset into data. Offset is converted 3530 * to bytes before read. 3531 **/ 3532 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3533 u32 *data) 3534 { 3535 /* Must convert word offset into bytes. */ 3536 offset <<= 1; 3537 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3538 } 3539 3540 /** 3541 * e1000_read_flash_word_ich8lan - Read word from flash 3542 * @hw: pointer to the HW structure 3543 * @offset: offset to data location 3544 * @data: pointer to the location for storing the data 3545 * 3546 * Reads the flash word at offset into data. Offset is converted 3547 * to bytes before read. 3548 **/ 3549 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3550 u16 *data) 3551 { 3552 /* Must convert offset into bytes. */ 3553 offset <<= 1; 3554 3555 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3556 } 3557 3558 /** 3559 * e1000_read_flash_byte_ich8lan - Read byte from flash 3560 * @hw: pointer to the HW structure 3561 * @offset: The offset of the byte to read. 3562 * @data: Pointer to a byte to store the value read. 3563 * 3564 * Reads a single byte from the NVM using the flash access registers. 3565 **/ 3566 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3567 u8 *data) 3568 { 3569 s32 ret_val; 3570 u16 word = 0; 3571 3572 /* In SPT, only 32 bits access is supported, 3573 * so this function should not be called. 3574 */ 3575 if (hw->mac.type >= e1000_pch_spt) 3576 return -E1000_ERR_NVM; 3577 else 3578 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3579 3580 if (ret_val) 3581 return ret_val; 3582 3583 *data = (u8)word; 3584 3585 return 0; 3586 } 3587 3588 /** 3589 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3590 * @hw: pointer to the HW structure 3591 * @offset: The offset (in bytes) of the byte or word to read. 3592 * @size: Size of data to read, 1=byte 2=word 3593 * @data: Pointer to the word to store the value read. 3594 * 3595 * Reads a byte or word from the NVM using the flash access registers. 3596 **/ 3597 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3598 u8 size, u16 *data) 3599 { 3600 union ich8_hws_flash_status hsfsts; 3601 union ich8_hws_flash_ctrl hsflctl; 3602 u32 flash_linear_addr; 3603 u32 flash_data = 0; 3604 s32 ret_val = -E1000_ERR_NVM; 3605 u8 count = 0; 3606 3607 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3608 return -E1000_ERR_NVM; 3609 3610 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3611 hw->nvm.flash_base_addr); 3612 3613 do { 3614 udelay(1); 3615 /* Steps */ 3616 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3617 if (ret_val) 3618 break; 3619 3620 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3621 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3622 hsflctl.hsf_ctrl.fldbcount = size - 1; 3623 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3624 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3625 3626 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3627 3628 ret_val = 3629 e1000_flash_cycle_ich8lan(hw, 3630 ICH_FLASH_READ_COMMAND_TIMEOUT); 3631 3632 /* Check if FCERR is set to 1, if set to 1, clear it 3633 * and try the whole sequence a few more times, else 3634 * read in (shift in) the Flash Data0, the order is 3635 * least significant byte first msb to lsb 3636 */ 3637 if (!ret_val) { 3638 flash_data = er32flash(ICH_FLASH_FDATA0); 3639 if (size == 1) 3640 *data = (u8)(flash_data & 0x000000FF); 3641 else if (size == 2) 3642 *data = (u16)(flash_data & 0x0000FFFF); 3643 break; 3644 } else { 3645 /* If we've gotten here, then things are probably 3646 * completely hosed, but if the error condition is 3647 * detected, it won't hurt to give it another try... 3648 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3649 */ 3650 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3651 if (hsfsts.hsf_status.flcerr) { 3652 /* Repeat for some time before giving up. */ 3653 continue; 3654 } else if (!hsfsts.hsf_status.flcdone) { 3655 e_dbg("Timeout error - flash cycle did not complete.\n"); 3656 break; 3657 } 3658 } 3659 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3660 3661 return ret_val; 3662 } 3663 3664 /** 3665 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3666 * @hw: pointer to the HW structure 3667 * @offset: The offset (in bytes) of the dword to read. 3668 * @data: Pointer to the dword to store the value read. 3669 * 3670 * Reads a byte or word from the NVM using the flash access registers. 3671 **/ 3672 3673 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3674 u32 *data) 3675 { 3676 union ich8_hws_flash_status hsfsts; 3677 union ich8_hws_flash_ctrl hsflctl; 3678 u32 flash_linear_addr; 3679 s32 ret_val = -E1000_ERR_NVM; 3680 u8 count = 0; 3681 3682 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3683 return -E1000_ERR_NVM; 3684 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3685 hw->nvm.flash_base_addr); 3686 3687 do { 3688 udelay(1); 3689 /* Steps */ 3690 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3691 if (ret_val) 3692 break; 3693 /* In SPT, This register is in Lan memory space, not flash. 3694 * Therefore, only 32 bit access is supported 3695 */ 3696 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3697 3698 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3699 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3700 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3701 /* In SPT, This register is in Lan memory space, not flash. 3702 * Therefore, only 32 bit access is supported 3703 */ 3704 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3705 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3706 3707 ret_val = 3708 e1000_flash_cycle_ich8lan(hw, 3709 ICH_FLASH_READ_COMMAND_TIMEOUT); 3710 3711 /* Check if FCERR is set to 1, if set to 1, clear it 3712 * and try the whole sequence a few more times, else 3713 * read in (shift in) the Flash Data0, the order is 3714 * least significant byte first msb to lsb 3715 */ 3716 if (!ret_val) { 3717 *data = er32flash(ICH_FLASH_FDATA0); 3718 break; 3719 } else { 3720 /* If we've gotten here, then things are probably 3721 * completely hosed, but if the error condition is 3722 * detected, it won't hurt to give it another try... 3723 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3724 */ 3725 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3726 if (hsfsts.hsf_status.flcerr) { 3727 /* Repeat for some time before giving up. */ 3728 continue; 3729 } else if (!hsfsts.hsf_status.flcdone) { 3730 e_dbg("Timeout error - flash cycle did not complete.\n"); 3731 break; 3732 } 3733 } 3734 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3735 3736 return ret_val; 3737 } 3738 3739 /** 3740 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3741 * @hw: pointer to the HW structure 3742 * @offset: The offset (in bytes) of the word(s) to write. 3743 * @words: Size of data to write in words 3744 * @data: Pointer to the word(s) to write at offset. 3745 * 3746 * Writes a byte or word to the NVM using the flash access registers. 3747 **/ 3748 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3749 u16 *data) 3750 { 3751 struct e1000_nvm_info *nvm = &hw->nvm; 3752 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3753 u16 i; 3754 3755 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3756 (words == 0)) { 3757 e_dbg("nvm parameter(s) out of bounds\n"); 3758 return -E1000_ERR_NVM; 3759 } 3760 3761 nvm->ops.acquire(hw); 3762 3763 for (i = 0; i < words; i++) { 3764 dev_spec->shadow_ram[offset + i].modified = true; 3765 dev_spec->shadow_ram[offset + i].value = data[i]; 3766 } 3767 3768 nvm->ops.release(hw); 3769 3770 return 0; 3771 } 3772 3773 /** 3774 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3775 * @hw: pointer to the HW structure 3776 * 3777 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3778 * which writes the checksum to the shadow ram. The changes in the shadow 3779 * ram are then committed to the EEPROM by processing each bank at a time 3780 * checking for the modified bit and writing only the pending changes. 3781 * After a successful commit, the shadow ram is cleared and is ready for 3782 * future writes. 3783 **/ 3784 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3785 { 3786 struct e1000_nvm_info *nvm = &hw->nvm; 3787 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3788 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3789 s32 ret_val; 3790 u32 dword = 0; 3791 3792 ret_val = e1000e_update_nvm_checksum_generic(hw); 3793 if (ret_val) 3794 goto out; 3795 3796 if (nvm->type != e1000_nvm_flash_sw) 3797 goto out; 3798 3799 nvm->ops.acquire(hw); 3800 3801 /* We're writing to the opposite bank so if we're on bank 1, 3802 * write to bank 0 etc. We also need to erase the segment that 3803 * is going to be written 3804 */ 3805 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3806 if (ret_val) { 3807 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3808 bank = 0; 3809 } 3810 3811 if (bank == 0) { 3812 new_bank_offset = nvm->flash_bank_size; 3813 old_bank_offset = 0; 3814 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3815 if (ret_val) 3816 goto release; 3817 } else { 3818 old_bank_offset = nvm->flash_bank_size; 3819 new_bank_offset = 0; 3820 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3821 if (ret_val) 3822 goto release; 3823 } 3824 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3825 /* Determine whether to write the value stored 3826 * in the other NVM bank or a modified value stored 3827 * in the shadow RAM 3828 */ 3829 ret_val = e1000_read_flash_dword_ich8lan(hw, 3830 i + old_bank_offset, 3831 &dword); 3832 3833 if (dev_spec->shadow_ram[i].modified) { 3834 dword &= 0xffff0000; 3835 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3836 } 3837 if (dev_spec->shadow_ram[i + 1].modified) { 3838 dword &= 0x0000ffff; 3839 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3840 << 16); 3841 } 3842 if (ret_val) 3843 break; 3844 3845 /* If the word is 0x13, then make sure the signature bits 3846 * (15:14) are 11b until the commit has completed. 3847 * This will allow us to write 10b which indicates the 3848 * signature is valid. We want to do this after the write 3849 * has completed so that we don't mark the segment valid 3850 * while the write is still in progress 3851 */ 3852 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3853 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3854 3855 /* Convert offset to bytes. */ 3856 act_offset = (i + new_bank_offset) << 1; 3857 3858 usleep_range(100, 200); 3859 3860 /* Write the data to the new bank. Offset in words */ 3861 act_offset = i + new_bank_offset; 3862 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3863 dword); 3864 if (ret_val) 3865 break; 3866 } 3867 3868 /* Don't bother writing the segment valid bits if sector 3869 * programming failed. 3870 */ 3871 if (ret_val) { 3872 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3873 e_dbg("Flash commit failed.\n"); 3874 goto release; 3875 } 3876 3877 /* Finally validate the new segment by setting bit 15:14 3878 * to 10b in word 0x13 , this can be done without an 3879 * erase as well since these bits are 11 to start with 3880 * and we need to change bit 14 to 0b 3881 */ 3882 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3883 3884 /*offset in words but we read dword */ 3885 --act_offset; 3886 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3887 3888 if (ret_val) 3889 goto release; 3890 3891 dword &= 0xBFFFFFFF; 3892 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3893 3894 if (ret_val) 3895 goto release; 3896 3897 /* offset in words but we read dword */ 3898 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3899 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3900 3901 if (ret_val) 3902 goto release; 3903 3904 dword &= 0x00FFFFFF; 3905 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3906 3907 if (ret_val) 3908 goto release; 3909 3910 /* Great! Everything worked, we can now clear the cached entries. */ 3911 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3912 dev_spec->shadow_ram[i].modified = false; 3913 dev_spec->shadow_ram[i].value = 0xFFFF; 3914 } 3915 3916 release: 3917 nvm->ops.release(hw); 3918 3919 /* Reload the EEPROM, or else modifications will not appear 3920 * until after the next adapter reset. 3921 */ 3922 if (!ret_val) { 3923 nvm->ops.reload(hw); 3924 usleep_range(10000, 11000); 3925 } 3926 3927 out: 3928 if (ret_val) 3929 e_dbg("NVM update error: %d\n", ret_val); 3930 3931 return ret_val; 3932 } 3933 3934 /** 3935 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3936 * @hw: pointer to the HW structure 3937 * 3938 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3939 * which writes the checksum to the shadow ram. The changes in the shadow 3940 * ram are then committed to the EEPROM by processing each bank at a time 3941 * checking for the modified bit and writing only the pending changes. 3942 * After a successful commit, the shadow ram is cleared and is ready for 3943 * future writes. 3944 **/ 3945 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3946 { 3947 struct e1000_nvm_info *nvm = &hw->nvm; 3948 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3949 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3950 s32 ret_val; 3951 u16 data = 0; 3952 3953 ret_val = e1000e_update_nvm_checksum_generic(hw); 3954 if (ret_val) 3955 goto out; 3956 3957 if (nvm->type != e1000_nvm_flash_sw) 3958 goto out; 3959 3960 nvm->ops.acquire(hw); 3961 3962 /* We're writing to the opposite bank so if we're on bank 1, 3963 * write to bank 0 etc. We also need to erase the segment that 3964 * is going to be written 3965 */ 3966 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3967 if (ret_val) { 3968 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3969 bank = 0; 3970 } 3971 3972 if (bank == 0) { 3973 new_bank_offset = nvm->flash_bank_size; 3974 old_bank_offset = 0; 3975 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3976 if (ret_val) 3977 goto release; 3978 } else { 3979 old_bank_offset = nvm->flash_bank_size; 3980 new_bank_offset = 0; 3981 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3982 if (ret_val) 3983 goto release; 3984 } 3985 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3986 if (dev_spec->shadow_ram[i].modified) { 3987 data = dev_spec->shadow_ram[i].value; 3988 } else { 3989 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3990 old_bank_offset, 3991 &data); 3992 if (ret_val) 3993 break; 3994 } 3995 3996 /* If the word is 0x13, then make sure the signature bits 3997 * (15:14) are 11b until the commit has completed. 3998 * This will allow us to write 10b which indicates the 3999 * signature is valid. We want to do this after the write 4000 * has completed so that we don't mark the segment valid 4001 * while the write is still in progress 4002 */ 4003 if (i == E1000_ICH_NVM_SIG_WORD) 4004 data |= E1000_ICH_NVM_SIG_MASK; 4005 4006 /* Convert offset to bytes. */ 4007 act_offset = (i + new_bank_offset) << 1; 4008 4009 usleep_range(100, 200); 4010 /* Write the bytes to the new bank. */ 4011 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4012 act_offset, 4013 (u8)data); 4014 if (ret_val) 4015 break; 4016 4017 usleep_range(100, 200); 4018 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4019 act_offset + 1, 4020 (u8)(data >> 8)); 4021 if (ret_val) 4022 break; 4023 } 4024 4025 /* Don't bother writing the segment valid bits if sector 4026 * programming failed. 4027 */ 4028 if (ret_val) { 4029 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4030 e_dbg("Flash commit failed.\n"); 4031 goto release; 4032 } 4033 4034 /* Finally validate the new segment by setting bit 15:14 4035 * to 10b in word 0x13 , this can be done without an 4036 * erase as well since these bits are 11 to start with 4037 * and we need to change bit 14 to 0b 4038 */ 4039 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4040 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4041 if (ret_val) 4042 goto release; 4043 4044 data &= 0xBFFF; 4045 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4046 act_offset * 2 + 1, 4047 (u8)(data >> 8)); 4048 if (ret_val) 4049 goto release; 4050 4051 /* And invalidate the previously valid segment by setting 4052 * its signature word (0x13) high_byte to 0b. This can be 4053 * done without an erase because flash erase sets all bits 4054 * to 1's. We can write 1's to 0's without an erase 4055 */ 4056 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4057 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4058 if (ret_val) 4059 goto release; 4060 4061 /* Great! Everything worked, we can now clear the cached entries. */ 4062 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4063 dev_spec->shadow_ram[i].modified = false; 4064 dev_spec->shadow_ram[i].value = 0xFFFF; 4065 } 4066 4067 release: 4068 nvm->ops.release(hw); 4069 4070 /* Reload the EEPROM, or else modifications will not appear 4071 * until after the next adapter reset. 4072 */ 4073 if (!ret_val) { 4074 nvm->ops.reload(hw); 4075 usleep_range(10000, 11000); 4076 } 4077 4078 out: 4079 if (ret_val) 4080 e_dbg("NVM update error: %d\n", ret_val); 4081 4082 return ret_val; 4083 } 4084 4085 /** 4086 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4087 * @hw: pointer to the HW structure 4088 * 4089 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4090 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4091 * calculated, in which case we need to calculate the checksum and set bit 6. 4092 **/ 4093 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4094 { 4095 s32 ret_val; 4096 u16 data; 4097 u16 word; 4098 u16 valid_csum_mask; 4099 4100 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4101 * the checksum needs to be fixed. This bit is an indication that 4102 * the NVM was prepared by OEM software and did not calculate 4103 * the checksum...a likely scenario. 4104 */ 4105 switch (hw->mac.type) { 4106 case e1000_pch_lpt: 4107 case e1000_pch_spt: 4108 case e1000_pch_cnp: 4109 case e1000_pch_tgp: 4110 case e1000_pch_adp: 4111 case e1000_pch_mtp: 4112 case e1000_pch_lnp: 4113 word = NVM_COMPAT; 4114 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4115 break; 4116 default: 4117 word = NVM_FUTURE_INIT_WORD1; 4118 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4119 break; 4120 } 4121 4122 ret_val = e1000_read_nvm(hw, word, 1, &data); 4123 if (ret_val) 4124 return ret_val; 4125 4126 if (!(data & valid_csum_mask)) { 4127 data |= valid_csum_mask; 4128 ret_val = e1000_write_nvm(hw, word, 1, &data); 4129 if (ret_val) 4130 return ret_val; 4131 ret_val = e1000e_update_nvm_checksum(hw); 4132 if (ret_val) 4133 return ret_val; 4134 } 4135 4136 return e1000e_validate_nvm_checksum_generic(hw); 4137 } 4138 4139 /** 4140 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4141 * @hw: pointer to the HW structure 4142 * 4143 * To prevent malicious write/erase of the NVM, set it to be read-only 4144 * so that the hardware ignores all write/erase cycles of the NVM via 4145 * the flash control registers. The shadow-ram copy of the NVM will 4146 * still be updated, however any updates to this copy will not stick 4147 * across driver reloads. 4148 **/ 4149 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4150 { 4151 struct e1000_nvm_info *nvm = &hw->nvm; 4152 union ich8_flash_protected_range pr0; 4153 union ich8_hws_flash_status hsfsts; 4154 u32 gfpreg; 4155 4156 nvm->ops.acquire(hw); 4157 4158 gfpreg = er32flash(ICH_FLASH_GFPREG); 4159 4160 /* Write-protect GbE Sector of NVM */ 4161 pr0.regval = er32flash(ICH_FLASH_PR0); 4162 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4163 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4164 pr0.range.wpe = true; 4165 ew32flash(ICH_FLASH_PR0, pr0.regval); 4166 4167 /* Lock down a subset of GbE Flash Control Registers, e.g. 4168 * PR0 to prevent the write-protection from being lifted. 4169 * Once FLOCKDN is set, the registers protected by it cannot 4170 * be written until FLOCKDN is cleared by a hardware reset. 4171 */ 4172 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4173 hsfsts.hsf_status.flockdn = true; 4174 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4175 4176 nvm->ops.release(hw); 4177 } 4178 4179 /** 4180 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4181 * @hw: pointer to the HW structure 4182 * @offset: The offset (in bytes) of the byte/word to read. 4183 * @size: Size of data to read, 1=byte 2=word 4184 * @data: The byte(s) to write to the NVM. 4185 * 4186 * Writes one/two bytes to the NVM using the flash access registers. 4187 **/ 4188 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4189 u8 size, u16 data) 4190 { 4191 union ich8_hws_flash_status hsfsts; 4192 union ich8_hws_flash_ctrl hsflctl; 4193 u32 flash_linear_addr; 4194 u32 flash_data = 0; 4195 s32 ret_val; 4196 u8 count = 0; 4197 4198 if (hw->mac.type >= e1000_pch_spt) { 4199 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4200 return -E1000_ERR_NVM; 4201 } else { 4202 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4203 return -E1000_ERR_NVM; 4204 } 4205 4206 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4207 hw->nvm.flash_base_addr); 4208 4209 do { 4210 udelay(1); 4211 /* Steps */ 4212 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4213 if (ret_val) 4214 break; 4215 /* In SPT, This register is in Lan memory space, not 4216 * flash. Therefore, only 32 bit access is supported 4217 */ 4218 if (hw->mac.type >= e1000_pch_spt) 4219 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4220 else 4221 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4222 4223 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4224 hsflctl.hsf_ctrl.fldbcount = size - 1; 4225 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4226 /* In SPT, This register is in Lan memory space, 4227 * not flash. Therefore, only 32 bit access is 4228 * supported 4229 */ 4230 if (hw->mac.type >= e1000_pch_spt) 4231 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4232 else 4233 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4234 4235 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4236 4237 if (size == 1) 4238 flash_data = (u32)data & 0x00FF; 4239 else 4240 flash_data = (u32)data; 4241 4242 ew32flash(ICH_FLASH_FDATA0, flash_data); 4243 4244 /* check if FCERR is set to 1 , if set to 1, clear it 4245 * and try the whole sequence a few more times else done 4246 */ 4247 ret_val = 4248 e1000_flash_cycle_ich8lan(hw, 4249 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4250 if (!ret_val) 4251 break; 4252 4253 /* If we're here, then things are most likely 4254 * completely hosed, but if the error condition 4255 * is detected, it won't hurt to give it another 4256 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4257 */ 4258 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4259 if (hsfsts.hsf_status.flcerr) 4260 /* Repeat for some time before giving up. */ 4261 continue; 4262 if (!hsfsts.hsf_status.flcdone) { 4263 e_dbg("Timeout error - flash cycle did not complete.\n"); 4264 break; 4265 } 4266 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4267 4268 return ret_val; 4269 } 4270 4271 /** 4272 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4273 * @hw: pointer to the HW structure 4274 * @offset: The offset (in bytes) of the dwords to read. 4275 * @data: The 4 bytes to write to the NVM. 4276 * 4277 * Writes one/two/four bytes to the NVM using the flash access registers. 4278 **/ 4279 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4280 u32 data) 4281 { 4282 union ich8_hws_flash_status hsfsts; 4283 union ich8_hws_flash_ctrl hsflctl; 4284 u32 flash_linear_addr; 4285 s32 ret_val; 4286 u8 count = 0; 4287 4288 if (hw->mac.type >= e1000_pch_spt) { 4289 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4290 return -E1000_ERR_NVM; 4291 } 4292 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4293 hw->nvm.flash_base_addr); 4294 do { 4295 udelay(1); 4296 /* Steps */ 4297 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4298 if (ret_val) 4299 break; 4300 4301 /* In SPT, This register is in Lan memory space, not 4302 * flash. Therefore, only 32 bit access is supported 4303 */ 4304 if (hw->mac.type >= e1000_pch_spt) 4305 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4306 >> 16; 4307 else 4308 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4309 4310 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4311 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4312 4313 /* In SPT, This register is in Lan memory space, 4314 * not flash. Therefore, only 32 bit access is 4315 * supported 4316 */ 4317 if (hw->mac.type >= e1000_pch_spt) 4318 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4319 else 4320 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4321 4322 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4323 4324 ew32flash(ICH_FLASH_FDATA0, data); 4325 4326 /* check if FCERR is set to 1 , if set to 1, clear it 4327 * and try the whole sequence a few more times else done 4328 */ 4329 ret_val = 4330 e1000_flash_cycle_ich8lan(hw, 4331 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4332 4333 if (!ret_val) 4334 break; 4335 4336 /* If we're here, then things are most likely 4337 * completely hosed, but if the error condition 4338 * is detected, it won't hurt to give it another 4339 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4340 */ 4341 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4342 4343 if (hsfsts.hsf_status.flcerr) 4344 /* Repeat for some time before giving up. */ 4345 continue; 4346 if (!hsfsts.hsf_status.flcdone) { 4347 e_dbg("Timeout error - flash cycle did not complete.\n"); 4348 break; 4349 } 4350 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4351 4352 return ret_val; 4353 } 4354 4355 /** 4356 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4357 * @hw: pointer to the HW structure 4358 * @offset: The index of the byte to read. 4359 * @data: The byte to write to the NVM. 4360 * 4361 * Writes a single byte to the NVM using the flash access registers. 4362 **/ 4363 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4364 u8 data) 4365 { 4366 u16 word = (u16)data; 4367 4368 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4369 } 4370 4371 /** 4372 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4373 * @hw: pointer to the HW structure 4374 * @offset: The offset of the word to write. 4375 * @dword: The dword to write to the NVM. 4376 * 4377 * Writes a single dword to the NVM using the flash access registers. 4378 * Goes through a retry algorithm before giving up. 4379 **/ 4380 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4381 u32 offset, u32 dword) 4382 { 4383 s32 ret_val; 4384 u16 program_retries; 4385 4386 /* Must convert word offset into bytes. */ 4387 offset <<= 1; 4388 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4389 4390 if (!ret_val) 4391 return ret_val; 4392 for (program_retries = 0; program_retries < 100; program_retries++) { 4393 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4394 usleep_range(100, 200); 4395 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4396 if (!ret_val) 4397 break; 4398 } 4399 if (program_retries == 100) 4400 return -E1000_ERR_NVM; 4401 4402 return 0; 4403 } 4404 4405 /** 4406 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4407 * @hw: pointer to the HW structure 4408 * @offset: The offset of the byte to write. 4409 * @byte: The byte to write to the NVM. 4410 * 4411 * Writes a single byte to the NVM using the flash access registers. 4412 * Goes through a retry algorithm before giving up. 4413 **/ 4414 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4415 u32 offset, u8 byte) 4416 { 4417 s32 ret_val; 4418 u16 program_retries; 4419 4420 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4421 if (!ret_val) 4422 return ret_val; 4423 4424 for (program_retries = 0; program_retries < 100; program_retries++) { 4425 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4426 usleep_range(100, 200); 4427 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4428 if (!ret_val) 4429 break; 4430 } 4431 if (program_retries == 100) 4432 return -E1000_ERR_NVM; 4433 4434 return 0; 4435 } 4436 4437 /** 4438 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4439 * @hw: pointer to the HW structure 4440 * @bank: 0 for first bank, 1 for second bank, etc. 4441 * 4442 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4443 * bank N is 4096 * N + flash_reg_addr. 4444 **/ 4445 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4446 { 4447 struct e1000_nvm_info *nvm = &hw->nvm; 4448 union ich8_hws_flash_status hsfsts; 4449 union ich8_hws_flash_ctrl hsflctl; 4450 u32 flash_linear_addr; 4451 /* bank size is in 16bit words - adjust to bytes */ 4452 u32 flash_bank_size = nvm->flash_bank_size * 2; 4453 s32 ret_val; 4454 s32 count = 0; 4455 s32 j, iteration, sector_size; 4456 4457 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4458 4459 /* Determine HW Sector size: Read BERASE bits of hw flash status 4460 * register 4461 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4462 * consecutive sectors. The start index for the nth Hw sector 4463 * can be calculated as = bank * 4096 + n * 256 4464 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4465 * The start index for the nth Hw sector can be calculated 4466 * as = bank * 4096 4467 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4468 * (ich9 only, otherwise error condition) 4469 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4470 */ 4471 switch (hsfsts.hsf_status.berasesz) { 4472 case 0: 4473 /* Hw sector size 256 */ 4474 sector_size = ICH_FLASH_SEG_SIZE_256; 4475 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4476 break; 4477 case 1: 4478 sector_size = ICH_FLASH_SEG_SIZE_4K; 4479 iteration = 1; 4480 break; 4481 case 2: 4482 sector_size = ICH_FLASH_SEG_SIZE_8K; 4483 iteration = 1; 4484 break; 4485 case 3: 4486 sector_size = ICH_FLASH_SEG_SIZE_64K; 4487 iteration = 1; 4488 break; 4489 default: 4490 return -E1000_ERR_NVM; 4491 } 4492 4493 /* Start with the base address, then add the sector offset. */ 4494 flash_linear_addr = hw->nvm.flash_base_addr; 4495 flash_linear_addr += (bank) ? flash_bank_size : 0; 4496 4497 for (j = 0; j < iteration; j++) { 4498 do { 4499 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4500 4501 /* Steps */ 4502 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4503 if (ret_val) 4504 return ret_val; 4505 4506 /* Write a value 11 (block Erase) in Flash 4507 * Cycle field in hw flash control 4508 */ 4509 if (hw->mac.type >= e1000_pch_spt) 4510 hsflctl.regval = 4511 er32flash(ICH_FLASH_HSFSTS) >> 16; 4512 else 4513 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4514 4515 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4516 if (hw->mac.type >= e1000_pch_spt) 4517 ew32flash(ICH_FLASH_HSFSTS, 4518 hsflctl.regval << 16); 4519 else 4520 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4521 4522 /* Write the last 24 bits of an index within the 4523 * block into Flash Linear address field in Flash 4524 * Address. 4525 */ 4526 flash_linear_addr += (j * sector_size); 4527 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4528 4529 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4530 if (!ret_val) 4531 break; 4532 4533 /* Check if FCERR is set to 1. If 1, 4534 * clear it and try the whole sequence 4535 * a few more times else Done 4536 */ 4537 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4538 if (hsfsts.hsf_status.flcerr) 4539 /* repeat for some time before giving up */ 4540 continue; 4541 else if (!hsfsts.hsf_status.flcdone) 4542 return ret_val; 4543 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4544 } 4545 4546 return 0; 4547 } 4548 4549 /** 4550 * e1000_valid_led_default_ich8lan - Set the default LED settings 4551 * @hw: pointer to the HW structure 4552 * @data: Pointer to the LED settings 4553 * 4554 * Reads the LED default settings from the NVM to data. If the NVM LED 4555 * settings is all 0's or F's, set the LED default to a valid LED default 4556 * setting. 4557 **/ 4558 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4559 { 4560 s32 ret_val; 4561 4562 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4563 if (ret_val) { 4564 e_dbg("NVM Read Error\n"); 4565 return ret_val; 4566 } 4567 4568 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4569 *data = ID_LED_DEFAULT_ICH8LAN; 4570 4571 return 0; 4572 } 4573 4574 /** 4575 * e1000_id_led_init_pchlan - store LED configurations 4576 * @hw: pointer to the HW structure 4577 * 4578 * PCH does not control LEDs via the LEDCTL register, rather it uses 4579 * the PHY LED configuration register. 4580 * 4581 * PCH also does not have an "always on" or "always off" mode which 4582 * complicates the ID feature. Instead of using the "on" mode to indicate 4583 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4584 * use "link_up" mode. The LEDs will still ID on request if there is no 4585 * link based on logic in e1000_led_[on|off]_pchlan(). 4586 **/ 4587 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4588 { 4589 struct e1000_mac_info *mac = &hw->mac; 4590 s32 ret_val; 4591 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4592 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4593 u16 data, i, temp, shift; 4594 4595 /* Get default ID LED modes */ 4596 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4597 if (ret_val) 4598 return ret_val; 4599 4600 mac->ledctl_default = er32(LEDCTL); 4601 mac->ledctl_mode1 = mac->ledctl_default; 4602 mac->ledctl_mode2 = mac->ledctl_default; 4603 4604 for (i = 0; i < 4; i++) { 4605 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4606 shift = (i * 5); 4607 switch (temp) { 4608 case ID_LED_ON1_DEF2: 4609 case ID_LED_ON1_ON2: 4610 case ID_LED_ON1_OFF2: 4611 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4612 mac->ledctl_mode1 |= (ledctl_on << shift); 4613 break; 4614 case ID_LED_OFF1_DEF2: 4615 case ID_LED_OFF1_ON2: 4616 case ID_LED_OFF1_OFF2: 4617 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4618 mac->ledctl_mode1 |= (ledctl_off << shift); 4619 break; 4620 default: 4621 /* Do nothing */ 4622 break; 4623 } 4624 switch (temp) { 4625 case ID_LED_DEF1_ON2: 4626 case ID_LED_ON1_ON2: 4627 case ID_LED_OFF1_ON2: 4628 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4629 mac->ledctl_mode2 |= (ledctl_on << shift); 4630 break; 4631 case ID_LED_DEF1_OFF2: 4632 case ID_LED_ON1_OFF2: 4633 case ID_LED_OFF1_OFF2: 4634 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4635 mac->ledctl_mode2 |= (ledctl_off << shift); 4636 break; 4637 default: 4638 /* Do nothing */ 4639 break; 4640 } 4641 } 4642 4643 return 0; 4644 } 4645 4646 /** 4647 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4648 * @hw: pointer to the HW structure 4649 * 4650 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4651 * register, so the bus width is hard coded. 4652 **/ 4653 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4654 { 4655 struct e1000_bus_info *bus = &hw->bus; 4656 s32 ret_val; 4657 4658 ret_val = e1000e_get_bus_info_pcie(hw); 4659 4660 /* ICH devices are "PCI Express"-ish. They have 4661 * a configuration space, but do not contain 4662 * PCI Express Capability registers, so bus width 4663 * must be hardcoded. 4664 */ 4665 if (bus->width == e1000_bus_width_unknown) 4666 bus->width = e1000_bus_width_pcie_x1; 4667 4668 return ret_val; 4669 } 4670 4671 /** 4672 * e1000_reset_hw_ich8lan - Reset the hardware 4673 * @hw: pointer to the HW structure 4674 * 4675 * Does a full reset of the hardware which includes a reset of the PHY and 4676 * MAC. 4677 **/ 4678 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4679 { 4680 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4681 u16 kum_cfg; 4682 u32 ctrl, reg; 4683 s32 ret_val; 4684 4685 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4686 * on the last TLP read/write transaction when MAC is reset. 4687 */ 4688 ret_val = e1000e_disable_pcie_master(hw); 4689 if (ret_val) 4690 e_dbg("PCI-E Master disable polling has failed.\n"); 4691 4692 e_dbg("Masking off all interrupts\n"); 4693 ew32(IMC, 0xffffffff); 4694 4695 /* Disable the Transmit and Receive units. Then delay to allow 4696 * any pending transactions to complete before we hit the MAC 4697 * with the global reset. 4698 */ 4699 ew32(RCTL, 0); 4700 ew32(TCTL, E1000_TCTL_PSP); 4701 e1e_flush(); 4702 4703 usleep_range(10000, 11000); 4704 4705 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4706 if (hw->mac.type == e1000_ich8lan) { 4707 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4708 ew32(PBA, E1000_PBA_8K); 4709 /* Set Packet Buffer Size to 16k. */ 4710 ew32(PBS, E1000_PBS_16K); 4711 } 4712 4713 if (hw->mac.type == e1000_pchlan) { 4714 /* Save the NVM K1 bit setting */ 4715 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4716 if (ret_val) 4717 return ret_val; 4718 4719 if (kum_cfg & E1000_NVM_K1_ENABLE) 4720 dev_spec->nvm_k1_enabled = true; 4721 else 4722 dev_spec->nvm_k1_enabled = false; 4723 } 4724 4725 ctrl = er32(CTRL); 4726 4727 if (!hw->phy.ops.check_reset_block(hw)) { 4728 /* Full-chip reset requires MAC and PHY reset at the same 4729 * time to make sure the interface between MAC and the 4730 * external PHY is reset. 4731 */ 4732 ctrl |= E1000_CTRL_PHY_RST; 4733 4734 /* Gate automatic PHY configuration by hardware on 4735 * non-managed 82579 4736 */ 4737 if ((hw->mac.type == e1000_pch2lan) && 4738 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4739 e1000_gate_hw_phy_config_ich8lan(hw, true); 4740 } 4741 ret_val = e1000_acquire_swflag_ich8lan(hw); 4742 e_dbg("Issuing a global reset to ich8lan\n"); 4743 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4744 /* cannot issue a flush here because it hangs the hardware */ 4745 msleep(20); 4746 4747 /* Set Phy Config Counter to 50msec */ 4748 if (hw->mac.type == e1000_pch2lan) { 4749 reg = er32(FEXTNVM3); 4750 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4751 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4752 ew32(FEXTNVM3, reg); 4753 } 4754 4755 if (!ret_val) 4756 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4757 4758 if (ctrl & E1000_CTRL_PHY_RST) { 4759 ret_val = hw->phy.ops.get_cfg_done(hw); 4760 if (ret_val) 4761 return ret_val; 4762 4763 ret_val = e1000_post_phy_reset_ich8lan(hw); 4764 if (ret_val) 4765 return ret_val; 4766 } 4767 4768 /* For PCH, this write will make sure that any noise 4769 * will be detected as a CRC error and be dropped rather than show up 4770 * as a bad packet to the DMA engine. 4771 */ 4772 if (hw->mac.type == e1000_pchlan) 4773 ew32(CRC_OFFSET, 0x65656565); 4774 4775 ew32(IMC, 0xffffffff); 4776 er32(ICR); 4777 4778 reg = er32(KABGTXD); 4779 reg |= E1000_KABGTXD_BGSQLBIAS; 4780 ew32(KABGTXD, reg); 4781 4782 return 0; 4783 } 4784 4785 /** 4786 * e1000_init_hw_ich8lan - Initialize the hardware 4787 * @hw: pointer to the HW structure 4788 * 4789 * Prepares the hardware for transmit and receive by doing the following: 4790 * - initialize hardware bits 4791 * - initialize LED identification 4792 * - setup receive address registers 4793 * - setup flow control 4794 * - setup transmit descriptors 4795 * - clear statistics 4796 **/ 4797 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4798 { 4799 struct e1000_mac_info *mac = &hw->mac; 4800 u32 ctrl_ext, txdctl, snoop; 4801 s32 ret_val; 4802 u16 i; 4803 4804 e1000_initialize_hw_bits_ich8lan(hw); 4805 4806 /* Initialize identification LED */ 4807 ret_val = mac->ops.id_led_init(hw); 4808 /* An error is not fatal and we should not stop init due to this */ 4809 if (ret_val) 4810 e_dbg("Error initializing identification LED\n"); 4811 4812 /* Setup the receive address. */ 4813 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4814 4815 /* Zero out the Multicast HASH table */ 4816 e_dbg("Zeroing the MTA\n"); 4817 for (i = 0; i < mac->mta_reg_count; i++) 4818 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4819 4820 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4821 * the ME. Disable wakeup by clearing the host wakeup bit. 4822 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4823 */ 4824 if (hw->phy.type == e1000_phy_82578) { 4825 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4826 i &= ~BM_WUC_HOST_WU_BIT; 4827 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4828 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4829 if (ret_val) 4830 return ret_val; 4831 } 4832 4833 /* Setup link and flow control */ 4834 ret_val = mac->ops.setup_link(hw); 4835 4836 /* Set the transmit descriptor write-back policy for both queues */ 4837 txdctl = er32(TXDCTL(0)); 4838 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4839 E1000_TXDCTL_FULL_TX_DESC_WB); 4840 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4841 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4842 ew32(TXDCTL(0), txdctl); 4843 txdctl = er32(TXDCTL(1)); 4844 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4845 E1000_TXDCTL_FULL_TX_DESC_WB); 4846 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4847 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4848 ew32(TXDCTL(1), txdctl); 4849 4850 /* ICH8 has opposite polarity of no_snoop bits. 4851 * By default, we should use snoop behavior. 4852 */ 4853 if (mac->type == e1000_ich8lan) 4854 snoop = PCIE_ICH8_SNOOP_ALL; 4855 else 4856 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4857 e1000e_set_pcie_no_snoop(hw, snoop); 4858 4859 ctrl_ext = er32(CTRL_EXT); 4860 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4861 ew32(CTRL_EXT, ctrl_ext); 4862 4863 /* Clear all of the statistics registers (clear on read). It is 4864 * important that we do this after we have tried to establish link 4865 * because the symbol error count will increment wildly if there 4866 * is no link. 4867 */ 4868 e1000_clear_hw_cntrs_ich8lan(hw); 4869 4870 return ret_val; 4871 } 4872 4873 /** 4874 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4875 * @hw: pointer to the HW structure 4876 * 4877 * Sets/Clears required hardware bits necessary for correctly setting up the 4878 * hardware for transmit and receive. 4879 **/ 4880 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4881 { 4882 u32 reg; 4883 4884 /* Extended Device Control */ 4885 reg = er32(CTRL_EXT); 4886 reg |= BIT(22); 4887 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4888 if (hw->mac.type >= e1000_pchlan) 4889 reg |= E1000_CTRL_EXT_PHYPDEN; 4890 ew32(CTRL_EXT, reg); 4891 4892 /* Transmit Descriptor Control 0 */ 4893 reg = er32(TXDCTL(0)); 4894 reg |= BIT(22); 4895 ew32(TXDCTL(0), reg); 4896 4897 /* Transmit Descriptor Control 1 */ 4898 reg = er32(TXDCTL(1)); 4899 reg |= BIT(22); 4900 ew32(TXDCTL(1), reg); 4901 4902 /* Transmit Arbitration Control 0 */ 4903 reg = er32(TARC(0)); 4904 if (hw->mac.type == e1000_ich8lan) 4905 reg |= BIT(28) | BIT(29); 4906 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4907 ew32(TARC(0), reg); 4908 4909 /* Transmit Arbitration Control 1 */ 4910 reg = er32(TARC(1)); 4911 if (er32(TCTL) & E1000_TCTL_MULR) 4912 reg &= ~BIT(28); 4913 else 4914 reg |= BIT(28); 4915 reg |= BIT(24) | BIT(26) | BIT(30); 4916 ew32(TARC(1), reg); 4917 4918 /* Device Status */ 4919 if (hw->mac.type == e1000_ich8lan) { 4920 reg = er32(STATUS); 4921 reg &= ~BIT(31); 4922 ew32(STATUS, reg); 4923 } 4924 4925 /* work-around descriptor data corruption issue during nfs v2 udp 4926 * traffic, just disable the nfs filtering capability 4927 */ 4928 reg = er32(RFCTL); 4929 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4930 4931 /* Disable IPv6 extension header parsing because some malformed 4932 * IPv6 headers can hang the Rx. 4933 */ 4934 if (hw->mac.type == e1000_ich8lan) 4935 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4936 ew32(RFCTL, reg); 4937 4938 /* Enable ECC on Lynxpoint */ 4939 if (hw->mac.type >= e1000_pch_lpt) { 4940 reg = er32(PBECCSTS); 4941 reg |= E1000_PBECCSTS_ECC_ENABLE; 4942 ew32(PBECCSTS, reg); 4943 4944 reg = er32(CTRL); 4945 reg |= E1000_CTRL_MEHE; 4946 ew32(CTRL, reg); 4947 } 4948 } 4949 4950 /** 4951 * e1000_setup_link_ich8lan - Setup flow control and link settings 4952 * @hw: pointer to the HW structure 4953 * 4954 * Determines which flow control settings to use, then configures flow 4955 * control. Calls the appropriate media-specific link configuration 4956 * function. Assuming the adapter has a valid link partner, a valid link 4957 * should be established. Assumes the hardware has previously been reset 4958 * and the transmitter and receiver are not enabled. 4959 **/ 4960 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4961 { 4962 s32 ret_val; 4963 4964 if (hw->phy.ops.check_reset_block(hw)) 4965 return 0; 4966 4967 /* ICH parts do not have a word in the NVM to determine 4968 * the default flow control setting, so we explicitly 4969 * set it to full. 4970 */ 4971 if (hw->fc.requested_mode == e1000_fc_default) { 4972 /* Workaround h/w hang when Tx flow control enabled */ 4973 if (hw->mac.type == e1000_pchlan) 4974 hw->fc.requested_mode = e1000_fc_rx_pause; 4975 else 4976 hw->fc.requested_mode = e1000_fc_full; 4977 } 4978 4979 /* Save off the requested flow control mode for use later. Depending 4980 * on the link partner's capabilities, we may or may not use this mode. 4981 */ 4982 hw->fc.current_mode = hw->fc.requested_mode; 4983 4984 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4985 4986 /* Continue to configure the copper link. */ 4987 ret_val = hw->mac.ops.setup_physical_interface(hw); 4988 if (ret_val) 4989 return ret_val; 4990 4991 ew32(FCTTV, hw->fc.pause_time); 4992 if ((hw->phy.type == e1000_phy_82578) || 4993 (hw->phy.type == e1000_phy_82579) || 4994 (hw->phy.type == e1000_phy_i217) || 4995 (hw->phy.type == e1000_phy_82577)) { 4996 ew32(FCRTV_PCH, hw->fc.refresh_time); 4997 4998 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4999 hw->fc.pause_time); 5000 if (ret_val) 5001 return ret_val; 5002 } 5003 5004 return e1000e_set_fc_watermarks(hw); 5005 } 5006 5007 /** 5008 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5009 * @hw: pointer to the HW structure 5010 * 5011 * Configures the kumeran interface to the PHY to wait the appropriate time 5012 * when polling the PHY, then call the generic setup_copper_link to finish 5013 * configuring the copper link. 5014 **/ 5015 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5016 { 5017 u32 ctrl; 5018 s32 ret_val; 5019 u16 reg_data; 5020 5021 ctrl = er32(CTRL); 5022 ctrl |= E1000_CTRL_SLU; 5023 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5024 ew32(CTRL, ctrl); 5025 5026 /* Set the mac to wait the maximum time between each iteration 5027 * and increase the max iterations when polling the phy; 5028 * this fixes erroneous timeouts at 10Mbps. 5029 */ 5030 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5031 if (ret_val) 5032 return ret_val; 5033 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5034 ®_data); 5035 if (ret_val) 5036 return ret_val; 5037 reg_data |= 0x3F; 5038 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5039 reg_data); 5040 if (ret_val) 5041 return ret_val; 5042 5043 switch (hw->phy.type) { 5044 case e1000_phy_igp_3: 5045 ret_val = e1000e_copper_link_setup_igp(hw); 5046 if (ret_val) 5047 return ret_val; 5048 break; 5049 case e1000_phy_bm: 5050 case e1000_phy_82578: 5051 ret_val = e1000e_copper_link_setup_m88(hw); 5052 if (ret_val) 5053 return ret_val; 5054 break; 5055 case e1000_phy_82577: 5056 case e1000_phy_82579: 5057 ret_val = e1000_copper_link_setup_82577(hw); 5058 if (ret_val) 5059 return ret_val; 5060 break; 5061 case e1000_phy_ife: 5062 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5063 if (ret_val) 5064 return ret_val; 5065 5066 reg_data &= ~IFE_PMC_AUTO_MDIX; 5067 5068 switch (hw->phy.mdix) { 5069 case 1: 5070 reg_data &= ~IFE_PMC_FORCE_MDIX; 5071 break; 5072 case 2: 5073 reg_data |= IFE_PMC_FORCE_MDIX; 5074 break; 5075 case 0: 5076 default: 5077 reg_data |= IFE_PMC_AUTO_MDIX; 5078 break; 5079 } 5080 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5081 if (ret_val) 5082 return ret_val; 5083 break; 5084 default: 5085 break; 5086 } 5087 5088 return e1000e_setup_copper_link(hw); 5089 } 5090 5091 /** 5092 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5093 * @hw: pointer to the HW structure 5094 * 5095 * Calls the PHY specific link setup function and then calls the 5096 * generic setup_copper_link to finish configuring the link for 5097 * Lynxpoint PCH devices 5098 **/ 5099 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5100 { 5101 u32 ctrl; 5102 s32 ret_val; 5103 5104 ctrl = er32(CTRL); 5105 ctrl |= E1000_CTRL_SLU; 5106 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5107 ew32(CTRL, ctrl); 5108 5109 ret_val = e1000_copper_link_setup_82577(hw); 5110 if (ret_val) 5111 return ret_val; 5112 5113 return e1000e_setup_copper_link(hw); 5114 } 5115 5116 /** 5117 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5118 * @hw: pointer to the HW structure 5119 * @speed: pointer to store current link speed 5120 * @duplex: pointer to store the current link duplex 5121 * 5122 * Calls the generic get_speed_and_duplex to retrieve the current link 5123 * information and then calls the Kumeran lock loss workaround for links at 5124 * gigabit speeds. 5125 **/ 5126 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5127 u16 *duplex) 5128 { 5129 s32 ret_val; 5130 5131 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5132 if (ret_val) 5133 return ret_val; 5134 5135 if ((hw->mac.type == e1000_ich8lan) && 5136 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5137 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5138 } 5139 5140 return ret_val; 5141 } 5142 5143 /** 5144 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5145 * @hw: pointer to the HW structure 5146 * 5147 * Work-around for 82566 Kumeran PCS lock loss: 5148 * On link status change (i.e. PCI reset, speed change) and link is up and 5149 * speed is gigabit- 5150 * 0) if workaround is optionally disabled do nothing 5151 * 1) wait 1ms for Kumeran link to come up 5152 * 2) check Kumeran Diagnostic register PCS lock loss bit 5153 * 3) if not set the link is locked (all is good), otherwise... 5154 * 4) reset the PHY 5155 * 5) repeat up to 10 times 5156 * Note: this is only called for IGP3 copper when speed is 1gb. 5157 **/ 5158 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5159 { 5160 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5161 u32 phy_ctrl; 5162 s32 ret_val; 5163 u16 i, data; 5164 bool link; 5165 5166 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5167 return 0; 5168 5169 /* Make sure link is up before proceeding. If not just return. 5170 * Attempting this while link is negotiating fouled up link 5171 * stability 5172 */ 5173 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5174 if (!link) 5175 return 0; 5176 5177 for (i = 0; i < 10; i++) { 5178 /* read once to clear */ 5179 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5180 if (ret_val) 5181 return ret_val; 5182 /* and again to get new status */ 5183 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5184 if (ret_val) 5185 return ret_val; 5186 5187 /* check for PCS lock */ 5188 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5189 return 0; 5190 5191 /* Issue PHY reset */ 5192 e1000_phy_hw_reset(hw); 5193 mdelay(5); 5194 } 5195 /* Disable GigE link negotiation */ 5196 phy_ctrl = er32(PHY_CTRL); 5197 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5198 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5199 ew32(PHY_CTRL, phy_ctrl); 5200 5201 /* Call gig speed drop workaround on Gig disable before accessing 5202 * any PHY registers 5203 */ 5204 e1000e_gig_downshift_workaround_ich8lan(hw); 5205 5206 /* unable to acquire PCS lock */ 5207 return -E1000_ERR_PHY; 5208 } 5209 5210 /** 5211 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5212 * @hw: pointer to the HW structure 5213 * @state: boolean value used to set the current Kumeran workaround state 5214 * 5215 * If ICH8, set the current Kumeran workaround state (enabled - true 5216 * /disabled - false). 5217 **/ 5218 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5219 bool state) 5220 { 5221 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5222 5223 if (hw->mac.type != e1000_ich8lan) { 5224 e_dbg("Workaround applies to ICH8 only.\n"); 5225 return; 5226 } 5227 5228 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5229 } 5230 5231 /** 5232 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5233 * @hw: pointer to the HW structure 5234 * 5235 * Workaround for 82566 power-down on D3 entry: 5236 * 1) disable gigabit link 5237 * 2) write VR power-down enable 5238 * 3) read it back 5239 * Continue if successful, else issue LCD reset and repeat 5240 **/ 5241 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5242 { 5243 u32 reg; 5244 u16 data; 5245 u8 retry = 0; 5246 5247 if (hw->phy.type != e1000_phy_igp_3) 5248 return; 5249 5250 /* Try the workaround twice (if needed) */ 5251 do { 5252 /* Disable link */ 5253 reg = er32(PHY_CTRL); 5254 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5255 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5256 ew32(PHY_CTRL, reg); 5257 5258 /* Call gig speed drop workaround on Gig disable before 5259 * accessing any PHY registers 5260 */ 5261 if (hw->mac.type == e1000_ich8lan) 5262 e1000e_gig_downshift_workaround_ich8lan(hw); 5263 5264 /* Write VR power-down enable */ 5265 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5266 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5267 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5268 5269 /* Read it back and test */ 5270 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5271 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5272 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5273 break; 5274 5275 /* Issue PHY reset and repeat at most one more time */ 5276 reg = er32(CTRL); 5277 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5278 retry++; 5279 } while (retry); 5280 } 5281 5282 /** 5283 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5284 * @hw: pointer to the HW structure 5285 * 5286 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5287 * LPLU, Gig disable, MDIC PHY reset): 5288 * 1) Set Kumeran Near-end loopback 5289 * 2) Clear Kumeran Near-end loopback 5290 * Should only be called for ICH8[m] devices with any 1G Phy. 5291 **/ 5292 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5293 { 5294 s32 ret_val; 5295 u16 reg_data; 5296 5297 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5298 return; 5299 5300 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5301 ®_data); 5302 if (ret_val) 5303 return; 5304 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5305 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5306 reg_data); 5307 if (ret_val) 5308 return; 5309 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5310 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5311 } 5312 5313 /** 5314 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5315 * @hw: pointer to the HW structure 5316 * 5317 * During S0 to Sx transition, it is possible the link remains at gig 5318 * instead of negotiating to a lower speed. Before going to Sx, set 5319 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5320 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5321 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5322 * needs to be written. 5323 * Parts that support (and are linked to a partner which support) EEE in 5324 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5325 * than 10Mbps w/o EEE. 5326 **/ 5327 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5328 { 5329 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5330 u32 phy_ctrl; 5331 s32 ret_val; 5332 5333 phy_ctrl = er32(PHY_CTRL); 5334 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5335 5336 if (hw->phy.type == e1000_phy_i217) { 5337 u16 phy_reg, device_id = hw->adapter->pdev->device; 5338 5339 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5340 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5341 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5342 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5343 (hw->mac.type >= e1000_pch_spt)) { 5344 u32 fextnvm6 = er32(FEXTNVM6); 5345 5346 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5347 } 5348 5349 ret_val = hw->phy.ops.acquire(hw); 5350 if (ret_val) 5351 goto out; 5352 5353 if (!dev_spec->eee_disable) { 5354 u16 eee_advert; 5355 5356 ret_val = 5357 e1000_read_emi_reg_locked(hw, 5358 I217_EEE_ADVERTISEMENT, 5359 &eee_advert); 5360 if (ret_val) 5361 goto release; 5362 5363 /* Disable LPLU if both link partners support 100BaseT 5364 * EEE and 100Full is advertised on both ends of the 5365 * link, and enable Auto Enable LPI since there will 5366 * be no driver to enable LPI while in Sx. 5367 */ 5368 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5369 (dev_spec->eee_lp_ability & 5370 I82579_EEE_100_SUPPORTED) && 5371 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5372 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5373 E1000_PHY_CTRL_NOND0A_LPLU); 5374 5375 /* Set Auto Enable LPI after link up */ 5376 e1e_rphy_locked(hw, 5377 I217_LPI_GPIO_CTRL, &phy_reg); 5378 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5379 e1e_wphy_locked(hw, 5380 I217_LPI_GPIO_CTRL, phy_reg); 5381 } 5382 } 5383 5384 /* For i217 Intel Rapid Start Technology support, 5385 * when the system is going into Sx and no manageability engine 5386 * is present, the driver must configure proxy to reset only on 5387 * power good. LPI (Low Power Idle) state must also reset only 5388 * on power good, as well as the MTA (Multicast table array). 5389 * The SMBus release must also be disabled on LCD reset. 5390 */ 5391 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5392 /* Enable proxy to reset only on power good. */ 5393 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5394 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5395 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5396 5397 /* Set bit enable LPI (EEE) to reset only on 5398 * power good. 5399 */ 5400 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5401 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5402 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5403 5404 /* Disable the SMB release on LCD reset. */ 5405 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5406 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5407 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5408 } 5409 5410 /* Enable MTA to reset for Intel Rapid Start Technology 5411 * Support 5412 */ 5413 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5414 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5415 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5416 5417 release: 5418 hw->phy.ops.release(hw); 5419 } 5420 out: 5421 ew32(PHY_CTRL, phy_ctrl); 5422 5423 if (hw->mac.type == e1000_ich8lan) 5424 e1000e_gig_downshift_workaround_ich8lan(hw); 5425 5426 if (hw->mac.type >= e1000_pchlan) { 5427 e1000_oem_bits_config_ich8lan(hw, false); 5428 5429 /* Reset PHY to activate OEM bits on 82577/8 */ 5430 if (hw->mac.type == e1000_pchlan) 5431 e1000e_phy_hw_reset_generic(hw); 5432 5433 ret_val = hw->phy.ops.acquire(hw); 5434 if (ret_val) 5435 return; 5436 e1000_write_smbus_addr(hw); 5437 hw->phy.ops.release(hw); 5438 } 5439 } 5440 5441 /** 5442 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5443 * @hw: pointer to the HW structure 5444 * 5445 * During Sx to S0 transitions on non-managed devices or managed devices 5446 * on which PHY resets are not blocked, if the PHY registers cannot be 5447 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5448 * the PHY. 5449 * On i217, setup Intel Rapid Start Technology. 5450 **/ 5451 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5452 { 5453 s32 ret_val; 5454 5455 if (hw->mac.type < e1000_pch2lan) 5456 return; 5457 5458 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5459 if (ret_val) { 5460 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5461 return; 5462 } 5463 5464 /* For i217 Intel Rapid Start Technology support when the system 5465 * is transitioning from Sx and no manageability engine is present 5466 * configure SMBus to restore on reset, disable proxy, and enable 5467 * the reset on MTA (Multicast table array). 5468 */ 5469 if (hw->phy.type == e1000_phy_i217) { 5470 u16 phy_reg; 5471 5472 ret_val = hw->phy.ops.acquire(hw); 5473 if (ret_val) { 5474 e_dbg("Failed to setup iRST\n"); 5475 return; 5476 } 5477 5478 /* Clear Auto Enable LPI after link up */ 5479 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5480 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5481 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5482 5483 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5484 /* Restore clear on SMB if no manageability engine 5485 * is present 5486 */ 5487 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5488 if (ret_val) 5489 goto release; 5490 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5491 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5492 5493 /* Disable Proxy */ 5494 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5495 } 5496 /* Enable reset on MTA */ 5497 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5498 if (ret_val) 5499 goto release; 5500 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5501 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5502 release: 5503 if (ret_val) 5504 e_dbg("Error %d in resume workarounds\n", ret_val); 5505 hw->phy.ops.release(hw); 5506 } 5507 } 5508 5509 /** 5510 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5511 * @hw: pointer to the HW structure 5512 * 5513 * Return the LED back to the default configuration. 5514 **/ 5515 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5516 { 5517 if (hw->phy.type == e1000_phy_ife) 5518 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5519 5520 ew32(LEDCTL, hw->mac.ledctl_default); 5521 return 0; 5522 } 5523 5524 /** 5525 * e1000_led_on_ich8lan - Turn LEDs on 5526 * @hw: pointer to the HW structure 5527 * 5528 * Turn on the LEDs. 5529 **/ 5530 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5531 { 5532 if (hw->phy.type == e1000_phy_ife) 5533 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5534 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5535 5536 ew32(LEDCTL, hw->mac.ledctl_mode2); 5537 return 0; 5538 } 5539 5540 /** 5541 * e1000_led_off_ich8lan - Turn LEDs off 5542 * @hw: pointer to the HW structure 5543 * 5544 * Turn off the LEDs. 5545 **/ 5546 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5547 { 5548 if (hw->phy.type == e1000_phy_ife) 5549 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5550 (IFE_PSCL_PROBE_MODE | 5551 IFE_PSCL_PROBE_LEDS_OFF)); 5552 5553 ew32(LEDCTL, hw->mac.ledctl_mode1); 5554 return 0; 5555 } 5556 5557 /** 5558 * e1000_setup_led_pchlan - Configures SW controllable LED 5559 * @hw: pointer to the HW structure 5560 * 5561 * This prepares the SW controllable LED for use. 5562 **/ 5563 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5564 { 5565 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5566 } 5567 5568 /** 5569 * e1000_cleanup_led_pchlan - Restore the default LED operation 5570 * @hw: pointer to the HW structure 5571 * 5572 * Return the LED back to the default configuration. 5573 **/ 5574 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5575 { 5576 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5577 } 5578 5579 /** 5580 * e1000_led_on_pchlan - Turn LEDs on 5581 * @hw: pointer to the HW structure 5582 * 5583 * Turn on the LEDs. 5584 **/ 5585 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5586 { 5587 u16 data = (u16)hw->mac.ledctl_mode2; 5588 u32 i, led; 5589 5590 /* If no link, then turn LED on by setting the invert bit 5591 * for each LED that's mode is "link_up" in ledctl_mode2. 5592 */ 5593 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5594 for (i = 0; i < 3; i++) { 5595 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5596 if ((led & E1000_PHY_LED0_MODE_MASK) != 5597 E1000_LEDCTL_MODE_LINK_UP) 5598 continue; 5599 if (led & E1000_PHY_LED0_IVRT) 5600 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5601 else 5602 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5603 } 5604 } 5605 5606 return e1e_wphy(hw, HV_LED_CONFIG, data); 5607 } 5608 5609 /** 5610 * e1000_led_off_pchlan - Turn LEDs off 5611 * @hw: pointer to the HW structure 5612 * 5613 * Turn off the LEDs. 5614 **/ 5615 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5616 { 5617 u16 data = (u16)hw->mac.ledctl_mode1; 5618 u32 i, led; 5619 5620 /* If no link, then turn LED off by clearing the invert bit 5621 * for each LED that's mode is "link_up" in ledctl_mode1. 5622 */ 5623 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5624 for (i = 0; i < 3; i++) { 5625 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5626 if ((led & E1000_PHY_LED0_MODE_MASK) != 5627 E1000_LEDCTL_MODE_LINK_UP) 5628 continue; 5629 if (led & E1000_PHY_LED0_IVRT) 5630 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5631 else 5632 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5633 } 5634 } 5635 5636 return e1e_wphy(hw, HV_LED_CONFIG, data); 5637 } 5638 5639 /** 5640 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5641 * @hw: pointer to the HW structure 5642 * 5643 * Read appropriate register for the config done bit for completion status 5644 * and configure the PHY through s/w for EEPROM-less parts. 5645 * 5646 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5647 * config done bit, so only an error is logged and continues. If we were 5648 * to return with error, EEPROM-less silicon would not be able to be reset 5649 * or change link. 5650 **/ 5651 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5652 { 5653 s32 ret_val = 0; 5654 u32 bank = 0; 5655 u32 status; 5656 5657 e1000e_get_cfg_done_generic(hw); 5658 5659 /* Wait for indication from h/w that it has completed basic config */ 5660 if (hw->mac.type >= e1000_ich10lan) { 5661 e1000_lan_init_done_ich8lan(hw); 5662 } else { 5663 ret_val = e1000e_get_auto_rd_done(hw); 5664 if (ret_val) { 5665 /* When auto config read does not complete, do not 5666 * return with an error. This can happen in situations 5667 * where there is no eeprom and prevents getting link. 5668 */ 5669 e_dbg("Auto Read Done did not complete\n"); 5670 ret_val = 0; 5671 } 5672 } 5673 5674 /* Clear PHY Reset Asserted bit */ 5675 status = er32(STATUS); 5676 if (status & E1000_STATUS_PHYRA) 5677 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5678 else 5679 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5680 5681 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5682 if (hw->mac.type <= e1000_ich9lan) { 5683 if (!(er32(EECD) & E1000_EECD_PRES) && 5684 (hw->phy.type == e1000_phy_igp_3)) { 5685 e1000e_phy_init_script_igp3(hw); 5686 } 5687 } else { 5688 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5689 /* Maybe we should do a basic PHY config */ 5690 e_dbg("EEPROM not present\n"); 5691 ret_val = -E1000_ERR_CONFIG; 5692 } 5693 } 5694 5695 return ret_val; 5696 } 5697 5698 /** 5699 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5700 * @hw: pointer to the HW structure 5701 * 5702 * In the case of a PHY power down to save power, or to turn off link during a 5703 * driver unload, or wake on lan is not enabled, remove the link. 5704 **/ 5705 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5706 { 5707 /* If the management interface is not enabled, then power down */ 5708 if (!(hw->mac.ops.check_mng_mode(hw) || 5709 hw->phy.ops.check_reset_block(hw))) 5710 e1000_power_down_phy_copper(hw); 5711 } 5712 5713 /** 5714 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5715 * @hw: pointer to the HW structure 5716 * 5717 * Clears hardware counters specific to the silicon family and calls 5718 * clear_hw_cntrs_generic to clear all general purpose counters. 5719 **/ 5720 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5721 { 5722 u16 phy_data; 5723 s32 ret_val; 5724 5725 e1000e_clear_hw_cntrs_base(hw); 5726 5727 er32(ALGNERRC); 5728 er32(RXERRC); 5729 er32(TNCRS); 5730 er32(CEXTERR); 5731 er32(TSCTC); 5732 er32(TSCTFC); 5733 5734 er32(MGTPRC); 5735 er32(MGTPDC); 5736 er32(MGTPTC); 5737 5738 er32(IAC); 5739 er32(ICRXOC); 5740 5741 /* Clear PHY statistics registers */ 5742 if ((hw->phy.type == e1000_phy_82578) || 5743 (hw->phy.type == e1000_phy_82579) || 5744 (hw->phy.type == e1000_phy_i217) || 5745 (hw->phy.type == e1000_phy_82577)) { 5746 ret_val = hw->phy.ops.acquire(hw); 5747 if (ret_val) 5748 return; 5749 ret_val = hw->phy.ops.set_page(hw, 5750 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5751 if (ret_val) 5752 goto release; 5753 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5754 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5755 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5756 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5757 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5758 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5759 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5760 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5761 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5762 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5763 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5764 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5765 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5766 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5767 release: 5768 hw->phy.ops.release(hw); 5769 } 5770 } 5771 5772 static const struct e1000_mac_operations ich8_mac_ops = { 5773 /* check_mng_mode dependent on mac type */ 5774 .check_for_link = e1000_check_for_copper_link_ich8lan, 5775 /* cleanup_led dependent on mac type */ 5776 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5777 .get_bus_info = e1000_get_bus_info_ich8lan, 5778 .set_lan_id = e1000_set_lan_id_single_port, 5779 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5780 /* led_on dependent on mac type */ 5781 /* led_off dependent on mac type */ 5782 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5783 .reset_hw = e1000_reset_hw_ich8lan, 5784 .init_hw = e1000_init_hw_ich8lan, 5785 .setup_link = e1000_setup_link_ich8lan, 5786 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5787 /* id_led_init dependent on mac type */ 5788 .config_collision_dist = e1000e_config_collision_dist_generic, 5789 .rar_set = e1000e_rar_set_generic, 5790 .rar_get_count = e1000e_rar_get_count_generic, 5791 }; 5792 5793 static const struct e1000_phy_operations ich8_phy_ops = { 5794 .acquire = e1000_acquire_swflag_ich8lan, 5795 .check_reset_block = e1000_check_reset_block_ich8lan, 5796 .commit = NULL, 5797 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5798 .get_cable_length = e1000e_get_cable_length_igp_2, 5799 .read_reg = e1000e_read_phy_reg_igp, 5800 .release = e1000_release_swflag_ich8lan, 5801 .reset = e1000_phy_hw_reset_ich8lan, 5802 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5803 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5804 .write_reg = e1000e_write_phy_reg_igp, 5805 }; 5806 5807 static const struct e1000_nvm_operations ich8_nvm_ops = { 5808 .acquire = e1000_acquire_nvm_ich8lan, 5809 .read = e1000_read_nvm_ich8lan, 5810 .release = e1000_release_nvm_ich8lan, 5811 .reload = e1000e_reload_nvm_generic, 5812 .update = e1000_update_nvm_checksum_ich8lan, 5813 .valid_led_default = e1000_valid_led_default_ich8lan, 5814 .validate = e1000_validate_nvm_checksum_ich8lan, 5815 .write = e1000_write_nvm_ich8lan, 5816 }; 5817 5818 static const struct e1000_nvm_operations spt_nvm_ops = { 5819 .acquire = e1000_acquire_nvm_ich8lan, 5820 .release = e1000_release_nvm_ich8lan, 5821 .read = e1000_read_nvm_spt, 5822 .update = e1000_update_nvm_checksum_spt, 5823 .reload = e1000e_reload_nvm_generic, 5824 .valid_led_default = e1000_valid_led_default_ich8lan, 5825 .validate = e1000_validate_nvm_checksum_ich8lan, 5826 .write = e1000_write_nvm_ich8lan, 5827 }; 5828 5829 const struct e1000_info e1000_ich8_info = { 5830 .mac = e1000_ich8lan, 5831 .flags = FLAG_HAS_WOL 5832 | FLAG_IS_ICH 5833 | FLAG_HAS_CTRLEXT_ON_LOAD 5834 | FLAG_HAS_AMT 5835 | FLAG_HAS_FLASH 5836 | FLAG_APME_IN_WUC, 5837 .pba = 8, 5838 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5839 .get_variants = e1000_get_variants_ich8lan, 5840 .mac_ops = &ich8_mac_ops, 5841 .phy_ops = &ich8_phy_ops, 5842 .nvm_ops = &ich8_nvm_ops, 5843 }; 5844 5845 const struct e1000_info e1000_ich9_info = { 5846 .mac = e1000_ich9lan, 5847 .flags = FLAG_HAS_JUMBO_FRAMES 5848 | FLAG_IS_ICH 5849 | FLAG_HAS_WOL 5850 | FLAG_HAS_CTRLEXT_ON_LOAD 5851 | FLAG_HAS_AMT 5852 | FLAG_HAS_FLASH 5853 | FLAG_APME_IN_WUC, 5854 .pba = 18, 5855 .max_hw_frame_size = DEFAULT_JUMBO, 5856 .get_variants = e1000_get_variants_ich8lan, 5857 .mac_ops = &ich8_mac_ops, 5858 .phy_ops = &ich8_phy_ops, 5859 .nvm_ops = &ich8_nvm_ops, 5860 }; 5861 5862 const struct e1000_info e1000_ich10_info = { 5863 .mac = e1000_ich10lan, 5864 .flags = FLAG_HAS_JUMBO_FRAMES 5865 | FLAG_IS_ICH 5866 | FLAG_HAS_WOL 5867 | FLAG_HAS_CTRLEXT_ON_LOAD 5868 | FLAG_HAS_AMT 5869 | FLAG_HAS_FLASH 5870 | FLAG_APME_IN_WUC, 5871 .pba = 18, 5872 .max_hw_frame_size = DEFAULT_JUMBO, 5873 .get_variants = e1000_get_variants_ich8lan, 5874 .mac_ops = &ich8_mac_ops, 5875 .phy_ops = &ich8_phy_ops, 5876 .nvm_ops = &ich8_nvm_ops, 5877 }; 5878 5879 const struct e1000_info e1000_pch_info = { 5880 .mac = e1000_pchlan, 5881 .flags = FLAG_IS_ICH 5882 | FLAG_HAS_WOL 5883 | FLAG_HAS_CTRLEXT_ON_LOAD 5884 | FLAG_HAS_AMT 5885 | FLAG_HAS_FLASH 5886 | FLAG_HAS_JUMBO_FRAMES 5887 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5888 | FLAG_APME_IN_WUC, 5889 .flags2 = FLAG2_HAS_PHY_STATS, 5890 .pba = 26, 5891 .max_hw_frame_size = 4096, 5892 .get_variants = e1000_get_variants_ich8lan, 5893 .mac_ops = &ich8_mac_ops, 5894 .phy_ops = &ich8_phy_ops, 5895 .nvm_ops = &ich8_nvm_ops, 5896 }; 5897 5898 const struct e1000_info e1000_pch2_info = { 5899 .mac = e1000_pch2lan, 5900 .flags = FLAG_IS_ICH 5901 | FLAG_HAS_WOL 5902 | FLAG_HAS_HW_TIMESTAMP 5903 | FLAG_HAS_CTRLEXT_ON_LOAD 5904 | FLAG_HAS_AMT 5905 | FLAG_HAS_FLASH 5906 | FLAG_HAS_JUMBO_FRAMES 5907 | FLAG_APME_IN_WUC, 5908 .flags2 = FLAG2_HAS_PHY_STATS 5909 | FLAG2_HAS_EEE 5910 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5911 .pba = 26, 5912 .max_hw_frame_size = 9022, 5913 .get_variants = e1000_get_variants_ich8lan, 5914 .mac_ops = &ich8_mac_ops, 5915 .phy_ops = &ich8_phy_ops, 5916 .nvm_ops = &ich8_nvm_ops, 5917 }; 5918 5919 const struct e1000_info e1000_pch_lpt_info = { 5920 .mac = e1000_pch_lpt, 5921 .flags = FLAG_IS_ICH 5922 | FLAG_HAS_WOL 5923 | FLAG_HAS_HW_TIMESTAMP 5924 | FLAG_HAS_CTRLEXT_ON_LOAD 5925 | FLAG_HAS_AMT 5926 | FLAG_HAS_FLASH 5927 | FLAG_HAS_JUMBO_FRAMES 5928 | FLAG_APME_IN_WUC, 5929 .flags2 = FLAG2_HAS_PHY_STATS 5930 | FLAG2_HAS_EEE 5931 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5932 .pba = 26, 5933 .max_hw_frame_size = 9022, 5934 .get_variants = e1000_get_variants_ich8lan, 5935 .mac_ops = &ich8_mac_ops, 5936 .phy_ops = &ich8_phy_ops, 5937 .nvm_ops = &ich8_nvm_ops, 5938 }; 5939 5940 const struct e1000_info e1000_pch_spt_info = { 5941 .mac = e1000_pch_spt, 5942 .flags = FLAG_IS_ICH 5943 | FLAG_HAS_WOL 5944 | FLAG_HAS_HW_TIMESTAMP 5945 | FLAG_HAS_CTRLEXT_ON_LOAD 5946 | FLAG_HAS_AMT 5947 | FLAG_HAS_FLASH 5948 | FLAG_HAS_JUMBO_FRAMES 5949 | FLAG_APME_IN_WUC, 5950 .flags2 = FLAG2_HAS_PHY_STATS 5951 | FLAG2_HAS_EEE, 5952 .pba = 26, 5953 .max_hw_frame_size = 9022, 5954 .get_variants = e1000_get_variants_ich8lan, 5955 .mac_ops = &ich8_mac_ops, 5956 .phy_ops = &ich8_phy_ops, 5957 .nvm_ops = &spt_nvm_ops, 5958 }; 5959 5960 const struct e1000_info e1000_pch_cnp_info = { 5961 .mac = e1000_pch_cnp, 5962 .flags = FLAG_IS_ICH 5963 | FLAG_HAS_WOL 5964 | FLAG_HAS_HW_TIMESTAMP 5965 | FLAG_HAS_CTRLEXT_ON_LOAD 5966 | FLAG_HAS_AMT 5967 | FLAG_HAS_FLASH 5968 | FLAG_HAS_JUMBO_FRAMES 5969 | FLAG_APME_IN_WUC, 5970 .flags2 = FLAG2_HAS_PHY_STATS 5971 | FLAG2_HAS_EEE, 5972 .pba = 26, 5973 .max_hw_frame_size = 9022, 5974 .get_variants = e1000_get_variants_ich8lan, 5975 .mac_ops = &ich8_mac_ops, 5976 .phy_ops = &ich8_phy_ops, 5977 .nvm_ops = &spt_nvm_ops, 5978 }; 5979