1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* 82562G 10/100 Network Connection 30 * 82562G-2 10/100 Network Connection 31 * 82562GT 10/100 Network Connection 32 * 82562GT-2 10/100 Network Connection 33 * 82562V 10/100 Network Connection 34 * 82562V-2 10/100 Network Connection 35 * 82566DC-2 Gigabit Network Connection 36 * 82566DC Gigabit Network Connection 37 * 82566DM-2 Gigabit Network Connection 38 * 82566DM Gigabit Network Connection 39 * 82566MC Gigabit Network Connection 40 * 82566MM Gigabit Network Connection 41 * 82567LM Gigabit Network Connection 42 * 82567LF Gigabit Network Connection 43 * 82567V Gigabit Network Connection 44 * 82567LM-2 Gigabit Network Connection 45 * 82567LF-2 Gigabit Network Connection 46 * 82567V-2 Gigabit Network Connection 47 * 82567LF-3 Gigabit Network Connection 48 * 82567LM-3 Gigabit Network Connection 49 * 82567LM-4 Gigabit Network Connection 50 * 82577LM Gigabit Network Connection 51 * 82577LC Gigabit Network Connection 52 * 82578DM Gigabit Network Connection 53 * 82578DC Gigabit Network Connection 54 * 82579LM Gigabit Network Connection 55 * 82579V Gigabit Network Connection 56 */ 57 58 #include "e1000.h" 59 60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 61 /* Offset 04h HSFSTS */ 62 union ich8_hws_flash_status { 63 struct ich8_hsfsts { 64 u16 flcdone :1; /* bit 0 Flash Cycle Done */ 65 u16 flcerr :1; /* bit 1 Flash Cycle Error */ 66 u16 dael :1; /* bit 2 Direct Access error Log */ 67 u16 berasesz :2; /* bit 4:3 Sector Erase Size */ 68 u16 flcinprog :1; /* bit 5 flash cycle in Progress */ 69 u16 reserved1 :2; /* bit 13:6 Reserved */ 70 u16 reserved2 :6; /* bit 13:6 Reserved */ 71 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 72 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ 73 } hsf_status; 74 u16 regval; 75 }; 76 77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 78 /* Offset 06h FLCTL */ 79 union ich8_hws_flash_ctrl { 80 struct ich8_hsflctl { 81 u16 flcgo :1; /* 0 Flash Cycle Go */ 82 u16 flcycle :2; /* 2:1 Flash Cycle */ 83 u16 reserved :5; /* 7:3 Reserved */ 84 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ 85 u16 flockdn :6; /* 15:10 Reserved */ 86 } hsf_ctrl; 87 u16 regval; 88 }; 89 90 /* ICH Flash Region Access Permissions */ 91 union ich8_hws_flash_regacc { 92 struct ich8_flracc { 93 u32 grra :8; /* 0:7 GbE region Read Access */ 94 u32 grwa :8; /* 8:15 GbE region Write Access */ 95 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ 96 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ 97 } hsf_flregacc; 98 u16 regval; 99 }; 100 101 /* ICH Flash Protected Region */ 102 union ich8_flash_protected_range { 103 struct ich8_pr { 104 u32 base:13; /* 0:12 Protected Range Base */ 105 u32 reserved1:2; /* 13:14 Reserved */ 106 u32 rpe:1; /* 15 Read Protection Enable */ 107 u32 limit:13; /* 16:28 Protected Range Limit */ 108 u32 reserved2:2; /* 29:30 Reserved */ 109 u32 wpe:1; /* 31 Write Protection Enable */ 110 } range; 111 u32 regval; 112 }; 113 114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 118 u32 offset, u8 byte); 119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 120 u8 *data); 121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 122 u16 *data); 123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 124 u8 size, u16 *data); 125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 145 146 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readw(hw->flash_address + reg); 149 } 150 151 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 152 { 153 return readl(hw->flash_address + reg); 154 } 155 156 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 157 { 158 writew(val, hw->flash_address + reg); 159 } 160 161 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 162 { 163 writel(val, hw->flash_address + reg); 164 } 165 166 #define er16flash(reg) __er16flash(hw, (reg)) 167 #define er32flash(reg) __er32flash(hw, (reg)) 168 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 169 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 170 171 /** 172 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 173 * @hw: pointer to the HW structure 174 * 175 * Test access to the PHY registers by reading the PHY ID registers. If 176 * the PHY ID is already known (e.g. resume path) compare it with known ID, 177 * otherwise assume the read PHY ID is correct if it is valid. 178 * 179 * Assumes the sw/fw/hw semaphore is already acquired. 180 **/ 181 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 182 { 183 u16 phy_reg = 0; 184 u32 phy_id = 0; 185 s32 ret_val; 186 u16 retry_count; 187 188 for (retry_count = 0; retry_count < 2; retry_count++) { 189 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 190 if (ret_val || (phy_reg == 0xFFFF)) 191 continue; 192 phy_id = (u32)(phy_reg << 16); 193 194 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 195 if (ret_val || (phy_reg == 0xFFFF)) { 196 phy_id = 0; 197 continue; 198 } 199 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 200 break; 201 } 202 203 if (hw->phy.id) { 204 if (hw->phy.id == phy_id) 205 return true; 206 } else if (phy_id) { 207 hw->phy.id = phy_id; 208 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 209 return true; 210 } 211 212 /* In case the PHY needs to be in mdio slow mode, 213 * set slow mode and try to get the PHY id again. 214 */ 215 hw->phy.ops.release(hw); 216 ret_val = e1000_set_mdio_slow_mode_hv(hw); 217 if (!ret_val) 218 ret_val = e1000e_get_phy_id(hw); 219 hw->phy.ops.acquire(hw); 220 221 return !ret_val; 222 } 223 224 /** 225 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 226 * @hw: pointer to the HW structure 227 * 228 * Workarounds/flow necessary for PHY initialization during driver load 229 * and resume paths. 230 **/ 231 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 232 { 233 u32 mac_reg, fwsm = er32(FWSM); 234 s32 ret_val; 235 u16 phy_reg; 236 237 /* Gate automatic PHY configuration by hardware on managed and 238 * non-managed 82579 and newer adapters. 239 */ 240 e1000_gate_hw_phy_config_ich8lan(hw, true); 241 242 ret_val = hw->phy.ops.acquire(hw); 243 if (ret_val) { 244 e_dbg("Failed to initialize PHY flow\n"); 245 goto out; 246 } 247 248 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 249 * inaccessible and resetting the PHY is not blocked, toggle the 250 * LANPHYPC Value bit to force the interconnect to PCIe mode. 251 */ 252 switch (hw->mac.type) { 253 case e1000_pch_lpt: 254 if (e1000_phy_is_accessible_pchlan(hw)) 255 break; 256 257 /* Before toggling LANPHYPC, see if PHY is accessible by 258 * forcing MAC to SMBus mode first. 259 */ 260 mac_reg = er32(CTRL_EXT); 261 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 262 ew32(CTRL_EXT, mac_reg); 263 264 /* fall-through */ 265 case e1000_pch2lan: 266 if (e1000_phy_is_accessible_pchlan(hw)) { 267 if (hw->mac.type == e1000_pch_lpt) { 268 /* Unforce SMBus mode in PHY */ 269 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 270 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 271 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 272 273 /* Unforce SMBus mode in MAC */ 274 mac_reg = er32(CTRL_EXT); 275 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 276 ew32(CTRL_EXT, mac_reg); 277 } 278 break; 279 } 280 281 /* fall-through */ 282 case e1000_pchlan: 283 if ((hw->mac.type == e1000_pchlan) && 284 (fwsm & E1000_ICH_FWSM_FW_VALID)) 285 break; 286 287 if (hw->phy.ops.check_reset_block(hw)) { 288 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 289 break; 290 } 291 292 e_dbg("Toggling LANPHYPC\n"); 293 294 /* Set Phy Config Counter to 50msec */ 295 mac_reg = er32(FEXTNVM3); 296 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 297 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 298 ew32(FEXTNVM3, mac_reg); 299 300 if (hw->mac.type == e1000_pch_lpt) { 301 /* Toggling LANPHYPC brings the PHY out of SMBus mode 302 * So ensure that the MAC is also out of SMBus mode 303 */ 304 mac_reg = er32(CTRL_EXT); 305 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 306 ew32(CTRL_EXT, mac_reg); 307 } 308 309 /* Toggle LANPHYPC Value bit */ 310 mac_reg = er32(CTRL); 311 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 312 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 313 ew32(CTRL, mac_reg); 314 e1e_flush(); 315 udelay(10); 316 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 317 ew32(CTRL, mac_reg); 318 e1e_flush(); 319 if (hw->mac.type < e1000_pch_lpt) { 320 msleep(50); 321 } else { 322 u16 count = 20; 323 do { 324 usleep_range(5000, 10000); 325 } while (!(er32(CTRL_EXT) & 326 E1000_CTRL_EXT_LPCD) && count--); 327 } 328 break; 329 default: 330 break; 331 } 332 333 hw->phy.ops.release(hw); 334 335 /* Reset the PHY before any access to it. Doing so, ensures 336 * that the PHY is in a known good state before we read/write 337 * PHY registers. The generic reset is sufficient here, 338 * because we haven't determined the PHY type yet. 339 */ 340 ret_val = e1000e_phy_hw_reset_generic(hw); 341 342 out: 343 /* Ungate automatic PHY configuration on non-managed 82579 */ 344 if ((hw->mac.type == e1000_pch2lan) && 345 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 346 usleep_range(10000, 20000); 347 e1000_gate_hw_phy_config_ich8lan(hw, false); 348 } 349 350 return ret_val; 351 } 352 353 /** 354 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 355 * @hw: pointer to the HW structure 356 * 357 * Initialize family-specific PHY parameters and function pointers. 358 **/ 359 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 360 { 361 struct e1000_phy_info *phy = &hw->phy; 362 s32 ret_val; 363 364 phy->addr = 1; 365 phy->reset_delay_us = 100; 366 367 phy->ops.set_page = e1000_set_page_igp; 368 phy->ops.read_reg = e1000_read_phy_reg_hv; 369 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 370 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 371 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 372 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 373 phy->ops.write_reg = e1000_write_phy_reg_hv; 374 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 375 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 376 phy->ops.power_up = e1000_power_up_phy_copper; 377 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 378 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 379 380 phy->id = e1000_phy_unknown; 381 382 ret_val = e1000_init_phy_workarounds_pchlan(hw); 383 if (ret_val) 384 return ret_val; 385 386 if (phy->id == e1000_phy_unknown) 387 switch (hw->mac.type) { 388 default: 389 ret_val = e1000e_get_phy_id(hw); 390 if (ret_val) 391 return ret_val; 392 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 393 break; 394 /* fall-through */ 395 case e1000_pch2lan: 396 case e1000_pch_lpt: 397 /* In case the PHY needs to be in mdio slow mode, 398 * set slow mode and try to get the PHY id again. 399 */ 400 ret_val = e1000_set_mdio_slow_mode_hv(hw); 401 if (ret_val) 402 return ret_val; 403 ret_val = e1000e_get_phy_id(hw); 404 if (ret_val) 405 return ret_val; 406 break; 407 } 408 phy->type = e1000e_get_phy_type_from_id(phy->id); 409 410 switch (phy->type) { 411 case e1000_phy_82577: 412 case e1000_phy_82579: 413 case e1000_phy_i217: 414 phy->ops.check_polarity = e1000_check_polarity_82577; 415 phy->ops.force_speed_duplex = 416 e1000_phy_force_speed_duplex_82577; 417 phy->ops.get_cable_length = e1000_get_cable_length_82577; 418 phy->ops.get_info = e1000_get_phy_info_82577; 419 phy->ops.commit = e1000e_phy_sw_reset; 420 break; 421 case e1000_phy_82578: 422 phy->ops.check_polarity = e1000_check_polarity_m88; 423 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 424 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 425 phy->ops.get_info = e1000e_get_phy_info_m88; 426 break; 427 default: 428 ret_val = -E1000_ERR_PHY; 429 break; 430 } 431 432 return ret_val; 433 } 434 435 /** 436 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 437 * @hw: pointer to the HW structure 438 * 439 * Initialize family-specific PHY parameters and function pointers. 440 **/ 441 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 442 { 443 struct e1000_phy_info *phy = &hw->phy; 444 s32 ret_val; 445 u16 i = 0; 446 447 phy->addr = 1; 448 phy->reset_delay_us = 100; 449 450 phy->ops.power_up = e1000_power_up_phy_copper; 451 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 452 453 /* We may need to do this twice - once for IGP and if that fails, 454 * we'll set BM func pointers and try again 455 */ 456 ret_val = e1000e_determine_phy_address(hw); 457 if (ret_val) { 458 phy->ops.write_reg = e1000e_write_phy_reg_bm; 459 phy->ops.read_reg = e1000e_read_phy_reg_bm; 460 ret_val = e1000e_determine_phy_address(hw); 461 if (ret_val) { 462 e_dbg("Cannot determine PHY addr. Erroring out\n"); 463 return ret_val; 464 } 465 } 466 467 phy->id = 0; 468 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 469 (i++ < 100)) { 470 usleep_range(1000, 2000); 471 ret_val = e1000e_get_phy_id(hw); 472 if (ret_val) 473 return ret_val; 474 } 475 476 /* Verify phy id */ 477 switch (phy->id) { 478 case IGP03E1000_E_PHY_ID: 479 phy->type = e1000_phy_igp_3; 480 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 481 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 482 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 483 phy->ops.get_info = e1000e_get_phy_info_igp; 484 phy->ops.check_polarity = e1000_check_polarity_igp; 485 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 486 break; 487 case IFE_E_PHY_ID: 488 case IFE_PLUS_E_PHY_ID: 489 case IFE_C_E_PHY_ID: 490 phy->type = e1000_phy_ife; 491 phy->autoneg_mask = E1000_ALL_NOT_GIG; 492 phy->ops.get_info = e1000_get_phy_info_ife; 493 phy->ops.check_polarity = e1000_check_polarity_ife; 494 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 495 break; 496 case BME1000_E_PHY_ID: 497 phy->type = e1000_phy_bm; 498 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 499 phy->ops.read_reg = e1000e_read_phy_reg_bm; 500 phy->ops.write_reg = e1000e_write_phy_reg_bm; 501 phy->ops.commit = e1000e_phy_sw_reset; 502 phy->ops.get_info = e1000e_get_phy_info_m88; 503 phy->ops.check_polarity = e1000_check_polarity_m88; 504 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 505 break; 506 default: 507 return -E1000_ERR_PHY; 508 break; 509 } 510 511 return 0; 512 } 513 514 /** 515 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 516 * @hw: pointer to the HW structure 517 * 518 * Initialize family-specific NVM parameters and function 519 * pointers. 520 **/ 521 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 522 { 523 struct e1000_nvm_info *nvm = &hw->nvm; 524 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 525 u32 gfpreg, sector_base_addr, sector_end_addr; 526 u16 i; 527 528 /* Can't read flash registers if the register set isn't mapped. */ 529 if (!hw->flash_address) { 530 e_dbg("ERROR: Flash registers not mapped\n"); 531 return -E1000_ERR_CONFIG; 532 } 533 534 nvm->type = e1000_nvm_flash_sw; 535 536 gfpreg = er32flash(ICH_FLASH_GFPREG); 537 538 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 539 * Add 1 to sector_end_addr since this sector is included in 540 * the overall size. 541 */ 542 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 543 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 544 545 /* flash_base_addr is byte-aligned */ 546 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 547 548 /* find total size of the NVM, then cut in half since the total 549 * size represents two separate NVM banks. 550 */ 551 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 552 << FLASH_SECTOR_ADDR_SHIFT; 553 nvm->flash_bank_size /= 2; 554 /* Adjust to word count */ 555 nvm->flash_bank_size /= sizeof(u16); 556 557 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 558 559 /* Clear shadow ram */ 560 for (i = 0; i < nvm->word_size; i++) { 561 dev_spec->shadow_ram[i].modified = false; 562 dev_spec->shadow_ram[i].value = 0xFFFF; 563 } 564 565 return 0; 566 } 567 568 /** 569 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 570 * @hw: pointer to the HW structure 571 * 572 * Initialize family-specific MAC parameters and function 573 * pointers. 574 **/ 575 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 576 { 577 struct e1000_mac_info *mac = &hw->mac; 578 579 /* Set media type function pointer */ 580 hw->phy.media_type = e1000_media_type_copper; 581 582 /* Set mta register count */ 583 mac->mta_reg_count = 32; 584 /* Set rar entry count */ 585 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 586 if (mac->type == e1000_ich8lan) 587 mac->rar_entry_count--; 588 /* FWSM register */ 589 mac->has_fwsm = true; 590 /* ARC subsystem not supported */ 591 mac->arc_subsystem_valid = false; 592 /* Adaptive IFS supported */ 593 mac->adaptive_ifs = true; 594 595 /* LED and other operations */ 596 switch (mac->type) { 597 case e1000_ich8lan: 598 case e1000_ich9lan: 599 case e1000_ich10lan: 600 /* check management mode */ 601 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 602 /* ID LED init */ 603 mac->ops.id_led_init = e1000e_id_led_init_generic; 604 /* blink LED */ 605 mac->ops.blink_led = e1000e_blink_led_generic; 606 /* setup LED */ 607 mac->ops.setup_led = e1000e_setup_led_generic; 608 /* cleanup LED */ 609 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 610 /* turn on/off LED */ 611 mac->ops.led_on = e1000_led_on_ich8lan; 612 mac->ops.led_off = e1000_led_off_ich8lan; 613 break; 614 case e1000_pch2lan: 615 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 616 mac->ops.rar_set = e1000_rar_set_pch2lan; 617 /* fall-through */ 618 case e1000_pch_lpt: 619 case e1000_pchlan: 620 /* check management mode */ 621 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 622 /* ID LED init */ 623 mac->ops.id_led_init = e1000_id_led_init_pchlan; 624 /* setup LED */ 625 mac->ops.setup_led = e1000_setup_led_pchlan; 626 /* cleanup LED */ 627 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 628 /* turn on/off LED */ 629 mac->ops.led_on = e1000_led_on_pchlan; 630 mac->ops.led_off = e1000_led_off_pchlan; 631 break; 632 default: 633 break; 634 } 635 636 if (mac->type == e1000_pch_lpt) { 637 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 638 mac->ops.rar_set = e1000_rar_set_pch_lpt; 639 } 640 641 /* Enable PCS Lock-loss workaround for ICH8 */ 642 if (mac->type == e1000_ich8lan) 643 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 644 645 return 0; 646 } 647 648 /** 649 * __e1000_access_emi_reg_locked - Read/write EMI register 650 * @hw: pointer to the HW structure 651 * @addr: EMI address to program 652 * @data: pointer to value to read/write from/to the EMI address 653 * @read: boolean flag to indicate read or write 654 * 655 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 656 **/ 657 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 658 u16 *data, bool read) 659 { 660 s32 ret_val; 661 662 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 663 if (ret_val) 664 return ret_val; 665 666 if (read) 667 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 668 else 669 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 670 671 return ret_val; 672 } 673 674 /** 675 * e1000_read_emi_reg_locked - Read Extended Management Interface register 676 * @hw: pointer to the HW structure 677 * @addr: EMI address to program 678 * @data: value to be read from the EMI address 679 * 680 * Assumes the SW/FW/HW Semaphore is already acquired. 681 **/ 682 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 683 { 684 return __e1000_access_emi_reg_locked(hw, addr, data, true); 685 } 686 687 /** 688 * e1000_write_emi_reg_locked - Write Extended Management Interface register 689 * @hw: pointer to the HW structure 690 * @addr: EMI address to program 691 * @data: value to be written to the EMI address 692 * 693 * Assumes the SW/FW/HW Semaphore is already acquired. 694 **/ 695 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 696 { 697 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 698 } 699 700 /** 701 * e1000_set_eee_pchlan - Enable/disable EEE support 702 * @hw: pointer to the HW structure 703 * 704 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 705 * the link and the EEE capabilities of the link partner. The LPI Control 706 * register bits will remain set only if/when link is up. 707 **/ 708 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 709 { 710 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 711 s32 ret_val; 712 u16 lpi_ctrl; 713 714 if ((hw->phy.type != e1000_phy_82579) && 715 (hw->phy.type != e1000_phy_i217)) 716 return 0; 717 718 ret_val = hw->phy.ops.acquire(hw); 719 if (ret_val) 720 return ret_val; 721 722 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 723 if (ret_val) 724 goto release; 725 726 /* Clear bits that enable EEE in various speeds */ 727 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 728 729 /* Enable EEE if not disabled by user */ 730 if (!dev_spec->eee_disable) { 731 u16 lpa, pcs_status, data; 732 733 /* Save off link partner's EEE ability */ 734 switch (hw->phy.type) { 735 case e1000_phy_82579: 736 lpa = I82579_EEE_LP_ABILITY; 737 pcs_status = I82579_EEE_PCS_STATUS; 738 break; 739 case e1000_phy_i217: 740 lpa = I217_EEE_LP_ABILITY; 741 pcs_status = I217_EEE_PCS_STATUS; 742 break; 743 default: 744 ret_val = -E1000_ERR_PHY; 745 goto release; 746 } 747 ret_val = e1000_read_emi_reg_locked(hw, lpa, 748 &dev_spec->eee_lp_ability); 749 if (ret_val) 750 goto release; 751 752 /* Enable EEE only for speeds in which the link partner is 753 * EEE capable. 754 */ 755 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 756 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 757 758 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 759 e1e_rphy_locked(hw, MII_LPA, &data); 760 if (data & LPA_100FULL) 761 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 762 else 763 /* EEE is not supported in 100Half, so ignore 764 * partner's EEE in 100 ability if full-duplex 765 * is not advertised. 766 */ 767 dev_spec->eee_lp_ability &= 768 ~I82579_EEE_100_SUPPORTED; 769 } 770 771 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 772 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 773 if (ret_val) 774 goto release; 775 } 776 777 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 778 release: 779 hw->phy.ops.release(hw); 780 781 return ret_val; 782 } 783 784 /** 785 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 786 * @hw: pointer to the HW structure 787 * 788 * Checks to see of the link status of the hardware has changed. If a 789 * change in link status has been detected, then we read the PHY registers 790 * to get the current speed/duplex if link exists. 791 **/ 792 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 793 { 794 struct e1000_mac_info *mac = &hw->mac; 795 s32 ret_val; 796 bool link; 797 u16 phy_reg; 798 799 /* We only want to go out to the PHY registers to see if Auto-Neg 800 * has completed and/or if our link status has changed. The 801 * get_link_status flag is set upon receiving a Link Status 802 * Change or Rx Sequence Error interrupt. 803 */ 804 if (!mac->get_link_status) 805 return 0; 806 807 /* First we want to see if the MII Status Register reports 808 * link. If so, then we want to get the current speed/duplex 809 * of the PHY. 810 */ 811 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 812 if (ret_val) 813 return ret_val; 814 815 if (hw->mac.type == e1000_pchlan) { 816 ret_val = e1000_k1_gig_workaround_hv(hw, link); 817 if (ret_val) 818 return ret_val; 819 } 820 821 /* Clear link partner's EEE ability */ 822 hw->dev_spec.ich8lan.eee_lp_ability = 0; 823 824 if (!link) 825 return 0; /* No link detected */ 826 827 mac->get_link_status = false; 828 829 switch (hw->mac.type) { 830 case e1000_pch2lan: 831 ret_val = e1000_k1_workaround_lv(hw); 832 if (ret_val) 833 return ret_val; 834 /* fall-thru */ 835 case e1000_pchlan: 836 if (hw->phy.type == e1000_phy_82578) { 837 ret_val = e1000_link_stall_workaround_hv(hw); 838 if (ret_val) 839 return ret_val; 840 } 841 842 /* Workaround for PCHx parts in half-duplex: 843 * Set the number of preambles removed from the packet 844 * when it is passed from the PHY to the MAC to prevent 845 * the MAC from misinterpreting the packet type. 846 */ 847 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 848 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 849 850 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 851 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 852 853 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 854 break; 855 default: 856 break; 857 } 858 859 /* Check if there was DownShift, must be checked 860 * immediately after link-up 861 */ 862 e1000e_check_downshift(hw); 863 864 /* Enable/Disable EEE after link up */ 865 ret_val = e1000_set_eee_pchlan(hw); 866 if (ret_val) 867 return ret_val; 868 869 /* If we are forcing speed/duplex, then we simply return since 870 * we have already determined whether we have link or not. 871 */ 872 if (!mac->autoneg) 873 return -E1000_ERR_CONFIG; 874 875 /* Auto-Neg is enabled. Auto Speed Detection takes care 876 * of MAC speed/duplex configuration. So we only need to 877 * configure Collision Distance in the MAC. 878 */ 879 mac->ops.config_collision_dist(hw); 880 881 /* Configure Flow Control now that Auto-Neg has completed. 882 * First, we need to restore the desired flow control 883 * settings because we may have had to re-autoneg with a 884 * different link partner. 885 */ 886 ret_val = e1000e_config_fc_after_link_up(hw); 887 if (ret_val) 888 e_dbg("Error configuring flow control\n"); 889 890 return ret_val; 891 } 892 893 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 894 { 895 struct e1000_hw *hw = &adapter->hw; 896 s32 rc; 897 898 rc = e1000_init_mac_params_ich8lan(hw); 899 if (rc) 900 return rc; 901 902 rc = e1000_init_nvm_params_ich8lan(hw); 903 if (rc) 904 return rc; 905 906 switch (hw->mac.type) { 907 case e1000_ich8lan: 908 case e1000_ich9lan: 909 case e1000_ich10lan: 910 rc = e1000_init_phy_params_ich8lan(hw); 911 break; 912 case e1000_pchlan: 913 case e1000_pch2lan: 914 case e1000_pch_lpt: 915 rc = e1000_init_phy_params_pchlan(hw); 916 break; 917 default: 918 break; 919 } 920 if (rc) 921 return rc; 922 923 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 924 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 925 */ 926 if ((adapter->hw.phy.type == e1000_phy_ife) || 927 ((adapter->hw.mac.type >= e1000_pch2lan) && 928 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 929 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 930 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; 931 932 hw->mac.ops.blink_led = NULL; 933 } 934 935 if ((adapter->hw.mac.type == e1000_ich8lan) && 936 (adapter->hw.phy.type != e1000_phy_ife)) 937 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 938 939 /* Enable workaround for 82579 w/ ME enabled */ 940 if ((adapter->hw.mac.type == e1000_pch2lan) && 941 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 942 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 943 944 /* Disable EEE by default until IEEE802.3az spec is finalized */ 945 if (adapter->flags2 & FLAG2_HAS_EEE) 946 adapter->hw.dev_spec.ich8lan.eee_disable = true; 947 948 return 0; 949 } 950 951 static DEFINE_MUTEX(nvm_mutex); 952 953 /** 954 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 955 * @hw: pointer to the HW structure 956 * 957 * Acquires the mutex for performing NVM operations. 958 **/ 959 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 960 { 961 mutex_lock(&nvm_mutex); 962 963 return 0; 964 } 965 966 /** 967 * e1000_release_nvm_ich8lan - Release NVM mutex 968 * @hw: pointer to the HW structure 969 * 970 * Releases the mutex used while performing NVM operations. 971 **/ 972 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 973 { 974 mutex_unlock(&nvm_mutex); 975 } 976 977 /** 978 * e1000_acquire_swflag_ich8lan - Acquire software control flag 979 * @hw: pointer to the HW structure 980 * 981 * Acquires the software control flag for performing PHY and select 982 * MAC CSR accesses. 983 **/ 984 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 985 { 986 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 987 s32 ret_val = 0; 988 989 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 990 &hw->adapter->state)) { 991 e_dbg("contention for Phy access\n"); 992 return -E1000_ERR_PHY; 993 } 994 995 while (timeout) { 996 extcnf_ctrl = er32(EXTCNF_CTRL); 997 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 998 break; 999 1000 mdelay(1); 1001 timeout--; 1002 } 1003 1004 if (!timeout) { 1005 e_dbg("SW has already locked the resource.\n"); 1006 ret_val = -E1000_ERR_CONFIG; 1007 goto out; 1008 } 1009 1010 timeout = SW_FLAG_TIMEOUT; 1011 1012 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1013 ew32(EXTCNF_CTRL, extcnf_ctrl); 1014 1015 while (timeout) { 1016 extcnf_ctrl = er32(EXTCNF_CTRL); 1017 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1018 break; 1019 1020 mdelay(1); 1021 timeout--; 1022 } 1023 1024 if (!timeout) { 1025 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1026 er32(FWSM), extcnf_ctrl); 1027 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1028 ew32(EXTCNF_CTRL, extcnf_ctrl); 1029 ret_val = -E1000_ERR_CONFIG; 1030 goto out; 1031 } 1032 1033 out: 1034 if (ret_val) 1035 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1036 1037 return ret_val; 1038 } 1039 1040 /** 1041 * e1000_release_swflag_ich8lan - Release software control flag 1042 * @hw: pointer to the HW structure 1043 * 1044 * Releases the software control flag for performing PHY and select 1045 * MAC CSR accesses. 1046 **/ 1047 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1048 { 1049 u32 extcnf_ctrl; 1050 1051 extcnf_ctrl = er32(EXTCNF_CTRL); 1052 1053 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1054 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1055 ew32(EXTCNF_CTRL, extcnf_ctrl); 1056 } else { 1057 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1058 } 1059 1060 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1061 } 1062 1063 /** 1064 * e1000_check_mng_mode_ich8lan - Checks management mode 1065 * @hw: pointer to the HW structure 1066 * 1067 * This checks if the adapter has any manageability enabled. 1068 * This is a function pointer entry point only called by read/write 1069 * routines for the PHY and NVM parts. 1070 **/ 1071 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1072 { 1073 u32 fwsm; 1074 1075 fwsm = er32(FWSM); 1076 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1077 ((fwsm & E1000_FWSM_MODE_MASK) == 1078 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1079 } 1080 1081 /** 1082 * e1000_check_mng_mode_pchlan - Checks management mode 1083 * @hw: pointer to the HW structure 1084 * 1085 * This checks if the adapter has iAMT enabled. 1086 * This is a function pointer entry point only called by read/write 1087 * routines for the PHY and NVM parts. 1088 **/ 1089 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1090 { 1091 u32 fwsm; 1092 1093 fwsm = er32(FWSM); 1094 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1095 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1096 } 1097 1098 /** 1099 * e1000_rar_set_pch2lan - Set receive address register 1100 * @hw: pointer to the HW structure 1101 * @addr: pointer to the receive address 1102 * @index: receive address array register 1103 * 1104 * Sets the receive address array register at index to the address passed 1105 * in by addr. For 82579, RAR[0] is the base address register that is to 1106 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1107 * Use SHRA[0-3] in place of those reserved for ME. 1108 **/ 1109 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1110 { 1111 u32 rar_low, rar_high; 1112 1113 /* HW expects these in little endian so we reverse the byte order 1114 * from network order (big endian) to little endian 1115 */ 1116 rar_low = ((u32)addr[0] | 1117 ((u32)addr[1] << 8) | 1118 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1119 1120 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1121 1122 /* If MAC address zero, no need to set the AV bit */ 1123 if (rar_low || rar_high) 1124 rar_high |= E1000_RAH_AV; 1125 1126 if (index == 0) { 1127 ew32(RAL(index), rar_low); 1128 e1e_flush(); 1129 ew32(RAH(index), rar_high); 1130 e1e_flush(); 1131 return; 1132 } 1133 1134 if (index < hw->mac.rar_entry_count) { 1135 s32 ret_val; 1136 1137 ret_val = e1000_acquire_swflag_ich8lan(hw); 1138 if (ret_val) 1139 goto out; 1140 1141 ew32(SHRAL(index - 1), rar_low); 1142 e1e_flush(); 1143 ew32(SHRAH(index - 1), rar_high); 1144 e1e_flush(); 1145 1146 e1000_release_swflag_ich8lan(hw); 1147 1148 /* verify the register updates */ 1149 if ((er32(SHRAL(index - 1)) == rar_low) && 1150 (er32(SHRAH(index - 1)) == rar_high)) 1151 return; 1152 1153 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1154 (index - 1), er32(FWSM)); 1155 } 1156 1157 out: 1158 e_dbg("Failed to write receive address at index %d\n", index); 1159 } 1160 1161 /** 1162 * e1000_rar_set_pch_lpt - Set receive address registers 1163 * @hw: pointer to the HW structure 1164 * @addr: pointer to the receive address 1165 * @index: receive address array register 1166 * 1167 * Sets the receive address register array at index to the address passed 1168 * in by addr. For LPT, RAR[0] is the base address register that is to 1169 * contain the MAC address. SHRA[0-10] are the shared receive address 1170 * registers that are shared between the Host and manageability engine (ME). 1171 **/ 1172 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1173 { 1174 u32 rar_low, rar_high; 1175 u32 wlock_mac; 1176 1177 /* HW expects these in little endian so we reverse the byte order 1178 * from network order (big endian) to little endian 1179 */ 1180 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1181 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1182 1183 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1184 1185 /* If MAC address zero, no need to set the AV bit */ 1186 if (rar_low || rar_high) 1187 rar_high |= E1000_RAH_AV; 1188 1189 if (index == 0) { 1190 ew32(RAL(index), rar_low); 1191 e1e_flush(); 1192 ew32(RAH(index), rar_high); 1193 e1e_flush(); 1194 return; 1195 } 1196 1197 /* The manageability engine (ME) can lock certain SHRAR registers that 1198 * it is using - those registers are unavailable for use. 1199 */ 1200 if (index < hw->mac.rar_entry_count) { 1201 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1202 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1203 1204 /* Check if all SHRAR registers are locked */ 1205 if (wlock_mac == 1) 1206 goto out; 1207 1208 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1209 s32 ret_val; 1210 1211 ret_val = e1000_acquire_swflag_ich8lan(hw); 1212 1213 if (ret_val) 1214 goto out; 1215 1216 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1217 e1e_flush(); 1218 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1219 e1e_flush(); 1220 1221 e1000_release_swflag_ich8lan(hw); 1222 1223 /* verify the register updates */ 1224 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1225 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1226 return; 1227 } 1228 } 1229 1230 out: 1231 e_dbg("Failed to write receive address at index %d\n", index); 1232 } 1233 1234 /** 1235 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 1236 * @hw: pointer to the HW structure 1237 * 1238 * Checks if firmware is blocking the reset of the PHY. 1239 * This is a function pointer entry point only called by 1240 * reset routines. 1241 **/ 1242 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 1243 { 1244 u32 fwsm; 1245 1246 fwsm = er32(FWSM); 1247 1248 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; 1249 } 1250 1251 /** 1252 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 1253 * @hw: pointer to the HW structure 1254 * 1255 * Assumes semaphore already acquired. 1256 * 1257 **/ 1258 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 1259 { 1260 u16 phy_data; 1261 u32 strap = er32(STRAP); 1262 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 1263 E1000_STRAP_SMT_FREQ_SHIFT; 1264 s32 ret_val; 1265 1266 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 1267 1268 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 1269 if (ret_val) 1270 return ret_val; 1271 1272 phy_data &= ~HV_SMB_ADDR_MASK; 1273 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 1274 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 1275 1276 if (hw->phy.type == e1000_phy_i217) { 1277 /* Restore SMBus frequency */ 1278 if (freq--) { 1279 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 1280 phy_data |= (freq & (1 << 0)) << 1281 HV_SMB_ADDR_FREQ_LOW_SHIFT; 1282 phy_data |= (freq & (1 << 1)) << 1283 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 1284 } else { 1285 e_dbg("Unsupported SMB frequency in PHY\n"); 1286 } 1287 } 1288 1289 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 1290 } 1291 1292 /** 1293 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 1294 * @hw: pointer to the HW structure 1295 * 1296 * SW should configure the LCD from the NVM extended configuration region 1297 * as a workaround for certain parts. 1298 **/ 1299 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 1300 { 1301 struct e1000_phy_info *phy = &hw->phy; 1302 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 1303 s32 ret_val = 0; 1304 u16 word_addr, reg_data, reg_addr, phy_page = 0; 1305 1306 /* Initialize the PHY from the NVM on ICH platforms. This 1307 * is needed due to an issue where the NVM configuration is 1308 * not properly autoloaded after power transitions. 1309 * Therefore, after each PHY reset, we will load the 1310 * configuration data out of the NVM manually. 1311 */ 1312 switch (hw->mac.type) { 1313 case e1000_ich8lan: 1314 if (phy->type != e1000_phy_igp_3) 1315 return ret_val; 1316 1317 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 1318 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 1319 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 1320 break; 1321 } 1322 /* Fall-thru */ 1323 case e1000_pchlan: 1324 case e1000_pch2lan: 1325 case e1000_pch_lpt: 1326 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 1327 break; 1328 default: 1329 return ret_val; 1330 } 1331 1332 ret_val = hw->phy.ops.acquire(hw); 1333 if (ret_val) 1334 return ret_val; 1335 1336 data = er32(FEXTNVM); 1337 if (!(data & sw_cfg_mask)) 1338 goto release; 1339 1340 /* Make sure HW does not configure LCD from PHY 1341 * extended configuration before SW configuration 1342 */ 1343 data = er32(EXTCNF_CTRL); 1344 if ((hw->mac.type < e1000_pch2lan) && 1345 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 1346 goto release; 1347 1348 cnf_size = er32(EXTCNF_SIZE); 1349 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 1350 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 1351 if (!cnf_size) 1352 goto release; 1353 1354 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 1355 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 1356 1357 if (((hw->mac.type == e1000_pchlan) && 1358 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 1359 (hw->mac.type > e1000_pchlan)) { 1360 /* HW configures the SMBus address and LEDs when the 1361 * OEM and LCD Write Enable bits are set in the NVM. 1362 * When both NVM bits are cleared, SW will configure 1363 * them instead. 1364 */ 1365 ret_val = e1000_write_smbus_addr(hw); 1366 if (ret_val) 1367 goto release; 1368 1369 data = er32(LEDCTL); 1370 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 1371 (u16)data); 1372 if (ret_val) 1373 goto release; 1374 } 1375 1376 /* Configure LCD from extended configuration region. */ 1377 1378 /* cnf_base_addr is in DWORD */ 1379 word_addr = (u16)(cnf_base_addr << 1); 1380 1381 for (i = 0; i < cnf_size; i++) { 1382 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, 1383 ®_data); 1384 if (ret_val) 1385 goto release; 1386 1387 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 1388 1, ®_addr); 1389 if (ret_val) 1390 goto release; 1391 1392 /* Save off the PHY page for future writes. */ 1393 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 1394 phy_page = reg_data; 1395 continue; 1396 } 1397 1398 reg_addr &= PHY_REG_MASK; 1399 reg_addr |= phy_page; 1400 1401 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 1402 if (ret_val) 1403 goto release; 1404 } 1405 1406 release: 1407 hw->phy.ops.release(hw); 1408 return ret_val; 1409 } 1410 1411 /** 1412 * e1000_k1_gig_workaround_hv - K1 Si workaround 1413 * @hw: pointer to the HW structure 1414 * @link: link up bool flag 1415 * 1416 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 1417 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 1418 * If link is down, the function will restore the default K1 setting located 1419 * in the NVM. 1420 **/ 1421 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 1422 { 1423 s32 ret_val = 0; 1424 u16 status_reg = 0; 1425 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 1426 1427 if (hw->mac.type != e1000_pchlan) 1428 return 0; 1429 1430 /* Wrap the whole flow with the sw flag */ 1431 ret_val = hw->phy.ops.acquire(hw); 1432 if (ret_val) 1433 return ret_val; 1434 1435 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 1436 if (link) { 1437 if (hw->phy.type == e1000_phy_82578) { 1438 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 1439 &status_reg); 1440 if (ret_val) 1441 goto release; 1442 1443 status_reg &= BM_CS_STATUS_LINK_UP | 1444 BM_CS_STATUS_RESOLVED | 1445 BM_CS_STATUS_SPEED_MASK; 1446 1447 if (status_reg == (BM_CS_STATUS_LINK_UP | 1448 BM_CS_STATUS_RESOLVED | 1449 BM_CS_STATUS_SPEED_1000)) 1450 k1_enable = false; 1451 } 1452 1453 if (hw->phy.type == e1000_phy_82577) { 1454 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 1455 if (ret_val) 1456 goto release; 1457 1458 status_reg &= HV_M_STATUS_LINK_UP | 1459 HV_M_STATUS_AUTONEG_COMPLETE | 1460 HV_M_STATUS_SPEED_MASK; 1461 1462 if (status_reg == (HV_M_STATUS_LINK_UP | 1463 HV_M_STATUS_AUTONEG_COMPLETE | 1464 HV_M_STATUS_SPEED_1000)) 1465 k1_enable = false; 1466 } 1467 1468 /* Link stall fix for link up */ 1469 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 1470 if (ret_val) 1471 goto release; 1472 1473 } else { 1474 /* Link stall fix for link down */ 1475 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 1476 if (ret_val) 1477 goto release; 1478 } 1479 1480 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1481 1482 release: 1483 hw->phy.ops.release(hw); 1484 1485 return ret_val; 1486 } 1487 1488 /** 1489 * e1000_configure_k1_ich8lan - Configure K1 power state 1490 * @hw: pointer to the HW structure 1491 * @enable: K1 state to configure 1492 * 1493 * Configure the K1 power state based on the provided parameter. 1494 * Assumes semaphore already acquired. 1495 * 1496 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1497 **/ 1498 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 1499 { 1500 s32 ret_val; 1501 u32 ctrl_reg = 0; 1502 u32 ctrl_ext = 0; 1503 u32 reg = 0; 1504 u16 kmrn_reg = 0; 1505 1506 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1507 &kmrn_reg); 1508 if (ret_val) 1509 return ret_val; 1510 1511 if (k1_enable) 1512 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 1513 else 1514 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 1515 1516 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 1517 kmrn_reg); 1518 if (ret_val) 1519 return ret_val; 1520 1521 udelay(20); 1522 ctrl_ext = er32(CTRL_EXT); 1523 ctrl_reg = er32(CTRL); 1524 1525 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1526 reg |= E1000_CTRL_FRCSPD; 1527 ew32(CTRL, reg); 1528 1529 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 1530 e1e_flush(); 1531 udelay(20); 1532 ew32(CTRL, ctrl_reg); 1533 ew32(CTRL_EXT, ctrl_ext); 1534 e1e_flush(); 1535 udelay(20); 1536 1537 return 0; 1538 } 1539 1540 /** 1541 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 1542 * @hw: pointer to the HW structure 1543 * @d0_state: boolean if entering d0 or d3 device state 1544 * 1545 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 1546 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 1547 * in NVM determines whether HW should configure LPLU and Gbe Disable. 1548 **/ 1549 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 1550 { 1551 s32 ret_val = 0; 1552 u32 mac_reg; 1553 u16 oem_reg; 1554 1555 if (hw->mac.type < e1000_pchlan) 1556 return ret_val; 1557 1558 ret_val = hw->phy.ops.acquire(hw); 1559 if (ret_val) 1560 return ret_val; 1561 1562 if (hw->mac.type == e1000_pchlan) { 1563 mac_reg = er32(EXTCNF_CTRL); 1564 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 1565 goto release; 1566 } 1567 1568 mac_reg = er32(FEXTNVM); 1569 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 1570 goto release; 1571 1572 mac_reg = er32(PHY_CTRL); 1573 1574 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 1575 if (ret_val) 1576 goto release; 1577 1578 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 1579 1580 if (d0_state) { 1581 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 1582 oem_reg |= HV_OEM_BITS_GBE_DIS; 1583 1584 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 1585 oem_reg |= HV_OEM_BITS_LPLU; 1586 } else { 1587 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 1588 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 1589 oem_reg |= HV_OEM_BITS_GBE_DIS; 1590 1591 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 1592 E1000_PHY_CTRL_NOND0A_LPLU)) 1593 oem_reg |= HV_OEM_BITS_LPLU; 1594 } 1595 1596 /* Set Restart auto-neg to activate the bits */ 1597 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 1598 !hw->phy.ops.check_reset_block(hw)) 1599 oem_reg |= HV_OEM_BITS_RESTART_AN; 1600 1601 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 1602 1603 release: 1604 hw->phy.ops.release(hw); 1605 1606 return ret_val; 1607 } 1608 1609 1610 /** 1611 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 1612 * @hw: pointer to the HW structure 1613 **/ 1614 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 1615 { 1616 s32 ret_val; 1617 u16 data; 1618 1619 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 1620 if (ret_val) 1621 return ret_val; 1622 1623 data |= HV_KMRN_MDIO_SLOW; 1624 1625 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 1626 1627 return ret_val; 1628 } 1629 1630 /** 1631 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1632 * done after every PHY reset. 1633 **/ 1634 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1635 { 1636 s32 ret_val = 0; 1637 u16 phy_data; 1638 1639 if (hw->mac.type != e1000_pchlan) 1640 return 0; 1641 1642 /* Set MDIO slow mode before any other MDIO access */ 1643 if (hw->phy.type == e1000_phy_82577) { 1644 ret_val = e1000_set_mdio_slow_mode_hv(hw); 1645 if (ret_val) 1646 return ret_val; 1647 } 1648 1649 if (((hw->phy.type == e1000_phy_82577) && 1650 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 1651 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 1652 /* Disable generation of early preamble */ 1653 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 1654 if (ret_val) 1655 return ret_val; 1656 1657 /* Preamble tuning for SSC */ 1658 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 1659 if (ret_val) 1660 return ret_val; 1661 } 1662 1663 if (hw->phy.type == e1000_phy_82578) { 1664 /* Return registers to default by doing a soft reset then 1665 * writing 0x3140 to the control register. 1666 */ 1667 if (hw->phy.revision < 2) { 1668 e1000e_phy_sw_reset(hw); 1669 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 1670 } 1671 } 1672 1673 /* Select page 0 */ 1674 ret_val = hw->phy.ops.acquire(hw); 1675 if (ret_val) 1676 return ret_val; 1677 1678 hw->phy.addr = 1; 1679 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1680 hw->phy.ops.release(hw); 1681 if (ret_val) 1682 return ret_val; 1683 1684 /* Configure the K1 Si workaround during phy reset assuming there is 1685 * link so that it disables K1 if link is in 1Gbps. 1686 */ 1687 ret_val = e1000_k1_gig_workaround_hv(hw, true); 1688 if (ret_val) 1689 return ret_val; 1690 1691 /* Workaround for link disconnects on a busy hub in half duplex */ 1692 ret_val = hw->phy.ops.acquire(hw); 1693 if (ret_val) 1694 return ret_val; 1695 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 1696 if (ret_val) 1697 goto release; 1698 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 1699 if (ret_val) 1700 goto release; 1701 1702 /* set MSE higher to enable link to stay up when noise is high */ 1703 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 1704 release: 1705 hw->phy.ops.release(hw); 1706 1707 return ret_val; 1708 } 1709 1710 /** 1711 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 1712 * @hw: pointer to the HW structure 1713 **/ 1714 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 1715 { 1716 u32 mac_reg; 1717 u16 i, phy_reg = 0; 1718 s32 ret_val; 1719 1720 ret_val = hw->phy.ops.acquire(hw); 1721 if (ret_val) 1722 return; 1723 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1724 if (ret_val) 1725 goto release; 1726 1727 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ 1728 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1729 mac_reg = er32(RAL(i)); 1730 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 1731 (u16)(mac_reg & 0xFFFF)); 1732 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 1733 (u16)((mac_reg >> 16) & 0xFFFF)); 1734 1735 mac_reg = er32(RAH(i)); 1736 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 1737 (u16)(mac_reg & 0xFFFF)); 1738 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 1739 (u16)((mac_reg & E1000_RAH_AV) 1740 >> 16)); 1741 } 1742 1743 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 1744 1745 release: 1746 hw->phy.ops.release(hw); 1747 } 1748 1749 /** 1750 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 1751 * with 82579 PHY 1752 * @hw: pointer to the HW structure 1753 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 1754 **/ 1755 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 1756 { 1757 s32 ret_val = 0; 1758 u16 phy_reg, data; 1759 u32 mac_reg; 1760 u16 i; 1761 1762 if (hw->mac.type < e1000_pch2lan) 1763 return 0; 1764 1765 /* disable Rx path while enabling/disabling workaround */ 1766 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 1767 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); 1768 if (ret_val) 1769 return ret_val; 1770 1771 if (enable) { 1772 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for 1773 * SHRAL/H) and initial CRC values to the MAC 1774 */ 1775 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1776 u8 mac_addr[ETH_ALEN] = {0}; 1777 u32 addr_high, addr_low; 1778 1779 addr_high = er32(RAH(i)); 1780 if (!(addr_high & E1000_RAH_AV)) 1781 continue; 1782 addr_low = er32(RAL(i)); 1783 mac_addr[0] = (addr_low & 0xFF); 1784 mac_addr[1] = ((addr_low >> 8) & 0xFF); 1785 mac_addr[2] = ((addr_low >> 16) & 0xFF); 1786 mac_addr[3] = ((addr_low >> 24) & 0xFF); 1787 mac_addr[4] = (addr_high & 0xFF); 1788 mac_addr[5] = ((addr_high >> 8) & 0xFF); 1789 1790 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 1791 } 1792 1793 /* Write Rx addresses to the PHY */ 1794 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 1795 1796 /* Enable jumbo frame workaround in the MAC */ 1797 mac_reg = er32(FFLT_DBG); 1798 mac_reg &= ~(1 << 14); 1799 mac_reg |= (7 << 15); 1800 ew32(FFLT_DBG, mac_reg); 1801 1802 mac_reg = er32(RCTL); 1803 mac_reg |= E1000_RCTL_SECRC; 1804 ew32(RCTL, mac_reg); 1805 1806 ret_val = e1000e_read_kmrn_reg(hw, 1807 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1808 &data); 1809 if (ret_val) 1810 return ret_val; 1811 ret_val = e1000e_write_kmrn_reg(hw, 1812 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1813 data | (1 << 0)); 1814 if (ret_val) 1815 return ret_val; 1816 ret_val = e1000e_read_kmrn_reg(hw, 1817 E1000_KMRNCTRLSTA_HD_CTRL, 1818 &data); 1819 if (ret_val) 1820 return ret_val; 1821 data &= ~(0xF << 8); 1822 data |= (0xB << 8); 1823 ret_val = e1000e_write_kmrn_reg(hw, 1824 E1000_KMRNCTRLSTA_HD_CTRL, 1825 data); 1826 if (ret_val) 1827 return ret_val; 1828 1829 /* Enable jumbo frame workaround in the PHY */ 1830 e1e_rphy(hw, PHY_REG(769, 23), &data); 1831 data &= ~(0x7F << 5); 1832 data |= (0x37 << 5); 1833 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 1834 if (ret_val) 1835 return ret_val; 1836 e1e_rphy(hw, PHY_REG(769, 16), &data); 1837 data &= ~(1 << 13); 1838 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 1839 if (ret_val) 1840 return ret_val; 1841 e1e_rphy(hw, PHY_REG(776, 20), &data); 1842 data &= ~(0x3FF << 2); 1843 data |= (0x1A << 2); 1844 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 1845 if (ret_val) 1846 return ret_val; 1847 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 1848 if (ret_val) 1849 return ret_val; 1850 e1e_rphy(hw, HV_PM_CTRL, &data); 1851 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); 1852 if (ret_val) 1853 return ret_val; 1854 } else { 1855 /* Write MAC register values back to h/w defaults */ 1856 mac_reg = er32(FFLT_DBG); 1857 mac_reg &= ~(0xF << 14); 1858 ew32(FFLT_DBG, mac_reg); 1859 1860 mac_reg = er32(RCTL); 1861 mac_reg &= ~E1000_RCTL_SECRC; 1862 ew32(RCTL, mac_reg); 1863 1864 ret_val = e1000e_read_kmrn_reg(hw, 1865 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1866 &data); 1867 if (ret_val) 1868 return ret_val; 1869 ret_val = e1000e_write_kmrn_reg(hw, 1870 E1000_KMRNCTRLSTA_CTRL_OFFSET, 1871 data & ~(1 << 0)); 1872 if (ret_val) 1873 return ret_val; 1874 ret_val = e1000e_read_kmrn_reg(hw, 1875 E1000_KMRNCTRLSTA_HD_CTRL, 1876 &data); 1877 if (ret_val) 1878 return ret_val; 1879 data &= ~(0xF << 8); 1880 data |= (0xB << 8); 1881 ret_val = e1000e_write_kmrn_reg(hw, 1882 E1000_KMRNCTRLSTA_HD_CTRL, 1883 data); 1884 if (ret_val) 1885 return ret_val; 1886 1887 /* Write PHY register values back to h/w defaults */ 1888 e1e_rphy(hw, PHY_REG(769, 23), &data); 1889 data &= ~(0x7F << 5); 1890 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 1891 if (ret_val) 1892 return ret_val; 1893 e1e_rphy(hw, PHY_REG(769, 16), &data); 1894 data |= (1 << 13); 1895 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 1896 if (ret_val) 1897 return ret_val; 1898 e1e_rphy(hw, PHY_REG(776, 20), &data); 1899 data &= ~(0x3FF << 2); 1900 data |= (0x8 << 2); 1901 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 1902 if (ret_val) 1903 return ret_val; 1904 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 1905 if (ret_val) 1906 return ret_val; 1907 e1e_rphy(hw, HV_PM_CTRL, &data); 1908 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); 1909 if (ret_val) 1910 return ret_val; 1911 } 1912 1913 /* re-enable Rx path after enabling/disabling workaround */ 1914 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); 1915 } 1916 1917 /** 1918 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 1919 * done after every PHY reset. 1920 **/ 1921 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 1922 { 1923 s32 ret_val = 0; 1924 1925 if (hw->mac.type != e1000_pch2lan) 1926 return 0; 1927 1928 /* Set MDIO slow mode before any other MDIO access */ 1929 ret_val = e1000_set_mdio_slow_mode_hv(hw); 1930 if (ret_val) 1931 return ret_val; 1932 1933 ret_val = hw->phy.ops.acquire(hw); 1934 if (ret_val) 1935 return ret_val; 1936 /* set MSE higher to enable link to stay up when noise is high */ 1937 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 1938 if (ret_val) 1939 goto release; 1940 /* drop link after 5 times MSE threshold was reached */ 1941 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 1942 release: 1943 hw->phy.ops.release(hw); 1944 1945 return ret_val; 1946 } 1947 1948 /** 1949 * e1000_k1_gig_workaround_lv - K1 Si workaround 1950 * @hw: pointer to the HW structure 1951 * 1952 * Workaround to set the K1 beacon duration for 82579 parts 1953 **/ 1954 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 1955 { 1956 s32 ret_val = 0; 1957 u16 status_reg = 0; 1958 u32 mac_reg; 1959 u16 phy_reg; 1960 1961 if (hw->mac.type != e1000_pch2lan) 1962 return 0; 1963 1964 /* Set K1 beacon duration based on 1Gbps speed or otherwise */ 1965 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 1966 if (ret_val) 1967 return ret_val; 1968 1969 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 1970 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 1971 mac_reg = er32(FEXTNVM4); 1972 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1973 1974 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); 1975 if (ret_val) 1976 return ret_val; 1977 1978 if (status_reg & HV_M_STATUS_SPEED_1000) { 1979 u16 pm_phy_reg; 1980 1981 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1982 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 1983 /* LV 1G Packet drop issue wa */ 1984 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 1985 if (ret_val) 1986 return ret_val; 1987 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; 1988 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 1989 if (ret_val) 1990 return ret_val; 1991 } else { 1992 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 1993 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; 1994 } 1995 ew32(FEXTNVM4, mac_reg); 1996 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); 1997 } 1998 1999 return ret_val; 2000 } 2001 2002 /** 2003 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2004 * @hw: pointer to the HW structure 2005 * @gate: boolean set to true to gate, false to ungate 2006 * 2007 * Gate/ungate the automatic PHY configuration via hardware; perform 2008 * the configuration via software instead. 2009 **/ 2010 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2011 { 2012 u32 extcnf_ctrl; 2013 2014 if (hw->mac.type < e1000_pch2lan) 2015 return; 2016 2017 extcnf_ctrl = er32(EXTCNF_CTRL); 2018 2019 if (gate) 2020 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2021 else 2022 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2023 2024 ew32(EXTCNF_CTRL, extcnf_ctrl); 2025 } 2026 2027 /** 2028 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2029 * @hw: pointer to the HW structure 2030 * 2031 * Check the appropriate indication the MAC has finished configuring the 2032 * PHY after a software reset. 2033 **/ 2034 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2035 { 2036 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2037 2038 /* Wait for basic configuration completes before proceeding */ 2039 do { 2040 data = er32(STATUS); 2041 data &= E1000_STATUS_LAN_INIT_DONE; 2042 udelay(100); 2043 } while ((!data) && --loop); 2044 2045 /* If basic configuration is incomplete before the above loop 2046 * count reaches 0, loading the configuration from NVM will 2047 * leave the PHY in a bad state possibly resulting in no link. 2048 */ 2049 if (loop == 0) 2050 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2051 2052 /* Clear the Init Done bit for the next init event */ 2053 data = er32(STATUS); 2054 data &= ~E1000_STATUS_LAN_INIT_DONE; 2055 ew32(STATUS, data); 2056 } 2057 2058 /** 2059 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2060 * @hw: pointer to the HW structure 2061 **/ 2062 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2063 { 2064 s32 ret_val = 0; 2065 u16 reg; 2066 2067 if (hw->phy.ops.check_reset_block(hw)) 2068 return 0; 2069 2070 /* Allow time for h/w to get to quiescent state after reset */ 2071 usleep_range(10000, 20000); 2072 2073 /* Perform any necessary post-reset workarounds */ 2074 switch (hw->mac.type) { 2075 case e1000_pchlan: 2076 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2077 if (ret_val) 2078 return ret_val; 2079 break; 2080 case e1000_pch2lan: 2081 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2082 if (ret_val) 2083 return ret_val; 2084 break; 2085 default: 2086 break; 2087 } 2088 2089 /* Clear the host wakeup bit after lcd reset */ 2090 if (hw->mac.type >= e1000_pchlan) { 2091 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2092 reg &= ~BM_WUC_HOST_WU_BIT; 2093 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2094 } 2095 2096 /* Configure the LCD with the extended configuration region in NVM */ 2097 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2098 if (ret_val) 2099 return ret_val; 2100 2101 /* Configure the LCD with the OEM bits in NVM */ 2102 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2103 2104 if (hw->mac.type == e1000_pch2lan) { 2105 /* Ungate automatic PHY configuration on non-managed 82579 */ 2106 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2107 usleep_range(10000, 20000); 2108 e1000_gate_hw_phy_config_ich8lan(hw, false); 2109 } 2110 2111 /* Set EEE LPI Update Timer to 200usec */ 2112 ret_val = hw->phy.ops.acquire(hw); 2113 if (ret_val) 2114 return ret_val; 2115 ret_val = e1000_write_emi_reg_locked(hw, 2116 I82579_LPI_UPDATE_TIMER, 2117 0x1387); 2118 hw->phy.ops.release(hw); 2119 } 2120 2121 return ret_val; 2122 } 2123 2124 /** 2125 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2126 * @hw: pointer to the HW structure 2127 * 2128 * Resets the PHY 2129 * This is a function pointer entry point called by drivers 2130 * or other shared routines. 2131 **/ 2132 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2133 { 2134 s32 ret_val = 0; 2135 2136 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2137 if ((hw->mac.type == e1000_pch2lan) && 2138 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2139 e1000_gate_hw_phy_config_ich8lan(hw, true); 2140 2141 ret_val = e1000e_phy_hw_reset_generic(hw); 2142 if (ret_val) 2143 return ret_val; 2144 2145 return e1000_post_phy_reset_ich8lan(hw); 2146 } 2147 2148 /** 2149 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2150 * @hw: pointer to the HW structure 2151 * @active: true to enable LPLU, false to disable 2152 * 2153 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2154 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2155 * the phy speed. This function will manually set the LPLU bit and restart 2156 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2157 * since it configures the same bit. 2158 **/ 2159 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2160 { 2161 s32 ret_val; 2162 u16 oem_reg; 2163 2164 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2165 if (ret_val) 2166 return ret_val; 2167 2168 if (active) 2169 oem_reg |= HV_OEM_BITS_LPLU; 2170 else 2171 oem_reg &= ~HV_OEM_BITS_LPLU; 2172 2173 if (!hw->phy.ops.check_reset_block(hw)) 2174 oem_reg |= HV_OEM_BITS_RESTART_AN; 2175 2176 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2177 } 2178 2179 /** 2180 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2181 * @hw: pointer to the HW structure 2182 * @active: true to enable LPLU, false to disable 2183 * 2184 * Sets the LPLU D0 state according to the active flag. When 2185 * activating LPLU this function also disables smart speed 2186 * and vice versa. LPLU will not be activated unless the 2187 * device autonegotiation advertisement meets standards of 2188 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2189 * This is a function pointer entry point only called by 2190 * PHY setup routines. 2191 **/ 2192 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2193 { 2194 struct e1000_phy_info *phy = &hw->phy; 2195 u32 phy_ctrl; 2196 s32 ret_val = 0; 2197 u16 data; 2198 2199 if (phy->type == e1000_phy_ife) 2200 return 0; 2201 2202 phy_ctrl = er32(PHY_CTRL); 2203 2204 if (active) { 2205 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2206 ew32(PHY_CTRL, phy_ctrl); 2207 2208 if (phy->type != e1000_phy_igp_3) 2209 return 0; 2210 2211 /* Call gig speed drop workaround on LPLU before accessing 2212 * any PHY registers 2213 */ 2214 if (hw->mac.type == e1000_ich8lan) 2215 e1000e_gig_downshift_workaround_ich8lan(hw); 2216 2217 /* When LPLU is enabled, we should disable SmartSpeed */ 2218 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2219 if (ret_val) 2220 return ret_val; 2221 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2222 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2223 if (ret_val) 2224 return ret_val; 2225 } else { 2226 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2227 ew32(PHY_CTRL, phy_ctrl); 2228 2229 if (phy->type != e1000_phy_igp_3) 2230 return 0; 2231 2232 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2233 * during Dx states where the power conservation is most 2234 * important. During driver activity we should enable 2235 * SmartSpeed, so performance is maintained. 2236 */ 2237 if (phy->smart_speed == e1000_smart_speed_on) { 2238 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2239 &data); 2240 if (ret_val) 2241 return ret_val; 2242 2243 data |= IGP01E1000_PSCFR_SMART_SPEED; 2244 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2245 data); 2246 if (ret_val) 2247 return ret_val; 2248 } else if (phy->smart_speed == e1000_smart_speed_off) { 2249 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2250 &data); 2251 if (ret_val) 2252 return ret_val; 2253 2254 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2255 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2256 data); 2257 if (ret_val) 2258 return ret_val; 2259 } 2260 } 2261 2262 return 0; 2263 } 2264 2265 /** 2266 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 2267 * @hw: pointer to the HW structure 2268 * @active: true to enable LPLU, false to disable 2269 * 2270 * Sets the LPLU D3 state according to the active flag. When 2271 * activating LPLU this function also disables smart speed 2272 * and vice versa. LPLU will not be activated unless the 2273 * device autonegotiation advertisement meets standards of 2274 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2275 * This is a function pointer entry point only called by 2276 * PHY setup routines. 2277 **/ 2278 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2279 { 2280 struct e1000_phy_info *phy = &hw->phy; 2281 u32 phy_ctrl; 2282 s32 ret_val = 0; 2283 u16 data; 2284 2285 phy_ctrl = er32(PHY_CTRL); 2286 2287 if (!active) { 2288 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 2289 ew32(PHY_CTRL, phy_ctrl); 2290 2291 if (phy->type != e1000_phy_igp_3) 2292 return 0; 2293 2294 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2295 * during Dx states where the power conservation is most 2296 * important. During driver activity we should enable 2297 * SmartSpeed, so performance is maintained. 2298 */ 2299 if (phy->smart_speed == e1000_smart_speed_on) { 2300 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2301 &data); 2302 if (ret_val) 2303 return ret_val; 2304 2305 data |= IGP01E1000_PSCFR_SMART_SPEED; 2306 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2307 data); 2308 if (ret_val) 2309 return ret_val; 2310 } else if (phy->smart_speed == e1000_smart_speed_off) { 2311 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2312 &data); 2313 if (ret_val) 2314 return ret_val; 2315 2316 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2317 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 2318 data); 2319 if (ret_val) 2320 return ret_val; 2321 } 2322 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2323 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2324 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2325 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 2326 ew32(PHY_CTRL, phy_ctrl); 2327 2328 if (phy->type != e1000_phy_igp_3) 2329 return 0; 2330 2331 /* Call gig speed drop workaround on LPLU before accessing 2332 * any PHY registers 2333 */ 2334 if (hw->mac.type == e1000_ich8lan) 2335 e1000e_gig_downshift_workaround_ich8lan(hw); 2336 2337 /* When LPLU is enabled, we should disable SmartSpeed */ 2338 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2339 if (ret_val) 2340 return ret_val; 2341 2342 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2343 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2344 } 2345 2346 return ret_val; 2347 } 2348 2349 /** 2350 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 2351 * @hw: pointer to the HW structure 2352 * @bank: pointer to the variable that returns the active bank 2353 * 2354 * Reads signature byte from the NVM using the flash access registers. 2355 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 2356 **/ 2357 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 2358 { 2359 u32 eecd; 2360 struct e1000_nvm_info *nvm = &hw->nvm; 2361 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 2362 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 2363 u8 sig_byte = 0; 2364 s32 ret_val; 2365 2366 switch (hw->mac.type) { 2367 case e1000_ich8lan: 2368 case e1000_ich9lan: 2369 eecd = er32(EECD); 2370 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 2371 E1000_EECD_SEC1VAL_VALID_MASK) { 2372 if (eecd & E1000_EECD_SEC1VAL) 2373 *bank = 1; 2374 else 2375 *bank = 0; 2376 2377 return 0; 2378 } 2379 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 2380 /* fall-thru */ 2381 default: 2382 /* set bank to 0 in case flash read fails */ 2383 *bank = 0; 2384 2385 /* Check bank 0 */ 2386 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 2387 &sig_byte); 2388 if (ret_val) 2389 return ret_val; 2390 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2391 E1000_ICH_NVM_SIG_VALUE) { 2392 *bank = 0; 2393 return 0; 2394 } 2395 2396 /* Check bank 1 */ 2397 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 2398 bank1_offset, 2399 &sig_byte); 2400 if (ret_val) 2401 return ret_val; 2402 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 2403 E1000_ICH_NVM_SIG_VALUE) { 2404 *bank = 1; 2405 return 0; 2406 } 2407 2408 e_dbg("ERROR: No valid NVM bank present\n"); 2409 return -E1000_ERR_NVM; 2410 } 2411 } 2412 2413 /** 2414 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 2415 * @hw: pointer to the HW structure 2416 * @offset: The offset (in bytes) of the word(s) to read. 2417 * @words: Size of data to read in words 2418 * @data: Pointer to the word(s) to read at offset. 2419 * 2420 * Reads a word(s) from the NVM using the flash access registers. 2421 **/ 2422 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2423 u16 *data) 2424 { 2425 struct e1000_nvm_info *nvm = &hw->nvm; 2426 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2427 u32 act_offset; 2428 s32 ret_val = 0; 2429 u32 bank = 0; 2430 u16 i, word; 2431 2432 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2433 (words == 0)) { 2434 e_dbg("nvm parameter(s) out of bounds\n"); 2435 ret_val = -E1000_ERR_NVM; 2436 goto out; 2437 } 2438 2439 nvm->ops.acquire(hw); 2440 2441 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2442 if (ret_val) { 2443 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2444 bank = 0; 2445 } 2446 2447 act_offset = (bank) ? nvm->flash_bank_size : 0; 2448 act_offset += offset; 2449 2450 ret_val = 0; 2451 for (i = 0; i < words; i++) { 2452 if (dev_spec->shadow_ram[offset+i].modified) { 2453 data[i] = dev_spec->shadow_ram[offset+i].value; 2454 } else { 2455 ret_val = e1000_read_flash_word_ich8lan(hw, 2456 act_offset + i, 2457 &word); 2458 if (ret_val) 2459 break; 2460 data[i] = word; 2461 } 2462 } 2463 2464 nvm->ops.release(hw); 2465 2466 out: 2467 if (ret_val) 2468 e_dbg("NVM read error: %d\n", ret_val); 2469 2470 return ret_val; 2471 } 2472 2473 /** 2474 * e1000_flash_cycle_init_ich8lan - Initialize flash 2475 * @hw: pointer to the HW structure 2476 * 2477 * This function does initial flash setup so that a new read/write/erase cycle 2478 * can be started. 2479 **/ 2480 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 2481 { 2482 union ich8_hws_flash_status hsfsts; 2483 s32 ret_val = -E1000_ERR_NVM; 2484 2485 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2486 2487 /* Check if the flash descriptor is valid */ 2488 if (!hsfsts.hsf_status.fldesvalid) { 2489 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 2490 return -E1000_ERR_NVM; 2491 } 2492 2493 /* Clear FCERR and DAEL in hw status by writing 1 */ 2494 hsfsts.hsf_status.flcerr = 1; 2495 hsfsts.hsf_status.dael = 1; 2496 2497 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2498 2499 /* Either we should have a hardware SPI cycle in progress 2500 * bit to check against, in order to start a new cycle or 2501 * FDONE bit should be changed in the hardware so that it 2502 * is 1 after hardware reset, which can then be used as an 2503 * indication whether a cycle is in progress or has been 2504 * completed. 2505 */ 2506 2507 if (!hsfsts.hsf_status.flcinprog) { 2508 /* There is no cycle running at present, 2509 * so we can start a cycle. 2510 * Begin by setting Flash Cycle Done. 2511 */ 2512 hsfsts.hsf_status.flcdone = 1; 2513 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2514 ret_val = 0; 2515 } else { 2516 s32 i; 2517 2518 /* Otherwise poll for sometime so the current 2519 * cycle has a chance to end before giving up. 2520 */ 2521 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2522 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2523 if (!hsfsts.hsf_status.flcinprog) { 2524 ret_val = 0; 2525 break; 2526 } 2527 udelay(1); 2528 } 2529 if (!ret_val) { 2530 /* Successful in waiting for previous cycle to timeout, 2531 * now set the Flash Cycle Done. 2532 */ 2533 hsfsts.hsf_status.flcdone = 1; 2534 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2535 } else { 2536 e_dbg("Flash controller busy, cannot get access\n"); 2537 } 2538 } 2539 2540 return ret_val; 2541 } 2542 2543 /** 2544 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 2545 * @hw: pointer to the HW structure 2546 * @timeout: maximum time to wait for completion 2547 * 2548 * This function starts a flash cycle and waits for its completion. 2549 **/ 2550 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 2551 { 2552 union ich8_hws_flash_ctrl hsflctl; 2553 union ich8_hws_flash_status hsfsts; 2554 u32 i = 0; 2555 2556 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 2557 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2558 hsflctl.hsf_ctrl.flcgo = 1; 2559 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2560 2561 /* wait till FDONE bit is set to 1 */ 2562 do { 2563 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2564 if (hsfsts.hsf_status.flcdone) 2565 break; 2566 udelay(1); 2567 } while (i++ < timeout); 2568 2569 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 2570 return 0; 2571 2572 return -E1000_ERR_NVM; 2573 } 2574 2575 /** 2576 * e1000_read_flash_word_ich8lan - Read word from flash 2577 * @hw: pointer to the HW structure 2578 * @offset: offset to data location 2579 * @data: pointer to the location for storing the data 2580 * 2581 * Reads the flash word at offset into data. Offset is converted 2582 * to bytes before read. 2583 **/ 2584 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 2585 u16 *data) 2586 { 2587 /* Must convert offset into bytes. */ 2588 offset <<= 1; 2589 2590 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 2591 } 2592 2593 /** 2594 * e1000_read_flash_byte_ich8lan - Read byte from flash 2595 * @hw: pointer to the HW structure 2596 * @offset: The offset of the byte to read. 2597 * @data: Pointer to a byte to store the value read. 2598 * 2599 * Reads a single byte from the NVM using the flash access registers. 2600 **/ 2601 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 2602 u8 *data) 2603 { 2604 s32 ret_val; 2605 u16 word = 0; 2606 2607 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 2608 if (ret_val) 2609 return ret_val; 2610 2611 *data = (u8)word; 2612 2613 return 0; 2614 } 2615 2616 /** 2617 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 2618 * @hw: pointer to the HW structure 2619 * @offset: The offset (in bytes) of the byte or word to read. 2620 * @size: Size of data to read, 1=byte 2=word 2621 * @data: Pointer to the word to store the value read. 2622 * 2623 * Reads a byte or word from the NVM using the flash access registers. 2624 **/ 2625 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2626 u8 size, u16 *data) 2627 { 2628 union ich8_hws_flash_status hsfsts; 2629 union ich8_hws_flash_ctrl hsflctl; 2630 u32 flash_linear_addr; 2631 u32 flash_data = 0; 2632 s32 ret_val = -E1000_ERR_NVM; 2633 u8 count = 0; 2634 2635 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 2636 return -E1000_ERR_NVM; 2637 2638 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2639 hw->nvm.flash_base_addr; 2640 2641 do { 2642 udelay(1); 2643 /* Steps */ 2644 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2645 if (ret_val) 2646 break; 2647 2648 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 2649 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 2650 hsflctl.hsf_ctrl.fldbcount = size - 1; 2651 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 2652 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 2653 2654 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 2655 2656 ret_val = e1000_flash_cycle_ich8lan(hw, 2657 ICH_FLASH_READ_COMMAND_TIMEOUT); 2658 2659 /* Check if FCERR is set to 1, if set to 1, clear it 2660 * and try the whole sequence a few more times, else 2661 * read in (shift in) the Flash Data0, the order is 2662 * least significant byte first msb to lsb 2663 */ 2664 if (!ret_val) { 2665 flash_data = er32flash(ICH_FLASH_FDATA0); 2666 if (size == 1) 2667 *data = (u8)(flash_data & 0x000000FF); 2668 else if (size == 2) 2669 *data = (u16)(flash_data & 0x0000FFFF); 2670 break; 2671 } else { 2672 /* If we've gotten here, then things are probably 2673 * completely hosed, but if the error condition is 2674 * detected, it won't hurt to give it another try... 2675 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2676 */ 2677 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2678 if (hsfsts.hsf_status.flcerr) { 2679 /* Repeat for some time before giving up. */ 2680 continue; 2681 } else if (!hsfsts.hsf_status.flcdone) { 2682 e_dbg("Timeout error - flash cycle did not complete.\n"); 2683 break; 2684 } 2685 } 2686 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 2687 2688 return ret_val; 2689 } 2690 2691 /** 2692 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 2693 * @hw: pointer to the HW structure 2694 * @offset: The offset (in bytes) of the word(s) to write. 2695 * @words: Size of data to write in words 2696 * @data: Pointer to the word(s) to write at offset. 2697 * 2698 * Writes a byte or word to the NVM using the flash access registers. 2699 **/ 2700 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 2701 u16 *data) 2702 { 2703 struct e1000_nvm_info *nvm = &hw->nvm; 2704 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2705 u16 i; 2706 2707 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 2708 (words == 0)) { 2709 e_dbg("nvm parameter(s) out of bounds\n"); 2710 return -E1000_ERR_NVM; 2711 } 2712 2713 nvm->ops.acquire(hw); 2714 2715 for (i = 0; i < words; i++) { 2716 dev_spec->shadow_ram[offset+i].modified = true; 2717 dev_spec->shadow_ram[offset+i].value = data[i]; 2718 } 2719 2720 nvm->ops.release(hw); 2721 2722 return 0; 2723 } 2724 2725 /** 2726 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 2727 * @hw: pointer to the HW structure 2728 * 2729 * The NVM checksum is updated by calling the generic update_nvm_checksum, 2730 * which writes the checksum to the shadow ram. The changes in the shadow 2731 * ram are then committed to the EEPROM by processing each bank at a time 2732 * checking for the modified bit and writing only the pending changes. 2733 * After a successful commit, the shadow ram is cleared and is ready for 2734 * future writes. 2735 **/ 2736 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 2737 { 2738 struct e1000_nvm_info *nvm = &hw->nvm; 2739 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 2740 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 2741 s32 ret_val; 2742 u16 data; 2743 2744 ret_val = e1000e_update_nvm_checksum_generic(hw); 2745 if (ret_val) 2746 goto out; 2747 2748 if (nvm->type != e1000_nvm_flash_sw) 2749 goto out; 2750 2751 nvm->ops.acquire(hw); 2752 2753 /* We're writing to the opposite bank so if we're on bank 1, 2754 * write to bank 0 etc. We also need to erase the segment that 2755 * is going to be written 2756 */ 2757 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 2758 if (ret_val) { 2759 e_dbg("Could not detect valid bank, assuming bank 0\n"); 2760 bank = 0; 2761 } 2762 2763 if (bank == 0) { 2764 new_bank_offset = nvm->flash_bank_size; 2765 old_bank_offset = 0; 2766 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2767 if (ret_val) 2768 goto release; 2769 } else { 2770 old_bank_offset = nvm->flash_bank_size; 2771 new_bank_offset = 0; 2772 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2773 if (ret_val) 2774 goto release; 2775 } 2776 2777 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2778 /* Determine whether to write the value stored 2779 * in the other NVM bank or a modified value stored 2780 * in the shadow RAM 2781 */ 2782 if (dev_spec->shadow_ram[i].modified) { 2783 data = dev_spec->shadow_ram[i].value; 2784 } else { 2785 ret_val = e1000_read_flash_word_ich8lan(hw, i + 2786 old_bank_offset, 2787 &data); 2788 if (ret_val) 2789 break; 2790 } 2791 2792 /* If the word is 0x13, then make sure the signature bits 2793 * (15:14) are 11b until the commit has completed. 2794 * This will allow us to write 10b which indicates the 2795 * signature is valid. We want to do this after the write 2796 * has completed so that we don't mark the segment valid 2797 * while the write is still in progress 2798 */ 2799 if (i == E1000_ICH_NVM_SIG_WORD) 2800 data |= E1000_ICH_NVM_SIG_MASK; 2801 2802 /* Convert offset to bytes. */ 2803 act_offset = (i + new_bank_offset) << 1; 2804 2805 udelay(100); 2806 /* Write the bytes to the new bank. */ 2807 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2808 act_offset, 2809 (u8)data); 2810 if (ret_val) 2811 break; 2812 2813 udelay(100); 2814 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2815 act_offset + 1, 2816 (u8)(data >> 8)); 2817 if (ret_val) 2818 break; 2819 } 2820 2821 /* Don't bother writing the segment valid bits if sector 2822 * programming failed. 2823 */ 2824 if (ret_val) { 2825 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 2826 e_dbg("Flash commit failed.\n"); 2827 goto release; 2828 } 2829 2830 /* Finally validate the new segment by setting bit 15:14 2831 * to 10b in word 0x13 , this can be done without an 2832 * erase as well since these bits are 11 to start with 2833 * and we need to change bit 14 to 0b 2834 */ 2835 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2836 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2837 if (ret_val) 2838 goto release; 2839 2840 data &= 0xBFFF; 2841 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 2842 act_offset * 2 + 1, 2843 (u8)(data >> 8)); 2844 if (ret_val) 2845 goto release; 2846 2847 /* And invalidate the previously valid segment by setting 2848 * its signature word (0x13) high_byte to 0b. This can be 2849 * done without an erase because flash erase sets all bits 2850 * to 1's. We can write 1's to 0's without an erase 2851 */ 2852 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2853 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2854 if (ret_val) 2855 goto release; 2856 2857 /* Great! Everything worked, we can now clear the cached entries. */ 2858 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2859 dev_spec->shadow_ram[i].modified = false; 2860 dev_spec->shadow_ram[i].value = 0xFFFF; 2861 } 2862 2863 release: 2864 nvm->ops.release(hw); 2865 2866 /* Reload the EEPROM, or else modifications will not appear 2867 * until after the next adapter reset. 2868 */ 2869 if (!ret_val) { 2870 nvm->ops.reload(hw); 2871 usleep_range(10000, 20000); 2872 } 2873 2874 out: 2875 if (ret_val) 2876 e_dbg("NVM update error: %d\n", ret_val); 2877 2878 return ret_val; 2879 } 2880 2881 /** 2882 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 2883 * @hw: pointer to the HW structure 2884 * 2885 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 2886 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 2887 * calculated, in which case we need to calculate the checksum and set bit 6. 2888 **/ 2889 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 2890 { 2891 s32 ret_val; 2892 u16 data; 2893 u16 word; 2894 u16 valid_csum_mask; 2895 2896 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 2897 * the checksum needs to be fixed. This bit is an indication that 2898 * the NVM was prepared by OEM software and did not calculate 2899 * the checksum...a likely scenario. 2900 */ 2901 switch (hw->mac.type) { 2902 case e1000_pch_lpt: 2903 word = NVM_COMPAT; 2904 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 2905 break; 2906 default: 2907 word = NVM_FUTURE_INIT_WORD1; 2908 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 2909 break; 2910 } 2911 2912 ret_val = e1000_read_nvm(hw, word, 1, &data); 2913 if (ret_val) 2914 return ret_val; 2915 2916 if (!(data & valid_csum_mask)) { 2917 data |= valid_csum_mask; 2918 ret_val = e1000_write_nvm(hw, word, 1, &data); 2919 if (ret_val) 2920 return ret_val; 2921 ret_val = e1000e_update_nvm_checksum(hw); 2922 if (ret_val) 2923 return ret_val; 2924 } 2925 2926 return e1000e_validate_nvm_checksum_generic(hw); 2927 } 2928 2929 /** 2930 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 2931 * @hw: pointer to the HW structure 2932 * 2933 * To prevent malicious write/erase of the NVM, set it to be read-only 2934 * so that the hardware ignores all write/erase cycles of the NVM via 2935 * the flash control registers. The shadow-ram copy of the NVM will 2936 * still be updated, however any updates to this copy will not stick 2937 * across driver reloads. 2938 **/ 2939 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 2940 { 2941 struct e1000_nvm_info *nvm = &hw->nvm; 2942 union ich8_flash_protected_range pr0; 2943 union ich8_hws_flash_status hsfsts; 2944 u32 gfpreg; 2945 2946 nvm->ops.acquire(hw); 2947 2948 gfpreg = er32flash(ICH_FLASH_GFPREG); 2949 2950 /* Write-protect GbE Sector of NVM */ 2951 pr0.regval = er32flash(ICH_FLASH_PR0); 2952 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 2953 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 2954 pr0.range.wpe = true; 2955 ew32flash(ICH_FLASH_PR0, pr0.regval); 2956 2957 /* Lock down a subset of GbE Flash Control Registers, e.g. 2958 * PR0 to prevent the write-protection from being lifted. 2959 * Once FLOCKDN is set, the registers protected by it cannot 2960 * be written until FLOCKDN is cleared by a hardware reset. 2961 */ 2962 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 2963 hsfsts.hsf_status.flockdn = true; 2964 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2965 2966 nvm->ops.release(hw); 2967 } 2968 2969 /** 2970 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 2971 * @hw: pointer to the HW structure 2972 * @offset: The offset (in bytes) of the byte/word to read. 2973 * @size: Size of data to read, 1=byte 2=word 2974 * @data: The byte(s) to write to the NVM. 2975 * 2976 * Writes one/two bytes to the NVM using the flash access registers. 2977 **/ 2978 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 2979 u8 size, u16 data) 2980 { 2981 union ich8_hws_flash_status hsfsts; 2982 union ich8_hws_flash_ctrl hsflctl; 2983 u32 flash_linear_addr; 2984 u32 flash_data = 0; 2985 s32 ret_val; 2986 u8 count = 0; 2987 2988 if (size < 1 || size > 2 || data > size * 0xff || 2989 offset > ICH_FLASH_LINEAR_ADDR_MASK) 2990 return -E1000_ERR_NVM; 2991 2992 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 2993 hw->nvm.flash_base_addr; 2994 2995 do { 2996 udelay(1); 2997 /* Steps */ 2998 ret_val = e1000_flash_cycle_init_ich8lan(hw); 2999 if (ret_val) 3000 break; 3001 3002 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3003 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3004 hsflctl.hsf_ctrl.fldbcount = size -1; 3005 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 3006 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3007 3008 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3009 3010 if (size == 1) 3011 flash_data = (u32)data & 0x00FF; 3012 else 3013 flash_data = (u32)data; 3014 3015 ew32flash(ICH_FLASH_FDATA0, flash_data); 3016 3017 /* check if FCERR is set to 1 , if set to 1, clear it 3018 * and try the whole sequence a few more times else done 3019 */ 3020 ret_val = e1000_flash_cycle_ich8lan(hw, 3021 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 3022 if (!ret_val) 3023 break; 3024 3025 /* If we're here, then things are most likely 3026 * completely hosed, but if the error condition 3027 * is detected, it won't hurt to give it another 3028 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 3029 */ 3030 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3031 if (hsfsts.hsf_status.flcerr) 3032 /* Repeat for some time before giving up. */ 3033 continue; 3034 if (!hsfsts.hsf_status.flcdone) { 3035 e_dbg("Timeout error - flash cycle did not complete.\n"); 3036 break; 3037 } 3038 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3039 3040 return ret_val; 3041 } 3042 3043 /** 3044 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 3045 * @hw: pointer to the HW structure 3046 * @offset: The index of the byte to read. 3047 * @data: The byte to write to the NVM. 3048 * 3049 * Writes a single byte to the NVM using the flash access registers. 3050 **/ 3051 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3052 u8 data) 3053 { 3054 u16 word = (u16)data; 3055 3056 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 3057 } 3058 3059 /** 3060 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 3061 * @hw: pointer to the HW structure 3062 * @offset: The offset of the byte to write. 3063 * @byte: The byte to write to the NVM. 3064 * 3065 * Writes a single byte to the NVM using the flash access registers. 3066 * Goes through a retry algorithm before giving up. 3067 **/ 3068 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 3069 u32 offset, u8 byte) 3070 { 3071 s32 ret_val; 3072 u16 program_retries; 3073 3074 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3075 if (!ret_val) 3076 return ret_val; 3077 3078 for (program_retries = 0; program_retries < 100; program_retries++) { 3079 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 3080 udelay(100); 3081 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 3082 if (!ret_val) 3083 break; 3084 } 3085 if (program_retries == 100) 3086 return -E1000_ERR_NVM; 3087 3088 return 0; 3089 } 3090 3091 /** 3092 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 3093 * @hw: pointer to the HW structure 3094 * @bank: 0 for first bank, 1 for second bank, etc. 3095 * 3096 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 3097 * bank N is 4096 * N + flash_reg_addr. 3098 **/ 3099 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 3100 { 3101 struct e1000_nvm_info *nvm = &hw->nvm; 3102 union ich8_hws_flash_status hsfsts; 3103 union ich8_hws_flash_ctrl hsflctl; 3104 u32 flash_linear_addr; 3105 /* bank size is in 16bit words - adjust to bytes */ 3106 u32 flash_bank_size = nvm->flash_bank_size * 2; 3107 s32 ret_val; 3108 s32 count = 0; 3109 s32 j, iteration, sector_size; 3110 3111 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3112 3113 /* Determine HW Sector size: Read BERASE bits of hw flash status 3114 * register 3115 * 00: The Hw sector is 256 bytes, hence we need to erase 16 3116 * consecutive sectors. The start index for the nth Hw sector 3117 * can be calculated as = bank * 4096 + n * 256 3118 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 3119 * The start index for the nth Hw sector can be calculated 3120 * as = bank * 4096 3121 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 3122 * (ich9 only, otherwise error condition) 3123 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 3124 */ 3125 switch (hsfsts.hsf_status.berasesz) { 3126 case 0: 3127 /* Hw sector size 256 */ 3128 sector_size = ICH_FLASH_SEG_SIZE_256; 3129 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 3130 break; 3131 case 1: 3132 sector_size = ICH_FLASH_SEG_SIZE_4K; 3133 iteration = 1; 3134 break; 3135 case 2: 3136 sector_size = ICH_FLASH_SEG_SIZE_8K; 3137 iteration = 1; 3138 break; 3139 case 3: 3140 sector_size = ICH_FLASH_SEG_SIZE_64K; 3141 iteration = 1; 3142 break; 3143 default: 3144 return -E1000_ERR_NVM; 3145 } 3146 3147 /* Start with the base address, then add the sector offset. */ 3148 flash_linear_addr = hw->nvm.flash_base_addr; 3149 flash_linear_addr += (bank) ? flash_bank_size : 0; 3150 3151 for (j = 0; j < iteration ; j++) { 3152 do { 3153 /* Steps */ 3154 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3155 if (ret_val) 3156 return ret_val; 3157 3158 /* Write a value 11 (block Erase) in Flash 3159 * Cycle field in hw flash control 3160 */ 3161 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3162 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3163 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3164 3165 /* Write the last 24 bits of an index within the 3166 * block into Flash Linear address field in Flash 3167 * Address. 3168 */ 3169 flash_linear_addr += (j * sector_size); 3170 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3171 3172 ret_val = e1000_flash_cycle_ich8lan(hw, 3173 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 3174 if (!ret_val) 3175 break; 3176 3177 /* Check if FCERR is set to 1. If 1, 3178 * clear it and try the whole sequence 3179 * a few more times else Done 3180 */ 3181 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3182 if (hsfsts.hsf_status.flcerr) 3183 /* repeat for some time before giving up */ 3184 continue; 3185 else if (!hsfsts.hsf_status.flcdone) 3186 return ret_val; 3187 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 3188 } 3189 3190 return 0; 3191 } 3192 3193 /** 3194 * e1000_valid_led_default_ich8lan - Set the default LED settings 3195 * @hw: pointer to the HW structure 3196 * @data: Pointer to the LED settings 3197 * 3198 * Reads the LED default settings from the NVM to data. If the NVM LED 3199 * settings is all 0's or F's, set the LED default to a valid LED default 3200 * setting. 3201 **/ 3202 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 3203 { 3204 s32 ret_val; 3205 3206 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 3207 if (ret_val) { 3208 e_dbg("NVM Read Error\n"); 3209 return ret_val; 3210 } 3211 3212 if (*data == ID_LED_RESERVED_0000 || 3213 *data == ID_LED_RESERVED_FFFF) 3214 *data = ID_LED_DEFAULT_ICH8LAN; 3215 3216 return 0; 3217 } 3218 3219 /** 3220 * e1000_id_led_init_pchlan - store LED configurations 3221 * @hw: pointer to the HW structure 3222 * 3223 * PCH does not control LEDs via the LEDCTL register, rather it uses 3224 * the PHY LED configuration register. 3225 * 3226 * PCH also does not have an "always on" or "always off" mode which 3227 * complicates the ID feature. Instead of using the "on" mode to indicate 3228 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 3229 * use "link_up" mode. The LEDs will still ID on request if there is no 3230 * link based on logic in e1000_led_[on|off]_pchlan(). 3231 **/ 3232 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 3233 { 3234 struct e1000_mac_info *mac = &hw->mac; 3235 s32 ret_val; 3236 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 3237 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 3238 u16 data, i, temp, shift; 3239 3240 /* Get default ID LED modes */ 3241 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 3242 if (ret_val) 3243 return ret_val; 3244 3245 mac->ledctl_default = er32(LEDCTL); 3246 mac->ledctl_mode1 = mac->ledctl_default; 3247 mac->ledctl_mode2 = mac->ledctl_default; 3248 3249 for (i = 0; i < 4; i++) { 3250 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 3251 shift = (i * 5); 3252 switch (temp) { 3253 case ID_LED_ON1_DEF2: 3254 case ID_LED_ON1_ON2: 3255 case ID_LED_ON1_OFF2: 3256 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3257 mac->ledctl_mode1 |= (ledctl_on << shift); 3258 break; 3259 case ID_LED_OFF1_DEF2: 3260 case ID_LED_OFF1_ON2: 3261 case ID_LED_OFF1_OFF2: 3262 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 3263 mac->ledctl_mode1 |= (ledctl_off << shift); 3264 break; 3265 default: 3266 /* Do nothing */ 3267 break; 3268 } 3269 switch (temp) { 3270 case ID_LED_DEF1_ON2: 3271 case ID_LED_ON1_ON2: 3272 case ID_LED_OFF1_ON2: 3273 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3274 mac->ledctl_mode2 |= (ledctl_on << shift); 3275 break; 3276 case ID_LED_DEF1_OFF2: 3277 case ID_LED_ON1_OFF2: 3278 case ID_LED_OFF1_OFF2: 3279 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 3280 mac->ledctl_mode2 |= (ledctl_off << shift); 3281 break; 3282 default: 3283 /* Do nothing */ 3284 break; 3285 } 3286 } 3287 3288 return 0; 3289 } 3290 3291 /** 3292 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 3293 * @hw: pointer to the HW structure 3294 * 3295 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 3296 * register, so the the bus width is hard coded. 3297 **/ 3298 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 3299 { 3300 struct e1000_bus_info *bus = &hw->bus; 3301 s32 ret_val; 3302 3303 ret_val = e1000e_get_bus_info_pcie(hw); 3304 3305 /* ICH devices are "PCI Express"-ish. They have 3306 * a configuration space, but do not contain 3307 * PCI Express Capability registers, so bus width 3308 * must be hardcoded. 3309 */ 3310 if (bus->width == e1000_bus_width_unknown) 3311 bus->width = e1000_bus_width_pcie_x1; 3312 3313 return ret_val; 3314 } 3315 3316 /** 3317 * e1000_reset_hw_ich8lan - Reset the hardware 3318 * @hw: pointer to the HW structure 3319 * 3320 * Does a full reset of the hardware which includes a reset of the PHY and 3321 * MAC. 3322 **/ 3323 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 3324 { 3325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3326 u16 kum_cfg; 3327 u32 ctrl, reg; 3328 s32 ret_val; 3329 3330 /* Prevent the PCI-E bus from sticking if there is no TLP connection 3331 * on the last TLP read/write transaction when MAC is reset. 3332 */ 3333 ret_val = e1000e_disable_pcie_master(hw); 3334 if (ret_val) 3335 e_dbg("PCI-E Master disable polling has failed.\n"); 3336 3337 e_dbg("Masking off all interrupts\n"); 3338 ew32(IMC, 0xffffffff); 3339 3340 /* Disable the Transmit and Receive units. Then delay to allow 3341 * any pending transactions to complete before we hit the MAC 3342 * with the global reset. 3343 */ 3344 ew32(RCTL, 0); 3345 ew32(TCTL, E1000_TCTL_PSP); 3346 e1e_flush(); 3347 3348 usleep_range(10000, 20000); 3349 3350 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 3351 if (hw->mac.type == e1000_ich8lan) { 3352 /* Set Tx and Rx buffer allocation to 8k apiece. */ 3353 ew32(PBA, E1000_PBA_8K); 3354 /* Set Packet Buffer Size to 16k. */ 3355 ew32(PBS, E1000_PBS_16K); 3356 } 3357 3358 if (hw->mac.type == e1000_pchlan) { 3359 /* Save the NVM K1 bit setting */ 3360 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 3361 if (ret_val) 3362 return ret_val; 3363 3364 if (kum_cfg & E1000_NVM_K1_ENABLE) 3365 dev_spec->nvm_k1_enabled = true; 3366 else 3367 dev_spec->nvm_k1_enabled = false; 3368 } 3369 3370 ctrl = er32(CTRL); 3371 3372 if (!hw->phy.ops.check_reset_block(hw)) { 3373 /* Full-chip reset requires MAC and PHY reset at the same 3374 * time to make sure the interface between MAC and the 3375 * external PHY is reset. 3376 */ 3377 ctrl |= E1000_CTRL_PHY_RST; 3378 3379 /* Gate automatic PHY configuration by hardware on 3380 * non-managed 82579 3381 */ 3382 if ((hw->mac.type == e1000_pch2lan) && 3383 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3384 e1000_gate_hw_phy_config_ich8lan(hw, true); 3385 } 3386 ret_val = e1000_acquire_swflag_ich8lan(hw); 3387 e_dbg("Issuing a global reset to ich8lan\n"); 3388 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 3389 /* cannot issue a flush here because it hangs the hardware */ 3390 msleep(20); 3391 3392 /* Set Phy Config Counter to 50msec */ 3393 if (hw->mac.type == e1000_pch2lan) { 3394 reg = er32(FEXTNVM3); 3395 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 3396 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 3397 ew32(FEXTNVM3, reg); 3398 } 3399 3400 if (!ret_val) 3401 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 3402 3403 if (ctrl & E1000_CTRL_PHY_RST) { 3404 ret_val = hw->phy.ops.get_cfg_done(hw); 3405 if (ret_val) 3406 return ret_val; 3407 3408 ret_val = e1000_post_phy_reset_ich8lan(hw); 3409 if (ret_val) 3410 return ret_val; 3411 } 3412 3413 /* For PCH, this write will make sure that any noise 3414 * will be detected as a CRC error and be dropped rather than show up 3415 * as a bad packet to the DMA engine. 3416 */ 3417 if (hw->mac.type == e1000_pchlan) 3418 ew32(CRC_OFFSET, 0x65656565); 3419 3420 ew32(IMC, 0xffffffff); 3421 er32(ICR); 3422 3423 reg = er32(KABGTXD); 3424 reg |= E1000_KABGTXD_BGSQLBIAS; 3425 ew32(KABGTXD, reg); 3426 3427 return 0; 3428 } 3429 3430 /** 3431 * e1000_init_hw_ich8lan - Initialize the hardware 3432 * @hw: pointer to the HW structure 3433 * 3434 * Prepares the hardware for transmit and receive by doing the following: 3435 * - initialize hardware bits 3436 * - initialize LED identification 3437 * - setup receive address registers 3438 * - setup flow control 3439 * - setup transmit descriptors 3440 * - clear statistics 3441 **/ 3442 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 3443 { 3444 struct e1000_mac_info *mac = &hw->mac; 3445 u32 ctrl_ext, txdctl, snoop; 3446 s32 ret_val; 3447 u16 i; 3448 3449 e1000_initialize_hw_bits_ich8lan(hw); 3450 3451 /* Initialize identification LED */ 3452 ret_val = mac->ops.id_led_init(hw); 3453 if (ret_val) 3454 e_dbg("Error initializing identification LED\n"); 3455 /* This is not fatal and we should not stop init due to this */ 3456 3457 /* Setup the receive address. */ 3458 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 3459 3460 /* Zero out the Multicast HASH table */ 3461 e_dbg("Zeroing the MTA\n"); 3462 for (i = 0; i < mac->mta_reg_count; i++) 3463 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3464 3465 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 3466 * the ME. Disable wakeup by clearing the host wakeup bit. 3467 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3468 */ 3469 if (hw->phy.type == e1000_phy_82578) { 3470 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 3471 i &= ~BM_WUC_HOST_WU_BIT; 3472 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 3473 ret_val = e1000_phy_hw_reset_ich8lan(hw); 3474 if (ret_val) 3475 return ret_val; 3476 } 3477 3478 /* Setup link and flow control */ 3479 ret_val = mac->ops.setup_link(hw); 3480 3481 /* Set the transmit descriptor write-back policy for both queues */ 3482 txdctl = er32(TXDCTL(0)); 3483 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3484 E1000_TXDCTL_FULL_TX_DESC_WB; 3485 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3486 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3487 ew32(TXDCTL(0), txdctl); 3488 txdctl = er32(TXDCTL(1)); 3489 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 3490 E1000_TXDCTL_FULL_TX_DESC_WB; 3491 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 3492 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3493 ew32(TXDCTL(1), txdctl); 3494 3495 /* ICH8 has opposite polarity of no_snoop bits. 3496 * By default, we should use snoop behavior. 3497 */ 3498 if (mac->type == e1000_ich8lan) 3499 snoop = PCIE_ICH8_SNOOP_ALL; 3500 else 3501 snoop = (u32) ~(PCIE_NO_SNOOP_ALL); 3502 e1000e_set_pcie_no_snoop(hw, snoop); 3503 3504 ctrl_ext = er32(CTRL_EXT); 3505 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3506 ew32(CTRL_EXT, ctrl_ext); 3507 3508 /* Clear all of the statistics registers (clear on read). It is 3509 * important that we do this after we have tried to establish link 3510 * because the symbol error count will increment wildly if there 3511 * is no link. 3512 */ 3513 e1000_clear_hw_cntrs_ich8lan(hw); 3514 3515 return ret_val; 3516 } 3517 /** 3518 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 3519 * @hw: pointer to the HW structure 3520 * 3521 * Sets/Clears required hardware bits necessary for correctly setting up the 3522 * hardware for transmit and receive. 3523 **/ 3524 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 3525 { 3526 u32 reg; 3527 3528 /* Extended Device Control */ 3529 reg = er32(CTRL_EXT); 3530 reg |= (1 << 22); 3531 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 3532 if (hw->mac.type >= e1000_pchlan) 3533 reg |= E1000_CTRL_EXT_PHYPDEN; 3534 ew32(CTRL_EXT, reg); 3535 3536 /* Transmit Descriptor Control 0 */ 3537 reg = er32(TXDCTL(0)); 3538 reg |= (1 << 22); 3539 ew32(TXDCTL(0), reg); 3540 3541 /* Transmit Descriptor Control 1 */ 3542 reg = er32(TXDCTL(1)); 3543 reg |= (1 << 22); 3544 ew32(TXDCTL(1), reg); 3545 3546 /* Transmit Arbitration Control 0 */ 3547 reg = er32(TARC(0)); 3548 if (hw->mac.type == e1000_ich8lan) 3549 reg |= (1 << 28) | (1 << 29); 3550 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 3551 ew32(TARC(0), reg); 3552 3553 /* Transmit Arbitration Control 1 */ 3554 reg = er32(TARC(1)); 3555 if (er32(TCTL) & E1000_TCTL_MULR) 3556 reg &= ~(1 << 28); 3557 else 3558 reg |= (1 << 28); 3559 reg |= (1 << 24) | (1 << 26) | (1 << 30); 3560 ew32(TARC(1), reg); 3561 3562 /* Device Status */ 3563 if (hw->mac.type == e1000_ich8lan) { 3564 reg = er32(STATUS); 3565 reg &= ~(1 << 31); 3566 ew32(STATUS, reg); 3567 } 3568 3569 /* work-around descriptor data corruption issue during nfs v2 udp 3570 * traffic, just disable the nfs filtering capability 3571 */ 3572 reg = er32(RFCTL); 3573 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3574 3575 /* Disable IPv6 extension header parsing because some malformed 3576 * IPv6 headers can hang the Rx. 3577 */ 3578 if (hw->mac.type == e1000_ich8lan) 3579 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 3580 ew32(RFCTL, reg); 3581 3582 /* Enable ECC on Lynxpoint */ 3583 if (hw->mac.type == e1000_pch_lpt) { 3584 reg = er32(PBECCSTS); 3585 reg |= E1000_PBECCSTS_ECC_ENABLE; 3586 ew32(PBECCSTS, reg); 3587 3588 reg = er32(CTRL); 3589 reg |= E1000_CTRL_MEHE; 3590 ew32(CTRL, reg); 3591 } 3592 } 3593 3594 /** 3595 * e1000_setup_link_ich8lan - Setup flow control and link settings 3596 * @hw: pointer to the HW structure 3597 * 3598 * Determines which flow control settings to use, then configures flow 3599 * control. Calls the appropriate media-specific link configuration 3600 * function. Assuming the adapter has a valid link partner, a valid link 3601 * should be established. Assumes the hardware has previously been reset 3602 * and the transmitter and receiver are not enabled. 3603 **/ 3604 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 3605 { 3606 s32 ret_val; 3607 3608 if (hw->phy.ops.check_reset_block(hw)) 3609 return 0; 3610 3611 /* ICH parts do not have a word in the NVM to determine 3612 * the default flow control setting, so we explicitly 3613 * set it to full. 3614 */ 3615 if (hw->fc.requested_mode == e1000_fc_default) { 3616 /* Workaround h/w hang when Tx flow control enabled */ 3617 if (hw->mac.type == e1000_pchlan) 3618 hw->fc.requested_mode = e1000_fc_rx_pause; 3619 else 3620 hw->fc.requested_mode = e1000_fc_full; 3621 } 3622 3623 /* Save off the requested flow control mode for use later. Depending 3624 * on the link partner's capabilities, we may or may not use this mode. 3625 */ 3626 hw->fc.current_mode = hw->fc.requested_mode; 3627 3628 e_dbg("After fix-ups FlowControl is now = %x\n", 3629 hw->fc.current_mode); 3630 3631 /* Continue to configure the copper link. */ 3632 ret_val = hw->mac.ops.setup_physical_interface(hw); 3633 if (ret_val) 3634 return ret_val; 3635 3636 ew32(FCTTV, hw->fc.pause_time); 3637 if ((hw->phy.type == e1000_phy_82578) || 3638 (hw->phy.type == e1000_phy_82579) || 3639 (hw->phy.type == e1000_phy_i217) || 3640 (hw->phy.type == e1000_phy_82577)) { 3641 ew32(FCRTV_PCH, hw->fc.refresh_time); 3642 3643 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 3644 hw->fc.pause_time); 3645 if (ret_val) 3646 return ret_val; 3647 } 3648 3649 return e1000e_set_fc_watermarks(hw); 3650 } 3651 3652 /** 3653 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 3654 * @hw: pointer to the HW structure 3655 * 3656 * Configures the kumeran interface to the PHY to wait the appropriate time 3657 * when polling the PHY, then call the generic setup_copper_link to finish 3658 * configuring the copper link. 3659 **/ 3660 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 3661 { 3662 u32 ctrl; 3663 s32 ret_val; 3664 u16 reg_data; 3665 3666 ctrl = er32(CTRL); 3667 ctrl |= E1000_CTRL_SLU; 3668 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3669 ew32(CTRL, ctrl); 3670 3671 /* Set the mac to wait the maximum time between each iteration 3672 * and increase the max iterations when polling the phy; 3673 * this fixes erroneous timeouts at 10Mbps. 3674 */ 3675 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 3676 if (ret_val) 3677 return ret_val; 3678 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3679 ®_data); 3680 if (ret_val) 3681 return ret_val; 3682 reg_data |= 0x3F; 3683 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 3684 reg_data); 3685 if (ret_val) 3686 return ret_val; 3687 3688 switch (hw->phy.type) { 3689 case e1000_phy_igp_3: 3690 ret_val = e1000e_copper_link_setup_igp(hw); 3691 if (ret_val) 3692 return ret_val; 3693 break; 3694 case e1000_phy_bm: 3695 case e1000_phy_82578: 3696 ret_val = e1000e_copper_link_setup_m88(hw); 3697 if (ret_val) 3698 return ret_val; 3699 break; 3700 case e1000_phy_82577: 3701 case e1000_phy_82579: 3702 case e1000_phy_i217: 3703 ret_val = e1000_copper_link_setup_82577(hw); 3704 if (ret_val) 3705 return ret_val; 3706 break; 3707 case e1000_phy_ife: 3708 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 3709 if (ret_val) 3710 return ret_val; 3711 3712 reg_data &= ~IFE_PMC_AUTO_MDIX; 3713 3714 switch (hw->phy.mdix) { 3715 case 1: 3716 reg_data &= ~IFE_PMC_FORCE_MDIX; 3717 break; 3718 case 2: 3719 reg_data |= IFE_PMC_FORCE_MDIX; 3720 break; 3721 case 0: 3722 default: 3723 reg_data |= IFE_PMC_AUTO_MDIX; 3724 break; 3725 } 3726 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 3727 if (ret_val) 3728 return ret_val; 3729 break; 3730 default: 3731 break; 3732 } 3733 3734 return e1000e_setup_copper_link(hw); 3735 } 3736 3737 /** 3738 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 3739 * @hw: pointer to the HW structure 3740 * @speed: pointer to store current link speed 3741 * @duplex: pointer to store the current link duplex 3742 * 3743 * Calls the generic get_speed_and_duplex to retrieve the current link 3744 * information and then calls the Kumeran lock loss workaround for links at 3745 * gigabit speeds. 3746 **/ 3747 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 3748 u16 *duplex) 3749 { 3750 s32 ret_val; 3751 3752 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 3753 if (ret_val) 3754 return ret_val; 3755 3756 if ((hw->mac.type == e1000_ich8lan) && 3757 (hw->phy.type == e1000_phy_igp_3) && 3758 (*speed == SPEED_1000)) { 3759 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 3760 } 3761 3762 return ret_val; 3763 } 3764 3765 /** 3766 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 3767 * @hw: pointer to the HW structure 3768 * 3769 * Work-around for 82566 Kumeran PCS lock loss: 3770 * On link status change (i.e. PCI reset, speed change) and link is up and 3771 * speed is gigabit- 3772 * 0) if workaround is optionally disabled do nothing 3773 * 1) wait 1ms for Kumeran link to come up 3774 * 2) check Kumeran Diagnostic register PCS lock loss bit 3775 * 3) if not set the link is locked (all is good), otherwise... 3776 * 4) reset the PHY 3777 * 5) repeat up to 10 times 3778 * Note: this is only called for IGP3 copper when speed is 1gb. 3779 **/ 3780 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 3781 { 3782 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3783 u32 phy_ctrl; 3784 s32 ret_val; 3785 u16 i, data; 3786 bool link; 3787 3788 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 3789 return 0; 3790 3791 /* Make sure link is up before proceeding. If not just return. 3792 * Attempting this while link is negotiating fouled up link 3793 * stability 3794 */ 3795 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 3796 if (!link) 3797 return 0; 3798 3799 for (i = 0; i < 10; i++) { 3800 /* read once to clear */ 3801 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 3802 if (ret_val) 3803 return ret_val; 3804 /* and again to get new status */ 3805 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 3806 if (ret_val) 3807 return ret_val; 3808 3809 /* check for PCS lock */ 3810 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 3811 return 0; 3812 3813 /* Issue PHY reset */ 3814 e1000_phy_hw_reset(hw); 3815 mdelay(5); 3816 } 3817 /* Disable GigE link negotiation */ 3818 phy_ctrl = er32(PHY_CTRL); 3819 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 3820 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3821 ew32(PHY_CTRL, phy_ctrl); 3822 3823 /* Call gig speed drop workaround on Gig disable before accessing 3824 * any PHY registers 3825 */ 3826 e1000e_gig_downshift_workaround_ich8lan(hw); 3827 3828 /* unable to acquire PCS lock */ 3829 return -E1000_ERR_PHY; 3830 } 3831 3832 /** 3833 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 3834 * @hw: pointer to the HW structure 3835 * @state: boolean value used to set the current Kumeran workaround state 3836 * 3837 * If ICH8, set the current Kumeran workaround state (enabled - true 3838 * /disabled - false). 3839 **/ 3840 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 3841 bool state) 3842 { 3843 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3844 3845 if (hw->mac.type != e1000_ich8lan) { 3846 e_dbg("Workaround applies to ICH8 only.\n"); 3847 return; 3848 } 3849 3850 dev_spec->kmrn_lock_loss_workaround_enabled = state; 3851 } 3852 3853 /** 3854 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 3855 * @hw: pointer to the HW structure 3856 * 3857 * Workaround for 82566 power-down on D3 entry: 3858 * 1) disable gigabit link 3859 * 2) write VR power-down enable 3860 * 3) read it back 3861 * Continue if successful, else issue LCD reset and repeat 3862 **/ 3863 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 3864 { 3865 u32 reg; 3866 u16 data; 3867 u8 retry = 0; 3868 3869 if (hw->phy.type != e1000_phy_igp_3) 3870 return; 3871 3872 /* Try the workaround twice (if needed) */ 3873 do { 3874 /* Disable link */ 3875 reg = er32(PHY_CTRL); 3876 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 3877 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3878 ew32(PHY_CTRL, reg); 3879 3880 /* Call gig speed drop workaround on Gig disable before 3881 * accessing any PHY registers 3882 */ 3883 if (hw->mac.type == e1000_ich8lan) 3884 e1000e_gig_downshift_workaround_ich8lan(hw); 3885 3886 /* Write VR power-down enable */ 3887 e1e_rphy(hw, IGP3_VR_CTRL, &data); 3888 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3889 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 3890 3891 /* Read it back and test */ 3892 e1e_rphy(hw, IGP3_VR_CTRL, &data); 3893 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 3894 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 3895 break; 3896 3897 /* Issue PHY reset and repeat at most one more time */ 3898 reg = er32(CTRL); 3899 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 3900 retry++; 3901 } while (retry); 3902 } 3903 3904 /** 3905 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 3906 * @hw: pointer to the HW structure 3907 * 3908 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 3909 * LPLU, Gig disable, MDIC PHY reset): 3910 * 1) Set Kumeran Near-end loopback 3911 * 2) Clear Kumeran Near-end loopback 3912 * Should only be called for ICH8[m] devices with any 1G Phy. 3913 **/ 3914 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 3915 { 3916 s32 ret_val; 3917 u16 reg_data; 3918 3919 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 3920 return; 3921 3922 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3923 ®_data); 3924 if (ret_val) 3925 return; 3926 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 3927 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 3928 reg_data); 3929 if (ret_val) 3930 return; 3931 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 3932 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 3933 } 3934 3935 /** 3936 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 3937 * @hw: pointer to the HW structure 3938 * 3939 * During S0 to Sx transition, it is possible the link remains at gig 3940 * instead of negotiating to a lower speed. Before going to Sx, set 3941 * 'Gig Disable' to force link speed negotiation to a lower speed based on 3942 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 3943 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 3944 * needs to be written. 3945 * Parts that support (and are linked to a partner which support) EEE in 3946 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 3947 * than 10Mbps w/o EEE. 3948 **/ 3949 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 3950 { 3951 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3952 u32 phy_ctrl; 3953 s32 ret_val; 3954 3955 phy_ctrl = er32(PHY_CTRL); 3956 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 3957 if (hw->phy.type == e1000_phy_i217) { 3958 u16 phy_reg; 3959 3960 ret_val = hw->phy.ops.acquire(hw); 3961 if (ret_val) 3962 goto out; 3963 3964 if (!dev_spec->eee_disable) { 3965 u16 eee_advert; 3966 3967 ret_val = 3968 e1000_read_emi_reg_locked(hw, 3969 I217_EEE_ADVERTISEMENT, 3970 &eee_advert); 3971 if (ret_val) 3972 goto release; 3973 3974 /* Disable LPLU if both link partners support 100BaseT 3975 * EEE and 100Full is advertised on both ends of the 3976 * link. 3977 */ 3978 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 3979 (dev_spec->eee_lp_ability & 3980 I82579_EEE_100_SUPPORTED) && 3981 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) 3982 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 3983 E1000_PHY_CTRL_NOND0A_LPLU); 3984 } 3985 3986 /* For i217 Intel Rapid Start Technology support, 3987 * when the system is going into Sx and no manageability engine 3988 * is present, the driver must configure proxy to reset only on 3989 * power good. LPI (Low Power Idle) state must also reset only 3990 * on power good, as well as the MTA (Multicast table array). 3991 * The SMBus release must also be disabled on LCD reset. 3992 */ 3993 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 3994 /* Enable proxy to reset only on power good. */ 3995 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 3996 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 3997 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 3998 3999 /* Set bit enable LPI (EEE) to reset only on 4000 * power good. 4001 */ 4002 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 4003 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 4004 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 4005 4006 /* Disable the SMB release on LCD reset. */ 4007 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 4008 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 4009 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 4010 } 4011 4012 /* Enable MTA to reset for Intel Rapid Start Technology 4013 * Support 4014 */ 4015 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 4016 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 4017 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 4018 4019 release: 4020 hw->phy.ops.release(hw); 4021 } 4022 out: 4023 ew32(PHY_CTRL, phy_ctrl); 4024 4025 if (hw->mac.type == e1000_ich8lan) 4026 e1000e_gig_downshift_workaround_ich8lan(hw); 4027 4028 if (hw->mac.type >= e1000_pchlan) { 4029 e1000_oem_bits_config_ich8lan(hw, false); 4030 4031 /* Reset PHY to activate OEM bits on 82577/8 */ 4032 if (hw->mac.type == e1000_pchlan) 4033 e1000e_phy_hw_reset_generic(hw); 4034 4035 ret_val = hw->phy.ops.acquire(hw); 4036 if (ret_val) 4037 return; 4038 e1000_write_smbus_addr(hw); 4039 hw->phy.ops.release(hw); 4040 } 4041 } 4042 4043 /** 4044 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 4045 * @hw: pointer to the HW structure 4046 * 4047 * During Sx to S0 transitions on non-managed devices or managed devices 4048 * on which PHY resets are not blocked, if the PHY registers cannot be 4049 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 4050 * the PHY. 4051 * On i217, setup Intel Rapid Start Technology. 4052 **/ 4053 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 4054 { 4055 s32 ret_val; 4056 4057 if (hw->mac.type < e1000_pch2lan) 4058 return; 4059 4060 ret_val = e1000_init_phy_workarounds_pchlan(hw); 4061 if (ret_val) { 4062 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 4063 return; 4064 } 4065 4066 /* For i217 Intel Rapid Start Technology support when the system 4067 * is transitioning from Sx and no manageability engine is present 4068 * configure SMBus to restore on reset, disable proxy, and enable 4069 * the reset on MTA (Multicast table array). 4070 */ 4071 if (hw->phy.type == e1000_phy_i217) { 4072 u16 phy_reg; 4073 4074 ret_val = hw->phy.ops.acquire(hw); 4075 if (ret_val) { 4076 e_dbg("Failed to setup iRST\n"); 4077 return; 4078 } 4079 4080 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 4081 /* Restore clear on SMB if no manageability engine 4082 * is present 4083 */ 4084 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 4085 if (ret_val) 4086 goto release; 4087 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 4088 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 4089 4090 /* Disable Proxy */ 4091 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 4092 } 4093 /* Enable reset on MTA */ 4094 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 4095 if (ret_val) 4096 goto release; 4097 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 4098 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 4099 release: 4100 if (ret_val) 4101 e_dbg("Error %d in resume workarounds\n", ret_val); 4102 hw->phy.ops.release(hw); 4103 } 4104 } 4105 4106 /** 4107 * e1000_cleanup_led_ich8lan - Restore the default LED operation 4108 * @hw: pointer to the HW structure 4109 * 4110 * Return the LED back to the default configuration. 4111 **/ 4112 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 4113 { 4114 if (hw->phy.type == e1000_phy_ife) 4115 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 4116 4117 ew32(LEDCTL, hw->mac.ledctl_default); 4118 return 0; 4119 } 4120 4121 /** 4122 * e1000_led_on_ich8lan - Turn LEDs on 4123 * @hw: pointer to the HW structure 4124 * 4125 * Turn on the LEDs. 4126 **/ 4127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 4128 { 4129 if (hw->phy.type == e1000_phy_ife) 4130 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4131 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 4132 4133 ew32(LEDCTL, hw->mac.ledctl_mode2); 4134 return 0; 4135 } 4136 4137 /** 4138 * e1000_led_off_ich8lan - Turn LEDs off 4139 * @hw: pointer to the HW structure 4140 * 4141 * Turn off the LEDs. 4142 **/ 4143 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 4144 { 4145 if (hw->phy.type == e1000_phy_ife) 4146 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4147 (IFE_PSCL_PROBE_MODE | 4148 IFE_PSCL_PROBE_LEDS_OFF)); 4149 4150 ew32(LEDCTL, hw->mac.ledctl_mode1); 4151 return 0; 4152 } 4153 4154 /** 4155 * e1000_setup_led_pchlan - Configures SW controllable LED 4156 * @hw: pointer to the HW structure 4157 * 4158 * This prepares the SW controllable LED for use. 4159 **/ 4160 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 4161 { 4162 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 4163 } 4164 4165 /** 4166 * e1000_cleanup_led_pchlan - Restore the default LED operation 4167 * @hw: pointer to the HW structure 4168 * 4169 * Return the LED back to the default configuration. 4170 **/ 4171 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 4172 { 4173 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 4174 } 4175 4176 /** 4177 * e1000_led_on_pchlan - Turn LEDs on 4178 * @hw: pointer to the HW structure 4179 * 4180 * Turn on the LEDs. 4181 **/ 4182 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 4183 { 4184 u16 data = (u16)hw->mac.ledctl_mode2; 4185 u32 i, led; 4186 4187 /* If no link, then turn LED on by setting the invert bit 4188 * for each LED that's mode is "link_up" in ledctl_mode2. 4189 */ 4190 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4191 for (i = 0; i < 3; i++) { 4192 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4193 if ((led & E1000_PHY_LED0_MODE_MASK) != 4194 E1000_LEDCTL_MODE_LINK_UP) 4195 continue; 4196 if (led & E1000_PHY_LED0_IVRT) 4197 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4198 else 4199 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4200 } 4201 } 4202 4203 return e1e_wphy(hw, HV_LED_CONFIG, data); 4204 } 4205 4206 /** 4207 * e1000_led_off_pchlan - Turn LEDs off 4208 * @hw: pointer to the HW structure 4209 * 4210 * Turn off the LEDs. 4211 **/ 4212 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 4213 { 4214 u16 data = (u16)hw->mac.ledctl_mode1; 4215 u32 i, led; 4216 4217 /* If no link, then turn LED off by clearing the invert bit 4218 * for each LED that's mode is "link_up" in ledctl_mode1. 4219 */ 4220 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4221 for (i = 0; i < 3; i++) { 4222 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 4223 if ((led & E1000_PHY_LED0_MODE_MASK) != 4224 E1000_LEDCTL_MODE_LINK_UP) 4225 continue; 4226 if (led & E1000_PHY_LED0_IVRT) 4227 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 4228 else 4229 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 4230 } 4231 } 4232 4233 return e1e_wphy(hw, HV_LED_CONFIG, data); 4234 } 4235 4236 /** 4237 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 4238 * @hw: pointer to the HW structure 4239 * 4240 * Read appropriate register for the config done bit for completion status 4241 * and configure the PHY through s/w for EEPROM-less parts. 4242 * 4243 * NOTE: some silicon which is EEPROM-less will fail trying to read the 4244 * config done bit, so only an error is logged and continues. If we were 4245 * to return with error, EEPROM-less silicon would not be able to be reset 4246 * or change link. 4247 **/ 4248 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 4249 { 4250 s32 ret_val = 0; 4251 u32 bank = 0; 4252 u32 status; 4253 4254 e1000e_get_cfg_done_generic(hw); 4255 4256 /* Wait for indication from h/w that it has completed basic config */ 4257 if (hw->mac.type >= e1000_ich10lan) { 4258 e1000_lan_init_done_ich8lan(hw); 4259 } else { 4260 ret_val = e1000e_get_auto_rd_done(hw); 4261 if (ret_val) { 4262 /* When auto config read does not complete, do not 4263 * return with an error. This can happen in situations 4264 * where there is no eeprom and prevents getting link. 4265 */ 4266 e_dbg("Auto Read Done did not complete\n"); 4267 ret_val = 0; 4268 } 4269 } 4270 4271 /* Clear PHY Reset Asserted bit */ 4272 status = er32(STATUS); 4273 if (status & E1000_STATUS_PHYRA) 4274 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 4275 else 4276 e_dbg("PHY Reset Asserted not set - needs delay\n"); 4277 4278 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 4279 if (hw->mac.type <= e1000_ich9lan) { 4280 if (!(er32(EECD) & E1000_EECD_PRES) && 4281 (hw->phy.type == e1000_phy_igp_3)) { 4282 e1000e_phy_init_script_igp3(hw); 4283 } 4284 } else { 4285 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 4286 /* Maybe we should do a basic PHY config */ 4287 e_dbg("EEPROM not present\n"); 4288 ret_val = -E1000_ERR_CONFIG; 4289 } 4290 } 4291 4292 return ret_val; 4293 } 4294 4295 /** 4296 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 4297 * @hw: pointer to the HW structure 4298 * 4299 * In the case of a PHY power down to save power, or to turn off link during a 4300 * driver unload, or wake on lan is not enabled, remove the link. 4301 **/ 4302 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 4303 { 4304 /* If the management interface is not enabled, then power down */ 4305 if (!(hw->mac.ops.check_mng_mode(hw) || 4306 hw->phy.ops.check_reset_block(hw))) 4307 e1000_power_down_phy_copper(hw); 4308 } 4309 4310 /** 4311 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 4312 * @hw: pointer to the HW structure 4313 * 4314 * Clears hardware counters specific to the silicon family and calls 4315 * clear_hw_cntrs_generic to clear all general purpose counters. 4316 **/ 4317 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 4318 { 4319 u16 phy_data; 4320 s32 ret_val; 4321 4322 e1000e_clear_hw_cntrs_base(hw); 4323 4324 er32(ALGNERRC); 4325 er32(RXERRC); 4326 er32(TNCRS); 4327 er32(CEXTERR); 4328 er32(TSCTC); 4329 er32(TSCTFC); 4330 4331 er32(MGTPRC); 4332 er32(MGTPDC); 4333 er32(MGTPTC); 4334 4335 er32(IAC); 4336 er32(ICRXOC); 4337 4338 /* Clear PHY statistics registers */ 4339 if ((hw->phy.type == e1000_phy_82578) || 4340 (hw->phy.type == e1000_phy_82579) || 4341 (hw->phy.type == e1000_phy_i217) || 4342 (hw->phy.type == e1000_phy_82577)) { 4343 ret_val = hw->phy.ops.acquire(hw); 4344 if (ret_val) 4345 return; 4346 ret_val = hw->phy.ops.set_page(hw, 4347 HV_STATS_PAGE << IGP_PAGE_SHIFT); 4348 if (ret_val) 4349 goto release; 4350 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 4351 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 4352 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 4353 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 4354 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 4355 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 4356 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 4357 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 4358 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 4359 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 4360 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 4361 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 4362 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 4363 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 4364 release: 4365 hw->phy.ops.release(hw); 4366 } 4367 } 4368 4369 static const struct e1000_mac_operations ich8_mac_ops = { 4370 /* check_mng_mode dependent on mac type */ 4371 .check_for_link = e1000_check_for_copper_link_ich8lan, 4372 /* cleanup_led dependent on mac type */ 4373 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 4374 .get_bus_info = e1000_get_bus_info_ich8lan, 4375 .set_lan_id = e1000_set_lan_id_single_port, 4376 .get_link_up_info = e1000_get_link_up_info_ich8lan, 4377 /* led_on dependent on mac type */ 4378 /* led_off dependent on mac type */ 4379 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 4380 .reset_hw = e1000_reset_hw_ich8lan, 4381 .init_hw = e1000_init_hw_ich8lan, 4382 .setup_link = e1000_setup_link_ich8lan, 4383 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 4384 /* id_led_init dependent on mac type */ 4385 .config_collision_dist = e1000e_config_collision_dist_generic, 4386 .rar_set = e1000e_rar_set_generic, 4387 }; 4388 4389 static const struct e1000_phy_operations ich8_phy_ops = { 4390 .acquire = e1000_acquire_swflag_ich8lan, 4391 .check_reset_block = e1000_check_reset_block_ich8lan, 4392 .commit = NULL, 4393 .get_cfg_done = e1000_get_cfg_done_ich8lan, 4394 .get_cable_length = e1000e_get_cable_length_igp_2, 4395 .read_reg = e1000e_read_phy_reg_igp, 4396 .release = e1000_release_swflag_ich8lan, 4397 .reset = e1000_phy_hw_reset_ich8lan, 4398 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 4399 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 4400 .write_reg = e1000e_write_phy_reg_igp, 4401 }; 4402 4403 static const struct e1000_nvm_operations ich8_nvm_ops = { 4404 .acquire = e1000_acquire_nvm_ich8lan, 4405 .read = e1000_read_nvm_ich8lan, 4406 .release = e1000_release_nvm_ich8lan, 4407 .reload = e1000e_reload_nvm_generic, 4408 .update = e1000_update_nvm_checksum_ich8lan, 4409 .valid_led_default = e1000_valid_led_default_ich8lan, 4410 .validate = e1000_validate_nvm_checksum_ich8lan, 4411 .write = e1000_write_nvm_ich8lan, 4412 }; 4413 4414 const struct e1000_info e1000_ich8_info = { 4415 .mac = e1000_ich8lan, 4416 .flags = FLAG_HAS_WOL 4417 | FLAG_IS_ICH 4418 | FLAG_HAS_CTRLEXT_ON_LOAD 4419 | FLAG_HAS_AMT 4420 | FLAG_HAS_FLASH 4421 | FLAG_APME_IN_WUC, 4422 .pba = 8, 4423 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 4424 .get_variants = e1000_get_variants_ich8lan, 4425 .mac_ops = &ich8_mac_ops, 4426 .phy_ops = &ich8_phy_ops, 4427 .nvm_ops = &ich8_nvm_ops, 4428 }; 4429 4430 const struct e1000_info e1000_ich9_info = { 4431 .mac = e1000_ich9lan, 4432 .flags = FLAG_HAS_JUMBO_FRAMES 4433 | FLAG_IS_ICH 4434 | FLAG_HAS_WOL 4435 | FLAG_HAS_CTRLEXT_ON_LOAD 4436 | FLAG_HAS_AMT 4437 | FLAG_HAS_FLASH 4438 | FLAG_APME_IN_WUC, 4439 .pba = 18, 4440 .max_hw_frame_size = DEFAULT_JUMBO, 4441 .get_variants = e1000_get_variants_ich8lan, 4442 .mac_ops = &ich8_mac_ops, 4443 .phy_ops = &ich8_phy_ops, 4444 .nvm_ops = &ich8_nvm_ops, 4445 }; 4446 4447 const struct e1000_info e1000_ich10_info = { 4448 .mac = e1000_ich10lan, 4449 .flags = FLAG_HAS_JUMBO_FRAMES 4450 | FLAG_IS_ICH 4451 | FLAG_HAS_WOL 4452 | FLAG_HAS_CTRLEXT_ON_LOAD 4453 | FLAG_HAS_AMT 4454 | FLAG_HAS_FLASH 4455 | FLAG_APME_IN_WUC, 4456 .pba = 18, 4457 .max_hw_frame_size = DEFAULT_JUMBO, 4458 .get_variants = e1000_get_variants_ich8lan, 4459 .mac_ops = &ich8_mac_ops, 4460 .phy_ops = &ich8_phy_ops, 4461 .nvm_ops = &ich8_nvm_ops, 4462 }; 4463 4464 const struct e1000_info e1000_pch_info = { 4465 .mac = e1000_pchlan, 4466 .flags = FLAG_IS_ICH 4467 | FLAG_HAS_WOL 4468 | FLAG_HAS_CTRLEXT_ON_LOAD 4469 | FLAG_HAS_AMT 4470 | FLAG_HAS_FLASH 4471 | FLAG_HAS_JUMBO_FRAMES 4472 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 4473 | FLAG_APME_IN_WUC, 4474 .flags2 = FLAG2_HAS_PHY_STATS, 4475 .pba = 26, 4476 .max_hw_frame_size = 4096, 4477 .get_variants = e1000_get_variants_ich8lan, 4478 .mac_ops = &ich8_mac_ops, 4479 .phy_ops = &ich8_phy_ops, 4480 .nvm_ops = &ich8_nvm_ops, 4481 }; 4482 4483 const struct e1000_info e1000_pch2_info = { 4484 .mac = e1000_pch2lan, 4485 .flags = FLAG_IS_ICH 4486 | FLAG_HAS_WOL 4487 | FLAG_HAS_HW_TIMESTAMP 4488 | FLAG_HAS_CTRLEXT_ON_LOAD 4489 | FLAG_HAS_AMT 4490 | FLAG_HAS_FLASH 4491 | FLAG_HAS_JUMBO_FRAMES 4492 | FLAG_APME_IN_WUC, 4493 .flags2 = FLAG2_HAS_PHY_STATS 4494 | FLAG2_HAS_EEE, 4495 .pba = 26, 4496 .max_hw_frame_size = 9018, 4497 .get_variants = e1000_get_variants_ich8lan, 4498 .mac_ops = &ich8_mac_ops, 4499 .phy_ops = &ich8_phy_ops, 4500 .nvm_ops = &ich8_nvm_ops, 4501 }; 4502 4503 const struct e1000_info e1000_pch_lpt_info = { 4504 .mac = e1000_pch_lpt, 4505 .flags = FLAG_IS_ICH 4506 | FLAG_HAS_WOL 4507 | FLAG_HAS_HW_TIMESTAMP 4508 | FLAG_HAS_CTRLEXT_ON_LOAD 4509 | FLAG_HAS_AMT 4510 | FLAG_HAS_FLASH 4511 | FLAG_HAS_JUMBO_FRAMES 4512 | FLAG_APME_IN_WUC, 4513 .flags2 = FLAG2_HAS_PHY_STATS 4514 | FLAG2_HAS_EEE, 4515 .pba = 26, 4516 .max_hw_frame_size = 9018, 4517 .get_variants = e1000_get_variants_ich8lan, 4518 .mac_ops = &ich8_mac_ops, 4519 .phy_ops = &ich8_phy_ops, 4520 .nvm_ops = &ich8_nvm_ops, 4521 }; 4522