1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* 82562G 10/100 Network Connection 23 * 82562G-2 10/100 Network Connection 24 * 82562GT 10/100 Network Connection 25 * 82562GT-2 10/100 Network Connection 26 * 82562V 10/100 Network Connection 27 * 82562V-2 10/100 Network Connection 28 * 82566DC-2 Gigabit Network Connection 29 * 82566DC Gigabit Network Connection 30 * 82566DM-2 Gigabit Network Connection 31 * 82566DM Gigabit Network Connection 32 * 82566MC Gigabit Network Connection 33 * 82566MM Gigabit Network Connection 34 * 82567LM Gigabit Network Connection 35 * 82567LF Gigabit Network Connection 36 * 82567V Gigabit Network Connection 37 * 82567LM-2 Gigabit Network Connection 38 * 82567LF-2 Gigabit Network Connection 39 * 82567V-2 Gigabit Network Connection 40 * 82567LF-3 Gigabit Network Connection 41 * 82567LM-3 Gigabit Network Connection 42 * 82567LM-4 Gigabit Network Connection 43 * 82577LM Gigabit Network Connection 44 * 82577LC Gigabit Network Connection 45 * 82578DM Gigabit Network Connection 46 * 82578DC Gigabit Network Connection 47 * 82579LM Gigabit Network Connection 48 * 82579V Gigabit Network Connection 49 * Ethernet Connection I217-LM 50 * Ethernet Connection I217-V 51 * Ethernet Connection I218-V 52 * Ethernet Connection I218-LM 53 * Ethernet Connection (2) I218-LM 54 * Ethernet Connection (2) I218-V 55 * Ethernet Connection (3) I218-LM 56 * Ethernet Connection (3) I218-V 57 */ 58 59 #include "e1000.h" 60 61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 62 /* Offset 04h HSFSTS */ 63 union ich8_hws_flash_status { 64 struct ich8_hsfsts { 65 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 66 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 67 u16 dael:1; /* bit 2 Direct Access error Log */ 68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 70 u16 reserved1:2; /* bit 13:6 Reserved */ 71 u16 reserved2:6; /* bit 13:6 Reserved */ 72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 74 } hsf_status; 75 u16 regval; 76 }; 77 78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 79 /* Offset 06h FLCTL */ 80 union ich8_hws_flash_ctrl { 81 struct ich8_hsflctl { 82 u16 flcgo:1; /* 0 Flash Cycle Go */ 83 u16 flcycle:2; /* 2:1 Flash Cycle */ 84 u16 reserved:5; /* 7:3 Reserved */ 85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 86 u16 flockdn:6; /* 15:10 Reserved */ 87 } hsf_ctrl; 88 u16 regval; 89 }; 90 91 /* ICH Flash Region Access Permissions */ 92 union ich8_hws_flash_regacc { 93 struct ich8_flracc { 94 u32 grra:8; /* 0:7 GbE region Read Access */ 95 u32 grwa:8; /* 8:15 GbE region Write Access */ 96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 98 } hsf_flregacc; 99 u16 regval; 100 }; 101 102 /* ICH Flash Protected Region */ 103 union ich8_flash_protected_range { 104 struct ich8_pr { 105 u32 base:13; /* 0:12 Protected Range Base */ 106 u32 reserved1:2; /* 13:14 Reserved */ 107 u32 rpe:1; /* 15 Read Protection Enable */ 108 u32 limit:13; /* 16:28 Protected Range Limit */ 109 u32 reserved2:2; /* 29:30 Reserved */ 110 u32 wpe:1; /* 31 Write Protection Enable */ 111 } range; 112 u32 regval; 113 }; 114 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 119 u32 offset, u8 byte); 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 121 u8 *data); 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 123 u16 *data); 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 125 u8 size, u16 *data); 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 127 u32 *data); 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 129 u32 offset, u32 *data); 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 131 u32 offset, u32 data); 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 133 u32 offset, u32 dword); 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 158 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 160 { 161 return readw(hw->flash_address + reg); 162 } 163 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 165 { 166 return readl(hw->flash_address + reg); 167 } 168 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 170 { 171 writew(val, hw->flash_address + reg); 172 } 173 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 175 { 176 writel(val, hw->flash_address + reg); 177 } 178 179 #define er16flash(reg) __er16flash(hw, (reg)) 180 #define er32flash(reg) __er32flash(hw, (reg)) 181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 183 184 /** 185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 186 * @hw: pointer to the HW structure 187 * 188 * Test access to the PHY registers by reading the PHY ID registers. If 189 * the PHY ID is already known (e.g. resume path) compare it with known ID, 190 * otherwise assume the read PHY ID is correct if it is valid. 191 * 192 * Assumes the sw/fw/hw semaphore is already acquired. 193 **/ 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 195 { 196 u16 phy_reg = 0; 197 u32 phy_id = 0; 198 s32 ret_val = 0; 199 u16 retry_count; 200 u32 mac_reg = 0; 201 202 for (retry_count = 0; retry_count < 2; retry_count++) { 203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 204 if (ret_val || (phy_reg == 0xFFFF)) 205 continue; 206 phy_id = (u32)(phy_reg << 16); 207 208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 209 if (ret_val || (phy_reg == 0xFFFF)) { 210 phy_id = 0; 211 continue; 212 } 213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 214 break; 215 } 216 217 if (hw->phy.id) { 218 if (hw->phy.id == phy_id) 219 goto out; 220 } else if (phy_id) { 221 hw->phy.id = phy_id; 222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 223 goto out; 224 } 225 226 /* In case the PHY needs to be in mdio slow mode, 227 * set slow mode and try to get the PHY id again. 228 */ 229 if (hw->mac.type < e1000_pch_lpt) { 230 hw->phy.ops.release(hw); 231 ret_val = e1000_set_mdio_slow_mode_hv(hw); 232 if (!ret_val) 233 ret_val = e1000e_get_phy_id(hw); 234 hw->phy.ops.acquire(hw); 235 } 236 237 if (ret_val) 238 return false; 239 out: 240 if (hw->mac.type >= e1000_pch_lpt) { 241 /* Only unforce SMBus if ME is not active */ 242 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 243 /* Unforce SMBus mode in PHY */ 244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 245 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 247 248 /* Unforce SMBus mode in MAC */ 249 mac_reg = er32(CTRL_EXT); 250 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 251 ew32(CTRL_EXT, mac_reg); 252 } 253 } 254 255 return true; 256 } 257 258 /** 259 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 260 * @hw: pointer to the HW structure 261 * 262 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 263 * used to reset the PHY to a quiescent state when necessary. 264 **/ 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 266 { 267 u32 mac_reg; 268 269 /* Set Phy Config Counter to 50msec */ 270 mac_reg = er32(FEXTNVM3); 271 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 272 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 273 ew32(FEXTNVM3, mac_reg); 274 275 /* Toggle LANPHYPC Value bit */ 276 mac_reg = er32(CTRL); 277 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 278 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 279 ew32(CTRL, mac_reg); 280 e1e_flush(); 281 usleep_range(10, 20); 282 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 283 ew32(CTRL, mac_reg); 284 e1e_flush(); 285 286 if (hw->mac.type < e1000_pch_lpt) { 287 msleep(50); 288 } else { 289 u16 count = 20; 290 291 do { 292 usleep_range(5000, 10000); 293 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 294 295 msleep(30); 296 } 297 } 298 299 /** 300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 301 * @hw: pointer to the HW structure 302 * 303 * Workarounds/flow necessary for PHY initialization during driver load 304 * and resume paths. 305 **/ 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 307 { 308 struct e1000_adapter *adapter = hw->adapter; 309 u32 mac_reg, fwsm = er32(FWSM); 310 s32 ret_val; 311 312 /* Gate automatic PHY configuration by hardware on managed and 313 * non-managed 82579 and newer adapters. 314 */ 315 e1000_gate_hw_phy_config_ich8lan(hw, true); 316 317 /* It is not possible to be certain of the current state of ULP 318 * so forcibly disable it. 319 */ 320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 321 e1000_disable_ulp_lpt_lp(hw, true); 322 323 ret_val = hw->phy.ops.acquire(hw); 324 if (ret_val) { 325 e_dbg("Failed to initialize PHY flow\n"); 326 goto out; 327 } 328 329 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 330 * inaccessible and resetting the PHY is not blocked, toggle the 331 * LANPHYPC Value bit to force the interconnect to PCIe mode. 332 */ 333 switch (hw->mac.type) { 334 case e1000_pch_lpt: 335 case e1000_pch_spt: 336 case e1000_pch_cnp: 337 if (e1000_phy_is_accessible_pchlan(hw)) 338 break; 339 340 /* Before toggling LANPHYPC, see if PHY is accessible by 341 * forcing MAC to SMBus mode first. 342 */ 343 mac_reg = er32(CTRL_EXT); 344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 345 ew32(CTRL_EXT, mac_reg); 346 347 /* Wait 50 milliseconds for MAC to finish any retries 348 * that it might be trying to perform from previous 349 * attempts to acknowledge any phy read requests. 350 */ 351 msleep(50); 352 353 /* fall-through */ 354 case e1000_pch2lan: 355 if (e1000_phy_is_accessible_pchlan(hw)) 356 break; 357 358 /* fall-through */ 359 case e1000_pchlan: 360 if ((hw->mac.type == e1000_pchlan) && 361 (fwsm & E1000_ICH_FWSM_FW_VALID)) 362 break; 363 364 if (hw->phy.ops.check_reset_block(hw)) { 365 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 366 ret_val = -E1000_ERR_PHY; 367 break; 368 } 369 370 /* Toggle LANPHYPC Value bit */ 371 e1000_toggle_lanphypc_pch_lpt(hw); 372 if (hw->mac.type >= e1000_pch_lpt) { 373 if (e1000_phy_is_accessible_pchlan(hw)) 374 break; 375 376 /* Toggling LANPHYPC brings the PHY out of SMBus mode 377 * so ensure that the MAC is also out of SMBus mode 378 */ 379 mac_reg = er32(CTRL_EXT); 380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 381 ew32(CTRL_EXT, mac_reg); 382 383 if (e1000_phy_is_accessible_pchlan(hw)) 384 break; 385 386 ret_val = -E1000_ERR_PHY; 387 } 388 break; 389 default: 390 break; 391 } 392 393 hw->phy.ops.release(hw); 394 if (!ret_val) { 395 396 /* Check to see if able to reset PHY. Print error if not */ 397 if (hw->phy.ops.check_reset_block(hw)) { 398 e_err("Reset blocked by ME\n"); 399 goto out; 400 } 401 402 /* Reset the PHY before any access to it. Doing so, ensures 403 * that the PHY is in a known good state before we read/write 404 * PHY registers. The generic reset is sufficient here, 405 * because we haven't determined the PHY type yet. 406 */ 407 ret_val = e1000e_phy_hw_reset_generic(hw); 408 if (ret_val) 409 goto out; 410 411 /* On a successful reset, possibly need to wait for the PHY 412 * to quiesce to an accessible state before returning control 413 * to the calling function. If the PHY does not quiesce, then 414 * return E1000E_BLK_PHY_RESET, as this is the condition that 415 * the PHY is in. 416 */ 417 ret_val = hw->phy.ops.check_reset_block(hw); 418 if (ret_val) 419 e_err("ME blocked access to PHY after reset\n"); 420 } 421 422 out: 423 /* Ungate automatic PHY configuration on non-managed 82579 */ 424 if ((hw->mac.type == e1000_pch2lan) && 425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 426 usleep_range(10000, 20000); 427 e1000_gate_hw_phy_config_ich8lan(hw, false); 428 } 429 430 return ret_val; 431 } 432 433 /** 434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 435 * @hw: pointer to the HW structure 436 * 437 * Initialize family-specific PHY parameters and function pointers. 438 **/ 439 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 440 { 441 struct e1000_phy_info *phy = &hw->phy; 442 s32 ret_val; 443 444 phy->addr = 1; 445 phy->reset_delay_us = 100; 446 447 phy->ops.set_page = e1000_set_page_igp; 448 phy->ops.read_reg = e1000_read_phy_reg_hv; 449 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 450 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 451 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 452 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 453 phy->ops.write_reg = e1000_write_phy_reg_hv; 454 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 455 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 456 phy->ops.power_up = e1000_power_up_phy_copper; 457 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 458 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 459 460 phy->id = e1000_phy_unknown; 461 462 ret_val = e1000_init_phy_workarounds_pchlan(hw); 463 if (ret_val) 464 return ret_val; 465 466 if (phy->id == e1000_phy_unknown) 467 switch (hw->mac.type) { 468 default: 469 ret_val = e1000e_get_phy_id(hw); 470 if (ret_val) 471 return ret_val; 472 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 473 break; 474 /* fall-through */ 475 case e1000_pch2lan: 476 case e1000_pch_lpt: 477 case e1000_pch_spt: 478 case e1000_pch_cnp: 479 /* In case the PHY needs to be in mdio slow mode, 480 * set slow mode and try to get the PHY id again. 481 */ 482 ret_val = e1000_set_mdio_slow_mode_hv(hw); 483 if (ret_val) 484 return ret_val; 485 ret_val = e1000e_get_phy_id(hw); 486 if (ret_val) 487 return ret_val; 488 break; 489 } 490 phy->type = e1000e_get_phy_type_from_id(phy->id); 491 492 switch (phy->type) { 493 case e1000_phy_82577: 494 case e1000_phy_82579: 495 case e1000_phy_i217: 496 phy->ops.check_polarity = e1000_check_polarity_82577; 497 phy->ops.force_speed_duplex = 498 e1000_phy_force_speed_duplex_82577; 499 phy->ops.get_cable_length = e1000_get_cable_length_82577; 500 phy->ops.get_info = e1000_get_phy_info_82577; 501 phy->ops.commit = e1000e_phy_sw_reset; 502 break; 503 case e1000_phy_82578: 504 phy->ops.check_polarity = e1000_check_polarity_m88; 505 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 506 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 507 phy->ops.get_info = e1000e_get_phy_info_m88; 508 break; 509 default: 510 ret_val = -E1000_ERR_PHY; 511 break; 512 } 513 514 return ret_val; 515 } 516 517 /** 518 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 519 * @hw: pointer to the HW structure 520 * 521 * Initialize family-specific PHY parameters and function pointers. 522 **/ 523 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 524 { 525 struct e1000_phy_info *phy = &hw->phy; 526 s32 ret_val; 527 u16 i = 0; 528 529 phy->addr = 1; 530 phy->reset_delay_us = 100; 531 532 phy->ops.power_up = e1000_power_up_phy_copper; 533 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 534 535 /* We may need to do this twice - once for IGP and if that fails, 536 * we'll set BM func pointers and try again 537 */ 538 ret_val = e1000e_determine_phy_address(hw); 539 if (ret_val) { 540 phy->ops.write_reg = e1000e_write_phy_reg_bm; 541 phy->ops.read_reg = e1000e_read_phy_reg_bm; 542 ret_val = e1000e_determine_phy_address(hw); 543 if (ret_val) { 544 e_dbg("Cannot determine PHY addr. Erroring out\n"); 545 return ret_val; 546 } 547 } 548 549 phy->id = 0; 550 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 551 (i++ < 100)) { 552 usleep_range(1000, 2000); 553 ret_val = e1000e_get_phy_id(hw); 554 if (ret_val) 555 return ret_val; 556 } 557 558 /* Verify phy id */ 559 switch (phy->id) { 560 case IGP03E1000_E_PHY_ID: 561 phy->type = e1000_phy_igp_3; 562 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 563 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 564 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 565 phy->ops.get_info = e1000e_get_phy_info_igp; 566 phy->ops.check_polarity = e1000_check_polarity_igp; 567 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 568 break; 569 case IFE_E_PHY_ID: 570 case IFE_PLUS_E_PHY_ID: 571 case IFE_C_E_PHY_ID: 572 phy->type = e1000_phy_ife; 573 phy->autoneg_mask = E1000_ALL_NOT_GIG; 574 phy->ops.get_info = e1000_get_phy_info_ife; 575 phy->ops.check_polarity = e1000_check_polarity_ife; 576 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 577 break; 578 case BME1000_E_PHY_ID: 579 phy->type = e1000_phy_bm; 580 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 581 phy->ops.read_reg = e1000e_read_phy_reg_bm; 582 phy->ops.write_reg = e1000e_write_phy_reg_bm; 583 phy->ops.commit = e1000e_phy_sw_reset; 584 phy->ops.get_info = e1000e_get_phy_info_m88; 585 phy->ops.check_polarity = e1000_check_polarity_m88; 586 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 587 break; 588 default: 589 return -E1000_ERR_PHY; 590 } 591 592 return 0; 593 } 594 595 /** 596 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 597 * @hw: pointer to the HW structure 598 * 599 * Initialize family-specific NVM parameters and function 600 * pointers. 601 **/ 602 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 603 { 604 struct e1000_nvm_info *nvm = &hw->nvm; 605 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 606 u32 gfpreg, sector_base_addr, sector_end_addr; 607 u16 i; 608 u32 nvm_size; 609 610 nvm->type = e1000_nvm_flash_sw; 611 612 if (hw->mac.type >= e1000_pch_spt) { 613 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 614 * STRAP register. This is because in SPT the GbE Flash region 615 * is no longer accessed through the flash registers. Instead, 616 * the mechanism has changed, and the Flash region access 617 * registers are now implemented in GbE memory space. 618 */ 619 nvm->flash_base_addr = 0; 620 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 621 * NVM_SIZE_MULTIPLIER; 622 nvm->flash_bank_size = nvm_size / 2; 623 /* Adjust to word count */ 624 nvm->flash_bank_size /= sizeof(u16); 625 /* Set the base address for flash register access */ 626 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 627 } else { 628 /* Can't read flash registers if register set isn't mapped. */ 629 if (!hw->flash_address) { 630 e_dbg("ERROR: Flash registers not mapped\n"); 631 return -E1000_ERR_CONFIG; 632 } 633 634 gfpreg = er32flash(ICH_FLASH_GFPREG); 635 636 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 637 * Add 1 to sector_end_addr since this sector is included in 638 * the overall size. 639 */ 640 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 641 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 642 643 /* flash_base_addr is byte-aligned */ 644 nvm->flash_base_addr = sector_base_addr 645 << FLASH_SECTOR_ADDR_SHIFT; 646 647 /* find total size of the NVM, then cut in half since the total 648 * size represents two separate NVM banks. 649 */ 650 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 651 << FLASH_SECTOR_ADDR_SHIFT); 652 nvm->flash_bank_size /= 2; 653 /* Adjust to word count */ 654 nvm->flash_bank_size /= sizeof(u16); 655 } 656 657 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 658 659 /* Clear shadow ram */ 660 for (i = 0; i < nvm->word_size; i++) { 661 dev_spec->shadow_ram[i].modified = false; 662 dev_spec->shadow_ram[i].value = 0xFFFF; 663 } 664 665 return 0; 666 } 667 668 /** 669 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 670 * @hw: pointer to the HW structure 671 * 672 * Initialize family-specific MAC parameters and function 673 * pointers. 674 **/ 675 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 676 { 677 struct e1000_mac_info *mac = &hw->mac; 678 679 /* Set media type function pointer */ 680 hw->phy.media_type = e1000_media_type_copper; 681 682 /* Set mta register count */ 683 mac->mta_reg_count = 32; 684 /* Set rar entry count */ 685 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 686 if (mac->type == e1000_ich8lan) 687 mac->rar_entry_count--; 688 /* FWSM register */ 689 mac->has_fwsm = true; 690 /* ARC subsystem not supported */ 691 mac->arc_subsystem_valid = false; 692 /* Adaptive IFS supported */ 693 mac->adaptive_ifs = true; 694 695 /* LED and other operations */ 696 switch (mac->type) { 697 case e1000_ich8lan: 698 case e1000_ich9lan: 699 case e1000_ich10lan: 700 /* check management mode */ 701 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 702 /* ID LED init */ 703 mac->ops.id_led_init = e1000e_id_led_init_generic; 704 /* blink LED */ 705 mac->ops.blink_led = e1000e_blink_led_generic; 706 /* setup LED */ 707 mac->ops.setup_led = e1000e_setup_led_generic; 708 /* cleanup LED */ 709 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 710 /* turn on/off LED */ 711 mac->ops.led_on = e1000_led_on_ich8lan; 712 mac->ops.led_off = e1000_led_off_ich8lan; 713 break; 714 case e1000_pch2lan: 715 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 716 mac->ops.rar_set = e1000_rar_set_pch2lan; 717 /* fall-through */ 718 case e1000_pch_lpt: 719 case e1000_pch_spt: 720 case e1000_pch_cnp: 721 case e1000_pchlan: 722 /* check management mode */ 723 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 724 /* ID LED init */ 725 mac->ops.id_led_init = e1000_id_led_init_pchlan; 726 /* setup LED */ 727 mac->ops.setup_led = e1000_setup_led_pchlan; 728 /* cleanup LED */ 729 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 730 /* turn on/off LED */ 731 mac->ops.led_on = e1000_led_on_pchlan; 732 mac->ops.led_off = e1000_led_off_pchlan; 733 break; 734 default: 735 break; 736 } 737 738 if (mac->type >= e1000_pch_lpt) { 739 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 740 mac->ops.rar_set = e1000_rar_set_pch_lpt; 741 mac->ops.setup_physical_interface = 742 e1000_setup_copper_link_pch_lpt; 743 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 744 } 745 746 /* Enable PCS Lock-loss workaround for ICH8 */ 747 if (mac->type == e1000_ich8lan) 748 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 749 750 return 0; 751 } 752 753 /** 754 * __e1000_access_emi_reg_locked - Read/write EMI register 755 * @hw: pointer to the HW structure 756 * @addr: EMI address to program 757 * @data: pointer to value to read/write from/to the EMI address 758 * @read: boolean flag to indicate read or write 759 * 760 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 761 **/ 762 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 763 u16 *data, bool read) 764 { 765 s32 ret_val; 766 767 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 768 if (ret_val) 769 return ret_val; 770 771 if (read) 772 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 773 else 774 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 775 776 return ret_val; 777 } 778 779 /** 780 * e1000_read_emi_reg_locked - Read Extended Management Interface register 781 * @hw: pointer to the HW structure 782 * @addr: EMI address to program 783 * @data: value to be read from the EMI address 784 * 785 * Assumes the SW/FW/HW Semaphore is already acquired. 786 **/ 787 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 788 { 789 return __e1000_access_emi_reg_locked(hw, addr, data, true); 790 } 791 792 /** 793 * e1000_write_emi_reg_locked - Write Extended Management Interface register 794 * @hw: pointer to the HW structure 795 * @addr: EMI address to program 796 * @data: value to be written to the EMI address 797 * 798 * Assumes the SW/FW/HW Semaphore is already acquired. 799 **/ 800 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 801 { 802 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 803 } 804 805 /** 806 * e1000_set_eee_pchlan - Enable/disable EEE support 807 * @hw: pointer to the HW structure 808 * 809 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 810 * the link and the EEE capabilities of the link partner. The LPI Control 811 * register bits will remain set only if/when link is up. 812 * 813 * EEE LPI must not be asserted earlier than one second after link is up. 814 * On 82579, EEE LPI should not be enabled until such time otherwise there 815 * can be link issues with some switches. Other devices can have EEE LPI 816 * enabled immediately upon link up since they have a timer in hardware which 817 * prevents LPI from being asserted too early. 818 **/ 819 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 820 { 821 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 822 s32 ret_val; 823 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 824 825 switch (hw->phy.type) { 826 case e1000_phy_82579: 827 lpa = I82579_EEE_LP_ABILITY; 828 pcs_status = I82579_EEE_PCS_STATUS; 829 adv_addr = I82579_EEE_ADVERTISEMENT; 830 break; 831 case e1000_phy_i217: 832 lpa = I217_EEE_LP_ABILITY; 833 pcs_status = I217_EEE_PCS_STATUS; 834 adv_addr = I217_EEE_ADVERTISEMENT; 835 break; 836 default: 837 return 0; 838 } 839 840 ret_val = hw->phy.ops.acquire(hw); 841 if (ret_val) 842 return ret_val; 843 844 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 845 if (ret_val) 846 goto release; 847 848 /* Clear bits that enable EEE in various speeds */ 849 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 850 851 /* Enable EEE if not disabled by user */ 852 if (!dev_spec->eee_disable) { 853 /* Save off link partner's EEE ability */ 854 ret_val = e1000_read_emi_reg_locked(hw, lpa, 855 &dev_spec->eee_lp_ability); 856 if (ret_val) 857 goto release; 858 859 /* Read EEE advertisement */ 860 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 861 if (ret_val) 862 goto release; 863 864 /* Enable EEE only for speeds in which the link partner is 865 * EEE capable and for which we advertise EEE. 866 */ 867 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 868 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 869 870 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 871 e1e_rphy_locked(hw, MII_LPA, &data); 872 if (data & LPA_100FULL) 873 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 874 else 875 /* EEE is not supported in 100Half, so ignore 876 * partner's EEE in 100 ability if full-duplex 877 * is not advertised. 878 */ 879 dev_spec->eee_lp_ability &= 880 ~I82579_EEE_100_SUPPORTED; 881 } 882 } 883 884 if (hw->phy.type == e1000_phy_82579) { 885 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 886 &data); 887 if (ret_val) 888 goto release; 889 890 data &= ~I82579_LPI_100_PLL_SHUT; 891 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 892 data); 893 } 894 895 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 896 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 897 if (ret_val) 898 goto release; 899 900 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 901 release: 902 hw->phy.ops.release(hw); 903 904 return ret_val; 905 } 906 907 /** 908 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 909 * @hw: pointer to the HW structure 910 * @link: link up bool flag 911 * 912 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 913 * preventing further DMA write requests. Workaround the issue by disabling 914 * the de-assertion of the clock request when in 1Gpbs mode. 915 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 916 * speeds in order to avoid Tx hangs. 917 **/ 918 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 919 { 920 u32 fextnvm6 = er32(FEXTNVM6); 921 u32 status = er32(STATUS); 922 s32 ret_val = 0; 923 u16 reg; 924 925 if (link && (status & E1000_STATUS_SPEED_1000)) { 926 ret_val = hw->phy.ops.acquire(hw); 927 if (ret_val) 928 return ret_val; 929 930 ret_val = 931 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 932 ®); 933 if (ret_val) 934 goto release; 935 936 ret_val = 937 e1000e_write_kmrn_reg_locked(hw, 938 E1000_KMRNCTRLSTA_K1_CONFIG, 939 reg & 940 ~E1000_KMRNCTRLSTA_K1_ENABLE); 941 if (ret_val) 942 goto release; 943 944 usleep_range(10, 20); 945 946 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 947 948 ret_val = 949 e1000e_write_kmrn_reg_locked(hw, 950 E1000_KMRNCTRLSTA_K1_CONFIG, 951 reg); 952 release: 953 hw->phy.ops.release(hw); 954 } else { 955 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 956 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 957 958 if ((hw->phy.revision > 5) || !link || 959 ((status & E1000_STATUS_SPEED_100) && 960 (status & E1000_STATUS_FD))) 961 goto update_fextnvm6; 962 963 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 964 if (ret_val) 965 return ret_val; 966 967 /* Clear link status transmit timeout */ 968 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 969 970 if (status & E1000_STATUS_SPEED_100) { 971 /* Set inband Tx timeout to 5x10us for 100Half */ 972 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 973 974 /* Do not extend the K1 entry latency for 100Half */ 975 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 976 } else { 977 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 978 reg |= 50 << 979 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 980 981 /* Extend the K1 entry latency for 10 Mbps */ 982 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 983 } 984 985 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 986 if (ret_val) 987 return ret_val; 988 989 update_fextnvm6: 990 ew32(FEXTNVM6, fextnvm6); 991 } 992 993 return ret_val; 994 } 995 996 /** 997 * e1000_platform_pm_pch_lpt - Set platform power management values 998 * @hw: pointer to the HW structure 999 * @link: bool indicating link status 1000 * 1001 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1002 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1003 * when link is up (which must not exceed the maximum latency supported 1004 * by the platform), otherwise specify there is no LTR requirement. 1005 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1006 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1007 * Capability register set, on this device LTR is set by writing the 1008 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1009 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1010 * message to the PMC. 1011 **/ 1012 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1013 { 1014 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1015 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1016 u16 lat_enc = 0; /* latency encoded */ 1017 1018 if (link) { 1019 u16 speed, duplex, scale = 0; 1020 u16 max_snoop, max_nosnoop; 1021 u16 max_ltr_enc; /* max LTR latency encoded */ 1022 u64 value; 1023 u32 rxa; 1024 1025 if (!hw->adapter->max_frame_size) { 1026 e_dbg("max_frame_size not set.\n"); 1027 return -E1000_ERR_CONFIG; 1028 } 1029 1030 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1031 if (!speed) { 1032 e_dbg("Speed not set.\n"); 1033 return -E1000_ERR_CONFIG; 1034 } 1035 1036 /* Rx Packet Buffer Allocation size (KB) */ 1037 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1038 1039 /* Determine the maximum latency tolerated by the device. 1040 * 1041 * Per the PCIe spec, the tolerated latencies are encoded as 1042 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1043 * a 10-bit value (0-1023) to provide a range from 1 ns to 1044 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1045 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1046 */ 1047 rxa *= 512; 1048 value = (rxa > hw->adapter->max_frame_size) ? 1049 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1050 0; 1051 1052 while (value > PCI_LTR_VALUE_MASK) { 1053 scale++; 1054 value = DIV_ROUND_UP(value, BIT(5)); 1055 } 1056 if (scale > E1000_LTRV_SCALE_MAX) { 1057 e_dbg("Invalid LTR latency scale %d\n", scale); 1058 return -E1000_ERR_CONFIG; 1059 } 1060 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1061 1062 /* Determine the maximum latency tolerated by the platform */ 1063 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1064 &max_snoop); 1065 pci_read_config_word(hw->adapter->pdev, 1066 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1067 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1068 1069 if (lat_enc > max_ltr_enc) 1070 lat_enc = max_ltr_enc; 1071 } 1072 1073 /* Set Snoop and No-Snoop latencies the same */ 1074 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1075 ew32(LTRV, reg); 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1082 * @hw: pointer to the HW structure 1083 * @to_sx: boolean indicating a system power state transition to Sx 1084 * 1085 * When link is down, configure ULP mode to significantly reduce the power 1086 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1087 * ME firmware to start the ULP configuration. If not on an ME enabled 1088 * system, configure the ULP mode by software. 1089 */ 1090 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1091 { 1092 u32 mac_reg; 1093 s32 ret_val = 0; 1094 u16 phy_reg; 1095 u16 oem_reg = 0; 1096 1097 if ((hw->mac.type < e1000_pch_lpt) || 1098 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1099 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1100 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1101 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1102 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1103 return 0; 1104 1105 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1106 /* Request ME configure ULP mode in the PHY */ 1107 mac_reg = er32(H2ME); 1108 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1109 ew32(H2ME, mac_reg); 1110 1111 goto out; 1112 } 1113 1114 if (!to_sx) { 1115 int i = 0; 1116 1117 /* Poll up to 5 seconds for Cable Disconnected indication */ 1118 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1119 /* Bail if link is re-acquired */ 1120 if (er32(STATUS) & E1000_STATUS_LU) 1121 return -E1000_ERR_PHY; 1122 1123 if (i++ == 100) 1124 break; 1125 1126 msleep(50); 1127 } 1128 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1129 (er32(FEXT) & 1130 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1131 } 1132 1133 ret_val = hw->phy.ops.acquire(hw); 1134 if (ret_val) 1135 goto out; 1136 1137 /* Force SMBus mode in PHY */ 1138 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1139 if (ret_val) 1140 goto release; 1141 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1142 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1143 1144 /* Force SMBus mode in MAC */ 1145 mac_reg = er32(CTRL_EXT); 1146 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1147 ew32(CTRL_EXT, mac_reg); 1148 1149 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1150 * LPLU and disable Gig speed when entering ULP 1151 */ 1152 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1153 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1154 &oem_reg); 1155 if (ret_val) 1156 goto release; 1157 1158 phy_reg = oem_reg; 1159 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1160 1161 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1162 phy_reg); 1163 1164 if (ret_val) 1165 goto release; 1166 } 1167 1168 /* Set Inband ULP Exit, Reset to SMBus mode and 1169 * Disable SMBus Release on PERST# in PHY 1170 */ 1171 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1172 if (ret_val) 1173 goto release; 1174 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1175 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1176 if (to_sx) { 1177 if (er32(WUFC) & E1000_WUFC_LNKC) 1178 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1179 else 1180 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1181 1182 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1183 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1184 } else { 1185 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1186 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1187 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1188 } 1189 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1190 1191 /* Set Disable SMBus Release on PERST# in MAC */ 1192 mac_reg = er32(FEXTNVM7); 1193 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1194 ew32(FEXTNVM7, mac_reg); 1195 1196 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1197 phy_reg |= I218_ULP_CONFIG1_START; 1198 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1199 1200 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1201 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1202 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1203 oem_reg); 1204 if (ret_val) 1205 goto release; 1206 } 1207 1208 release: 1209 hw->phy.ops.release(hw); 1210 out: 1211 if (ret_val) 1212 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1213 else 1214 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1215 1216 return ret_val; 1217 } 1218 1219 /** 1220 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1221 * @hw: pointer to the HW structure 1222 * @force: boolean indicating whether or not to force disabling ULP 1223 * 1224 * Un-configure ULP mode when link is up, the system is transitioned from 1225 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1226 * system, poll for an indication from ME that ULP has been un-configured. 1227 * If not on an ME enabled system, un-configure the ULP mode by software. 1228 * 1229 * During nominal operation, this function is called when link is acquired 1230 * to disable ULP mode (force=false); otherwise, for example when unloading 1231 * the driver or during Sx->S0 transitions, this is called with force=true 1232 * to forcibly disable ULP. 1233 */ 1234 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1235 { 1236 s32 ret_val = 0; 1237 u32 mac_reg; 1238 u16 phy_reg; 1239 int i = 0; 1240 1241 if ((hw->mac.type < e1000_pch_lpt) || 1242 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1243 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1244 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1245 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1246 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1247 return 0; 1248 1249 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1250 if (force) { 1251 /* Request ME un-configure ULP mode in the PHY */ 1252 mac_reg = er32(H2ME); 1253 mac_reg &= ~E1000_H2ME_ULP; 1254 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1255 ew32(H2ME, mac_reg); 1256 } 1257 1258 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1259 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1260 if (i++ == 30) { 1261 ret_val = -E1000_ERR_PHY; 1262 goto out; 1263 } 1264 1265 usleep_range(10000, 20000); 1266 } 1267 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1268 1269 if (force) { 1270 mac_reg = er32(H2ME); 1271 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1272 ew32(H2ME, mac_reg); 1273 } else { 1274 /* Clear H2ME.ULP after ME ULP configuration */ 1275 mac_reg = er32(H2ME); 1276 mac_reg &= ~E1000_H2ME_ULP; 1277 ew32(H2ME, mac_reg); 1278 } 1279 1280 goto out; 1281 } 1282 1283 ret_val = hw->phy.ops.acquire(hw); 1284 if (ret_val) 1285 goto out; 1286 1287 if (force) 1288 /* Toggle LANPHYPC Value bit */ 1289 e1000_toggle_lanphypc_pch_lpt(hw); 1290 1291 /* Unforce SMBus mode in PHY */ 1292 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1293 if (ret_val) { 1294 /* The MAC might be in PCIe mode, so temporarily force to 1295 * SMBus mode in order to access the PHY. 1296 */ 1297 mac_reg = er32(CTRL_EXT); 1298 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1299 ew32(CTRL_EXT, mac_reg); 1300 1301 msleep(50); 1302 1303 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1304 &phy_reg); 1305 if (ret_val) 1306 goto release; 1307 } 1308 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1309 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1310 1311 /* Unforce SMBus mode in MAC */ 1312 mac_reg = er32(CTRL_EXT); 1313 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1314 ew32(CTRL_EXT, mac_reg); 1315 1316 /* When ULP mode was previously entered, K1 was disabled by the 1317 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1318 */ 1319 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1320 if (ret_val) 1321 goto release; 1322 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1323 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1324 1325 /* Clear ULP enabled configuration */ 1326 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1327 if (ret_val) 1328 goto release; 1329 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1330 I218_ULP_CONFIG1_STICKY_ULP | 1331 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1332 I218_ULP_CONFIG1_WOL_HOST | 1333 I218_ULP_CONFIG1_INBAND_EXIT | 1334 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1335 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1336 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1337 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1338 1339 /* Commit ULP changes by starting auto ULP configuration */ 1340 phy_reg |= I218_ULP_CONFIG1_START; 1341 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1342 1343 /* Clear Disable SMBus Release on PERST# in MAC */ 1344 mac_reg = er32(FEXTNVM7); 1345 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1346 ew32(FEXTNVM7, mac_reg); 1347 1348 release: 1349 hw->phy.ops.release(hw); 1350 if (force) { 1351 e1000_phy_hw_reset(hw); 1352 msleep(50); 1353 } 1354 out: 1355 if (ret_val) 1356 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1357 else 1358 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1359 1360 return ret_val; 1361 } 1362 1363 /** 1364 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1365 * @hw: pointer to the HW structure 1366 * 1367 * Checks to see of the link status of the hardware has changed. If a 1368 * change in link status has been detected, then we read the PHY registers 1369 * to get the current speed/duplex if link exists. 1370 * 1371 * Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link 1372 * up). 1373 **/ 1374 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1375 { 1376 struct e1000_mac_info *mac = &hw->mac; 1377 s32 ret_val, tipg_reg = 0; 1378 u16 emi_addr, emi_val = 0; 1379 bool link; 1380 u16 phy_reg; 1381 1382 /* We only want to go out to the PHY registers to see if Auto-Neg 1383 * has completed and/or if our link status has changed. The 1384 * get_link_status flag is set upon receiving a Link Status 1385 * Change or Rx Sequence Error interrupt. 1386 */ 1387 if (!mac->get_link_status) 1388 return 1; 1389 1390 /* First we want to see if the MII Status Register reports 1391 * link. If so, then we want to get the current speed/duplex 1392 * of the PHY. 1393 */ 1394 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1395 if (ret_val) 1396 return ret_val; 1397 1398 if (hw->mac.type == e1000_pchlan) { 1399 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1400 if (ret_val) 1401 return ret_val; 1402 } 1403 1404 /* When connected at 10Mbps half-duplex, some parts are excessively 1405 * aggressive resulting in many collisions. To avoid this, increase 1406 * the IPG and reduce Rx latency in the PHY. 1407 */ 1408 if ((hw->mac.type >= e1000_pch2lan) && link) { 1409 u16 speed, duplex; 1410 1411 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1412 tipg_reg = er32(TIPG); 1413 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1414 1415 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1416 tipg_reg |= 0xFF; 1417 /* Reduce Rx latency in analog PHY */ 1418 emi_val = 0; 1419 } else if (hw->mac.type >= e1000_pch_spt && 1420 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1421 tipg_reg |= 0xC; 1422 emi_val = 1; 1423 } else { 1424 1425 /* Roll back the default values */ 1426 tipg_reg |= 0x08; 1427 emi_val = 1; 1428 } 1429 1430 ew32(TIPG, tipg_reg); 1431 1432 ret_val = hw->phy.ops.acquire(hw); 1433 if (ret_val) 1434 return ret_val; 1435 1436 if (hw->mac.type == e1000_pch2lan) 1437 emi_addr = I82579_RX_CONFIG; 1438 else 1439 emi_addr = I217_RX_CONFIG; 1440 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1441 1442 if (hw->mac.type >= e1000_pch_lpt) { 1443 u16 phy_reg; 1444 1445 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1446 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1447 if (speed == SPEED_100 || speed == SPEED_10) 1448 phy_reg |= 0x3E8; 1449 else 1450 phy_reg |= 0xFA; 1451 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1452 } 1453 hw->phy.ops.release(hw); 1454 1455 if (ret_val) 1456 return ret_val; 1457 1458 if (hw->mac.type >= e1000_pch_spt) { 1459 u16 data; 1460 u16 ptr_gap; 1461 1462 if (speed == SPEED_1000) { 1463 ret_val = hw->phy.ops.acquire(hw); 1464 if (ret_val) 1465 return ret_val; 1466 1467 ret_val = e1e_rphy_locked(hw, 1468 PHY_REG(776, 20), 1469 &data); 1470 if (ret_val) { 1471 hw->phy.ops.release(hw); 1472 return ret_val; 1473 } 1474 1475 ptr_gap = (data & (0x3FF << 2)) >> 2; 1476 if (ptr_gap < 0x18) { 1477 data &= ~(0x3FF << 2); 1478 data |= (0x18 << 2); 1479 ret_val = 1480 e1e_wphy_locked(hw, 1481 PHY_REG(776, 20), 1482 data); 1483 } 1484 hw->phy.ops.release(hw); 1485 if (ret_val) 1486 return ret_val; 1487 } else { 1488 ret_val = hw->phy.ops.acquire(hw); 1489 if (ret_val) 1490 return ret_val; 1491 1492 ret_val = e1e_wphy_locked(hw, 1493 PHY_REG(776, 20), 1494 0xC023); 1495 hw->phy.ops.release(hw); 1496 if (ret_val) 1497 return ret_val; 1498 1499 } 1500 } 1501 } 1502 1503 /* I217 Packet Loss issue: 1504 * ensure that FEXTNVM4 Beacon Duration is set correctly 1505 * on power up. 1506 * Set the Beacon Duration for I217 to 8 usec 1507 */ 1508 if (hw->mac.type >= e1000_pch_lpt) { 1509 u32 mac_reg; 1510 1511 mac_reg = er32(FEXTNVM4); 1512 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1513 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1514 ew32(FEXTNVM4, mac_reg); 1515 } 1516 1517 /* Work-around I218 hang issue */ 1518 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1519 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1520 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1521 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1522 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1523 if (ret_val) 1524 return ret_val; 1525 } 1526 if (hw->mac.type >= e1000_pch_lpt) { 1527 /* Set platform power management values for 1528 * Latency Tolerance Reporting (LTR) 1529 */ 1530 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1531 if (ret_val) 1532 return ret_val; 1533 } 1534 1535 /* Clear link partner's EEE ability */ 1536 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1537 1538 if (hw->mac.type >= e1000_pch_lpt) { 1539 u32 fextnvm6 = er32(FEXTNVM6); 1540 1541 if (hw->mac.type == e1000_pch_spt) { 1542 /* FEXTNVM6 K1-off workaround - for SPT only */ 1543 u32 pcieanacfg = er32(PCIEANACFG); 1544 1545 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1546 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1547 else 1548 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1549 } 1550 1551 ew32(FEXTNVM6, fextnvm6); 1552 } 1553 1554 if (!link) 1555 return 0; /* No link detected */ 1556 1557 mac->get_link_status = false; 1558 1559 switch (hw->mac.type) { 1560 case e1000_pch2lan: 1561 ret_val = e1000_k1_workaround_lv(hw); 1562 if (ret_val) 1563 return ret_val; 1564 /* fall-thru */ 1565 case e1000_pchlan: 1566 if (hw->phy.type == e1000_phy_82578) { 1567 ret_val = e1000_link_stall_workaround_hv(hw); 1568 if (ret_val) 1569 return ret_val; 1570 } 1571 1572 /* Workaround for PCHx parts in half-duplex: 1573 * Set the number of preambles removed from the packet 1574 * when it is passed from the PHY to the MAC to prevent 1575 * the MAC from misinterpreting the packet type. 1576 */ 1577 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1578 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1579 1580 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1581 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1582 1583 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1584 break; 1585 default: 1586 break; 1587 } 1588 1589 /* Check if there was DownShift, must be checked 1590 * immediately after link-up 1591 */ 1592 e1000e_check_downshift(hw); 1593 1594 /* Enable/Disable EEE after link up */ 1595 if (hw->phy.type > e1000_phy_82579) { 1596 ret_val = e1000_set_eee_pchlan(hw); 1597 if (ret_val) 1598 return ret_val; 1599 } 1600 1601 /* If we are forcing speed/duplex, then we simply return since 1602 * we have already determined whether we have link or not. 1603 */ 1604 if (!mac->autoneg) 1605 return -E1000_ERR_CONFIG; 1606 1607 /* Auto-Neg is enabled. Auto Speed Detection takes care 1608 * of MAC speed/duplex configuration. So we only need to 1609 * configure Collision Distance in the MAC. 1610 */ 1611 mac->ops.config_collision_dist(hw); 1612 1613 /* Configure Flow Control now that Auto-Neg has completed. 1614 * First, we need to restore the desired flow control 1615 * settings because we may have had to re-autoneg with a 1616 * different link partner. 1617 */ 1618 ret_val = e1000e_config_fc_after_link_up(hw); 1619 if (ret_val) { 1620 e_dbg("Error configuring flow control\n"); 1621 return ret_val; 1622 } 1623 1624 return 1; 1625 } 1626 1627 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1628 { 1629 struct e1000_hw *hw = &adapter->hw; 1630 s32 rc; 1631 1632 rc = e1000_init_mac_params_ich8lan(hw); 1633 if (rc) 1634 return rc; 1635 1636 rc = e1000_init_nvm_params_ich8lan(hw); 1637 if (rc) 1638 return rc; 1639 1640 switch (hw->mac.type) { 1641 case e1000_ich8lan: 1642 case e1000_ich9lan: 1643 case e1000_ich10lan: 1644 rc = e1000_init_phy_params_ich8lan(hw); 1645 break; 1646 case e1000_pchlan: 1647 case e1000_pch2lan: 1648 case e1000_pch_lpt: 1649 case e1000_pch_spt: 1650 case e1000_pch_cnp: 1651 rc = e1000_init_phy_params_pchlan(hw); 1652 break; 1653 default: 1654 break; 1655 } 1656 if (rc) 1657 return rc; 1658 1659 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1660 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1661 */ 1662 if ((adapter->hw.phy.type == e1000_phy_ife) || 1663 ((adapter->hw.mac.type >= e1000_pch2lan) && 1664 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1665 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1666 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1667 1668 hw->mac.ops.blink_led = NULL; 1669 } 1670 1671 if ((adapter->hw.mac.type == e1000_ich8lan) && 1672 (adapter->hw.phy.type != e1000_phy_ife)) 1673 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1674 1675 /* Enable workaround for 82579 w/ ME enabled */ 1676 if ((adapter->hw.mac.type == e1000_pch2lan) && 1677 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1678 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1679 1680 return 0; 1681 } 1682 1683 static DEFINE_MUTEX(nvm_mutex); 1684 1685 /** 1686 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1687 * @hw: pointer to the HW structure 1688 * 1689 * Acquires the mutex for performing NVM operations. 1690 **/ 1691 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1692 { 1693 mutex_lock(&nvm_mutex); 1694 1695 return 0; 1696 } 1697 1698 /** 1699 * e1000_release_nvm_ich8lan - Release NVM mutex 1700 * @hw: pointer to the HW structure 1701 * 1702 * Releases the mutex used while performing NVM operations. 1703 **/ 1704 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1705 { 1706 mutex_unlock(&nvm_mutex); 1707 } 1708 1709 /** 1710 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1711 * @hw: pointer to the HW structure 1712 * 1713 * Acquires the software control flag for performing PHY and select 1714 * MAC CSR accesses. 1715 **/ 1716 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1717 { 1718 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1719 s32 ret_val = 0; 1720 1721 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1722 &hw->adapter->state)) { 1723 e_dbg("contention for Phy access\n"); 1724 return -E1000_ERR_PHY; 1725 } 1726 1727 while (timeout) { 1728 extcnf_ctrl = er32(EXTCNF_CTRL); 1729 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1730 break; 1731 1732 mdelay(1); 1733 timeout--; 1734 } 1735 1736 if (!timeout) { 1737 e_dbg("SW has already locked the resource.\n"); 1738 ret_val = -E1000_ERR_CONFIG; 1739 goto out; 1740 } 1741 1742 timeout = SW_FLAG_TIMEOUT; 1743 1744 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1745 ew32(EXTCNF_CTRL, extcnf_ctrl); 1746 1747 while (timeout) { 1748 extcnf_ctrl = er32(EXTCNF_CTRL); 1749 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1750 break; 1751 1752 mdelay(1); 1753 timeout--; 1754 } 1755 1756 if (!timeout) { 1757 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1758 er32(FWSM), extcnf_ctrl); 1759 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1760 ew32(EXTCNF_CTRL, extcnf_ctrl); 1761 ret_val = -E1000_ERR_CONFIG; 1762 goto out; 1763 } 1764 1765 out: 1766 if (ret_val) 1767 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1768 1769 return ret_val; 1770 } 1771 1772 /** 1773 * e1000_release_swflag_ich8lan - Release software control flag 1774 * @hw: pointer to the HW structure 1775 * 1776 * Releases the software control flag for performing PHY and select 1777 * MAC CSR accesses. 1778 **/ 1779 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1780 { 1781 u32 extcnf_ctrl; 1782 1783 extcnf_ctrl = er32(EXTCNF_CTRL); 1784 1785 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1786 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1787 ew32(EXTCNF_CTRL, extcnf_ctrl); 1788 } else { 1789 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1790 } 1791 1792 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1793 } 1794 1795 /** 1796 * e1000_check_mng_mode_ich8lan - Checks management mode 1797 * @hw: pointer to the HW structure 1798 * 1799 * This checks if the adapter has any manageability enabled. 1800 * This is a function pointer entry point only called by read/write 1801 * routines for the PHY and NVM parts. 1802 **/ 1803 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1804 { 1805 u32 fwsm; 1806 1807 fwsm = er32(FWSM); 1808 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1809 ((fwsm & E1000_FWSM_MODE_MASK) == 1810 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1811 } 1812 1813 /** 1814 * e1000_check_mng_mode_pchlan - Checks management mode 1815 * @hw: pointer to the HW structure 1816 * 1817 * This checks if the adapter has iAMT enabled. 1818 * This is a function pointer entry point only called by read/write 1819 * routines for the PHY and NVM parts. 1820 **/ 1821 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1822 { 1823 u32 fwsm; 1824 1825 fwsm = er32(FWSM); 1826 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1827 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1828 } 1829 1830 /** 1831 * e1000_rar_set_pch2lan - Set receive address register 1832 * @hw: pointer to the HW structure 1833 * @addr: pointer to the receive address 1834 * @index: receive address array register 1835 * 1836 * Sets the receive address array register at index to the address passed 1837 * in by addr. For 82579, RAR[0] is the base address register that is to 1838 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1839 * Use SHRA[0-3] in place of those reserved for ME. 1840 **/ 1841 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1842 { 1843 u32 rar_low, rar_high; 1844 1845 /* HW expects these in little endian so we reverse the byte order 1846 * from network order (big endian) to little endian 1847 */ 1848 rar_low = ((u32)addr[0] | 1849 ((u32)addr[1] << 8) | 1850 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1851 1852 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1853 1854 /* If MAC address zero, no need to set the AV bit */ 1855 if (rar_low || rar_high) 1856 rar_high |= E1000_RAH_AV; 1857 1858 if (index == 0) { 1859 ew32(RAL(index), rar_low); 1860 e1e_flush(); 1861 ew32(RAH(index), rar_high); 1862 e1e_flush(); 1863 return 0; 1864 } 1865 1866 /* RAR[1-6] are owned by manageability. Skip those and program the 1867 * next address into the SHRA register array. 1868 */ 1869 if (index < (u32)(hw->mac.rar_entry_count)) { 1870 s32 ret_val; 1871 1872 ret_val = e1000_acquire_swflag_ich8lan(hw); 1873 if (ret_val) 1874 goto out; 1875 1876 ew32(SHRAL(index - 1), rar_low); 1877 e1e_flush(); 1878 ew32(SHRAH(index - 1), rar_high); 1879 e1e_flush(); 1880 1881 e1000_release_swflag_ich8lan(hw); 1882 1883 /* verify the register updates */ 1884 if ((er32(SHRAL(index - 1)) == rar_low) && 1885 (er32(SHRAH(index - 1)) == rar_high)) 1886 return 0; 1887 1888 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1889 (index - 1), er32(FWSM)); 1890 } 1891 1892 out: 1893 e_dbg("Failed to write receive address at index %d\n", index); 1894 return -E1000_ERR_CONFIG; 1895 } 1896 1897 /** 1898 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1899 * @hw: pointer to the HW structure 1900 * 1901 * Get the number of available receive registers that the Host can 1902 * program. SHRA[0-10] are the shared receive address registers 1903 * that are shared between the Host and manageability engine (ME). 1904 * ME can reserve any number of addresses and the host needs to be 1905 * able to tell how many available registers it has access to. 1906 **/ 1907 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1908 { 1909 u32 wlock_mac; 1910 u32 num_entries; 1911 1912 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1913 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1914 1915 switch (wlock_mac) { 1916 case 0: 1917 /* All SHRA[0..10] and RAR[0] available */ 1918 num_entries = hw->mac.rar_entry_count; 1919 break; 1920 case 1: 1921 /* Only RAR[0] available */ 1922 num_entries = 1; 1923 break; 1924 default: 1925 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1926 num_entries = wlock_mac + 1; 1927 break; 1928 } 1929 1930 return num_entries; 1931 } 1932 1933 /** 1934 * e1000_rar_set_pch_lpt - Set receive address registers 1935 * @hw: pointer to the HW structure 1936 * @addr: pointer to the receive address 1937 * @index: receive address array register 1938 * 1939 * Sets the receive address register array at index to the address passed 1940 * in by addr. For LPT, RAR[0] is the base address register that is to 1941 * contain the MAC address. SHRA[0-10] are the shared receive address 1942 * registers that are shared between the Host and manageability engine (ME). 1943 **/ 1944 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1945 { 1946 u32 rar_low, rar_high; 1947 u32 wlock_mac; 1948 1949 /* HW expects these in little endian so we reverse the byte order 1950 * from network order (big endian) to little endian 1951 */ 1952 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1953 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1954 1955 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1956 1957 /* If MAC address zero, no need to set the AV bit */ 1958 if (rar_low || rar_high) 1959 rar_high |= E1000_RAH_AV; 1960 1961 if (index == 0) { 1962 ew32(RAL(index), rar_low); 1963 e1e_flush(); 1964 ew32(RAH(index), rar_high); 1965 e1e_flush(); 1966 return 0; 1967 } 1968 1969 /* The manageability engine (ME) can lock certain SHRAR registers that 1970 * it is using - those registers are unavailable for use. 1971 */ 1972 if (index < hw->mac.rar_entry_count) { 1973 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1974 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1975 1976 /* Check if all SHRAR registers are locked */ 1977 if (wlock_mac == 1) 1978 goto out; 1979 1980 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1981 s32 ret_val; 1982 1983 ret_val = e1000_acquire_swflag_ich8lan(hw); 1984 1985 if (ret_val) 1986 goto out; 1987 1988 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1989 e1e_flush(); 1990 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1991 e1e_flush(); 1992 1993 e1000_release_swflag_ich8lan(hw); 1994 1995 /* verify the register updates */ 1996 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1997 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1998 return 0; 1999 } 2000 } 2001 2002 out: 2003 e_dbg("Failed to write receive address at index %d\n", index); 2004 return -E1000_ERR_CONFIG; 2005 } 2006 2007 /** 2008 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2009 * @hw: pointer to the HW structure 2010 * 2011 * Checks if firmware is blocking the reset of the PHY. 2012 * This is a function pointer entry point only called by 2013 * reset routines. 2014 **/ 2015 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2016 { 2017 bool blocked = false; 2018 int i = 0; 2019 2020 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2021 (i++ < 30)) 2022 usleep_range(10000, 20000); 2023 return blocked ? E1000_BLK_PHY_RESET : 0; 2024 } 2025 2026 /** 2027 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2028 * @hw: pointer to the HW structure 2029 * 2030 * Assumes semaphore already acquired. 2031 * 2032 **/ 2033 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2034 { 2035 u16 phy_data; 2036 u32 strap = er32(STRAP); 2037 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2038 E1000_STRAP_SMT_FREQ_SHIFT; 2039 s32 ret_val; 2040 2041 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2042 2043 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2044 if (ret_val) 2045 return ret_val; 2046 2047 phy_data &= ~HV_SMB_ADDR_MASK; 2048 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2049 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2050 2051 if (hw->phy.type == e1000_phy_i217) { 2052 /* Restore SMBus frequency */ 2053 if (freq--) { 2054 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2055 phy_data |= (freq & BIT(0)) << 2056 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2057 phy_data |= (freq & BIT(1)) << 2058 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2059 } else { 2060 e_dbg("Unsupported SMB frequency in PHY\n"); 2061 } 2062 } 2063 2064 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2065 } 2066 2067 /** 2068 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2069 * @hw: pointer to the HW structure 2070 * 2071 * SW should configure the LCD from the NVM extended configuration region 2072 * as a workaround for certain parts. 2073 **/ 2074 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2075 { 2076 struct e1000_phy_info *phy = &hw->phy; 2077 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2078 s32 ret_val = 0; 2079 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2080 2081 /* Initialize the PHY from the NVM on ICH platforms. This 2082 * is needed due to an issue where the NVM configuration is 2083 * not properly autoloaded after power transitions. 2084 * Therefore, after each PHY reset, we will load the 2085 * configuration data out of the NVM manually. 2086 */ 2087 switch (hw->mac.type) { 2088 case e1000_ich8lan: 2089 if (phy->type != e1000_phy_igp_3) 2090 return ret_val; 2091 2092 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2093 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2094 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2095 break; 2096 } 2097 /* Fall-thru */ 2098 case e1000_pchlan: 2099 case e1000_pch2lan: 2100 case e1000_pch_lpt: 2101 case e1000_pch_spt: 2102 case e1000_pch_cnp: 2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2104 break; 2105 default: 2106 return ret_val; 2107 } 2108 2109 ret_val = hw->phy.ops.acquire(hw); 2110 if (ret_val) 2111 return ret_val; 2112 2113 data = er32(FEXTNVM); 2114 if (!(data & sw_cfg_mask)) 2115 goto release; 2116 2117 /* Make sure HW does not configure LCD from PHY 2118 * extended configuration before SW configuration 2119 */ 2120 data = er32(EXTCNF_CTRL); 2121 if ((hw->mac.type < e1000_pch2lan) && 2122 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2123 goto release; 2124 2125 cnf_size = er32(EXTCNF_SIZE); 2126 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2127 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2128 if (!cnf_size) 2129 goto release; 2130 2131 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2132 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2133 2134 if (((hw->mac.type == e1000_pchlan) && 2135 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2136 (hw->mac.type > e1000_pchlan)) { 2137 /* HW configures the SMBus address and LEDs when the 2138 * OEM and LCD Write Enable bits are set in the NVM. 2139 * When both NVM bits are cleared, SW will configure 2140 * them instead. 2141 */ 2142 ret_val = e1000_write_smbus_addr(hw); 2143 if (ret_val) 2144 goto release; 2145 2146 data = er32(LEDCTL); 2147 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2148 (u16)data); 2149 if (ret_val) 2150 goto release; 2151 } 2152 2153 /* Configure LCD from extended configuration region. */ 2154 2155 /* cnf_base_addr is in DWORD */ 2156 word_addr = (u16)(cnf_base_addr << 1); 2157 2158 for (i = 0; i < cnf_size; i++) { 2159 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2160 if (ret_val) 2161 goto release; 2162 2163 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2164 1, ®_addr); 2165 if (ret_val) 2166 goto release; 2167 2168 /* Save off the PHY page for future writes. */ 2169 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2170 phy_page = reg_data; 2171 continue; 2172 } 2173 2174 reg_addr &= PHY_REG_MASK; 2175 reg_addr |= phy_page; 2176 2177 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2178 if (ret_val) 2179 goto release; 2180 } 2181 2182 release: 2183 hw->phy.ops.release(hw); 2184 return ret_val; 2185 } 2186 2187 /** 2188 * e1000_k1_gig_workaround_hv - K1 Si workaround 2189 * @hw: pointer to the HW structure 2190 * @link: link up bool flag 2191 * 2192 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2193 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2194 * If link is down, the function will restore the default K1 setting located 2195 * in the NVM. 2196 **/ 2197 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2198 { 2199 s32 ret_val = 0; 2200 u16 status_reg = 0; 2201 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2202 2203 if (hw->mac.type != e1000_pchlan) 2204 return 0; 2205 2206 /* Wrap the whole flow with the sw flag */ 2207 ret_val = hw->phy.ops.acquire(hw); 2208 if (ret_val) 2209 return ret_val; 2210 2211 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2212 if (link) { 2213 if (hw->phy.type == e1000_phy_82578) { 2214 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2215 &status_reg); 2216 if (ret_val) 2217 goto release; 2218 2219 status_reg &= (BM_CS_STATUS_LINK_UP | 2220 BM_CS_STATUS_RESOLVED | 2221 BM_CS_STATUS_SPEED_MASK); 2222 2223 if (status_reg == (BM_CS_STATUS_LINK_UP | 2224 BM_CS_STATUS_RESOLVED | 2225 BM_CS_STATUS_SPEED_1000)) 2226 k1_enable = false; 2227 } 2228 2229 if (hw->phy.type == e1000_phy_82577) { 2230 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2231 if (ret_val) 2232 goto release; 2233 2234 status_reg &= (HV_M_STATUS_LINK_UP | 2235 HV_M_STATUS_AUTONEG_COMPLETE | 2236 HV_M_STATUS_SPEED_MASK); 2237 2238 if (status_reg == (HV_M_STATUS_LINK_UP | 2239 HV_M_STATUS_AUTONEG_COMPLETE | 2240 HV_M_STATUS_SPEED_1000)) 2241 k1_enable = false; 2242 } 2243 2244 /* Link stall fix for link up */ 2245 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2246 if (ret_val) 2247 goto release; 2248 2249 } else { 2250 /* Link stall fix for link down */ 2251 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2252 if (ret_val) 2253 goto release; 2254 } 2255 2256 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2257 2258 release: 2259 hw->phy.ops.release(hw); 2260 2261 return ret_val; 2262 } 2263 2264 /** 2265 * e1000_configure_k1_ich8lan - Configure K1 power state 2266 * @hw: pointer to the HW structure 2267 * @enable: K1 state to configure 2268 * 2269 * Configure the K1 power state based on the provided parameter. 2270 * Assumes semaphore already acquired. 2271 * 2272 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2273 **/ 2274 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2275 { 2276 s32 ret_val; 2277 u32 ctrl_reg = 0; 2278 u32 ctrl_ext = 0; 2279 u32 reg = 0; 2280 u16 kmrn_reg = 0; 2281 2282 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2283 &kmrn_reg); 2284 if (ret_val) 2285 return ret_val; 2286 2287 if (k1_enable) 2288 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2289 else 2290 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2291 2292 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2293 kmrn_reg); 2294 if (ret_val) 2295 return ret_val; 2296 2297 usleep_range(20, 40); 2298 ctrl_ext = er32(CTRL_EXT); 2299 ctrl_reg = er32(CTRL); 2300 2301 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2302 reg |= E1000_CTRL_FRCSPD; 2303 ew32(CTRL, reg); 2304 2305 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2306 e1e_flush(); 2307 usleep_range(20, 40); 2308 ew32(CTRL, ctrl_reg); 2309 ew32(CTRL_EXT, ctrl_ext); 2310 e1e_flush(); 2311 usleep_range(20, 40); 2312 2313 return 0; 2314 } 2315 2316 /** 2317 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2318 * @hw: pointer to the HW structure 2319 * @d0_state: boolean if entering d0 or d3 device state 2320 * 2321 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2322 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2323 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2324 **/ 2325 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2326 { 2327 s32 ret_val = 0; 2328 u32 mac_reg; 2329 u16 oem_reg; 2330 2331 if (hw->mac.type < e1000_pchlan) 2332 return ret_val; 2333 2334 ret_val = hw->phy.ops.acquire(hw); 2335 if (ret_val) 2336 return ret_val; 2337 2338 if (hw->mac.type == e1000_pchlan) { 2339 mac_reg = er32(EXTCNF_CTRL); 2340 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2341 goto release; 2342 } 2343 2344 mac_reg = er32(FEXTNVM); 2345 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2346 goto release; 2347 2348 mac_reg = er32(PHY_CTRL); 2349 2350 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2351 if (ret_val) 2352 goto release; 2353 2354 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2355 2356 if (d0_state) { 2357 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2358 oem_reg |= HV_OEM_BITS_GBE_DIS; 2359 2360 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2361 oem_reg |= HV_OEM_BITS_LPLU; 2362 } else { 2363 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2364 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2365 oem_reg |= HV_OEM_BITS_GBE_DIS; 2366 2367 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2368 E1000_PHY_CTRL_NOND0A_LPLU)) 2369 oem_reg |= HV_OEM_BITS_LPLU; 2370 } 2371 2372 /* Set Restart auto-neg to activate the bits */ 2373 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2374 !hw->phy.ops.check_reset_block(hw)) 2375 oem_reg |= HV_OEM_BITS_RESTART_AN; 2376 2377 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2378 2379 release: 2380 hw->phy.ops.release(hw); 2381 2382 return ret_val; 2383 } 2384 2385 /** 2386 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2387 * @hw: pointer to the HW structure 2388 **/ 2389 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2390 { 2391 s32 ret_val; 2392 u16 data; 2393 2394 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2395 if (ret_val) 2396 return ret_val; 2397 2398 data |= HV_KMRN_MDIO_SLOW; 2399 2400 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2401 2402 return ret_val; 2403 } 2404 2405 /** 2406 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2407 * done after every PHY reset. 2408 **/ 2409 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2410 { 2411 s32 ret_val = 0; 2412 u16 phy_data; 2413 2414 if (hw->mac.type != e1000_pchlan) 2415 return 0; 2416 2417 /* Set MDIO slow mode before any other MDIO access */ 2418 if (hw->phy.type == e1000_phy_82577) { 2419 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2420 if (ret_val) 2421 return ret_val; 2422 } 2423 2424 if (((hw->phy.type == e1000_phy_82577) && 2425 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2426 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2427 /* Disable generation of early preamble */ 2428 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2429 if (ret_val) 2430 return ret_val; 2431 2432 /* Preamble tuning for SSC */ 2433 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2434 if (ret_val) 2435 return ret_val; 2436 } 2437 2438 if (hw->phy.type == e1000_phy_82578) { 2439 /* Return registers to default by doing a soft reset then 2440 * writing 0x3140 to the control register. 2441 */ 2442 if (hw->phy.revision < 2) { 2443 e1000e_phy_sw_reset(hw); 2444 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2445 if (ret_val) 2446 return ret_val; 2447 } 2448 } 2449 2450 /* Select page 0 */ 2451 ret_val = hw->phy.ops.acquire(hw); 2452 if (ret_val) 2453 return ret_val; 2454 2455 hw->phy.addr = 1; 2456 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2457 hw->phy.ops.release(hw); 2458 if (ret_val) 2459 return ret_val; 2460 2461 /* Configure the K1 Si workaround during phy reset assuming there is 2462 * link so that it disables K1 if link is in 1Gbps. 2463 */ 2464 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2465 if (ret_val) 2466 return ret_val; 2467 2468 /* Workaround for link disconnects on a busy hub in half duplex */ 2469 ret_val = hw->phy.ops.acquire(hw); 2470 if (ret_val) 2471 return ret_val; 2472 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2473 if (ret_val) 2474 goto release; 2475 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2476 if (ret_val) 2477 goto release; 2478 2479 /* set MSE higher to enable link to stay up when noise is high */ 2480 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2481 release: 2482 hw->phy.ops.release(hw); 2483 2484 return ret_val; 2485 } 2486 2487 /** 2488 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2489 * @hw: pointer to the HW structure 2490 **/ 2491 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2492 { 2493 u32 mac_reg; 2494 u16 i, phy_reg = 0; 2495 s32 ret_val; 2496 2497 ret_val = hw->phy.ops.acquire(hw); 2498 if (ret_val) 2499 return; 2500 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2501 if (ret_val) 2502 goto release; 2503 2504 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2505 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2506 mac_reg = er32(RAL(i)); 2507 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2508 (u16)(mac_reg & 0xFFFF)); 2509 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2510 (u16)((mac_reg >> 16) & 0xFFFF)); 2511 2512 mac_reg = er32(RAH(i)); 2513 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2514 (u16)(mac_reg & 0xFFFF)); 2515 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2516 (u16)((mac_reg & E1000_RAH_AV) 2517 >> 16)); 2518 } 2519 2520 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2521 2522 release: 2523 hw->phy.ops.release(hw); 2524 } 2525 2526 /** 2527 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2528 * with 82579 PHY 2529 * @hw: pointer to the HW structure 2530 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2531 **/ 2532 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2533 { 2534 s32 ret_val = 0; 2535 u16 phy_reg, data; 2536 u32 mac_reg; 2537 u16 i; 2538 2539 if (hw->mac.type < e1000_pch2lan) 2540 return 0; 2541 2542 /* disable Rx path while enabling/disabling workaround */ 2543 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2544 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2545 if (ret_val) 2546 return ret_val; 2547 2548 if (enable) { 2549 /* Write Rx addresses (rar_entry_count for RAL/H, and 2550 * SHRAL/H) and initial CRC values to the MAC 2551 */ 2552 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2553 u8 mac_addr[ETH_ALEN] = { 0 }; 2554 u32 addr_high, addr_low; 2555 2556 addr_high = er32(RAH(i)); 2557 if (!(addr_high & E1000_RAH_AV)) 2558 continue; 2559 addr_low = er32(RAL(i)); 2560 mac_addr[0] = (addr_low & 0xFF); 2561 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2562 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2563 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2564 mac_addr[4] = (addr_high & 0xFF); 2565 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2566 2567 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2568 } 2569 2570 /* Write Rx addresses to the PHY */ 2571 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2572 2573 /* Enable jumbo frame workaround in the MAC */ 2574 mac_reg = er32(FFLT_DBG); 2575 mac_reg &= ~BIT(14); 2576 mac_reg |= (7 << 15); 2577 ew32(FFLT_DBG, mac_reg); 2578 2579 mac_reg = er32(RCTL); 2580 mac_reg |= E1000_RCTL_SECRC; 2581 ew32(RCTL, mac_reg); 2582 2583 ret_val = e1000e_read_kmrn_reg(hw, 2584 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2585 &data); 2586 if (ret_val) 2587 return ret_val; 2588 ret_val = e1000e_write_kmrn_reg(hw, 2589 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2590 data | BIT(0)); 2591 if (ret_val) 2592 return ret_val; 2593 ret_val = e1000e_read_kmrn_reg(hw, 2594 E1000_KMRNCTRLSTA_HD_CTRL, 2595 &data); 2596 if (ret_val) 2597 return ret_val; 2598 data &= ~(0xF << 8); 2599 data |= (0xB << 8); 2600 ret_val = e1000e_write_kmrn_reg(hw, 2601 E1000_KMRNCTRLSTA_HD_CTRL, 2602 data); 2603 if (ret_val) 2604 return ret_val; 2605 2606 /* Enable jumbo frame workaround in the PHY */ 2607 e1e_rphy(hw, PHY_REG(769, 23), &data); 2608 data &= ~(0x7F << 5); 2609 data |= (0x37 << 5); 2610 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2611 if (ret_val) 2612 return ret_val; 2613 e1e_rphy(hw, PHY_REG(769, 16), &data); 2614 data &= ~BIT(13); 2615 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2616 if (ret_val) 2617 return ret_val; 2618 e1e_rphy(hw, PHY_REG(776, 20), &data); 2619 data &= ~(0x3FF << 2); 2620 data |= (E1000_TX_PTR_GAP << 2); 2621 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2622 if (ret_val) 2623 return ret_val; 2624 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2625 if (ret_val) 2626 return ret_val; 2627 e1e_rphy(hw, HV_PM_CTRL, &data); 2628 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2629 if (ret_val) 2630 return ret_val; 2631 } else { 2632 /* Write MAC register values back to h/w defaults */ 2633 mac_reg = er32(FFLT_DBG); 2634 mac_reg &= ~(0xF << 14); 2635 ew32(FFLT_DBG, mac_reg); 2636 2637 mac_reg = er32(RCTL); 2638 mac_reg &= ~E1000_RCTL_SECRC; 2639 ew32(RCTL, mac_reg); 2640 2641 ret_val = e1000e_read_kmrn_reg(hw, 2642 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2643 &data); 2644 if (ret_val) 2645 return ret_val; 2646 ret_val = e1000e_write_kmrn_reg(hw, 2647 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2648 data & ~BIT(0)); 2649 if (ret_val) 2650 return ret_val; 2651 ret_val = e1000e_read_kmrn_reg(hw, 2652 E1000_KMRNCTRLSTA_HD_CTRL, 2653 &data); 2654 if (ret_val) 2655 return ret_val; 2656 data &= ~(0xF << 8); 2657 data |= (0xB << 8); 2658 ret_val = e1000e_write_kmrn_reg(hw, 2659 E1000_KMRNCTRLSTA_HD_CTRL, 2660 data); 2661 if (ret_val) 2662 return ret_val; 2663 2664 /* Write PHY register values back to h/w defaults */ 2665 e1e_rphy(hw, PHY_REG(769, 23), &data); 2666 data &= ~(0x7F << 5); 2667 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2668 if (ret_val) 2669 return ret_val; 2670 e1e_rphy(hw, PHY_REG(769, 16), &data); 2671 data |= BIT(13); 2672 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2673 if (ret_val) 2674 return ret_val; 2675 e1e_rphy(hw, PHY_REG(776, 20), &data); 2676 data &= ~(0x3FF << 2); 2677 data |= (0x8 << 2); 2678 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2679 if (ret_val) 2680 return ret_val; 2681 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2682 if (ret_val) 2683 return ret_val; 2684 e1e_rphy(hw, HV_PM_CTRL, &data); 2685 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2686 if (ret_val) 2687 return ret_val; 2688 } 2689 2690 /* re-enable Rx path after enabling/disabling workaround */ 2691 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2692 } 2693 2694 /** 2695 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2696 * done after every PHY reset. 2697 **/ 2698 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2699 { 2700 s32 ret_val = 0; 2701 2702 if (hw->mac.type != e1000_pch2lan) 2703 return 0; 2704 2705 /* Set MDIO slow mode before any other MDIO access */ 2706 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2707 if (ret_val) 2708 return ret_val; 2709 2710 ret_val = hw->phy.ops.acquire(hw); 2711 if (ret_val) 2712 return ret_val; 2713 /* set MSE higher to enable link to stay up when noise is high */ 2714 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2715 if (ret_val) 2716 goto release; 2717 /* drop link after 5 times MSE threshold was reached */ 2718 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2719 release: 2720 hw->phy.ops.release(hw); 2721 2722 return ret_val; 2723 } 2724 2725 /** 2726 * e1000_k1_gig_workaround_lv - K1 Si workaround 2727 * @hw: pointer to the HW structure 2728 * 2729 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2730 * Disable K1 in 1000Mbps and 100Mbps 2731 **/ 2732 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2733 { 2734 s32 ret_val = 0; 2735 u16 status_reg = 0; 2736 2737 if (hw->mac.type != e1000_pch2lan) 2738 return 0; 2739 2740 /* Set K1 beacon duration based on 10Mbs speed */ 2741 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2742 if (ret_val) 2743 return ret_val; 2744 2745 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2746 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2747 if (status_reg & 2748 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2749 u16 pm_phy_reg; 2750 2751 /* LV 1G/100 Packet drop issue wa */ 2752 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2753 if (ret_val) 2754 return ret_val; 2755 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2756 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2757 if (ret_val) 2758 return ret_val; 2759 } else { 2760 u32 mac_reg; 2761 2762 mac_reg = er32(FEXTNVM4); 2763 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2764 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2765 ew32(FEXTNVM4, mac_reg); 2766 } 2767 } 2768 2769 return ret_val; 2770 } 2771 2772 /** 2773 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2774 * @hw: pointer to the HW structure 2775 * @gate: boolean set to true to gate, false to ungate 2776 * 2777 * Gate/ungate the automatic PHY configuration via hardware; perform 2778 * the configuration via software instead. 2779 **/ 2780 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2781 { 2782 u32 extcnf_ctrl; 2783 2784 if (hw->mac.type < e1000_pch2lan) 2785 return; 2786 2787 extcnf_ctrl = er32(EXTCNF_CTRL); 2788 2789 if (gate) 2790 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2791 else 2792 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2793 2794 ew32(EXTCNF_CTRL, extcnf_ctrl); 2795 } 2796 2797 /** 2798 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2799 * @hw: pointer to the HW structure 2800 * 2801 * Check the appropriate indication the MAC has finished configuring the 2802 * PHY after a software reset. 2803 **/ 2804 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2805 { 2806 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2807 2808 /* Wait for basic configuration completes before proceeding */ 2809 do { 2810 data = er32(STATUS); 2811 data &= E1000_STATUS_LAN_INIT_DONE; 2812 usleep_range(100, 200); 2813 } while ((!data) && --loop); 2814 2815 /* If basic configuration is incomplete before the above loop 2816 * count reaches 0, loading the configuration from NVM will 2817 * leave the PHY in a bad state possibly resulting in no link. 2818 */ 2819 if (loop == 0) 2820 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2821 2822 /* Clear the Init Done bit for the next init event */ 2823 data = er32(STATUS); 2824 data &= ~E1000_STATUS_LAN_INIT_DONE; 2825 ew32(STATUS, data); 2826 } 2827 2828 /** 2829 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2830 * @hw: pointer to the HW structure 2831 **/ 2832 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2833 { 2834 s32 ret_val = 0; 2835 u16 reg; 2836 2837 if (hw->phy.ops.check_reset_block(hw)) 2838 return 0; 2839 2840 /* Allow time for h/w to get to quiescent state after reset */ 2841 usleep_range(10000, 20000); 2842 2843 /* Perform any necessary post-reset workarounds */ 2844 switch (hw->mac.type) { 2845 case e1000_pchlan: 2846 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2847 if (ret_val) 2848 return ret_val; 2849 break; 2850 case e1000_pch2lan: 2851 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2852 if (ret_val) 2853 return ret_val; 2854 break; 2855 default: 2856 break; 2857 } 2858 2859 /* Clear the host wakeup bit after lcd reset */ 2860 if (hw->mac.type >= e1000_pchlan) { 2861 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2862 reg &= ~BM_WUC_HOST_WU_BIT; 2863 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2864 } 2865 2866 /* Configure the LCD with the extended configuration region in NVM */ 2867 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2868 if (ret_val) 2869 return ret_val; 2870 2871 /* Configure the LCD with the OEM bits in NVM */ 2872 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2873 2874 if (hw->mac.type == e1000_pch2lan) { 2875 /* Ungate automatic PHY configuration on non-managed 82579 */ 2876 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2877 usleep_range(10000, 20000); 2878 e1000_gate_hw_phy_config_ich8lan(hw, false); 2879 } 2880 2881 /* Set EEE LPI Update Timer to 200usec */ 2882 ret_val = hw->phy.ops.acquire(hw); 2883 if (ret_val) 2884 return ret_val; 2885 ret_val = e1000_write_emi_reg_locked(hw, 2886 I82579_LPI_UPDATE_TIMER, 2887 0x1387); 2888 hw->phy.ops.release(hw); 2889 } 2890 2891 return ret_val; 2892 } 2893 2894 /** 2895 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2896 * @hw: pointer to the HW structure 2897 * 2898 * Resets the PHY 2899 * This is a function pointer entry point called by drivers 2900 * or other shared routines. 2901 **/ 2902 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2903 { 2904 s32 ret_val = 0; 2905 2906 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2907 if ((hw->mac.type == e1000_pch2lan) && 2908 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2909 e1000_gate_hw_phy_config_ich8lan(hw, true); 2910 2911 ret_val = e1000e_phy_hw_reset_generic(hw); 2912 if (ret_val) 2913 return ret_val; 2914 2915 return e1000_post_phy_reset_ich8lan(hw); 2916 } 2917 2918 /** 2919 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2920 * @hw: pointer to the HW structure 2921 * @active: true to enable LPLU, false to disable 2922 * 2923 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2924 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2925 * the phy speed. This function will manually set the LPLU bit and restart 2926 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2927 * since it configures the same bit. 2928 **/ 2929 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2930 { 2931 s32 ret_val; 2932 u16 oem_reg; 2933 2934 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2935 if (ret_val) 2936 return ret_val; 2937 2938 if (active) 2939 oem_reg |= HV_OEM_BITS_LPLU; 2940 else 2941 oem_reg &= ~HV_OEM_BITS_LPLU; 2942 2943 if (!hw->phy.ops.check_reset_block(hw)) 2944 oem_reg |= HV_OEM_BITS_RESTART_AN; 2945 2946 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2947 } 2948 2949 /** 2950 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2951 * @hw: pointer to the HW structure 2952 * @active: true to enable LPLU, false to disable 2953 * 2954 * Sets the LPLU D0 state according to the active flag. When 2955 * activating LPLU this function also disables smart speed 2956 * and vice versa. LPLU will not be activated unless the 2957 * device autonegotiation advertisement meets standards of 2958 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2959 * This is a function pointer entry point only called by 2960 * PHY setup routines. 2961 **/ 2962 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2963 { 2964 struct e1000_phy_info *phy = &hw->phy; 2965 u32 phy_ctrl; 2966 s32 ret_val = 0; 2967 u16 data; 2968 2969 if (phy->type == e1000_phy_ife) 2970 return 0; 2971 2972 phy_ctrl = er32(PHY_CTRL); 2973 2974 if (active) { 2975 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2976 ew32(PHY_CTRL, phy_ctrl); 2977 2978 if (phy->type != e1000_phy_igp_3) 2979 return 0; 2980 2981 /* Call gig speed drop workaround on LPLU before accessing 2982 * any PHY registers 2983 */ 2984 if (hw->mac.type == e1000_ich8lan) 2985 e1000e_gig_downshift_workaround_ich8lan(hw); 2986 2987 /* When LPLU is enabled, we should disable SmartSpeed */ 2988 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2989 if (ret_val) 2990 return ret_val; 2991 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2992 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2993 if (ret_val) 2994 return ret_val; 2995 } else { 2996 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2997 ew32(PHY_CTRL, phy_ctrl); 2998 2999 if (phy->type != e1000_phy_igp_3) 3000 return 0; 3001 3002 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3003 * during Dx states where the power conservation is most 3004 * important. During driver activity we should enable 3005 * SmartSpeed, so performance is maintained. 3006 */ 3007 if (phy->smart_speed == e1000_smart_speed_on) { 3008 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3009 &data); 3010 if (ret_val) 3011 return ret_val; 3012 3013 data |= IGP01E1000_PSCFR_SMART_SPEED; 3014 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3015 data); 3016 if (ret_val) 3017 return ret_val; 3018 } else if (phy->smart_speed == e1000_smart_speed_off) { 3019 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3020 &data); 3021 if (ret_val) 3022 return ret_val; 3023 3024 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3025 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3026 data); 3027 if (ret_val) 3028 return ret_val; 3029 } 3030 } 3031 3032 return 0; 3033 } 3034 3035 /** 3036 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3037 * @hw: pointer to the HW structure 3038 * @active: true to enable LPLU, false to disable 3039 * 3040 * Sets the LPLU D3 state according to the active flag. When 3041 * activating LPLU this function also disables smart speed 3042 * and vice versa. LPLU will not be activated unless the 3043 * device autonegotiation advertisement meets standards of 3044 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3045 * This is a function pointer entry point only called by 3046 * PHY setup routines. 3047 **/ 3048 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3049 { 3050 struct e1000_phy_info *phy = &hw->phy; 3051 u32 phy_ctrl; 3052 s32 ret_val = 0; 3053 u16 data; 3054 3055 phy_ctrl = er32(PHY_CTRL); 3056 3057 if (!active) { 3058 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3059 ew32(PHY_CTRL, phy_ctrl); 3060 3061 if (phy->type != e1000_phy_igp_3) 3062 return 0; 3063 3064 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3065 * during Dx states where the power conservation is most 3066 * important. During driver activity we should enable 3067 * SmartSpeed, so performance is maintained. 3068 */ 3069 if (phy->smart_speed == e1000_smart_speed_on) { 3070 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3071 &data); 3072 if (ret_val) 3073 return ret_val; 3074 3075 data |= IGP01E1000_PSCFR_SMART_SPEED; 3076 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3077 data); 3078 if (ret_val) 3079 return ret_val; 3080 } else if (phy->smart_speed == e1000_smart_speed_off) { 3081 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3082 &data); 3083 if (ret_val) 3084 return ret_val; 3085 3086 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3087 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3088 data); 3089 if (ret_val) 3090 return ret_val; 3091 } 3092 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3093 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3094 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3095 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3096 ew32(PHY_CTRL, phy_ctrl); 3097 3098 if (phy->type != e1000_phy_igp_3) 3099 return 0; 3100 3101 /* Call gig speed drop workaround on LPLU before accessing 3102 * any PHY registers 3103 */ 3104 if (hw->mac.type == e1000_ich8lan) 3105 e1000e_gig_downshift_workaround_ich8lan(hw); 3106 3107 /* When LPLU is enabled, we should disable SmartSpeed */ 3108 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3109 if (ret_val) 3110 return ret_val; 3111 3112 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3113 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3114 } 3115 3116 return ret_val; 3117 } 3118 3119 /** 3120 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3121 * @hw: pointer to the HW structure 3122 * @bank: pointer to the variable that returns the active bank 3123 * 3124 * Reads signature byte from the NVM using the flash access registers. 3125 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3126 **/ 3127 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3128 { 3129 u32 eecd; 3130 struct e1000_nvm_info *nvm = &hw->nvm; 3131 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3132 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3133 u32 nvm_dword = 0; 3134 u8 sig_byte = 0; 3135 s32 ret_val; 3136 3137 switch (hw->mac.type) { 3138 case e1000_pch_spt: 3139 case e1000_pch_cnp: 3140 bank1_offset = nvm->flash_bank_size; 3141 act_offset = E1000_ICH_NVM_SIG_WORD; 3142 3143 /* set bank to 0 in case flash read fails */ 3144 *bank = 0; 3145 3146 /* Check bank 0 */ 3147 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3148 &nvm_dword); 3149 if (ret_val) 3150 return ret_val; 3151 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3152 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3153 E1000_ICH_NVM_SIG_VALUE) { 3154 *bank = 0; 3155 return 0; 3156 } 3157 3158 /* Check bank 1 */ 3159 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3160 bank1_offset, 3161 &nvm_dword); 3162 if (ret_val) 3163 return ret_val; 3164 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3165 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3166 E1000_ICH_NVM_SIG_VALUE) { 3167 *bank = 1; 3168 return 0; 3169 } 3170 3171 e_dbg("ERROR: No valid NVM bank present\n"); 3172 return -E1000_ERR_NVM; 3173 case e1000_ich8lan: 3174 case e1000_ich9lan: 3175 eecd = er32(EECD); 3176 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3177 E1000_EECD_SEC1VAL_VALID_MASK) { 3178 if (eecd & E1000_EECD_SEC1VAL) 3179 *bank = 1; 3180 else 3181 *bank = 0; 3182 3183 return 0; 3184 } 3185 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3186 /* fall-thru */ 3187 default: 3188 /* set bank to 0 in case flash read fails */ 3189 *bank = 0; 3190 3191 /* Check bank 0 */ 3192 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3193 &sig_byte); 3194 if (ret_val) 3195 return ret_val; 3196 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3197 E1000_ICH_NVM_SIG_VALUE) { 3198 *bank = 0; 3199 return 0; 3200 } 3201 3202 /* Check bank 1 */ 3203 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3204 bank1_offset, 3205 &sig_byte); 3206 if (ret_val) 3207 return ret_val; 3208 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3209 E1000_ICH_NVM_SIG_VALUE) { 3210 *bank = 1; 3211 return 0; 3212 } 3213 3214 e_dbg("ERROR: No valid NVM bank present\n"); 3215 return -E1000_ERR_NVM; 3216 } 3217 } 3218 3219 /** 3220 * e1000_read_nvm_spt - NVM access for SPT 3221 * @hw: pointer to the HW structure 3222 * @offset: The offset (in bytes) of the word(s) to read. 3223 * @words: Size of data to read in words. 3224 * @data: pointer to the word(s) to read at offset. 3225 * 3226 * Reads a word(s) from the NVM 3227 **/ 3228 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3229 u16 *data) 3230 { 3231 struct e1000_nvm_info *nvm = &hw->nvm; 3232 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3233 u32 act_offset; 3234 s32 ret_val = 0; 3235 u32 bank = 0; 3236 u32 dword = 0; 3237 u16 offset_to_read; 3238 u16 i; 3239 3240 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3241 (words == 0)) { 3242 e_dbg("nvm parameter(s) out of bounds\n"); 3243 ret_val = -E1000_ERR_NVM; 3244 goto out; 3245 } 3246 3247 nvm->ops.acquire(hw); 3248 3249 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3250 if (ret_val) { 3251 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3252 bank = 0; 3253 } 3254 3255 act_offset = (bank) ? nvm->flash_bank_size : 0; 3256 act_offset += offset; 3257 3258 ret_val = 0; 3259 3260 for (i = 0; i < words; i += 2) { 3261 if (words - i == 1) { 3262 if (dev_spec->shadow_ram[offset + i].modified) { 3263 data[i] = 3264 dev_spec->shadow_ram[offset + i].value; 3265 } else { 3266 offset_to_read = act_offset + i - 3267 ((act_offset + i) % 2); 3268 ret_val = 3269 e1000_read_flash_dword_ich8lan(hw, 3270 offset_to_read, 3271 &dword); 3272 if (ret_val) 3273 break; 3274 if ((act_offset + i) % 2 == 0) 3275 data[i] = (u16)(dword & 0xFFFF); 3276 else 3277 data[i] = (u16)((dword >> 16) & 0xFFFF); 3278 } 3279 } else { 3280 offset_to_read = act_offset + i; 3281 if (!(dev_spec->shadow_ram[offset + i].modified) || 3282 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3283 ret_val = 3284 e1000_read_flash_dword_ich8lan(hw, 3285 offset_to_read, 3286 &dword); 3287 if (ret_val) 3288 break; 3289 } 3290 if (dev_spec->shadow_ram[offset + i].modified) 3291 data[i] = 3292 dev_spec->shadow_ram[offset + i].value; 3293 else 3294 data[i] = (u16)(dword & 0xFFFF); 3295 if (dev_spec->shadow_ram[offset + i].modified) 3296 data[i + 1] = 3297 dev_spec->shadow_ram[offset + i + 1].value; 3298 else 3299 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3300 } 3301 } 3302 3303 nvm->ops.release(hw); 3304 3305 out: 3306 if (ret_val) 3307 e_dbg("NVM read error: %d\n", ret_val); 3308 3309 return ret_val; 3310 } 3311 3312 /** 3313 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3314 * @hw: pointer to the HW structure 3315 * @offset: The offset (in bytes) of the word(s) to read. 3316 * @words: Size of data to read in words 3317 * @data: Pointer to the word(s) to read at offset. 3318 * 3319 * Reads a word(s) from the NVM using the flash access registers. 3320 **/ 3321 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3322 u16 *data) 3323 { 3324 struct e1000_nvm_info *nvm = &hw->nvm; 3325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3326 u32 act_offset; 3327 s32 ret_val = 0; 3328 u32 bank = 0; 3329 u16 i, word; 3330 3331 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3332 (words == 0)) { 3333 e_dbg("nvm parameter(s) out of bounds\n"); 3334 ret_val = -E1000_ERR_NVM; 3335 goto out; 3336 } 3337 3338 nvm->ops.acquire(hw); 3339 3340 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3341 if (ret_val) { 3342 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3343 bank = 0; 3344 } 3345 3346 act_offset = (bank) ? nvm->flash_bank_size : 0; 3347 act_offset += offset; 3348 3349 ret_val = 0; 3350 for (i = 0; i < words; i++) { 3351 if (dev_spec->shadow_ram[offset + i].modified) { 3352 data[i] = dev_spec->shadow_ram[offset + i].value; 3353 } else { 3354 ret_val = e1000_read_flash_word_ich8lan(hw, 3355 act_offset + i, 3356 &word); 3357 if (ret_val) 3358 break; 3359 data[i] = word; 3360 } 3361 } 3362 3363 nvm->ops.release(hw); 3364 3365 out: 3366 if (ret_val) 3367 e_dbg("NVM read error: %d\n", ret_val); 3368 3369 return ret_val; 3370 } 3371 3372 /** 3373 * e1000_flash_cycle_init_ich8lan - Initialize flash 3374 * @hw: pointer to the HW structure 3375 * 3376 * This function does initial flash setup so that a new read/write/erase cycle 3377 * can be started. 3378 **/ 3379 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3380 { 3381 union ich8_hws_flash_status hsfsts; 3382 s32 ret_val = -E1000_ERR_NVM; 3383 3384 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3385 3386 /* Check if the flash descriptor is valid */ 3387 if (!hsfsts.hsf_status.fldesvalid) { 3388 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3389 return -E1000_ERR_NVM; 3390 } 3391 3392 /* Clear FCERR and DAEL in hw status by writing 1 */ 3393 hsfsts.hsf_status.flcerr = 1; 3394 hsfsts.hsf_status.dael = 1; 3395 if (hw->mac.type >= e1000_pch_spt) 3396 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3397 else 3398 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3399 3400 /* Either we should have a hardware SPI cycle in progress 3401 * bit to check against, in order to start a new cycle or 3402 * FDONE bit should be changed in the hardware so that it 3403 * is 1 after hardware reset, which can then be used as an 3404 * indication whether a cycle is in progress or has been 3405 * completed. 3406 */ 3407 3408 if (!hsfsts.hsf_status.flcinprog) { 3409 /* There is no cycle running at present, 3410 * so we can start a cycle. 3411 * Begin by setting Flash Cycle Done. 3412 */ 3413 hsfsts.hsf_status.flcdone = 1; 3414 if (hw->mac.type >= e1000_pch_spt) 3415 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3416 else 3417 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3418 ret_val = 0; 3419 } else { 3420 s32 i; 3421 3422 /* Otherwise poll for sometime so the current 3423 * cycle has a chance to end before giving up. 3424 */ 3425 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3426 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3427 if (!hsfsts.hsf_status.flcinprog) { 3428 ret_val = 0; 3429 break; 3430 } 3431 udelay(1); 3432 } 3433 if (!ret_val) { 3434 /* Successful in waiting for previous cycle to timeout, 3435 * now set the Flash Cycle Done. 3436 */ 3437 hsfsts.hsf_status.flcdone = 1; 3438 if (hw->mac.type >= e1000_pch_spt) 3439 ew32flash(ICH_FLASH_HSFSTS, 3440 hsfsts.regval & 0xFFFF); 3441 else 3442 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3443 } else { 3444 e_dbg("Flash controller busy, cannot get access\n"); 3445 } 3446 } 3447 3448 return ret_val; 3449 } 3450 3451 /** 3452 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3453 * @hw: pointer to the HW structure 3454 * @timeout: maximum time to wait for completion 3455 * 3456 * This function starts a flash cycle and waits for its completion. 3457 **/ 3458 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3459 { 3460 union ich8_hws_flash_ctrl hsflctl; 3461 union ich8_hws_flash_status hsfsts; 3462 u32 i = 0; 3463 3464 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3465 if (hw->mac.type >= e1000_pch_spt) 3466 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3467 else 3468 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3469 hsflctl.hsf_ctrl.flcgo = 1; 3470 3471 if (hw->mac.type >= e1000_pch_spt) 3472 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3473 else 3474 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3475 3476 /* wait till FDONE bit is set to 1 */ 3477 do { 3478 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3479 if (hsfsts.hsf_status.flcdone) 3480 break; 3481 udelay(1); 3482 } while (i++ < timeout); 3483 3484 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3485 return 0; 3486 3487 return -E1000_ERR_NVM; 3488 } 3489 3490 /** 3491 * e1000_read_flash_dword_ich8lan - Read dword from flash 3492 * @hw: pointer to the HW structure 3493 * @offset: offset to data location 3494 * @data: pointer to the location for storing the data 3495 * 3496 * Reads the flash dword at offset into data. Offset is converted 3497 * to bytes before read. 3498 **/ 3499 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3500 u32 *data) 3501 { 3502 /* Must convert word offset into bytes. */ 3503 offset <<= 1; 3504 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3505 } 3506 3507 /** 3508 * e1000_read_flash_word_ich8lan - Read word from flash 3509 * @hw: pointer to the HW structure 3510 * @offset: offset to data location 3511 * @data: pointer to the location for storing the data 3512 * 3513 * Reads the flash word at offset into data. Offset is converted 3514 * to bytes before read. 3515 **/ 3516 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3517 u16 *data) 3518 { 3519 /* Must convert offset into bytes. */ 3520 offset <<= 1; 3521 3522 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3523 } 3524 3525 /** 3526 * e1000_read_flash_byte_ich8lan - Read byte from flash 3527 * @hw: pointer to the HW structure 3528 * @offset: The offset of the byte to read. 3529 * @data: Pointer to a byte to store the value read. 3530 * 3531 * Reads a single byte from the NVM using the flash access registers. 3532 **/ 3533 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3534 u8 *data) 3535 { 3536 s32 ret_val; 3537 u16 word = 0; 3538 3539 /* In SPT, only 32 bits access is supported, 3540 * so this function should not be called. 3541 */ 3542 if (hw->mac.type >= e1000_pch_spt) 3543 return -E1000_ERR_NVM; 3544 else 3545 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3546 3547 if (ret_val) 3548 return ret_val; 3549 3550 *data = (u8)word; 3551 3552 return 0; 3553 } 3554 3555 /** 3556 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3557 * @hw: pointer to the HW structure 3558 * @offset: The offset (in bytes) of the byte or word to read. 3559 * @size: Size of data to read, 1=byte 2=word 3560 * @data: Pointer to the word to store the value read. 3561 * 3562 * Reads a byte or word from the NVM using the flash access registers. 3563 **/ 3564 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3565 u8 size, u16 *data) 3566 { 3567 union ich8_hws_flash_status hsfsts; 3568 union ich8_hws_flash_ctrl hsflctl; 3569 u32 flash_linear_addr; 3570 u32 flash_data = 0; 3571 s32 ret_val = -E1000_ERR_NVM; 3572 u8 count = 0; 3573 3574 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3575 return -E1000_ERR_NVM; 3576 3577 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3578 hw->nvm.flash_base_addr); 3579 3580 do { 3581 udelay(1); 3582 /* Steps */ 3583 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3584 if (ret_val) 3585 break; 3586 3587 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3588 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3589 hsflctl.hsf_ctrl.fldbcount = size - 1; 3590 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3591 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3592 3593 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3594 3595 ret_val = 3596 e1000_flash_cycle_ich8lan(hw, 3597 ICH_FLASH_READ_COMMAND_TIMEOUT); 3598 3599 /* Check if FCERR is set to 1, if set to 1, clear it 3600 * and try the whole sequence a few more times, else 3601 * read in (shift in) the Flash Data0, the order is 3602 * least significant byte first msb to lsb 3603 */ 3604 if (!ret_val) { 3605 flash_data = er32flash(ICH_FLASH_FDATA0); 3606 if (size == 1) 3607 *data = (u8)(flash_data & 0x000000FF); 3608 else if (size == 2) 3609 *data = (u16)(flash_data & 0x0000FFFF); 3610 break; 3611 } else { 3612 /* If we've gotten here, then things are probably 3613 * completely hosed, but if the error condition is 3614 * detected, it won't hurt to give it another try... 3615 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3616 */ 3617 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3618 if (hsfsts.hsf_status.flcerr) { 3619 /* Repeat for some time before giving up. */ 3620 continue; 3621 } else if (!hsfsts.hsf_status.flcdone) { 3622 e_dbg("Timeout error - flash cycle did not complete.\n"); 3623 break; 3624 } 3625 } 3626 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3627 3628 return ret_val; 3629 } 3630 3631 /** 3632 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3633 * @hw: pointer to the HW structure 3634 * @offset: The offset (in bytes) of the dword to read. 3635 * @data: Pointer to the dword to store the value read. 3636 * 3637 * Reads a byte or word from the NVM using the flash access registers. 3638 **/ 3639 3640 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3641 u32 *data) 3642 { 3643 union ich8_hws_flash_status hsfsts; 3644 union ich8_hws_flash_ctrl hsflctl; 3645 u32 flash_linear_addr; 3646 s32 ret_val = -E1000_ERR_NVM; 3647 u8 count = 0; 3648 3649 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3650 return -E1000_ERR_NVM; 3651 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3652 hw->nvm.flash_base_addr); 3653 3654 do { 3655 udelay(1); 3656 /* Steps */ 3657 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3658 if (ret_val) 3659 break; 3660 /* In SPT, This register is in Lan memory space, not flash. 3661 * Therefore, only 32 bit access is supported 3662 */ 3663 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3664 3665 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3666 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3667 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3668 /* In SPT, This register is in Lan memory space, not flash. 3669 * Therefore, only 32 bit access is supported 3670 */ 3671 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3672 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3673 3674 ret_val = 3675 e1000_flash_cycle_ich8lan(hw, 3676 ICH_FLASH_READ_COMMAND_TIMEOUT); 3677 3678 /* Check if FCERR is set to 1, if set to 1, clear it 3679 * and try the whole sequence a few more times, else 3680 * read in (shift in) the Flash Data0, the order is 3681 * least significant byte first msb to lsb 3682 */ 3683 if (!ret_val) { 3684 *data = er32flash(ICH_FLASH_FDATA0); 3685 break; 3686 } else { 3687 /* If we've gotten here, then things are probably 3688 * completely hosed, but if the error condition is 3689 * detected, it won't hurt to give it another try... 3690 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3691 */ 3692 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3693 if (hsfsts.hsf_status.flcerr) { 3694 /* Repeat for some time before giving up. */ 3695 continue; 3696 } else if (!hsfsts.hsf_status.flcdone) { 3697 e_dbg("Timeout error - flash cycle did not complete.\n"); 3698 break; 3699 } 3700 } 3701 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3702 3703 return ret_val; 3704 } 3705 3706 /** 3707 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3708 * @hw: pointer to the HW structure 3709 * @offset: The offset (in bytes) of the word(s) to write. 3710 * @words: Size of data to write in words 3711 * @data: Pointer to the word(s) to write at offset. 3712 * 3713 * Writes a byte or word to the NVM using the flash access registers. 3714 **/ 3715 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3716 u16 *data) 3717 { 3718 struct e1000_nvm_info *nvm = &hw->nvm; 3719 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3720 u16 i; 3721 3722 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3723 (words == 0)) { 3724 e_dbg("nvm parameter(s) out of bounds\n"); 3725 return -E1000_ERR_NVM; 3726 } 3727 3728 nvm->ops.acquire(hw); 3729 3730 for (i = 0; i < words; i++) { 3731 dev_spec->shadow_ram[offset + i].modified = true; 3732 dev_spec->shadow_ram[offset + i].value = data[i]; 3733 } 3734 3735 nvm->ops.release(hw); 3736 3737 return 0; 3738 } 3739 3740 /** 3741 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3742 * @hw: pointer to the HW structure 3743 * 3744 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3745 * which writes the checksum to the shadow ram. The changes in the shadow 3746 * ram are then committed to the EEPROM by processing each bank at a time 3747 * checking for the modified bit and writing only the pending changes. 3748 * After a successful commit, the shadow ram is cleared and is ready for 3749 * future writes. 3750 **/ 3751 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3752 { 3753 struct e1000_nvm_info *nvm = &hw->nvm; 3754 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3755 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3756 s32 ret_val; 3757 u32 dword = 0; 3758 3759 ret_val = e1000e_update_nvm_checksum_generic(hw); 3760 if (ret_val) 3761 goto out; 3762 3763 if (nvm->type != e1000_nvm_flash_sw) 3764 goto out; 3765 3766 nvm->ops.acquire(hw); 3767 3768 /* We're writing to the opposite bank so if we're on bank 1, 3769 * write to bank 0 etc. We also need to erase the segment that 3770 * is going to be written 3771 */ 3772 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3773 if (ret_val) { 3774 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3775 bank = 0; 3776 } 3777 3778 if (bank == 0) { 3779 new_bank_offset = nvm->flash_bank_size; 3780 old_bank_offset = 0; 3781 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3782 if (ret_val) 3783 goto release; 3784 } else { 3785 old_bank_offset = nvm->flash_bank_size; 3786 new_bank_offset = 0; 3787 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3788 if (ret_val) 3789 goto release; 3790 } 3791 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3792 /* Determine whether to write the value stored 3793 * in the other NVM bank or a modified value stored 3794 * in the shadow RAM 3795 */ 3796 ret_val = e1000_read_flash_dword_ich8lan(hw, 3797 i + old_bank_offset, 3798 &dword); 3799 3800 if (dev_spec->shadow_ram[i].modified) { 3801 dword &= 0xffff0000; 3802 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3803 } 3804 if (dev_spec->shadow_ram[i + 1].modified) { 3805 dword &= 0x0000ffff; 3806 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3807 << 16); 3808 } 3809 if (ret_val) 3810 break; 3811 3812 /* If the word is 0x13, then make sure the signature bits 3813 * (15:14) are 11b until the commit has completed. 3814 * This will allow us to write 10b which indicates the 3815 * signature is valid. We want to do this after the write 3816 * has completed so that we don't mark the segment valid 3817 * while the write is still in progress 3818 */ 3819 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3820 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3821 3822 /* Convert offset to bytes. */ 3823 act_offset = (i + new_bank_offset) << 1; 3824 3825 usleep_range(100, 200); 3826 3827 /* Write the data to the new bank. Offset in words */ 3828 act_offset = i + new_bank_offset; 3829 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3830 dword); 3831 if (ret_val) 3832 break; 3833 } 3834 3835 /* Don't bother writing the segment valid bits if sector 3836 * programming failed. 3837 */ 3838 if (ret_val) { 3839 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3840 e_dbg("Flash commit failed.\n"); 3841 goto release; 3842 } 3843 3844 /* Finally validate the new segment by setting bit 15:14 3845 * to 10b in word 0x13 , this can be done without an 3846 * erase as well since these bits are 11 to start with 3847 * and we need to change bit 14 to 0b 3848 */ 3849 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3850 3851 /*offset in words but we read dword */ 3852 --act_offset; 3853 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3854 3855 if (ret_val) 3856 goto release; 3857 3858 dword &= 0xBFFFFFFF; 3859 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3860 3861 if (ret_val) 3862 goto release; 3863 3864 /* And invalidate the previously valid segment by setting 3865 * its signature word (0x13) high_byte to 0b. This can be 3866 * done without an erase because flash erase sets all bits 3867 * to 1's. We can write 1's to 0's without an erase 3868 */ 3869 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3870 3871 /* offset in words but we read dword */ 3872 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3873 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3874 3875 if (ret_val) 3876 goto release; 3877 3878 dword &= 0x00FFFFFF; 3879 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3880 3881 if (ret_val) 3882 goto release; 3883 3884 /* Great! Everything worked, we can now clear the cached entries. */ 3885 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3886 dev_spec->shadow_ram[i].modified = false; 3887 dev_spec->shadow_ram[i].value = 0xFFFF; 3888 } 3889 3890 release: 3891 nvm->ops.release(hw); 3892 3893 /* Reload the EEPROM, or else modifications will not appear 3894 * until after the next adapter reset. 3895 */ 3896 if (!ret_val) { 3897 nvm->ops.reload(hw); 3898 usleep_range(10000, 20000); 3899 } 3900 3901 out: 3902 if (ret_val) 3903 e_dbg("NVM update error: %d\n", ret_val); 3904 3905 return ret_val; 3906 } 3907 3908 /** 3909 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3910 * @hw: pointer to the HW structure 3911 * 3912 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3913 * which writes the checksum to the shadow ram. The changes in the shadow 3914 * ram are then committed to the EEPROM by processing each bank at a time 3915 * checking for the modified bit and writing only the pending changes. 3916 * After a successful commit, the shadow ram is cleared and is ready for 3917 * future writes. 3918 **/ 3919 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3920 { 3921 struct e1000_nvm_info *nvm = &hw->nvm; 3922 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3923 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3924 s32 ret_val; 3925 u16 data = 0; 3926 3927 ret_val = e1000e_update_nvm_checksum_generic(hw); 3928 if (ret_val) 3929 goto out; 3930 3931 if (nvm->type != e1000_nvm_flash_sw) 3932 goto out; 3933 3934 nvm->ops.acquire(hw); 3935 3936 /* We're writing to the opposite bank so if we're on bank 1, 3937 * write to bank 0 etc. We also need to erase the segment that 3938 * is going to be written 3939 */ 3940 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3941 if (ret_val) { 3942 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3943 bank = 0; 3944 } 3945 3946 if (bank == 0) { 3947 new_bank_offset = nvm->flash_bank_size; 3948 old_bank_offset = 0; 3949 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3950 if (ret_val) 3951 goto release; 3952 } else { 3953 old_bank_offset = nvm->flash_bank_size; 3954 new_bank_offset = 0; 3955 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3956 if (ret_val) 3957 goto release; 3958 } 3959 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3960 if (dev_spec->shadow_ram[i].modified) { 3961 data = dev_spec->shadow_ram[i].value; 3962 } else { 3963 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3964 old_bank_offset, 3965 &data); 3966 if (ret_val) 3967 break; 3968 } 3969 3970 /* If the word is 0x13, then make sure the signature bits 3971 * (15:14) are 11b until the commit has completed. 3972 * This will allow us to write 10b which indicates the 3973 * signature is valid. We want to do this after the write 3974 * has completed so that we don't mark the segment valid 3975 * while the write is still in progress 3976 */ 3977 if (i == E1000_ICH_NVM_SIG_WORD) 3978 data |= E1000_ICH_NVM_SIG_MASK; 3979 3980 /* Convert offset to bytes. */ 3981 act_offset = (i + new_bank_offset) << 1; 3982 3983 usleep_range(100, 200); 3984 /* Write the bytes to the new bank. */ 3985 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3986 act_offset, 3987 (u8)data); 3988 if (ret_val) 3989 break; 3990 3991 usleep_range(100, 200); 3992 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3993 act_offset + 1, 3994 (u8)(data >> 8)); 3995 if (ret_val) 3996 break; 3997 } 3998 3999 /* Don't bother writing the segment valid bits if sector 4000 * programming failed. 4001 */ 4002 if (ret_val) { 4003 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4004 e_dbg("Flash commit failed.\n"); 4005 goto release; 4006 } 4007 4008 /* Finally validate the new segment by setting bit 15:14 4009 * to 10b in word 0x13 , this can be done without an 4010 * erase as well since these bits are 11 to start with 4011 * and we need to change bit 14 to 0b 4012 */ 4013 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4014 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4015 if (ret_val) 4016 goto release; 4017 4018 data &= 0xBFFF; 4019 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4020 act_offset * 2 + 1, 4021 (u8)(data >> 8)); 4022 if (ret_val) 4023 goto release; 4024 4025 /* And invalidate the previously valid segment by setting 4026 * its signature word (0x13) high_byte to 0b. This can be 4027 * done without an erase because flash erase sets all bits 4028 * to 1's. We can write 1's to 0's without an erase 4029 */ 4030 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4031 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4032 if (ret_val) 4033 goto release; 4034 4035 /* Great! Everything worked, we can now clear the cached entries. */ 4036 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4037 dev_spec->shadow_ram[i].modified = false; 4038 dev_spec->shadow_ram[i].value = 0xFFFF; 4039 } 4040 4041 release: 4042 nvm->ops.release(hw); 4043 4044 /* Reload the EEPROM, or else modifications will not appear 4045 * until after the next adapter reset. 4046 */ 4047 if (!ret_val) { 4048 nvm->ops.reload(hw); 4049 usleep_range(10000, 20000); 4050 } 4051 4052 out: 4053 if (ret_val) 4054 e_dbg("NVM update error: %d\n", ret_val); 4055 4056 return ret_val; 4057 } 4058 4059 /** 4060 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4061 * @hw: pointer to the HW structure 4062 * 4063 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4064 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4065 * calculated, in which case we need to calculate the checksum and set bit 6. 4066 **/ 4067 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4068 { 4069 s32 ret_val; 4070 u16 data; 4071 u16 word; 4072 u16 valid_csum_mask; 4073 4074 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4075 * the checksum needs to be fixed. This bit is an indication that 4076 * the NVM was prepared by OEM software and did not calculate 4077 * the checksum...a likely scenario. 4078 */ 4079 switch (hw->mac.type) { 4080 case e1000_pch_lpt: 4081 case e1000_pch_spt: 4082 case e1000_pch_cnp: 4083 word = NVM_COMPAT; 4084 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4085 break; 4086 default: 4087 word = NVM_FUTURE_INIT_WORD1; 4088 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4089 break; 4090 } 4091 4092 ret_val = e1000_read_nvm(hw, word, 1, &data); 4093 if (ret_val) 4094 return ret_val; 4095 4096 if (!(data & valid_csum_mask)) { 4097 data |= valid_csum_mask; 4098 ret_val = e1000_write_nvm(hw, word, 1, &data); 4099 if (ret_val) 4100 return ret_val; 4101 ret_val = e1000e_update_nvm_checksum(hw); 4102 if (ret_val) 4103 return ret_val; 4104 } 4105 4106 return e1000e_validate_nvm_checksum_generic(hw); 4107 } 4108 4109 /** 4110 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4111 * @hw: pointer to the HW structure 4112 * 4113 * To prevent malicious write/erase of the NVM, set it to be read-only 4114 * so that the hardware ignores all write/erase cycles of the NVM via 4115 * the flash control registers. The shadow-ram copy of the NVM will 4116 * still be updated, however any updates to this copy will not stick 4117 * across driver reloads. 4118 **/ 4119 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4120 { 4121 struct e1000_nvm_info *nvm = &hw->nvm; 4122 union ich8_flash_protected_range pr0; 4123 union ich8_hws_flash_status hsfsts; 4124 u32 gfpreg; 4125 4126 nvm->ops.acquire(hw); 4127 4128 gfpreg = er32flash(ICH_FLASH_GFPREG); 4129 4130 /* Write-protect GbE Sector of NVM */ 4131 pr0.regval = er32flash(ICH_FLASH_PR0); 4132 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4133 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4134 pr0.range.wpe = true; 4135 ew32flash(ICH_FLASH_PR0, pr0.regval); 4136 4137 /* Lock down a subset of GbE Flash Control Registers, e.g. 4138 * PR0 to prevent the write-protection from being lifted. 4139 * Once FLOCKDN is set, the registers protected by it cannot 4140 * be written until FLOCKDN is cleared by a hardware reset. 4141 */ 4142 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4143 hsfsts.hsf_status.flockdn = true; 4144 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4145 4146 nvm->ops.release(hw); 4147 } 4148 4149 /** 4150 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4151 * @hw: pointer to the HW structure 4152 * @offset: The offset (in bytes) of the byte/word to read. 4153 * @size: Size of data to read, 1=byte 2=word 4154 * @data: The byte(s) to write to the NVM. 4155 * 4156 * Writes one/two bytes to the NVM using the flash access registers. 4157 **/ 4158 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4159 u8 size, u16 data) 4160 { 4161 union ich8_hws_flash_status hsfsts; 4162 union ich8_hws_flash_ctrl hsflctl; 4163 u32 flash_linear_addr; 4164 u32 flash_data = 0; 4165 s32 ret_val; 4166 u8 count = 0; 4167 4168 if (hw->mac.type >= e1000_pch_spt) { 4169 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4170 return -E1000_ERR_NVM; 4171 } else { 4172 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4173 return -E1000_ERR_NVM; 4174 } 4175 4176 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4177 hw->nvm.flash_base_addr); 4178 4179 do { 4180 udelay(1); 4181 /* Steps */ 4182 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4183 if (ret_val) 4184 break; 4185 /* In SPT, This register is in Lan memory space, not 4186 * flash. Therefore, only 32 bit access is supported 4187 */ 4188 if (hw->mac.type >= e1000_pch_spt) 4189 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4190 else 4191 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4192 4193 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4194 hsflctl.hsf_ctrl.fldbcount = size - 1; 4195 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4196 /* In SPT, This register is in Lan memory space, 4197 * not flash. Therefore, only 32 bit access is 4198 * supported 4199 */ 4200 if (hw->mac.type >= e1000_pch_spt) 4201 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4202 else 4203 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4204 4205 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4206 4207 if (size == 1) 4208 flash_data = (u32)data & 0x00FF; 4209 else 4210 flash_data = (u32)data; 4211 4212 ew32flash(ICH_FLASH_FDATA0, flash_data); 4213 4214 /* check if FCERR is set to 1 , if set to 1, clear it 4215 * and try the whole sequence a few more times else done 4216 */ 4217 ret_val = 4218 e1000_flash_cycle_ich8lan(hw, 4219 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4220 if (!ret_val) 4221 break; 4222 4223 /* If we're here, then things are most likely 4224 * completely hosed, but if the error condition 4225 * is detected, it won't hurt to give it another 4226 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4227 */ 4228 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4229 if (hsfsts.hsf_status.flcerr) 4230 /* Repeat for some time before giving up. */ 4231 continue; 4232 if (!hsfsts.hsf_status.flcdone) { 4233 e_dbg("Timeout error - flash cycle did not complete.\n"); 4234 break; 4235 } 4236 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4237 4238 return ret_val; 4239 } 4240 4241 /** 4242 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4243 * @hw: pointer to the HW structure 4244 * @offset: The offset (in bytes) of the dwords to read. 4245 * @data: The 4 bytes to write to the NVM. 4246 * 4247 * Writes one/two/four bytes to the NVM using the flash access registers. 4248 **/ 4249 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4250 u32 data) 4251 { 4252 union ich8_hws_flash_status hsfsts; 4253 union ich8_hws_flash_ctrl hsflctl; 4254 u32 flash_linear_addr; 4255 s32 ret_val; 4256 u8 count = 0; 4257 4258 if (hw->mac.type >= e1000_pch_spt) { 4259 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4260 return -E1000_ERR_NVM; 4261 } 4262 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4263 hw->nvm.flash_base_addr); 4264 do { 4265 udelay(1); 4266 /* Steps */ 4267 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4268 if (ret_val) 4269 break; 4270 4271 /* In SPT, This register is in Lan memory space, not 4272 * flash. Therefore, only 32 bit access is supported 4273 */ 4274 if (hw->mac.type >= e1000_pch_spt) 4275 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4276 >> 16; 4277 else 4278 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4279 4280 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4281 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4282 4283 /* In SPT, This register is in Lan memory space, 4284 * not flash. Therefore, only 32 bit access is 4285 * supported 4286 */ 4287 if (hw->mac.type >= e1000_pch_spt) 4288 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4289 else 4290 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4291 4292 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4293 4294 ew32flash(ICH_FLASH_FDATA0, data); 4295 4296 /* check if FCERR is set to 1 , if set to 1, clear it 4297 * and try the whole sequence a few more times else done 4298 */ 4299 ret_val = 4300 e1000_flash_cycle_ich8lan(hw, 4301 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4302 4303 if (!ret_val) 4304 break; 4305 4306 /* If we're here, then things are most likely 4307 * completely hosed, but if the error condition 4308 * is detected, it won't hurt to give it another 4309 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4310 */ 4311 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4312 4313 if (hsfsts.hsf_status.flcerr) 4314 /* Repeat for some time before giving up. */ 4315 continue; 4316 if (!hsfsts.hsf_status.flcdone) { 4317 e_dbg("Timeout error - flash cycle did not complete.\n"); 4318 break; 4319 } 4320 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4321 4322 return ret_val; 4323 } 4324 4325 /** 4326 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4327 * @hw: pointer to the HW structure 4328 * @offset: The index of the byte to read. 4329 * @data: The byte to write to the NVM. 4330 * 4331 * Writes a single byte to the NVM using the flash access registers. 4332 **/ 4333 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4334 u8 data) 4335 { 4336 u16 word = (u16)data; 4337 4338 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4339 } 4340 4341 /** 4342 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4343 * @hw: pointer to the HW structure 4344 * @offset: The offset of the word to write. 4345 * @dword: The dword to write to the NVM. 4346 * 4347 * Writes a single dword to the NVM using the flash access registers. 4348 * Goes through a retry algorithm before giving up. 4349 **/ 4350 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4351 u32 offset, u32 dword) 4352 { 4353 s32 ret_val; 4354 u16 program_retries; 4355 4356 /* Must convert word offset into bytes. */ 4357 offset <<= 1; 4358 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4359 4360 if (!ret_val) 4361 return ret_val; 4362 for (program_retries = 0; program_retries < 100; program_retries++) { 4363 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4364 usleep_range(100, 200); 4365 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4366 if (!ret_val) 4367 break; 4368 } 4369 if (program_retries == 100) 4370 return -E1000_ERR_NVM; 4371 4372 return 0; 4373 } 4374 4375 /** 4376 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4377 * @hw: pointer to the HW structure 4378 * @offset: The offset of the byte to write. 4379 * @byte: The byte to write to the NVM. 4380 * 4381 * Writes a single byte to the NVM using the flash access registers. 4382 * Goes through a retry algorithm before giving up. 4383 **/ 4384 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4385 u32 offset, u8 byte) 4386 { 4387 s32 ret_val; 4388 u16 program_retries; 4389 4390 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4391 if (!ret_val) 4392 return ret_val; 4393 4394 for (program_retries = 0; program_retries < 100; program_retries++) { 4395 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4396 usleep_range(100, 200); 4397 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4398 if (!ret_val) 4399 break; 4400 } 4401 if (program_retries == 100) 4402 return -E1000_ERR_NVM; 4403 4404 return 0; 4405 } 4406 4407 /** 4408 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4409 * @hw: pointer to the HW structure 4410 * @bank: 0 for first bank, 1 for second bank, etc. 4411 * 4412 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4413 * bank N is 4096 * N + flash_reg_addr. 4414 **/ 4415 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4416 { 4417 struct e1000_nvm_info *nvm = &hw->nvm; 4418 union ich8_hws_flash_status hsfsts; 4419 union ich8_hws_flash_ctrl hsflctl; 4420 u32 flash_linear_addr; 4421 /* bank size is in 16bit words - adjust to bytes */ 4422 u32 flash_bank_size = nvm->flash_bank_size * 2; 4423 s32 ret_val; 4424 s32 count = 0; 4425 s32 j, iteration, sector_size; 4426 4427 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4428 4429 /* Determine HW Sector size: Read BERASE bits of hw flash status 4430 * register 4431 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4432 * consecutive sectors. The start index for the nth Hw sector 4433 * can be calculated as = bank * 4096 + n * 256 4434 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4435 * The start index for the nth Hw sector can be calculated 4436 * as = bank * 4096 4437 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4438 * (ich9 only, otherwise error condition) 4439 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4440 */ 4441 switch (hsfsts.hsf_status.berasesz) { 4442 case 0: 4443 /* Hw sector size 256 */ 4444 sector_size = ICH_FLASH_SEG_SIZE_256; 4445 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4446 break; 4447 case 1: 4448 sector_size = ICH_FLASH_SEG_SIZE_4K; 4449 iteration = 1; 4450 break; 4451 case 2: 4452 sector_size = ICH_FLASH_SEG_SIZE_8K; 4453 iteration = 1; 4454 break; 4455 case 3: 4456 sector_size = ICH_FLASH_SEG_SIZE_64K; 4457 iteration = 1; 4458 break; 4459 default: 4460 return -E1000_ERR_NVM; 4461 } 4462 4463 /* Start with the base address, then add the sector offset. */ 4464 flash_linear_addr = hw->nvm.flash_base_addr; 4465 flash_linear_addr += (bank) ? flash_bank_size : 0; 4466 4467 for (j = 0; j < iteration; j++) { 4468 do { 4469 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4470 4471 /* Steps */ 4472 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4473 if (ret_val) 4474 return ret_val; 4475 4476 /* Write a value 11 (block Erase) in Flash 4477 * Cycle field in hw flash control 4478 */ 4479 if (hw->mac.type >= e1000_pch_spt) 4480 hsflctl.regval = 4481 er32flash(ICH_FLASH_HSFSTS) >> 16; 4482 else 4483 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4484 4485 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4486 if (hw->mac.type >= e1000_pch_spt) 4487 ew32flash(ICH_FLASH_HSFSTS, 4488 hsflctl.regval << 16); 4489 else 4490 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4491 4492 /* Write the last 24 bits of an index within the 4493 * block into Flash Linear address field in Flash 4494 * Address. 4495 */ 4496 flash_linear_addr += (j * sector_size); 4497 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4498 4499 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4500 if (!ret_val) 4501 break; 4502 4503 /* Check if FCERR is set to 1. If 1, 4504 * clear it and try the whole sequence 4505 * a few more times else Done 4506 */ 4507 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4508 if (hsfsts.hsf_status.flcerr) 4509 /* repeat for some time before giving up */ 4510 continue; 4511 else if (!hsfsts.hsf_status.flcdone) 4512 return ret_val; 4513 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4514 } 4515 4516 return 0; 4517 } 4518 4519 /** 4520 * e1000_valid_led_default_ich8lan - Set the default LED settings 4521 * @hw: pointer to the HW structure 4522 * @data: Pointer to the LED settings 4523 * 4524 * Reads the LED default settings from the NVM to data. If the NVM LED 4525 * settings is all 0's or F's, set the LED default to a valid LED default 4526 * setting. 4527 **/ 4528 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4529 { 4530 s32 ret_val; 4531 4532 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4533 if (ret_val) { 4534 e_dbg("NVM Read Error\n"); 4535 return ret_val; 4536 } 4537 4538 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4539 *data = ID_LED_DEFAULT_ICH8LAN; 4540 4541 return 0; 4542 } 4543 4544 /** 4545 * e1000_id_led_init_pchlan - store LED configurations 4546 * @hw: pointer to the HW structure 4547 * 4548 * PCH does not control LEDs via the LEDCTL register, rather it uses 4549 * the PHY LED configuration register. 4550 * 4551 * PCH also does not have an "always on" or "always off" mode which 4552 * complicates the ID feature. Instead of using the "on" mode to indicate 4553 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4554 * use "link_up" mode. The LEDs will still ID on request if there is no 4555 * link based on logic in e1000_led_[on|off]_pchlan(). 4556 **/ 4557 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4558 { 4559 struct e1000_mac_info *mac = &hw->mac; 4560 s32 ret_val; 4561 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4562 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4563 u16 data, i, temp, shift; 4564 4565 /* Get default ID LED modes */ 4566 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4567 if (ret_val) 4568 return ret_val; 4569 4570 mac->ledctl_default = er32(LEDCTL); 4571 mac->ledctl_mode1 = mac->ledctl_default; 4572 mac->ledctl_mode2 = mac->ledctl_default; 4573 4574 for (i = 0; i < 4; i++) { 4575 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4576 shift = (i * 5); 4577 switch (temp) { 4578 case ID_LED_ON1_DEF2: 4579 case ID_LED_ON1_ON2: 4580 case ID_LED_ON1_OFF2: 4581 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4582 mac->ledctl_mode1 |= (ledctl_on << shift); 4583 break; 4584 case ID_LED_OFF1_DEF2: 4585 case ID_LED_OFF1_ON2: 4586 case ID_LED_OFF1_OFF2: 4587 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4588 mac->ledctl_mode1 |= (ledctl_off << shift); 4589 break; 4590 default: 4591 /* Do nothing */ 4592 break; 4593 } 4594 switch (temp) { 4595 case ID_LED_DEF1_ON2: 4596 case ID_LED_ON1_ON2: 4597 case ID_LED_OFF1_ON2: 4598 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4599 mac->ledctl_mode2 |= (ledctl_on << shift); 4600 break; 4601 case ID_LED_DEF1_OFF2: 4602 case ID_LED_ON1_OFF2: 4603 case ID_LED_OFF1_OFF2: 4604 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4605 mac->ledctl_mode2 |= (ledctl_off << shift); 4606 break; 4607 default: 4608 /* Do nothing */ 4609 break; 4610 } 4611 } 4612 4613 return 0; 4614 } 4615 4616 /** 4617 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4618 * @hw: pointer to the HW structure 4619 * 4620 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4621 * register, so the the bus width is hard coded. 4622 **/ 4623 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4624 { 4625 struct e1000_bus_info *bus = &hw->bus; 4626 s32 ret_val; 4627 4628 ret_val = e1000e_get_bus_info_pcie(hw); 4629 4630 /* ICH devices are "PCI Express"-ish. They have 4631 * a configuration space, but do not contain 4632 * PCI Express Capability registers, so bus width 4633 * must be hardcoded. 4634 */ 4635 if (bus->width == e1000_bus_width_unknown) 4636 bus->width = e1000_bus_width_pcie_x1; 4637 4638 return ret_val; 4639 } 4640 4641 /** 4642 * e1000_reset_hw_ich8lan - Reset the hardware 4643 * @hw: pointer to the HW structure 4644 * 4645 * Does a full reset of the hardware which includes a reset of the PHY and 4646 * MAC. 4647 **/ 4648 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4649 { 4650 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4651 u16 kum_cfg; 4652 u32 ctrl, reg; 4653 s32 ret_val; 4654 4655 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4656 * on the last TLP read/write transaction when MAC is reset. 4657 */ 4658 ret_val = e1000e_disable_pcie_master(hw); 4659 if (ret_val) 4660 e_dbg("PCI-E Master disable polling has failed.\n"); 4661 4662 e_dbg("Masking off all interrupts\n"); 4663 ew32(IMC, 0xffffffff); 4664 4665 /* Disable the Transmit and Receive units. Then delay to allow 4666 * any pending transactions to complete before we hit the MAC 4667 * with the global reset. 4668 */ 4669 ew32(RCTL, 0); 4670 ew32(TCTL, E1000_TCTL_PSP); 4671 e1e_flush(); 4672 4673 usleep_range(10000, 20000); 4674 4675 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4676 if (hw->mac.type == e1000_ich8lan) { 4677 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4678 ew32(PBA, E1000_PBA_8K); 4679 /* Set Packet Buffer Size to 16k. */ 4680 ew32(PBS, E1000_PBS_16K); 4681 } 4682 4683 if (hw->mac.type == e1000_pchlan) { 4684 /* Save the NVM K1 bit setting */ 4685 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4686 if (ret_val) 4687 return ret_val; 4688 4689 if (kum_cfg & E1000_NVM_K1_ENABLE) 4690 dev_spec->nvm_k1_enabled = true; 4691 else 4692 dev_spec->nvm_k1_enabled = false; 4693 } 4694 4695 ctrl = er32(CTRL); 4696 4697 if (!hw->phy.ops.check_reset_block(hw)) { 4698 /* Full-chip reset requires MAC and PHY reset at the same 4699 * time to make sure the interface between MAC and the 4700 * external PHY is reset. 4701 */ 4702 ctrl |= E1000_CTRL_PHY_RST; 4703 4704 /* Gate automatic PHY configuration by hardware on 4705 * non-managed 82579 4706 */ 4707 if ((hw->mac.type == e1000_pch2lan) && 4708 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4709 e1000_gate_hw_phy_config_ich8lan(hw, true); 4710 } 4711 ret_val = e1000_acquire_swflag_ich8lan(hw); 4712 e_dbg("Issuing a global reset to ich8lan\n"); 4713 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4714 /* cannot issue a flush here because it hangs the hardware */ 4715 msleep(20); 4716 4717 /* Set Phy Config Counter to 50msec */ 4718 if (hw->mac.type == e1000_pch2lan) { 4719 reg = er32(FEXTNVM3); 4720 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4721 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4722 ew32(FEXTNVM3, reg); 4723 } 4724 4725 if (!ret_val) 4726 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4727 4728 if (ctrl & E1000_CTRL_PHY_RST) { 4729 ret_val = hw->phy.ops.get_cfg_done(hw); 4730 if (ret_val) 4731 return ret_val; 4732 4733 ret_val = e1000_post_phy_reset_ich8lan(hw); 4734 if (ret_val) 4735 return ret_val; 4736 } 4737 4738 /* For PCH, this write will make sure that any noise 4739 * will be detected as a CRC error and be dropped rather than show up 4740 * as a bad packet to the DMA engine. 4741 */ 4742 if (hw->mac.type == e1000_pchlan) 4743 ew32(CRC_OFFSET, 0x65656565); 4744 4745 ew32(IMC, 0xffffffff); 4746 er32(ICR); 4747 4748 reg = er32(KABGTXD); 4749 reg |= E1000_KABGTXD_BGSQLBIAS; 4750 ew32(KABGTXD, reg); 4751 4752 return 0; 4753 } 4754 4755 /** 4756 * e1000_init_hw_ich8lan - Initialize the hardware 4757 * @hw: pointer to the HW structure 4758 * 4759 * Prepares the hardware for transmit and receive by doing the following: 4760 * - initialize hardware bits 4761 * - initialize LED identification 4762 * - setup receive address registers 4763 * - setup flow control 4764 * - setup transmit descriptors 4765 * - clear statistics 4766 **/ 4767 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4768 { 4769 struct e1000_mac_info *mac = &hw->mac; 4770 u32 ctrl_ext, txdctl, snoop; 4771 s32 ret_val; 4772 u16 i; 4773 4774 e1000_initialize_hw_bits_ich8lan(hw); 4775 4776 /* Initialize identification LED */ 4777 ret_val = mac->ops.id_led_init(hw); 4778 /* An error is not fatal and we should not stop init due to this */ 4779 if (ret_val) 4780 e_dbg("Error initializing identification LED\n"); 4781 4782 /* Setup the receive address. */ 4783 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4784 4785 /* Zero out the Multicast HASH table */ 4786 e_dbg("Zeroing the MTA\n"); 4787 for (i = 0; i < mac->mta_reg_count; i++) 4788 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4789 4790 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4791 * the ME. Disable wakeup by clearing the host wakeup bit. 4792 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4793 */ 4794 if (hw->phy.type == e1000_phy_82578) { 4795 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4796 i &= ~BM_WUC_HOST_WU_BIT; 4797 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4798 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4799 if (ret_val) 4800 return ret_val; 4801 } 4802 4803 /* Setup link and flow control */ 4804 ret_val = mac->ops.setup_link(hw); 4805 4806 /* Set the transmit descriptor write-back policy for both queues */ 4807 txdctl = er32(TXDCTL(0)); 4808 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4809 E1000_TXDCTL_FULL_TX_DESC_WB); 4810 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4811 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4812 ew32(TXDCTL(0), txdctl); 4813 txdctl = er32(TXDCTL(1)); 4814 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4815 E1000_TXDCTL_FULL_TX_DESC_WB); 4816 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4817 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4818 ew32(TXDCTL(1), txdctl); 4819 4820 /* ICH8 has opposite polarity of no_snoop bits. 4821 * By default, we should use snoop behavior. 4822 */ 4823 if (mac->type == e1000_ich8lan) 4824 snoop = PCIE_ICH8_SNOOP_ALL; 4825 else 4826 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4827 e1000e_set_pcie_no_snoop(hw, snoop); 4828 4829 ctrl_ext = er32(CTRL_EXT); 4830 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4831 ew32(CTRL_EXT, ctrl_ext); 4832 4833 /* Clear all of the statistics registers (clear on read). It is 4834 * important that we do this after we have tried to establish link 4835 * because the symbol error count will increment wildly if there 4836 * is no link. 4837 */ 4838 e1000_clear_hw_cntrs_ich8lan(hw); 4839 4840 return ret_val; 4841 } 4842 4843 /** 4844 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4845 * @hw: pointer to the HW structure 4846 * 4847 * Sets/Clears required hardware bits necessary for correctly setting up the 4848 * hardware for transmit and receive. 4849 **/ 4850 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4851 { 4852 u32 reg; 4853 4854 /* Extended Device Control */ 4855 reg = er32(CTRL_EXT); 4856 reg |= BIT(22); 4857 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4858 if (hw->mac.type >= e1000_pchlan) 4859 reg |= E1000_CTRL_EXT_PHYPDEN; 4860 ew32(CTRL_EXT, reg); 4861 4862 /* Transmit Descriptor Control 0 */ 4863 reg = er32(TXDCTL(0)); 4864 reg |= BIT(22); 4865 ew32(TXDCTL(0), reg); 4866 4867 /* Transmit Descriptor Control 1 */ 4868 reg = er32(TXDCTL(1)); 4869 reg |= BIT(22); 4870 ew32(TXDCTL(1), reg); 4871 4872 /* Transmit Arbitration Control 0 */ 4873 reg = er32(TARC(0)); 4874 if (hw->mac.type == e1000_ich8lan) 4875 reg |= BIT(28) | BIT(29); 4876 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4877 ew32(TARC(0), reg); 4878 4879 /* Transmit Arbitration Control 1 */ 4880 reg = er32(TARC(1)); 4881 if (er32(TCTL) & E1000_TCTL_MULR) 4882 reg &= ~BIT(28); 4883 else 4884 reg |= BIT(28); 4885 reg |= BIT(24) | BIT(26) | BIT(30); 4886 ew32(TARC(1), reg); 4887 4888 /* Device Status */ 4889 if (hw->mac.type == e1000_ich8lan) { 4890 reg = er32(STATUS); 4891 reg &= ~BIT(31); 4892 ew32(STATUS, reg); 4893 } 4894 4895 /* work-around descriptor data corruption issue during nfs v2 udp 4896 * traffic, just disable the nfs filtering capability 4897 */ 4898 reg = er32(RFCTL); 4899 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4900 4901 /* Disable IPv6 extension header parsing because some malformed 4902 * IPv6 headers can hang the Rx. 4903 */ 4904 if (hw->mac.type == e1000_ich8lan) 4905 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4906 ew32(RFCTL, reg); 4907 4908 /* Enable ECC on Lynxpoint */ 4909 if (hw->mac.type >= e1000_pch_lpt) { 4910 reg = er32(PBECCSTS); 4911 reg |= E1000_PBECCSTS_ECC_ENABLE; 4912 ew32(PBECCSTS, reg); 4913 4914 reg = er32(CTRL); 4915 reg |= E1000_CTRL_MEHE; 4916 ew32(CTRL, reg); 4917 } 4918 } 4919 4920 /** 4921 * e1000_setup_link_ich8lan - Setup flow control and link settings 4922 * @hw: pointer to the HW structure 4923 * 4924 * Determines which flow control settings to use, then configures flow 4925 * control. Calls the appropriate media-specific link configuration 4926 * function. Assuming the adapter has a valid link partner, a valid link 4927 * should be established. Assumes the hardware has previously been reset 4928 * and the transmitter and receiver are not enabled. 4929 **/ 4930 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4931 { 4932 s32 ret_val; 4933 4934 if (hw->phy.ops.check_reset_block(hw)) 4935 return 0; 4936 4937 /* ICH parts do not have a word in the NVM to determine 4938 * the default flow control setting, so we explicitly 4939 * set it to full. 4940 */ 4941 if (hw->fc.requested_mode == e1000_fc_default) { 4942 /* Workaround h/w hang when Tx flow control enabled */ 4943 if (hw->mac.type == e1000_pchlan) 4944 hw->fc.requested_mode = e1000_fc_rx_pause; 4945 else 4946 hw->fc.requested_mode = e1000_fc_full; 4947 } 4948 4949 /* Save off the requested flow control mode for use later. Depending 4950 * on the link partner's capabilities, we may or may not use this mode. 4951 */ 4952 hw->fc.current_mode = hw->fc.requested_mode; 4953 4954 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4955 4956 /* Continue to configure the copper link. */ 4957 ret_val = hw->mac.ops.setup_physical_interface(hw); 4958 if (ret_val) 4959 return ret_val; 4960 4961 ew32(FCTTV, hw->fc.pause_time); 4962 if ((hw->phy.type == e1000_phy_82578) || 4963 (hw->phy.type == e1000_phy_82579) || 4964 (hw->phy.type == e1000_phy_i217) || 4965 (hw->phy.type == e1000_phy_82577)) { 4966 ew32(FCRTV_PCH, hw->fc.refresh_time); 4967 4968 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4969 hw->fc.pause_time); 4970 if (ret_val) 4971 return ret_val; 4972 } 4973 4974 return e1000e_set_fc_watermarks(hw); 4975 } 4976 4977 /** 4978 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4979 * @hw: pointer to the HW structure 4980 * 4981 * Configures the kumeran interface to the PHY to wait the appropriate time 4982 * when polling the PHY, then call the generic setup_copper_link to finish 4983 * configuring the copper link. 4984 **/ 4985 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 4986 { 4987 u32 ctrl; 4988 s32 ret_val; 4989 u16 reg_data; 4990 4991 ctrl = er32(CTRL); 4992 ctrl |= E1000_CTRL_SLU; 4993 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4994 ew32(CTRL, ctrl); 4995 4996 /* Set the mac to wait the maximum time between each iteration 4997 * and increase the max iterations when polling the phy; 4998 * this fixes erroneous timeouts at 10Mbps. 4999 */ 5000 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5001 if (ret_val) 5002 return ret_val; 5003 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5004 ®_data); 5005 if (ret_val) 5006 return ret_val; 5007 reg_data |= 0x3F; 5008 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5009 reg_data); 5010 if (ret_val) 5011 return ret_val; 5012 5013 switch (hw->phy.type) { 5014 case e1000_phy_igp_3: 5015 ret_val = e1000e_copper_link_setup_igp(hw); 5016 if (ret_val) 5017 return ret_val; 5018 break; 5019 case e1000_phy_bm: 5020 case e1000_phy_82578: 5021 ret_val = e1000e_copper_link_setup_m88(hw); 5022 if (ret_val) 5023 return ret_val; 5024 break; 5025 case e1000_phy_82577: 5026 case e1000_phy_82579: 5027 ret_val = e1000_copper_link_setup_82577(hw); 5028 if (ret_val) 5029 return ret_val; 5030 break; 5031 case e1000_phy_ife: 5032 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5033 if (ret_val) 5034 return ret_val; 5035 5036 reg_data &= ~IFE_PMC_AUTO_MDIX; 5037 5038 switch (hw->phy.mdix) { 5039 case 1: 5040 reg_data &= ~IFE_PMC_FORCE_MDIX; 5041 break; 5042 case 2: 5043 reg_data |= IFE_PMC_FORCE_MDIX; 5044 break; 5045 case 0: 5046 default: 5047 reg_data |= IFE_PMC_AUTO_MDIX; 5048 break; 5049 } 5050 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5051 if (ret_val) 5052 return ret_val; 5053 break; 5054 default: 5055 break; 5056 } 5057 5058 return e1000e_setup_copper_link(hw); 5059 } 5060 5061 /** 5062 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5063 * @hw: pointer to the HW structure 5064 * 5065 * Calls the PHY specific link setup function and then calls the 5066 * generic setup_copper_link to finish configuring the link for 5067 * Lynxpoint PCH devices 5068 **/ 5069 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5070 { 5071 u32 ctrl; 5072 s32 ret_val; 5073 5074 ctrl = er32(CTRL); 5075 ctrl |= E1000_CTRL_SLU; 5076 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5077 ew32(CTRL, ctrl); 5078 5079 ret_val = e1000_copper_link_setup_82577(hw); 5080 if (ret_val) 5081 return ret_val; 5082 5083 return e1000e_setup_copper_link(hw); 5084 } 5085 5086 /** 5087 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5088 * @hw: pointer to the HW structure 5089 * @speed: pointer to store current link speed 5090 * @duplex: pointer to store the current link duplex 5091 * 5092 * Calls the generic get_speed_and_duplex to retrieve the current link 5093 * information and then calls the Kumeran lock loss workaround for links at 5094 * gigabit speeds. 5095 **/ 5096 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5097 u16 *duplex) 5098 { 5099 s32 ret_val; 5100 5101 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5102 if (ret_val) 5103 return ret_val; 5104 5105 if ((hw->mac.type == e1000_ich8lan) && 5106 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5107 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5108 } 5109 5110 return ret_val; 5111 } 5112 5113 /** 5114 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5115 * @hw: pointer to the HW structure 5116 * 5117 * Work-around for 82566 Kumeran PCS lock loss: 5118 * On link status change (i.e. PCI reset, speed change) and link is up and 5119 * speed is gigabit- 5120 * 0) if workaround is optionally disabled do nothing 5121 * 1) wait 1ms for Kumeran link to come up 5122 * 2) check Kumeran Diagnostic register PCS lock loss bit 5123 * 3) if not set the link is locked (all is good), otherwise... 5124 * 4) reset the PHY 5125 * 5) repeat up to 10 times 5126 * Note: this is only called for IGP3 copper when speed is 1gb. 5127 **/ 5128 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5129 { 5130 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5131 u32 phy_ctrl; 5132 s32 ret_val; 5133 u16 i, data; 5134 bool link; 5135 5136 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5137 return 0; 5138 5139 /* Make sure link is up before proceeding. If not just return. 5140 * Attempting this while link is negotiating fouled up link 5141 * stability 5142 */ 5143 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5144 if (!link) 5145 return 0; 5146 5147 for (i = 0; i < 10; i++) { 5148 /* read once to clear */ 5149 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5150 if (ret_val) 5151 return ret_val; 5152 /* and again to get new status */ 5153 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5154 if (ret_val) 5155 return ret_val; 5156 5157 /* check for PCS lock */ 5158 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5159 return 0; 5160 5161 /* Issue PHY reset */ 5162 e1000_phy_hw_reset(hw); 5163 mdelay(5); 5164 } 5165 /* Disable GigE link negotiation */ 5166 phy_ctrl = er32(PHY_CTRL); 5167 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5168 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5169 ew32(PHY_CTRL, phy_ctrl); 5170 5171 /* Call gig speed drop workaround on Gig disable before accessing 5172 * any PHY registers 5173 */ 5174 e1000e_gig_downshift_workaround_ich8lan(hw); 5175 5176 /* unable to acquire PCS lock */ 5177 return -E1000_ERR_PHY; 5178 } 5179 5180 /** 5181 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5182 * @hw: pointer to the HW structure 5183 * @state: boolean value used to set the current Kumeran workaround state 5184 * 5185 * If ICH8, set the current Kumeran workaround state (enabled - true 5186 * /disabled - false). 5187 **/ 5188 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5189 bool state) 5190 { 5191 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5192 5193 if (hw->mac.type != e1000_ich8lan) { 5194 e_dbg("Workaround applies to ICH8 only.\n"); 5195 return; 5196 } 5197 5198 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5199 } 5200 5201 /** 5202 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5203 * @hw: pointer to the HW structure 5204 * 5205 * Workaround for 82566 power-down on D3 entry: 5206 * 1) disable gigabit link 5207 * 2) write VR power-down enable 5208 * 3) read it back 5209 * Continue if successful, else issue LCD reset and repeat 5210 **/ 5211 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5212 { 5213 u32 reg; 5214 u16 data; 5215 u8 retry = 0; 5216 5217 if (hw->phy.type != e1000_phy_igp_3) 5218 return; 5219 5220 /* Try the workaround twice (if needed) */ 5221 do { 5222 /* Disable link */ 5223 reg = er32(PHY_CTRL); 5224 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5225 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5226 ew32(PHY_CTRL, reg); 5227 5228 /* Call gig speed drop workaround on Gig disable before 5229 * accessing any PHY registers 5230 */ 5231 if (hw->mac.type == e1000_ich8lan) 5232 e1000e_gig_downshift_workaround_ich8lan(hw); 5233 5234 /* Write VR power-down enable */ 5235 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5236 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5237 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5238 5239 /* Read it back and test */ 5240 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5241 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5242 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5243 break; 5244 5245 /* Issue PHY reset and repeat at most one more time */ 5246 reg = er32(CTRL); 5247 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5248 retry++; 5249 } while (retry); 5250 } 5251 5252 /** 5253 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5254 * @hw: pointer to the HW structure 5255 * 5256 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5257 * LPLU, Gig disable, MDIC PHY reset): 5258 * 1) Set Kumeran Near-end loopback 5259 * 2) Clear Kumeran Near-end loopback 5260 * Should only be called for ICH8[m] devices with any 1G Phy. 5261 **/ 5262 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5263 { 5264 s32 ret_val; 5265 u16 reg_data; 5266 5267 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5268 return; 5269 5270 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5271 ®_data); 5272 if (ret_val) 5273 return; 5274 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5275 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5276 reg_data); 5277 if (ret_val) 5278 return; 5279 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5280 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5281 } 5282 5283 /** 5284 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5285 * @hw: pointer to the HW structure 5286 * 5287 * During S0 to Sx transition, it is possible the link remains at gig 5288 * instead of negotiating to a lower speed. Before going to Sx, set 5289 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5290 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5291 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5292 * needs to be written. 5293 * Parts that support (and are linked to a partner which support) EEE in 5294 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5295 * than 10Mbps w/o EEE. 5296 **/ 5297 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5298 { 5299 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5300 u32 phy_ctrl; 5301 s32 ret_val; 5302 5303 phy_ctrl = er32(PHY_CTRL); 5304 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5305 5306 if (hw->phy.type == e1000_phy_i217) { 5307 u16 phy_reg, device_id = hw->adapter->pdev->device; 5308 5309 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5310 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5311 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5312 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5313 (hw->mac.type >= e1000_pch_spt)) { 5314 u32 fextnvm6 = er32(FEXTNVM6); 5315 5316 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5317 } 5318 5319 ret_val = hw->phy.ops.acquire(hw); 5320 if (ret_val) 5321 goto out; 5322 5323 if (!dev_spec->eee_disable) { 5324 u16 eee_advert; 5325 5326 ret_val = 5327 e1000_read_emi_reg_locked(hw, 5328 I217_EEE_ADVERTISEMENT, 5329 &eee_advert); 5330 if (ret_val) 5331 goto release; 5332 5333 /* Disable LPLU if both link partners support 100BaseT 5334 * EEE and 100Full is advertised on both ends of the 5335 * link, and enable Auto Enable LPI since there will 5336 * be no driver to enable LPI while in Sx. 5337 */ 5338 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5339 (dev_spec->eee_lp_ability & 5340 I82579_EEE_100_SUPPORTED) && 5341 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5342 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5343 E1000_PHY_CTRL_NOND0A_LPLU); 5344 5345 /* Set Auto Enable LPI after link up */ 5346 e1e_rphy_locked(hw, 5347 I217_LPI_GPIO_CTRL, &phy_reg); 5348 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5349 e1e_wphy_locked(hw, 5350 I217_LPI_GPIO_CTRL, phy_reg); 5351 } 5352 } 5353 5354 /* For i217 Intel Rapid Start Technology support, 5355 * when the system is going into Sx and no manageability engine 5356 * is present, the driver must configure proxy to reset only on 5357 * power good. LPI (Low Power Idle) state must also reset only 5358 * on power good, as well as the MTA (Multicast table array). 5359 * The SMBus release must also be disabled on LCD reset. 5360 */ 5361 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5362 /* Enable proxy to reset only on power good. */ 5363 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5364 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5365 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5366 5367 /* Set bit enable LPI (EEE) to reset only on 5368 * power good. 5369 */ 5370 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5371 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5372 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5373 5374 /* Disable the SMB release on LCD reset. */ 5375 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5376 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5377 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5378 } 5379 5380 /* Enable MTA to reset for Intel Rapid Start Technology 5381 * Support 5382 */ 5383 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5384 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5385 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5386 5387 release: 5388 hw->phy.ops.release(hw); 5389 } 5390 out: 5391 ew32(PHY_CTRL, phy_ctrl); 5392 5393 if (hw->mac.type == e1000_ich8lan) 5394 e1000e_gig_downshift_workaround_ich8lan(hw); 5395 5396 if (hw->mac.type >= e1000_pchlan) { 5397 e1000_oem_bits_config_ich8lan(hw, false); 5398 5399 /* Reset PHY to activate OEM bits on 82577/8 */ 5400 if (hw->mac.type == e1000_pchlan) 5401 e1000e_phy_hw_reset_generic(hw); 5402 5403 ret_val = hw->phy.ops.acquire(hw); 5404 if (ret_val) 5405 return; 5406 e1000_write_smbus_addr(hw); 5407 hw->phy.ops.release(hw); 5408 } 5409 } 5410 5411 /** 5412 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5413 * @hw: pointer to the HW structure 5414 * 5415 * During Sx to S0 transitions on non-managed devices or managed devices 5416 * on which PHY resets are not blocked, if the PHY registers cannot be 5417 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5418 * the PHY. 5419 * On i217, setup Intel Rapid Start Technology. 5420 **/ 5421 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5422 { 5423 s32 ret_val; 5424 5425 if (hw->mac.type < e1000_pch2lan) 5426 return; 5427 5428 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5429 if (ret_val) { 5430 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5431 return; 5432 } 5433 5434 /* For i217 Intel Rapid Start Technology support when the system 5435 * is transitioning from Sx and no manageability engine is present 5436 * configure SMBus to restore on reset, disable proxy, and enable 5437 * the reset on MTA (Multicast table array). 5438 */ 5439 if (hw->phy.type == e1000_phy_i217) { 5440 u16 phy_reg; 5441 5442 ret_val = hw->phy.ops.acquire(hw); 5443 if (ret_val) { 5444 e_dbg("Failed to setup iRST\n"); 5445 return; 5446 } 5447 5448 /* Clear Auto Enable LPI after link up */ 5449 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5450 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5451 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5452 5453 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5454 /* Restore clear on SMB if no manageability engine 5455 * is present 5456 */ 5457 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5458 if (ret_val) 5459 goto release; 5460 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5461 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5462 5463 /* Disable Proxy */ 5464 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5465 } 5466 /* Enable reset on MTA */ 5467 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5468 if (ret_val) 5469 goto release; 5470 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5471 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5472 release: 5473 if (ret_val) 5474 e_dbg("Error %d in resume workarounds\n", ret_val); 5475 hw->phy.ops.release(hw); 5476 } 5477 } 5478 5479 /** 5480 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5481 * @hw: pointer to the HW structure 5482 * 5483 * Return the LED back to the default configuration. 5484 **/ 5485 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5486 { 5487 if (hw->phy.type == e1000_phy_ife) 5488 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5489 5490 ew32(LEDCTL, hw->mac.ledctl_default); 5491 return 0; 5492 } 5493 5494 /** 5495 * e1000_led_on_ich8lan - Turn LEDs on 5496 * @hw: pointer to the HW structure 5497 * 5498 * Turn on the LEDs. 5499 **/ 5500 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5501 { 5502 if (hw->phy.type == e1000_phy_ife) 5503 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5504 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5505 5506 ew32(LEDCTL, hw->mac.ledctl_mode2); 5507 return 0; 5508 } 5509 5510 /** 5511 * e1000_led_off_ich8lan - Turn LEDs off 5512 * @hw: pointer to the HW structure 5513 * 5514 * Turn off the LEDs. 5515 **/ 5516 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5517 { 5518 if (hw->phy.type == e1000_phy_ife) 5519 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5520 (IFE_PSCL_PROBE_MODE | 5521 IFE_PSCL_PROBE_LEDS_OFF)); 5522 5523 ew32(LEDCTL, hw->mac.ledctl_mode1); 5524 return 0; 5525 } 5526 5527 /** 5528 * e1000_setup_led_pchlan - Configures SW controllable LED 5529 * @hw: pointer to the HW structure 5530 * 5531 * This prepares the SW controllable LED for use. 5532 **/ 5533 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5534 { 5535 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5536 } 5537 5538 /** 5539 * e1000_cleanup_led_pchlan - Restore the default LED operation 5540 * @hw: pointer to the HW structure 5541 * 5542 * Return the LED back to the default configuration. 5543 **/ 5544 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5545 { 5546 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5547 } 5548 5549 /** 5550 * e1000_led_on_pchlan - Turn LEDs on 5551 * @hw: pointer to the HW structure 5552 * 5553 * Turn on the LEDs. 5554 **/ 5555 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5556 { 5557 u16 data = (u16)hw->mac.ledctl_mode2; 5558 u32 i, led; 5559 5560 /* If no link, then turn LED on by setting the invert bit 5561 * for each LED that's mode is "link_up" in ledctl_mode2. 5562 */ 5563 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5564 for (i = 0; i < 3; i++) { 5565 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5566 if ((led & E1000_PHY_LED0_MODE_MASK) != 5567 E1000_LEDCTL_MODE_LINK_UP) 5568 continue; 5569 if (led & E1000_PHY_LED0_IVRT) 5570 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5571 else 5572 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5573 } 5574 } 5575 5576 return e1e_wphy(hw, HV_LED_CONFIG, data); 5577 } 5578 5579 /** 5580 * e1000_led_off_pchlan - Turn LEDs off 5581 * @hw: pointer to the HW structure 5582 * 5583 * Turn off the LEDs. 5584 **/ 5585 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5586 { 5587 u16 data = (u16)hw->mac.ledctl_mode1; 5588 u32 i, led; 5589 5590 /* If no link, then turn LED off by clearing the invert bit 5591 * for each LED that's mode is "link_up" in ledctl_mode1. 5592 */ 5593 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5594 for (i = 0; i < 3; i++) { 5595 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5596 if ((led & E1000_PHY_LED0_MODE_MASK) != 5597 E1000_LEDCTL_MODE_LINK_UP) 5598 continue; 5599 if (led & E1000_PHY_LED0_IVRT) 5600 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5601 else 5602 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5603 } 5604 } 5605 5606 return e1e_wphy(hw, HV_LED_CONFIG, data); 5607 } 5608 5609 /** 5610 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5611 * @hw: pointer to the HW structure 5612 * 5613 * Read appropriate register for the config done bit for completion status 5614 * and configure the PHY through s/w for EEPROM-less parts. 5615 * 5616 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5617 * config done bit, so only an error is logged and continues. If we were 5618 * to return with error, EEPROM-less silicon would not be able to be reset 5619 * or change link. 5620 **/ 5621 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5622 { 5623 s32 ret_val = 0; 5624 u32 bank = 0; 5625 u32 status; 5626 5627 e1000e_get_cfg_done_generic(hw); 5628 5629 /* Wait for indication from h/w that it has completed basic config */ 5630 if (hw->mac.type >= e1000_ich10lan) { 5631 e1000_lan_init_done_ich8lan(hw); 5632 } else { 5633 ret_val = e1000e_get_auto_rd_done(hw); 5634 if (ret_val) { 5635 /* When auto config read does not complete, do not 5636 * return with an error. This can happen in situations 5637 * where there is no eeprom and prevents getting link. 5638 */ 5639 e_dbg("Auto Read Done did not complete\n"); 5640 ret_val = 0; 5641 } 5642 } 5643 5644 /* Clear PHY Reset Asserted bit */ 5645 status = er32(STATUS); 5646 if (status & E1000_STATUS_PHYRA) 5647 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5648 else 5649 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5650 5651 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5652 if (hw->mac.type <= e1000_ich9lan) { 5653 if (!(er32(EECD) & E1000_EECD_PRES) && 5654 (hw->phy.type == e1000_phy_igp_3)) { 5655 e1000e_phy_init_script_igp3(hw); 5656 } 5657 } else { 5658 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5659 /* Maybe we should do a basic PHY config */ 5660 e_dbg("EEPROM not present\n"); 5661 ret_val = -E1000_ERR_CONFIG; 5662 } 5663 } 5664 5665 return ret_val; 5666 } 5667 5668 /** 5669 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5670 * @hw: pointer to the HW structure 5671 * 5672 * In the case of a PHY power down to save power, or to turn off link during a 5673 * driver unload, or wake on lan is not enabled, remove the link. 5674 **/ 5675 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5676 { 5677 /* If the management interface is not enabled, then power down */ 5678 if (!(hw->mac.ops.check_mng_mode(hw) || 5679 hw->phy.ops.check_reset_block(hw))) 5680 e1000_power_down_phy_copper(hw); 5681 } 5682 5683 /** 5684 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5685 * @hw: pointer to the HW structure 5686 * 5687 * Clears hardware counters specific to the silicon family and calls 5688 * clear_hw_cntrs_generic to clear all general purpose counters. 5689 **/ 5690 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5691 { 5692 u16 phy_data; 5693 s32 ret_val; 5694 5695 e1000e_clear_hw_cntrs_base(hw); 5696 5697 er32(ALGNERRC); 5698 er32(RXERRC); 5699 er32(TNCRS); 5700 er32(CEXTERR); 5701 er32(TSCTC); 5702 er32(TSCTFC); 5703 5704 er32(MGTPRC); 5705 er32(MGTPDC); 5706 er32(MGTPTC); 5707 5708 er32(IAC); 5709 er32(ICRXOC); 5710 5711 /* Clear PHY statistics registers */ 5712 if ((hw->phy.type == e1000_phy_82578) || 5713 (hw->phy.type == e1000_phy_82579) || 5714 (hw->phy.type == e1000_phy_i217) || 5715 (hw->phy.type == e1000_phy_82577)) { 5716 ret_val = hw->phy.ops.acquire(hw); 5717 if (ret_val) 5718 return; 5719 ret_val = hw->phy.ops.set_page(hw, 5720 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5721 if (ret_val) 5722 goto release; 5723 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5724 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5725 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5726 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5727 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5728 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5729 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5730 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5731 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5732 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5733 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5734 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5735 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5736 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5737 release: 5738 hw->phy.ops.release(hw); 5739 } 5740 } 5741 5742 static const struct e1000_mac_operations ich8_mac_ops = { 5743 /* check_mng_mode dependent on mac type */ 5744 .check_for_link = e1000_check_for_copper_link_ich8lan, 5745 /* cleanup_led dependent on mac type */ 5746 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5747 .get_bus_info = e1000_get_bus_info_ich8lan, 5748 .set_lan_id = e1000_set_lan_id_single_port, 5749 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5750 /* led_on dependent on mac type */ 5751 /* led_off dependent on mac type */ 5752 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5753 .reset_hw = e1000_reset_hw_ich8lan, 5754 .init_hw = e1000_init_hw_ich8lan, 5755 .setup_link = e1000_setup_link_ich8lan, 5756 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5757 /* id_led_init dependent on mac type */ 5758 .config_collision_dist = e1000e_config_collision_dist_generic, 5759 .rar_set = e1000e_rar_set_generic, 5760 .rar_get_count = e1000e_rar_get_count_generic, 5761 }; 5762 5763 static const struct e1000_phy_operations ich8_phy_ops = { 5764 .acquire = e1000_acquire_swflag_ich8lan, 5765 .check_reset_block = e1000_check_reset_block_ich8lan, 5766 .commit = NULL, 5767 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5768 .get_cable_length = e1000e_get_cable_length_igp_2, 5769 .read_reg = e1000e_read_phy_reg_igp, 5770 .release = e1000_release_swflag_ich8lan, 5771 .reset = e1000_phy_hw_reset_ich8lan, 5772 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5773 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5774 .write_reg = e1000e_write_phy_reg_igp, 5775 }; 5776 5777 static const struct e1000_nvm_operations ich8_nvm_ops = { 5778 .acquire = e1000_acquire_nvm_ich8lan, 5779 .read = e1000_read_nvm_ich8lan, 5780 .release = e1000_release_nvm_ich8lan, 5781 .reload = e1000e_reload_nvm_generic, 5782 .update = e1000_update_nvm_checksum_ich8lan, 5783 .valid_led_default = e1000_valid_led_default_ich8lan, 5784 .validate = e1000_validate_nvm_checksum_ich8lan, 5785 .write = e1000_write_nvm_ich8lan, 5786 }; 5787 5788 static const struct e1000_nvm_operations spt_nvm_ops = { 5789 .acquire = e1000_acquire_nvm_ich8lan, 5790 .release = e1000_release_nvm_ich8lan, 5791 .read = e1000_read_nvm_spt, 5792 .update = e1000_update_nvm_checksum_spt, 5793 .reload = e1000e_reload_nvm_generic, 5794 .valid_led_default = e1000_valid_led_default_ich8lan, 5795 .validate = e1000_validate_nvm_checksum_ich8lan, 5796 .write = e1000_write_nvm_ich8lan, 5797 }; 5798 5799 const struct e1000_info e1000_ich8_info = { 5800 .mac = e1000_ich8lan, 5801 .flags = FLAG_HAS_WOL 5802 | FLAG_IS_ICH 5803 | FLAG_HAS_CTRLEXT_ON_LOAD 5804 | FLAG_HAS_AMT 5805 | FLAG_HAS_FLASH 5806 | FLAG_APME_IN_WUC, 5807 .pba = 8, 5808 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5809 .get_variants = e1000_get_variants_ich8lan, 5810 .mac_ops = &ich8_mac_ops, 5811 .phy_ops = &ich8_phy_ops, 5812 .nvm_ops = &ich8_nvm_ops, 5813 }; 5814 5815 const struct e1000_info e1000_ich9_info = { 5816 .mac = e1000_ich9lan, 5817 .flags = FLAG_HAS_JUMBO_FRAMES 5818 | FLAG_IS_ICH 5819 | FLAG_HAS_WOL 5820 | FLAG_HAS_CTRLEXT_ON_LOAD 5821 | FLAG_HAS_AMT 5822 | FLAG_HAS_FLASH 5823 | FLAG_APME_IN_WUC, 5824 .pba = 18, 5825 .max_hw_frame_size = DEFAULT_JUMBO, 5826 .get_variants = e1000_get_variants_ich8lan, 5827 .mac_ops = &ich8_mac_ops, 5828 .phy_ops = &ich8_phy_ops, 5829 .nvm_ops = &ich8_nvm_ops, 5830 }; 5831 5832 const struct e1000_info e1000_ich10_info = { 5833 .mac = e1000_ich10lan, 5834 .flags = FLAG_HAS_JUMBO_FRAMES 5835 | FLAG_IS_ICH 5836 | FLAG_HAS_WOL 5837 | FLAG_HAS_CTRLEXT_ON_LOAD 5838 | FLAG_HAS_AMT 5839 | FLAG_HAS_FLASH 5840 | FLAG_APME_IN_WUC, 5841 .pba = 18, 5842 .max_hw_frame_size = DEFAULT_JUMBO, 5843 .get_variants = e1000_get_variants_ich8lan, 5844 .mac_ops = &ich8_mac_ops, 5845 .phy_ops = &ich8_phy_ops, 5846 .nvm_ops = &ich8_nvm_ops, 5847 }; 5848 5849 const struct e1000_info e1000_pch_info = { 5850 .mac = e1000_pchlan, 5851 .flags = FLAG_IS_ICH 5852 | FLAG_HAS_WOL 5853 | FLAG_HAS_CTRLEXT_ON_LOAD 5854 | FLAG_HAS_AMT 5855 | FLAG_HAS_FLASH 5856 | FLAG_HAS_JUMBO_FRAMES 5857 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5858 | FLAG_APME_IN_WUC, 5859 .flags2 = FLAG2_HAS_PHY_STATS, 5860 .pba = 26, 5861 .max_hw_frame_size = 4096, 5862 .get_variants = e1000_get_variants_ich8lan, 5863 .mac_ops = &ich8_mac_ops, 5864 .phy_ops = &ich8_phy_ops, 5865 .nvm_ops = &ich8_nvm_ops, 5866 }; 5867 5868 const struct e1000_info e1000_pch2_info = { 5869 .mac = e1000_pch2lan, 5870 .flags = FLAG_IS_ICH 5871 | FLAG_HAS_WOL 5872 | FLAG_HAS_HW_TIMESTAMP 5873 | FLAG_HAS_CTRLEXT_ON_LOAD 5874 | FLAG_HAS_AMT 5875 | FLAG_HAS_FLASH 5876 | FLAG_HAS_JUMBO_FRAMES 5877 | FLAG_APME_IN_WUC, 5878 .flags2 = FLAG2_HAS_PHY_STATS 5879 | FLAG2_HAS_EEE 5880 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5881 .pba = 26, 5882 .max_hw_frame_size = 9022, 5883 .get_variants = e1000_get_variants_ich8lan, 5884 .mac_ops = &ich8_mac_ops, 5885 .phy_ops = &ich8_phy_ops, 5886 .nvm_ops = &ich8_nvm_ops, 5887 }; 5888 5889 const struct e1000_info e1000_pch_lpt_info = { 5890 .mac = e1000_pch_lpt, 5891 .flags = FLAG_IS_ICH 5892 | FLAG_HAS_WOL 5893 | FLAG_HAS_HW_TIMESTAMP 5894 | FLAG_HAS_CTRLEXT_ON_LOAD 5895 | FLAG_HAS_AMT 5896 | FLAG_HAS_FLASH 5897 | FLAG_HAS_JUMBO_FRAMES 5898 | FLAG_APME_IN_WUC, 5899 .flags2 = FLAG2_HAS_PHY_STATS 5900 | FLAG2_HAS_EEE 5901 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5902 .pba = 26, 5903 .max_hw_frame_size = 9022, 5904 .get_variants = e1000_get_variants_ich8lan, 5905 .mac_ops = &ich8_mac_ops, 5906 .phy_ops = &ich8_phy_ops, 5907 .nvm_ops = &ich8_nvm_ops, 5908 }; 5909 5910 const struct e1000_info e1000_pch_spt_info = { 5911 .mac = e1000_pch_spt, 5912 .flags = FLAG_IS_ICH 5913 | FLAG_HAS_WOL 5914 | FLAG_HAS_HW_TIMESTAMP 5915 | FLAG_HAS_CTRLEXT_ON_LOAD 5916 | FLAG_HAS_AMT 5917 | FLAG_HAS_FLASH 5918 | FLAG_HAS_JUMBO_FRAMES 5919 | FLAG_APME_IN_WUC, 5920 .flags2 = FLAG2_HAS_PHY_STATS 5921 | FLAG2_HAS_EEE, 5922 .pba = 26, 5923 .max_hw_frame_size = 9022, 5924 .get_variants = e1000_get_variants_ich8lan, 5925 .mac_ops = &ich8_mac_ops, 5926 .phy_ops = &ich8_phy_ops, 5927 .nvm_ops = &spt_nvm_ops, 5928 }; 5929 5930 const struct e1000_info e1000_pch_cnp_info = { 5931 .mac = e1000_pch_cnp, 5932 .flags = FLAG_IS_ICH 5933 | FLAG_HAS_WOL 5934 | FLAG_HAS_HW_TIMESTAMP 5935 | FLAG_HAS_CTRLEXT_ON_LOAD 5936 | FLAG_HAS_AMT 5937 | FLAG_HAS_FLASH 5938 | FLAG_HAS_JUMBO_FRAMES 5939 | FLAG_APME_IN_WUC, 5940 .flags2 = FLAG2_HAS_PHY_STATS 5941 | FLAG2_HAS_EEE, 5942 .pba = 26, 5943 .max_hw_frame_size = 9022, 5944 .get_variants = e1000_get_variants_ich8lan, 5945 .mac_ops = &ich8_mac_ops, 5946 .phy_ops = &ich8_phy_ops, 5947 .nvm_ops = &spt_nvm_ops, 5948 }; 5949