1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Switching PHY interface always returns MDI error 226 * so disable retry mechanism to avoid wasting time 227 */ 228 e1000e_disable_phy_retry(hw); 229 230 /* Unforce SMBus mode in PHY */ 231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 234 235 e1000e_enable_phy_retry(hw); 236 237 /* Unforce SMBus mode in MAC */ 238 mac_reg = er32(CTRL_EXT); 239 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 240 ew32(CTRL_EXT, mac_reg); 241 } 242 } 243 244 return true; 245 } 246 247 /** 248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 249 * @hw: pointer to the HW structure 250 * 251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 252 * used to reset the PHY to a quiescent state when necessary. 253 **/ 254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 255 { 256 u32 mac_reg; 257 258 /* Set Phy Config Counter to 50msec */ 259 mac_reg = er32(FEXTNVM3); 260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 262 ew32(FEXTNVM3, mac_reg); 263 264 /* Toggle LANPHYPC Value bit */ 265 mac_reg = er32(CTRL); 266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 268 ew32(CTRL, mac_reg); 269 e1e_flush(); 270 usleep_range(10, 20); 271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 272 ew32(CTRL, mac_reg); 273 e1e_flush(); 274 275 if (hw->mac.type < e1000_pch_lpt) { 276 msleep(50); 277 } else { 278 u16 count = 20; 279 280 do { 281 usleep_range(5000, 6000); 282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 283 284 msleep(30); 285 } 286 } 287 288 /** 289 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 290 * @hw: pointer to the HW structure 291 * 292 * Workarounds/flow necessary for PHY initialization during driver load 293 * and resume paths. 294 **/ 295 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 296 { 297 struct e1000_adapter *adapter = hw->adapter; 298 u32 mac_reg, fwsm = er32(FWSM); 299 s32 ret_val; 300 301 /* Gate automatic PHY configuration by hardware on managed and 302 * non-managed 82579 and newer adapters. 303 */ 304 e1000_gate_hw_phy_config_ich8lan(hw, true); 305 306 /* It is not possible to be certain of the current state of ULP 307 * so forcibly disable it. 308 */ 309 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 310 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 311 if (ret_val) 312 e_warn("Failed to disable ULP\n"); 313 314 ret_val = hw->phy.ops.acquire(hw); 315 if (ret_val) { 316 e_dbg("Failed to initialize PHY flow\n"); 317 goto out; 318 } 319 320 /* There is no guarantee that the PHY is accessible at this time 321 * so disable retry mechanism to avoid wasting time 322 */ 323 e1000e_disable_phy_retry(hw); 324 325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 326 * inaccessible and resetting the PHY is not blocked, toggle the 327 * LANPHYPC Value bit to force the interconnect to PCIe mode. 328 */ 329 switch (hw->mac.type) { 330 case e1000_pch_lpt: 331 case e1000_pch_spt: 332 case e1000_pch_cnp: 333 case e1000_pch_tgp: 334 case e1000_pch_adp: 335 case e1000_pch_mtp: 336 case e1000_pch_lnp: 337 case e1000_pch_ptp: 338 case e1000_pch_nvp: 339 if (e1000_phy_is_accessible_pchlan(hw)) 340 break; 341 342 /* Before toggling LANPHYPC, see if PHY is accessible by 343 * forcing MAC to SMBus mode first. 344 */ 345 mac_reg = er32(CTRL_EXT); 346 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 347 ew32(CTRL_EXT, mac_reg); 348 349 /* Wait 50 milliseconds for MAC to finish any retries 350 * that it might be trying to perform from previous 351 * attempts to acknowledge any phy read requests. 352 */ 353 msleep(50); 354 355 fallthrough; 356 case e1000_pch2lan: 357 if (e1000_phy_is_accessible_pchlan(hw)) 358 break; 359 360 fallthrough; 361 case e1000_pchlan: 362 if ((hw->mac.type == e1000_pchlan) && 363 (fwsm & E1000_ICH_FWSM_FW_VALID)) 364 break; 365 366 if (hw->phy.ops.check_reset_block(hw)) { 367 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 368 ret_val = -E1000_ERR_PHY; 369 break; 370 } 371 372 /* Toggle LANPHYPC Value bit */ 373 e1000_toggle_lanphypc_pch_lpt(hw); 374 if (hw->mac.type >= e1000_pch_lpt) { 375 if (e1000_phy_is_accessible_pchlan(hw)) 376 break; 377 378 /* Toggling LANPHYPC brings the PHY out of SMBus mode 379 * so ensure that the MAC is also out of SMBus mode 380 */ 381 mac_reg = er32(CTRL_EXT); 382 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 383 ew32(CTRL_EXT, mac_reg); 384 385 if (e1000_phy_is_accessible_pchlan(hw)) 386 break; 387 388 ret_val = -E1000_ERR_PHY; 389 } 390 break; 391 default: 392 break; 393 } 394 395 e1000e_enable_phy_retry(hw); 396 397 hw->phy.ops.release(hw); 398 if (!ret_val) { 399 400 /* Check to see if able to reset PHY. Print error if not */ 401 if (hw->phy.ops.check_reset_block(hw)) { 402 e_err("Reset blocked by ME\n"); 403 goto out; 404 } 405 406 /* Reset the PHY before any access to it. Doing so, ensures 407 * that the PHY is in a known good state before we read/write 408 * PHY registers. The generic reset is sufficient here, 409 * because we haven't determined the PHY type yet. 410 */ 411 ret_val = e1000e_phy_hw_reset_generic(hw); 412 if (ret_val) 413 goto out; 414 415 /* On a successful reset, possibly need to wait for the PHY 416 * to quiesce to an accessible state before returning control 417 * to the calling function. If the PHY does not quiesce, then 418 * return E1000E_BLK_PHY_RESET, as this is the condition that 419 * the PHY is in. 420 */ 421 ret_val = hw->phy.ops.check_reset_block(hw); 422 if (ret_val) 423 e_err("ME blocked access to PHY after reset\n"); 424 } 425 426 out: 427 /* Ungate automatic PHY configuration on non-managed 82579 */ 428 if ((hw->mac.type == e1000_pch2lan) && 429 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 430 usleep_range(10000, 11000); 431 e1000_gate_hw_phy_config_ich8lan(hw, false); 432 } 433 434 return ret_val; 435 } 436 437 /** 438 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 439 * @hw: pointer to the HW structure 440 * 441 * Initialize family-specific PHY parameters and function pointers. 442 **/ 443 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 444 { 445 struct e1000_phy_info *phy = &hw->phy; 446 s32 ret_val; 447 448 phy->addr = 1; 449 phy->reset_delay_us = 100; 450 451 phy->ops.set_page = e1000_set_page_igp; 452 phy->ops.read_reg = e1000_read_phy_reg_hv; 453 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 454 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 455 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 456 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 457 phy->ops.write_reg = e1000_write_phy_reg_hv; 458 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 459 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 460 phy->ops.power_up = e1000_power_up_phy_copper; 461 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 462 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 463 464 phy->id = e1000_phy_unknown; 465 466 if (hw->mac.type == e1000_pch_mtp) { 467 phy->retry_count = 2; 468 e1000e_enable_phy_retry(hw); 469 } 470 471 ret_val = e1000_init_phy_workarounds_pchlan(hw); 472 if (ret_val) 473 return ret_val; 474 475 if (phy->id == e1000_phy_unknown) 476 switch (hw->mac.type) { 477 default: 478 ret_val = e1000e_get_phy_id(hw); 479 if (ret_val) 480 return ret_val; 481 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 482 break; 483 fallthrough; 484 case e1000_pch2lan: 485 case e1000_pch_lpt: 486 case e1000_pch_spt: 487 case e1000_pch_cnp: 488 case e1000_pch_tgp: 489 case e1000_pch_adp: 490 case e1000_pch_mtp: 491 case e1000_pch_lnp: 492 case e1000_pch_ptp: 493 case e1000_pch_nvp: 494 /* In case the PHY needs to be in mdio slow mode, 495 * set slow mode and try to get the PHY id again. 496 */ 497 ret_val = e1000_set_mdio_slow_mode_hv(hw); 498 if (ret_val) 499 return ret_val; 500 ret_val = e1000e_get_phy_id(hw); 501 if (ret_val) 502 return ret_val; 503 break; 504 } 505 phy->type = e1000e_get_phy_type_from_id(phy->id); 506 507 switch (phy->type) { 508 case e1000_phy_82577: 509 case e1000_phy_82579: 510 case e1000_phy_i217: 511 phy->ops.check_polarity = e1000_check_polarity_82577; 512 phy->ops.force_speed_duplex = 513 e1000_phy_force_speed_duplex_82577; 514 phy->ops.get_cable_length = e1000_get_cable_length_82577; 515 phy->ops.get_info = e1000_get_phy_info_82577; 516 phy->ops.commit = e1000e_phy_sw_reset; 517 break; 518 case e1000_phy_82578: 519 phy->ops.check_polarity = e1000_check_polarity_m88; 520 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 521 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 522 phy->ops.get_info = e1000e_get_phy_info_m88; 523 break; 524 default: 525 ret_val = -E1000_ERR_PHY; 526 break; 527 } 528 529 return ret_val; 530 } 531 532 /** 533 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 534 * @hw: pointer to the HW structure 535 * 536 * Initialize family-specific PHY parameters and function pointers. 537 **/ 538 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 539 { 540 struct e1000_phy_info *phy = &hw->phy; 541 s32 ret_val; 542 u16 i = 0; 543 544 phy->addr = 1; 545 phy->reset_delay_us = 100; 546 547 phy->ops.power_up = e1000_power_up_phy_copper; 548 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 549 550 /* We may need to do this twice - once for IGP and if that fails, 551 * we'll set BM func pointers and try again 552 */ 553 ret_val = e1000e_determine_phy_address(hw); 554 if (ret_val) { 555 phy->ops.write_reg = e1000e_write_phy_reg_bm; 556 phy->ops.read_reg = e1000e_read_phy_reg_bm; 557 ret_val = e1000e_determine_phy_address(hw); 558 if (ret_val) { 559 e_dbg("Cannot determine PHY addr. Erroring out\n"); 560 return ret_val; 561 } 562 } 563 564 phy->id = 0; 565 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 566 (i++ < 100)) { 567 usleep_range(1000, 1100); 568 ret_val = e1000e_get_phy_id(hw); 569 if (ret_val) 570 return ret_val; 571 } 572 573 /* Verify phy id */ 574 switch (phy->id) { 575 case IGP03E1000_E_PHY_ID: 576 phy->type = e1000_phy_igp_3; 577 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 578 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 579 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 580 phy->ops.get_info = e1000e_get_phy_info_igp; 581 phy->ops.check_polarity = e1000_check_polarity_igp; 582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 583 break; 584 case IFE_E_PHY_ID: 585 case IFE_PLUS_E_PHY_ID: 586 case IFE_C_E_PHY_ID: 587 phy->type = e1000_phy_ife; 588 phy->autoneg_mask = E1000_ALL_NOT_GIG; 589 phy->ops.get_info = e1000_get_phy_info_ife; 590 phy->ops.check_polarity = e1000_check_polarity_ife; 591 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 592 break; 593 case BME1000_E_PHY_ID: 594 phy->type = e1000_phy_bm; 595 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 596 phy->ops.read_reg = e1000e_read_phy_reg_bm; 597 phy->ops.write_reg = e1000e_write_phy_reg_bm; 598 phy->ops.commit = e1000e_phy_sw_reset; 599 phy->ops.get_info = e1000e_get_phy_info_m88; 600 phy->ops.check_polarity = e1000_check_polarity_m88; 601 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 602 break; 603 default: 604 return -E1000_ERR_PHY; 605 } 606 607 return 0; 608 } 609 610 /** 611 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 612 * @hw: pointer to the HW structure 613 * 614 * Initialize family-specific NVM parameters and function 615 * pointers. 616 **/ 617 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 618 { 619 struct e1000_nvm_info *nvm = &hw->nvm; 620 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 621 u32 gfpreg, sector_base_addr, sector_end_addr; 622 u16 i; 623 u32 nvm_size; 624 625 nvm->type = e1000_nvm_flash_sw; 626 627 if (hw->mac.type >= e1000_pch_spt) { 628 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 629 * STRAP register. This is because in SPT the GbE Flash region 630 * is no longer accessed through the flash registers. Instead, 631 * the mechanism has changed, and the Flash region access 632 * registers are now implemented in GbE memory space. 633 */ 634 nvm->flash_base_addr = 0; 635 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 636 * NVM_SIZE_MULTIPLIER; 637 nvm->flash_bank_size = nvm_size / 2; 638 /* Adjust to word count */ 639 nvm->flash_bank_size /= sizeof(u16); 640 /* Set the base address for flash register access */ 641 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 642 } else { 643 /* Can't read flash registers if register set isn't mapped. */ 644 if (!hw->flash_address) { 645 e_dbg("ERROR: Flash registers not mapped\n"); 646 return -E1000_ERR_CONFIG; 647 } 648 649 gfpreg = er32flash(ICH_FLASH_GFPREG); 650 651 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 652 * Add 1 to sector_end_addr since this sector is included in 653 * the overall size. 654 */ 655 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 656 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 657 658 /* flash_base_addr is byte-aligned */ 659 nvm->flash_base_addr = sector_base_addr 660 << FLASH_SECTOR_ADDR_SHIFT; 661 662 /* find total size of the NVM, then cut in half since the total 663 * size represents two separate NVM banks. 664 */ 665 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 666 << FLASH_SECTOR_ADDR_SHIFT); 667 nvm->flash_bank_size /= 2; 668 /* Adjust to word count */ 669 nvm->flash_bank_size /= sizeof(u16); 670 } 671 672 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 673 674 /* Clear shadow ram */ 675 for (i = 0; i < nvm->word_size; i++) { 676 dev_spec->shadow_ram[i].modified = false; 677 dev_spec->shadow_ram[i].value = 0xFFFF; 678 } 679 680 return 0; 681 } 682 683 /** 684 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 685 * @hw: pointer to the HW structure 686 * 687 * Initialize family-specific MAC parameters and function 688 * pointers. 689 **/ 690 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 691 { 692 struct e1000_mac_info *mac = &hw->mac; 693 694 /* Set media type function pointer */ 695 hw->phy.media_type = e1000_media_type_copper; 696 697 /* Set mta register count */ 698 mac->mta_reg_count = 32; 699 /* Set rar entry count */ 700 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 701 if (mac->type == e1000_ich8lan) 702 mac->rar_entry_count--; 703 /* FWSM register */ 704 mac->has_fwsm = true; 705 /* ARC subsystem not supported */ 706 mac->arc_subsystem_valid = false; 707 /* Adaptive IFS supported */ 708 mac->adaptive_ifs = true; 709 710 /* LED and other operations */ 711 switch (mac->type) { 712 case e1000_ich8lan: 713 case e1000_ich9lan: 714 case e1000_ich10lan: 715 /* check management mode */ 716 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 717 /* ID LED init */ 718 mac->ops.id_led_init = e1000e_id_led_init_generic; 719 /* blink LED */ 720 mac->ops.blink_led = e1000e_blink_led_generic; 721 /* setup LED */ 722 mac->ops.setup_led = e1000e_setup_led_generic; 723 /* cleanup LED */ 724 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 725 /* turn on/off LED */ 726 mac->ops.led_on = e1000_led_on_ich8lan; 727 mac->ops.led_off = e1000_led_off_ich8lan; 728 break; 729 case e1000_pch2lan: 730 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 731 mac->ops.rar_set = e1000_rar_set_pch2lan; 732 fallthrough; 733 case e1000_pch_lpt: 734 case e1000_pch_spt: 735 case e1000_pch_cnp: 736 case e1000_pch_tgp: 737 case e1000_pch_adp: 738 case e1000_pch_mtp: 739 case e1000_pch_lnp: 740 case e1000_pch_ptp: 741 case e1000_pch_nvp: 742 case e1000_pchlan: 743 /* check management mode */ 744 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 745 /* ID LED init */ 746 mac->ops.id_led_init = e1000_id_led_init_pchlan; 747 /* setup LED */ 748 mac->ops.setup_led = e1000_setup_led_pchlan; 749 /* cleanup LED */ 750 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 751 /* turn on/off LED */ 752 mac->ops.led_on = e1000_led_on_pchlan; 753 mac->ops.led_off = e1000_led_off_pchlan; 754 break; 755 default: 756 break; 757 } 758 759 if (mac->type >= e1000_pch_lpt) { 760 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 761 mac->ops.rar_set = e1000_rar_set_pch_lpt; 762 mac->ops.setup_physical_interface = 763 e1000_setup_copper_link_pch_lpt; 764 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 765 } 766 767 /* Enable PCS Lock-loss workaround for ICH8 */ 768 if (mac->type == e1000_ich8lan) 769 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 770 771 return 0; 772 } 773 774 /** 775 * __e1000_access_emi_reg_locked - Read/write EMI register 776 * @hw: pointer to the HW structure 777 * @address: EMI address to program 778 * @data: pointer to value to read/write from/to the EMI address 779 * @read: boolean flag to indicate read or write 780 * 781 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 782 **/ 783 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 784 u16 *data, bool read) 785 { 786 s32 ret_val; 787 788 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 789 if (ret_val) 790 return ret_val; 791 792 if (read) 793 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 794 else 795 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 796 797 return ret_val; 798 } 799 800 /** 801 * e1000_read_emi_reg_locked - Read Extended Management Interface register 802 * @hw: pointer to the HW structure 803 * @addr: EMI address to program 804 * @data: value to be read from the EMI address 805 * 806 * Assumes the SW/FW/HW Semaphore is already acquired. 807 **/ 808 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 809 { 810 return __e1000_access_emi_reg_locked(hw, addr, data, true); 811 } 812 813 /** 814 * e1000_write_emi_reg_locked - Write Extended Management Interface register 815 * @hw: pointer to the HW structure 816 * @addr: EMI address to program 817 * @data: value to be written to the EMI address 818 * 819 * Assumes the SW/FW/HW Semaphore is already acquired. 820 **/ 821 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 822 { 823 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 824 } 825 826 /** 827 * e1000_set_eee_pchlan - Enable/disable EEE support 828 * @hw: pointer to the HW structure 829 * 830 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 831 * the link and the EEE capabilities of the link partner. The LPI Control 832 * register bits will remain set only if/when link is up. 833 * 834 * EEE LPI must not be asserted earlier than one second after link is up. 835 * On 82579, EEE LPI should not be enabled until such time otherwise there 836 * can be link issues with some switches. Other devices can have EEE LPI 837 * enabled immediately upon link up since they have a timer in hardware which 838 * prevents LPI from being asserted too early. 839 **/ 840 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 841 { 842 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 843 s32 ret_val; 844 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 845 846 switch (hw->phy.type) { 847 case e1000_phy_82579: 848 lpa = I82579_EEE_LP_ABILITY; 849 pcs_status = I82579_EEE_PCS_STATUS; 850 adv_addr = I82579_EEE_ADVERTISEMENT; 851 break; 852 case e1000_phy_i217: 853 lpa = I217_EEE_LP_ABILITY; 854 pcs_status = I217_EEE_PCS_STATUS; 855 adv_addr = I217_EEE_ADVERTISEMENT; 856 break; 857 default: 858 return 0; 859 } 860 861 ret_val = hw->phy.ops.acquire(hw); 862 if (ret_val) 863 return ret_val; 864 865 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 866 if (ret_val) 867 goto release; 868 869 /* Clear bits that enable EEE in various speeds */ 870 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 871 872 /* Enable EEE if not disabled by user */ 873 if (!dev_spec->eee_disable) { 874 /* Save off link partner's EEE ability */ 875 ret_val = e1000_read_emi_reg_locked(hw, lpa, 876 &dev_spec->eee_lp_ability); 877 if (ret_val) 878 goto release; 879 880 /* Read EEE advertisement */ 881 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 882 if (ret_val) 883 goto release; 884 885 /* Enable EEE only for speeds in which the link partner is 886 * EEE capable and for which we advertise EEE. 887 */ 888 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 889 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 890 891 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 892 e1e_rphy_locked(hw, MII_LPA, &data); 893 if (data & LPA_100FULL) 894 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 895 else 896 /* EEE is not supported in 100Half, so ignore 897 * partner's EEE in 100 ability if full-duplex 898 * is not advertised. 899 */ 900 dev_spec->eee_lp_ability &= 901 ~I82579_EEE_100_SUPPORTED; 902 } 903 } 904 905 if (hw->phy.type == e1000_phy_82579) { 906 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 907 &data); 908 if (ret_val) 909 goto release; 910 911 data &= ~I82579_LPI_100_PLL_SHUT; 912 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 913 data); 914 } 915 916 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 917 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 918 if (ret_val) 919 goto release; 920 921 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 922 release: 923 hw->phy.ops.release(hw); 924 925 return ret_val; 926 } 927 928 /** 929 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 930 * @hw: pointer to the HW structure 931 * @link: link up bool flag 932 * 933 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 934 * preventing further DMA write requests. Workaround the issue by disabling 935 * the de-assertion of the clock request when in 1Gpbs mode. 936 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 937 * speeds in order to avoid Tx hangs. 938 **/ 939 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 940 { 941 u32 fextnvm6 = er32(FEXTNVM6); 942 u32 status = er32(STATUS); 943 s32 ret_val = 0; 944 u16 reg; 945 946 if (link && (status & E1000_STATUS_SPEED_1000)) { 947 ret_val = hw->phy.ops.acquire(hw); 948 if (ret_val) 949 return ret_val; 950 951 ret_val = 952 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 953 ®); 954 if (ret_val) 955 goto release; 956 957 ret_val = 958 e1000e_write_kmrn_reg_locked(hw, 959 E1000_KMRNCTRLSTA_K1_CONFIG, 960 reg & 961 ~E1000_KMRNCTRLSTA_K1_ENABLE); 962 if (ret_val) 963 goto release; 964 965 usleep_range(10, 20); 966 967 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 968 969 ret_val = 970 e1000e_write_kmrn_reg_locked(hw, 971 E1000_KMRNCTRLSTA_K1_CONFIG, 972 reg); 973 release: 974 hw->phy.ops.release(hw); 975 } else { 976 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 977 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 978 979 if ((hw->phy.revision > 5) || !link || 980 ((status & E1000_STATUS_SPEED_100) && 981 (status & E1000_STATUS_FD))) 982 goto update_fextnvm6; 983 984 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 985 if (ret_val) 986 return ret_val; 987 988 /* Clear link status transmit timeout */ 989 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 990 991 if (status & E1000_STATUS_SPEED_100) { 992 /* Set inband Tx timeout to 5x10us for 100Half */ 993 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 994 995 /* Do not extend the K1 entry latency for 100Half */ 996 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 997 } else { 998 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 999 reg |= 50 << 1000 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 1001 1002 /* Extend the K1 entry latency for 10 Mbps */ 1003 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 1004 } 1005 1006 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 1007 if (ret_val) 1008 return ret_val; 1009 1010 update_fextnvm6: 1011 ew32(FEXTNVM6, fextnvm6); 1012 } 1013 1014 return ret_val; 1015 } 1016 1017 /** 1018 * e1000_platform_pm_pch_lpt - Set platform power management values 1019 * @hw: pointer to the HW structure 1020 * @link: bool indicating link status 1021 * 1022 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 1023 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 1024 * when link is up (which must not exceed the maximum latency supported 1025 * by the platform), otherwise specify there is no LTR requirement. 1026 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 1027 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1028 * Capability register set, on this device LTR is set by writing the 1029 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1030 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1031 * message to the PMC. 1032 **/ 1033 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1034 { 1035 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1036 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1037 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */ 1038 u32 lat_enc_d = 0; /* latency decoded */ 1039 u16 lat_enc = 0; /* latency encoded */ 1040 1041 if (link) { 1042 u16 speed, duplex, scale = 0; 1043 u16 max_snoop, max_nosnoop; 1044 u16 max_ltr_enc; /* max LTR latency encoded */ 1045 u64 value; 1046 u32 rxa; 1047 1048 if (!hw->adapter->max_frame_size) { 1049 e_dbg("max_frame_size not set.\n"); 1050 return -E1000_ERR_CONFIG; 1051 } 1052 1053 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1054 if (!speed) { 1055 e_dbg("Speed not set.\n"); 1056 return -E1000_ERR_CONFIG; 1057 } 1058 1059 /* Rx Packet Buffer Allocation size (KB) */ 1060 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1061 1062 /* Determine the maximum latency tolerated by the device. 1063 * 1064 * Per the PCIe spec, the tolerated latencies are encoded as 1065 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1066 * a 10-bit value (0-1023) to provide a range from 1 ns to 1067 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1068 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1069 */ 1070 rxa *= 512; 1071 value = (rxa > hw->adapter->max_frame_size) ? 1072 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1073 0; 1074 1075 while (value > PCI_LTR_VALUE_MASK) { 1076 scale++; 1077 value = DIV_ROUND_UP(value, BIT(5)); 1078 } 1079 if (scale > E1000_LTRV_SCALE_MAX) { 1080 e_dbg("Invalid LTR latency scale %d\n", scale); 1081 return -E1000_ERR_CONFIG; 1082 } 1083 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1084 1085 /* Determine the maximum latency tolerated by the platform */ 1086 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1087 &max_snoop); 1088 pci_read_config_word(hw->adapter->pdev, 1089 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1090 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1091 1092 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1093 (1U << (E1000_LTRV_SCALE_FACTOR * 1094 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1095 1096 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1097 (1U << (E1000_LTRV_SCALE_FACTOR * 1098 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1099 1100 if (lat_enc_d > max_ltr_enc_d) 1101 lat_enc = max_ltr_enc; 1102 } 1103 1104 /* Set Snoop and No-Snoop latencies the same */ 1105 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1106 ew32(LTRV, reg); 1107 1108 return 0; 1109 } 1110 1111 /** 1112 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode. 1113 * @hw: pointer to the HW structure 1114 * 1115 * Force the MAC and the PHY to SMBUS mode. Assumes semaphore already 1116 * acquired. 1117 * 1118 * Return: 0 on success, negative errno on failure. 1119 **/ 1120 static s32 e1000e_force_smbus(struct e1000_hw *hw) 1121 { 1122 u16 smb_ctrl = 0; 1123 u32 ctrl_ext; 1124 s32 ret_val; 1125 1126 /* Switching PHY interface always returns MDI error 1127 * so disable retry mechanism to avoid wasting time 1128 */ 1129 e1000e_disable_phy_retry(hw); 1130 1131 /* Force SMBus mode in the PHY */ 1132 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); 1133 if (ret_val) { 1134 e1000e_enable_phy_retry(hw); 1135 return ret_val; 1136 } 1137 1138 smb_ctrl |= CV_SMB_CTRL_FORCE_SMBUS; 1139 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); 1140 1141 e1000e_enable_phy_retry(hw); 1142 1143 /* Force SMBus mode in the MAC */ 1144 ctrl_ext = er32(CTRL_EXT); 1145 ctrl_ext |= E1000_CTRL_EXT_FORCE_SMBUS; 1146 ew32(CTRL_EXT, ctrl_ext); 1147 1148 return 0; 1149 } 1150 1151 /** 1152 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1153 * @hw: pointer to the HW structure 1154 * @to_sx: boolean indicating a system power state transition to Sx 1155 * 1156 * When link is down, configure ULP mode to significantly reduce the power 1157 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1158 * ME firmware to start the ULP configuration. If not on an ME enabled 1159 * system, configure the ULP mode by software. 1160 */ 1161 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1162 { 1163 u32 mac_reg; 1164 s32 ret_val = 0; 1165 u16 phy_reg; 1166 u16 oem_reg = 0; 1167 1168 if ((hw->mac.type < e1000_pch_lpt) || 1169 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1170 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1171 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1172 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1173 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1174 return 0; 1175 1176 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1177 /* Request ME configure ULP mode in the PHY */ 1178 mac_reg = er32(H2ME); 1179 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1180 ew32(H2ME, mac_reg); 1181 1182 goto out; 1183 } 1184 1185 if (!to_sx) { 1186 int i = 0; 1187 1188 /* Poll up to 5 seconds for Cable Disconnected indication */ 1189 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1190 /* Bail if link is re-acquired */ 1191 if (er32(STATUS) & E1000_STATUS_LU) 1192 return -E1000_ERR_PHY; 1193 1194 if (i++ == 100) 1195 break; 1196 1197 msleep(50); 1198 } 1199 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1200 (er32(FEXT) & 1201 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1202 } 1203 1204 ret_val = hw->phy.ops.acquire(hw); 1205 if (ret_val) 1206 goto out; 1207 1208 ret_val = e1000e_force_smbus(hw); 1209 if (ret_val) { 1210 e_dbg("Failed to force SMBUS: %d\n", ret_val); 1211 goto release; 1212 } 1213 1214 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1215 * LPLU and disable Gig speed when entering ULP 1216 */ 1217 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1218 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1219 &oem_reg); 1220 if (ret_val) 1221 goto release; 1222 1223 phy_reg = oem_reg; 1224 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1225 1226 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1227 phy_reg); 1228 1229 if (ret_val) 1230 goto release; 1231 } 1232 1233 /* Set Inband ULP Exit, Reset to SMBus mode and 1234 * Disable SMBus Release on PERST# in PHY 1235 */ 1236 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1237 if (ret_val) 1238 goto release; 1239 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1240 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1241 if (to_sx) { 1242 if (er32(WUFC) & E1000_WUFC_LNKC) 1243 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1244 else 1245 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1246 1247 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1248 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1249 } else { 1250 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1251 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1252 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1253 } 1254 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1255 1256 /* Set Disable SMBus Release on PERST# in MAC */ 1257 mac_reg = er32(FEXTNVM7); 1258 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1259 ew32(FEXTNVM7, mac_reg); 1260 1261 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1262 phy_reg |= I218_ULP_CONFIG1_START; 1263 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1264 1265 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1266 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1267 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1268 oem_reg); 1269 if (ret_val) 1270 goto release; 1271 } 1272 1273 release: 1274 hw->phy.ops.release(hw); 1275 out: 1276 if (ret_val) 1277 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1278 else 1279 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1280 1281 return ret_val; 1282 } 1283 1284 /** 1285 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1286 * @hw: pointer to the HW structure 1287 * @force: boolean indicating whether or not to force disabling ULP 1288 * 1289 * Un-configure ULP mode when link is up, the system is transitioned from 1290 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1291 * system, poll for an indication from ME that ULP has been un-configured. 1292 * If not on an ME enabled system, un-configure the ULP mode by software. 1293 * 1294 * During nominal operation, this function is called when link is acquired 1295 * to disable ULP mode (force=false); otherwise, for example when unloading 1296 * the driver or during Sx->S0 transitions, this is called with force=true 1297 * to forcibly disable ULP. 1298 */ 1299 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1300 { 1301 s32 ret_val = 0; 1302 u32 mac_reg; 1303 u16 phy_reg; 1304 int i = 0; 1305 1306 if ((hw->mac.type < e1000_pch_lpt) || 1307 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1308 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1309 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1310 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1311 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1312 return 0; 1313 1314 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1315 struct e1000_adapter *adapter = hw->adapter; 1316 bool firmware_bug = false; 1317 1318 if (force) { 1319 /* Request ME un-configure ULP mode in the PHY */ 1320 mac_reg = er32(H2ME); 1321 mac_reg &= ~E1000_H2ME_ULP; 1322 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1323 ew32(H2ME, mac_reg); 1324 } 1325 1326 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE. 1327 * If this takes more than 1 second, show a warning indicating a 1328 * firmware bug 1329 */ 1330 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1331 if (i++ == 250) { 1332 ret_val = -E1000_ERR_PHY; 1333 goto out; 1334 } 1335 if (i > 100 && !firmware_bug) 1336 firmware_bug = true; 1337 1338 usleep_range(10000, 11000); 1339 } 1340 if (firmware_bug) 1341 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n", 1342 i * 10); 1343 else 1344 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n", 1345 i * 10); 1346 1347 if (force) { 1348 mac_reg = er32(H2ME); 1349 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1350 ew32(H2ME, mac_reg); 1351 } else { 1352 /* Clear H2ME.ULP after ME ULP configuration */ 1353 mac_reg = er32(H2ME); 1354 mac_reg &= ~E1000_H2ME_ULP; 1355 ew32(H2ME, mac_reg); 1356 } 1357 1358 goto out; 1359 } 1360 1361 ret_val = hw->phy.ops.acquire(hw); 1362 if (ret_val) 1363 goto out; 1364 1365 if (force) 1366 /* Toggle LANPHYPC Value bit */ 1367 e1000_toggle_lanphypc_pch_lpt(hw); 1368 1369 /* Switching PHY interface always returns MDI error 1370 * so disable retry mechanism to avoid wasting time 1371 */ 1372 e1000e_disable_phy_retry(hw); 1373 1374 /* Unforce SMBus mode in PHY */ 1375 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1376 if (ret_val) { 1377 /* The MAC might be in PCIe mode, so temporarily force to 1378 * SMBus mode in order to access the PHY. 1379 */ 1380 mac_reg = er32(CTRL_EXT); 1381 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1382 ew32(CTRL_EXT, mac_reg); 1383 1384 msleep(50); 1385 1386 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1387 &phy_reg); 1388 if (ret_val) 1389 goto release; 1390 } 1391 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1392 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1393 1394 e1000e_enable_phy_retry(hw); 1395 1396 /* Unforce SMBus mode in MAC */ 1397 mac_reg = er32(CTRL_EXT); 1398 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1399 ew32(CTRL_EXT, mac_reg); 1400 1401 /* When ULP mode was previously entered, K1 was disabled by the 1402 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1403 */ 1404 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1405 if (ret_val) 1406 goto release; 1407 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1408 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1409 1410 /* Clear ULP enabled configuration */ 1411 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1412 if (ret_val) 1413 goto release; 1414 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1415 I218_ULP_CONFIG1_STICKY_ULP | 1416 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1417 I218_ULP_CONFIG1_WOL_HOST | 1418 I218_ULP_CONFIG1_INBAND_EXIT | 1419 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1420 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1421 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1422 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1423 1424 /* Commit ULP changes by starting auto ULP configuration */ 1425 phy_reg |= I218_ULP_CONFIG1_START; 1426 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1427 1428 /* Clear Disable SMBus Release on PERST# in MAC */ 1429 mac_reg = er32(FEXTNVM7); 1430 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1431 ew32(FEXTNVM7, mac_reg); 1432 1433 release: 1434 hw->phy.ops.release(hw); 1435 if (force) { 1436 e1000_phy_hw_reset(hw); 1437 msleep(50); 1438 } 1439 out: 1440 if (ret_val) 1441 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1442 else 1443 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1444 1445 return ret_val; 1446 } 1447 1448 /** 1449 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1450 * @hw: pointer to the HW structure 1451 * 1452 * Checks to see of the link status of the hardware has changed. If a 1453 * change in link status has been detected, then we read the PHY registers 1454 * to get the current speed/duplex if link exists. 1455 **/ 1456 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1457 { 1458 struct e1000_mac_info *mac = &hw->mac; 1459 s32 ret_val, tipg_reg = 0; 1460 u16 emi_addr, emi_val = 0; 1461 bool link; 1462 u16 phy_reg; 1463 1464 /* We only want to go out to the PHY registers to see if Auto-Neg 1465 * has completed and/or if our link status has changed. The 1466 * get_link_status flag is set upon receiving a Link Status 1467 * Change or Rx Sequence Error interrupt. 1468 */ 1469 if (!mac->get_link_status) 1470 return 0; 1471 mac->get_link_status = false; 1472 1473 /* First we want to see if the MII Status Register reports 1474 * link. If so, then we want to get the current speed/duplex 1475 * of the PHY. 1476 */ 1477 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1478 if (ret_val) 1479 goto out; 1480 1481 if (hw->mac.type == e1000_pchlan) { 1482 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1483 if (ret_val) 1484 goto out; 1485 } 1486 1487 /* When connected at 10Mbps half-duplex, some parts are excessively 1488 * aggressive resulting in many collisions. To avoid this, increase 1489 * the IPG and reduce Rx latency in the PHY. 1490 */ 1491 if ((hw->mac.type >= e1000_pch2lan) && link) { 1492 u16 speed, duplex; 1493 1494 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1495 tipg_reg = er32(TIPG); 1496 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1497 1498 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1499 tipg_reg |= 0xFF; 1500 /* Reduce Rx latency in analog PHY */ 1501 emi_val = 0; 1502 } else if (hw->mac.type >= e1000_pch_spt && 1503 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1504 tipg_reg |= 0xC; 1505 emi_val = 1; 1506 } else { 1507 1508 /* Roll back the default values */ 1509 tipg_reg |= 0x08; 1510 emi_val = 1; 1511 } 1512 1513 ew32(TIPG, tipg_reg); 1514 1515 ret_val = hw->phy.ops.acquire(hw); 1516 if (ret_val) 1517 goto out; 1518 1519 if (hw->mac.type == e1000_pch2lan) 1520 emi_addr = I82579_RX_CONFIG; 1521 else 1522 emi_addr = I217_RX_CONFIG; 1523 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1524 1525 if (hw->mac.type >= e1000_pch_lpt) { 1526 u16 phy_reg; 1527 1528 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1529 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1530 if (speed == SPEED_100 || speed == SPEED_10) 1531 phy_reg |= 0x3E8; 1532 else 1533 phy_reg |= 0xFA; 1534 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1535 1536 if (speed == SPEED_1000) { 1537 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1538 &phy_reg); 1539 1540 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1541 1542 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1543 phy_reg); 1544 } 1545 } 1546 hw->phy.ops.release(hw); 1547 1548 if (ret_val) 1549 goto out; 1550 1551 if (hw->mac.type >= e1000_pch_spt) { 1552 u16 data; 1553 u16 ptr_gap; 1554 1555 if (speed == SPEED_1000) { 1556 ret_val = hw->phy.ops.acquire(hw); 1557 if (ret_val) 1558 goto out; 1559 1560 ret_val = e1e_rphy_locked(hw, 1561 PHY_REG(776, 20), 1562 &data); 1563 if (ret_val) { 1564 hw->phy.ops.release(hw); 1565 goto out; 1566 } 1567 1568 ptr_gap = (data & (0x3FF << 2)) >> 2; 1569 if (ptr_gap < 0x18) { 1570 data &= ~(0x3FF << 2); 1571 data |= (0x18 << 2); 1572 ret_val = 1573 e1e_wphy_locked(hw, 1574 PHY_REG(776, 20), 1575 data); 1576 } 1577 hw->phy.ops.release(hw); 1578 if (ret_val) 1579 goto out; 1580 } else { 1581 ret_val = hw->phy.ops.acquire(hw); 1582 if (ret_val) 1583 goto out; 1584 1585 ret_val = e1e_wphy_locked(hw, 1586 PHY_REG(776, 20), 1587 0xC023); 1588 hw->phy.ops.release(hw); 1589 if (ret_val) 1590 goto out; 1591 1592 } 1593 } 1594 } 1595 1596 /* I217 Packet Loss issue: 1597 * ensure that FEXTNVM4 Beacon Duration is set correctly 1598 * on power up. 1599 * Set the Beacon Duration for I217 to 8 usec 1600 */ 1601 if (hw->mac.type >= e1000_pch_lpt) { 1602 u32 mac_reg; 1603 1604 mac_reg = er32(FEXTNVM4); 1605 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1606 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1607 ew32(FEXTNVM4, mac_reg); 1608 } 1609 1610 /* Work-around I218 hang issue */ 1611 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1612 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1613 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1614 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1615 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1616 if (ret_val) 1617 goto out; 1618 } 1619 if (hw->mac.type >= e1000_pch_lpt) { 1620 /* Set platform power management values for 1621 * Latency Tolerance Reporting (LTR) 1622 */ 1623 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1624 if (ret_val) 1625 goto out; 1626 } 1627 1628 /* Clear link partner's EEE ability */ 1629 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1630 1631 if (hw->mac.type >= e1000_pch_lpt) { 1632 u32 fextnvm6 = er32(FEXTNVM6); 1633 1634 if (hw->mac.type == e1000_pch_spt) { 1635 /* FEXTNVM6 K1-off workaround - for SPT only */ 1636 u32 pcieanacfg = er32(PCIEANACFG); 1637 1638 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1639 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1640 else 1641 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1642 } 1643 1644 ew32(FEXTNVM6, fextnvm6); 1645 } 1646 1647 if (!link) 1648 goto out; 1649 1650 switch (hw->mac.type) { 1651 case e1000_pch2lan: 1652 ret_val = e1000_k1_workaround_lv(hw); 1653 if (ret_val) 1654 return ret_val; 1655 fallthrough; 1656 case e1000_pchlan: 1657 if (hw->phy.type == e1000_phy_82578) { 1658 ret_val = e1000_link_stall_workaround_hv(hw); 1659 if (ret_val) 1660 return ret_val; 1661 } 1662 1663 /* Workaround for PCHx parts in half-duplex: 1664 * Set the number of preambles removed from the packet 1665 * when it is passed from the PHY to the MAC to prevent 1666 * the MAC from misinterpreting the packet type. 1667 */ 1668 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1669 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1670 1671 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1672 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1673 1674 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1675 break; 1676 default: 1677 break; 1678 } 1679 1680 /* Check if there was DownShift, must be checked 1681 * immediately after link-up 1682 */ 1683 e1000e_check_downshift(hw); 1684 1685 /* Enable/Disable EEE after link up */ 1686 if (hw->phy.type > e1000_phy_82579) { 1687 ret_val = e1000_set_eee_pchlan(hw); 1688 if (ret_val) 1689 return ret_val; 1690 } 1691 1692 /* If we are forcing speed/duplex, then we simply return since 1693 * we have already determined whether we have link or not. 1694 */ 1695 if (!mac->autoneg) 1696 return -E1000_ERR_CONFIG; 1697 1698 /* Auto-Neg is enabled. Auto Speed Detection takes care 1699 * of MAC speed/duplex configuration. So we only need to 1700 * configure Collision Distance in the MAC. 1701 */ 1702 mac->ops.config_collision_dist(hw); 1703 1704 /* Configure Flow Control now that Auto-Neg has completed. 1705 * First, we need to restore the desired flow control 1706 * settings because we may have had to re-autoneg with a 1707 * different link partner. 1708 */ 1709 ret_val = e1000e_config_fc_after_link_up(hw); 1710 if (ret_val) 1711 e_dbg("Error configuring flow control\n"); 1712 1713 return ret_val; 1714 1715 out: 1716 mac->get_link_status = true; 1717 return ret_val; 1718 } 1719 1720 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1721 { 1722 struct e1000_hw *hw = &adapter->hw; 1723 s32 rc; 1724 1725 rc = e1000_init_mac_params_ich8lan(hw); 1726 if (rc) 1727 return rc; 1728 1729 rc = e1000_init_nvm_params_ich8lan(hw); 1730 if (rc) 1731 return rc; 1732 1733 switch (hw->mac.type) { 1734 case e1000_ich8lan: 1735 case e1000_ich9lan: 1736 case e1000_ich10lan: 1737 rc = e1000_init_phy_params_ich8lan(hw); 1738 break; 1739 case e1000_pchlan: 1740 case e1000_pch2lan: 1741 case e1000_pch_lpt: 1742 case e1000_pch_spt: 1743 case e1000_pch_cnp: 1744 case e1000_pch_tgp: 1745 case e1000_pch_adp: 1746 case e1000_pch_mtp: 1747 case e1000_pch_lnp: 1748 case e1000_pch_ptp: 1749 case e1000_pch_nvp: 1750 rc = e1000_init_phy_params_pchlan(hw); 1751 break; 1752 default: 1753 break; 1754 } 1755 if (rc) 1756 return rc; 1757 1758 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1759 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1760 */ 1761 if ((adapter->hw.phy.type == e1000_phy_ife) || 1762 ((adapter->hw.mac.type >= e1000_pch2lan) && 1763 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1764 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1765 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1766 1767 hw->mac.ops.blink_led = NULL; 1768 } 1769 1770 if ((adapter->hw.mac.type == e1000_ich8lan) && 1771 (adapter->hw.phy.type != e1000_phy_ife)) 1772 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1773 1774 /* Enable workaround for 82579 w/ ME enabled */ 1775 if ((adapter->hw.mac.type == e1000_pch2lan) && 1776 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1777 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1778 1779 return 0; 1780 } 1781 1782 static DEFINE_MUTEX(nvm_mutex); 1783 1784 /** 1785 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1786 * @hw: pointer to the HW structure 1787 * 1788 * Acquires the mutex for performing NVM operations. 1789 **/ 1790 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1791 { 1792 mutex_lock(&nvm_mutex); 1793 1794 return 0; 1795 } 1796 1797 /** 1798 * e1000_release_nvm_ich8lan - Release NVM mutex 1799 * @hw: pointer to the HW structure 1800 * 1801 * Releases the mutex used while performing NVM operations. 1802 **/ 1803 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1804 { 1805 mutex_unlock(&nvm_mutex); 1806 } 1807 1808 /** 1809 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1810 * @hw: pointer to the HW structure 1811 * 1812 * Acquires the software control flag for performing PHY and select 1813 * MAC CSR accesses. 1814 **/ 1815 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1816 { 1817 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1818 s32 ret_val = 0; 1819 1820 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1821 &hw->adapter->state)) { 1822 e_dbg("contention for Phy access\n"); 1823 return -E1000_ERR_PHY; 1824 } 1825 1826 while (timeout) { 1827 extcnf_ctrl = er32(EXTCNF_CTRL); 1828 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1829 break; 1830 1831 mdelay(1); 1832 timeout--; 1833 } 1834 1835 if (!timeout) { 1836 e_dbg("SW has already locked the resource.\n"); 1837 ret_val = -E1000_ERR_CONFIG; 1838 goto out; 1839 } 1840 1841 timeout = SW_FLAG_TIMEOUT; 1842 1843 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1844 ew32(EXTCNF_CTRL, extcnf_ctrl); 1845 1846 while (timeout) { 1847 extcnf_ctrl = er32(EXTCNF_CTRL); 1848 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1849 break; 1850 1851 mdelay(1); 1852 timeout--; 1853 } 1854 1855 if (!timeout) { 1856 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1857 er32(FWSM), extcnf_ctrl); 1858 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1859 ew32(EXTCNF_CTRL, extcnf_ctrl); 1860 ret_val = -E1000_ERR_CONFIG; 1861 goto out; 1862 } 1863 1864 out: 1865 if (ret_val) 1866 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1867 1868 return ret_val; 1869 } 1870 1871 /** 1872 * e1000_release_swflag_ich8lan - Release software control flag 1873 * @hw: pointer to the HW structure 1874 * 1875 * Releases the software control flag for performing PHY and select 1876 * MAC CSR accesses. 1877 **/ 1878 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1879 { 1880 u32 extcnf_ctrl; 1881 1882 extcnf_ctrl = er32(EXTCNF_CTRL); 1883 1884 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1885 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1886 ew32(EXTCNF_CTRL, extcnf_ctrl); 1887 } else { 1888 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1889 } 1890 1891 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1892 } 1893 1894 /** 1895 * e1000_check_mng_mode_ich8lan - Checks management mode 1896 * @hw: pointer to the HW structure 1897 * 1898 * This checks if the adapter has any manageability enabled. 1899 * This is a function pointer entry point only called by read/write 1900 * routines for the PHY and NVM parts. 1901 **/ 1902 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1903 { 1904 u32 fwsm; 1905 1906 fwsm = er32(FWSM); 1907 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1908 ((fwsm & E1000_FWSM_MODE_MASK) == 1909 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1910 } 1911 1912 /** 1913 * e1000_check_mng_mode_pchlan - Checks management mode 1914 * @hw: pointer to the HW structure 1915 * 1916 * This checks if the adapter has iAMT enabled. 1917 * This is a function pointer entry point only called by read/write 1918 * routines for the PHY and NVM parts. 1919 **/ 1920 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1921 { 1922 u32 fwsm; 1923 1924 fwsm = er32(FWSM); 1925 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1926 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1927 } 1928 1929 /** 1930 * e1000_rar_set_pch2lan - Set receive address register 1931 * @hw: pointer to the HW structure 1932 * @addr: pointer to the receive address 1933 * @index: receive address array register 1934 * 1935 * Sets the receive address array register at index to the address passed 1936 * in by addr. For 82579, RAR[0] is the base address register that is to 1937 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1938 * Use SHRA[0-3] in place of those reserved for ME. 1939 **/ 1940 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1941 { 1942 u32 rar_low, rar_high; 1943 1944 /* HW expects these in little endian so we reverse the byte order 1945 * from network order (big endian) to little endian 1946 */ 1947 rar_low = ((u32)addr[0] | 1948 ((u32)addr[1] << 8) | 1949 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1950 1951 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1952 1953 /* If MAC address zero, no need to set the AV bit */ 1954 if (rar_low || rar_high) 1955 rar_high |= E1000_RAH_AV; 1956 1957 if (index == 0) { 1958 ew32(RAL(index), rar_low); 1959 e1e_flush(); 1960 ew32(RAH(index), rar_high); 1961 e1e_flush(); 1962 return 0; 1963 } 1964 1965 /* RAR[1-6] are owned by manageability. Skip those and program the 1966 * next address into the SHRA register array. 1967 */ 1968 if (index < (u32)(hw->mac.rar_entry_count)) { 1969 s32 ret_val; 1970 1971 ret_val = e1000_acquire_swflag_ich8lan(hw); 1972 if (ret_val) 1973 goto out; 1974 1975 ew32(SHRAL(index - 1), rar_low); 1976 e1e_flush(); 1977 ew32(SHRAH(index - 1), rar_high); 1978 e1e_flush(); 1979 1980 e1000_release_swflag_ich8lan(hw); 1981 1982 /* verify the register updates */ 1983 if ((er32(SHRAL(index - 1)) == rar_low) && 1984 (er32(SHRAH(index - 1)) == rar_high)) 1985 return 0; 1986 1987 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1988 (index - 1), er32(FWSM)); 1989 } 1990 1991 out: 1992 e_dbg("Failed to write receive address at index %d\n", index); 1993 return -E1000_ERR_CONFIG; 1994 } 1995 1996 /** 1997 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1998 * @hw: pointer to the HW structure 1999 * 2000 * Get the number of available receive registers that the Host can 2001 * program. SHRA[0-10] are the shared receive address registers 2002 * that are shared between the Host and manageability engine (ME). 2003 * ME can reserve any number of addresses and the host needs to be 2004 * able to tell how many available registers it has access to. 2005 **/ 2006 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 2007 { 2008 u32 wlock_mac; 2009 u32 num_entries; 2010 2011 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2012 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2013 2014 switch (wlock_mac) { 2015 case 0: 2016 /* All SHRA[0..10] and RAR[0] available */ 2017 num_entries = hw->mac.rar_entry_count; 2018 break; 2019 case 1: 2020 /* Only RAR[0] available */ 2021 num_entries = 1; 2022 break; 2023 default: 2024 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 2025 num_entries = wlock_mac + 1; 2026 break; 2027 } 2028 2029 return num_entries; 2030 } 2031 2032 /** 2033 * e1000_rar_set_pch_lpt - Set receive address registers 2034 * @hw: pointer to the HW structure 2035 * @addr: pointer to the receive address 2036 * @index: receive address array register 2037 * 2038 * Sets the receive address register array at index to the address passed 2039 * in by addr. For LPT, RAR[0] is the base address register that is to 2040 * contain the MAC address. SHRA[0-10] are the shared receive address 2041 * registers that are shared between the Host and manageability engine (ME). 2042 **/ 2043 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 2044 { 2045 u32 rar_low, rar_high; 2046 u32 wlock_mac; 2047 2048 /* HW expects these in little endian so we reverse the byte order 2049 * from network order (big endian) to little endian 2050 */ 2051 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 2052 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 2053 2054 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 2055 2056 /* If MAC address zero, no need to set the AV bit */ 2057 if (rar_low || rar_high) 2058 rar_high |= E1000_RAH_AV; 2059 2060 if (index == 0) { 2061 ew32(RAL(index), rar_low); 2062 e1e_flush(); 2063 ew32(RAH(index), rar_high); 2064 e1e_flush(); 2065 return 0; 2066 } 2067 2068 /* The manageability engine (ME) can lock certain SHRAR registers that 2069 * it is using - those registers are unavailable for use. 2070 */ 2071 if (index < hw->mac.rar_entry_count) { 2072 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 2073 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 2074 2075 /* Check if all SHRAR registers are locked */ 2076 if (wlock_mac == 1) 2077 goto out; 2078 2079 if ((wlock_mac == 0) || (index <= wlock_mac)) { 2080 s32 ret_val; 2081 2082 ret_val = e1000_acquire_swflag_ich8lan(hw); 2083 2084 if (ret_val) 2085 goto out; 2086 2087 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 2088 e1e_flush(); 2089 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 2090 e1e_flush(); 2091 2092 e1000_release_swflag_ich8lan(hw); 2093 2094 /* verify the register updates */ 2095 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2096 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2097 return 0; 2098 } 2099 } 2100 2101 out: 2102 e_dbg("Failed to write receive address at index %d\n", index); 2103 return -E1000_ERR_CONFIG; 2104 } 2105 2106 /** 2107 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2108 * @hw: pointer to the HW structure 2109 * 2110 * Checks if firmware is blocking the reset of the PHY. 2111 * This is a function pointer entry point only called by 2112 * reset routines. 2113 **/ 2114 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2115 { 2116 bool blocked = false; 2117 int i = 0; 2118 2119 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2120 (i++ < 30)) 2121 usleep_range(10000, 11000); 2122 return blocked ? E1000_BLK_PHY_RESET : 0; 2123 } 2124 2125 /** 2126 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2127 * @hw: pointer to the HW structure 2128 * 2129 * Assumes semaphore already acquired. 2130 * 2131 **/ 2132 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2133 { 2134 u16 phy_data; 2135 u32 strap = er32(STRAP); 2136 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2137 s32 ret_val; 2138 2139 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2140 2141 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2142 if (ret_val) 2143 return ret_val; 2144 2145 phy_data &= ~HV_SMB_ADDR_MASK; 2146 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2147 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2148 2149 if (hw->phy.type == e1000_phy_i217) { 2150 /* Restore SMBus frequency */ 2151 if (freq--) { 2152 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2153 phy_data |= (freq & BIT(0)) << 2154 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2155 phy_data |= (freq & BIT(1)) << 2156 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2157 } else { 2158 e_dbg("Unsupported SMB frequency in PHY\n"); 2159 } 2160 } 2161 2162 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2163 } 2164 2165 /** 2166 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2167 * @hw: pointer to the HW structure 2168 * 2169 * SW should configure the LCD from the NVM extended configuration region 2170 * as a workaround for certain parts. 2171 **/ 2172 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2173 { 2174 struct e1000_phy_info *phy = &hw->phy; 2175 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2176 s32 ret_val = 0; 2177 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2178 2179 /* Initialize the PHY from the NVM on ICH platforms. This 2180 * is needed due to an issue where the NVM configuration is 2181 * not properly autoloaded after power transitions. 2182 * Therefore, after each PHY reset, we will load the 2183 * configuration data out of the NVM manually. 2184 */ 2185 switch (hw->mac.type) { 2186 case e1000_ich8lan: 2187 if (phy->type != e1000_phy_igp_3) 2188 return ret_val; 2189 2190 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2191 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2192 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2193 break; 2194 } 2195 fallthrough; 2196 case e1000_pchlan: 2197 case e1000_pch2lan: 2198 case e1000_pch_lpt: 2199 case e1000_pch_spt: 2200 case e1000_pch_cnp: 2201 case e1000_pch_tgp: 2202 case e1000_pch_adp: 2203 case e1000_pch_mtp: 2204 case e1000_pch_lnp: 2205 case e1000_pch_ptp: 2206 case e1000_pch_nvp: 2207 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2208 break; 2209 default: 2210 return ret_val; 2211 } 2212 2213 ret_val = hw->phy.ops.acquire(hw); 2214 if (ret_val) 2215 return ret_val; 2216 2217 data = er32(FEXTNVM); 2218 if (!(data & sw_cfg_mask)) 2219 goto release; 2220 2221 /* Make sure HW does not configure LCD from PHY 2222 * extended configuration before SW configuration 2223 */ 2224 data = er32(EXTCNF_CTRL); 2225 if ((hw->mac.type < e1000_pch2lan) && 2226 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2227 goto release; 2228 2229 cnf_size = er32(EXTCNF_SIZE); 2230 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2231 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2232 if (!cnf_size) 2233 goto release; 2234 2235 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2236 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2237 2238 if (((hw->mac.type == e1000_pchlan) && 2239 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2240 (hw->mac.type > e1000_pchlan)) { 2241 /* HW configures the SMBus address and LEDs when the 2242 * OEM and LCD Write Enable bits are set in the NVM. 2243 * When both NVM bits are cleared, SW will configure 2244 * them instead. 2245 */ 2246 ret_val = e1000_write_smbus_addr(hw); 2247 if (ret_val) 2248 goto release; 2249 2250 data = er32(LEDCTL); 2251 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2252 (u16)data); 2253 if (ret_val) 2254 goto release; 2255 } 2256 2257 /* Configure LCD from extended configuration region. */ 2258 2259 /* cnf_base_addr is in DWORD */ 2260 word_addr = (u16)(cnf_base_addr << 1); 2261 2262 for (i = 0; i < cnf_size; i++) { 2263 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2264 if (ret_val) 2265 goto release; 2266 2267 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2268 1, ®_addr); 2269 if (ret_val) 2270 goto release; 2271 2272 /* Save off the PHY page for future writes. */ 2273 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2274 phy_page = reg_data; 2275 continue; 2276 } 2277 2278 reg_addr &= PHY_REG_MASK; 2279 reg_addr |= phy_page; 2280 2281 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2282 if (ret_val) 2283 goto release; 2284 } 2285 2286 release: 2287 hw->phy.ops.release(hw); 2288 return ret_val; 2289 } 2290 2291 /** 2292 * e1000_k1_gig_workaround_hv - K1 Si workaround 2293 * @hw: pointer to the HW structure 2294 * @link: link up bool flag 2295 * 2296 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2297 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2298 * If link is down, the function will restore the default K1 setting located 2299 * in the NVM. 2300 **/ 2301 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2302 { 2303 s32 ret_val = 0; 2304 u16 status_reg = 0; 2305 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2306 2307 if (hw->mac.type != e1000_pchlan) 2308 return 0; 2309 2310 /* Wrap the whole flow with the sw flag */ 2311 ret_val = hw->phy.ops.acquire(hw); 2312 if (ret_val) 2313 return ret_val; 2314 2315 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2316 if (link) { 2317 if (hw->phy.type == e1000_phy_82578) { 2318 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2319 &status_reg); 2320 if (ret_val) 2321 goto release; 2322 2323 status_reg &= (BM_CS_STATUS_LINK_UP | 2324 BM_CS_STATUS_RESOLVED | 2325 BM_CS_STATUS_SPEED_MASK); 2326 2327 if (status_reg == (BM_CS_STATUS_LINK_UP | 2328 BM_CS_STATUS_RESOLVED | 2329 BM_CS_STATUS_SPEED_1000)) 2330 k1_enable = false; 2331 } 2332 2333 if (hw->phy.type == e1000_phy_82577) { 2334 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2335 if (ret_val) 2336 goto release; 2337 2338 status_reg &= (HV_M_STATUS_LINK_UP | 2339 HV_M_STATUS_AUTONEG_COMPLETE | 2340 HV_M_STATUS_SPEED_MASK); 2341 2342 if (status_reg == (HV_M_STATUS_LINK_UP | 2343 HV_M_STATUS_AUTONEG_COMPLETE | 2344 HV_M_STATUS_SPEED_1000)) 2345 k1_enable = false; 2346 } 2347 2348 /* Link stall fix for link up */ 2349 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2350 if (ret_val) 2351 goto release; 2352 2353 } else { 2354 /* Link stall fix for link down */ 2355 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2356 if (ret_val) 2357 goto release; 2358 } 2359 2360 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2361 2362 release: 2363 hw->phy.ops.release(hw); 2364 2365 return ret_val; 2366 } 2367 2368 /** 2369 * e1000_configure_k1_ich8lan - Configure K1 power state 2370 * @hw: pointer to the HW structure 2371 * @k1_enable: K1 state to configure 2372 * 2373 * Configure the K1 power state based on the provided parameter. 2374 * Assumes semaphore already acquired. 2375 * 2376 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2377 **/ 2378 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2379 { 2380 s32 ret_val; 2381 u32 ctrl_reg = 0; 2382 u32 ctrl_ext = 0; 2383 u32 reg = 0; 2384 u16 kmrn_reg = 0; 2385 2386 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2387 &kmrn_reg); 2388 if (ret_val) 2389 return ret_val; 2390 2391 if (k1_enable) 2392 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2393 else 2394 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2395 2396 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2397 kmrn_reg); 2398 if (ret_val) 2399 return ret_val; 2400 2401 usleep_range(20, 40); 2402 ctrl_ext = er32(CTRL_EXT); 2403 ctrl_reg = er32(CTRL); 2404 2405 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2406 reg |= E1000_CTRL_FRCSPD; 2407 ew32(CTRL, reg); 2408 2409 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2410 e1e_flush(); 2411 usleep_range(20, 40); 2412 ew32(CTRL, ctrl_reg); 2413 ew32(CTRL_EXT, ctrl_ext); 2414 e1e_flush(); 2415 usleep_range(20, 40); 2416 2417 return 0; 2418 } 2419 2420 /** 2421 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2422 * @hw: pointer to the HW structure 2423 * @d0_state: boolean if entering d0 or d3 device state 2424 * 2425 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2426 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2427 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2428 **/ 2429 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2430 { 2431 s32 ret_val = 0; 2432 u32 mac_reg; 2433 u16 oem_reg; 2434 2435 if (hw->mac.type < e1000_pchlan) 2436 return ret_val; 2437 2438 ret_val = hw->phy.ops.acquire(hw); 2439 if (ret_val) 2440 return ret_val; 2441 2442 if (hw->mac.type == e1000_pchlan) { 2443 mac_reg = er32(EXTCNF_CTRL); 2444 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2445 goto release; 2446 } 2447 2448 mac_reg = er32(FEXTNVM); 2449 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2450 goto release; 2451 2452 mac_reg = er32(PHY_CTRL); 2453 2454 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2455 if (ret_val) 2456 goto release; 2457 2458 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2459 2460 if (d0_state) { 2461 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2462 oem_reg |= HV_OEM_BITS_GBE_DIS; 2463 2464 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2465 oem_reg |= HV_OEM_BITS_LPLU; 2466 } else { 2467 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2468 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2469 oem_reg |= HV_OEM_BITS_GBE_DIS; 2470 2471 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2472 E1000_PHY_CTRL_NOND0A_LPLU)) 2473 oem_reg |= HV_OEM_BITS_LPLU; 2474 } 2475 2476 /* Set Restart auto-neg to activate the bits */ 2477 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2478 !hw->phy.ops.check_reset_block(hw)) 2479 oem_reg |= HV_OEM_BITS_RESTART_AN; 2480 2481 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2482 2483 release: 2484 hw->phy.ops.release(hw); 2485 2486 return ret_val; 2487 } 2488 2489 /** 2490 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2491 * @hw: pointer to the HW structure 2492 **/ 2493 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2494 { 2495 s32 ret_val; 2496 u16 data; 2497 2498 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2499 if (ret_val) 2500 return ret_val; 2501 2502 data |= HV_KMRN_MDIO_SLOW; 2503 2504 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2505 2506 return ret_val; 2507 } 2508 2509 /** 2510 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2511 * @hw: pointer to the HW structure 2512 * 2513 * A series of PHY workarounds to be done after every PHY reset. 2514 **/ 2515 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2516 { 2517 s32 ret_val = 0; 2518 u16 phy_data; 2519 2520 if (hw->mac.type != e1000_pchlan) 2521 return 0; 2522 2523 /* Set MDIO slow mode before any other MDIO access */ 2524 if (hw->phy.type == e1000_phy_82577) { 2525 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2526 if (ret_val) 2527 return ret_val; 2528 } 2529 2530 if (((hw->phy.type == e1000_phy_82577) && 2531 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2532 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2533 /* Disable generation of early preamble */ 2534 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2535 if (ret_val) 2536 return ret_val; 2537 2538 /* Preamble tuning for SSC */ 2539 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2540 if (ret_val) 2541 return ret_val; 2542 } 2543 2544 if (hw->phy.type == e1000_phy_82578) { 2545 /* Return registers to default by doing a soft reset then 2546 * writing 0x3140 to the control register. 2547 */ 2548 if (hw->phy.revision < 2) { 2549 e1000e_phy_sw_reset(hw); 2550 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2551 if (ret_val) 2552 return ret_val; 2553 } 2554 } 2555 2556 /* Select page 0 */ 2557 ret_val = hw->phy.ops.acquire(hw); 2558 if (ret_val) 2559 return ret_val; 2560 2561 hw->phy.addr = 1; 2562 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2563 hw->phy.ops.release(hw); 2564 if (ret_val) 2565 return ret_val; 2566 2567 /* Configure the K1 Si workaround during phy reset assuming there is 2568 * link so that it disables K1 if link is in 1Gbps. 2569 */ 2570 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2571 if (ret_val) 2572 return ret_val; 2573 2574 /* Workaround for link disconnects on a busy hub in half duplex */ 2575 ret_val = hw->phy.ops.acquire(hw); 2576 if (ret_val) 2577 return ret_val; 2578 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2579 if (ret_val) 2580 goto release; 2581 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2582 if (ret_val) 2583 goto release; 2584 2585 /* set MSE higher to enable link to stay up when noise is high */ 2586 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2587 release: 2588 hw->phy.ops.release(hw); 2589 2590 return ret_val; 2591 } 2592 2593 /** 2594 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2595 * @hw: pointer to the HW structure 2596 **/ 2597 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2598 { 2599 u32 mac_reg; 2600 u16 i, phy_reg = 0; 2601 s32 ret_val; 2602 2603 ret_val = hw->phy.ops.acquire(hw); 2604 if (ret_val) 2605 return; 2606 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2607 if (ret_val) 2608 goto release; 2609 2610 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2611 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2612 mac_reg = er32(RAL(i)); 2613 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2614 (u16)(mac_reg & 0xFFFF)); 2615 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2616 (u16)((mac_reg >> 16) & 0xFFFF)); 2617 2618 mac_reg = er32(RAH(i)); 2619 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2620 (u16)(mac_reg & 0xFFFF)); 2621 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2622 (u16)((mac_reg & E1000_RAH_AV) >> 16)); 2623 } 2624 2625 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2626 2627 release: 2628 hw->phy.ops.release(hw); 2629 } 2630 2631 /** 2632 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2633 * with 82579 PHY 2634 * @hw: pointer to the HW structure 2635 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2636 **/ 2637 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2638 { 2639 s32 ret_val = 0; 2640 u16 phy_reg, data; 2641 u32 mac_reg; 2642 u16 i; 2643 2644 if (hw->mac.type < e1000_pch2lan) 2645 return 0; 2646 2647 /* disable Rx path while enabling/disabling workaround */ 2648 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2649 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2650 if (ret_val) 2651 return ret_val; 2652 2653 if (enable) { 2654 /* Write Rx addresses (rar_entry_count for RAL/H, and 2655 * SHRAL/H) and initial CRC values to the MAC 2656 */ 2657 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2658 u8 mac_addr[ETH_ALEN] = { 0 }; 2659 u32 addr_high, addr_low; 2660 2661 addr_high = er32(RAH(i)); 2662 if (!(addr_high & E1000_RAH_AV)) 2663 continue; 2664 addr_low = er32(RAL(i)); 2665 mac_addr[0] = (addr_low & 0xFF); 2666 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2667 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2668 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2669 mac_addr[4] = (addr_high & 0xFF); 2670 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2671 2672 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2673 } 2674 2675 /* Write Rx addresses to the PHY */ 2676 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2677 2678 /* Enable jumbo frame workaround in the MAC */ 2679 mac_reg = er32(FFLT_DBG); 2680 mac_reg &= ~BIT(14); 2681 mac_reg |= (7 << 15); 2682 ew32(FFLT_DBG, mac_reg); 2683 2684 mac_reg = er32(RCTL); 2685 mac_reg |= E1000_RCTL_SECRC; 2686 ew32(RCTL, mac_reg); 2687 2688 ret_val = e1000e_read_kmrn_reg(hw, 2689 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2690 &data); 2691 if (ret_val) 2692 return ret_val; 2693 ret_val = e1000e_write_kmrn_reg(hw, 2694 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2695 data | BIT(0)); 2696 if (ret_val) 2697 return ret_val; 2698 ret_val = e1000e_read_kmrn_reg(hw, 2699 E1000_KMRNCTRLSTA_HD_CTRL, 2700 &data); 2701 if (ret_val) 2702 return ret_val; 2703 data &= ~(0xF << 8); 2704 data |= (0xB << 8); 2705 ret_val = e1000e_write_kmrn_reg(hw, 2706 E1000_KMRNCTRLSTA_HD_CTRL, 2707 data); 2708 if (ret_val) 2709 return ret_val; 2710 2711 /* Enable jumbo frame workaround in the PHY */ 2712 e1e_rphy(hw, PHY_REG(769, 23), &data); 2713 data &= ~(0x7F << 5); 2714 data |= (0x37 << 5); 2715 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2716 if (ret_val) 2717 return ret_val; 2718 e1e_rphy(hw, PHY_REG(769, 16), &data); 2719 data &= ~BIT(13); 2720 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2721 if (ret_val) 2722 return ret_val; 2723 e1e_rphy(hw, PHY_REG(776, 20), &data); 2724 data &= ~(0x3FF << 2); 2725 data |= (E1000_TX_PTR_GAP << 2); 2726 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2727 if (ret_val) 2728 return ret_val; 2729 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2730 if (ret_val) 2731 return ret_val; 2732 e1e_rphy(hw, HV_PM_CTRL, &data); 2733 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2734 if (ret_val) 2735 return ret_val; 2736 } else { 2737 /* Write MAC register values back to h/w defaults */ 2738 mac_reg = er32(FFLT_DBG); 2739 mac_reg &= ~(0xF << 14); 2740 ew32(FFLT_DBG, mac_reg); 2741 2742 mac_reg = er32(RCTL); 2743 mac_reg &= ~E1000_RCTL_SECRC; 2744 ew32(RCTL, mac_reg); 2745 2746 ret_val = e1000e_read_kmrn_reg(hw, 2747 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2748 &data); 2749 if (ret_val) 2750 return ret_val; 2751 ret_val = e1000e_write_kmrn_reg(hw, 2752 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2753 data & ~BIT(0)); 2754 if (ret_val) 2755 return ret_val; 2756 ret_val = e1000e_read_kmrn_reg(hw, 2757 E1000_KMRNCTRLSTA_HD_CTRL, 2758 &data); 2759 if (ret_val) 2760 return ret_val; 2761 data &= ~(0xF << 8); 2762 data |= (0xB << 8); 2763 ret_val = e1000e_write_kmrn_reg(hw, 2764 E1000_KMRNCTRLSTA_HD_CTRL, 2765 data); 2766 if (ret_val) 2767 return ret_val; 2768 2769 /* Write PHY register values back to h/w defaults */ 2770 e1e_rphy(hw, PHY_REG(769, 23), &data); 2771 data &= ~(0x7F << 5); 2772 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2773 if (ret_val) 2774 return ret_val; 2775 e1e_rphy(hw, PHY_REG(769, 16), &data); 2776 data |= BIT(13); 2777 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2778 if (ret_val) 2779 return ret_val; 2780 e1e_rphy(hw, PHY_REG(776, 20), &data); 2781 data &= ~(0x3FF << 2); 2782 data |= (0x8 << 2); 2783 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2784 if (ret_val) 2785 return ret_val; 2786 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2787 if (ret_val) 2788 return ret_val; 2789 e1e_rphy(hw, HV_PM_CTRL, &data); 2790 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2791 if (ret_val) 2792 return ret_val; 2793 } 2794 2795 /* re-enable Rx path after enabling/disabling workaround */ 2796 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2797 } 2798 2799 /** 2800 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2801 * @hw: pointer to the HW structure 2802 * 2803 * A series of PHY workarounds to be done after every PHY reset. 2804 **/ 2805 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2806 { 2807 s32 ret_val = 0; 2808 2809 if (hw->mac.type != e1000_pch2lan) 2810 return 0; 2811 2812 /* Set MDIO slow mode before any other MDIO access */ 2813 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2814 if (ret_val) 2815 return ret_val; 2816 2817 ret_val = hw->phy.ops.acquire(hw); 2818 if (ret_val) 2819 return ret_val; 2820 /* set MSE higher to enable link to stay up when noise is high */ 2821 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2822 if (ret_val) 2823 goto release; 2824 /* drop link after 5 times MSE threshold was reached */ 2825 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2826 release: 2827 hw->phy.ops.release(hw); 2828 2829 return ret_val; 2830 } 2831 2832 /** 2833 * e1000_k1_workaround_lv - K1 Si workaround 2834 * @hw: pointer to the HW structure 2835 * 2836 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2837 * Disable K1 in 1000Mbps and 100Mbps 2838 **/ 2839 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2840 { 2841 s32 ret_val = 0; 2842 u16 status_reg = 0; 2843 2844 if (hw->mac.type != e1000_pch2lan) 2845 return 0; 2846 2847 /* Set K1 beacon duration based on 10Mbs speed */ 2848 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2849 if (ret_val) 2850 return ret_val; 2851 2852 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2853 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2854 if (status_reg & 2855 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2856 u16 pm_phy_reg; 2857 2858 /* LV 1G/100 Packet drop issue wa */ 2859 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2860 if (ret_val) 2861 return ret_val; 2862 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2863 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2864 if (ret_val) 2865 return ret_val; 2866 } else { 2867 u32 mac_reg; 2868 2869 mac_reg = er32(FEXTNVM4); 2870 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2871 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2872 ew32(FEXTNVM4, mac_reg); 2873 } 2874 } 2875 2876 return ret_val; 2877 } 2878 2879 /** 2880 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2881 * @hw: pointer to the HW structure 2882 * @gate: boolean set to true to gate, false to ungate 2883 * 2884 * Gate/ungate the automatic PHY configuration via hardware; perform 2885 * the configuration via software instead. 2886 **/ 2887 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2888 { 2889 u32 extcnf_ctrl; 2890 2891 if (hw->mac.type < e1000_pch2lan) 2892 return; 2893 2894 extcnf_ctrl = er32(EXTCNF_CTRL); 2895 2896 if (gate) 2897 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2898 else 2899 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2900 2901 ew32(EXTCNF_CTRL, extcnf_ctrl); 2902 } 2903 2904 /** 2905 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2906 * @hw: pointer to the HW structure 2907 * 2908 * Check the appropriate indication the MAC has finished configuring the 2909 * PHY after a software reset. 2910 **/ 2911 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2912 { 2913 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2914 2915 /* Wait for basic configuration completes before proceeding */ 2916 do { 2917 data = er32(STATUS); 2918 data &= E1000_STATUS_LAN_INIT_DONE; 2919 usleep_range(100, 200); 2920 } while ((!data) && --loop); 2921 2922 /* If basic configuration is incomplete before the above loop 2923 * count reaches 0, loading the configuration from NVM will 2924 * leave the PHY in a bad state possibly resulting in no link. 2925 */ 2926 if (loop == 0) 2927 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2928 2929 /* Clear the Init Done bit for the next init event */ 2930 data = er32(STATUS); 2931 data &= ~E1000_STATUS_LAN_INIT_DONE; 2932 ew32(STATUS, data); 2933 } 2934 2935 /** 2936 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2937 * @hw: pointer to the HW structure 2938 **/ 2939 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2940 { 2941 s32 ret_val = 0; 2942 u16 reg; 2943 2944 if (hw->phy.ops.check_reset_block(hw)) 2945 return 0; 2946 2947 /* Allow time for h/w to get to quiescent state after reset */ 2948 usleep_range(10000, 11000); 2949 2950 /* Perform any necessary post-reset workarounds */ 2951 switch (hw->mac.type) { 2952 case e1000_pchlan: 2953 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2954 if (ret_val) 2955 return ret_val; 2956 break; 2957 case e1000_pch2lan: 2958 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2959 if (ret_val) 2960 return ret_val; 2961 break; 2962 default: 2963 break; 2964 } 2965 2966 /* Clear the host wakeup bit after lcd reset */ 2967 if (hw->mac.type >= e1000_pchlan) { 2968 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2969 reg &= ~BM_WUC_HOST_WU_BIT; 2970 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2971 } 2972 2973 /* Configure the LCD with the extended configuration region in NVM */ 2974 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2975 if (ret_val) 2976 return ret_val; 2977 2978 /* Configure the LCD with the OEM bits in NVM */ 2979 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2980 2981 if (hw->mac.type == e1000_pch2lan) { 2982 /* Ungate automatic PHY configuration on non-managed 82579 */ 2983 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2984 usleep_range(10000, 11000); 2985 e1000_gate_hw_phy_config_ich8lan(hw, false); 2986 } 2987 2988 /* Set EEE LPI Update Timer to 200usec */ 2989 ret_val = hw->phy.ops.acquire(hw); 2990 if (ret_val) 2991 return ret_val; 2992 ret_val = e1000_write_emi_reg_locked(hw, 2993 I82579_LPI_UPDATE_TIMER, 2994 0x1387); 2995 hw->phy.ops.release(hw); 2996 } 2997 2998 return ret_val; 2999 } 3000 3001 /** 3002 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 3003 * @hw: pointer to the HW structure 3004 * 3005 * Resets the PHY 3006 * This is a function pointer entry point called by drivers 3007 * or other shared routines. 3008 **/ 3009 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 3010 { 3011 s32 ret_val = 0; 3012 3013 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 3014 if ((hw->mac.type == e1000_pch2lan) && 3015 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 3016 e1000_gate_hw_phy_config_ich8lan(hw, true); 3017 3018 ret_val = e1000e_phy_hw_reset_generic(hw); 3019 if (ret_val) 3020 return ret_val; 3021 3022 return e1000_post_phy_reset_ich8lan(hw); 3023 } 3024 3025 /** 3026 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 3027 * @hw: pointer to the HW structure 3028 * @active: true to enable LPLU, false to disable 3029 * 3030 * Sets the LPLU state according to the active flag. For PCH, if OEM write 3031 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 3032 * the phy speed. This function will manually set the LPLU bit and restart 3033 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 3034 * since it configures the same bit. 3035 **/ 3036 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 3037 { 3038 s32 ret_val; 3039 u16 oem_reg; 3040 3041 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 3042 if (ret_val) 3043 return ret_val; 3044 3045 if (active) 3046 oem_reg |= HV_OEM_BITS_LPLU; 3047 else 3048 oem_reg &= ~HV_OEM_BITS_LPLU; 3049 3050 if (!hw->phy.ops.check_reset_block(hw)) 3051 oem_reg |= HV_OEM_BITS_RESTART_AN; 3052 3053 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 3054 } 3055 3056 /** 3057 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 3058 * @hw: pointer to the HW structure 3059 * @active: true to enable LPLU, false to disable 3060 * 3061 * Sets the LPLU D0 state according to the active flag. When 3062 * activating LPLU this function also disables smart speed 3063 * and vice versa. LPLU will not be activated unless the 3064 * device autonegotiation advertisement meets standards of 3065 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3066 * This is a function pointer entry point only called by 3067 * PHY setup routines. 3068 **/ 3069 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3070 { 3071 struct e1000_phy_info *phy = &hw->phy; 3072 u32 phy_ctrl; 3073 s32 ret_val = 0; 3074 u16 data; 3075 3076 if (phy->type == e1000_phy_ife) 3077 return 0; 3078 3079 phy_ctrl = er32(PHY_CTRL); 3080 3081 if (active) { 3082 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 3083 ew32(PHY_CTRL, phy_ctrl); 3084 3085 if (phy->type != e1000_phy_igp_3) 3086 return 0; 3087 3088 /* Call gig speed drop workaround on LPLU before accessing 3089 * any PHY registers 3090 */ 3091 if (hw->mac.type == e1000_ich8lan) 3092 e1000e_gig_downshift_workaround_ich8lan(hw); 3093 3094 /* When LPLU is enabled, we should disable SmartSpeed */ 3095 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3096 if (ret_val) 3097 return ret_val; 3098 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3099 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3100 if (ret_val) 3101 return ret_val; 3102 } else { 3103 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3104 ew32(PHY_CTRL, phy_ctrl); 3105 3106 if (phy->type != e1000_phy_igp_3) 3107 return 0; 3108 3109 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3110 * during Dx states where the power conservation is most 3111 * important. During driver activity we should enable 3112 * SmartSpeed, so performance is maintained. 3113 */ 3114 if (phy->smart_speed == e1000_smart_speed_on) { 3115 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3116 &data); 3117 if (ret_val) 3118 return ret_val; 3119 3120 data |= IGP01E1000_PSCFR_SMART_SPEED; 3121 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3122 data); 3123 if (ret_val) 3124 return ret_val; 3125 } else if (phy->smart_speed == e1000_smart_speed_off) { 3126 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3127 &data); 3128 if (ret_val) 3129 return ret_val; 3130 3131 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3132 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3133 data); 3134 if (ret_val) 3135 return ret_val; 3136 } 3137 } 3138 3139 return 0; 3140 } 3141 3142 /** 3143 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3144 * @hw: pointer to the HW structure 3145 * @active: true to enable LPLU, false to disable 3146 * 3147 * Sets the LPLU D3 state according to the active flag. When 3148 * activating LPLU this function also disables smart speed 3149 * and vice versa. LPLU will not be activated unless the 3150 * device autonegotiation advertisement meets standards of 3151 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3152 * This is a function pointer entry point only called by 3153 * PHY setup routines. 3154 **/ 3155 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3156 { 3157 struct e1000_phy_info *phy = &hw->phy; 3158 u32 phy_ctrl; 3159 s32 ret_val = 0; 3160 u16 data; 3161 3162 phy_ctrl = er32(PHY_CTRL); 3163 3164 if (!active) { 3165 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3166 ew32(PHY_CTRL, phy_ctrl); 3167 3168 if (phy->type != e1000_phy_igp_3) 3169 return 0; 3170 3171 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3172 * during Dx states where the power conservation is most 3173 * important. During driver activity we should enable 3174 * SmartSpeed, so performance is maintained. 3175 */ 3176 if (phy->smart_speed == e1000_smart_speed_on) { 3177 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3178 &data); 3179 if (ret_val) 3180 return ret_val; 3181 3182 data |= IGP01E1000_PSCFR_SMART_SPEED; 3183 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3184 data); 3185 if (ret_val) 3186 return ret_val; 3187 } else if (phy->smart_speed == e1000_smart_speed_off) { 3188 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3189 &data); 3190 if (ret_val) 3191 return ret_val; 3192 3193 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3194 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3195 data); 3196 if (ret_val) 3197 return ret_val; 3198 } 3199 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3200 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3201 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3202 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3203 ew32(PHY_CTRL, phy_ctrl); 3204 3205 if (phy->type != e1000_phy_igp_3) 3206 return 0; 3207 3208 /* Call gig speed drop workaround on LPLU before accessing 3209 * any PHY registers 3210 */ 3211 if (hw->mac.type == e1000_ich8lan) 3212 e1000e_gig_downshift_workaround_ich8lan(hw); 3213 3214 /* When LPLU is enabled, we should disable SmartSpeed */ 3215 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3216 if (ret_val) 3217 return ret_val; 3218 3219 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3220 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3221 } 3222 3223 return ret_val; 3224 } 3225 3226 /** 3227 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3228 * @hw: pointer to the HW structure 3229 * @bank: pointer to the variable that returns the active bank 3230 * 3231 * Reads signature byte from the NVM using the flash access registers. 3232 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3233 **/ 3234 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3235 { 3236 u32 eecd; 3237 struct e1000_nvm_info *nvm = &hw->nvm; 3238 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3239 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3240 u32 nvm_dword = 0; 3241 u8 sig_byte = 0; 3242 s32 ret_val; 3243 3244 switch (hw->mac.type) { 3245 case e1000_pch_spt: 3246 case e1000_pch_cnp: 3247 case e1000_pch_tgp: 3248 case e1000_pch_adp: 3249 case e1000_pch_mtp: 3250 case e1000_pch_lnp: 3251 case e1000_pch_ptp: 3252 case e1000_pch_nvp: 3253 bank1_offset = nvm->flash_bank_size; 3254 act_offset = E1000_ICH_NVM_SIG_WORD; 3255 3256 /* set bank to 0 in case flash read fails */ 3257 *bank = 0; 3258 3259 /* Check bank 0 */ 3260 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3261 &nvm_dword); 3262 if (ret_val) 3263 return ret_val; 3264 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3265 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3266 E1000_ICH_NVM_SIG_VALUE) { 3267 *bank = 0; 3268 return 0; 3269 } 3270 3271 /* Check bank 1 */ 3272 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3273 bank1_offset, 3274 &nvm_dword); 3275 if (ret_val) 3276 return ret_val; 3277 sig_byte = FIELD_GET(0xFF00, nvm_dword); 3278 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3279 E1000_ICH_NVM_SIG_VALUE) { 3280 *bank = 1; 3281 return 0; 3282 } 3283 3284 e_dbg("ERROR: No valid NVM bank present\n"); 3285 return -E1000_ERR_NVM; 3286 case e1000_ich8lan: 3287 case e1000_ich9lan: 3288 eecd = er32(EECD); 3289 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3290 E1000_EECD_SEC1VAL_VALID_MASK) { 3291 if (eecd & E1000_EECD_SEC1VAL) 3292 *bank = 1; 3293 else 3294 *bank = 0; 3295 3296 return 0; 3297 } 3298 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3299 fallthrough; 3300 default: 3301 /* set bank to 0 in case flash read fails */ 3302 *bank = 0; 3303 3304 /* Check bank 0 */ 3305 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3306 &sig_byte); 3307 if (ret_val) 3308 return ret_val; 3309 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3310 E1000_ICH_NVM_SIG_VALUE) { 3311 *bank = 0; 3312 return 0; 3313 } 3314 3315 /* Check bank 1 */ 3316 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3317 bank1_offset, 3318 &sig_byte); 3319 if (ret_val) 3320 return ret_val; 3321 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3322 E1000_ICH_NVM_SIG_VALUE) { 3323 *bank = 1; 3324 return 0; 3325 } 3326 3327 e_dbg("ERROR: No valid NVM bank present\n"); 3328 return -E1000_ERR_NVM; 3329 } 3330 } 3331 3332 /** 3333 * e1000_read_nvm_spt - NVM access for SPT 3334 * @hw: pointer to the HW structure 3335 * @offset: The offset (in bytes) of the word(s) to read. 3336 * @words: Size of data to read in words. 3337 * @data: pointer to the word(s) to read at offset. 3338 * 3339 * Reads a word(s) from the NVM 3340 **/ 3341 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3342 u16 *data) 3343 { 3344 struct e1000_nvm_info *nvm = &hw->nvm; 3345 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3346 u32 act_offset; 3347 s32 ret_val = 0; 3348 u32 bank = 0; 3349 u32 dword = 0; 3350 u16 offset_to_read; 3351 u16 i; 3352 3353 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3354 (words == 0)) { 3355 e_dbg("nvm parameter(s) out of bounds\n"); 3356 ret_val = -E1000_ERR_NVM; 3357 goto out; 3358 } 3359 3360 nvm->ops.acquire(hw); 3361 3362 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3363 if (ret_val) { 3364 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3365 bank = 0; 3366 } 3367 3368 act_offset = (bank) ? nvm->flash_bank_size : 0; 3369 act_offset += offset; 3370 3371 ret_val = 0; 3372 3373 for (i = 0; i < words; i += 2) { 3374 if (words - i == 1) { 3375 if (dev_spec->shadow_ram[offset + i].modified) { 3376 data[i] = 3377 dev_spec->shadow_ram[offset + i].value; 3378 } else { 3379 offset_to_read = act_offset + i - 3380 ((act_offset + i) % 2); 3381 ret_val = 3382 e1000_read_flash_dword_ich8lan(hw, 3383 offset_to_read, 3384 &dword); 3385 if (ret_val) 3386 break; 3387 if ((act_offset + i) % 2 == 0) 3388 data[i] = (u16)(dword & 0xFFFF); 3389 else 3390 data[i] = (u16)((dword >> 16) & 0xFFFF); 3391 } 3392 } else { 3393 offset_to_read = act_offset + i; 3394 if (!(dev_spec->shadow_ram[offset + i].modified) || 3395 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3396 ret_val = 3397 e1000_read_flash_dword_ich8lan(hw, 3398 offset_to_read, 3399 &dword); 3400 if (ret_val) 3401 break; 3402 } 3403 if (dev_spec->shadow_ram[offset + i].modified) 3404 data[i] = 3405 dev_spec->shadow_ram[offset + i].value; 3406 else 3407 data[i] = (u16)(dword & 0xFFFF); 3408 if (dev_spec->shadow_ram[offset + i].modified) 3409 data[i + 1] = 3410 dev_spec->shadow_ram[offset + i + 1].value; 3411 else 3412 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3413 } 3414 } 3415 3416 nvm->ops.release(hw); 3417 3418 out: 3419 if (ret_val) 3420 e_dbg("NVM read error: %d\n", ret_val); 3421 3422 return ret_val; 3423 } 3424 3425 /** 3426 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3427 * @hw: pointer to the HW structure 3428 * @offset: The offset (in bytes) of the word(s) to read. 3429 * @words: Size of data to read in words 3430 * @data: Pointer to the word(s) to read at offset. 3431 * 3432 * Reads a word(s) from the NVM using the flash access registers. 3433 **/ 3434 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3435 u16 *data) 3436 { 3437 struct e1000_nvm_info *nvm = &hw->nvm; 3438 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3439 u32 act_offset; 3440 s32 ret_val = 0; 3441 u32 bank = 0; 3442 u16 i, word; 3443 3444 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3445 (words == 0)) { 3446 e_dbg("nvm parameter(s) out of bounds\n"); 3447 ret_val = -E1000_ERR_NVM; 3448 goto out; 3449 } 3450 3451 nvm->ops.acquire(hw); 3452 3453 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3454 if (ret_val) { 3455 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3456 bank = 0; 3457 } 3458 3459 act_offset = (bank) ? nvm->flash_bank_size : 0; 3460 act_offset += offset; 3461 3462 ret_val = 0; 3463 for (i = 0; i < words; i++) { 3464 if (dev_spec->shadow_ram[offset + i].modified) { 3465 data[i] = dev_spec->shadow_ram[offset + i].value; 3466 } else { 3467 ret_val = e1000_read_flash_word_ich8lan(hw, 3468 act_offset + i, 3469 &word); 3470 if (ret_val) 3471 break; 3472 data[i] = word; 3473 } 3474 } 3475 3476 nvm->ops.release(hw); 3477 3478 out: 3479 if (ret_val) 3480 e_dbg("NVM read error: %d\n", ret_val); 3481 3482 return ret_val; 3483 } 3484 3485 /** 3486 * e1000_flash_cycle_init_ich8lan - Initialize flash 3487 * @hw: pointer to the HW structure 3488 * 3489 * This function does initial flash setup so that a new read/write/erase cycle 3490 * can be started. 3491 **/ 3492 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3493 { 3494 union ich8_hws_flash_status hsfsts; 3495 s32 ret_val = -E1000_ERR_NVM; 3496 3497 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3498 3499 /* Check if the flash descriptor is valid */ 3500 if (!hsfsts.hsf_status.fldesvalid) { 3501 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3502 return -E1000_ERR_NVM; 3503 } 3504 3505 /* Clear FCERR and DAEL in hw status by writing 1 */ 3506 hsfsts.hsf_status.flcerr = 1; 3507 hsfsts.hsf_status.dael = 1; 3508 if (hw->mac.type >= e1000_pch_spt) 3509 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3510 else 3511 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3512 3513 /* Either we should have a hardware SPI cycle in progress 3514 * bit to check against, in order to start a new cycle or 3515 * FDONE bit should be changed in the hardware so that it 3516 * is 1 after hardware reset, which can then be used as an 3517 * indication whether a cycle is in progress or has been 3518 * completed. 3519 */ 3520 3521 if (!hsfsts.hsf_status.flcinprog) { 3522 /* There is no cycle running at present, 3523 * so we can start a cycle. 3524 * Begin by setting Flash Cycle Done. 3525 */ 3526 hsfsts.hsf_status.flcdone = 1; 3527 if (hw->mac.type >= e1000_pch_spt) 3528 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3529 else 3530 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3531 ret_val = 0; 3532 } else { 3533 s32 i; 3534 3535 /* Otherwise poll for sometime so the current 3536 * cycle has a chance to end before giving up. 3537 */ 3538 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3539 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3540 if (!hsfsts.hsf_status.flcinprog) { 3541 ret_val = 0; 3542 break; 3543 } 3544 udelay(1); 3545 } 3546 if (!ret_val) { 3547 /* Successful in waiting for previous cycle to timeout, 3548 * now set the Flash Cycle Done. 3549 */ 3550 hsfsts.hsf_status.flcdone = 1; 3551 if (hw->mac.type >= e1000_pch_spt) 3552 ew32flash(ICH_FLASH_HSFSTS, 3553 hsfsts.regval & 0xFFFF); 3554 else 3555 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3556 } else { 3557 e_dbg("Flash controller busy, cannot get access\n"); 3558 } 3559 } 3560 3561 return ret_val; 3562 } 3563 3564 /** 3565 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3566 * @hw: pointer to the HW structure 3567 * @timeout: maximum time to wait for completion 3568 * 3569 * This function starts a flash cycle and waits for its completion. 3570 **/ 3571 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3572 { 3573 union ich8_hws_flash_ctrl hsflctl; 3574 union ich8_hws_flash_status hsfsts; 3575 u32 i = 0; 3576 3577 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3578 if (hw->mac.type >= e1000_pch_spt) 3579 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3580 else 3581 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3582 hsflctl.hsf_ctrl.flcgo = 1; 3583 3584 if (hw->mac.type >= e1000_pch_spt) 3585 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3586 else 3587 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3588 3589 /* wait till FDONE bit is set to 1 */ 3590 do { 3591 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3592 if (hsfsts.hsf_status.flcdone) 3593 break; 3594 udelay(1); 3595 } while (i++ < timeout); 3596 3597 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3598 return 0; 3599 3600 return -E1000_ERR_NVM; 3601 } 3602 3603 /** 3604 * e1000_read_flash_dword_ich8lan - Read dword from flash 3605 * @hw: pointer to the HW structure 3606 * @offset: offset to data location 3607 * @data: pointer to the location for storing the data 3608 * 3609 * Reads the flash dword at offset into data. Offset is converted 3610 * to bytes before read. 3611 **/ 3612 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3613 u32 *data) 3614 { 3615 /* Must convert word offset into bytes. */ 3616 offset <<= 1; 3617 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3618 } 3619 3620 /** 3621 * e1000_read_flash_word_ich8lan - Read word from flash 3622 * @hw: pointer to the HW structure 3623 * @offset: offset to data location 3624 * @data: pointer to the location for storing the data 3625 * 3626 * Reads the flash word at offset into data. Offset is converted 3627 * to bytes before read. 3628 **/ 3629 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3630 u16 *data) 3631 { 3632 /* Must convert offset into bytes. */ 3633 offset <<= 1; 3634 3635 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3636 } 3637 3638 /** 3639 * e1000_read_flash_byte_ich8lan - Read byte from flash 3640 * @hw: pointer to the HW structure 3641 * @offset: The offset of the byte to read. 3642 * @data: Pointer to a byte to store the value read. 3643 * 3644 * Reads a single byte from the NVM using the flash access registers. 3645 **/ 3646 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3647 u8 *data) 3648 { 3649 s32 ret_val; 3650 u16 word = 0; 3651 3652 /* In SPT, only 32 bits access is supported, 3653 * so this function should not be called. 3654 */ 3655 if (hw->mac.type >= e1000_pch_spt) 3656 return -E1000_ERR_NVM; 3657 else 3658 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3659 3660 if (ret_val) 3661 return ret_val; 3662 3663 *data = (u8)word; 3664 3665 return 0; 3666 } 3667 3668 /** 3669 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3670 * @hw: pointer to the HW structure 3671 * @offset: The offset (in bytes) of the byte or word to read. 3672 * @size: Size of data to read, 1=byte 2=word 3673 * @data: Pointer to the word to store the value read. 3674 * 3675 * Reads a byte or word from the NVM using the flash access registers. 3676 **/ 3677 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3678 u8 size, u16 *data) 3679 { 3680 union ich8_hws_flash_status hsfsts; 3681 union ich8_hws_flash_ctrl hsflctl; 3682 u32 flash_linear_addr; 3683 u32 flash_data = 0; 3684 s32 ret_val = -E1000_ERR_NVM; 3685 u8 count = 0; 3686 3687 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3688 return -E1000_ERR_NVM; 3689 3690 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3691 hw->nvm.flash_base_addr); 3692 3693 do { 3694 udelay(1); 3695 /* Steps */ 3696 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3697 if (ret_val) 3698 break; 3699 3700 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3701 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3702 hsflctl.hsf_ctrl.fldbcount = size - 1; 3703 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3704 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3705 3706 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3707 3708 ret_val = 3709 e1000_flash_cycle_ich8lan(hw, 3710 ICH_FLASH_READ_COMMAND_TIMEOUT); 3711 3712 /* Check if FCERR is set to 1, if set to 1, clear it 3713 * and try the whole sequence a few more times, else 3714 * read in (shift in) the Flash Data0, the order is 3715 * least significant byte first msb to lsb 3716 */ 3717 if (!ret_val) { 3718 flash_data = er32flash(ICH_FLASH_FDATA0); 3719 if (size == 1) 3720 *data = (u8)(flash_data & 0x000000FF); 3721 else if (size == 2) 3722 *data = (u16)(flash_data & 0x0000FFFF); 3723 break; 3724 } else { 3725 /* If we've gotten here, then things are probably 3726 * completely hosed, but if the error condition is 3727 * detected, it won't hurt to give it another try... 3728 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3729 */ 3730 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3731 if (hsfsts.hsf_status.flcerr) { 3732 /* Repeat for some time before giving up. */ 3733 continue; 3734 } else if (!hsfsts.hsf_status.flcdone) { 3735 e_dbg("Timeout error - flash cycle did not complete.\n"); 3736 break; 3737 } 3738 } 3739 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3740 3741 return ret_val; 3742 } 3743 3744 /** 3745 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3746 * @hw: pointer to the HW structure 3747 * @offset: The offset (in bytes) of the dword to read. 3748 * @data: Pointer to the dword to store the value read. 3749 * 3750 * Reads a byte or word from the NVM using the flash access registers. 3751 **/ 3752 3753 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3754 u32 *data) 3755 { 3756 union ich8_hws_flash_status hsfsts; 3757 union ich8_hws_flash_ctrl hsflctl; 3758 u32 flash_linear_addr; 3759 s32 ret_val = -E1000_ERR_NVM; 3760 u8 count = 0; 3761 3762 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3763 return -E1000_ERR_NVM; 3764 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3765 hw->nvm.flash_base_addr); 3766 3767 do { 3768 udelay(1); 3769 /* Steps */ 3770 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3771 if (ret_val) 3772 break; 3773 /* In SPT, This register is in Lan memory space, not flash. 3774 * Therefore, only 32 bit access is supported 3775 */ 3776 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3777 3778 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3779 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3780 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3781 /* In SPT, This register is in Lan memory space, not flash. 3782 * Therefore, only 32 bit access is supported 3783 */ 3784 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3785 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3786 3787 ret_val = 3788 e1000_flash_cycle_ich8lan(hw, 3789 ICH_FLASH_READ_COMMAND_TIMEOUT); 3790 3791 /* Check if FCERR is set to 1, if set to 1, clear it 3792 * and try the whole sequence a few more times, else 3793 * read in (shift in) the Flash Data0, the order is 3794 * least significant byte first msb to lsb 3795 */ 3796 if (!ret_val) { 3797 *data = er32flash(ICH_FLASH_FDATA0); 3798 break; 3799 } else { 3800 /* If we've gotten here, then things are probably 3801 * completely hosed, but if the error condition is 3802 * detected, it won't hurt to give it another try... 3803 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3804 */ 3805 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3806 if (hsfsts.hsf_status.flcerr) { 3807 /* Repeat for some time before giving up. */ 3808 continue; 3809 } else if (!hsfsts.hsf_status.flcdone) { 3810 e_dbg("Timeout error - flash cycle did not complete.\n"); 3811 break; 3812 } 3813 } 3814 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3815 3816 return ret_val; 3817 } 3818 3819 /** 3820 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3821 * @hw: pointer to the HW structure 3822 * @offset: The offset (in bytes) of the word(s) to write. 3823 * @words: Size of data to write in words 3824 * @data: Pointer to the word(s) to write at offset. 3825 * 3826 * Writes a byte or word to the NVM using the flash access registers. 3827 **/ 3828 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3829 u16 *data) 3830 { 3831 struct e1000_nvm_info *nvm = &hw->nvm; 3832 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3833 u16 i; 3834 3835 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3836 (words == 0)) { 3837 e_dbg("nvm parameter(s) out of bounds\n"); 3838 return -E1000_ERR_NVM; 3839 } 3840 3841 nvm->ops.acquire(hw); 3842 3843 for (i = 0; i < words; i++) { 3844 dev_spec->shadow_ram[offset + i].modified = true; 3845 dev_spec->shadow_ram[offset + i].value = data[i]; 3846 } 3847 3848 nvm->ops.release(hw); 3849 3850 return 0; 3851 } 3852 3853 /** 3854 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3855 * @hw: pointer to the HW structure 3856 * 3857 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3858 * which writes the checksum to the shadow ram. The changes in the shadow 3859 * ram are then committed to the EEPROM by processing each bank at a time 3860 * checking for the modified bit and writing only the pending changes. 3861 * After a successful commit, the shadow ram is cleared and is ready for 3862 * future writes. 3863 **/ 3864 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3865 { 3866 struct e1000_nvm_info *nvm = &hw->nvm; 3867 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3868 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3869 s32 ret_val; 3870 u32 dword = 0; 3871 3872 ret_val = e1000e_update_nvm_checksum_generic(hw); 3873 if (ret_val) 3874 goto out; 3875 3876 if (nvm->type != e1000_nvm_flash_sw) 3877 goto out; 3878 3879 nvm->ops.acquire(hw); 3880 3881 /* We're writing to the opposite bank so if we're on bank 1, 3882 * write to bank 0 etc. We also need to erase the segment that 3883 * is going to be written 3884 */ 3885 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3886 if (ret_val) { 3887 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3888 bank = 0; 3889 } 3890 3891 if (bank == 0) { 3892 new_bank_offset = nvm->flash_bank_size; 3893 old_bank_offset = 0; 3894 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3895 if (ret_val) 3896 goto release; 3897 } else { 3898 old_bank_offset = nvm->flash_bank_size; 3899 new_bank_offset = 0; 3900 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3901 if (ret_val) 3902 goto release; 3903 } 3904 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3905 /* Determine whether to write the value stored 3906 * in the other NVM bank or a modified value stored 3907 * in the shadow RAM 3908 */ 3909 ret_val = e1000_read_flash_dword_ich8lan(hw, 3910 i + old_bank_offset, 3911 &dword); 3912 3913 if (dev_spec->shadow_ram[i].modified) { 3914 dword &= 0xffff0000; 3915 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3916 } 3917 if (dev_spec->shadow_ram[i + 1].modified) { 3918 dword &= 0x0000ffff; 3919 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3920 << 16); 3921 } 3922 if (ret_val) 3923 break; 3924 3925 /* If the word is 0x13, then make sure the signature bits 3926 * (15:14) are 11b until the commit has completed. 3927 * This will allow us to write 10b which indicates the 3928 * signature is valid. We want to do this after the write 3929 * has completed so that we don't mark the segment valid 3930 * while the write is still in progress 3931 */ 3932 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3933 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3934 3935 /* Convert offset to bytes. */ 3936 act_offset = (i + new_bank_offset) << 1; 3937 3938 usleep_range(100, 200); 3939 3940 /* Write the data to the new bank. Offset in words */ 3941 act_offset = i + new_bank_offset; 3942 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3943 dword); 3944 if (ret_val) 3945 break; 3946 } 3947 3948 /* Don't bother writing the segment valid bits if sector 3949 * programming failed. 3950 */ 3951 if (ret_val) { 3952 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3953 e_dbg("Flash commit failed.\n"); 3954 goto release; 3955 } 3956 3957 /* Finally validate the new segment by setting bit 15:14 3958 * to 10b in word 0x13 , this can be done without an 3959 * erase as well since these bits are 11 to start with 3960 * and we need to change bit 14 to 0b 3961 */ 3962 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3963 3964 /*offset in words but we read dword */ 3965 --act_offset; 3966 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3967 3968 if (ret_val) 3969 goto release; 3970 3971 dword &= 0xBFFFFFFF; 3972 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3973 3974 if (ret_val) 3975 goto release; 3976 3977 /* offset in words but we read dword */ 3978 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3979 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3980 3981 if (ret_val) 3982 goto release; 3983 3984 dword &= 0x00FFFFFF; 3985 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3986 3987 if (ret_val) 3988 goto release; 3989 3990 /* Great! Everything worked, we can now clear the cached entries. */ 3991 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3992 dev_spec->shadow_ram[i].modified = false; 3993 dev_spec->shadow_ram[i].value = 0xFFFF; 3994 } 3995 3996 release: 3997 nvm->ops.release(hw); 3998 3999 /* Reload the EEPROM, or else modifications will not appear 4000 * until after the next adapter reset. 4001 */ 4002 if (!ret_val) { 4003 nvm->ops.reload(hw); 4004 usleep_range(10000, 11000); 4005 } 4006 4007 out: 4008 if (ret_val) 4009 e_dbg("NVM update error: %d\n", ret_val); 4010 4011 return ret_val; 4012 } 4013 4014 /** 4015 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 4016 * @hw: pointer to the HW structure 4017 * 4018 * The NVM checksum is updated by calling the generic update_nvm_checksum, 4019 * which writes the checksum to the shadow ram. The changes in the shadow 4020 * ram are then committed to the EEPROM by processing each bank at a time 4021 * checking for the modified bit and writing only the pending changes. 4022 * After a successful commit, the shadow ram is cleared and is ready for 4023 * future writes. 4024 **/ 4025 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 4026 { 4027 struct e1000_nvm_info *nvm = &hw->nvm; 4028 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4029 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 4030 s32 ret_val; 4031 u16 data = 0; 4032 4033 ret_val = e1000e_update_nvm_checksum_generic(hw); 4034 if (ret_val) 4035 goto out; 4036 4037 if (nvm->type != e1000_nvm_flash_sw) 4038 goto out; 4039 4040 nvm->ops.acquire(hw); 4041 4042 /* We're writing to the opposite bank so if we're on bank 1, 4043 * write to bank 0 etc. We also need to erase the segment that 4044 * is going to be written 4045 */ 4046 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 4047 if (ret_val) { 4048 e_dbg("Could not detect valid bank, assuming bank 0\n"); 4049 bank = 0; 4050 } 4051 4052 if (bank == 0) { 4053 new_bank_offset = nvm->flash_bank_size; 4054 old_bank_offset = 0; 4055 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 4056 if (ret_val) 4057 goto release; 4058 } else { 4059 old_bank_offset = nvm->flash_bank_size; 4060 new_bank_offset = 0; 4061 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 4062 if (ret_val) 4063 goto release; 4064 } 4065 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4066 if (dev_spec->shadow_ram[i].modified) { 4067 data = dev_spec->shadow_ram[i].value; 4068 } else { 4069 ret_val = e1000_read_flash_word_ich8lan(hw, i + 4070 old_bank_offset, 4071 &data); 4072 if (ret_val) 4073 break; 4074 } 4075 4076 /* If the word is 0x13, then make sure the signature bits 4077 * (15:14) are 11b until the commit has completed. 4078 * This will allow us to write 10b which indicates the 4079 * signature is valid. We want to do this after the write 4080 * has completed so that we don't mark the segment valid 4081 * while the write is still in progress 4082 */ 4083 if (i == E1000_ICH_NVM_SIG_WORD) 4084 data |= E1000_ICH_NVM_SIG_MASK; 4085 4086 /* Convert offset to bytes. */ 4087 act_offset = (i + new_bank_offset) << 1; 4088 4089 usleep_range(100, 200); 4090 /* Write the bytes to the new bank. */ 4091 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4092 act_offset, 4093 (u8)data); 4094 if (ret_val) 4095 break; 4096 4097 usleep_range(100, 200); 4098 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4099 act_offset + 1, 4100 (u8)(data >> 8)); 4101 if (ret_val) 4102 break; 4103 } 4104 4105 /* Don't bother writing the segment valid bits if sector 4106 * programming failed. 4107 */ 4108 if (ret_val) { 4109 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4110 e_dbg("Flash commit failed.\n"); 4111 goto release; 4112 } 4113 4114 /* Finally validate the new segment by setting bit 15:14 4115 * to 10b in word 0x13 , this can be done without an 4116 * erase as well since these bits are 11 to start with 4117 * and we need to change bit 14 to 0b 4118 */ 4119 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4120 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4121 if (ret_val) 4122 goto release; 4123 4124 data &= 0xBFFF; 4125 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4126 act_offset * 2 + 1, 4127 (u8)(data >> 8)); 4128 if (ret_val) 4129 goto release; 4130 4131 /* And invalidate the previously valid segment by setting 4132 * its signature word (0x13) high_byte to 0b. This can be 4133 * done without an erase because flash erase sets all bits 4134 * to 1's. We can write 1's to 0's without an erase 4135 */ 4136 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4137 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4138 if (ret_val) 4139 goto release; 4140 4141 /* Great! Everything worked, we can now clear the cached entries. */ 4142 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4143 dev_spec->shadow_ram[i].modified = false; 4144 dev_spec->shadow_ram[i].value = 0xFFFF; 4145 } 4146 4147 release: 4148 nvm->ops.release(hw); 4149 4150 /* Reload the EEPROM, or else modifications will not appear 4151 * until after the next adapter reset. 4152 */ 4153 if (!ret_val) { 4154 nvm->ops.reload(hw); 4155 usleep_range(10000, 11000); 4156 } 4157 4158 out: 4159 if (ret_val) 4160 e_dbg("NVM update error: %d\n", ret_val); 4161 4162 return ret_val; 4163 } 4164 4165 /** 4166 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4167 * @hw: pointer to the HW structure 4168 * 4169 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4170 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4171 * calculated, in which case we need to calculate the checksum and set bit 6. 4172 **/ 4173 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4174 { 4175 s32 ret_val; 4176 u16 data; 4177 u16 word; 4178 u16 valid_csum_mask; 4179 4180 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4181 * the checksum needs to be fixed. This bit is an indication that 4182 * the NVM was prepared by OEM software and did not calculate 4183 * the checksum...a likely scenario. 4184 */ 4185 switch (hw->mac.type) { 4186 case e1000_pch_lpt: 4187 case e1000_pch_spt: 4188 case e1000_pch_cnp: 4189 case e1000_pch_tgp: 4190 case e1000_pch_adp: 4191 case e1000_pch_mtp: 4192 case e1000_pch_lnp: 4193 case e1000_pch_ptp: 4194 case e1000_pch_nvp: 4195 word = NVM_COMPAT; 4196 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4197 break; 4198 default: 4199 word = NVM_FUTURE_INIT_WORD1; 4200 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4201 break; 4202 } 4203 4204 ret_val = e1000_read_nvm(hw, word, 1, &data); 4205 if (ret_val) 4206 return ret_val; 4207 4208 if (!(data & valid_csum_mask)) { 4209 e_dbg("NVM Checksum valid bit not set\n"); 4210 4211 if (hw->mac.type < e1000_pch_tgp) { 4212 data |= valid_csum_mask; 4213 ret_val = e1000_write_nvm(hw, word, 1, &data); 4214 if (ret_val) 4215 return ret_val; 4216 ret_val = e1000e_update_nvm_checksum(hw); 4217 if (ret_val) 4218 return ret_val; 4219 } 4220 } 4221 4222 return e1000e_validate_nvm_checksum_generic(hw); 4223 } 4224 4225 /** 4226 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4227 * @hw: pointer to the HW structure 4228 * 4229 * To prevent malicious write/erase of the NVM, set it to be read-only 4230 * so that the hardware ignores all write/erase cycles of the NVM via 4231 * the flash control registers. The shadow-ram copy of the NVM will 4232 * still be updated, however any updates to this copy will not stick 4233 * across driver reloads. 4234 **/ 4235 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4236 { 4237 struct e1000_nvm_info *nvm = &hw->nvm; 4238 union ich8_flash_protected_range pr0; 4239 union ich8_hws_flash_status hsfsts; 4240 u32 gfpreg; 4241 4242 nvm->ops.acquire(hw); 4243 4244 gfpreg = er32flash(ICH_FLASH_GFPREG); 4245 4246 /* Write-protect GbE Sector of NVM */ 4247 pr0.regval = er32flash(ICH_FLASH_PR0); 4248 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4249 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4250 pr0.range.wpe = true; 4251 ew32flash(ICH_FLASH_PR0, pr0.regval); 4252 4253 /* Lock down a subset of GbE Flash Control Registers, e.g. 4254 * PR0 to prevent the write-protection from being lifted. 4255 * Once FLOCKDN is set, the registers protected by it cannot 4256 * be written until FLOCKDN is cleared by a hardware reset. 4257 */ 4258 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4259 hsfsts.hsf_status.flockdn = true; 4260 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4261 4262 nvm->ops.release(hw); 4263 } 4264 4265 /** 4266 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4267 * @hw: pointer to the HW structure 4268 * @offset: The offset (in bytes) of the byte/word to read. 4269 * @size: Size of data to read, 1=byte 2=word 4270 * @data: The byte(s) to write to the NVM. 4271 * 4272 * Writes one/two bytes to the NVM using the flash access registers. 4273 **/ 4274 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4275 u8 size, u16 data) 4276 { 4277 union ich8_hws_flash_status hsfsts; 4278 union ich8_hws_flash_ctrl hsflctl; 4279 u32 flash_linear_addr; 4280 u32 flash_data = 0; 4281 s32 ret_val; 4282 u8 count = 0; 4283 4284 if (hw->mac.type >= e1000_pch_spt) { 4285 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4286 return -E1000_ERR_NVM; 4287 } else { 4288 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4289 return -E1000_ERR_NVM; 4290 } 4291 4292 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4293 hw->nvm.flash_base_addr); 4294 4295 do { 4296 udelay(1); 4297 /* Steps */ 4298 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4299 if (ret_val) 4300 break; 4301 /* In SPT, This register is in Lan memory space, not 4302 * flash. Therefore, only 32 bit access is supported 4303 */ 4304 if (hw->mac.type >= e1000_pch_spt) 4305 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4306 else 4307 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4308 4309 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4310 hsflctl.hsf_ctrl.fldbcount = size - 1; 4311 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4312 /* In SPT, This register is in Lan memory space, 4313 * not flash. Therefore, only 32 bit access is 4314 * supported 4315 */ 4316 if (hw->mac.type >= e1000_pch_spt) 4317 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4318 else 4319 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4320 4321 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4322 4323 if (size == 1) 4324 flash_data = (u32)data & 0x00FF; 4325 else 4326 flash_data = (u32)data; 4327 4328 ew32flash(ICH_FLASH_FDATA0, flash_data); 4329 4330 /* check if FCERR is set to 1 , if set to 1, clear it 4331 * and try the whole sequence a few more times else done 4332 */ 4333 ret_val = 4334 e1000_flash_cycle_ich8lan(hw, 4335 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4336 if (!ret_val) 4337 break; 4338 4339 /* If we're here, then things are most likely 4340 * completely hosed, but if the error condition 4341 * is detected, it won't hurt to give it another 4342 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4343 */ 4344 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4345 if (hsfsts.hsf_status.flcerr) 4346 /* Repeat for some time before giving up. */ 4347 continue; 4348 if (!hsfsts.hsf_status.flcdone) { 4349 e_dbg("Timeout error - flash cycle did not complete.\n"); 4350 break; 4351 } 4352 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4353 4354 return ret_val; 4355 } 4356 4357 /** 4358 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4359 * @hw: pointer to the HW structure 4360 * @offset: The offset (in bytes) of the dwords to read. 4361 * @data: The 4 bytes to write to the NVM. 4362 * 4363 * Writes one/two/four bytes to the NVM using the flash access registers. 4364 **/ 4365 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4366 u32 data) 4367 { 4368 union ich8_hws_flash_status hsfsts; 4369 union ich8_hws_flash_ctrl hsflctl; 4370 u32 flash_linear_addr; 4371 s32 ret_val; 4372 u8 count = 0; 4373 4374 if (hw->mac.type >= e1000_pch_spt) { 4375 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4376 return -E1000_ERR_NVM; 4377 } 4378 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4379 hw->nvm.flash_base_addr); 4380 do { 4381 udelay(1); 4382 /* Steps */ 4383 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4384 if (ret_val) 4385 break; 4386 4387 /* In SPT, This register is in Lan memory space, not 4388 * flash. Therefore, only 32 bit access is supported 4389 */ 4390 if (hw->mac.type >= e1000_pch_spt) 4391 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4392 >> 16; 4393 else 4394 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4395 4396 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4397 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4398 4399 /* In SPT, This register is in Lan memory space, 4400 * not flash. Therefore, only 32 bit access is 4401 * supported 4402 */ 4403 if (hw->mac.type >= e1000_pch_spt) 4404 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4405 else 4406 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4407 4408 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4409 4410 ew32flash(ICH_FLASH_FDATA0, data); 4411 4412 /* check if FCERR is set to 1 , if set to 1, clear it 4413 * and try the whole sequence a few more times else done 4414 */ 4415 ret_val = 4416 e1000_flash_cycle_ich8lan(hw, 4417 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4418 4419 if (!ret_val) 4420 break; 4421 4422 /* If we're here, then things are most likely 4423 * completely hosed, but if the error condition 4424 * is detected, it won't hurt to give it another 4425 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4426 */ 4427 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4428 4429 if (hsfsts.hsf_status.flcerr) 4430 /* Repeat for some time before giving up. */ 4431 continue; 4432 if (!hsfsts.hsf_status.flcdone) { 4433 e_dbg("Timeout error - flash cycle did not complete.\n"); 4434 break; 4435 } 4436 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4437 4438 return ret_val; 4439 } 4440 4441 /** 4442 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4443 * @hw: pointer to the HW structure 4444 * @offset: The index of the byte to read. 4445 * @data: The byte to write to the NVM. 4446 * 4447 * Writes a single byte to the NVM using the flash access registers. 4448 **/ 4449 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4450 u8 data) 4451 { 4452 u16 word = (u16)data; 4453 4454 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4455 } 4456 4457 /** 4458 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4459 * @hw: pointer to the HW structure 4460 * @offset: The offset of the word to write. 4461 * @dword: The dword to write to the NVM. 4462 * 4463 * Writes a single dword to the NVM using the flash access registers. 4464 * Goes through a retry algorithm before giving up. 4465 **/ 4466 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4467 u32 offset, u32 dword) 4468 { 4469 s32 ret_val; 4470 u16 program_retries; 4471 4472 /* Must convert word offset into bytes. */ 4473 offset <<= 1; 4474 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4475 4476 if (!ret_val) 4477 return ret_val; 4478 for (program_retries = 0; program_retries < 100; program_retries++) { 4479 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4480 usleep_range(100, 200); 4481 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4482 if (!ret_val) 4483 break; 4484 } 4485 if (program_retries == 100) 4486 return -E1000_ERR_NVM; 4487 4488 return 0; 4489 } 4490 4491 /** 4492 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4493 * @hw: pointer to the HW structure 4494 * @offset: The offset of the byte to write. 4495 * @byte: The byte to write to the NVM. 4496 * 4497 * Writes a single byte to the NVM using the flash access registers. 4498 * Goes through a retry algorithm before giving up. 4499 **/ 4500 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4501 u32 offset, u8 byte) 4502 { 4503 s32 ret_val; 4504 u16 program_retries; 4505 4506 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4507 if (!ret_val) 4508 return ret_val; 4509 4510 for (program_retries = 0; program_retries < 100; program_retries++) { 4511 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4512 usleep_range(100, 200); 4513 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4514 if (!ret_val) 4515 break; 4516 } 4517 if (program_retries == 100) 4518 return -E1000_ERR_NVM; 4519 4520 return 0; 4521 } 4522 4523 /** 4524 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4525 * @hw: pointer to the HW structure 4526 * @bank: 0 for first bank, 1 for second bank, etc. 4527 * 4528 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4529 * bank N is 4096 * N + flash_reg_addr. 4530 **/ 4531 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4532 { 4533 struct e1000_nvm_info *nvm = &hw->nvm; 4534 union ich8_hws_flash_status hsfsts; 4535 union ich8_hws_flash_ctrl hsflctl; 4536 u32 flash_linear_addr; 4537 /* bank size is in 16bit words - adjust to bytes */ 4538 u32 flash_bank_size = nvm->flash_bank_size * 2; 4539 s32 ret_val; 4540 s32 count = 0; 4541 s32 j, iteration, sector_size; 4542 4543 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4544 4545 /* Determine HW Sector size: Read BERASE bits of hw flash status 4546 * register 4547 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4548 * consecutive sectors. The start index for the nth Hw sector 4549 * can be calculated as = bank * 4096 + n * 256 4550 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4551 * The start index for the nth Hw sector can be calculated 4552 * as = bank * 4096 4553 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4554 * (ich9 only, otherwise error condition) 4555 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4556 */ 4557 switch (hsfsts.hsf_status.berasesz) { 4558 case 0: 4559 /* Hw sector size 256 */ 4560 sector_size = ICH_FLASH_SEG_SIZE_256; 4561 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4562 break; 4563 case 1: 4564 sector_size = ICH_FLASH_SEG_SIZE_4K; 4565 iteration = 1; 4566 break; 4567 case 2: 4568 sector_size = ICH_FLASH_SEG_SIZE_8K; 4569 iteration = 1; 4570 break; 4571 case 3: 4572 sector_size = ICH_FLASH_SEG_SIZE_64K; 4573 iteration = 1; 4574 break; 4575 default: 4576 return -E1000_ERR_NVM; 4577 } 4578 4579 /* Start with the base address, then add the sector offset. */ 4580 flash_linear_addr = hw->nvm.flash_base_addr; 4581 flash_linear_addr += (bank) ? flash_bank_size : 0; 4582 4583 for (j = 0; j < iteration; j++) { 4584 do { 4585 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4586 4587 /* Steps */ 4588 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4589 if (ret_val) 4590 return ret_val; 4591 4592 /* Write a value 11 (block Erase) in Flash 4593 * Cycle field in hw flash control 4594 */ 4595 if (hw->mac.type >= e1000_pch_spt) 4596 hsflctl.regval = 4597 er32flash(ICH_FLASH_HSFSTS) >> 16; 4598 else 4599 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4600 4601 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4602 if (hw->mac.type >= e1000_pch_spt) 4603 ew32flash(ICH_FLASH_HSFSTS, 4604 hsflctl.regval << 16); 4605 else 4606 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4607 4608 /* Write the last 24 bits of an index within the 4609 * block into Flash Linear address field in Flash 4610 * Address. 4611 */ 4612 flash_linear_addr += (j * sector_size); 4613 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4614 4615 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4616 if (!ret_val) 4617 break; 4618 4619 /* Check if FCERR is set to 1. If 1, 4620 * clear it and try the whole sequence 4621 * a few more times else Done 4622 */ 4623 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4624 if (hsfsts.hsf_status.flcerr) 4625 /* repeat for some time before giving up */ 4626 continue; 4627 else if (!hsfsts.hsf_status.flcdone) 4628 return ret_val; 4629 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4630 } 4631 4632 return 0; 4633 } 4634 4635 /** 4636 * e1000_valid_led_default_ich8lan - Set the default LED settings 4637 * @hw: pointer to the HW structure 4638 * @data: Pointer to the LED settings 4639 * 4640 * Reads the LED default settings from the NVM to data. If the NVM LED 4641 * settings is all 0's or F's, set the LED default to a valid LED default 4642 * setting. 4643 **/ 4644 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4645 { 4646 s32 ret_val; 4647 4648 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4649 if (ret_val) { 4650 e_dbg("NVM Read Error\n"); 4651 return ret_val; 4652 } 4653 4654 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4655 *data = ID_LED_DEFAULT_ICH8LAN; 4656 4657 return 0; 4658 } 4659 4660 /** 4661 * e1000_id_led_init_pchlan - store LED configurations 4662 * @hw: pointer to the HW structure 4663 * 4664 * PCH does not control LEDs via the LEDCTL register, rather it uses 4665 * the PHY LED configuration register. 4666 * 4667 * PCH also does not have an "always on" or "always off" mode which 4668 * complicates the ID feature. Instead of using the "on" mode to indicate 4669 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4670 * use "link_up" mode. The LEDs will still ID on request if there is no 4671 * link based on logic in e1000_led_[on|off]_pchlan(). 4672 **/ 4673 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4674 { 4675 struct e1000_mac_info *mac = &hw->mac; 4676 s32 ret_val; 4677 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4678 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4679 u16 data, i, temp, shift; 4680 4681 /* Get default ID LED modes */ 4682 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4683 if (ret_val) 4684 return ret_val; 4685 4686 mac->ledctl_default = er32(LEDCTL); 4687 mac->ledctl_mode1 = mac->ledctl_default; 4688 mac->ledctl_mode2 = mac->ledctl_default; 4689 4690 for (i = 0; i < 4; i++) { 4691 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4692 shift = (i * 5); 4693 switch (temp) { 4694 case ID_LED_ON1_DEF2: 4695 case ID_LED_ON1_ON2: 4696 case ID_LED_ON1_OFF2: 4697 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4698 mac->ledctl_mode1 |= (ledctl_on << shift); 4699 break; 4700 case ID_LED_OFF1_DEF2: 4701 case ID_LED_OFF1_ON2: 4702 case ID_LED_OFF1_OFF2: 4703 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4704 mac->ledctl_mode1 |= (ledctl_off << shift); 4705 break; 4706 default: 4707 /* Do nothing */ 4708 break; 4709 } 4710 switch (temp) { 4711 case ID_LED_DEF1_ON2: 4712 case ID_LED_ON1_ON2: 4713 case ID_LED_OFF1_ON2: 4714 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4715 mac->ledctl_mode2 |= (ledctl_on << shift); 4716 break; 4717 case ID_LED_DEF1_OFF2: 4718 case ID_LED_ON1_OFF2: 4719 case ID_LED_OFF1_OFF2: 4720 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4721 mac->ledctl_mode2 |= (ledctl_off << shift); 4722 break; 4723 default: 4724 /* Do nothing */ 4725 break; 4726 } 4727 } 4728 4729 return 0; 4730 } 4731 4732 /** 4733 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4734 * @hw: pointer to the HW structure 4735 * 4736 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4737 * register, so the bus width is hard coded. 4738 **/ 4739 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4740 { 4741 struct e1000_bus_info *bus = &hw->bus; 4742 s32 ret_val; 4743 4744 ret_val = e1000e_get_bus_info_pcie(hw); 4745 4746 /* ICH devices are "PCI Express"-ish. They have 4747 * a configuration space, but do not contain 4748 * PCI Express Capability registers, so bus width 4749 * must be hardcoded. 4750 */ 4751 if (bus->width == e1000_bus_width_unknown) 4752 bus->width = e1000_bus_width_pcie_x1; 4753 4754 return ret_val; 4755 } 4756 4757 /** 4758 * e1000_reset_hw_ich8lan - Reset the hardware 4759 * @hw: pointer to the HW structure 4760 * 4761 * Does a full reset of the hardware which includes a reset of the PHY and 4762 * MAC. 4763 **/ 4764 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4765 { 4766 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4767 u16 kum_cfg; 4768 u32 ctrl, reg; 4769 s32 ret_val; 4770 4771 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4772 * on the last TLP read/write transaction when MAC is reset. 4773 */ 4774 ret_val = e1000e_disable_pcie_master(hw); 4775 if (ret_val) 4776 e_dbg("PCI-E Master disable polling has failed.\n"); 4777 4778 e_dbg("Masking off all interrupts\n"); 4779 ew32(IMC, 0xffffffff); 4780 4781 /* Disable the Transmit and Receive units. Then delay to allow 4782 * any pending transactions to complete before we hit the MAC 4783 * with the global reset. 4784 */ 4785 ew32(RCTL, 0); 4786 ew32(TCTL, E1000_TCTL_PSP); 4787 e1e_flush(); 4788 4789 usleep_range(10000, 11000); 4790 4791 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4792 if (hw->mac.type == e1000_ich8lan) { 4793 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4794 ew32(PBA, E1000_PBA_8K); 4795 /* Set Packet Buffer Size to 16k. */ 4796 ew32(PBS, E1000_PBS_16K); 4797 } 4798 4799 if (hw->mac.type == e1000_pchlan) { 4800 /* Save the NVM K1 bit setting */ 4801 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4802 if (ret_val) 4803 return ret_val; 4804 4805 if (kum_cfg & E1000_NVM_K1_ENABLE) 4806 dev_spec->nvm_k1_enabled = true; 4807 else 4808 dev_spec->nvm_k1_enabled = false; 4809 } 4810 4811 ctrl = er32(CTRL); 4812 4813 if (!hw->phy.ops.check_reset_block(hw)) { 4814 /* Full-chip reset requires MAC and PHY reset at the same 4815 * time to make sure the interface between MAC and the 4816 * external PHY is reset. 4817 */ 4818 ctrl |= E1000_CTRL_PHY_RST; 4819 4820 /* Gate automatic PHY configuration by hardware on 4821 * non-managed 82579 4822 */ 4823 if ((hw->mac.type == e1000_pch2lan) && 4824 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4825 e1000_gate_hw_phy_config_ich8lan(hw, true); 4826 } 4827 ret_val = e1000_acquire_swflag_ich8lan(hw); 4828 e_dbg("Issuing a global reset to ich8lan\n"); 4829 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4830 /* cannot issue a flush here because it hangs the hardware */ 4831 msleep(20); 4832 4833 /* Set Phy Config Counter to 50msec */ 4834 if (hw->mac.type == e1000_pch2lan) { 4835 reg = er32(FEXTNVM3); 4836 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4837 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4838 ew32(FEXTNVM3, reg); 4839 } 4840 4841 if (!ret_val) 4842 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4843 4844 if (ctrl & E1000_CTRL_PHY_RST) { 4845 ret_val = hw->phy.ops.get_cfg_done(hw); 4846 if (ret_val) 4847 return ret_val; 4848 4849 ret_val = e1000_post_phy_reset_ich8lan(hw); 4850 if (ret_val) 4851 return ret_val; 4852 } 4853 4854 /* For PCH, this write will make sure that any noise 4855 * will be detected as a CRC error and be dropped rather than show up 4856 * as a bad packet to the DMA engine. 4857 */ 4858 if (hw->mac.type == e1000_pchlan) 4859 ew32(CRC_OFFSET, 0x65656565); 4860 4861 ew32(IMC, 0xffffffff); 4862 er32(ICR); 4863 4864 reg = er32(KABGTXD); 4865 reg |= E1000_KABGTXD_BGSQLBIAS; 4866 ew32(KABGTXD, reg); 4867 4868 return 0; 4869 } 4870 4871 /** 4872 * e1000_init_hw_ich8lan - Initialize the hardware 4873 * @hw: pointer to the HW structure 4874 * 4875 * Prepares the hardware for transmit and receive by doing the following: 4876 * - initialize hardware bits 4877 * - initialize LED identification 4878 * - setup receive address registers 4879 * - setup flow control 4880 * - setup transmit descriptors 4881 * - clear statistics 4882 **/ 4883 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4884 { 4885 struct e1000_mac_info *mac = &hw->mac; 4886 u32 ctrl_ext, txdctl, snoop, fflt_dbg; 4887 s32 ret_val; 4888 u16 i; 4889 4890 e1000_initialize_hw_bits_ich8lan(hw); 4891 4892 /* Initialize identification LED */ 4893 ret_val = mac->ops.id_led_init(hw); 4894 /* An error is not fatal and we should not stop init due to this */ 4895 if (ret_val) 4896 e_dbg("Error initializing identification LED\n"); 4897 4898 /* Setup the receive address. */ 4899 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4900 4901 /* Zero out the Multicast HASH table */ 4902 e_dbg("Zeroing the MTA\n"); 4903 for (i = 0; i < mac->mta_reg_count; i++) 4904 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4905 4906 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4907 * the ME. Disable wakeup by clearing the host wakeup bit. 4908 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4909 */ 4910 if (hw->phy.type == e1000_phy_82578) { 4911 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4912 i &= ~BM_WUC_HOST_WU_BIT; 4913 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4914 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4915 if (ret_val) 4916 return ret_val; 4917 } 4918 4919 /* Setup link and flow control */ 4920 ret_val = mac->ops.setup_link(hw); 4921 4922 /* Set the transmit descriptor write-back policy for both queues */ 4923 txdctl = er32(TXDCTL(0)); 4924 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4925 E1000_TXDCTL_FULL_TX_DESC_WB); 4926 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4927 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4928 ew32(TXDCTL(0), txdctl); 4929 txdctl = er32(TXDCTL(1)); 4930 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4931 E1000_TXDCTL_FULL_TX_DESC_WB); 4932 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4933 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4934 ew32(TXDCTL(1), txdctl); 4935 4936 /* ICH8 has opposite polarity of no_snoop bits. 4937 * By default, we should use snoop behavior. 4938 */ 4939 if (mac->type == e1000_ich8lan) 4940 snoop = PCIE_ICH8_SNOOP_ALL; 4941 else 4942 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4943 e1000e_set_pcie_no_snoop(hw, snoop); 4944 4945 /* Enable workaround for packet loss issue on TGP PCH 4946 * Do not gate DMA clock from the modPHY block 4947 */ 4948 if (mac->type >= e1000_pch_tgp) { 4949 fflt_dbg = er32(FFLT_DBG); 4950 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK; 4951 ew32(FFLT_DBG, fflt_dbg); 4952 } 4953 4954 ctrl_ext = er32(CTRL_EXT); 4955 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4956 ew32(CTRL_EXT, ctrl_ext); 4957 4958 /* Clear all of the statistics registers (clear on read). It is 4959 * important that we do this after we have tried to establish link 4960 * because the symbol error count will increment wildly if there 4961 * is no link. 4962 */ 4963 e1000_clear_hw_cntrs_ich8lan(hw); 4964 4965 return ret_val; 4966 } 4967 4968 /** 4969 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4970 * @hw: pointer to the HW structure 4971 * 4972 * Sets/Clears required hardware bits necessary for correctly setting up the 4973 * hardware for transmit and receive. 4974 **/ 4975 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4976 { 4977 u32 reg; 4978 4979 /* Extended Device Control */ 4980 reg = er32(CTRL_EXT); 4981 reg |= BIT(22); 4982 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4983 if (hw->mac.type >= e1000_pchlan) 4984 reg |= E1000_CTRL_EXT_PHYPDEN; 4985 ew32(CTRL_EXT, reg); 4986 4987 /* Transmit Descriptor Control 0 */ 4988 reg = er32(TXDCTL(0)); 4989 reg |= BIT(22); 4990 ew32(TXDCTL(0), reg); 4991 4992 /* Transmit Descriptor Control 1 */ 4993 reg = er32(TXDCTL(1)); 4994 reg |= BIT(22); 4995 ew32(TXDCTL(1), reg); 4996 4997 /* Transmit Arbitration Control 0 */ 4998 reg = er32(TARC(0)); 4999 if (hw->mac.type == e1000_ich8lan) 5000 reg |= BIT(28) | BIT(29); 5001 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 5002 ew32(TARC(0), reg); 5003 5004 /* Transmit Arbitration Control 1 */ 5005 reg = er32(TARC(1)); 5006 if (er32(TCTL) & E1000_TCTL_MULR) 5007 reg &= ~BIT(28); 5008 else 5009 reg |= BIT(28); 5010 reg |= BIT(24) | BIT(26) | BIT(30); 5011 ew32(TARC(1), reg); 5012 5013 /* Device Status */ 5014 if (hw->mac.type == e1000_ich8lan) { 5015 reg = er32(STATUS); 5016 reg &= ~BIT(31); 5017 ew32(STATUS, reg); 5018 } 5019 5020 /* work-around descriptor data corruption issue during nfs v2 udp 5021 * traffic, just disable the nfs filtering capability 5022 */ 5023 reg = er32(RFCTL); 5024 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 5025 5026 /* Disable IPv6 extension header parsing because some malformed 5027 * IPv6 headers can hang the Rx. 5028 */ 5029 if (hw->mac.type == e1000_ich8lan) 5030 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 5031 ew32(RFCTL, reg); 5032 5033 /* Enable ECC on Lynxpoint */ 5034 if (hw->mac.type >= e1000_pch_lpt) { 5035 reg = er32(PBECCSTS); 5036 reg |= E1000_PBECCSTS_ECC_ENABLE; 5037 ew32(PBECCSTS, reg); 5038 5039 reg = er32(CTRL); 5040 reg |= E1000_CTRL_MEHE; 5041 ew32(CTRL, reg); 5042 } 5043 } 5044 5045 /** 5046 * e1000_setup_link_ich8lan - Setup flow control and link settings 5047 * @hw: pointer to the HW structure 5048 * 5049 * Determines which flow control settings to use, then configures flow 5050 * control. Calls the appropriate media-specific link configuration 5051 * function. Assuming the adapter has a valid link partner, a valid link 5052 * should be established. Assumes the hardware has previously been reset 5053 * and the transmitter and receiver are not enabled. 5054 **/ 5055 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 5056 { 5057 s32 ret_val; 5058 5059 if (hw->phy.ops.check_reset_block(hw)) 5060 return 0; 5061 5062 /* ICH parts do not have a word in the NVM to determine 5063 * the default flow control setting, so we explicitly 5064 * set it to full. 5065 */ 5066 if (hw->fc.requested_mode == e1000_fc_default) { 5067 /* Workaround h/w hang when Tx flow control enabled */ 5068 if (hw->mac.type == e1000_pchlan) 5069 hw->fc.requested_mode = e1000_fc_rx_pause; 5070 else 5071 hw->fc.requested_mode = e1000_fc_full; 5072 } 5073 5074 /* Save off the requested flow control mode for use later. Depending 5075 * on the link partner's capabilities, we may or may not use this mode. 5076 */ 5077 hw->fc.current_mode = hw->fc.requested_mode; 5078 5079 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 5080 5081 /* Continue to configure the copper link. */ 5082 ret_val = hw->mac.ops.setup_physical_interface(hw); 5083 if (ret_val) 5084 return ret_val; 5085 5086 ew32(FCTTV, hw->fc.pause_time); 5087 if ((hw->phy.type == e1000_phy_82578) || 5088 (hw->phy.type == e1000_phy_82579) || 5089 (hw->phy.type == e1000_phy_i217) || 5090 (hw->phy.type == e1000_phy_82577)) { 5091 ew32(FCRTV_PCH, hw->fc.refresh_time); 5092 5093 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 5094 hw->fc.pause_time); 5095 if (ret_val) 5096 return ret_val; 5097 } 5098 5099 return e1000e_set_fc_watermarks(hw); 5100 } 5101 5102 /** 5103 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 5104 * @hw: pointer to the HW structure 5105 * 5106 * Configures the kumeran interface to the PHY to wait the appropriate time 5107 * when polling the PHY, then call the generic setup_copper_link to finish 5108 * configuring the copper link. 5109 **/ 5110 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5111 { 5112 u32 ctrl; 5113 s32 ret_val; 5114 u16 reg_data; 5115 5116 ctrl = er32(CTRL); 5117 ctrl |= E1000_CTRL_SLU; 5118 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5119 ew32(CTRL, ctrl); 5120 5121 /* Set the mac to wait the maximum time between each iteration 5122 * and increase the max iterations when polling the phy; 5123 * this fixes erroneous timeouts at 10Mbps. 5124 */ 5125 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5126 if (ret_val) 5127 return ret_val; 5128 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5129 ®_data); 5130 if (ret_val) 5131 return ret_val; 5132 reg_data |= 0x3F; 5133 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5134 reg_data); 5135 if (ret_val) 5136 return ret_val; 5137 5138 switch (hw->phy.type) { 5139 case e1000_phy_igp_3: 5140 ret_val = e1000e_copper_link_setup_igp(hw); 5141 if (ret_val) 5142 return ret_val; 5143 break; 5144 case e1000_phy_bm: 5145 case e1000_phy_82578: 5146 ret_val = e1000e_copper_link_setup_m88(hw); 5147 if (ret_val) 5148 return ret_val; 5149 break; 5150 case e1000_phy_82577: 5151 case e1000_phy_82579: 5152 ret_val = e1000_copper_link_setup_82577(hw); 5153 if (ret_val) 5154 return ret_val; 5155 break; 5156 case e1000_phy_ife: 5157 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5158 if (ret_val) 5159 return ret_val; 5160 5161 reg_data &= ~IFE_PMC_AUTO_MDIX; 5162 5163 switch (hw->phy.mdix) { 5164 case 1: 5165 reg_data &= ~IFE_PMC_FORCE_MDIX; 5166 break; 5167 case 2: 5168 reg_data |= IFE_PMC_FORCE_MDIX; 5169 break; 5170 case 0: 5171 default: 5172 reg_data |= IFE_PMC_AUTO_MDIX; 5173 break; 5174 } 5175 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5176 if (ret_val) 5177 return ret_val; 5178 break; 5179 default: 5180 break; 5181 } 5182 5183 return e1000e_setup_copper_link(hw); 5184 } 5185 5186 /** 5187 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5188 * @hw: pointer to the HW structure 5189 * 5190 * Calls the PHY specific link setup function and then calls the 5191 * generic setup_copper_link to finish configuring the link for 5192 * Lynxpoint PCH devices 5193 **/ 5194 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5195 { 5196 u32 ctrl; 5197 s32 ret_val; 5198 5199 ctrl = er32(CTRL); 5200 ctrl |= E1000_CTRL_SLU; 5201 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5202 ew32(CTRL, ctrl); 5203 5204 ret_val = e1000_copper_link_setup_82577(hw); 5205 if (ret_val) 5206 return ret_val; 5207 5208 return e1000e_setup_copper_link(hw); 5209 } 5210 5211 /** 5212 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5213 * @hw: pointer to the HW structure 5214 * @speed: pointer to store current link speed 5215 * @duplex: pointer to store the current link duplex 5216 * 5217 * Calls the generic get_speed_and_duplex to retrieve the current link 5218 * information and then calls the Kumeran lock loss workaround for links at 5219 * gigabit speeds. 5220 **/ 5221 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5222 u16 *duplex) 5223 { 5224 s32 ret_val; 5225 5226 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5227 if (ret_val) 5228 return ret_val; 5229 5230 if ((hw->mac.type == e1000_ich8lan) && 5231 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5232 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5233 } 5234 5235 return ret_val; 5236 } 5237 5238 /** 5239 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5240 * @hw: pointer to the HW structure 5241 * 5242 * Work-around for 82566 Kumeran PCS lock loss: 5243 * On link status change (i.e. PCI reset, speed change) and link is up and 5244 * speed is gigabit- 5245 * 0) if workaround is optionally disabled do nothing 5246 * 1) wait 1ms for Kumeran link to come up 5247 * 2) check Kumeran Diagnostic register PCS lock loss bit 5248 * 3) if not set the link is locked (all is good), otherwise... 5249 * 4) reset the PHY 5250 * 5) repeat up to 10 times 5251 * Note: this is only called for IGP3 copper when speed is 1gb. 5252 **/ 5253 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5254 { 5255 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5256 u32 phy_ctrl; 5257 s32 ret_val; 5258 u16 i, data; 5259 bool link; 5260 5261 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5262 return 0; 5263 5264 /* Make sure link is up before proceeding. If not just return. 5265 * Attempting this while link is negotiating fouled up link 5266 * stability 5267 */ 5268 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5269 if (!link) 5270 return 0; 5271 5272 for (i = 0; i < 10; i++) { 5273 /* read once to clear */ 5274 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5275 if (ret_val) 5276 return ret_val; 5277 /* and again to get new status */ 5278 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5279 if (ret_val) 5280 return ret_val; 5281 5282 /* check for PCS lock */ 5283 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5284 return 0; 5285 5286 /* Issue PHY reset */ 5287 e1000_phy_hw_reset(hw); 5288 mdelay(5); 5289 } 5290 /* Disable GigE link negotiation */ 5291 phy_ctrl = er32(PHY_CTRL); 5292 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5293 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5294 ew32(PHY_CTRL, phy_ctrl); 5295 5296 /* Call gig speed drop workaround on Gig disable before accessing 5297 * any PHY registers 5298 */ 5299 e1000e_gig_downshift_workaround_ich8lan(hw); 5300 5301 /* unable to acquire PCS lock */ 5302 return -E1000_ERR_PHY; 5303 } 5304 5305 /** 5306 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5307 * @hw: pointer to the HW structure 5308 * @state: boolean value used to set the current Kumeran workaround state 5309 * 5310 * If ICH8, set the current Kumeran workaround state (enabled - true 5311 * /disabled - false). 5312 **/ 5313 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5314 bool state) 5315 { 5316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5317 5318 if (hw->mac.type != e1000_ich8lan) { 5319 e_dbg("Workaround applies to ICH8 only.\n"); 5320 return; 5321 } 5322 5323 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5324 } 5325 5326 /** 5327 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5328 * @hw: pointer to the HW structure 5329 * 5330 * Workaround for 82566 power-down on D3 entry: 5331 * 1) disable gigabit link 5332 * 2) write VR power-down enable 5333 * 3) read it back 5334 * Continue if successful, else issue LCD reset and repeat 5335 **/ 5336 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5337 { 5338 u32 reg; 5339 u16 data; 5340 u8 retry = 0; 5341 5342 if (hw->phy.type != e1000_phy_igp_3) 5343 return; 5344 5345 /* Try the workaround twice (if needed) */ 5346 do { 5347 /* Disable link */ 5348 reg = er32(PHY_CTRL); 5349 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5350 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5351 ew32(PHY_CTRL, reg); 5352 5353 /* Call gig speed drop workaround on Gig disable before 5354 * accessing any PHY registers 5355 */ 5356 if (hw->mac.type == e1000_ich8lan) 5357 e1000e_gig_downshift_workaround_ich8lan(hw); 5358 5359 /* Write VR power-down enable */ 5360 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5361 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5362 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5363 5364 /* Read it back and test */ 5365 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5366 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5367 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5368 break; 5369 5370 /* Issue PHY reset and repeat at most one more time */ 5371 reg = er32(CTRL); 5372 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5373 retry++; 5374 } while (retry); 5375 } 5376 5377 /** 5378 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5379 * @hw: pointer to the HW structure 5380 * 5381 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5382 * LPLU, Gig disable, MDIC PHY reset): 5383 * 1) Set Kumeran Near-end loopback 5384 * 2) Clear Kumeran Near-end loopback 5385 * Should only be called for ICH8[m] devices with any 1G Phy. 5386 **/ 5387 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5388 { 5389 s32 ret_val; 5390 u16 reg_data; 5391 5392 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5393 return; 5394 5395 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5396 ®_data); 5397 if (ret_val) 5398 return; 5399 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5400 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5401 reg_data); 5402 if (ret_val) 5403 return; 5404 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5405 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5406 } 5407 5408 /** 5409 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5410 * @hw: pointer to the HW structure 5411 * 5412 * During S0 to Sx transition, it is possible the link remains at gig 5413 * instead of negotiating to a lower speed. Before going to Sx, set 5414 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5415 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5416 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5417 * needs to be written. 5418 * Parts that support (and are linked to a partner which support) EEE in 5419 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5420 * than 10Mbps w/o EEE. 5421 **/ 5422 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5423 { 5424 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5425 u32 phy_ctrl; 5426 s32 ret_val; 5427 5428 phy_ctrl = er32(PHY_CTRL); 5429 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5430 5431 if (hw->phy.type == e1000_phy_i217) { 5432 u16 phy_reg, device_id = hw->adapter->pdev->device; 5433 5434 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5435 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5436 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5437 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5438 (hw->mac.type >= e1000_pch_spt)) { 5439 u32 fextnvm6 = er32(FEXTNVM6); 5440 5441 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5442 } 5443 5444 ret_val = hw->phy.ops.acquire(hw); 5445 if (ret_val) 5446 goto out; 5447 5448 if (!dev_spec->eee_disable) { 5449 u16 eee_advert; 5450 5451 ret_val = 5452 e1000_read_emi_reg_locked(hw, 5453 I217_EEE_ADVERTISEMENT, 5454 &eee_advert); 5455 if (ret_val) 5456 goto release; 5457 5458 /* Disable LPLU if both link partners support 100BaseT 5459 * EEE and 100Full is advertised on both ends of the 5460 * link, and enable Auto Enable LPI since there will 5461 * be no driver to enable LPI while in Sx. 5462 */ 5463 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5464 (dev_spec->eee_lp_ability & 5465 I82579_EEE_100_SUPPORTED) && 5466 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5467 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5468 E1000_PHY_CTRL_NOND0A_LPLU); 5469 5470 /* Set Auto Enable LPI after link up */ 5471 e1e_rphy_locked(hw, 5472 I217_LPI_GPIO_CTRL, &phy_reg); 5473 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5474 e1e_wphy_locked(hw, 5475 I217_LPI_GPIO_CTRL, phy_reg); 5476 } 5477 } 5478 5479 /* For i217 Intel Rapid Start Technology support, 5480 * when the system is going into Sx and no manageability engine 5481 * is present, the driver must configure proxy to reset only on 5482 * power good. LPI (Low Power Idle) state must also reset only 5483 * on power good, as well as the MTA (Multicast table array). 5484 * The SMBus release must also be disabled on LCD reset. 5485 */ 5486 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5487 /* Enable proxy to reset only on power good. */ 5488 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5489 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5490 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5491 5492 /* Set bit enable LPI (EEE) to reset only on 5493 * power good. 5494 */ 5495 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5496 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5497 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5498 5499 /* Disable the SMB release on LCD reset. */ 5500 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5501 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5502 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5503 } 5504 5505 /* Enable MTA to reset for Intel Rapid Start Technology 5506 * Support 5507 */ 5508 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5509 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5510 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5511 5512 release: 5513 hw->phy.ops.release(hw); 5514 } 5515 out: 5516 ew32(PHY_CTRL, phy_ctrl); 5517 5518 if (hw->mac.type == e1000_ich8lan) 5519 e1000e_gig_downshift_workaround_ich8lan(hw); 5520 5521 if (hw->mac.type >= e1000_pchlan) { 5522 e1000_oem_bits_config_ich8lan(hw, false); 5523 5524 /* Reset PHY to activate OEM bits on 82577/8 */ 5525 if (hw->mac.type == e1000_pchlan) 5526 e1000e_phy_hw_reset_generic(hw); 5527 5528 ret_val = hw->phy.ops.acquire(hw); 5529 if (ret_val) 5530 return; 5531 e1000_write_smbus_addr(hw); 5532 hw->phy.ops.release(hw); 5533 } 5534 } 5535 5536 /** 5537 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5538 * @hw: pointer to the HW structure 5539 * 5540 * During Sx to S0 transitions on non-managed devices or managed devices 5541 * on which PHY resets are not blocked, if the PHY registers cannot be 5542 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5543 * the PHY. 5544 * On i217, setup Intel Rapid Start Technology. 5545 **/ 5546 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5547 { 5548 s32 ret_val; 5549 5550 if (hw->mac.type < e1000_pch2lan) 5551 return; 5552 5553 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5554 if (ret_val) { 5555 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5556 return; 5557 } 5558 5559 /* For i217 Intel Rapid Start Technology support when the system 5560 * is transitioning from Sx and no manageability engine is present 5561 * configure SMBus to restore on reset, disable proxy, and enable 5562 * the reset on MTA (Multicast table array). 5563 */ 5564 if (hw->phy.type == e1000_phy_i217) { 5565 u16 phy_reg; 5566 5567 ret_val = hw->phy.ops.acquire(hw); 5568 if (ret_val) { 5569 e_dbg("Failed to setup iRST\n"); 5570 return; 5571 } 5572 5573 /* Clear Auto Enable LPI after link up */ 5574 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5575 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5576 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5577 5578 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5579 /* Restore clear on SMB if no manageability engine 5580 * is present 5581 */ 5582 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5583 if (ret_val) 5584 goto release; 5585 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5586 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5587 5588 /* Disable Proxy */ 5589 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5590 } 5591 /* Enable reset on MTA */ 5592 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5593 if (ret_val) 5594 goto release; 5595 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5596 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5597 release: 5598 if (ret_val) 5599 e_dbg("Error %d in resume workarounds\n", ret_val); 5600 hw->phy.ops.release(hw); 5601 } 5602 } 5603 5604 /** 5605 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5606 * @hw: pointer to the HW structure 5607 * 5608 * Return the LED back to the default configuration. 5609 **/ 5610 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5611 { 5612 if (hw->phy.type == e1000_phy_ife) 5613 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5614 5615 ew32(LEDCTL, hw->mac.ledctl_default); 5616 return 0; 5617 } 5618 5619 /** 5620 * e1000_led_on_ich8lan - Turn LEDs on 5621 * @hw: pointer to the HW structure 5622 * 5623 * Turn on the LEDs. 5624 **/ 5625 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5626 { 5627 if (hw->phy.type == e1000_phy_ife) 5628 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5629 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5630 5631 ew32(LEDCTL, hw->mac.ledctl_mode2); 5632 return 0; 5633 } 5634 5635 /** 5636 * e1000_led_off_ich8lan - Turn LEDs off 5637 * @hw: pointer to the HW structure 5638 * 5639 * Turn off the LEDs. 5640 **/ 5641 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5642 { 5643 if (hw->phy.type == e1000_phy_ife) 5644 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5645 (IFE_PSCL_PROBE_MODE | 5646 IFE_PSCL_PROBE_LEDS_OFF)); 5647 5648 ew32(LEDCTL, hw->mac.ledctl_mode1); 5649 return 0; 5650 } 5651 5652 /** 5653 * e1000_setup_led_pchlan - Configures SW controllable LED 5654 * @hw: pointer to the HW structure 5655 * 5656 * This prepares the SW controllable LED for use. 5657 **/ 5658 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5659 { 5660 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5661 } 5662 5663 /** 5664 * e1000_cleanup_led_pchlan - Restore the default LED operation 5665 * @hw: pointer to the HW structure 5666 * 5667 * Return the LED back to the default configuration. 5668 **/ 5669 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5670 { 5671 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5672 } 5673 5674 /** 5675 * e1000_led_on_pchlan - Turn LEDs on 5676 * @hw: pointer to the HW structure 5677 * 5678 * Turn on the LEDs. 5679 **/ 5680 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5681 { 5682 u16 data = (u16)hw->mac.ledctl_mode2; 5683 u32 i, led; 5684 5685 /* If no link, then turn LED on by setting the invert bit 5686 * for each LED that's mode is "link_up" in ledctl_mode2. 5687 */ 5688 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5689 for (i = 0; i < 3; i++) { 5690 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5691 if ((led & E1000_PHY_LED0_MODE_MASK) != 5692 E1000_LEDCTL_MODE_LINK_UP) 5693 continue; 5694 if (led & E1000_PHY_LED0_IVRT) 5695 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5696 else 5697 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5698 } 5699 } 5700 5701 return e1e_wphy(hw, HV_LED_CONFIG, data); 5702 } 5703 5704 /** 5705 * e1000_led_off_pchlan - Turn LEDs off 5706 * @hw: pointer to the HW structure 5707 * 5708 * Turn off the LEDs. 5709 **/ 5710 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5711 { 5712 u16 data = (u16)hw->mac.ledctl_mode1; 5713 u32 i, led; 5714 5715 /* If no link, then turn LED off by clearing the invert bit 5716 * for each LED that's mode is "link_up" in ledctl_mode1. 5717 */ 5718 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5719 for (i = 0; i < 3; i++) { 5720 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5721 if ((led & E1000_PHY_LED0_MODE_MASK) != 5722 E1000_LEDCTL_MODE_LINK_UP) 5723 continue; 5724 if (led & E1000_PHY_LED0_IVRT) 5725 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5726 else 5727 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5728 } 5729 } 5730 5731 return e1e_wphy(hw, HV_LED_CONFIG, data); 5732 } 5733 5734 /** 5735 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5736 * @hw: pointer to the HW structure 5737 * 5738 * Read appropriate register for the config done bit for completion status 5739 * and configure the PHY through s/w for EEPROM-less parts. 5740 * 5741 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5742 * config done bit, so only an error is logged and continues. If we were 5743 * to return with error, EEPROM-less silicon would not be able to be reset 5744 * or change link. 5745 **/ 5746 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5747 { 5748 s32 ret_val = 0; 5749 u32 bank = 0; 5750 u32 status; 5751 5752 e1000e_get_cfg_done_generic(hw); 5753 5754 /* Wait for indication from h/w that it has completed basic config */ 5755 if (hw->mac.type >= e1000_ich10lan) { 5756 e1000_lan_init_done_ich8lan(hw); 5757 } else { 5758 ret_val = e1000e_get_auto_rd_done(hw); 5759 if (ret_val) { 5760 /* When auto config read does not complete, do not 5761 * return with an error. This can happen in situations 5762 * where there is no eeprom and prevents getting link. 5763 */ 5764 e_dbg("Auto Read Done did not complete\n"); 5765 ret_val = 0; 5766 } 5767 } 5768 5769 /* Clear PHY Reset Asserted bit */ 5770 status = er32(STATUS); 5771 if (status & E1000_STATUS_PHYRA) 5772 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5773 else 5774 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5775 5776 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5777 if (hw->mac.type <= e1000_ich9lan) { 5778 if (!(er32(EECD) & E1000_EECD_PRES) && 5779 (hw->phy.type == e1000_phy_igp_3)) { 5780 e1000e_phy_init_script_igp3(hw); 5781 } 5782 } else { 5783 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5784 /* Maybe we should do a basic PHY config */ 5785 e_dbg("EEPROM not present\n"); 5786 ret_val = -E1000_ERR_CONFIG; 5787 } 5788 } 5789 5790 return ret_val; 5791 } 5792 5793 /** 5794 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5795 * @hw: pointer to the HW structure 5796 * 5797 * In the case of a PHY power down to save power, or to turn off link during a 5798 * driver unload, or wake on lan is not enabled, remove the link. 5799 **/ 5800 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5801 { 5802 /* If the management interface is not enabled, then power down */ 5803 if (!(hw->mac.ops.check_mng_mode(hw) || 5804 hw->phy.ops.check_reset_block(hw))) 5805 e1000_power_down_phy_copper(hw); 5806 } 5807 5808 /** 5809 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5810 * @hw: pointer to the HW structure 5811 * 5812 * Clears hardware counters specific to the silicon family and calls 5813 * clear_hw_cntrs_generic to clear all general purpose counters. 5814 **/ 5815 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5816 { 5817 u16 phy_data; 5818 s32 ret_val; 5819 5820 e1000e_clear_hw_cntrs_base(hw); 5821 5822 er32(ALGNERRC); 5823 er32(RXERRC); 5824 er32(TNCRS); 5825 er32(CEXTERR); 5826 er32(TSCTC); 5827 er32(TSCTFC); 5828 5829 er32(MGTPRC); 5830 er32(MGTPDC); 5831 er32(MGTPTC); 5832 5833 er32(IAC); 5834 er32(ICRXOC); 5835 5836 /* Clear PHY statistics registers */ 5837 if ((hw->phy.type == e1000_phy_82578) || 5838 (hw->phy.type == e1000_phy_82579) || 5839 (hw->phy.type == e1000_phy_i217) || 5840 (hw->phy.type == e1000_phy_82577)) { 5841 ret_val = hw->phy.ops.acquire(hw); 5842 if (ret_val) 5843 return; 5844 ret_val = hw->phy.ops.set_page(hw, 5845 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5846 if (ret_val) 5847 goto release; 5848 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5849 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5850 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5851 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5852 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5853 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5854 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5855 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5856 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5857 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5858 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5859 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5860 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5861 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5862 release: 5863 hw->phy.ops.release(hw); 5864 } 5865 } 5866 5867 static const struct e1000_mac_operations ich8_mac_ops = { 5868 /* check_mng_mode dependent on mac type */ 5869 .check_for_link = e1000_check_for_copper_link_ich8lan, 5870 /* cleanup_led dependent on mac type */ 5871 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5872 .get_bus_info = e1000_get_bus_info_ich8lan, 5873 .set_lan_id = e1000_set_lan_id_single_port, 5874 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5875 /* led_on dependent on mac type */ 5876 /* led_off dependent on mac type */ 5877 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5878 .reset_hw = e1000_reset_hw_ich8lan, 5879 .init_hw = e1000_init_hw_ich8lan, 5880 .setup_link = e1000_setup_link_ich8lan, 5881 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5882 /* id_led_init dependent on mac type */ 5883 .config_collision_dist = e1000e_config_collision_dist_generic, 5884 .rar_set = e1000e_rar_set_generic, 5885 .rar_get_count = e1000e_rar_get_count_generic, 5886 }; 5887 5888 static const struct e1000_phy_operations ich8_phy_ops = { 5889 .acquire = e1000_acquire_swflag_ich8lan, 5890 .check_reset_block = e1000_check_reset_block_ich8lan, 5891 .commit = NULL, 5892 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5893 .get_cable_length = e1000e_get_cable_length_igp_2, 5894 .read_reg = e1000e_read_phy_reg_igp, 5895 .release = e1000_release_swflag_ich8lan, 5896 .reset = e1000_phy_hw_reset_ich8lan, 5897 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5898 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5899 .write_reg = e1000e_write_phy_reg_igp, 5900 }; 5901 5902 static const struct e1000_nvm_operations ich8_nvm_ops = { 5903 .acquire = e1000_acquire_nvm_ich8lan, 5904 .read = e1000_read_nvm_ich8lan, 5905 .release = e1000_release_nvm_ich8lan, 5906 .reload = e1000e_reload_nvm_generic, 5907 .update = e1000_update_nvm_checksum_ich8lan, 5908 .valid_led_default = e1000_valid_led_default_ich8lan, 5909 .validate = e1000_validate_nvm_checksum_ich8lan, 5910 .write = e1000_write_nvm_ich8lan, 5911 }; 5912 5913 static const struct e1000_nvm_operations spt_nvm_ops = { 5914 .acquire = e1000_acquire_nvm_ich8lan, 5915 .release = e1000_release_nvm_ich8lan, 5916 .read = e1000_read_nvm_spt, 5917 .update = e1000_update_nvm_checksum_spt, 5918 .reload = e1000e_reload_nvm_generic, 5919 .valid_led_default = e1000_valid_led_default_ich8lan, 5920 .validate = e1000_validate_nvm_checksum_ich8lan, 5921 .write = e1000_write_nvm_ich8lan, 5922 }; 5923 5924 const struct e1000_info e1000_ich8_info = { 5925 .mac = e1000_ich8lan, 5926 .flags = FLAG_HAS_WOL 5927 | FLAG_IS_ICH 5928 | FLAG_HAS_CTRLEXT_ON_LOAD 5929 | FLAG_HAS_AMT 5930 | FLAG_HAS_FLASH 5931 | FLAG_APME_IN_WUC, 5932 .pba = 8, 5933 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5934 .get_variants = e1000_get_variants_ich8lan, 5935 .mac_ops = &ich8_mac_ops, 5936 .phy_ops = &ich8_phy_ops, 5937 .nvm_ops = &ich8_nvm_ops, 5938 }; 5939 5940 const struct e1000_info e1000_ich9_info = { 5941 .mac = e1000_ich9lan, 5942 .flags = FLAG_HAS_JUMBO_FRAMES 5943 | FLAG_IS_ICH 5944 | FLAG_HAS_WOL 5945 | FLAG_HAS_CTRLEXT_ON_LOAD 5946 | FLAG_HAS_AMT 5947 | FLAG_HAS_FLASH 5948 | FLAG_APME_IN_WUC, 5949 .pba = 18, 5950 .max_hw_frame_size = DEFAULT_JUMBO, 5951 .get_variants = e1000_get_variants_ich8lan, 5952 .mac_ops = &ich8_mac_ops, 5953 .phy_ops = &ich8_phy_ops, 5954 .nvm_ops = &ich8_nvm_ops, 5955 }; 5956 5957 const struct e1000_info e1000_ich10_info = { 5958 .mac = e1000_ich10lan, 5959 .flags = FLAG_HAS_JUMBO_FRAMES 5960 | FLAG_IS_ICH 5961 | FLAG_HAS_WOL 5962 | FLAG_HAS_CTRLEXT_ON_LOAD 5963 | FLAG_HAS_AMT 5964 | FLAG_HAS_FLASH 5965 | FLAG_APME_IN_WUC, 5966 .pba = 18, 5967 .max_hw_frame_size = DEFAULT_JUMBO, 5968 .get_variants = e1000_get_variants_ich8lan, 5969 .mac_ops = &ich8_mac_ops, 5970 .phy_ops = &ich8_phy_ops, 5971 .nvm_ops = &ich8_nvm_ops, 5972 }; 5973 5974 const struct e1000_info e1000_pch_info = { 5975 .mac = e1000_pchlan, 5976 .flags = FLAG_IS_ICH 5977 | FLAG_HAS_WOL 5978 | FLAG_HAS_CTRLEXT_ON_LOAD 5979 | FLAG_HAS_AMT 5980 | FLAG_HAS_FLASH 5981 | FLAG_HAS_JUMBO_FRAMES 5982 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5983 | FLAG_APME_IN_WUC, 5984 .flags2 = FLAG2_HAS_PHY_STATS, 5985 .pba = 26, 5986 .max_hw_frame_size = 4096, 5987 .get_variants = e1000_get_variants_ich8lan, 5988 .mac_ops = &ich8_mac_ops, 5989 .phy_ops = &ich8_phy_ops, 5990 .nvm_ops = &ich8_nvm_ops, 5991 }; 5992 5993 const struct e1000_info e1000_pch2_info = { 5994 .mac = e1000_pch2lan, 5995 .flags = FLAG_IS_ICH 5996 | FLAG_HAS_WOL 5997 | FLAG_HAS_HW_TIMESTAMP 5998 | FLAG_HAS_CTRLEXT_ON_LOAD 5999 | FLAG_HAS_AMT 6000 | FLAG_HAS_FLASH 6001 | FLAG_HAS_JUMBO_FRAMES 6002 | FLAG_APME_IN_WUC, 6003 .flags2 = FLAG2_HAS_PHY_STATS 6004 | FLAG2_HAS_EEE 6005 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6006 .pba = 26, 6007 .max_hw_frame_size = 9022, 6008 .get_variants = e1000_get_variants_ich8lan, 6009 .mac_ops = &ich8_mac_ops, 6010 .phy_ops = &ich8_phy_ops, 6011 .nvm_ops = &ich8_nvm_ops, 6012 }; 6013 6014 const struct e1000_info e1000_pch_lpt_info = { 6015 .mac = e1000_pch_lpt, 6016 .flags = FLAG_IS_ICH 6017 | FLAG_HAS_WOL 6018 | FLAG_HAS_HW_TIMESTAMP 6019 | FLAG_HAS_CTRLEXT_ON_LOAD 6020 | FLAG_HAS_AMT 6021 | FLAG_HAS_FLASH 6022 | FLAG_HAS_JUMBO_FRAMES 6023 | FLAG_APME_IN_WUC, 6024 .flags2 = FLAG2_HAS_PHY_STATS 6025 | FLAG2_HAS_EEE 6026 | FLAG2_CHECK_SYSTIM_OVERFLOW, 6027 .pba = 26, 6028 .max_hw_frame_size = 9022, 6029 .get_variants = e1000_get_variants_ich8lan, 6030 .mac_ops = &ich8_mac_ops, 6031 .phy_ops = &ich8_phy_ops, 6032 .nvm_ops = &ich8_nvm_ops, 6033 }; 6034 6035 const struct e1000_info e1000_pch_spt_info = { 6036 .mac = e1000_pch_spt, 6037 .flags = FLAG_IS_ICH 6038 | FLAG_HAS_WOL 6039 | FLAG_HAS_HW_TIMESTAMP 6040 | FLAG_HAS_CTRLEXT_ON_LOAD 6041 | FLAG_HAS_AMT 6042 | FLAG_HAS_FLASH 6043 | FLAG_HAS_JUMBO_FRAMES 6044 | FLAG_APME_IN_WUC, 6045 .flags2 = FLAG2_HAS_PHY_STATS 6046 | FLAG2_HAS_EEE, 6047 .pba = 26, 6048 .max_hw_frame_size = 9022, 6049 .get_variants = e1000_get_variants_ich8lan, 6050 .mac_ops = &ich8_mac_ops, 6051 .phy_ops = &ich8_phy_ops, 6052 .nvm_ops = &spt_nvm_ops, 6053 }; 6054 6055 const struct e1000_info e1000_pch_cnp_info = { 6056 .mac = e1000_pch_cnp, 6057 .flags = FLAG_IS_ICH 6058 | FLAG_HAS_WOL 6059 | FLAG_HAS_HW_TIMESTAMP 6060 | FLAG_HAS_CTRLEXT_ON_LOAD 6061 | FLAG_HAS_AMT 6062 | FLAG_HAS_FLASH 6063 | FLAG_HAS_JUMBO_FRAMES 6064 | FLAG_APME_IN_WUC, 6065 .flags2 = FLAG2_HAS_PHY_STATS 6066 | FLAG2_HAS_EEE, 6067 .pba = 26, 6068 .max_hw_frame_size = 9022, 6069 .get_variants = e1000_get_variants_ich8lan, 6070 .mac_ops = &ich8_mac_ops, 6071 .phy_ops = &ich8_phy_ops, 6072 .nvm_ops = &spt_nvm_ops, 6073 }; 6074 6075 const struct e1000_info e1000_pch_tgp_info = { 6076 .mac = e1000_pch_tgp, 6077 .flags = FLAG_IS_ICH 6078 | FLAG_HAS_WOL 6079 | FLAG_HAS_HW_TIMESTAMP 6080 | FLAG_HAS_CTRLEXT_ON_LOAD 6081 | FLAG_HAS_AMT 6082 | FLAG_HAS_FLASH 6083 | FLAG_HAS_JUMBO_FRAMES 6084 | FLAG_APME_IN_WUC, 6085 .flags2 = FLAG2_HAS_PHY_STATS 6086 | FLAG2_HAS_EEE, 6087 .pba = 26, 6088 .max_hw_frame_size = 9022, 6089 .get_variants = e1000_get_variants_ich8lan, 6090 .mac_ops = &ich8_mac_ops, 6091 .phy_ops = &ich8_phy_ops, 6092 .nvm_ops = &spt_nvm_ops, 6093 }; 6094 6095 const struct e1000_info e1000_pch_adp_info = { 6096 .mac = e1000_pch_adp, 6097 .flags = FLAG_IS_ICH 6098 | FLAG_HAS_WOL 6099 | FLAG_HAS_HW_TIMESTAMP 6100 | FLAG_HAS_CTRLEXT_ON_LOAD 6101 | FLAG_HAS_AMT 6102 | FLAG_HAS_FLASH 6103 | FLAG_HAS_JUMBO_FRAMES 6104 | FLAG_APME_IN_WUC, 6105 .flags2 = FLAG2_HAS_PHY_STATS 6106 | FLAG2_HAS_EEE, 6107 .pba = 26, 6108 .max_hw_frame_size = 9022, 6109 .get_variants = e1000_get_variants_ich8lan, 6110 .mac_ops = &ich8_mac_ops, 6111 .phy_ops = &ich8_phy_ops, 6112 .nvm_ops = &spt_nvm_ops, 6113 }; 6114 6115 const struct e1000_info e1000_pch_mtp_info = { 6116 .mac = e1000_pch_mtp, 6117 .flags = FLAG_IS_ICH 6118 | FLAG_HAS_WOL 6119 | FLAG_HAS_HW_TIMESTAMP 6120 | FLAG_HAS_CTRLEXT_ON_LOAD 6121 | FLAG_HAS_AMT 6122 | FLAG_HAS_FLASH 6123 | FLAG_HAS_JUMBO_FRAMES 6124 | FLAG_APME_IN_WUC, 6125 .flags2 = FLAG2_HAS_PHY_STATS 6126 | FLAG2_HAS_EEE, 6127 .pba = 26, 6128 .max_hw_frame_size = 9022, 6129 .get_variants = e1000_get_variants_ich8lan, 6130 .mac_ops = &ich8_mac_ops, 6131 .phy_ops = &ich8_phy_ops, 6132 .nvm_ops = &spt_nvm_ops, 6133 }; 6134