1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Unforce SMBus mode in PHY */ 226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 229 230 /* Unforce SMBus mode in MAC */ 231 mac_reg = er32(CTRL_EXT); 232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 233 ew32(CTRL_EXT, mac_reg); 234 } 235 } 236 237 return true; 238 } 239 240 /** 241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 242 * @hw: pointer to the HW structure 243 * 244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 245 * used to reset the PHY to a quiescent state when necessary. 246 **/ 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 248 { 249 u32 mac_reg; 250 251 /* Set Phy Config Counter to 50msec */ 252 mac_reg = er32(FEXTNVM3); 253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 255 ew32(FEXTNVM3, mac_reg); 256 257 /* Toggle LANPHYPC Value bit */ 258 mac_reg = er32(CTRL); 259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 261 ew32(CTRL, mac_reg); 262 e1e_flush(); 263 usleep_range(10, 20); 264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 265 ew32(CTRL, mac_reg); 266 e1e_flush(); 267 268 if (hw->mac.type < e1000_pch_lpt) { 269 msleep(50); 270 } else { 271 u16 count = 20; 272 273 do { 274 usleep_range(5000, 6000); 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 276 277 msleep(30); 278 } 279 } 280 281 /** 282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 283 * @hw: pointer to the HW structure 284 * 285 * Workarounds/flow necessary for PHY initialization during driver load 286 * and resume paths. 287 **/ 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 289 { 290 struct e1000_adapter *adapter = hw->adapter; 291 u32 mac_reg, fwsm = er32(FWSM); 292 s32 ret_val; 293 294 /* Gate automatic PHY configuration by hardware on managed and 295 * non-managed 82579 and newer adapters. 296 */ 297 e1000_gate_hw_phy_config_ich8lan(hw, true); 298 299 /* It is not possible to be certain of the current state of ULP 300 * so forcibly disable it. 301 */ 302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 303 ret_val = e1000_disable_ulp_lpt_lp(hw, true); 304 if (ret_val) 305 e_warn("Failed to disable ULP\n"); 306 307 ret_val = hw->phy.ops.acquire(hw); 308 if (ret_val) { 309 e_dbg("Failed to initialize PHY flow\n"); 310 goto out; 311 } 312 313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 314 * inaccessible and resetting the PHY is not blocked, toggle the 315 * LANPHYPC Value bit to force the interconnect to PCIe mode. 316 */ 317 switch (hw->mac.type) { 318 case e1000_pch_lpt: 319 case e1000_pch_spt: 320 case e1000_pch_cnp: 321 case e1000_pch_tgp: 322 case e1000_pch_adp: 323 case e1000_pch_mtp: 324 if (e1000_phy_is_accessible_pchlan(hw)) 325 break; 326 327 /* Before toggling LANPHYPC, see if PHY is accessible by 328 * forcing MAC to SMBus mode first. 329 */ 330 mac_reg = er32(CTRL_EXT); 331 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 332 ew32(CTRL_EXT, mac_reg); 333 334 /* Wait 50 milliseconds for MAC to finish any retries 335 * that it might be trying to perform from previous 336 * attempts to acknowledge any phy read requests. 337 */ 338 msleep(50); 339 340 fallthrough; 341 case e1000_pch2lan: 342 if (e1000_phy_is_accessible_pchlan(hw)) 343 break; 344 345 fallthrough; 346 case e1000_pchlan: 347 if ((hw->mac.type == e1000_pchlan) && 348 (fwsm & E1000_ICH_FWSM_FW_VALID)) 349 break; 350 351 if (hw->phy.ops.check_reset_block(hw)) { 352 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 353 ret_val = -E1000_ERR_PHY; 354 break; 355 } 356 357 /* Toggle LANPHYPC Value bit */ 358 e1000_toggle_lanphypc_pch_lpt(hw); 359 if (hw->mac.type >= e1000_pch_lpt) { 360 if (e1000_phy_is_accessible_pchlan(hw)) 361 break; 362 363 /* Toggling LANPHYPC brings the PHY out of SMBus mode 364 * so ensure that the MAC is also out of SMBus mode 365 */ 366 mac_reg = er32(CTRL_EXT); 367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 368 ew32(CTRL_EXT, mac_reg); 369 370 if (e1000_phy_is_accessible_pchlan(hw)) 371 break; 372 373 ret_val = -E1000_ERR_PHY; 374 } 375 break; 376 default: 377 break; 378 } 379 380 hw->phy.ops.release(hw); 381 if (!ret_val) { 382 383 /* Check to see if able to reset PHY. Print error if not */ 384 if (hw->phy.ops.check_reset_block(hw)) { 385 e_err("Reset blocked by ME\n"); 386 goto out; 387 } 388 389 /* Reset the PHY before any access to it. Doing so, ensures 390 * that the PHY is in a known good state before we read/write 391 * PHY registers. The generic reset is sufficient here, 392 * because we haven't determined the PHY type yet. 393 */ 394 ret_val = e1000e_phy_hw_reset_generic(hw); 395 if (ret_val) 396 goto out; 397 398 /* On a successful reset, possibly need to wait for the PHY 399 * to quiesce to an accessible state before returning control 400 * to the calling function. If the PHY does not quiesce, then 401 * return E1000E_BLK_PHY_RESET, as this is the condition that 402 * the PHY is in. 403 */ 404 ret_val = hw->phy.ops.check_reset_block(hw); 405 if (ret_val) 406 e_err("ME blocked access to PHY after reset\n"); 407 } 408 409 out: 410 /* Ungate automatic PHY configuration on non-managed 82579 */ 411 if ((hw->mac.type == e1000_pch2lan) && 412 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 413 usleep_range(10000, 11000); 414 e1000_gate_hw_phy_config_ich8lan(hw, false); 415 } 416 417 return ret_val; 418 } 419 420 /** 421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 422 * @hw: pointer to the HW structure 423 * 424 * Initialize family-specific PHY parameters and function pointers. 425 **/ 426 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 427 { 428 struct e1000_phy_info *phy = &hw->phy; 429 s32 ret_val; 430 431 phy->addr = 1; 432 phy->reset_delay_us = 100; 433 434 phy->ops.set_page = e1000_set_page_igp; 435 phy->ops.read_reg = e1000_read_phy_reg_hv; 436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 440 phy->ops.write_reg = e1000_write_phy_reg_hv; 441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 443 phy->ops.power_up = e1000_power_up_phy_copper; 444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 446 447 phy->id = e1000_phy_unknown; 448 449 ret_val = e1000_init_phy_workarounds_pchlan(hw); 450 if (ret_val) 451 return ret_val; 452 453 if (phy->id == e1000_phy_unknown) 454 switch (hw->mac.type) { 455 default: 456 ret_val = e1000e_get_phy_id(hw); 457 if (ret_val) 458 return ret_val; 459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 460 break; 461 fallthrough; 462 case e1000_pch2lan: 463 case e1000_pch_lpt: 464 case e1000_pch_spt: 465 case e1000_pch_cnp: 466 case e1000_pch_tgp: 467 case e1000_pch_adp: 468 case e1000_pch_mtp: 469 /* In case the PHY needs to be in mdio slow mode, 470 * set slow mode and try to get the PHY id again. 471 */ 472 ret_val = e1000_set_mdio_slow_mode_hv(hw); 473 if (ret_val) 474 return ret_val; 475 ret_val = e1000e_get_phy_id(hw); 476 if (ret_val) 477 return ret_val; 478 break; 479 } 480 phy->type = e1000e_get_phy_type_from_id(phy->id); 481 482 switch (phy->type) { 483 case e1000_phy_82577: 484 case e1000_phy_82579: 485 case e1000_phy_i217: 486 phy->ops.check_polarity = e1000_check_polarity_82577; 487 phy->ops.force_speed_duplex = 488 e1000_phy_force_speed_duplex_82577; 489 phy->ops.get_cable_length = e1000_get_cable_length_82577; 490 phy->ops.get_info = e1000_get_phy_info_82577; 491 phy->ops.commit = e1000e_phy_sw_reset; 492 break; 493 case e1000_phy_82578: 494 phy->ops.check_polarity = e1000_check_polarity_m88; 495 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 496 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 497 phy->ops.get_info = e1000e_get_phy_info_m88; 498 break; 499 default: 500 ret_val = -E1000_ERR_PHY; 501 break; 502 } 503 504 return ret_val; 505 } 506 507 /** 508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 509 * @hw: pointer to the HW structure 510 * 511 * Initialize family-specific PHY parameters and function pointers. 512 **/ 513 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 514 { 515 struct e1000_phy_info *phy = &hw->phy; 516 s32 ret_val; 517 u16 i = 0; 518 519 phy->addr = 1; 520 phy->reset_delay_us = 100; 521 522 phy->ops.power_up = e1000_power_up_phy_copper; 523 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 524 525 /* We may need to do this twice - once for IGP and if that fails, 526 * we'll set BM func pointers and try again 527 */ 528 ret_val = e1000e_determine_phy_address(hw); 529 if (ret_val) { 530 phy->ops.write_reg = e1000e_write_phy_reg_bm; 531 phy->ops.read_reg = e1000e_read_phy_reg_bm; 532 ret_val = e1000e_determine_phy_address(hw); 533 if (ret_val) { 534 e_dbg("Cannot determine PHY addr. Erroring out\n"); 535 return ret_val; 536 } 537 } 538 539 phy->id = 0; 540 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 541 (i++ < 100)) { 542 usleep_range(1000, 1100); 543 ret_val = e1000e_get_phy_id(hw); 544 if (ret_val) 545 return ret_val; 546 } 547 548 /* Verify phy id */ 549 switch (phy->id) { 550 case IGP03E1000_E_PHY_ID: 551 phy->type = e1000_phy_igp_3; 552 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 553 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 554 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 555 phy->ops.get_info = e1000e_get_phy_info_igp; 556 phy->ops.check_polarity = e1000_check_polarity_igp; 557 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 558 break; 559 case IFE_E_PHY_ID: 560 case IFE_PLUS_E_PHY_ID: 561 case IFE_C_E_PHY_ID: 562 phy->type = e1000_phy_ife; 563 phy->autoneg_mask = E1000_ALL_NOT_GIG; 564 phy->ops.get_info = e1000_get_phy_info_ife; 565 phy->ops.check_polarity = e1000_check_polarity_ife; 566 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 567 break; 568 case BME1000_E_PHY_ID: 569 phy->type = e1000_phy_bm; 570 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 571 phy->ops.read_reg = e1000e_read_phy_reg_bm; 572 phy->ops.write_reg = e1000e_write_phy_reg_bm; 573 phy->ops.commit = e1000e_phy_sw_reset; 574 phy->ops.get_info = e1000e_get_phy_info_m88; 575 phy->ops.check_polarity = e1000_check_polarity_m88; 576 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 577 break; 578 default: 579 return -E1000_ERR_PHY; 580 } 581 582 return 0; 583 } 584 585 /** 586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 587 * @hw: pointer to the HW structure 588 * 589 * Initialize family-specific NVM parameters and function 590 * pointers. 591 **/ 592 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 593 { 594 struct e1000_nvm_info *nvm = &hw->nvm; 595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 596 u32 gfpreg, sector_base_addr, sector_end_addr; 597 u16 i; 598 u32 nvm_size; 599 600 nvm->type = e1000_nvm_flash_sw; 601 602 if (hw->mac.type >= e1000_pch_spt) { 603 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 604 * STRAP register. This is because in SPT the GbE Flash region 605 * is no longer accessed through the flash registers. Instead, 606 * the mechanism has changed, and the Flash region access 607 * registers are now implemented in GbE memory space. 608 */ 609 nvm->flash_base_addr = 0; 610 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 611 * NVM_SIZE_MULTIPLIER; 612 nvm->flash_bank_size = nvm_size / 2; 613 /* Adjust to word count */ 614 nvm->flash_bank_size /= sizeof(u16); 615 /* Set the base address for flash register access */ 616 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 617 } else { 618 /* Can't read flash registers if register set isn't mapped. */ 619 if (!hw->flash_address) { 620 e_dbg("ERROR: Flash registers not mapped\n"); 621 return -E1000_ERR_CONFIG; 622 } 623 624 gfpreg = er32flash(ICH_FLASH_GFPREG); 625 626 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 627 * Add 1 to sector_end_addr since this sector is included in 628 * the overall size. 629 */ 630 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 631 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 632 633 /* flash_base_addr is byte-aligned */ 634 nvm->flash_base_addr = sector_base_addr 635 << FLASH_SECTOR_ADDR_SHIFT; 636 637 /* find total size of the NVM, then cut in half since the total 638 * size represents two separate NVM banks. 639 */ 640 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 641 << FLASH_SECTOR_ADDR_SHIFT); 642 nvm->flash_bank_size /= 2; 643 /* Adjust to word count */ 644 nvm->flash_bank_size /= sizeof(u16); 645 } 646 647 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 648 649 /* Clear shadow ram */ 650 for (i = 0; i < nvm->word_size; i++) { 651 dev_spec->shadow_ram[i].modified = false; 652 dev_spec->shadow_ram[i].value = 0xFFFF; 653 } 654 655 return 0; 656 } 657 658 /** 659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 660 * @hw: pointer to the HW structure 661 * 662 * Initialize family-specific MAC parameters and function 663 * pointers. 664 **/ 665 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 666 { 667 struct e1000_mac_info *mac = &hw->mac; 668 669 /* Set media type function pointer */ 670 hw->phy.media_type = e1000_media_type_copper; 671 672 /* Set mta register count */ 673 mac->mta_reg_count = 32; 674 /* Set rar entry count */ 675 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 676 if (mac->type == e1000_ich8lan) 677 mac->rar_entry_count--; 678 /* FWSM register */ 679 mac->has_fwsm = true; 680 /* ARC subsystem not supported */ 681 mac->arc_subsystem_valid = false; 682 /* Adaptive IFS supported */ 683 mac->adaptive_ifs = true; 684 685 /* LED and other operations */ 686 switch (mac->type) { 687 case e1000_ich8lan: 688 case e1000_ich9lan: 689 case e1000_ich10lan: 690 /* check management mode */ 691 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 692 /* ID LED init */ 693 mac->ops.id_led_init = e1000e_id_led_init_generic; 694 /* blink LED */ 695 mac->ops.blink_led = e1000e_blink_led_generic; 696 /* setup LED */ 697 mac->ops.setup_led = e1000e_setup_led_generic; 698 /* cleanup LED */ 699 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 700 /* turn on/off LED */ 701 mac->ops.led_on = e1000_led_on_ich8lan; 702 mac->ops.led_off = e1000_led_off_ich8lan; 703 break; 704 case e1000_pch2lan: 705 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 706 mac->ops.rar_set = e1000_rar_set_pch2lan; 707 fallthrough; 708 case e1000_pch_lpt: 709 case e1000_pch_spt: 710 case e1000_pch_cnp: 711 case e1000_pch_tgp: 712 case e1000_pch_adp: 713 case e1000_pch_mtp: 714 case e1000_pchlan: 715 /* check management mode */ 716 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 717 /* ID LED init */ 718 mac->ops.id_led_init = e1000_id_led_init_pchlan; 719 /* setup LED */ 720 mac->ops.setup_led = e1000_setup_led_pchlan; 721 /* cleanup LED */ 722 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 723 /* turn on/off LED */ 724 mac->ops.led_on = e1000_led_on_pchlan; 725 mac->ops.led_off = e1000_led_off_pchlan; 726 break; 727 default: 728 break; 729 } 730 731 if (mac->type >= e1000_pch_lpt) { 732 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 733 mac->ops.rar_set = e1000_rar_set_pch_lpt; 734 mac->ops.setup_physical_interface = 735 e1000_setup_copper_link_pch_lpt; 736 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 737 } 738 739 /* Enable PCS Lock-loss workaround for ICH8 */ 740 if (mac->type == e1000_ich8lan) 741 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 742 743 return 0; 744 } 745 746 /** 747 * __e1000_access_emi_reg_locked - Read/write EMI register 748 * @hw: pointer to the HW structure 749 * @address: EMI address to program 750 * @data: pointer to value to read/write from/to the EMI address 751 * @read: boolean flag to indicate read or write 752 * 753 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 754 **/ 755 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 756 u16 *data, bool read) 757 { 758 s32 ret_val; 759 760 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 761 if (ret_val) 762 return ret_val; 763 764 if (read) 765 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 766 else 767 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 768 769 return ret_val; 770 } 771 772 /** 773 * e1000_read_emi_reg_locked - Read Extended Management Interface register 774 * @hw: pointer to the HW structure 775 * @addr: EMI address to program 776 * @data: value to be read from the EMI address 777 * 778 * Assumes the SW/FW/HW Semaphore is already acquired. 779 **/ 780 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 781 { 782 return __e1000_access_emi_reg_locked(hw, addr, data, true); 783 } 784 785 /** 786 * e1000_write_emi_reg_locked - Write Extended Management Interface register 787 * @hw: pointer to the HW structure 788 * @addr: EMI address to program 789 * @data: value to be written to the EMI address 790 * 791 * Assumes the SW/FW/HW Semaphore is already acquired. 792 **/ 793 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 794 { 795 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 796 } 797 798 /** 799 * e1000_set_eee_pchlan - Enable/disable EEE support 800 * @hw: pointer to the HW structure 801 * 802 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 803 * the link and the EEE capabilities of the link partner. The LPI Control 804 * register bits will remain set only if/when link is up. 805 * 806 * EEE LPI must not be asserted earlier than one second after link is up. 807 * On 82579, EEE LPI should not be enabled until such time otherwise there 808 * can be link issues with some switches. Other devices can have EEE LPI 809 * enabled immediately upon link up since they have a timer in hardware which 810 * prevents LPI from being asserted too early. 811 **/ 812 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 813 { 814 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 815 s32 ret_val; 816 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 817 818 switch (hw->phy.type) { 819 case e1000_phy_82579: 820 lpa = I82579_EEE_LP_ABILITY; 821 pcs_status = I82579_EEE_PCS_STATUS; 822 adv_addr = I82579_EEE_ADVERTISEMENT; 823 break; 824 case e1000_phy_i217: 825 lpa = I217_EEE_LP_ABILITY; 826 pcs_status = I217_EEE_PCS_STATUS; 827 adv_addr = I217_EEE_ADVERTISEMENT; 828 break; 829 default: 830 return 0; 831 } 832 833 ret_val = hw->phy.ops.acquire(hw); 834 if (ret_val) 835 return ret_val; 836 837 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 838 if (ret_val) 839 goto release; 840 841 /* Clear bits that enable EEE in various speeds */ 842 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 843 844 /* Enable EEE if not disabled by user */ 845 if (!dev_spec->eee_disable) { 846 /* Save off link partner's EEE ability */ 847 ret_val = e1000_read_emi_reg_locked(hw, lpa, 848 &dev_spec->eee_lp_ability); 849 if (ret_val) 850 goto release; 851 852 /* Read EEE advertisement */ 853 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 854 if (ret_val) 855 goto release; 856 857 /* Enable EEE only for speeds in which the link partner is 858 * EEE capable and for which we advertise EEE. 859 */ 860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 861 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 862 863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 864 e1e_rphy_locked(hw, MII_LPA, &data); 865 if (data & LPA_100FULL) 866 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 867 else 868 /* EEE is not supported in 100Half, so ignore 869 * partner's EEE in 100 ability if full-duplex 870 * is not advertised. 871 */ 872 dev_spec->eee_lp_ability &= 873 ~I82579_EEE_100_SUPPORTED; 874 } 875 } 876 877 if (hw->phy.type == e1000_phy_82579) { 878 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 879 &data); 880 if (ret_val) 881 goto release; 882 883 data &= ~I82579_LPI_100_PLL_SHUT; 884 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 885 data); 886 } 887 888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 889 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 890 if (ret_val) 891 goto release; 892 893 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 894 release: 895 hw->phy.ops.release(hw); 896 897 return ret_val; 898 } 899 900 /** 901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 902 * @hw: pointer to the HW structure 903 * @link: link up bool flag 904 * 905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 906 * preventing further DMA write requests. Workaround the issue by disabling 907 * the de-assertion of the clock request when in 1Gpbs mode. 908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 909 * speeds in order to avoid Tx hangs. 910 **/ 911 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 912 { 913 u32 fextnvm6 = er32(FEXTNVM6); 914 u32 status = er32(STATUS); 915 s32 ret_val = 0; 916 u16 reg; 917 918 if (link && (status & E1000_STATUS_SPEED_1000)) { 919 ret_val = hw->phy.ops.acquire(hw); 920 if (ret_val) 921 return ret_val; 922 923 ret_val = 924 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 925 ®); 926 if (ret_val) 927 goto release; 928 929 ret_val = 930 e1000e_write_kmrn_reg_locked(hw, 931 E1000_KMRNCTRLSTA_K1_CONFIG, 932 reg & 933 ~E1000_KMRNCTRLSTA_K1_ENABLE); 934 if (ret_val) 935 goto release; 936 937 usleep_range(10, 20); 938 939 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 940 941 ret_val = 942 e1000e_write_kmrn_reg_locked(hw, 943 E1000_KMRNCTRLSTA_K1_CONFIG, 944 reg); 945 release: 946 hw->phy.ops.release(hw); 947 } else { 948 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 949 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 950 951 if ((hw->phy.revision > 5) || !link || 952 ((status & E1000_STATUS_SPEED_100) && 953 (status & E1000_STATUS_FD))) 954 goto update_fextnvm6; 955 956 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 957 if (ret_val) 958 return ret_val; 959 960 /* Clear link status transmit timeout */ 961 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 962 963 if (status & E1000_STATUS_SPEED_100) { 964 /* Set inband Tx timeout to 5x10us for 100Half */ 965 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 966 967 /* Do not extend the K1 entry latency for 100Half */ 968 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 969 } else { 970 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 971 reg |= 50 << 972 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 973 974 /* Extend the K1 entry latency for 10 Mbps */ 975 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 976 } 977 978 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 979 if (ret_val) 980 return ret_val; 981 982 update_fextnvm6: 983 ew32(FEXTNVM6, fextnvm6); 984 } 985 986 return ret_val; 987 } 988 989 /** 990 * e1000_platform_pm_pch_lpt - Set platform power management values 991 * @hw: pointer to the HW structure 992 * @link: bool indicating link status 993 * 994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 996 * when link is up (which must not exceed the maximum latency supported 997 * by the platform), otherwise specify there is no LTR requirement. 998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 999 * latencies in the LTR Extended Capability Structure in the PCIe Extended 1000 * Capability register set, on this device LTR is set by writing the 1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 1003 * message to the PMC. 1004 **/ 1005 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 1006 { 1007 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1008 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1009 u16 lat_enc = 0; /* latency encoded */ 1010 1011 if (link) { 1012 u16 speed, duplex, scale = 0; 1013 u16 max_snoop, max_nosnoop; 1014 u16 max_ltr_enc; /* max LTR latency encoded */ 1015 u64 value; 1016 u32 rxa; 1017 1018 if (!hw->adapter->max_frame_size) { 1019 e_dbg("max_frame_size not set.\n"); 1020 return -E1000_ERR_CONFIG; 1021 } 1022 1023 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1024 if (!speed) { 1025 e_dbg("Speed not set.\n"); 1026 return -E1000_ERR_CONFIG; 1027 } 1028 1029 /* Rx Packet Buffer Allocation size (KB) */ 1030 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1031 1032 /* Determine the maximum latency tolerated by the device. 1033 * 1034 * Per the PCIe spec, the tolerated latencies are encoded as 1035 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1036 * a 10-bit value (0-1023) to provide a range from 1 ns to 1037 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1038 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1039 */ 1040 rxa *= 512; 1041 value = (rxa > hw->adapter->max_frame_size) ? 1042 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1043 0; 1044 1045 while (value > PCI_LTR_VALUE_MASK) { 1046 scale++; 1047 value = DIV_ROUND_UP(value, BIT(5)); 1048 } 1049 if (scale > E1000_LTRV_SCALE_MAX) { 1050 e_dbg("Invalid LTR latency scale %d\n", scale); 1051 return -E1000_ERR_CONFIG; 1052 } 1053 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1054 1055 /* Determine the maximum latency tolerated by the platform */ 1056 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1057 &max_snoop); 1058 pci_read_config_word(hw->adapter->pdev, 1059 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1060 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1061 1062 if (lat_enc > max_ltr_enc) 1063 lat_enc = max_ltr_enc; 1064 } 1065 1066 /* Set Snoop and No-Snoop latencies the same */ 1067 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1068 ew32(LTRV, reg); 1069 1070 return 0; 1071 } 1072 1073 /** 1074 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1075 * @hw: pointer to the HW structure 1076 * @to_sx: boolean indicating a system power state transition to Sx 1077 * 1078 * When link is down, configure ULP mode to significantly reduce the power 1079 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1080 * ME firmware to start the ULP configuration. If not on an ME enabled 1081 * system, configure the ULP mode by software. 1082 */ 1083 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1084 { 1085 u32 mac_reg; 1086 s32 ret_val = 0; 1087 u16 phy_reg; 1088 u16 oem_reg = 0; 1089 1090 if ((hw->mac.type < e1000_pch_lpt) || 1091 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1092 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1093 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1094 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1095 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1096 return 0; 1097 1098 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1099 /* Request ME configure ULP mode in the PHY */ 1100 mac_reg = er32(H2ME); 1101 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1102 ew32(H2ME, mac_reg); 1103 1104 goto out; 1105 } 1106 1107 if (!to_sx) { 1108 int i = 0; 1109 1110 /* Poll up to 5 seconds for Cable Disconnected indication */ 1111 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1112 /* Bail if link is re-acquired */ 1113 if (er32(STATUS) & E1000_STATUS_LU) 1114 return -E1000_ERR_PHY; 1115 1116 if (i++ == 100) 1117 break; 1118 1119 msleep(50); 1120 } 1121 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1122 (er32(FEXT) & 1123 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1124 } 1125 1126 ret_val = hw->phy.ops.acquire(hw); 1127 if (ret_val) 1128 goto out; 1129 1130 /* Force SMBus mode in PHY */ 1131 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1132 if (ret_val) 1133 goto release; 1134 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1135 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1136 1137 /* Force SMBus mode in MAC */ 1138 mac_reg = er32(CTRL_EXT); 1139 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1140 ew32(CTRL_EXT, mac_reg); 1141 1142 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1143 * LPLU and disable Gig speed when entering ULP 1144 */ 1145 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1146 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1147 &oem_reg); 1148 if (ret_val) 1149 goto release; 1150 1151 phy_reg = oem_reg; 1152 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1153 1154 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1155 phy_reg); 1156 1157 if (ret_val) 1158 goto release; 1159 } 1160 1161 /* Set Inband ULP Exit, Reset to SMBus mode and 1162 * Disable SMBus Release on PERST# in PHY 1163 */ 1164 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1165 if (ret_val) 1166 goto release; 1167 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1168 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1169 if (to_sx) { 1170 if (er32(WUFC) & E1000_WUFC_LNKC) 1171 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1172 else 1173 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1174 1175 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1176 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1177 } else { 1178 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1179 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1180 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1181 } 1182 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1183 1184 /* Set Disable SMBus Release on PERST# in MAC */ 1185 mac_reg = er32(FEXTNVM7); 1186 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1187 ew32(FEXTNVM7, mac_reg); 1188 1189 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1190 phy_reg |= I218_ULP_CONFIG1_START; 1191 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1192 1193 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1194 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1195 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1196 oem_reg); 1197 if (ret_val) 1198 goto release; 1199 } 1200 1201 release: 1202 hw->phy.ops.release(hw); 1203 out: 1204 if (ret_val) 1205 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1206 else 1207 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1208 1209 return ret_val; 1210 } 1211 1212 /** 1213 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1214 * @hw: pointer to the HW structure 1215 * @force: boolean indicating whether or not to force disabling ULP 1216 * 1217 * Un-configure ULP mode when link is up, the system is transitioned from 1218 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1219 * system, poll for an indication from ME that ULP has been un-configured. 1220 * If not on an ME enabled system, un-configure the ULP mode by software. 1221 * 1222 * During nominal operation, this function is called when link is acquired 1223 * to disable ULP mode (force=false); otherwise, for example when unloading 1224 * the driver or during Sx->S0 transitions, this is called with force=true 1225 * to forcibly disable ULP. 1226 */ 1227 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1228 { 1229 s32 ret_val = 0; 1230 u32 mac_reg; 1231 u16 phy_reg; 1232 int i = 0; 1233 1234 if ((hw->mac.type < e1000_pch_lpt) || 1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1236 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1237 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1238 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1239 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1240 return 0; 1241 1242 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1243 if (force) { 1244 /* Request ME un-configure ULP mode in the PHY */ 1245 mac_reg = er32(H2ME); 1246 mac_reg &= ~E1000_H2ME_ULP; 1247 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1248 ew32(H2ME, mac_reg); 1249 } 1250 1251 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1252 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1253 if (i++ == 30) { 1254 ret_val = -E1000_ERR_PHY; 1255 goto out; 1256 } 1257 1258 usleep_range(10000, 11000); 1259 } 1260 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1261 1262 if (force) { 1263 mac_reg = er32(H2ME); 1264 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1265 ew32(H2ME, mac_reg); 1266 } else { 1267 /* Clear H2ME.ULP after ME ULP configuration */ 1268 mac_reg = er32(H2ME); 1269 mac_reg &= ~E1000_H2ME_ULP; 1270 ew32(H2ME, mac_reg); 1271 } 1272 1273 goto out; 1274 } 1275 1276 ret_val = hw->phy.ops.acquire(hw); 1277 if (ret_val) 1278 goto out; 1279 1280 if (force) 1281 /* Toggle LANPHYPC Value bit */ 1282 e1000_toggle_lanphypc_pch_lpt(hw); 1283 1284 /* Unforce SMBus mode in PHY */ 1285 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1286 if (ret_val) { 1287 /* The MAC might be in PCIe mode, so temporarily force to 1288 * SMBus mode in order to access the PHY. 1289 */ 1290 mac_reg = er32(CTRL_EXT); 1291 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1292 ew32(CTRL_EXT, mac_reg); 1293 1294 msleep(50); 1295 1296 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1297 &phy_reg); 1298 if (ret_val) 1299 goto release; 1300 } 1301 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1302 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1303 1304 /* Unforce SMBus mode in MAC */ 1305 mac_reg = er32(CTRL_EXT); 1306 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1307 ew32(CTRL_EXT, mac_reg); 1308 1309 /* When ULP mode was previously entered, K1 was disabled by the 1310 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1311 */ 1312 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1313 if (ret_val) 1314 goto release; 1315 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1316 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1317 1318 /* Clear ULP enabled configuration */ 1319 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1320 if (ret_val) 1321 goto release; 1322 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1323 I218_ULP_CONFIG1_STICKY_ULP | 1324 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1325 I218_ULP_CONFIG1_WOL_HOST | 1326 I218_ULP_CONFIG1_INBAND_EXIT | 1327 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1328 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1329 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1330 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1331 1332 /* Commit ULP changes by starting auto ULP configuration */ 1333 phy_reg |= I218_ULP_CONFIG1_START; 1334 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1335 1336 /* Clear Disable SMBus Release on PERST# in MAC */ 1337 mac_reg = er32(FEXTNVM7); 1338 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1339 ew32(FEXTNVM7, mac_reg); 1340 1341 release: 1342 hw->phy.ops.release(hw); 1343 if (force) { 1344 e1000_phy_hw_reset(hw); 1345 msleep(50); 1346 } 1347 out: 1348 if (ret_val) 1349 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1350 else 1351 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1352 1353 return ret_val; 1354 } 1355 1356 /** 1357 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1358 * @hw: pointer to the HW structure 1359 * 1360 * Checks to see of the link status of the hardware has changed. If a 1361 * change in link status has been detected, then we read the PHY registers 1362 * to get the current speed/duplex if link exists. 1363 **/ 1364 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1365 { 1366 struct e1000_mac_info *mac = &hw->mac; 1367 s32 ret_val, tipg_reg = 0; 1368 u16 emi_addr, emi_val = 0; 1369 bool link; 1370 u16 phy_reg; 1371 1372 /* We only want to go out to the PHY registers to see if Auto-Neg 1373 * has completed and/or if our link status has changed. The 1374 * get_link_status flag is set upon receiving a Link Status 1375 * Change or Rx Sequence Error interrupt. 1376 */ 1377 if (!mac->get_link_status) 1378 return 0; 1379 mac->get_link_status = false; 1380 1381 /* First we want to see if the MII Status Register reports 1382 * link. If so, then we want to get the current speed/duplex 1383 * of the PHY. 1384 */ 1385 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1386 if (ret_val) 1387 goto out; 1388 1389 if (hw->mac.type == e1000_pchlan) { 1390 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1391 if (ret_val) 1392 goto out; 1393 } 1394 1395 /* When connected at 10Mbps half-duplex, some parts are excessively 1396 * aggressive resulting in many collisions. To avoid this, increase 1397 * the IPG and reduce Rx latency in the PHY. 1398 */ 1399 if ((hw->mac.type >= e1000_pch2lan) && link) { 1400 u16 speed, duplex; 1401 1402 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1403 tipg_reg = er32(TIPG); 1404 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1405 1406 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1407 tipg_reg |= 0xFF; 1408 /* Reduce Rx latency in analog PHY */ 1409 emi_val = 0; 1410 } else if (hw->mac.type >= e1000_pch_spt && 1411 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1412 tipg_reg |= 0xC; 1413 emi_val = 1; 1414 } else { 1415 1416 /* Roll back the default values */ 1417 tipg_reg |= 0x08; 1418 emi_val = 1; 1419 } 1420 1421 ew32(TIPG, tipg_reg); 1422 1423 ret_val = hw->phy.ops.acquire(hw); 1424 if (ret_val) 1425 goto out; 1426 1427 if (hw->mac.type == e1000_pch2lan) 1428 emi_addr = I82579_RX_CONFIG; 1429 else 1430 emi_addr = I217_RX_CONFIG; 1431 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1432 1433 if (hw->mac.type >= e1000_pch_lpt) { 1434 u16 phy_reg; 1435 1436 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1437 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1438 if (speed == SPEED_100 || speed == SPEED_10) 1439 phy_reg |= 0x3E8; 1440 else 1441 phy_reg |= 0xFA; 1442 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1443 1444 if (speed == SPEED_1000) { 1445 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1446 &phy_reg); 1447 1448 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1449 1450 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1451 phy_reg); 1452 } 1453 } 1454 hw->phy.ops.release(hw); 1455 1456 if (ret_val) 1457 goto out; 1458 1459 if (hw->mac.type >= e1000_pch_spt) { 1460 u16 data; 1461 u16 ptr_gap; 1462 1463 if (speed == SPEED_1000) { 1464 ret_val = hw->phy.ops.acquire(hw); 1465 if (ret_val) 1466 goto out; 1467 1468 ret_val = e1e_rphy_locked(hw, 1469 PHY_REG(776, 20), 1470 &data); 1471 if (ret_val) { 1472 hw->phy.ops.release(hw); 1473 goto out; 1474 } 1475 1476 ptr_gap = (data & (0x3FF << 2)) >> 2; 1477 if (ptr_gap < 0x18) { 1478 data &= ~(0x3FF << 2); 1479 data |= (0x18 << 2); 1480 ret_val = 1481 e1e_wphy_locked(hw, 1482 PHY_REG(776, 20), 1483 data); 1484 } 1485 hw->phy.ops.release(hw); 1486 if (ret_val) 1487 goto out; 1488 } else { 1489 ret_val = hw->phy.ops.acquire(hw); 1490 if (ret_val) 1491 goto out; 1492 1493 ret_val = e1e_wphy_locked(hw, 1494 PHY_REG(776, 20), 1495 0xC023); 1496 hw->phy.ops.release(hw); 1497 if (ret_val) 1498 goto out; 1499 1500 } 1501 } 1502 } 1503 1504 /* I217 Packet Loss issue: 1505 * ensure that FEXTNVM4 Beacon Duration is set correctly 1506 * on power up. 1507 * Set the Beacon Duration for I217 to 8 usec 1508 */ 1509 if (hw->mac.type >= e1000_pch_lpt) { 1510 u32 mac_reg; 1511 1512 mac_reg = er32(FEXTNVM4); 1513 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1514 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1515 ew32(FEXTNVM4, mac_reg); 1516 } 1517 1518 /* Work-around I218 hang issue */ 1519 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1520 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1521 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1522 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1523 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1524 if (ret_val) 1525 goto out; 1526 } 1527 if (hw->mac.type >= e1000_pch_lpt) { 1528 /* Set platform power management values for 1529 * Latency Tolerance Reporting (LTR) 1530 */ 1531 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1532 if (ret_val) 1533 goto out; 1534 } 1535 1536 /* Clear link partner's EEE ability */ 1537 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1538 1539 if (hw->mac.type >= e1000_pch_lpt) { 1540 u32 fextnvm6 = er32(FEXTNVM6); 1541 1542 if (hw->mac.type == e1000_pch_spt) { 1543 /* FEXTNVM6 K1-off workaround - for SPT only */ 1544 u32 pcieanacfg = er32(PCIEANACFG); 1545 1546 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1547 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1548 else 1549 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1550 } 1551 1552 ew32(FEXTNVM6, fextnvm6); 1553 } 1554 1555 if (!link) 1556 goto out; 1557 1558 switch (hw->mac.type) { 1559 case e1000_pch2lan: 1560 ret_val = e1000_k1_workaround_lv(hw); 1561 if (ret_val) 1562 return ret_val; 1563 fallthrough; 1564 case e1000_pchlan: 1565 if (hw->phy.type == e1000_phy_82578) { 1566 ret_val = e1000_link_stall_workaround_hv(hw); 1567 if (ret_val) 1568 return ret_val; 1569 } 1570 1571 /* Workaround for PCHx parts in half-duplex: 1572 * Set the number of preambles removed from the packet 1573 * when it is passed from the PHY to the MAC to prevent 1574 * the MAC from misinterpreting the packet type. 1575 */ 1576 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1577 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1578 1579 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1580 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1581 1582 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 /* Check if there was DownShift, must be checked 1589 * immediately after link-up 1590 */ 1591 e1000e_check_downshift(hw); 1592 1593 /* Enable/Disable EEE after link up */ 1594 if (hw->phy.type > e1000_phy_82579) { 1595 ret_val = e1000_set_eee_pchlan(hw); 1596 if (ret_val) 1597 return ret_val; 1598 } 1599 1600 /* If we are forcing speed/duplex, then we simply return since 1601 * we have already determined whether we have link or not. 1602 */ 1603 if (!mac->autoneg) 1604 return -E1000_ERR_CONFIG; 1605 1606 /* Auto-Neg is enabled. Auto Speed Detection takes care 1607 * of MAC speed/duplex configuration. So we only need to 1608 * configure Collision Distance in the MAC. 1609 */ 1610 mac->ops.config_collision_dist(hw); 1611 1612 /* Configure Flow Control now that Auto-Neg has completed. 1613 * First, we need to restore the desired flow control 1614 * settings because we may have had to re-autoneg with a 1615 * different link partner. 1616 */ 1617 ret_val = e1000e_config_fc_after_link_up(hw); 1618 if (ret_val) 1619 e_dbg("Error configuring flow control\n"); 1620 1621 return ret_val; 1622 1623 out: 1624 mac->get_link_status = true; 1625 return ret_val; 1626 } 1627 1628 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1629 { 1630 struct e1000_hw *hw = &adapter->hw; 1631 s32 rc; 1632 1633 rc = e1000_init_mac_params_ich8lan(hw); 1634 if (rc) 1635 return rc; 1636 1637 rc = e1000_init_nvm_params_ich8lan(hw); 1638 if (rc) 1639 return rc; 1640 1641 switch (hw->mac.type) { 1642 case e1000_ich8lan: 1643 case e1000_ich9lan: 1644 case e1000_ich10lan: 1645 rc = e1000_init_phy_params_ich8lan(hw); 1646 break; 1647 case e1000_pchlan: 1648 case e1000_pch2lan: 1649 case e1000_pch_lpt: 1650 case e1000_pch_spt: 1651 case e1000_pch_cnp: 1652 case e1000_pch_tgp: 1653 case e1000_pch_adp: 1654 case e1000_pch_mtp: 1655 rc = e1000_init_phy_params_pchlan(hw); 1656 break; 1657 default: 1658 break; 1659 } 1660 if (rc) 1661 return rc; 1662 1663 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1664 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1665 */ 1666 if ((adapter->hw.phy.type == e1000_phy_ife) || 1667 ((adapter->hw.mac.type >= e1000_pch2lan) && 1668 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1669 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1670 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1671 1672 hw->mac.ops.blink_led = NULL; 1673 } 1674 1675 if ((adapter->hw.mac.type == e1000_ich8lan) && 1676 (adapter->hw.phy.type != e1000_phy_ife)) 1677 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1678 1679 /* Enable workaround for 82579 w/ ME enabled */ 1680 if ((adapter->hw.mac.type == e1000_pch2lan) && 1681 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1682 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1683 1684 return 0; 1685 } 1686 1687 static DEFINE_MUTEX(nvm_mutex); 1688 1689 /** 1690 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1691 * @hw: pointer to the HW structure 1692 * 1693 * Acquires the mutex for performing NVM operations. 1694 **/ 1695 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1696 { 1697 mutex_lock(&nvm_mutex); 1698 1699 return 0; 1700 } 1701 1702 /** 1703 * e1000_release_nvm_ich8lan - Release NVM mutex 1704 * @hw: pointer to the HW structure 1705 * 1706 * Releases the mutex used while performing NVM operations. 1707 **/ 1708 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1709 { 1710 mutex_unlock(&nvm_mutex); 1711 } 1712 1713 /** 1714 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1715 * @hw: pointer to the HW structure 1716 * 1717 * Acquires the software control flag for performing PHY and select 1718 * MAC CSR accesses. 1719 **/ 1720 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1721 { 1722 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1723 s32 ret_val = 0; 1724 1725 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1726 &hw->adapter->state)) { 1727 e_dbg("contention for Phy access\n"); 1728 return -E1000_ERR_PHY; 1729 } 1730 1731 while (timeout) { 1732 extcnf_ctrl = er32(EXTCNF_CTRL); 1733 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1734 break; 1735 1736 mdelay(1); 1737 timeout--; 1738 } 1739 1740 if (!timeout) { 1741 e_dbg("SW has already locked the resource.\n"); 1742 ret_val = -E1000_ERR_CONFIG; 1743 goto out; 1744 } 1745 1746 timeout = SW_FLAG_TIMEOUT; 1747 1748 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1749 ew32(EXTCNF_CTRL, extcnf_ctrl); 1750 1751 while (timeout) { 1752 extcnf_ctrl = er32(EXTCNF_CTRL); 1753 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1754 break; 1755 1756 mdelay(1); 1757 timeout--; 1758 } 1759 1760 if (!timeout) { 1761 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1762 er32(FWSM), extcnf_ctrl); 1763 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1764 ew32(EXTCNF_CTRL, extcnf_ctrl); 1765 ret_val = -E1000_ERR_CONFIG; 1766 goto out; 1767 } 1768 1769 out: 1770 if (ret_val) 1771 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1772 1773 return ret_val; 1774 } 1775 1776 /** 1777 * e1000_release_swflag_ich8lan - Release software control flag 1778 * @hw: pointer to the HW structure 1779 * 1780 * Releases the software control flag for performing PHY and select 1781 * MAC CSR accesses. 1782 **/ 1783 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1784 { 1785 u32 extcnf_ctrl; 1786 1787 extcnf_ctrl = er32(EXTCNF_CTRL); 1788 1789 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1790 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1791 ew32(EXTCNF_CTRL, extcnf_ctrl); 1792 } else { 1793 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1794 } 1795 1796 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1797 } 1798 1799 /** 1800 * e1000_check_mng_mode_ich8lan - Checks management mode 1801 * @hw: pointer to the HW structure 1802 * 1803 * This checks if the adapter has any manageability enabled. 1804 * This is a function pointer entry point only called by read/write 1805 * routines for the PHY and NVM parts. 1806 **/ 1807 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1808 { 1809 u32 fwsm; 1810 1811 fwsm = er32(FWSM); 1812 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1813 ((fwsm & E1000_FWSM_MODE_MASK) == 1814 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1815 } 1816 1817 /** 1818 * e1000_check_mng_mode_pchlan - Checks management mode 1819 * @hw: pointer to the HW structure 1820 * 1821 * This checks if the adapter has iAMT enabled. 1822 * This is a function pointer entry point only called by read/write 1823 * routines for the PHY and NVM parts. 1824 **/ 1825 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1826 { 1827 u32 fwsm; 1828 1829 fwsm = er32(FWSM); 1830 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1831 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1832 } 1833 1834 /** 1835 * e1000_rar_set_pch2lan - Set receive address register 1836 * @hw: pointer to the HW structure 1837 * @addr: pointer to the receive address 1838 * @index: receive address array register 1839 * 1840 * Sets the receive address array register at index to the address passed 1841 * in by addr. For 82579, RAR[0] is the base address register that is to 1842 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1843 * Use SHRA[0-3] in place of those reserved for ME. 1844 **/ 1845 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1846 { 1847 u32 rar_low, rar_high; 1848 1849 /* HW expects these in little endian so we reverse the byte order 1850 * from network order (big endian) to little endian 1851 */ 1852 rar_low = ((u32)addr[0] | 1853 ((u32)addr[1] << 8) | 1854 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1855 1856 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1857 1858 /* If MAC address zero, no need to set the AV bit */ 1859 if (rar_low || rar_high) 1860 rar_high |= E1000_RAH_AV; 1861 1862 if (index == 0) { 1863 ew32(RAL(index), rar_low); 1864 e1e_flush(); 1865 ew32(RAH(index), rar_high); 1866 e1e_flush(); 1867 return 0; 1868 } 1869 1870 /* RAR[1-6] are owned by manageability. Skip those and program the 1871 * next address into the SHRA register array. 1872 */ 1873 if (index < (u32)(hw->mac.rar_entry_count)) { 1874 s32 ret_val; 1875 1876 ret_val = e1000_acquire_swflag_ich8lan(hw); 1877 if (ret_val) 1878 goto out; 1879 1880 ew32(SHRAL(index - 1), rar_low); 1881 e1e_flush(); 1882 ew32(SHRAH(index - 1), rar_high); 1883 e1e_flush(); 1884 1885 e1000_release_swflag_ich8lan(hw); 1886 1887 /* verify the register updates */ 1888 if ((er32(SHRAL(index - 1)) == rar_low) && 1889 (er32(SHRAH(index - 1)) == rar_high)) 1890 return 0; 1891 1892 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1893 (index - 1), er32(FWSM)); 1894 } 1895 1896 out: 1897 e_dbg("Failed to write receive address at index %d\n", index); 1898 return -E1000_ERR_CONFIG; 1899 } 1900 1901 /** 1902 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1903 * @hw: pointer to the HW structure 1904 * 1905 * Get the number of available receive registers that the Host can 1906 * program. SHRA[0-10] are the shared receive address registers 1907 * that are shared between the Host and manageability engine (ME). 1908 * ME can reserve any number of addresses and the host needs to be 1909 * able to tell how many available registers it has access to. 1910 **/ 1911 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1912 { 1913 u32 wlock_mac; 1914 u32 num_entries; 1915 1916 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1917 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1918 1919 switch (wlock_mac) { 1920 case 0: 1921 /* All SHRA[0..10] and RAR[0] available */ 1922 num_entries = hw->mac.rar_entry_count; 1923 break; 1924 case 1: 1925 /* Only RAR[0] available */ 1926 num_entries = 1; 1927 break; 1928 default: 1929 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1930 num_entries = wlock_mac + 1; 1931 break; 1932 } 1933 1934 return num_entries; 1935 } 1936 1937 /** 1938 * e1000_rar_set_pch_lpt - Set receive address registers 1939 * @hw: pointer to the HW structure 1940 * @addr: pointer to the receive address 1941 * @index: receive address array register 1942 * 1943 * Sets the receive address register array at index to the address passed 1944 * in by addr. For LPT, RAR[0] is the base address register that is to 1945 * contain the MAC address. SHRA[0-10] are the shared receive address 1946 * registers that are shared between the Host and manageability engine (ME). 1947 **/ 1948 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1949 { 1950 u32 rar_low, rar_high; 1951 u32 wlock_mac; 1952 1953 /* HW expects these in little endian so we reverse the byte order 1954 * from network order (big endian) to little endian 1955 */ 1956 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1957 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1958 1959 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1960 1961 /* If MAC address zero, no need to set the AV bit */ 1962 if (rar_low || rar_high) 1963 rar_high |= E1000_RAH_AV; 1964 1965 if (index == 0) { 1966 ew32(RAL(index), rar_low); 1967 e1e_flush(); 1968 ew32(RAH(index), rar_high); 1969 e1e_flush(); 1970 return 0; 1971 } 1972 1973 /* The manageability engine (ME) can lock certain SHRAR registers that 1974 * it is using - those registers are unavailable for use. 1975 */ 1976 if (index < hw->mac.rar_entry_count) { 1977 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1978 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1979 1980 /* Check if all SHRAR registers are locked */ 1981 if (wlock_mac == 1) 1982 goto out; 1983 1984 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1985 s32 ret_val; 1986 1987 ret_val = e1000_acquire_swflag_ich8lan(hw); 1988 1989 if (ret_val) 1990 goto out; 1991 1992 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1993 e1e_flush(); 1994 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1995 e1e_flush(); 1996 1997 e1000_release_swflag_ich8lan(hw); 1998 1999 /* verify the register updates */ 2000 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 2001 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 2002 return 0; 2003 } 2004 } 2005 2006 out: 2007 e_dbg("Failed to write receive address at index %d\n", index); 2008 return -E1000_ERR_CONFIG; 2009 } 2010 2011 /** 2012 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2013 * @hw: pointer to the HW structure 2014 * 2015 * Checks if firmware is blocking the reset of the PHY. 2016 * This is a function pointer entry point only called by 2017 * reset routines. 2018 **/ 2019 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2020 { 2021 bool blocked = false; 2022 int i = 0; 2023 2024 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2025 (i++ < 30)) 2026 usleep_range(10000, 11000); 2027 return blocked ? E1000_BLK_PHY_RESET : 0; 2028 } 2029 2030 /** 2031 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2032 * @hw: pointer to the HW structure 2033 * 2034 * Assumes semaphore already acquired. 2035 * 2036 **/ 2037 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2038 { 2039 u16 phy_data; 2040 u32 strap = er32(STRAP); 2041 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2042 E1000_STRAP_SMT_FREQ_SHIFT; 2043 s32 ret_val; 2044 2045 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2046 2047 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2048 if (ret_val) 2049 return ret_val; 2050 2051 phy_data &= ~HV_SMB_ADDR_MASK; 2052 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2053 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2054 2055 if (hw->phy.type == e1000_phy_i217) { 2056 /* Restore SMBus frequency */ 2057 if (freq--) { 2058 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2059 phy_data |= (freq & BIT(0)) << 2060 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2061 phy_data |= (freq & BIT(1)) << 2062 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2063 } else { 2064 e_dbg("Unsupported SMB frequency in PHY\n"); 2065 } 2066 } 2067 2068 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2069 } 2070 2071 /** 2072 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2073 * @hw: pointer to the HW structure 2074 * 2075 * SW should configure the LCD from the NVM extended configuration region 2076 * as a workaround for certain parts. 2077 **/ 2078 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2079 { 2080 struct e1000_phy_info *phy = &hw->phy; 2081 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2082 s32 ret_val = 0; 2083 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2084 2085 /* Initialize the PHY from the NVM on ICH platforms. This 2086 * is needed due to an issue where the NVM configuration is 2087 * not properly autoloaded after power transitions. 2088 * Therefore, after each PHY reset, we will load the 2089 * configuration data out of the NVM manually. 2090 */ 2091 switch (hw->mac.type) { 2092 case e1000_ich8lan: 2093 if (phy->type != e1000_phy_igp_3) 2094 return ret_val; 2095 2096 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2097 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2098 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2099 break; 2100 } 2101 fallthrough; 2102 case e1000_pchlan: 2103 case e1000_pch2lan: 2104 case e1000_pch_lpt: 2105 case e1000_pch_spt: 2106 case e1000_pch_cnp: 2107 case e1000_pch_tgp: 2108 case e1000_pch_adp: 2109 case e1000_pch_mtp: 2110 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2111 break; 2112 default: 2113 return ret_val; 2114 } 2115 2116 ret_val = hw->phy.ops.acquire(hw); 2117 if (ret_val) 2118 return ret_val; 2119 2120 data = er32(FEXTNVM); 2121 if (!(data & sw_cfg_mask)) 2122 goto release; 2123 2124 /* Make sure HW does not configure LCD from PHY 2125 * extended configuration before SW configuration 2126 */ 2127 data = er32(EXTCNF_CTRL); 2128 if ((hw->mac.type < e1000_pch2lan) && 2129 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2130 goto release; 2131 2132 cnf_size = er32(EXTCNF_SIZE); 2133 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2134 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2135 if (!cnf_size) 2136 goto release; 2137 2138 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2139 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2140 2141 if (((hw->mac.type == e1000_pchlan) && 2142 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2143 (hw->mac.type > e1000_pchlan)) { 2144 /* HW configures the SMBus address and LEDs when the 2145 * OEM and LCD Write Enable bits are set in the NVM. 2146 * When both NVM bits are cleared, SW will configure 2147 * them instead. 2148 */ 2149 ret_val = e1000_write_smbus_addr(hw); 2150 if (ret_val) 2151 goto release; 2152 2153 data = er32(LEDCTL); 2154 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2155 (u16)data); 2156 if (ret_val) 2157 goto release; 2158 } 2159 2160 /* Configure LCD from extended configuration region. */ 2161 2162 /* cnf_base_addr is in DWORD */ 2163 word_addr = (u16)(cnf_base_addr << 1); 2164 2165 for (i = 0; i < cnf_size; i++) { 2166 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2167 if (ret_val) 2168 goto release; 2169 2170 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2171 1, ®_addr); 2172 if (ret_val) 2173 goto release; 2174 2175 /* Save off the PHY page for future writes. */ 2176 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2177 phy_page = reg_data; 2178 continue; 2179 } 2180 2181 reg_addr &= PHY_REG_MASK; 2182 reg_addr |= phy_page; 2183 2184 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2185 if (ret_val) 2186 goto release; 2187 } 2188 2189 release: 2190 hw->phy.ops.release(hw); 2191 return ret_val; 2192 } 2193 2194 /** 2195 * e1000_k1_gig_workaround_hv - K1 Si workaround 2196 * @hw: pointer to the HW structure 2197 * @link: link up bool flag 2198 * 2199 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2200 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2201 * If link is down, the function will restore the default K1 setting located 2202 * in the NVM. 2203 **/ 2204 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2205 { 2206 s32 ret_val = 0; 2207 u16 status_reg = 0; 2208 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2209 2210 if (hw->mac.type != e1000_pchlan) 2211 return 0; 2212 2213 /* Wrap the whole flow with the sw flag */ 2214 ret_val = hw->phy.ops.acquire(hw); 2215 if (ret_val) 2216 return ret_val; 2217 2218 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2219 if (link) { 2220 if (hw->phy.type == e1000_phy_82578) { 2221 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2222 &status_reg); 2223 if (ret_val) 2224 goto release; 2225 2226 status_reg &= (BM_CS_STATUS_LINK_UP | 2227 BM_CS_STATUS_RESOLVED | 2228 BM_CS_STATUS_SPEED_MASK); 2229 2230 if (status_reg == (BM_CS_STATUS_LINK_UP | 2231 BM_CS_STATUS_RESOLVED | 2232 BM_CS_STATUS_SPEED_1000)) 2233 k1_enable = false; 2234 } 2235 2236 if (hw->phy.type == e1000_phy_82577) { 2237 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2238 if (ret_val) 2239 goto release; 2240 2241 status_reg &= (HV_M_STATUS_LINK_UP | 2242 HV_M_STATUS_AUTONEG_COMPLETE | 2243 HV_M_STATUS_SPEED_MASK); 2244 2245 if (status_reg == (HV_M_STATUS_LINK_UP | 2246 HV_M_STATUS_AUTONEG_COMPLETE | 2247 HV_M_STATUS_SPEED_1000)) 2248 k1_enable = false; 2249 } 2250 2251 /* Link stall fix for link up */ 2252 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2253 if (ret_val) 2254 goto release; 2255 2256 } else { 2257 /* Link stall fix for link down */ 2258 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2259 if (ret_val) 2260 goto release; 2261 } 2262 2263 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2264 2265 release: 2266 hw->phy.ops.release(hw); 2267 2268 return ret_val; 2269 } 2270 2271 /** 2272 * e1000_configure_k1_ich8lan - Configure K1 power state 2273 * @hw: pointer to the HW structure 2274 * @k1_enable: K1 state to configure 2275 * 2276 * Configure the K1 power state based on the provided parameter. 2277 * Assumes semaphore already acquired. 2278 * 2279 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2280 **/ 2281 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2282 { 2283 s32 ret_val; 2284 u32 ctrl_reg = 0; 2285 u32 ctrl_ext = 0; 2286 u32 reg = 0; 2287 u16 kmrn_reg = 0; 2288 2289 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2290 &kmrn_reg); 2291 if (ret_val) 2292 return ret_val; 2293 2294 if (k1_enable) 2295 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2296 else 2297 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2298 2299 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2300 kmrn_reg); 2301 if (ret_val) 2302 return ret_val; 2303 2304 usleep_range(20, 40); 2305 ctrl_ext = er32(CTRL_EXT); 2306 ctrl_reg = er32(CTRL); 2307 2308 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2309 reg |= E1000_CTRL_FRCSPD; 2310 ew32(CTRL, reg); 2311 2312 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2313 e1e_flush(); 2314 usleep_range(20, 40); 2315 ew32(CTRL, ctrl_reg); 2316 ew32(CTRL_EXT, ctrl_ext); 2317 e1e_flush(); 2318 usleep_range(20, 40); 2319 2320 return 0; 2321 } 2322 2323 /** 2324 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2325 * @hw: pointer to the HW structure 2326 * @d0_state: boolean if entering d0 or d3 device state 2327 * 2328 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2329 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2330 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2331 **/ 2332 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2333 { 2334 s32 ret_val = 0; 2335 u32 mac_reg; 2336 u16 oem_reg; 2337 2338 if (hw->mac.type < e1000_pchlan) 2339 return ret_val; 2340 2341 ret_val = hw->phy.ops.acquire(hw); 2342 if (ret_val) 2343 return ret_val; 2344 2345 if (hw->mac.type == e1000_pchlan) { 2346 mac_reg = er32(EXTCNF_CTRL); 2347 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2348 goto release; 2349 } 2350 2351 mac_reg = er32(FEXTNVM); 2352 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2353 goto release; 2354 2355 mac_reg = er32(PHY_CTRL); 2356 2357 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2358 if (ret_val) 2359 goto release; 2360 2361 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2362 2363 if (d0_state) { 2364 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2365 oem_reg |= HV_OEM_BITS_GBE_DIS; 2366 2367 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2368 oem_reg |= HV_OEM_BITS_LPLU; 2369 } else { 2370 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2371 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2372 oem_reg |= HV_OEM_BITS_GBE_DIS; 2373 2374 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2375 E1000_PHY_CTRL_NOND0A_LPLU)) 2376 oem_reg |= HV_OEM_BITS_LPLU; 2377 } 2378 2379 /* Set Restart auto-neg to activate the bits */ 2380 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2381 !hw->phy.ops.check_reset_block(hw)) 2382 oem_reg |= HV_OEM_BITS_RESTART_AN; 2383 2384 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2385 2386 release: 2387 hw->phy.ops.release(hw); 2388 2389 return ret_val; 2390 } 2391 2392 /** 2393 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2394 * @hw: pointer to the HW structure 2395 **/ 2396 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2397 { 2398 s32 ret_val; 2399 u16 data; 2400 2401 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2402 if (ret_val) 2403 return ret_val; 2404 2405 data |= HV_KMRN_MDIO_SLOW; 2406 2407 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2408 2409 return ret_val; 2410 } 2411 2412 /** 2413 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds 2414 * @hw: pointer to the HW structure 2415 * 2416 * A series of PHY workarounds to be done after every PHY reset. 2417 **/ 2418 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2419 { 2420 s32 ret_val = 0; 2421 u16 phy_data; 2422 2423 if (hw->mac.type != e1000_pchlan) 2424 return 0; 2425 2426 /* Set MDIO slow mode before any other MDIO access */ 2427 if (hw->phy.type == e1000_phy_82577) { 2428 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2429 if (ret_val) 2430 return ret_val; 2431 } 2432 2433 if (((hw->phy.type == e1000_phy_82577) && 2434 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2435 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2436 /* Disable generation of early preamble */ 2437 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2438 if (ret_val) 2439 return ret_val; 2440 2441 /* Preamble tuning for SSC */ 2442 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2443 if (ret_val) 2444 return ret_val; 2445 } 2446 2447 if (hw->phy.type == e1000_phy_82578) { 2448 /* Return registers to default by doing a soft reset then 2449 * writing 0x3140 to the control register. 2450 */ 2451 if (hw->phy.revision < 2) { 2452 e1000e_phy_sw_reset(hw); 2453 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2454 if (ret_val) 2455 return ret_val; 2456 } 2457 } 2458 2459 /* Select page 0 */ 2460 ret_val = hw->phy.ops.acquire(hw); 2461 if (ret_val) 2462 return ret_val; 2463 2464 hw->phy.addr = 1; 2465 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2466 hw->phy.ops.release(hw); 2467 if (ret_val) 2468 return ret_val; 2469 2470 /* Configure the K1 Si workaround during phy reset assuming there is 2471 * link so that it disables K1 if link is in 1Gbps. 2472 */ 2473 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2474 if (ret_val) 2475 return ret_val; 2476 2477 /* Workaround for link disconnects on a busy hub in half duplex */ 2478 ret_val = hw->phy.ops.acquire(hw); 2479 if (ret_val) 2480 return ret_val; 2481 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2482 if (ret_val) 2483 goto release; 2484 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2485 if (ret_val) 2486 goto release; 2487 2488 /* set MSE higher to enable link to stay up when noise is high */ 2489 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2490 release: 2491 hw->phy.ops.release(hw); 2492 2493 return ret_val; 2494 } 2495 2496 /** 2497 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2498 * @hw: pointer to the HW structure 2499 **/ 2500 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2501 { 2502 u32 mac_reg; 2503 u16 i, phy_reg = 0; 2504 s32 ret_val; 2505 2506 ret_val = hw->phy.ops.acquire(hw); 2507 if (ret_val) 2508 return; 2509 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2510 if (ret_val) 2511 goto release; 2512 2513 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2514 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2515 mac_reg = er32(RAL(i)); 2516 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2517 (u16)(mac_reg & 0xFFFF)); 2518 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2519 (u16)((mac_reg >> 16) & 0xFFFF)); 2520 2521 mac_reg = er32(RAH(i)); 2522 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2523 (u16)(mac_reg & 0xFFFF)); 2524 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2525 (u16)((mac_reg & E1000_RAH_AV) 2526 >> 16)); 2527 } 2528 2529 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2530 2531 release: 2532 hw->phy.ops.release(hw); 2533 } 2534 2535 /** 2536 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2537 * with 82579 PHY 2538 * @hw: pointer to the HW structure 2539 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2540 **/ 2541 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2542 { 2543 s32 ret_val = 0; 2544 u16 phy_reg, data; 2545 u32 mac_reg; 2546 u16 i; 2547 2548 if (hw->mac.type < e1000_pch2lan) 2549 return 0; 2550 2551 /* disable Rx path while enabling/disabling workaround */ 2552 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2553 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2554 if (ret_val) 2555 return ret_val; 2556 2557 if (enable) { 2558 /* Write Rx addresses (rar_entry_count for RAL/H, and 2559 * SHRAL/H) and initial CRC values to the MAC 2560 */ 2561 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2562 u8 mac_addr[ETH_ALEN] = { 0 }; 2563 u32 addr_high, addr_low; 2564 2565 addr_high = er32(RAH(i)); 2566 if (!(addr_high & E1000_RAH_AV)) 2567 continue; 2568 addr_low = er32(RAL(i)); 2569 mac_addr[0] = (addr_low & 0xFF); 2570 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2571 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2572 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2573 mac_addr[4] = (addr_high & 0xFF); 2574 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2575 2576 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2577 } 2578 2579 /* Write Rx addresses to the PHY */ 2580 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2581 2582 /* Enable jumbo frame workaround in the MAC */ 2583 mac_reg = er32(FFLT_DBG); 2584 mac_reg &= ~BIT(14); 2585 mac_reg |= (7 << 15); 2586 ew32(FFLT_DBG, mac_reg); 2587 2588 mac_reg = er32(RCTL); 2589 mac_reg |= E1000_RCTL_SECRC; 2590 ew32(RCTL, mac_reg); 2591 2592 ret_val = e1000e_read_kmrn_reg(hw, 2593 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2594 &data); 2595 if (ret_val) 2596 return ret_val; 2597 ret_val = e1000e_write_kmrn_reg(hw, 2598 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2599 data | BIT(0)); 2600 if (ret_val) 2601 return ret_val; 2602 ret_val = e1000e_read_kmrn_reg(hw, 2603 E1000_KMRNCTRLSTA_HD_CTRL, 2604 &data); 2605 if (ret_val) 2606 return ret_val; 2607 data &= ~(0xF << 8); 2608 data |= (0xB << 8); 2609 ret_val = e1000e_write_kmrn_reg(hw, 2610 E1000_KMRNCTRLSTA_HD_CTRL, 2611 data); 2612 if (ret_val) 2613 return ret_val; 2614 2615 /* Enable jumbo frame workaround in the PHY */ 2616 e1e_rphy(hw, PHY_REG(769, 23), &data); 2617 data &= ~(0x7F << 5); 2618 data |= (0x37 << 5); 2619 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2620 if (ret_val) 2621 return ret_val; 2622 e1e_rphy(hw, PHY_REG(769, 16), &data); 2623 data &= ~BIT(13); 2624 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2625 if (ret_val) 2626 return ret_val; 2627 e1e_rphy(hw, PHY_REG(776, 20), &data); 2628 data &= ~(0x3FF << 2); 2629 data |= (E1000_TX_PTR_GAP << 2); 2630 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2631 if (ret_val) 2632 return ret_val; 2633 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2634 if (ret_val) 2635 return ret_val; 2636 e1e_rphy(hw, HV_PM_CTRL, &data); 2637 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2638 if (ret_val) 2639 return ret_val; 2640 } else { 2641 /* Write MAC register values back to h/w defaults */ 2642 mac_reg = er32(FFLT_DBG); 2643 mac_reg &= ~(0xF << 14); 2644 ew32(FFLT_DBG, mac_reg); 2645 2646 mac_reg = er32(RCTL); 2647 mac_reg &= ~E1000_RCTL_SECRC; 2648 ew32(RCTL, mac_reg); 2649 2650 ret_val = e1000e_read_kmrn_reg(hw, 2651 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2652 &data); 2653 if (ret_val) 2654 return ret_val; 2655 ret_val = e1000e_write_kmrn_reg(hw, 2656 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2657 data & ~BIT(0)); 2658 if (ret_val) 2659 return ret_val; 2660 ret_val = e1000e_read_kmrn_reg(hw, 2661 E1000_KMRNCTRLSTA_HD_CTRL, 2662 &data); 2663 if (ret_val) 2664 return ret_val; 2665 data &= ~(0xF << 8); 2666 data |= (0xB << 8); 2667 ret_val = e1000e_write_kmrn_reg(hw, 2668 E1000_KMRNCTRLSTA_HD_CTRL, 2669 data); 2670 if (ret_val) 2671 return ret_val; 2672 2673 /* Write PHY register values back to h/w defaults */ 2674 e1e_rphy(hw, PHY_REG(769, 23), &data); 2675 data &= ~(0x7F << 5); 2676 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2677 if (ret_val) 2678 return ret_val; 2679 e1e_rphy(hw, PHY_REG(769, 16), &data); 2680 data |= BIT(13); 2681 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2682 if (ret_val) 2683 return ret_val; 2684 e1e_rphy(hw, PHY_REG(776, 20), &data); 2685 data &= ~(0x3FF << 2); 2686 data |= (0x8 << 2); 2687 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2688 if (ret_val) 2689 return ret_val; 2690 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2691 if (ret_val) 2692 return ret_val; 2693 e1e_rphy(hw, HV_PM_CTRL, &data); 2694 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2695 if (ret_val) 2696 return ret_val; 2697 } 2698 2699 /* re-enable Rx path after enabling/disabling workaround */ 2700 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2701 } 2702 2703 /** 2704 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds 2705 * @hw: pointer to the HW structure 2706 * 2707 * A series of PHY workarounds to be done after every PHY reset. 2708 **/ 2709 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2710 { 2711 s32 ret_val = 0; 2712 2713 if (hw->mac.type != e1000_pch2lan) 2714 return 0; 2715 2716 /* Set MDIO slow mode before any other MDIO access */ 2717 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2718 if (ret_val) 2719 return ret_val; 2720 2721 ret_val = hw->phy.ops.acquire(hw); 2722 if (ret_val) 2723 return ret_val; 2724 /* set MSE higher to enable link to stay up when noise is high */ 2725 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2726 if (ret_val) 2727 goto release; 2728 /* drop link after 5 times MSE threshold was reached */ 2729 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2730 release: 2731 hw->phy.ops.release(hw); 2732 2733 return ret_val; 2734 } 2735 2736 /** 2737 * e1000_k1_gig_workaround_lv - K1 Si workaround 2738 * @hw: pointer to the HW structure 2739 * 2740 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2741 * Disable K1 in 1000Mbps and 100Mbps 2742 **/ 2743 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2744 { 2745 s32 ret_val = 0; 2746 u16 status_reg = 0; 2747 2748 if (hw->mac.type != e1000_pch2lan) 2749 return 0; 2750 2751 /* Set K1 beacon duration based on 10Mbs speed */ 2752 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2753 if (ret_val) 2754 return ret_val; 2755 2756 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2757 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2758 if (status_reg & 2759 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2760 u16 pm_phy_reg; 2761 2762 /* LV 1G/100 Packet drop issue wa */ 2763 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2764 if (ret_val) 2765 return ret_val; 2766 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2767 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2768 if (ret_val) 2769 return ret_val; 2770 } else { 2771 u32 mac_reg; 2772 2773 mac_reg = er32(FEXTNVM4); 2774 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2775 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2776 ew32(FEXTNVM4, mac_reg); 2777 } 2778 } 2779 2780 return ret_val; 2781 } 2782 2783 /** 2784 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2785 * @hw: pointer to the HW structure 2786 * @gate: boolean set to true to gate, false to ungate 2787 * 2788 * Gate/ungate the automatic PHY configuration via hardware; perform 2789 * the configuration via software instead. 2790 **/ 2791 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2792 { 2793 u32 extcnf_ctrl; 2794 2795 if (hw->mac.type < e1000_pch2lan) 2796 return; 2797 2798 extcnf_ctrl = er32(EXTCNF_CTRL); 2799 2800 if (gate) 2801 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2802 else 2803 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2804 2805 ew32(EXTCNF_CTRL, extcnf_ctrl); 2806 } 2807 2808 /** 2809 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2810 * @hw: pointer to the HW structure 2811 * 2812 * Check the appropriate indication the MAC has finished configuring the 2813 * PHY after a software reset. 2814 **/ 2815 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2816 { 2817 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2818 2819 /* Wait for basic configuration completes before proceeding */ 2820 do { 2821 data = er32(STATUS); 2822 data &= E1000_STATUS_LAN_INIT_DONE; 2823 usleep_range(100, 200); 2824 } while ((!data) && --loop); 2825 2826 /* If basic configuration is incomplete before the above loop 2827 * count reaches 0, loading the configuration from NVM will 2828 * leave the PHY in a bad state possibly resulting in no link. 2829 */ 2830 if (loop == 0) 2831 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2832 2833 /* Clear the Init Done bit for the next init event */ 2834 data = er32(STATUS); 2835 data &= ~E1000_STATUS_LAN_INIT_DONE; 2836 ew32(STATUS, data); 2837 } 2838 2839 /** 2840 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2841 * @hw: pointer to the HW structure 2842 **/ 2843 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2844 { 2845 s32 ret_val = 0; 2846 u16 reg; 2847 2848 if (hw->phy.ops.check_reset_block(hw)) 2849 return 0; 2850 2851 /* Allow time for h/w to get to quiescent state after reset */ 2852 usleep_range(10000, 11000); 2853 2854 /* Perform any necessary post-reset workarounds */ 2855 switch (hw->mac.type) { 2856 case e1000_pchlan: 2857 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2858 if (ret_val) 2859 return ret_val; 2860 break; 2861 case e1000_pch2lan: 2862 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2863 if (ret_val) 2864 return ret_val; 2865 break; 2866 default: 2867 break; 2868 } 2869 2870 /* Clear the host wakeup bit after lcd reset */ 2871 if (hw->mac.type >= e1000_pchlan) { 2872 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2873 reg &= ~BM_WUC_HOST_WU_BIT; 2874 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2875 } 2876 2877 /* Configure the LCD with the extended configuration region in NVM */ 2878 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2879 if (ret_val) 2880 return ret_val; 2881 2882 /* Configure the LCD with the OEM bits in NVM */ 2883 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2884 2885 if (hw->mac.type == e1000_pch2lan) { 2886 /* Ungate automatic PHY configuration on non-managed 82579 */ 2887 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2888 usleep_range(10000, 11000); 2889 e1000_gate_hw_phy_config_ich8lan(hw, false); 2890 } 2891 2892 /* Set EEE LPI Update Timer to 200usec */ 2893 ret_val = hw->phy.ops.acquire(hw); 2894 if (ret_val) 2895 return ret_val; 2896 ret_val = e1000_write_emi_reg_locked(hw, 2897 I82579_LPI_UPDATE_TIMER, 2898 0x1387); 2899 hw->phy.ops.release(hw); 2900 } 2901 2902 return ret_val; 2903 } 2904 2905 /** 2906 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2907 * @hw: pointer to the HW structure 2908 * 2909 * Resets the PHY 2910 * This is a function pointer entry point called by drivers 2911 * or other shared routines. 2912 **/ 2913 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2914 { 2915 s32 ret_val = 0; 2916 2917 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2918 if ((hw->mac.type == e1000_pch2lan) && 2919 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2920 e1000_gate_hw_phy_config_ich8lan(hw, true); 2921 2922 ret_val = e1000e_phy_hw_reset_generic(hw); 2923 if (ret_val) 2924 return ret_val; 2925 2926 return e1000_post_phy_reset_ich8lan(hw); 2927 } 2928 2929 /** 2930 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2931 * @hw: pointer to the HW structure 2932 * @active: true to enable LPLU, false to disable 2933 * 2934 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2935 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2936 * the phy speed. This function will manually set the LPLU bit and restart 2937 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2938 * since it configures the same bit. 2939 **/ 2940 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2941 { 2942 s32 ret_val; 2943 u16 oem_reg; 2944 2945 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2946 if (ret_val) 2947 return ret_val; 2948 2949 if (active) 2950 oem_reg |= HV_OEM_BITS_LPLU; 2951 else 2952 oem_reg &= ~HV_OEM_BITS_LPLU; 2953 2954 if (!hw->phy.ops.check_reset_block(hw)) 2955 oem_reg |= HV_OEM_BITS_RESTART_AN; 2956 2957 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2958 } 2959 2960 /** 2961 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2962 * @hw: pointer to the HW structure 2963 * @active: true to enable LPLU, false to disable 2964 * 2965 * Sets the LPLU D0 state according to the active flag. When 2966 * activating LPLU this function also disables smart speed 2967 * and vice versa. LPLU will not be activated unless the 2968 * device autonegotiation advertisement meets standards of 2969 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2970 * This is a function pointer entry point only called by 2971 * PHY setup routines. 2972 **/ 2973 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2974 { 2975 struct e1000_phy_info *phy = &hw->phy; 2976 u32 phy_ctrl; 2977 s32 ret_val = 0; 2978 u16 data; 2979 2980 if (phy->type == e1000_phy_ife) 2981 return 0; 2982 2983 phy_ctrl = er32(PHY_CTRL); 2984 2985 if (active) { 2986 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2987 ew32(PHY_CTRL, phy_ctrl); 2988 2989 if (phy->type != e1000_phy_igp_3) 2990 return 0; 2991 2992 /* Call gig speed drop workaround on LPLU before accessing 2993 * any PHY registers 2994 */ 2995 if (hw->mac.type == e1000_ich8lan) 2996 e1000e_gig_downshift_workaround_ich8lan(hw); 2997 2998 /* When LPLU is enabled, we should disable SmartSpeed */ 2999 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3000 if (ret_val) 3001 return ret_val; 3002 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3003 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3004 if (ret_val) 3005 return ret_val; 3006 } else { 3007 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 3008 ew32(PHY_CTRL, phy_ctrl); 3009 3010 if (phy->type != e1000_phy_igp_3) 3011 return 0; 3012 3013 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3014 * during Dx states where the power conservation is most 3015 * important. During driver activity we should enable 3016 * SmartSpeed, so performance is maintained. 3017 */ 3018 if (phy->smart_speed == e1000_smart_speed_on) { 3019 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3020 &data); 3021 if (ret_val) 3022 return ret_val; 3023 3024 data |= IGP01E1000_PSCFR_SMART_SPEED; 3025 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3026 data); 3027 if (ret_val) 3028 return ret_val; 3029 } else if (phy->smart_speed == e1000_smart_speed_off) { 3030 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3031 &data); 3032 if (ret_val) 3033 return ret_val; 3034 3035 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3036 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3037 data); 3038 if (ret_val) 3039 return ret_val; 3040 } 3041 } 3042 3043 return 0; 3044 } 3045 3046 /** 3047 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3048 * @hw: pointer to the HW structure 3049 * @active: true to enable LPLU, false to disable 3050 * 3051 * Sets the LPLU D3 state according to the active flag. When 3052 * activating LPLU this function also disables smart speed 3053 * and vice versa. LPLU will not be activated unless the 3054 * device autonegotiation advertisement meets standards of 3055 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3056 * This is a function pointer entry point only called by 3057 * PHY setup routines. 3058 **/ 3059 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3060 { 3061 struct e1000_phy_info *phy = &hw->phy; 3062 u32 phy_ctrl; 3063 s32 ret_val = 0; 3064 u16 data; 3065 3066 phy_ctrl = er32(PHY_CTRL); 3067 3068 if (!active) { 3069 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3070 ew32(PHY_CTRL, phy_ctrl); 3071 3072 if (phy->type != e1000_phy_igp_3) 3073 return 0; 3074 3075 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3076 * during Dx states where the power conservation is most 3077 * important. During driver activity we should enable 3078 * SmartSpeed, so performance is maintained. 3079 */ 3080 if (phy->smart_speed == e1000_smart_speed_on) { 3081 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3082 &data); 3083 if (ret_val) 3084 return ret_val; 3085 3086 data |= IGP01E1000_PSCFR_SMART_SPEED; 3087 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3088 data); 3089 if (ret_val) 3090 return ret_val; 3091 } else if (phy->smart_speed == e1000_smart_speed_off) { 3092 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3093 &data); 3094 if (ret_val) 3095 return ret_val; 3096 3097 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3098 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3099 data); 3100 if (ret_val) 3101 return ret_val; 3102 } 3103 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3104 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3105 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3106 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3107 ew32(PHY_CTRL, phy_ctrl); 3108 3109 if (phy->type != e1000_phy_igp_3) 3110 return 0; 3111 3112 /* Call gig speed drop workaround on LPLU before accessing 3113 * any PHY registers 3114 */ 3115 if (hw->mac.type == e1000_ich8lan) 3116 e1000e_gig_downshift_workaround_ich8lan(hw); 3117 3118 /* When LPLU is enabled, we should disable SmartSpeed */ 3119 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3120 if (ret_val) 3121 return ret_val; 3122 3123 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3124 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3125 } 3126 3127 return ret_val; 3128 } 3129 3130 /** 3131 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3132 * @hw: pointer to the HW structure 3133 * @bank: pointer to the variable that returns the active bank 3134 * 3135 * Reads signature byte from the NVM using the flash access registers. 3136 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3137 **/ 3138 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3139 { 3140 u32 eecd; 3141 struct e1000_nvm_info *nvm = &hw->nvm; 3142 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3143 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3144 u32 nvm_dword = 0; 3145 u8 sig_byte = 0; 3146 s32 ret_val; 3147 3148 switch (hw->mac.type) { 3149 case e1000_pch_spt: 3150 case e1000_pch_cnp: 3151 case e1000_pch_tgp: 3152 case e1000_pch_adp: 3153 case e1000_pch_mtp: 3154 bank1_offset = nvm->flash_bank_size; 3155 act_offset = E1000_ICH_NVM_SIG_WORD; 3156 3157 /* set bank to 0 in case flash read fails */ 3158 *bank = 0; 3159 3160 /* Check bank 0 */ 3161 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3162 &nvm_dword); 3163 if (ret_val) 3164 return ret_val; 3165 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3166 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3167 E1000_ICH_NVM_SIG_VALUE) { 3168 *bank = 0; 3169 return 0; 3170 } 3171 3172 /* Check bank 1 */ 3173 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3174 bank1_offset, 3175 &nvm_dword); 3176 if (ret_val) 3177 return ret_val; 3178 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3179 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3180 E1000_ICH_NVM_SIG_VALUE) { 3181 *bank = 1; 3182 return 0; 3183 } 3184 3185 e_dbg("ERROR: No valid NVM bank present\n"); 3186 return -E1000_ERR_NVM; 3187 case e1000_ich8lan: 3188 case e1000_ich9lan: 3189 eecd = er32(EECD); 3190 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3191 E1000_EECD_SEC1VAL_VALID_MASK) { 3192 if (eecd & E1000_EECD_SEC1VAL) 3193 *bank = 1; 3194 else 3195 *bank = 0; 3196 3197 return 0; 3198 } 3199 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3200 fallthrough; 3201 default: 3202 /* set bank to 0 in case flash read fails */ 3203 *bank = 0; 3204 3205 /* Check bank 0 */ 3206 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3207 &sig_byte); 3208 if (ret_val) 3209 return ret_val; 3210 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3211 E1000_ICH_NVM_SIG_VALUE) { 3212 *bank = 0; 3213 return 0; 3214 } 3215 3216 /* Check bank 1 */ 3217 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3218 bank1_offset, 3219 &sig_byte); 3220 if (ret_val) 3221 return ret_val; 3222 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3223 E1000_ICH_NVM_SIG_VALUE) { 3224 *bank = 1; 3225 return 0; 3226 } 3227 3228 e_dbg("ERROR: No valid NVM bank present\n"); 3229 return -E1000_ERR_NVM; 3230 } 3231 } 3232 3233 /** 3234 * e1000_read_nvm_spt - NVM access for SPT 3235 * @hw: pointer to the HW structure 3236 * @offset: The offset (in bytes) of the word(s) to read. 3237 * @words: Size of data to read in words. 3238 * @data: pointer to the word(s) to read at offset. 3239 * 3240 * Reads a word(s) from the NVM 3241 **/ 3242 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3243 u16 *data) 3244 { 3245 struct e1000_nvm_info *nvm = &hw->nvm; 3246 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3247 u32 act_offset; 3248 s32 ret_val = 0; 3249 u32 bank = 0; 3250 u32 dword = 0; 3251 u16 offset_to_read; 3252 u16 i; 3253 3254 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3255 (words == 0)) { 3256 e_dbg("nvm parameter(s) out of bounds\n"); 3257 ret_val = -E1000_ERR_NVM; 3258 goto out; 3259 } 3260 3261 nvm->ops.acquire(hw); 3262 3263 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3264 if (ret_val) { 3265 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3266 bank = 0; 3267 } 3268 3269 act_offset = (bank) ? nvm->flash_bank_size : 0; 3270 act_offset += offset; 3271 3272 ret_val = 0; 3273 3274 for (i = 0; i < words; i += 2) { 3275 if (words - i == 1) { 3276 if (dev_spec->shadow_ram[offset + i].modified) { 3277 data[i] = 3278 dev_spec->shadow_ram[offset + i].value; 3279 } else { 3280 offset_to_read = act_offset + i - 3281 ((act_offset + i) % 2); 3282 ret_val = 3283 e1000_read_flash_dword_ich8lan(hw, 3284 offset_to_read, 3285 &dword); 3286 if (ret_val) 3287 break; 3288 if ((act_offset + i) % 2 == 0) 3289 data[i] = (u16)(dword & 0xFFFF); 3290 else 3291 data[i] = (u16)((dword >> 16) & 0xFFFF); 3292 } 3293 } else { 3294 offset_to_read = act_offset + i; 3295 if (!(dev_spec->shadow_ram[offset + i].modified) || 3296 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3297 ret_val = 3298 e1000_read_flash_dword_ich8lan(hw, 3299 offset_to_read, 3300 &dword); 3301 if (ret_val) 3302 break; 3303 } 3304 if (dev_spec->shadow_ram[offset + i].modified) 3305 data[i] = 3306 dev_spec->shadow_ram[offset + i].value; 3307 else 3308 data[i] = (u16)(dword & 0xFFFF); 3309 if (dev_spec->shadow_ram[offset + i].modified) 3310 data[i + 1] = 3311 dev_spec->shadow_ram[offset + i + 1].value; 3312 else 3313 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3314 } 3315 } 3316 3317 nvm->ops.release(hw); 3318 3319 out: 3320 if (ret_val) 3321 e_dbg("NVM read error: %d\n", ret_val); 3322 3323 return ret_val; 3324 } 3325 3326 /** 3327 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3328 * @hw: pointer to the HW structure 3329 * @offset: The offset (in bytes) of the word(s) to read. 3330 * @words: Size of data to read in words 3331 * @data: Pointer to the word(s) to read at offset. 3332 * 3333 * Reads a word(s) from the NVM using the flash access registers. 3334 **/ 3335 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3336 u16 *data) 3337 { 3338 struct e1000_nvm_info *nvm = &hw->nvm; 3339 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3340 u32 act_offset; 3341 s32 ret_val = 0; 3342 u32 bank = 0; 3343 u16 i, word; 3344 3345 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3346 (words == 0)) { 3347 e_dbg("nvm parameter(s) out of bounds\n"); 3348 ret_val = -E1000_ERR_NVM; 3349 goto out; 3350 } 3351 3352 nvm->ops.acquire(hw); 3353 3354 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3355 if (ret_val) { 3356 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3357 bank = 0; 3358 } 3359 3360 act_offset = (bank) ? nvm->flash_bank_size : 0; 3361 act_offset += offset; 3362 3363 ret_val = 0; 3364 for (i = 0; i < words; i++) { 3365 if (dev_spec->shadow_ram[offset + i].modified) { 3366 data[i] = dev_spec->shadow_ram[offset + i].value; 3367 } else { 3368 ret_val = e1000_read_flash_word_ich8lan(hw, 3369 act_offset + i, 3370 &word); 3371 if (ret_val) 3372 break; 3373 data[i] = word; 3374 } 3375 } 3376 3377 nvm->ops.release(hw); 3378 3379 out: 3380 if (ret_val) 3381 e_dbg("NVM read error: %d\n", ret_val); 3382 3383 return ret_val; 3384 } 3385 3386 /** 3387 * e1000_flash_cycle_init_ich8lan - Initialize flash 3388 * @hw: pointer to the HW structure 3389 * 3390 * This function does initial flash setup so that a new read/write/erase cycle 3391 * can be started. 3392 **/ 3393 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3394 { 3395 union ich8_hws_flash_status hsfsts; 3396 s32 ret_val = -E1000_ERR_NVM; 3397 3398 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3399 3400 /* Check if the flash descriptor is valid */ 3401 if (!hsfsts.hsf_status.fldesvalid) { 3402 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3403 return -E1000_ERR_NVM; 3404 } 3405 3406 /* Clear FCERR and DAEL in hw status by writing 1 */ 3407 hsfsts.hsf_status.flcerr = 1; 3408 hsfsts.hsf_status.dael = 1; 3409 if (hw->mac.type >= e1000_pch_spt) 3410 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3411 else 3412 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3413 3414 /* Either we should have a hardware SPI cycle in progress 3415 * bit to check against, in order to start a new cycle or 3416 * FDONE bit should be changed in the hardware so that it 3417 * is 1 after hardware reset, which can then be used as an 3418 * indication whether a cycle is in progress or has been 3419 * completed. 3420 */ 3421 3422 if (!hsfsts.hsf_status.flcinprog) { 3423 /* There is no cycle running at present, 3424 * so we can start a cycle. 3425 * Begin by setting Flash Cycle Done. 3426 */ 3427 hsfsts.hsf_status.flcdone = 1; 3428 if (hw->mac.type >= e1000_pch_spt) 3429 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3430 else 3431 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3432 ret_val = 0; 3433 } else { 3434 s32 i; 3435 3436 /* Otherwise poll for sometime so the current 3437 * cycle has a chance to end before giving up. 3438 */ 3439 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3440 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3441 if (!hsfsts.hsf_status.flcinprog) { 3442 ret_val = 0; 3443 break; 3444 } 3445 udelay(1); 3446 } 3447 if (!ret_val) { 3448 /* Successful in waiting for previous cycle to timeout, 3449 * now set the Flash Cycle Done. 3450 */ 3451 hsfsts.hsf_status.flcdone = 1; 3452 if (hw->mac.type >= e1000_pch_spt) 3453 ew32flash(ICH_FLASH_HSFSTS, 3454 hsfsts.regval & 0xFFFF); 3455 else 3456 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3457 } else { 3458 e_dbg("Flash controller busy, cannot get access\n"); 3459 } 3460 } 3461 3462 return ret_val; 3463 } 3464 3465 /** 3466 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3467 * @hw: pointer to the HW structure 3468 * @timeout: maximum time to wait for completion 3469 * 3470 * This function starts a flash cycle and waits for its completion. 3471 **/ 3472 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3473 { 3474 union ich8_hws_flash_ctrl hsflctl; 3475 union ich8_hws_flash_status hsfsts; 3476 u32 i = 0; 3477 3478 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3479 if (hw->mac.type >= e1000_pch_spt) 3480 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3481 else 3482 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3483 hsflctl.hsf_ctrl.flcgo = 1; 3484 3485 if (hw->mac.type >= e1000_pch_spt) 3486 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3487 else 3488 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3489 3490 /* wait till FDONE bit is set to 1 */ 3491 do { 3492 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3493 if (hsfsts.hsf_status.flcdone) 3494 break; 3495 udelay(1); 3496 } while (i++ < timeout); 3497 3498 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3499 return 0; 3500 3501 return -E1000_ERR_NVM; 3502 } 3503 3504 /** 3505 * e1000_read_flash_dword_ich8lan - Read dword from flash 3506 * @hw: pointer to the HW structure 3507 * @offset: offset to data location 3508 * @data: pointer to the location for storing the data 3509 * 3510 * Reads the flash dword at offset into data. Offset is converted 3511 * to bytes before read. 3512 **/ 3513 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3514 u32 *data) 3515 { 3516 /* Must convert word offset into bytes. */ 3517 offset <<= 1; 3518 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3519 } 3520 3521 /** 3522 * e1000_read_flash_word_ich8lan - Read word from flash 3523 * @hw: pointer to the HW structure 3524 * @offset: offset to data location 3525 * @data: pointer to the location for storing the data 3526 * 3527 * Reads the flash word at offset into data. Offset is converted 3528 * to bytes before read. 3529 **/ 3530 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3531 u16 *data) 3532 { 3533 /* Must convert offset into bytes. */ 3534 offset <<= 1; 3535 3536 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3537 } 3538 3539 /** 3540 * e1000_read_flash_byte_ich8lan - Read byte from flash 3541 * @hw: pointer to the HW structure 3542 * @offset: The offset of the byte to read. 3543 * @data: Pointer to a byte to store the value read. 3544 * 3545 * Reads a single byte from the NVM using the flash access registers. 3546 **/ 3547 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3548 u8 *data) 3549 { 3550 s32 ret_val; 3551 u16 word = 0; 3552 3553 /* In SPT, only 32 bits access is supported, 3554 * so this function should not be called. 3555 */ 3556 if (hw->mac.type >= e1000_pch_spt) 3557 return -E1000_ERR_NVM; 3558 else 3559 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3560 3561 if (ret_val) 3562 return ret_val; 3563 3564 *data = (u8)word; 3565 3566 return 0; 3567 } 3568 3569 /** 3570 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3571 * @hw: pointer to the HW structure 3572 * @offset: The offset (in bytes) of the byte or word to read. 3573 * @size: Size of data to read, 1=byte 2=word 3574 * @data: Pointer to the word to store the value read. 3575 * 3576 * Reads a byte or word from the NVM using the flash access registers. 3577 **/ 3578 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3579 u8 size, u16 *data) 3580 { 3581 union ich8_hws_flash_status hsfsts; 3582 union ich8_hws_flash_ctrl hsflctl; 3583 u32 flash_linear_addr; 3584 u32 flash_data = 0; 3585 s32 ret_val = -E1000_ERR_NVM; 3586 u8 count = 0; 3587 3588 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3589 return -E1000_ERR_NVM; 3590 3591 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3592 hw->nvm.flash_base_addr); 3593 3594 do { 3595 udelay(1); 3596 /* Steps */ 3597 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3598 if (ret_val) 3599 break; 3600 3601 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3602 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3603 hsflctl.hsf_ctrl.fldbcount = size - 1; 3604 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3605 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3606 3607 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3608 3609 ret_val = 3610 e1000_flash_cycle_ich8lan(hw, 3611 ICH_FLASH_READ_COMMAND_TIMEOUT); 3612 3613 /* Check if FCERR is set to 1, if set to 1, clear it 3614 * and try the whole sequence a few more times, else 3615 * read in (shift in) the Flash Data0, the order is 3616 * least significant byte first msb to lsb 3617 */ 3618 if (!ret_val) { 3619 flash_data = er32flash(ICH_FLASH_FDATA0); 3620 if (size == 1) 3621 *data = (u8)(flash_data & 0x000000FF); 3622 else if (size == 2) 3623 *data = (u16)(flash_data & 0x0000FFFF); 3624 break; 3625 } else { 3626 /* If we've gotten here, then things are probably 3627 * completely hosed, but if the error condition is 3628 * detected, it won't hurt to give it another try... 3629 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3630 */ 3631 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3632 if (hsfsts.hsf_status.flcerr) { 3633 /* Repeat for some time before giving up. */ 3634 continue; 3635 } else if (!hsfsts.hsf_status.flcdone) { 3636 e_dbg("Timeout error - flash cycle did not complete.\n"); 3637 break; 3638 } 3639 } 3640 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3641 3642 return ret_val; 3643 } 3644 3645 /** 3646 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3647 * @hw: pointer to the HW structure 3648 * @offset: The offset (in bytes) of the dword to read. 3649 * @data: Pointer to the dword to store the value read. 3650 * 3651 * Reads a byte or word from the NVM using the flash access registers. 3652 **/ 3653 3654 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3655 u32 *data) 3656 { 3657 union ich8_hws_flash_status hsfsts; 3658 union ich8_hws_flash_ctrl hsflctl; 3659 u32 flash_linear_addr; 3660 s32 ret_val = -E1000_ERR_NVM; 3661 u8 count = 0; 3662 3663 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3664 return -E1000_ERR_NVM; 3665 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3666 hw->nvm.flash_base_addr); 3667 3668 do { 3669 udelay(1); 3670 /* Steps */ 3671 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3672 if (ret_val) 3673 break; 3674 /* In SPT, This register is in Lan memory space, not flash. 3675 * Therefore, only 32 bit access is supported 3676 */ 3677 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3678 3679 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3680 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3681 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3682 /* In SPT, This register is in Lan memory space, not flash. 3683 * Therefore, only 32 bit access is supported 3684 */ 3685 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3686 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3687 3688 ret_val = 3689 e1000_flash_cycle_ich8lan(hw, 3690 ICH_FLASH_READ_COMMAND_TIMEOUT); 3691 3692 /* Check if FCERR is set to 1, if set to 1, clear it 3693 * and try the whole sequence a few more times, else 3694 * read in (shift in) the Flash Data0, the order is 3695 * least significant byte first msb to lsb 3696 */ 3697 if (!ret_val) { 3698 *data = er32flash(ICH_FLASH_FDATA0); 3699 break; 3700 } else { 3701 /* If we've gotten here, then things are probably 3702 * completely hosed, but if the error condition is 3703 * detected, it won't hurt to give it another try... 3704 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3705 */ 3706 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3707 if (hsfsts.hsf_status.flcerr) { 3708 /* Repeat for some time before giving up. */ 3709 continue; 3710 } else if (!hsfsts.hsf_status.flcdone) { 3711 e_dbg("Timeout error - flash cycle did not complete.\n"); 3712 break; 3713 } 3714 } 3715 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3716 3717 return ret_val; 3718 } 3719 3720 /** 3721 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3722 * @hw: pointer to the HW structure 3723 * @offset: The offset (in bytes) of the word(s) to write. 3724 * @words: Size of data to write in words 3725 * @data: Pointer to the word(s) to write at offset. 3726 * 3727 * Writes a byte or word to the NVM using the flash access registers. 3728 **/ 3729 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3730 u16 *data) 3731 { 3732 struct e1000_nvm_info *nvm = &hw->nvm; 3733 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3734 u16 i; 3735 3736 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3737 (words == 0)) { 3738 e_dbg("nvm parameter(s) out of bounds\n"); 3739 return -E1000_ERR_NVM; 3740 } 3741 3742 nvm->ops.acquire(hw); 3743 3744 for (i = 0; i < words; i++) { 3745 dev_spec->shadow_ram[offset + i].modified = true; 3746 dev_spec->shadow_ram[offset + i].value = data[i]; 3747 } 3748 3749 nvm->ops.release(hw); 3750 3751 return 0; 3752 } 3753 3754 /** 3755 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3756 * @hw: pointer to the HW structure 3757 * 3758 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3759 * which writes the checksum to the shadow ram. The changes in the shadow 3760 * ram are then committed to the EEPROM by processing each bank at a time 3761 * checking for the modified bit and writing only the pending changes. 3762 * After a successful commit, the shadow ram is cleared and is ready for 3763 * future writes. 3764 **/ 3765 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3766 { 3767 struct e1000_nvm_info *nvm = &hw->nvm; 3768 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3769 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3770 s32 ret_val; 3771 u32 dword = 0; 3772 3773 ret_val = e1000e_update_nvm_checksum_generic(hw); 3774 if (ret_val) 3775 goto out; 3776 3777 if (nvm->type != e1000_nvm_flash_sw) 3778 goto out; 3779 3780 nvm->ops.acquire(hw); 3781 3782 /* We're writing to the opposite bank so if we're on bank 1, 3783 * write to bank 0 etc. We also need to erase the segment that 3784 * is going to be written 3785 */ 3786 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3787 if (ret_val) { 3788 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3789 bank = 0; 3790 } 3791 3792 if (bank == 0) { 3793 new_bank_offset = nvm->flash_bank_size; 3794 old_bank_offset = 0; 3795 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3796 if (ret_val) 3797 goto release; 3798 } else { 3799 old_bank_offset = nvm->flash_bank_size; 3800 new_bank_offset = 0; 3801 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3802 if (ret_val) 3803 goto release; 3804 } 3805 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3806 /* Determine whether to write the value stored 3807 * in the other NVM bank or a modified value stored 3808 * in the shadow RAM 3809 */ 3810 ret_val = e1000_read_flash_dword_ich8lan(hw, 3811 i + old_bank_offset, 3812 &dword); 3813 3814 if (dev_spec->shadow_ram[i].modified) { 3815 dword &= 0xffff0000; 3816 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3817 } 3818 if (dev_spec->shadow_ram[i + 1].modified) { 3819 dword &= 0x0000ffff; 3820 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3821 << 16); 3822 } 3823 if (ret_val) 3824 break; 3825 3826 /* If the word is 0x13, then make sure the signature bits 3827 * (15:14) are 11b until the commit has completed. 3828 * This will allow us to write 10b which indicates the 3829 * signature is valid. We want to do this after the write 3830 * has completed so that we don't mark the segment valid 3831 * while the write is still in progress 3832 */ 3833 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3834 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3835 3836 /* Convert offset to bytes. */ 3837 act_offset = (i + new_bank_offset) << 1; 3838 3839 usleep_range(100, 200); 3840 3841 /* Write the data to the new bank. Offset in words */ 3842 act_offset = i + new_bank_offset; 3843 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3844 dword); 3845 if (ret_val) 3846 break; 3847 } 3848 3849 /* Don't bother writing the segment valid bits if sector 3850 * programming failed. 3851 */ 3852 if (ret_val) { 3853 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3854 e_dbg("Flash commit failed.\n"); 3855 goto release; 3856 } 3857 3858 /* Finally validate the new segment by setting bit 15:14 3859 * to 10b in word 0x13 , this can be done without an 3860 * erase as well since these bits are 11 to start with 3861 * and we need to change bit 14 to 0b 3862 */ 3863 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3864 3865 /*offset in words but we read dword */ 3866 --act_offset; 3867 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3868 3869 if (ret_val) 3870 goto release; 3871 3872 dword &= 0xBFFFFFFF; 3873 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3874 3875 if (ret_val) 3876 goto release; 3877 3878 /* And invalidate the previously valid segment by setting 3879 * its signature word (0x13) high_byte to 0b. This can be 3880 * done without an erase because flash erase sets all bits 3881 * to 1's. We can write 1's to 0's without an erase 3882 */ 3883 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3884 3885 /* offset in words but we read dword */ 3886 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3887 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3888 3889 if (ret_val) 3890 goto release; 3891 3892 dword &= 0x00FFFFFF; 3893 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3894 3895 if (ret_val) 3896 goto release; 3897 3898 /* Great! Everything worked, we can now clear the cached entries. */ 3899 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3900 dev_spec->shadow_ram[i].modified = false; 3901 dev_spec->shadow_ram[i].value = 0xFFFF; 3902 } 3903 3904 release: 3905 nvm->ops.release(hw); 3906 3907 /* Reload the EEPROM, or else modifications will not appear 3908 * until after the next adapter reset. 3909 */ 3910 if (!ret_val) { 3911 nvm->ops.reload(hw); 3912 usleep_range(10000, 11000); 3913 } 3914 3915 out: 3916 if (ret_val) 3917 e_dbg("NVM update error: %d\n", ret_val); 3918 3919 return ret_val; 3920 } 3921 3922 /** 3923 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3924 * @hw: pointer to the HW structure 3925 * 3926 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3927 * which writes the checksum to the shadow ram. The changes in the shadow 3928 * ram are then committed to the EEPROM by processing each bank at a time 3929 * checking for the modified bit and writing only the pending changes. 3930 * After a successful commit, the shadow ram is cleared and is ready for 3931 * future writes. 3932 **/ 3933 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3934 { 3935 struct e1000_nvm_info *nvm = &hw->nvm; 3936 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3937 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3938 s32 ret_val; 3939 u16 data = 0; 3940 3941 ret_val = e1000e_update_nvm_checksum_generic(hw); 3942 if (ret_val) 3943 goto out; 3944 3945 if (nvm->type != e1000_nvm_flash_sw) 3946 goto out; 3947 3948 nvm->ops.acquire(hw); 3949 3950 /* We're writing to the opposite bank so if we're on bank 1, 3951 * write to bank 0 etc. We also need to erase the segment that 3952 * is going to be written 3953 */ 3954 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3955 if (ret_val) { 3956 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3957 bank = 0; 3958 } 3959 3960 if (bank == 0) { 3961 new_bank_offset = nvm->flash_bank_size; 3962 old_bank_offset = 0; 3963 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3964 if (ret_val) 3965 goto release; 3966 } else { 3967 old_bank_offset = nvm->flash_bank_size; 3968 new_bank_offset = 0; 3969 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3970 if (ret_val) 3971 goto release; 3972 } 3973 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3974 if (dev_spec->shadow_ram[i].modified) { 3975 data = dev_spec->shadow_ram[i].value; 3976 } else { 3977 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3978 old_bank_offset, 3979 &data); 3980 if (ret_val) 3981 break; 3982 } 3983 3984 /* If the word is 0x13, then make sure the signature bits 3985 * (15:14) are 11b until the commit has completed. 3986 * This will allow us to write 10b which indicates the 3987 * signature is valid. We want to do this after the write 3988 * has completed so that we don't mark the segment valid 3989 * while the write is still in progress 3990 */ 3991 if (i == E1000_ICH_NVM_SIG_WORD) 3992 data |= E1000_ICH_NVM_SIG_MASK; 3993 3994 /* Convert offset to bytes. */ 3995 act_offset = (i + new_bank_offset) << 1; 3996 3997 usleep_range(100, 200); 3998 /* Write the bytes to the new bank. */ 3999 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4000 act_offset, 4001 (u8)data); 4002 if (ret_val) 4003 break; 4004 4005 usleep_range(100, 200); 4006 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4007 act_offset + 1, 4008 (u8)(data >> 8)); 4009 if (ret_val) 4010 break; 4011 } 4012 4013 /* Don't bother writing the segment valid bits if sector 4014 * programming failed. 4015 */ 4016 if (ret_val) { 4017 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4018 e_dbg("Flash commit failed.\n"); 4019 goto release; 4020 } 4021 4022 /* Finally validate the new segment by setting bit 15:14 4023 * to 10b in word 0x13 , this can be done without an 4024 * erase as well since these bits are 11 to start with 4025 * and we need to change bit 14 to 0b 4026 */ 4027 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4028 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4029 if (ret_val) 4030 goto release; 4031 4032 data &= 0xBFFF; 4033 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4034 act_offset * 2 + 1, 4035 (u8)(data >> 8)); 4036 if (ret_val) 4037 goto release; 4038 4039 /* And invalidate the previously valid segment by setting 4040 * its signature word (0x13) high_byte to 0b. This can be 4041 * done without an erase because flash erase sets all bits 4042 * to 1's. We can write 1's to 0's without an erase 4043 */ 4044 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4045 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4046 if (ret_val) 4047 goto release; 4048 4049 /* Great! Everything worked, we can now clear the cached entries. */ 4050 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4051 dev_spec->shadow_ram[i].modified = false; 4052 dev_spec->shadow_ram[i].value = 0xFFFF; 4053 } 4054 4055 release: 4056 nvm->ops.release(hw); 4057 4058 /* Reload the EEPROM, or else modifications will not appear 4059 * until after the next adapter reset. 4060 */ 4061 if (!ret_val) { 4062 nvm->ops.reload(hw); 4063 usleep_range(10000, 11000); 4064 } 4065 4066 out: 4067 if (ret_val) 4068 e_dbg("NVM update error: %d\n", ret_val); 4069 4070 return ret_val; 4071 } 4072 4073 /** 4074 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4075 * @hw: pointer to the HW structure 4076 * 4077 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4078 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4079 * calculated, in which case we need to calculate the checksum and set bit 6. 4080 **/ 4081 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4082 { 4083 s32 ret_val; 4084 u16 data; 4085 u16 word; 4086 u16 valid_csum_mask; 4087 4088 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4089 * the checksum needs to be fixed. This bit is an indication that 4090 * the NVM was prepared by OEM software and did not calculate 4091 * the checksum...a likely scenario. 4092 */ 4093 switch (hw->mac.type) { 4094 case e1000_pch_lpt: 4095 case e1000_pch_spt: 4096 case e1000_pch_cnp: 4097 case e1000_pch_tgp: 4098 case e1000_pch_adp: 4099 case e1000_pch_mtp: 4100 word = NVM_COMPAT; 4101 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4102 break; 4103 default: 4104 word = NVM_FUTURE_INIT_WORD1; 4105 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4106 break; 4107 } 4108 4109 ret_val = e1000_read_nvm(hw, word, 1, &data); 4110 if (ret_val) 4111 return ret_val; 4112 4113 if (!(data & valid_csum_mask)) { 4114 data |= valid_csum_mask; 4115 ret_val = e1000_write_nvm(hw, word, 1, &data); 4116 if (ret_val) 4117 return ret_val; 4118 ret_val = e1000e_update_nvm_checksum(hw); 4119 if (ret_val) 4120 return ret_val; 4121 } 4122 4123 return e1000e_validate_nvm_checksum_generic(hw); 4124 } 4125 4126 /** 4127 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4128 * @hw: pointer to the HW structure 4129 * 4130 * To prevent malicious write/erase of the NVM, set it to be read-only 4131 * so that the hardware ignores all write/erase cycles of the NVM via 4132 * the flash control registers. The shadow-ram copy of the NVM will 4133 * still be updated, however any updates to this copy will not stick 4134 * across driver reloads. 4135 **/ 4136 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4137 { 4138 struct e1000_nvm_info *nvm = &hw->nvm; 4139 union ich8_flash_protected_range pr0; 4140 union ich8_hws_flash_status hsfsts; 4141 u32 gfpreg; 4142 4143 nvm->ops.acquire(hw); 4144 4145 gfpreg = er32flash(ICH_FLASH_GFPREG); 4146 4147 /* Write-protect GbE Sector of NVM */ 4148 pr0.regval = er32flash(ICH_FLASH_PR0); 4149 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4150 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4151 pr0.range.wpe = true; 4152 ew32flash(ICH_FLASH_PR0, pr0.regval); 4153 4154 /* Lock down a subset of GbE Flash Control Registers, e.g. 4155 * PR0 to prevent the write-protection from being lifted. 4156 * Once FLOCKDN is set, the registers protected by it cannot 4157 * be written until FLOCKDN is cleared by a hardware reset. 4158 */ 4159 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4160 hsfsts.hsf_status.flockdn = true; 4161 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4162 4163 nvm->ops.release(hw); 4164 } 4165 4166 /** 4167 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4168 * @hw: pointer to the HW structure 4169 * @offset: The offset (in bytes) of the byte/word to read. 4170 * @size: Size of data to read, 1=byte 2=word 4171 * @data: The byte(s) to write to the NVM. 4172 * 4173 * Writes one/two bytes to the NVM using the flash access registers. 4174 **/ 4175 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4176 u8 size, u16 data) 4177 { 4178 union ich8_hws_flash_status hsfsts; 4179 union ich8_hws_flash_ctrl hsflctl; 4180 u32 flash_linear_addr; 4181 u32 flash_data = 0; 4182 s32 ret_val; 4183 u8 count = 0; 4184 4185 if (hw->mac.type >= e1000_pch_spt) { 4186 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4187 return -E1000_ERR_NVM; 4188 } else { 4189 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4190 return -E1000_ERR_NVM; 4191 } 4192 4193 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4194 hw->nvm.flash_base_addr); 4195 4196 do { 4197 udelay(1); 4198 /* Steps */ 4199 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4200 if (ret_val) 4201 break; 4202 /* In SPT, This register is in Lan memory space, not 4203 * flash. Therefore, only 32 bit access is supported 4204 */ 4205 if (hw->mac.type >= e1000_pch_spt) 4206 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4207 else 4208 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4209 4210 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4211 hsflctl.hsf_ctrl.fldbcount = size - 1; 4212 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4213 /* In SPT, This register is in Lan memory space, 4214 * not flash. Therefore, only 32 bit access is 4215 * supported 4216 */ 4217 if (hw->mac.type >= e1000_pch_spt) 4218 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4219 else 4220 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4221 4222 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4223 4224 if (size == 1) 4225 flash_data = (u32)data & 0x00FF; 4226 else 4227 flash_data = (u32)data; 4228 4229 ew32flash(ICH_FLASH_FDATA0, flash_data); 4230 4231 /* check if FCERR is set to 1 , if set to 1, clear it 4232 * and try the whole sequence a few more times else done 4233 */ 4234 ret_val = 4235 e1000_flash_cycle_ich8lan(hw, 4236 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4237 if (!ret_val) 4238 break; 4239 4240 /* If we're here, then things are most likely 4241 * completely hosed, but if the error condition 4242 * is detected, it won't hurt to give it another 4243 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4244 */ 4245 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4246 if (hsfsts.hsf_status.flcerr) 4247 /* Repeat for some time before giving up. */ 4248 continue; 4249 if (!hsfsts.hsf_status.flcdone) { 4250 e_dbg("Timeout error - flash cycle did not complete.\n"); 4251 break; 4252 } 4253 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4254 4255 return ret_val; 4256 } 4257 4258 /** 4259 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4260 * @hw: pointer to the HW structure 4261 * @offset: The offset (in bytes) of the dwords to read. 4262 * @data: The 4 bytes to write to the NVM. 4263 * 4264 * Writes one/two/four bytes to the NVM using the flash access registers. 4265 **/ 4266 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4267 u32 data) 4268 { 4269 union ich8_hws_flash_status hsfsts; 4270 union ich8_hws_flash_ctrl hsflctl; 4271 u32 flash_linear_addr; 4272 s32 ret_val; 4273 u8 count = 0; 4274 4275 if (hw->mac.type >= e1000_pch_spt) { 4276 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4277 return -E1000_ERR_NVM; 4278 } 4279 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4280 hw->nvm.flash_base_addr); 4281 do { 4282 udelay(1); 4283 /* Steps */ 4284 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4285 if (ret_val) 4286 break; 4287 4288 /* In SPT, This register is in Lan memory space, not 4289 * flash. Therefore, only 32 bit access is supported 4290 */ 4291 if (hw->mac.type >= e1000_pch_spt) 4292 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4293 >> 16; 4294 else 4295 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4296 4297 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4298 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4299 4300 /* In SPT, This register is in Lan memory space, 4301 * not flash. Therefore, only 32 bit access is 4302 * supported 4303 */ 4304 if (hw->mac.type >= e1000_pch_spt) 4305 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4306 else 4307 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4308 4309 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4310 4311 ew32flash(ICH_FLASH_FDATA0, data); 4312 4313 /* check if FCERR is set to 1 , if set to 1, clear it 4314 * and try the whole sequence a few more times else done 4315 */ 4316 ret_val = 4317 e1000_flash_cycle_ich8lan(hw, 4318 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4319 4320 if (!ret_val) 4321 break; 4322 4323 /* If we're here, then things are most likely 4324 * completely hosed, but if the error condition 4325 * is detected, it won't hurt to give it another 4326 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4327 */ 4328 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4329 4330 if (hsfsts.hsf_status.flcerr) 4331 /* Repeat for some time before giving up. */ 4332 continue; 4333 if (!hsfsts.hsf_status.flcdone) { 4334 e_dbg("Timeout error - flash cycle did not complete.\n"); 4335 break; 4336 } 4337 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4338 4339 return ret_val; 4340 } 4341 4342 /** 4343 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4344 * @hw: pointer to the HW structure 4345 * @offset: The index of the byte to read. 4346 * @data: The byte to write to the NVM. 4347 * 4348 * Writes a single byte to the NVM using the flash access registers. 4349 **/ 4350 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4351 u8 data) 4352 { 4353 u16 word = (u16)data; 4354 4355 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4356 } 4357 4358 /** 4359 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4360 * @hw: pointer to the HW structure 4361 * @offset: The offset of the word to write. 4362 * @dword: The dword to write to the NVM. 4363 * 4364 * Writes a single dword to the NVM using the flash access registers. 4365 * Goes through a retry algorithm before giving up. 4366 **/ 4367 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4368 u32 offset, u32 dword) 4369 { 4370 s32 ret_val; 4371 u16 program_retries; 4372 4373 /* Must convert word offset into bytes. */ 4374 offset <<= 1; 4375 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4376 4377 if (!ret_val) 4378 return ret_val; 4379 for (program_retries = 0; program_retries < 100; program_retries++) { 4380 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4381 usleep_range(100, 200); 4382 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4383 if (!ret_val) 4384 break; 4385 } 4386 if (program_retries == 100) 4387 return -E1000_ERR_NVM; 4388 4389 return 0; 4390 } 4391 4392 /** 4393 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4394 * @hw: pointer to the HW structure 4395 * @offset: The offset of the byte to write. 4396 * @byte: The byte to write to the NVM. 4397 * 4398 * Writes a single byte to the NVM using the flash access registers. 4399 * Goes through a retry algorithm before giving up. 4400 **/ 4401 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4402 u32 offset, u8 byte) 4403 { 4404 s32 ret_val; 4405 u16 program_retries; 4406 4407 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4408 if (!ret_val) 4409 return ret_val; 4410 4411 for (program_retries = 0; program_retries < 100; program_retries++) { 4412 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4413 usleep_range(100, 200); 4414 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4415 if (!ret_val) 4416 break; 4417 } 4418 if (program_retries == 100) 4419 return -E1000_ERR_NVM; 4420 4421 return 0; 4422 } 4423 4424 /** 4425 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4426 * @hw: pointer to the HW structure 4427 * @bank: 0 for first bank, 1 for second bank, etc. 4428 * 4429 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4430 * bank N is 4096 * N + flash_reg_addr. 4431 **/ 4432 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4433 { 4434 struct e1000_nvm_info *nvm = &hw->nvm; 4435 union ich8_hws_flash_status hsfsts; 4436 union ich8_hws_flash_ctrl hsflctl; 4437 u32 flash_linear_addr; 4438 /* bank size is in 16bit words - adjust to bytes */ 4439 u32 flash_bank_size = nvm->flash_bank_size * 2; 4440 s32 ret_val; 4441 s32 count = 0; 4442 s32 j, iteration, sector_size; 4443 4444 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4445 4446 /* Determine HW Sector size: Read BERASE bits of hw flash status 4447 * register 4448 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4449 * consecutive sectors. The start index for the nth Hw sector 4450 * can be calculated as = bank * 4096 + n * 256 4451 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4452 * The start index for the nth Hw sector can be calculated 4453 * as = bank * 4096 4454 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4455 * (ich9 only, otherwise error condition) 4456 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4457 */ 4458 switch (hsfsts.hsf_status.berasesz) { 4459 case 0: 4460 /* Hw sector size 256 */ 4461 sector_size = ICH_FLASH_SEG_SIZE_256; 4462 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4463 break; 4464 case 1: 4465 sector_size = ICH_FLASH_SEG_SIZE_4K; 4466 iteration = 1; 4467 break; 4468 case 2: 4469 sector_size = ICH_FLASH_SEG_SIZE_8K; 4470 iteration = 1; 4471 break; 4472 case 3: 4473 sector_size = ICH_FLASH_SEG_SIZE_64K; 4474 iteration = 1; 4475 break; 4476 default: 4477 return -E1000_ERR_NVM; 4478 } 4479 4480 /* Start with the base address, then add the sector offset. */ 4481 flash_linear_addr = hw->nvm.flash_base_addr; 4482 flash_linear_addr += (bank) ? flash_bank_size : 0; 4483 4484 for (j = 0; j < iteration; j++) { 4485 do { 4486 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4487 4488 /* Steps */ 4489 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4490 if (ret_val) 4491 return ret_val; 4492 4493 /* Write a value 11 (block Erase) in Flash 4494 * Cycle field in hw flash control 4495 */ 4496 if (hw->mac.type >= e1000_pch_spt) 4497 hsflctl.regval = 4498 er32flash(ICH_FLASH_HSFSTS) >> 16; 4499 else 4500 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4501 4502 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4503 if (hw->mac.type >= e1000_pch_spt) 4504 ew32flash(ICH_FLASH_HSFSTS, 4505 hsflctl.regval << 16); 4506 else 4507 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4508 4509 /* Write the last 24 bits of an index within the 4510 * block into Flash Linear address field in Flash 4511 * Address. 4512 */ 4513 flash_linear_addr += (j * sector_size); 4514 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4515 4516 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4517 if (!ret_val) 4518 break; 4519 4520 /* Check if FCERR is set to 1. If 1, 4521 * clear it and try the whole sequence 4522 * a few more times else Done 4523 */ 4524 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4525 if (hsfsts.hsf_status.flcerr) 4526 /* repeat for some time before giving up */ 4527 continue; 4528 else if (!hsfsts.hsf_status.flcdone) 4529 return ret_val; 4530 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4531 } 4532 4533 return 0; 4534 } 4535 4536 /** 4537 * e1000_valid_led_default_ich8lan - Set the default LED settings 4538 * @hw: pointer to the HW structure 4539 * @data: Pointer to the LED settings 4540 * 4541 * Reads the LED default settings from the NVM to data. If the NVM LED 4542 * settings is all 0's or F's, set the LED default to a valid LED default 4543 * setting. 4544 **/ 4545 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4546 { 4547 s32 ret_val; 4548 4549 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4550 if (ret_val) { 4551 e_dbg("NVM Read Error\n"); 4552 return ret_val; 4553 } 4554 4555 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4556 *data = ID_LED_DEFAULT_ICH8LAN; 4557 4558 return 0; 4559 } 4560 4561 /** 4562 * e1000_id_led_init_pchlan - store LED configurations 4563 * @hw: pointer to the HW structure 4564 * 4565 * PCH does not control LEDs via the LEDCTL register, rather it uses 4566 * the PHY LED configuration register. 4567 * 4568 * PCH also does not have an "always on" or "always off" mode which 4569 * complicates the ID feature. Instead of using the "on" mode to indicate 4570 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4571 * use "link_up" mode. The LEDs will still ID on request if there is no 4572 * link based on logic in e1000_led_[on|off]_pchlan(). 4573 **/ 4574 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4575 { 4576 struct e1000_mac_info *mac = &hw->mac; 4577 s32 ret_val; 4578 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4579 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4580 u16 data, i, temp, shift; 4581 4582 /* Get default ID LED modes */ 4583 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4584 if (ret_val) 4585 return ret_val; 4586 4587 mac->ledctl_default = er32(LEDCTL); 4588 mac->ledctl_mode1 = mac->ledctl_default; 4589 mac->ledctl_mode2 = mac->ledctl_default; 4590 4591 for (i = 0; i < 4; i++) { 4592 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4593 shift = (i * 5); 4594 switch (temp) { 4595 case ID_LED_ON1_DEF2: 4596 case ID_LED_ON1_ON2: 4597 case ID_LED_ON1_OFF2: 4598 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4599 mac->ledctl_mode1 |= (ledctl_on << shift); 4600 break; 4601 case ID_LED_OFF1_DEF2: 4602 case ID_LED_OFF1_ON2: 4603 case ID_LED_OFF1_OFF2: 4604 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4605 mac->ledctl_mode1 |= (ledctl_off << shift); 4606 break; 4607 default: 4608 /* Do nothing */ 4609 break; 4610 } 4611 switch (temp) { 4612 case ID_LED_DEF1_ON2: 4613 case ID_LED_ON1_ON2: 4614 case ID_LED_OFF1_ON2: 4615 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4616 mac->ledctl_mode2 |= (ledctl_on << shift); 4617 break; 4618 case ID_LED_DEF1_OFF2: 4619 case ID_LED_ON1_OFF2: 4620 case ID_LED_OFF1_OFF2: 4621 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4622 mac->ledctl_mode2 |= (ledctl_off << shift); 4623 break; 4624 default: 4625 /* Do nothing */ 4626 break; 4627 } 4628 } 4629 4630 return 0; 4631 } 4632 4633 /** 4634 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4635 * @hw: pointer to the HW structure 4636 * 4637 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4638 * register, so the the bus width is hard coded. 4639 **/ 4640 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4641 { 4642 struct e1000_bus_info *bus = &hw->bus; 4643 s32 ret_val; 4644 4645 ret_val = e1000e_get_bus_info_pcie(hw); 4646 4647 /* ICH devices are "PCI Express"-ish. They have 4648 * a configuration space, but do not contain 4649 * PCI Express Capability registers, so bus width 4650 * must be hardcoded. 4651 */ 4652 if (bus->width == e1000_bus_width_unknown) 4653 bus->width = e1000_bus_width_pcie_x1; 4654 4655 return ret_val; 4656 } 4657 4658 /** 4659 * e1000_reset_hw_ich8lan - Reset the hardware 4660 * @hw: pointer to the HW structure 4661 * 4662 * Does a full reset of the hardware which includes a reset of the PHY and 4663 * MAC. 4664 **/ 4665 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4666 { 4667 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4668 u16 kum_cfg; 4669 u32 ctrl, reg; 4670 s32 ret_val; 4671 4672 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4673 * on the last TLP read/write transaction when MAC is reset. 4674 */ 4675 ret_val = e1000e_disable_pcie_master(hw); 4676 if (ret_val) 4677 e_dbg("PCI-E Master disable polling has failed.\n"); 4678 4679 e_dbg("Masking off all interrupts\n"); 4680 ew32(IMC, 0xffffffff); 4681 4682 /* Disable the Transmit and Receive units. Then delay to allow 4683 * any pending transactions to complete before we hit the MAC 4684 * with the global reset. 4685 */ 4686 ew32(RCTL, 0); 4687 ew32(TCTL, E1000_TCTL_PSP); 4688 e1e_flush(); 4689 4690 usleep_range(10000, 11000); 4691 4692 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4693 if (hw->mac.type == e1000_ich8lan) { 4694 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4695 ew32(PBA, E1000_PBA_8K); 4696 /* Set Packet Buffer Size to 16k. */ 4697 ew32(PBS, E1000_PBS_16K); 4698 } 4699 4700 if (hw->mac.type == e1000_pchlan) { 4701 /* Save the NVM K1 bit setting */ 4702 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4703 if (ret_val) 4704 return ret_val; 4705 4706 if (kum_cfg & E1000_NVM_K1_ENABLE) 4707 dev_spec->nvm_k1_enabled = true; 4708 else 4709 dev_spec->nvm_k1_enabled = false; 4710 } 4711 4712 ctrl = er32(CTRL); 4713 4714 if (!hw->phy.ops.check_reset_block(hw)) { 4715 /* Full-chip reset requires MAC and PHY reset at the same 4716 * time to make sure the interface between MAC and the 4717 * external PHY is reset. 4718 */ 4719 ctrl |= E1000_CTRL_PHY_RST; 4720 4721 /* Gate automatic PHY configuration by hardware on 4722 * non-managed 82579 4723 */ 4724 if ((hw->mac.type == e1000_pch2lan) && 4725 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4726 e1000_gate_hw_phy_config_ich8lan(hw, true); 4727 } 4728 ret_val = e1000_acquire_swflag_ich8lan(hw); 4729 e_dbg("Issuing a global reset to ich8lan\n"); 4730 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4731 /* cannot issue a flush here because it hangs the hardware */ 4732 msleep(20); 4733 4734 /* Set Phy Config Counter to 50msec */ 4735 if (hw->mac.type == e1000_pch2lan) { 4736 reg = er32(FEXTNVM3); 4737 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4738 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4739 ew32(FEXTNVM3, reg); 4740 } 4741 4742 if (!ret_val) 4743 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4744 4745 if (ctrl & E1000_CTRL_PHY_RST) { 4746 ret_val = hw->phy.ops.get_cfg_done(hw); 4747 if (ret_val) 4748 return ret_val; 4749 4750 ret_val = e1000_post_phy_reset_ich8lan(hw); 4751 if (ret_val) 4752 return ret_val; 4753 } 4754 4755 /* For PCH, this write will make sure that any noise 4756 * will be detected as a CRC error and be dropped rather than show up 4757 * as a bad packet to the DMA engine. 4758 */ 4759 if (hw->mac.type == e1000_pchlan) 4760 ew32(CRC_OFFSET, 0x65656565); 4761 4762 ew32(IMC, 0xffffffff); 4763 er32(ICR); 4764 4765 reg = er32(KABGTXD); 4766 reg |= E1000_KABGTXD_BGSQLBIAS; 4767 ew32(KABGTXD, reg); 4768 4769 return 0; 4770 } 4771 4772 /** 4773 * e1000_init_hw_ich8lan - Initialize the hardware 4774 * @hw: pointer to the HW structure 4775 * 4776 * Prepares the hardware for transmit and receive by doing the following: 4777 * - initialize hardware bits 4778 * - initialize LED identification 4779 * - setup receive address registers 4780 * - setup flow control 4781 * - setup transmit descriptors 4782 * - clear statistics 4783 **/ 4784 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4785 { 4786 struct e1000_mac_info *mac = &hw->mac; 4787 u32 ctrl_ext, txdctl, snoop; 4788 s32 ret_val; 4789 u16 i; 4790 4791 e1000_initialize_hw_bits_ich8lan(hw); 4792 4793 /* Initialize identification LED */ 4794 ret_val = mac->ops.id_led_init(hw); 4795 /* An error is not fatal and we should not stop init due to this */ 4796 if (ret_val) 4797 e_dbg("Error initializing identification LED\n"); 4798 4799 /* Setup the receive address. */ 4800 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4801 4802 /* Zero out the Multicast HASH table */ 4803 e_dbg("Zeroing the MTA\n"); 4804 for (i = 0; i < mac->mta_reg_count; i++) 4805 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4806 4807 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4808 * the ME. Disable wakeup by clearing the host wakeup bit. 4809 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4810 */ 4811 if (hw->phy.type == e1000_phy_82578) { 4812 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4813 i &= ~BM_WUC_HOST_WU_BIT; 4814 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4815 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4816 if (ret_val) 4817 return ret_val; 4818 } 4819 4820 /* Setup link and flow control */ 4821 ret_val = mac->ops.setup_link(hw); 4822 4823 /* Set the transmit descriptor write-back policy for both queues */ 4824 txdctl = er32(TXDCTL(0)); 4825 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4826 E1000_TXDCTL_FULL_TX_DESC_WB); 4827 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4828 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4829 ew32(TXDCTL(0), txdctl); 4830 txdctl = er32(TXDCTL(1)); 4831 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4832 E1000_TXDCTL_FULL_TX_DESC_WB); 4833 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4834 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4835 ew32(TXDCTL(1), txdctl); 4836 4837 /* ICH8 has opposite polarity of no_snoop bits. 4838 * By default, we should use snoop behavior. 4839 */ 4840 if (mac->type == e1000_ich8lan) 4841 snoop = PCIE_ICH8_SNOOP_ALL; 4842 else 4843 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4844 e1000e_set_pcie_no_snoop(hw, snoop); 4845 4846 ctrl_ext = er32(CTRL_EXT); 4847 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4848 ew32(CTRL_EXT, ctrl_ext); 4849 4850 /* Clear all of the statistics registers (clear on read). It is 4851 * important that we do this after we have tried to establish link 4852 * because the symbol error count will increment wildly if there 4853 * is no link. 4854 */ 4855 e1000_clear_hw_cntrs_ich8lan(hw); 4856 4857 return ret_val; 4858 } 4859 4860 /** 4861 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4862 * @hw: pointer to the HW structure 4863 * 4864 * Sets/Clears required hardware bits necessary for correctly setting up the 4865 * hardware for transmit and receive. 4866 **/ 4867 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4868 { 4869 u32 reg; 4870 4871 /* Extended Device Control */ 4872 reg = er32(CTRL_EXT); 4873 reg |= BIT(22); 4874 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4875 if (hw->mac.type >= e1000_pchlan) 4876 reg |= E1000_CTRL_EXT_PHYPDEN; 4877 ew32(CTRL_EXT, reg); 4878 4879 /* Transmit Descriptor Control 0 */ 4880 reg = er32(TXDCTL(0)); 4881 reg |= BIT(22); 4882 ew32(TXDCTL(0), reg); 4883 4884 /* Transmit Descriptor Control 1 */ 4885 reg = er32(TXDCTL(1)); 4886 reg |= BIT(22); 4887 ew32(TXDCTL(1), reg); 4888 4889 /* Transmit Arbitration Control 0 */ 4890 reg = er32(TARC(0)); 4891 if (hw->mac.type == e1000_ich8lan) 4892 reg |= BIT(28) | BIT(29); 4893 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4894 ew32(TARC(0), reg); 4895 4896 /* Transmit Arbitration Control 1 */ 4897 reg = er32(TARC(1)); 4898 if (er32(TCTL) & E1000_TCTL_MULR) 4899 reg &= ~BIT(28); 4900 else 4901 reg |= BIT(28); 4902 reg |= BIT(24) | BIT(26) | BIT(30); 4903 ew32(TARC(1), reg); 4904 4905 /* Device Status */ 4906 if (hw->mac.type == e1000_ich8lan) { 4907 reg = er32(STATUS); 4908 reg &= ~BIT(31); 4909 ew32(STATUS, reg); 4910 } 4911 4912 /* work-around descriptor data corruption issue during nfs v2 udp 4913 * traffic, just disable the nfs filtering capability 4914 */ 4915 reg = er32(RFCTL); 4916 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4917 4918 /* Disable IPv6 extension header parsing because some malformed 4919 * IPv6 headers can hang the Rx. 4920 */ 4921 if (hw->mac.type == e1000_ich8lan) 4922 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4923 ew32(RFCTL, reg); 4924 4925 /* Enable ECC on Lynxpoint */ 4926 if (hw->mac.type >= e1000_pch_lpt) { 4927 reg = er32(PBECCSTS); 4928 reg |= E1000_PBECCSTS_ECC_ENABLE; 4929 ew32(PBECCSTS, reg); 4930 4931 reg = er32(CTRL); 4932 reg |= E1000_CTRL_MEHE; 4933 ew32(CTRL, reg); 4934 } 4935 } 4936 4937 /** 4938 * e1000_setup_link_ich8lan - Setup flow control and link settings 4939 * @hw: pointer to the HW structure 4940 * 4941 * Determines which flow control settings to use, then configures flow 4942 * control. Calls the appropriate media-specific link configuration 4943 * function. Assuming the adapter has a valid link partner, a valid link 4944 * should be established. Assumes the hardware has previously been reset 4945 * and the transmitter and receiver are not enabled. 4946 **/ 4947 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4948 { 4949 s32 ret_val; 4950 4951 if (hw->phy.ops.check_reset_block(hw)) 4952 return 0; 4953 4954 /* ICH parts do not have a word in the NVM to determine 4955 * the default flow control setting, so we explicitly 4956 * set it to full. 4957 */ 4958 if (hw->fc.requested_mode == e1000_fc_default) { 4959 /* Workaround h/w hang when Tx flow control enabled */ 4960 if (hw->mac.type == e1000_pchlan) 4961 hw->fc.requested_mode = e1000_fc_rx_pause; 4962 else 4963 hw->fc.requested_mode = e1000_fc_full; 4964 } 4965 4966 /* Save off the requested flow control mode for use later. Depending 4967 * on the link partner's capabilities, we may or may not use this mode. 4968 */ 4969 hw->fc.current_mode = hw->fc.requested_mode; 4970 4971 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4972 4973 /* Continue to configure the copper link. */ 4974 ret_val = hw->mac.ops.setup_physical_interface(hw); 4975 if (ret_val) 4976 return ret_val; 4977 4978 ew32(FCTTV, hw->fc.pause_time); 4979 if ((hw->phy.type == e1000_phy_82578) || 4980 (hw->phy.type == e1000_phy_82579) || 4981 (hw->phy.type == e1000_phy_i217) || 4982 (hw->phy.type == e1000_phy_82577)) { 4983 ew32(FCRTV_PCH, hw->fc.refresh_time); 4984 4985 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4986 hw->fc.pause_time); 4987 if (ret_val) 4988 return ret_val; 4989 } 4990 4991 return e1000e_set_fc_watermarks(hw); 4992 } 4993 4994 /** 4995 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4996 * @hw: pointer to the HW structure 4997 * 4998 * Configures the kumeran interface to the PHY to wait the appropriate time 4999 * when polling the PHY, then call the generic setup_copper_link to finish 5000 * configuring the copper link. 5001 **/ 5002 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 5003 { 5004 u32 ctrl; 5005 s32 ret_val; 5006 u16 reg_data; 5007 5008 ctrl = er32(CTRL); 5009 ctrl |= E1000_CTRL_SLU; 5010 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5011 ew32(CTRL, ctrl); 5012 5013 /* Set the mac to wait the maximum time between each iteration 5014 * and increase the max iterations when polling the phy; 5015 * this fixes erroneous timeouts at 10Mbps. 5016 */ 5017 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 5018 if (ret_val) 5019 return ret_val; 5020 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5021 ®_data); 5022 if (ret_val) 5023 return ret_val; 5024 reg_data |= 0x3F; 5025 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5026 reg_data); 5027 if (ret_val) 5028 return ret_val; 5029 5030 switch (hw->phy.type) { 5031 case e1000_phy_igp_3: 5032 ret_val = e1000e_copper_link_setup_igp(hw); 5033 if (ret_val) 5034 return ret_val; 5035 break; 5036 case e1000_phy_bm: 5037 case e1000_phy_82578: 5038 ret_val = e1000e_copper_link_setup_m88(hw); 5039 if (ret_val) 5040 return ret_val; 5041 break; 5042 case e1000_phy_82577: 5043 case e1000_phy_82579: 5044 ret_val = e1000_copper_link_setup_82577(hw); 5045 if (ret_val) 5046 return ret_val; 5047 break; 5048 case e1000_phy_ife: 5049 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5050 if (ret_val) 5051 return ret_val; 5052 5053 reg_data &= ~IFE_PMC_AUTO_MDIX; 5054 5055 switch (hw->phy.mdix) { 5056 case 1: 5057 reg_data &= ~IFE_PMC_FORCE_MDIX; 5058 break; 5059 case 2: 5060 reg_data |= IFE_PMC_FORCE_MDIX; 5061 break; 5062 case 0: 5063 default: 5064 reg_data |= IFE_PMC_AUTO_MDIX; 5065 break; 5066 } 5067 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5068 if (ret_val) 5069 return ret_val; 5070 break; 5071 default: 5072 break; 5073 } 5074 5075 return e1000e_setup_copper_link(hw); 5076 } 5077 5078 /** 5079 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5080 * @hw: pointer to the HW structure 5081 * 5082 * Calls the PHY specific link setup function and then calls the 5083 * generic setup_copper_link to finish configuring the link for 5084 * Lynxpoint PCH devices 5085 **/ 5086 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5087 { 5088 u32 ctrl; 5089 s32 ret_val; 5090 5091 ctrl = er32(CTRL); 5092 ctrl |= E1000_CTRL_SLU; 5093 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5094 ew32(CTRL, ctrl); 5095 5096 ret_val = e1000_copper_link_setup_82577(hw); 5097 if (ret_val) 5098 return ret_val; 5099 5100 return e1000e_setup_copper_link(hw); 5101 } 5102 5103 /** 5104 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5105 * @hw: pointer to the HW structure 5106 * @speed: pointer to store current link speed 5107 * @duplex: pointer to store the current link duplex 5108 * 5109 * Calls the generic get_speed_and_duplex to retrieve the current link 5110 * information and then calls the Kumeran lock loss workaround for links at 5111 * gigabit speeds. 5112 **/ 5113 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5114 u16 *duplex) 5115 { 5116 s32 ret_val; 5117 5118 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5119 if (ret_val) 5120 return ret_val; 5121 5122 if ((hw->mac.type == e1000_ich8lan) && 5123 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5124 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5125 } 5126 5127 return ret_val; 5128 } 5129 5130 /** 5131 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5132 * @hw: pointer to the HW structure 5133 * 5134 * Work-around for 82566 Kumeran PCS lock loss: 5135 * On link status change (i.e. PCI reset, speed change) and link is up and 5136 * speed is gigabit- 5137 * 0) if workaround is optionally disabled do nothing 5138 * 1) wait 1ms for Kumeran link to come up 5139 * 2) check Kumeran Diagnostic register PCS lock loss bit 5140 * 3) if not set the link is locked (all is good), otherwise... 5141 * 4) reset the PHY 5142 * 5) repeat up to 10 times 5143 * Note: this is only called for IGP3 copper when speed is 1gb. 5144 **/ 5145 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5146 { 5147 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5148 u32 phy_ctrl; 5149 s32 ret_val; 5150 u16 i, data; 5151 bool link; 5152 5153 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5154 return 0; 5155 5156 /* Make sure link is up before proceeding. If not just return. 5157 * Attempting this while link is negotiating fouled up link 5158 * stability 5159 */ 5160 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5161 if (!link) 5162 return 0; 5163 5164 for (i = 0; i < 10; i++) { 5165 /* read once to clear */ 5166 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5167 if (ret_val) 5168 return ret_val; 5169 /* and again to get new status */ 5170 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5171 if (ret_val) 5172 return ret_val; 5173 5174 /* check for PCS lock */ 5175 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5176 return 0; 5177 5178 /* Issue PHY reset */ 5179 e1000_phy_hw_reset(hw); 5180 mdelay(5); 5181 } 5182 /* Disable GigE link negotiation */ 5183 phy_ctrl = er32(PHY_CTRL); 5184 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5185 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5186 ew32(PHY_CTRL, phy_ctrl); 5187 5188 /* Call gig speed drop workaround on Gig disable before accessing 5189 * any PHY registers 5190 */ 5191 e1000e_gig_downshift_workaround_ich8lan(hw); 5192 5193 /* unable to acquire PCS lock */ 5194 return -E1000_ERR_PHY; 5195 } 5196 5197 /** 5198 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5199 * @hw: pointer to the HW structure 5200 * @state: boolean value used to set the current Kumeran workaround state 5201 * 5202 * If ICH8, set the current Kumeran workaround state (enabled - true 5203 * /disabled - false). 5204 **/ 5205 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5206 bool state) 5207 { 5208 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5209 5210 if (hw->mac.type != e1000_ich8lan) { 5211 e_dbg("Workaround applies to ICH8 only.\n"); 5212 return; 5213 } 5214 5215 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5216 } 5217 5218 /** 5219 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5220 * @hw: pointer to the HW structure 5221 * 5222 * Workaround for 82566 power-down on D3 entry: 5223 * 1) disable gigabit link 5224 * 2) write VR power-down enable 5225 * 3) read it back 5226 * Continue if successful, else issue LCD reset and repeat 5227 **/ 5228 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5229 { 5230 u32 reg; 5231 u16 data; 5232 u8 retry = 0; 5233 5234 if (hw->phy.type != e1000_phy_igp_3) 5235 return; 5236 5237 /* Try the workaround twice (if needed) */ 5238 do { 5239 /* Disable link */ 5240 reg = er32(PHY_CTRL); 5241 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5242 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5243 ew32(PHY_CTRL, reg); 5244 5245 /* Call gig speed drop workaround on Gig disable before 5246 * accessing any PHY registers 5247 */ 5248 if (hw->mac.type == e1000_ich8lan) 5249 e1000e_gig_downshift_workaround_ich8lan(hw); 5250 5251 /* Write VR power-down enable */ 5252 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5253 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5254 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5255 5256 /* Read it back and test */ 5257 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5258 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5259 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5260 break; 5261 5262 /* Issue PHY reset and repeat at most one more time */ 5263 reg = er32(CTRL); 5264 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5265 retry++; 5266 } while (retry); 5267 } 5268 5269 /** 5270 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5271 * @hw: pointer to the HW structure 5272 * 5273 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5274 * LPLU, Gig disable, MDIC PHY reset): 5275 * 1) Set Kumeran Near-end loopback 5276 * 2) Clear Kumeran Near-end loopback 5277 * Should only be called for ICH8[m] devices with any 1G Phy. 5278 **/ 5279 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5280 { 5281 s32 ret_val; 5282 u16 reg_data; 5283 5284 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5285 return; 5286 5287 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5288 ®_data); 5289 if (ret_val) 5290 return; 5291 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5292 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5293 reg_data); 5294 if (ret_val) 5295 return; 5296 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5297 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5298 } 5299 5300 /** 5301 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5302 * @hw: pointer to the HW structure 5303 * 5304 * During S0 to Sx transition, it is possible the link remains at gig 5305 * instead of negotiating to a lower speed. Before going to Sx, set 5306 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5307 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5308 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5309 * needs to be written. 5310 * Parts that support (and are linked to a partner which support) EEE in 5311 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5312 * than 10Mbps w/o EEE. 5313 **/ 5314 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5315 { 5316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5317 u32 phy_ctrl; 5318 s32 ret_val; 5319 5320 phy_ctrl = er32(PHY_CTRL); 5321 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5322 5323 if (hw->phy.type == e1000_phy_i217) { 5324 u16 phy_reg, device_id = hw->adapter->pdev->device; 5325 5326 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5327 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5328 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5329 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5330 (hw->mac.type >= e1000_pch_spt)) { 5331 u32 fextnvm6 = er32(FEXTNVM6); 5332 5333 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5334 } 5335 5336 ret_val = hw->phy.ops.acquire(hw); 5337 if (ret_val) 5338 goto out; 5339 5340 if (!dev_spec->eee_disable) { 5341 u16 eee_advert; 5342 5343 ret_val = 5344 e1000_read_emi_reg_locked(hw, 5345 I217_EEE_ADVERTISEMENT, 5346 &eee_advert); 5347 if (ret_val) 5348 goto release; 5349 5350 /* Disable LPLU if both link partners support 100BaseT 5351 * EEE and 100Full is advertised on both ends of the 5352 * link, and enable Auto Enable LPI since there will 5353 * be no driver to enable LPI while in Sx. 5354 */ 5355 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5356 (dev_spec->eee_lp_ability & 5357 I82579_EEE_100_SUPPORTED) && 5358 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5359 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5360 E1000_PHY_CTRL_NOND0A_LPLU); 5361 5362 /* Set Auto Enable LPI after link up */ 5363 e1e_rphy_locked(hw, 5364 I217_LPI_GPIO_CTRL, &phy_reg); 5365 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5366 e1e_wphy_locked(hw, 5367 I217_LPI_GPIO_CTRL, phy_reg); 5368 } 5369 } 5370 5371 /* For i217 Intel Rapid Start Technology support, 5372 * when the system is going into Sx and no manageability engine 5373 * is present, the driver must configure proxy to reset only on 5374 * power good. LPI (Low Power Idle) state must also reset only 5375 * on power good, as well as the MTA (Multicast table array). 5376 * The SMBus release must also be disabled on LCD reset. 5377 */ 5378 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5379 /* Enable proxy to reset only on power good. */ 5380 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5381 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5382 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5383 5384 /* Set bit enable LPI (EEE) to reset only on 5385 * power good. 5386 */ 5387 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5388 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5389 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5390 5391 /* Disable the SMB release on LCD reset. */ 5392 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5393 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5394 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5395 } 5396 5397 /* Enable MTA to reset for Intel Rapid Start Technology 5398 * Support 5399 */ 5400 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5401 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5402 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5403 5404 release: 5405 hw->phy.ops.release(hw); 5406 } 5407 out: 5408 ew32(PHY_CTRL, phy_ctrl); 5409 5410 if (hw->mac.type == e1000_ich8lan) 5411 e1000e_gig_downshift_workaround_ich8lan(hw); 5412 5413 if (hw->mac.type >= e1000_pchlan) { 5414 e1000_oem_bits_config_ich8lan(hw, false); 5415 5416 /* Reset PHY to activate OEM bits on 82577/8 */ 5417 if (hw->mac.type == e1000_pchlan) 5418 e1000e_phy_hw_reset_generic(hw); 5419 5420 ret_val = hw->phy.ops.acquire(hw); 5421 if (ret_val) 5422 return; 5423 e1000_write_smbus_addr(hw); 5424 hw->phy.ops.release(hw); 5425 } 5426 } 5427 5428 /** 5429 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5430 * @hw: pointer to the HW structure 5431 * 5432 * During Sx to S0 transitions on non-managed devices or managed devices 5433 * on which PHY resets are not blocked, if the PHY registers cannot be 5434 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5435 * the PHY. 5436 * On i217, setup Intel Rapid Start Technology. 5437 **/ 5438 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5439 { 5440 s32 ret_val; 5441 5442 if (hw->mac.type < e1000_pch2lan) 5443 return; 5444 5445 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5446 if (ret_val) { 5447 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5448 return; 5449 } 5450 5451 /* For i217 Intel Rapid Start Technology support when the system 5452 * is transitioning from Sx and no manageability engine is present 5453 * configure SMBus to restore on reset, disable proxy, and enable 5454 * the reset on MTA (Multicast table array). 5455 */ 5456 if (hw->phy.type == e1000_phy_i217) { 5457 u16 phy_reg; 5458 5459 ret_val = hw->phy.ops.acquire(hw); 5460 if (ret_val) { 5461 e_dbg("Failed to setup iRST\n"); 5462 return; 5463 } 5464 5465 /* Clear Auto Enable LPI after link up */ 5466 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5467 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5468 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5469 5470 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5471 /* Restore clear on SMB if no manageability engine 5472 * is present 5473 */ 5474 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5475 if (ret_val) 5476 goto release; 5477 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5478 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5479 5480 /* Disable Proxy */ 5481 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5482 } 5483 /* Enable reset on MTA */ 5484 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5485 if (ret_val) 5486 goto release; 5487 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5488 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5489 release: 5490 if (ret_val) 5491 e_dbg("Error %d in resume workarounds\n", ret_val); 5492 hw->phy.ops.release(hw); 5493 } 5494 } 5495 5496 /** 5497 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5498 * @hw: pointer to the HW structure 5499 * 5500 * Return the LED back to the default configuration. 5501 **/ 5502 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5503 { 5504 if (hw->phy.type == e1000_phy_ife) 5505 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5506 5507 ew32(LEDCTL, hw->mac.ledctl_default); 5508 return 0; 5509 } 5510 5511 /** 5512 * e1000_led_on_ich8lan - Turn LEDs on 5513 * @hw: pointer to the HW structure 5514 * 5515 * Turn on the LEDs. 5516 **/ 5517 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5518 { 5519 if (hw->phy.type == e1000_phy_ife) 5520 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5521 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5522 5523 ew32(LEDCTL, hw->mac.ledctl_mode2); 5524 return 0; 5525 } 5526 5527 /** 5528 * e1000_led_off_ich8lan - Turn LEDs off 5529 * @hw: pointer to the HW structure 5530 * 5531 * Turn off the LEDs. 5532 **/ 5533 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5534 { 5535 if (hw->phy.type == e1000_phy_ife) 5536 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5537 (IFE_PSCL_PROBE_MODE | 5538 IFE_PSCL_PROBE_LEDS_OFF)); 5539 5540 ew32(LEDCTL, hw->mac.ledctl_mode1); 5541 return 0; 5542 } 5543 5544 /** 5545 * e1000_setup_led_pchlan - Configures SW controllable LED 5546 * @hw: pointer to the HW structure 5547 * 5548 * This prepares the SW controllable LED for use. 5549 **/ 5550 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5551 { 5552 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5553 } 5554 5555 /** 5556 * e1000_cleanup_led_pchlan - Restore the default LED operation 5557 * @hw: pointer to the HW structure 5558 * 5559 * Return the LED back to the default configuration. 5560 **/ 5561 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5562 { 5563 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5564 } 5565 5566 /** 5567 * e1000_led_on_pchlan - Turn LEDs on 5568 * @hw: pointer to the HW structure 5569 * 5570 * Turn on the LEDs. 5571 **/ 5572 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5573 { 5574 u16 data = (u16)hw->mac.ledctl_mode2; 5575 u32 i, led; 5576 5577 /* If no link, then turn LED on by setting the invert bit 5578 * for each LED that's mode is "link_up" in ledctl_mode2. 5579 */ 5580 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5581 for (i = 0; i < 3; i++) { 5582 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5583 if ((led & E1000_PHY_LED0_MODE_MASK) != 5584 E1000_LEDCTL_MODE_LINK_UP) 5585 continue; 5586 if (led & E1000_PHY_LED0_IVRT) 5587 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5588 else 5589 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5590 } 5591 } 5592 5593 return e1e_wphy(hw, HV_LED_CONFIG, data); 5594 } 5595 5596 /** 5597 * e1000_led_off_pchlan - Turn LEDs off 5598 * @hw: pointer to the HW structure 5599 * 5600 * Turn off the LEDs. 5601 **/ 5602 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5603 { 5604 u16 data = (u16)hw->mac.ledctl_mode1; 5605 u32 i, led; 5606 5607 /* If no link, then turn LED off by clearing the invert bit 5608 * for each LED that's mode is "link_up" in ledctl_mode1. 5609 */ 5610 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5611 for (i = 0; i < 3; i++) { 5612 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5613 if ((led & E1000_PHY_LED0_MODE_MASK) != 5614 E1000_LEDCTL_MODE_LINK_UP) 5615 continue; 5616 if (led & E1000_PHY_LED0_IVRT) 5617 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5618 else 5619 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5620 } 5621 } 5622 5623 return e1e_wphy(hw, HV_LED_CONFIG, data); 5624 } 5625 5626 /** 5627 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5628 * @hw: pointer to the HW structure 5629 * 5630 * Read appropriate register for the config done bit for completion status 5631 * and configure the PHY through s/w for EEPROM-less parts. 5632 * 5633 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5634 * config done bit, so only an error is logged and continues. If we were 5635 * to return with error, EEPROM-less silicon would not be able to be reset 5636 * or change link. 5637 **/ 5638 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5639 { 5640 s32 ret_val = 0; 5641 u32 bank = 0; 5642 u32 status; 5643 5644 e1000e_get_cfg_done_generic(hw); 5645 5646 /* Wait for indication from h/w that it has completed basic config */ 5647 if (hw->mac.type >= e1000_ich10lan) { 5648 e1000_lan_init_done_ich8lan(hw); 5649 } else { 5650 ret_val = e1000e_get_auto_rd_done(hw); 5651 if (ret_val) { 5652 /* When auto config read does not complete, do not 5653 * return with an error. This can happen in situations 5654 * where there is no eeprom and prevents getting link. 5655 */ 5656 e_dbg("Auto Read Done did not complete\n"); 5657 ret_val = 0; 5658 } 5659 } 5660 5661 /* Clear PHY Reset Asserted bit */ 5662 status = er32(STATUS); 5663 if (status & E1000_STATUS_PHYRA) 5664 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5665 else 5666 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5667 5668 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5669 if (hw->mac.type <= e1000_ich9lan) { 5670 if (!(er32(EECD) & E1000_EECD_PRES) && 5671 (hw->phy.type == e1000_phy_igp_3)) { 5672 e1000e_phy_init_script_igp3(hw); 5673 } 5674 } else { 5675 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5676 /* Maybe we should do a basic PHY config */ 5677 e_dbg("EEPROM not present\n"); 5678 ret_val = -E1000_ERR_CONFIG; 5679 } 5680 } 5681 5682 return ret_val; 5683 } 5684 5685 /** 5686 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5687 * @hw: pointer to the HW structure 5688 * 5689 * In the case of a PHY power down to save power, or to turn off link during a 5690 * driver unload, or wake on lan is not enabled, remove the link. 5691 **/ 5692 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5693 { 5694 /* If the management interface is not enabled, then power down */ 5695 if (!(hw->mac.ops.check_mng_mode(hw) || 5696 hw->phy.ops.check_reset_block(hw))) 5697 e1000_power_down_phy_copper(hw); 5698 } 5699 5700 /** 5701 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5702 * @hw: pointer to the HW structure 5703 * 5704 * Clears hardware counters specific to the silicon family and calls 5705 * clear_hw_cntrs_generic to clear all general purpose counters. 5706 **/ 5707 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5708 { 5709 u16 phy_data; 5710 s32 ret_val; 5711 5712 e1000e_clear_hw_cntrs_base(hw); 5713 5714 er32(ALGNERRC); 5715 er32(RXERRC); 5716 er32(TNCRS); 5717 er32(CEXTERR); 5718 er32(TSCTC); 5719 er32(TSCTFC); 5720 5721 er32(MGTPRC); 5722 er32(MGTPDC); 5723 er32(MGTPTC); 5724 5725 er32(IAC); 5726 er32(ICRXOC); 5727 5728 /* Clear PHY statistics registers */ 5729 if ((hw->phy.type == e1000_phy_82578) || 5730 (hw->phy.type == e1000_phy_82579) || 5731 (hw->phy.type == e1000_phy_i217) || 5732 (hw->phy.type == e1000_phy_82577)) { 5733 ret_val = hw->phy.ops.acquire(hw); 5734 if (ret_val) 5735 return; 5736 ret_val = hw->phy.ops.set_page(hw, 5737 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5738 if (ret_val) 5739 goto release; 5740 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5741 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5742 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5743 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5744 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5745 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5746 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5747 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5748 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5749 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5750 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5751 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5752 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5753 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5754 release: 5755 hw->phy.ops.release(hw); 5756 } 5757 } 5758 5759 static const struct e1000_mac_operations ich8_mac_ops = { 5760 /* check_mng_mode dependent on mac type */ 5761 .check_for_link = e1000_check_for_copper_link_ich8lan, 5762 /* cleanup_led dependent on mac type */ 5763 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5764 .get_bus_info = e1000_get_bus_info_ich8lan, 5765 .set_lan_id = e1000_set_lan_id_single_port, 5766 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5767 /* led_on dependent on mac type */ 5768 /* led_off dependent on mac type */ 5769 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5770 .reset_hw = e1000_reset_hw_ich8lan, 5771 .init_hw = e1000_init_hw_ich8lan, 5772 .setup_link = e1000_setup_link_ich8lan, 5773 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5774 /* id_led_init dependent on mac type */ 5775 .config_collision_dist = e1000e_config_collision_dist_generic, 5776 .rar_set = e1000e_rar_set_generic, 5777 .rar_get_count = e1000e_rar_get_count_generic, 5778 }; 5779 5780 static const struct e1000_phy_operations ich8_phy_ops = { 5781 .acquire = e1000_acquire_swflag_ich8lan, 5782 .check_reset_block = e1000_check_reset_block_ich8lan, 5783 .commit = NULL, 5784 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5785 .get_cable_length = e1000e_get_cable_length_igp_2, 5786 .read_reg = e1000e_read_phy_reg_igp, 5787 .release = e1000_release_swflag_ich8lan, 5788 .reset = e1000_phy_hw_reset_ich8lan, 5789 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5790 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5791 .write_reg = e1000e_write_phy_reg_igp, 5792 }; 5793 5794 static const struct e1000_nvm_operations ich8_nvm_ops = { 5795 .acquire = e1000_acquire_nvm_ich8lan, 5796 .read = e1000_read_nvm_ich8lan, 5797 .release = e1000_release_nvm_ich8lan, 5798 .reload = e1000e_reload_nvm_generic, 5799 .update = e1000_update_nvm_checksum_ich8lan, 5800 .valid_led_default = e1000_valid_led_default_ich8lan, 5801 .validate = e1000_validate_nvm_checksum_ich8lan, 5802 .write = e1000_write_nvm_ich8lan, 5803 }; 5804 5805 static const struct e1000_nvm_operations spt_nvm_ops = { 5806 .acquire = e1000_acquire_nvm_ich8lan, 5807 .release = e1000_release_nvm_ich8lan, 5808 .read = e1000_read_nvm_spt, 5809 .update = e1000_update_nvm_checksum_spt, 5810 .reload = e1000e_reload_nvm_generic, 5811 .valid_led_default = e1000_valid_led_default_ich8lan, 5812 .validate = e1000_validate_nvm_checksum_ich8lan, 5813 .write = e1000_write_nvm_ich8lan, 5814 }; 5815 5816 const struct e1000_info e1000_ich8_info = { 5817 .mac = e1000_ich8lan, 5818 .flags = FLAG_HAS_WOL 5819 | FLAG_IS_ICH 5820 | FLAG_HAS_CTRLEXT_ON_LOAD 5821 | FLAG_HAS_AMT 5822 | FLAG_HAS_FLASH 5823 | FLAG_APME_IN_WUC, 5824 .pba = 8, 5825 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5826 .get_variants = e1000_get_variants_ich8lan, 5827 .mac_ops = &ich8_mac_ops, 5828 .phy_ops = &ich8_phy_ops, 5829 .nvm_ops = &ich8_nvm_ops, 5830 }; 5831 5832 const struct e1000_info e1000_ich9_info = { 5833 .mac = e1000_ich9lan, 5834 .flags = FLAG_HAS_JUMBO_FRAMES 5835 | FLAG_IS_ICH 5836 | FLAG_HAS_WOL 5837 | FLAG_HAS_CTRLEXT_ON_LOAD 5838 | FLAG_HAS_AMT 5839 | FLAG_HAS_FLASH 5840 | FLAG_APME_IN_WUC, 5841 .pba = 18, 5842 .max_hw_frame_size = DEFAULT_JUMBO, 5843 .get_variants = e1000_get_variants_ich8lan, 5844 .mac_ops = &ich8_mac_ops, 5845 .phy_ops = &ich8_phy_ops, 5846 .nvm_ops = &ich8_nvm_ops, 5847 }; 5848 5849 const struct e1000_info e1000_ich10_info = { 5850 .mac = e1000_ich10lan, 5851 .flags = FLAG_HAS_JUMBO_FRAMES 5852 | FLAG_IS_ICH 5853 | FLAG_HAS_WOL 5854 | FLAG_HAS_CTRLEXT_ON_LOAD 5855 | FLAG_HAS_AMT 5856 | FLAG_HAS_FLASH 5857 | FLAG_APME_IN_WUC, 5858 .pba = 18, 5859 .max_hw_frame_size = DEFAULT_JUMBO, 5860 .get_variants = e1000_get_variants_ich8lan, 5861 .mac_ops = &ich8_mac_ops, 5862 .phy_ops = &ich8_phy_ops, 5863 .nvm_ops = &ich8_nvm_ops, 5864 }; 5865 5866 const struct e1000_info e1000_pch_info = { 5867 .mac = e1000_pchlan, 5868 .flags = FLAG_IS_ICH 5869 | FLAG_HAS_WOL 5870 | FLAG_HAS_CTRLEXT_ON_LOAD 5871 | FLAG_HAS_AMT 5872 | FLAG_HAS_FLASH 5873 | FLAG_HAS_JUMBO_FRAMES 5874 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5875 | FLAG_APME_IN_WUC, 5876 .flags2 = FLAG2_HAS_PHY_STATS, 5877 .pba = 26, 5878 .max_hw_frame_size = 4096, 5879 .get_variants = e1000_get_variants_ich8lan, 5880 .mac_ops = &ich8_mac_ops, 5881 .phy_ops = &ich8_phy_ops, 5882 .nvm_ops = &ich8_nvm_ops, 5883 }; 5884 5885 const struct e1000_info e1000_pch2_info = { 5886 .mac = e1000_pch2lan, 5887 .flags = FLAG_IS_ICH 5888 | FLAG_HAS_WOL 5889 | FLAG_HAS_HW_TIMESTAMP 5890 | FLAG_HAS_CTRLEXT_ON_LOAD 5891 | FLAG_HAS_AMT 5892 | FLAG_HAS_FLASH 5893 | FLAG_HAS_JUMBO_FRAMES 5894 | FLAG_APME_IN_WUC, 5895 .flags2 = FLAG2_HAS_PHY_STATS 5896 | FLAG2_HAS_EEE 5897 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5898 .pba = 26, 5899 .max_hw_frame_size = 9022, 5900 .get_variants = e1000_get_variants_ich8lan, 5901 .mac_ops = &ich8_mac_ops, 5902 .phy_ops = &ich8_phy_ops, 5903 .nvm_ops = &ich8_nvm_ops, 5904 }; 5905 5906 const struct e1000_info e1000_pch_lpt_info = { 5907 .mac = e1000_pch_lpt, 5908 .flags = FLAG_IS_ICH 5909 | FLAG_HAS_WOL 5910 | FLAG_HAS_HW_TIMESTAMP 5911 | FLAG_HAS_CTRLEXT_ON_LOAD 5912 | FLAG_HAS_AMT 5913 | FLAG_HAS_FLASH 5914 | FLAG_HAS_JUMBO_FRAMES 5915 | FLAG_APME_IN_WUC, 5916 .flags2 = FLAG2_HAS_PHY_STATS 5917 | FLAG2_HAS_EEE 5918 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5919 .pba = 26, 5920 .max_hw_frame_size = 9022, 5921 .get_variants = e1000_get_variants_ich8lan, 5922 .mac_ops = &ich8_mac_ops, 5923 .phy_ops = &ich8_phy_ops, 5924 .nvm_ops = &ich8_nvm_ops, 5925 }; 5926 5927 const struct e1000_info e1000_pch_spt_info = { 5928 .mac = e1000_pch_spt, 5929 .flags = FLAG_IS_ICH 5930 | FLAG_HAS_WOL 5931 | FLAG_HAS_HW_TIMESTAMP 5932 | FLAG_HAS_CTRLEXT_ON_LOAD 5933 | FLAG_HAS_AMT 5934 | FLAG_HAS_FLASH 5935 | FLAG_HAS_JUMBO_FRAMES 5936 | FLAG_APME_IN_WUC, 5937 .flags2 = FLAG2_HAS_PHY_STATS 5938 | FLAG2_HAS_EEE, 5939 .pba = 26, 5940 .max_hw_frame_size = 9022, 5941 .get_variants = e1000_get_variants_ich8lan, 5942 .mac_ops = &ich8_mac_ops, 5943 .phy_ops = &ich8_phy_ops, 5944 .nvm_ops = &spt_nvm_ops, 5945 }; 5946 5947 const struct e1000_info e1000_pch_cnp_info = { 5948 .mac = e1000_pch_cnp, 5949 .flags = FLAG_IS_ICH 5950 | FLAG_HAS_WOL 5951 | FLAG_HAS_HW_TIMESTAMP 5952 | FLAG_HAS_CTRLEXT_ON_LOAD 5953 | FLAG_HAS_AMT 5954 | FLAG_HAS_FLASH 5955 | FLAG_HAS_JUMBO_FRAMES 5956 | FLAG_APME_IN_WUC, 5957 .flags2 = FLAG2_HAS_PHY_STATS 5958 | FLAG2_HAS_EEE, 5959 .pba = 26, 5960 .max_hw_frame_size = 9022, 5961 .get_variants = e1000_get_variants_ich8lan, 5962 .mac_ops = &ich8_mac_ops, 5963 .phy_ops = &ich8_phy_ops, 5964 .nvm_ops = &spt_nvm_ops, 5965 }; 5966