1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 /* 82562G 10/100 Network Connection
5  * 82562G-2 10/100 Network Connection
6  * 82562GT 10/100 Network Connection
7  * 82562GT-2 10/100 Network Connection
8  * 82562V 10/100 Network Connection
9  * 82562V-2 10/100 Network Connection
10  * 82566DC-2 Gigabit Network Connection
11  * 82566DC Gigabit Network Connection
12  * 82566DM-2 Gigabit Network Connection
13  * 82566DM Gigabit Network Connection
14  * 82566MC Gigabit Network Connection
15  * 82566MM Gigabit Network Connection
16  * 82567LM Gigabit Network Connection
17  * 82567LF Gigabit Network Connection
18  * 82567V Gigabit Network Connection
19  * 82567LM-2 Gigabit Network Connection
20  * 82567LF-2 Gigabit Network Connection
21  * 82567V-2 Gigabit Network Connection
22  * 82567LF-3 Gigabit Network Connection
23  * 82567LM-3 Gigabit Network Connection
24  * 82567LM-4 Gigabit Network Connection
25  * 82577LM Gigabit Network Connection
26  * 82577LC Gigabit Network Connection
27  * 82578DM Gigabit Network Connection
28  * 82578DC Gigabit Network Connection
29  * 82579LM Gigabit Network Connection
30  * 82579V Gigabit Network Connection
31  * Ethernet Connection I217-LM
32  * Ethernet Connection I217-V
33  * Ethernet Connection I218-V
34  * Ethernet Connection I218-LM
35  * Ethernet Connection (2) I218-LM
36  * Ethernet Connection (2) I218-V
37  * Ethernet Connection (3) I218-LM
38  * Ethernet Connection (3) I218-V
39  */
40 
41 #include "e1000.h"
42 
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
46 	struct ich8_hsfsts {
47 		u16 flcdone:1;	/* bit 0 Flash Cycle Done */
48 		u16 flcerr:1;	/* bit 1 Flash Cycle Error */
49 		u16 dael:1;	/* bit 2 Direct Access error Log */
50 		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */
51 		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */
52 		u16 reserved1:2;	/* bit 13:6 Reserved */
53 		u16 reserved2:6;	/* bit 13:6 Reserved */
54 		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */
55 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */
56 	} hsf_status;
57 	u16 regval;
58 };
59 
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
63 	struct ich8_hsflctl {
64 		u16 flcgo:1;	/* 0 Flash Cycle Go */
65 		u16 flcycle:2;	/* 2:1 Flash Cycle */
66 		u16 reserved:5;	/* 7:3 Reserved  */
67 		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */
68 		u16 flockdn:6;	/* 15:10 Reserved */
69 	} hsf_ctrl;
70 	u16 regval;
71 };
72 
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
75 	struct ich8_flracc {
76 		u32 grra:8;	/* 0:7 GbE region Read Access */
77 		u32 grwa:8;	/* 8:15 GbE region Write Access */
78 		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */
79 		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */
80 	} hsf_flregacc;
81 	u16 regval;
82 };
83 
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
86 	struct ich8_pr {
87 		u32 base:13;	/* 0:12 Protected Range Base */
88 		u32 reserved1:2;	/* 13:14 Reserved */
89 		u32 rpe:1;	/* 15 Read Protection Enable */
90 		u32 limit:13;	/* 16:28 Protected Range Limit */
91 		u32 reserved2:2;	/* 29:30 Reserved */
92 		u32 wpe:1;	/* 31 Write Protection Enable */
93 	} range;
94 	u32 regval;
95 };
96 
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 						u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 					 u8 *data);
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 					 u16 *data);
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 					 u8 size, u16 *data);
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 					   u32 *data);
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 					  u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 					    u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 						 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140 
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142 {
143 	return readw(hw->flash_address + reg);
144 }
145 
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147 {
148 	return readl(hw->flash_address + reg);
149 }
150 
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152 {
153 	writew(val, hw->flash_address + reg);
154 }
155 
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157 {
158 	writel(val, hw->flash_address + reg);
159 }
160 
161 #define er16flash(reg)		__er16flash(hw, (reg))
162 #define er32flash(reg)		__er32flash(hw, (reg))
163 #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
165 
166 /**
167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168  *  @hw: pointer to the HW structure
169  *
170  *  Test access to the PHY registers by reading the PHY ID registers.  If
171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
172  *  otherwise assume the read PHY ID is correct if it is valid.
173  *
174  *  Assumes the sw/fw/hw semaphore is already acquired.
175  **/
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177 {
178 	u16 phy_reg = 0;
179 	u32 phy_id = 0;
180 	s32 ret_val = 0;
181 	u16 retry_count;
182 	u32 mac_reg = 0;
183 
184 	for (retry_count = 0; retry_count < 2; retry_count++) {
185 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 		if (ret_val || (phy_reg == 0xFFFF))
187 			continue;
188 		phy_id = (u32)(phy_reg << 16);
189 
190 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 		if (ret_val || (phy_reg == 0xFFFF)) {
192 			phy_id = 0;
193 			continue;
194 		}
195 		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 		break;
197 	}
198 
199 	if (hw->phy.id) {
200 		if (hw->phy.id == phy_id)
201 			goto out;
202 	} else if (phy_id) {
203 		hw->phy.id = phy_id;
204 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 		goto out;
206 	}
207 
208 	/* In case the PHY needs to be in mdio slow mode,
209 	 * set slow mode and try to get the PHY id again.
210 	 */
211 	if (hw->mac.type < e1000_pch_lpt) {
212 		hw->phy.ops.release(hw);
213 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 		if (!ret_val)
215 			ret_val = e1000e_get_phy_id(hw);
216 		hw->phy.ops.acquire(hw);
217 	}
218 
219 	if (ret_val)
220 		return false;
221 out:
222 	if (hw->mac.type >= e1000_pch_lpt) {
223 		/* Only unforce SMBus if ME is not active */
224 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 			/* Unforce SMBus mode in PHY */
226 			e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 			e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229 
230 			/* Unforce SMBus mode in MAC */
231 			mac_reg = er32(CTRL_EXT);
232 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 			ew32(CTRL_EXT, mac_reg);
234 		}
235 	}
236 
237 	return true;
238 }
239 
240 /**
241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242  *  @hw: pointer to the HW structure
243  *
244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245  *  used to reset the PHY to a quiescent state when necessary.
246  **/
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 {
249 	u32 mac_reg;
250 
251 	/* Set Phy Config Counter to 50msec */
252 	mac_reg = er32(FEXTNVM3);
253 	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 	ew32(FEXTNVM3, mac_reg);
256 
257 	/* Toggle LANPHYPC Value bit */
258 	mac_reg = er32(CTRL);
259 	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 	ew32(CTRL, mac_reg);
262 	e1e_flush();
263 	usleep_range(10, 20);
264 	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 	ew32(CTRL, mac_reg);
266 	e1e_flush();
267 
268 	if (hw->mac.type < e1000_pch_lpt) {
269 		msleep(50);
270 	} else {
271 		u16 count = 20;
272 
273 		do {
274 			usleep_range(5000, 6000);
275 		} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276 
277 		msleep(30);
278 	}
279 }
280 
281 /**
282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283  *  @hw: pointer to the HW structure
284  *
285  *  Workarounds/flow necessary for PHY initialization during driver load
286  *  and resume paths.
287  **/
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289 {
290 	struct e1000_adapter *adapter = hw->adapter;
291 	u32 mac_reg, fwsm = er32(FWSM);
292 	s32 ret_val;
293 
294 	/* Gate automatic PHY configuration by hardware on managed and
295 	 * non-managed 82579 and newer adapters.
296 	 */
297 	e1000_gate_hw_phy_config_ich8lan(hw, true);
298 
299 	/* It is not possible to be certain of the current state of ULP
300 	 * so forcibly disable it.
301 	 */
302 	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 	ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 	if (ret_val)
305 		e_warn("Failed to disable ULP\n");
306 
307 	ret_val = hw->phy.ops.acquire(hw);
308 	if (ret_val) {
309 		e_dbg("Failed to initialize PHY flow\n");
310 		goto out;
311 	}
312 
313 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
314 	 * inaccessible and resetting the PHY is not blocked, toggle the
315 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 	 */
317 	switch (hw->mac.type) {
318 	case e1000_pch_lpt:
319 	case e1000_pch_spt:
320 	case e1000_pch_cnp:
321 	case e1000_pch_tgp:
322 	case e1000_pch_adp:
323 	case e1000_pch_mtp:
324 	case e1000_pch_lnp:
325 		if (e1000_phy_is_accessible_pchlan(hw))
326 			break;
327 
328 		/* Before toggling LANPHYPC, see if PHY is accessible by
329 		 * forcing MAC to SMBus mode first.
330 		 */
331 		mac_reg = er32(CTRL_EXT);
332 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
333 		ew32(CTRL_EXT, mac_reg);
334 
335 		/* Wait 50 milliseconds for MAC to finish any retries
336 		 * that it might be trying to perform from previous
337 		 * attempts to acknowledge any phy read requests.
338 		 */
339 		msleep(50);
340 
341 		fallthrough;
342 	case e1000_pch2lan:
343 		if (e1000_phy_is_accessible_pchlan(hw))
344 			break;
345 
346 		fallthrough;
347 	case e1000_pchlan:
348 		if ((hw->mac.type == e1000_pchlan) &&
349 		    (fwsm & E1000_ICH_FWSM_FW_VALID))
350 			break;
351 
352 		if (hw->phy.ops.check_reset_block(hw)) {
353 			e_dbg("Required LANPHYPC toggle blocked by ME\n");
354 			ret_val = -E1000_ERR_PHY;
355 			break;
356 		}
357 
358 		/* Toggle LANPHYPC Value bit */
359 		e1000_toggle_lanphypc_pch_lpt(hw);
360 		if (hw->mac.type >= e1000_pch_lpt) {
361 			if (e1000_phy_is_accessible_pchlan(hw))
362 				break;
363 
364 			/* Toggling LANPHYPC brings the PHY out of SMBus mode
365 			 * so ensure that the MAC is also out of SMBus mode
366 			 */
367 			mac_reg = er32(CTRL_EXT);
368 			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
369 			ew32(CTRL_EXT, mac_reg);
370 
371 			if (e1000_phy_is_accessible_pchlan(hw))
372 				break;
373 
374 			ret_val = -E1000_ERR_PHY;
375 		}
376 		break;
377 	default:
378 		break;
379 	}
380 
381 	hw->phy.ops.release(hw);
382 	if (!ret_val) {
383 
384 		/* Check to see if able to reset PHY.  Print error if not */
385 		if (hw->phy.ops.check_reset_block(hw)) {
386 			e_err("Reset blocked by ME\n");
387 			goto out;
388 		}
389 
390 		/* Reset the PHY before any access to it.  Doing so, ensures
391 		 * that the PHY is in a known good state before we read/write
392 		 * PHY registers.  The generic reset is sufficient here,
393 		 * because we haven't determined the PHY type yet.
394 		 */
395 		ret_val = e1000e_phy_hw_reset_generic(hw);
396 		if (ret_val)
397 			goto out;
398 
399 		/* On a successful reset, possibly need to wait for the PHY
400 		 * to quiesce to an accessible state before returning control
401 		 * to the calling function.  If the PHY does not quiesce, then
402 		 * return E1000E_BLK_PHY_RESET, as this is the condition that
403 		 *  the PHY is in.
404 		 */
405 		ret_val = hw->phy.ops.check_reset_block(hw);
406 		if (ret_val)
407 			e_err("ME blocked access to PHY after reset\n");
408 	}
409 
410 out:
411 	/* Ungate automatic PHY configuration on non-managed 82579 */
412 	if ((hw->mac.type == e1000_pch2lan) &&
413 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
414 		usleep_range(10000, 11000);
415 		e1000_gate_hw_phy_config_ich8lan(hw, false);
416 	}
417 
418 	return ret_val;
419 }
420 
421 /**
422  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
423  *  @hw: pointer to the HW structure
424  *
425  *  Initialize family-specific PHY parameters and function pointers.
426  **/
427 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
428 {
429 	struct e1000_phy_info *phy = &hw->phy;
430 	s32 ret_val;
431 
432 	phy->addr = 1;
433 	phy->reset_delay_us = 100;
434 
435 	phy->ops.set_page = e1000_set_page_igp;
436 	phy->ops.read_reg = e1000_read_phy_reg_hv;
437 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
438 	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
439 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
440 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
441 	phy->ops.write_reg = e1000_write_phy_reg_hv;
442 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
443 	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
444 	phy->ops.power_up = e1000_power_up_phy_copper;
445 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
446 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
447 
448 	phy->id = e1000_phy_unknown;
449 
450 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
451 	if (ret_val)
452 		return ret_val;
453 
454 	if (phy->id == e1000_phy_unknown)
455 		switch (hw->mac.type) {
456 		default:
457 			ret_val = e1000e_get_phy_id(hw);
458 			if (ret_val)
459 				return ret_val;
460 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
461 				break;
462 			fallthrough;
463 		case e1000_pch2lan:
464 		case e1000_pch_lpt:
465 		case e1000_pch_spt:
466 		case e1000_pch_cnp:
467 		case e1000_pch_tgp:
468 		case e1000_pch_adp:
469 		case e1000_pch_mtp:
470 		case e1000_pch_lnp:
471 			/* In case the PHY needs to be in mdio slow mode,
472 			 * set slow mode and try to get the PHY id again.
473 			 */
474 			ret_val = e1000_set_mdio_slow_mode_hv(hw);
475 			if (ret_val)
476 				return ret_val;
477 			ret_val = e1000e_get_phy_id(hw);
478 			if (ret_val)
479 				return ret_val;
480 			break;
481 		}
482 	phy->type = e1000e_get_phy_type_from_id(phy->id);
483 
484 	switch (phy->type) {
485 	case e1000_phy_82577:
486 	case e1000_phy_82579:
487 	case e1000_phy_i217:
488 		phy->ops.check_polarity = e1000_check_polarity_82577;
489 		phy->ops.force_speed_duplex =
490 		    e1000_phy_force_speed_duplex_82577;
491 		phy->ops.get_cable_length = e1000_get_cable_length_82577;
492 		phy->ops.get_info = e1000_get_phy_info_82577;
493 		phy->ops.commit = e1000e_phy_sw_reset;
494 		break;
495 	case e1000_phy_82578:
496 		phy->ops.check_polarity = e1000_check_polarity_m88;
497 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
498 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;
499 		phy->ops.get_info = e1000e_get_phy_info_m88;
500 		break;
501 	default:
502 		ret_val = -E1000_ERR_PHY;
503 		break;
504 	}
505 
506 	return ret_val;
507 }
508 
509 /**
510  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
511  *  @hw: pointer to the HW structure
512  *
513  *  Initialize family-specific PHY parameters and function pointers.
514  **/
515 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
516 {
517 	struct e1000_phy_info *phy = &hw->phy;
518 	s32 ret_val;
519 	u16 i = 0;
520 
521 	phy->addr = 1;
522 	phy->reset_delay_us = 100;
523 
524 	phy->ops.power_up = e1000_power_up_phy_copper;
525 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
526 
527 	/* We may need to do this twice - once for IGP and if that fails,
528 	 * we'll set BM func pointers and try again
529 	 */
530 	ret_val = e1000e_determine_phy_address(hw);
531 	if (ret_val) {
532 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
533 		phy->ops.read_reg = e1000e_read_phy_reg_bm;
534 		ret_val = e1000e_determine_phy_address(hw);
535 		if (ret_val) {
536 			e_dbg("Cannot determine PHY addr. Erroring out\n");
537 			return ret_val;
538 		}
539 	}
540 
541 	phy->id = 0;
542 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
543 	       (i++ < 100)) {
544 		usleep_range(1000, 1100);
545 		ret_val = e1000e_get_phy_id(hw);
546 		if (ret_val)
547 			return ret_val;
548 	}
549 
550 	/* Verify phy id */
551 	switch (phy->id) {
552 	case IGP03E1000_E_PHY_ID:
553 		phy->type = e1000_phy_igp_3;
554 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
555 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
556 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
557 		phy->ops.get_info = e1000e_get_phy_info_igp;
558 		phy->ops.check_polarity = e1000_check_polarity_igp;
559 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
560 		break;
561 	case IFE_E_PHY_ID:
562 	case IFE_PLUS_E_PHY_ID:
563 	case IFE_C_E_PHY_ID:
564 		phy->type = e1000_phy_ife;
565 		phy->autoneg_mask = E1000_ALL_NOT_GIG;
566 		phy->ops.get_info = e1000_get_phy_info_ife;
567 		phy->ops.check_polarity = e1000_check_polarity_ife;
568 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
569 		break;
570 	case BME1000_E_PHY_ID:
571 		phy->type = e1000_phy_bm;
572 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
573 		phy->ops.read_reg = e1000e_read_phy_reg_bm;
574 		phy->ops.write_reg = e1000e_write_phy_reg_bm;
575 		phy->ops.commit = e1000e_phy_sw_reset;
576 		phy->ops.get_info = e1000e_get_phy_info_m88;
577 		phy->ops.check_polarity = e1000_check_polarity_m88;
578 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
579 		break;
580 	default:
581 		return -E1000_ERR_PHY;
582 	}
583 
584 	return 0;
585 }
586 
587 /**
588  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
589  *  @hw: pointer to the HW structure
590  *
591  *  Initialize family-specific NVM parameters and function
592  *  pointers.
593  **/
594 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
595 {
596 	struct e1000_nvm_info *nvm = &hw->nvm;
597 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
598 	u32 gfpreg, sector_base_addr, sector_end_addr;
599 	u16 i;
600 	u32 nvm_size;
601 
602 	nvm->type = e1000_nvm_flash_sw;
603 
604 	if (hw->mac.type >= e1000_pch_spt) {
605 		/* in SPT, gfpreg doesn't exist. NVM size is taken from the
606 		 * STRAP register. This is because in SPT the GbE Flash region
607 		 * is no longer accessed through the flash registers. Instead,
608 		 * the mechanism has changed, and the Flash region access
609 		 * registers are now implemented in GbE memory space.
610 		 */
611 		nvm->flash_base_addr = 0;
612 		nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
613 		    * NVM_SIZE_MULTIPLIER;
614 		nvm->flash_bank_size = nvm_size / 2;
615 		/* Adjust to word count */
616 		nvm->flash_bank_size /= sizeof(u16);
617 		/* Set the base address for flash register access */
618 		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
619 	} else {
620 		/* Can't read flash registers if register set isn't mapped. */
621 		if (!hw->flash_address) {
622 			e_dbg("ERROR: Flash registers not mapped\n");
623 			return -E1000_ERR_CONFIG;
624 		}
625 
626 		gfpreg = er32flash(ICH_FLASH_GFPREG);
627 
628 		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
629 		 * Add 1 to sector_end_addr since this sector is included in
630 		 * the overall size.
631 		 */
632 		sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
633 		sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
634 
635 		/* flash_base_addr is byte-aligned */
636 		nvm->flash_base_addr = sector_base_addr
637 		    << FLASH_SECTOR_ADDR_SHIFT;
638 
639 		/* find total size of the NVM, then cut in half since the total
640 		 * size represents two separate NVM banks.
641 		 */
642 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
643 					<< FLASH_SECTOR_ADDR_SHIFT);
644 		nvm->flash_bank_size /= 2;
645 		/* Adjust to word count */
646 		nvm->flash_bank_size /= sizeof(u16);
647 	}
648 
649 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
650 
651 	/* Clear shadow ram */
652 	for (i = 0; i < nvm->word_size; i++) {
653 		dev_spec->shadow_ram[i].modified = false;
654 		dev_spec->shadow_ram[i].value = 0xFFFF;
655 	}
656 
657 	return 0;
658 }
659 
660 /**
661  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
662  *  @hw: pointer to the HW structure
663  *
664  *  Initialize family-specific MAC parameters and function
665  *  pointers.
666  **/
667 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
668 {
669 	struct e1000_mac_info *mac = &hw->mac;
670 
671 	/* Set media type function pointer */
672 	hw->phy.media_type = e1000_media_type_copper;
673 
674 	/* Set mta register count */
675 	mac->mta_reg_count = 32;
676 	/* Set rar entry count */
677 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
678 	if (mac->type == e1000_ich8lan)
679 		mac->rar_entry_count--;
680 	/* FWSM register */
681 	mac->has_fwsm = true;
682 	/* ARC subsystem not supported */
683 	mac->arc_subsystem_valid = false;
684 	/* Adaptive IFS supported */
685 	mac->adaptive_ifs = true;
686 
687 	/* LED and other operations */
688 	switch (mac->type) {
689 	case e1000_ich8lan:
690 	case e1000_ich9lan:
691 	case e1000_ich10lan:
692 		/* check management mode */
693 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
694 		/* ID LED init */
695 		mac->ops.id_led_init = e1000e_id_led_init_generic;
696 		/* blink LED */
697 		mac->ops.blink_led = e1000e_blink_led_generic;
698 		/* setup LED */
699 		mac->ops.setup_led = e1000e_setup_led_generic;
700 		/* cleanup LED */
701 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
702 		/* turn on/off LED */
703 		mac->ops.led_on = e1000_led_on_ich8lan;
704 		mac->ops.led_off = e1000_led_off_ich8lan;
705 		break;
706 	case e1000_pch2lan:
707 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
708 		mac->ops.rar_set = e1000_rar_set_pch2lan;
709 		fallthrough;
710 	case e1000_pch_lpt:
711 	case e1000_pch_spt:
712 	case e1000_pch_cnp:
713 	case e1000_pch_tgp:
714 	case e1000_pch_adp:
715 	case e1000_pch_mtp:
716 	case e1000_pch_lnp:
717 	case e1000_pchlan:
718 		/* check management mode */
719 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
720 		/* ID LED init */
721 		mac->ops.id_led_init = e1000_id_led_init_pchlan;
722 		/* setup LED */
723 		mac->ops.setup_led = e1000_setup_led_pchlan;
724 		/* cleanup LED */
725 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
726 		/* turn on/off LED */
727 		mac->ops.led_on = e1000_led_on_pchlan;
728 		mac->ops.led_off = e1000_led_off_pchlan;
729 		break;
730 	default:
731 		break;
732 	}
733 
734 	if (mac->type >= e1000_pch_lpt) {
735 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
736 		mac->ops.rar_set = e1000_rar_set_pch_lpt;
737 		mac->ops.setup_physical_interface =
738 		    e1000_setup_copper_link_pch_lpt;
739 		mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
740 	}
741 
742 	/* Enable PCS Lock-loss workaround for ICH8 */
743 	if (mac->type == e1000_ich8lan)
744 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
745 
746 	return 0;
747 }
748 
749 /**
750  *  __e1000_access_emi_reg_locked - Read/write EMI register
751  *  @hw: pointer to the HW structure
752  *  @address: EMI address to program
753  *  @data: pointer to value to read/write from/to the EMI address
754  *  @read: boolean flag to indicate read or write
755  *
756  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
757  **/
758 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
759 					 u16 *data, bool read)
760 {
761 	s32 ret_val;
762 
763 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
764 	if (ret_val)
765 		return ret_val;
766 
767 	if (read)
768 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
769 	else
770 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
771 
772 	return ret_val;
773 }
774 
775 /**
776  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
777  *  @hw: pointer to the HW structure
778  *  @addr: EMI address to program
779  *  @data: value to be read from the EMI address
780  *
781  *  Assumes the SW/FW/HW Semaphore is already acquired.
782  **/
783 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
784 {
785 	return __e1000_access_emi_reg_locked(hw, addr, data, true);
786 }
787 
788 /**
789  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
790  *  @hw: pointer to the HW structure
791  *  @addr: EMI address to program
792  *  @data: value to be written to the EMI address
793  *
794  *  Assumes the SW/FW/HW Semaphore is already acquired.
795  **/
796 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
797 {
798 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);
799 }
800 
801 /**
802  *  e1000_set_eee_pchlan - Enable/disable EEE support
803  *  @hw: pointer to the HW structure
804  *
805  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
806  *  the link and the EEE capabilities of the link partner.  The LPI Control
807  *  register bits will remain set only if/when link is up.
808  *
809  *  EEE LPI must not be asserted earlier than one second after link is up.
810  *  On 82579, EEE LPI should not be enabled until such time otherwise there
811  *  can be link issues with some switches.  Other devices can have EEE LPI
812  *  enabled immediately upon link up since they have a timer in hardware which
813  *  prevents LPI from being asserted too early.
814  **/
815 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
816 {
817 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
818 	s32 ret_val;
819 	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
820 
821 	switch (hw->phy.type) {
822 	case e1000_phy_82579:
823 		lpa = I82579_EEE_LP_ABILITY;
824 		pcs_status = I82579_EEE_PCS_STATUS;
825 		adv_addr = I82579_EEE_ADVERTISEMENT;
826 		break;
827 	case e1000_phy_i217:
828 		lpa = I217_EEE_LP_ABILITY;
829 		pcs_status = I217_EEE_PCS_STATUS;
830 		adv_addr = I217_EEE_ADVERTISEMENT;
831 		break;
832 	default:
833 		return 0;
834 	}
835 
836 	ret_val = hw->phy.ops.acquire(hw);
837 	if (ret_val)
838 		return ret_val;
839 
840 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
841 	if (ret_val)
842 		goto release;
843 
844 	/* Clear bits that enable EEE in various speeds */
845 	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
846 
847 	/* Enable EEE if not disabled by user */
848 	if (!dev_spec->eee_disable) {
849 		/* Save off link partner's EEE ability */
850 		ret_val = e1000_read_emi_reg_locked(hw, lpa,
851 						    &dev_spec->eee_lp_ability);
852 		if (ret_val)
853 			goto release;
854 
855 		/* Read EEE advertisement */
856 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
857 		if (ret_val)
858 			goto release;
859 
860 		/* Enable EEE only for speeds in which the link partner is
861 		 * EEE capable and for which we advertise EEE.
862 		 */
863 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
864 			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
865 
866 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
867 			e1e_rphy_locked(hw, MII_LPA, &data);
868 			if (data & LPA_100FULL)
869 				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
870 			else
871 				/* EEE is not supported in 100Half, so ignore
872 				 * partner's EEE in 100 ability if full-duplex
873 				 * is not advertised.
874 				 */
875 				dev_spec->eee_lp_ability &=
876 				    ~I82579_EEE_100_SUPPORTED;
877 		}
878 	}
879 
880 	if (hw->phy.type == e1000_phy_82579) {
881 		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
882 						    &data);
883 		if (ret_val)
884 			goto release;
885 
886 		data &= ~I82579_LPI_100_PLL_SHUT;
887 		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
888 						     data);
889 	}
890 
891 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
892 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
893 	if (ret_val)
894 		goto release;
895 
896 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
897 release:
898 	hw->phy.ops.release(hw);
899 
900 	return ret_val;
901 }
902 
903 /**
904  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
905  *  @hw:   pointer to the HW structure
906  *  @link: link up bool flag
907  *
908  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
909  *  preventing further DMA write requests.  Workaround the issue by disabling
910  *  the de-assertion of the clock request when in 1Gpbs mode.
911  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
912  *  speeds in order to avoid Tx hangs.
913  **/
914 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
915 {
916 	u32 fextnvm6 = er32(FEXTNVM6);
917 	u32 status = er32(STATUS);
918 	s32 ret_val = 0;
919 	u16 reg;
920 
921 	if (link && (status & E1000_STATUS_SPEED_1000)) {
922 		ret_val = hw->phy.ops.acquire(hw);
923 		if (ret_val)
924 			return ret_val;
925 
926 		ret_val =
927 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
928 						&reg);
929 		if (ret_val)
930 			goto release;
931 
932 		ret_val =
933 		    e1000e_write_kmrn_reg_locked(hw,
934 						 E1000_KMRNCTRLSTA_K1_CONFIG,
935 						 reg &
936 						 ~E1000_KMRNCTRLSTA_K1_ENABLE);
937 		if (ret_val)
938 			goto release;
939 
940 		usleep_range(10, 20);
941 
942 		ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
943 
944 		ret_val =
945 		    e1000e_write_kmrn_reg_locked(hw,
946 						 E1000_KMRNCTRLSTA_K1_CONFIG,
947 						 reg);
948 release:
949 		hw->phy.ops.release(hw);
950 	} else {
951 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
952 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
953 
954 		if ((hw->phy.revision > 5) || !link ||
955 		    ((status & E1000_STATUS_SPEED_100) &&
956 		     (status & E1000_STATUS_FD)))
957 			goto update_fextnvm6;
958 
959 		ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
960 		if (ret_val)
961 			return ret_val;
962 
963 		/* Clear link status transmit timeout */
964 		reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
965 
966 		if (status & E1000_STATUS_SPEED_100) {
967 			/* Set inband Tx timeout to 5x10us for 100Half */
968 			reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
969 
970 			/* Do not extend the K1 entry latency for 100Half */
971 			fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
972 		} else {
973 			/* Set inband Tx timeout to 50x10us for 10Full/Half */
974 			reg |= 50 <<
975 			    I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
976 
977 			/* Extend the K1 entry latency for 10 Mbps */
978 			fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
979 		}
980 
981 		ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
982 		if (ret_val)
983 			return ret_val;
984 
985 update_fextnvm6:
986 		ew32(FEXTNVM6, fextnvm6);
987 	}
988 
989 	return ret_val;
990 }
991 
992 /**
993  *  e1000_platform_pm_pch_lpt - Set platform power management values
994  *  @hw: pointer to the HW structure
995  *  @link: bool indicating link status
996  *
997  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
998  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
999  *  when link is up (which must not exceed the maximum latency supported
1000  *  by the platform), otherwise specify there is no LTR requirement.
1001  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1002  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1003  *  Capability register set, on this device LTR is set by writing the
1004  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1005  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1006  *  message to the PMC.
1007  **/
1008 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1009 {
1010 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1011 	    link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1012 	u16 max_ltr_enc_d = 0;	/* maximum LTR decoded by platform */
1013 	u16 lat_enc_d = 0;	/* latency decoded */
1014 	u16 lat_enc = 0;	/* latency encoded */
1015 
1016 	if (link) {
1017 		u16 speed, duplex, scale = 0;
1018 		u16 max_snoop, max_nosnoop;
1019 		u16 max_ltr_enc;	/* max LTR latency encoded */
1020 		u64 value;
1021 		u32 rxa;
1022 
1023 		if (!hw->adapter->max_frame_size) {
1024 			e_dbg("max_frame_size not set.\n");
1025 			return -E1000_ERR_CONFIG;
1026 		}
1027 
1028 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1029 		if (!speed) {
1030 			e_dbg("Speed not set.\n");
1031 			return -E1000_ERR_CONFIG;
1032 		}
1033 
1034 		/* Rx Packet Buffer Allocation size (KB) */
1035 		rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1036 
1037 		/* Determine the maximum latency tolerated by the device.
1038 		 *
1039 		 * Per the PCIe spec, the tolerated latencies are encoded as
1040 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1041 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
1042 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1043 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1044 		 */
1045 		rxa *= 512;
1046 		value = (rxa > hw->adapter->max_frame_size) ?
1047 			(rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1048 			0;
1049 
1050 		while (value > PCI_LTR_VALUE_MASK) {
1051 			scale++;
1052 			value = DIV_ROUND_UP(value, BIT(5));
1053 		}
1054 		if (scale > E1000_LTRV_SCALE_MAX) {
1055 			e_dbg("Invalid LTR latency scale %d\n", scale);
1056 			return -E1000_ERR_CONFIG;
1057 		}
1058 		lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1059 
1060 		/* Determine the maximum latency tolerated by the platform */
1061 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1062 				     &max_snoop);
1063 		pci_read_config_word(hw->adapter->pdev,
1064 				     E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1065 		max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1066 
1067 		lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1068 			     (1U << (E1000_LTRV_SCALE_FACTOR *
1069 			     ((lat_enc & E1000_LTRV_SCALE_MASK)
1070 			     >> E1000_LTRV_SCALE_SHIFT)));
1071 
1072 		max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1073 				 (1U << (E1000_LTRV_SCALE_FACTOR *
1074 				 ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1075 				 >> E1000_LTRV_SCALE_SHIFT)));
1076 
1077 		if (lat_enc_d > max_ltr_enc_d)
1078 			lat_enc = max_ltr_enc;
1079 	}
1080 
1081 	/* Set Snoop and No-Snoop latencies the same */
1082 	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1083 	ew32(LTRV, reg);
1084 
1085 	return 0;
1086 }
1087 
1088 /**
1089  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1090  *  @hw: pointer to the HW structure
1091  *  @to_sx: boolean indicating a system power state transition to Sx
1092  *
1093  *  When link is down, configure ULP mode to significantly reduce the power
1094  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1095  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1096  *  system, configure the ULP mode by software.
1097  */
1098 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1099 {
1100 	u32 mac_reg;
1101 	s32 ret_val = 0;
1102 	u16 phy_reg;
1103 	u16 oem_reg = 0;
1104 
1105 	if ((hw->mac.type < e1000_pch_lpt) ||
1106 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1107 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1108 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1109 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1110 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1111 		return 0;
1112 
1113 	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1114 		/* Request ME configure ULP mode in the PHY */
1115 		mac_reg = er32(H2ME);
1116 		mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1117 		ew32(H2ME, mac_reg);
1118 
1119 		goto out;
1120 	}
1121 
1122 	if (!to_sx) {
1123 		int i = 0;
1124 
1125 		/* Poll up to 5 seconds for Cable Disconnected indication */
1126 		while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1127 			/* Bail if link is re-acquired */
1128 			if (er32(STATUS) & E1000_STATUS_LU)
1129 				return -E1000_ERR_PHY;
1130 
1131 			if (i++ == 100)
1132 				break;
1133 
1134 			msleep(50);
1135 		}
1136 		e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1137 		      (er32(FEXT) &
1138 		       E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1139 	}
1140 
1141 	ret_val = hw->phy.ops.acquire(hw);
1142 	if (ret_val)
1143 		goto out;
1144 
1145 	/* Force SMBus mode in PHY */
1146 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1147 	if (ret_val)
1148 		goto release;
1149 	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1150 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1151 
1152 	/* Force SMBus mode in MAC */
1153 	mac_reg = er32(CTRL_EXT);
1154 	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1155 	ew32(CTRL_EXT, mac_reg);
1156 
1157 	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1158 	 * LPLU and disable Gig speed when entering ULP
1159 	 */
1160 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1161 		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1162 						       &oem_reg);
1163 		if (ret_val)
1164 			goto release;
1165 
1166 		phy_reg = oem_reg;
1167 		phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1168 
1169 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1170 							phy_reg);
1171 
1172 		if (ret_val)
1173 			goto release;
1174 	}
1175 
1176 	/* Set Inband ULP Exit, Reset to SMBus mode and
1177 	 * Disable SMBus Release on PERST# in PHY
1178 	 */
1179 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1180 	if (ret_val)
1181 		goto release;
1182 	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1183 		    I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1184 	if (to_sx) {
1185 		if (er32(WUFC) & E1000_WUFC_LNKC)
1186 			phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1187 		else
1188 			phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1189 
1190 		phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1191 		phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1192 	} else {
1193 		phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1194 		phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1195 		phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1196 	}
1197 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1198 
1199 	/* Set Disable SMBus Release on PERST# in MAC */
1200 	mac_reg = er32(FEXTNVM7);
1201 	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1202 	ew32(FEXTNVM7, mac_reg);
1203 
1204 	/* Commit ULP changes in PHY by starting auto ULP configuration */
1205 	phy_reg |= I218_ULP_CONFIG1_START;
1206 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1207 
1208 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1209 	    to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1210 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1211 							oem_reg);
1212 		if (ret_val)
1213 			goto release;
1214 	}
1215 
1216 release:
1217 	hw->phy.ops.release(hw);
1218 out:
1219 	if (ret_val)
1220 		e_dbg("Error in ULP enable flow: %d\n", ret_val);
1221 	else
1222 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1223 
1224 	return ret_val;
1225 }
1226 
1227 /**
1228  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1229  *  @hw: pointer to the HW structure
1230  *  @force: boolean indicating whether or not to force disabling ULP
1231  *
1232  *  Un-configure ULP mode when link is up, the system is transitioned from
1233  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1234  *  system, poll for an indication from ME that ULP has been un-configured.
1235  *  If not on an ME enabled system, un-configure the ULP mode by software.
1236  *
1237  *  During nominal operation, this function is called when link is acquired
1238  *  to disable ULP mode (force=false); otherwise, for example when unloading
1239  *  the driver or during Sx->S0 transitions, this is called with force=true
1240  *  to forcibly disable ULP.
1241  */
1242 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1243 {
1244 	s32 ret_val = 0;
1245 	u32 mac_reg;
1246 	u16 phy_reg;
1247 	int i = 0;
1248 
1249 	if ((hw->mac.type < e1000_pch_lpt) ||
1250 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1251 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1252 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1253 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1254 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1255 		return 0;
1256 
1257 	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1258 		struct e1000_adapter *adapter = hw->adapter;
1259 		bool firmware_bug = false;
1260 
1261 		if (force) {
1262 			/* Request ME un-configure ULP mode in the PHY */
1263 			mac_reg = er32(H2ME);
1264 			mac_reg &= ~E1000_H2ME_ULP;
1265 			mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1266 			ew32(H2ME, mac_reg);
1267 		}
1268 
1269 		/* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1270 		 * If this takes more than 1 second, show a warning indicating a
1271 		 * firmware bug
1272 		 */
1273 		while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1274 			if (i++ == 250) {
1275 				ret_val = -E1000_ERR_PHY;
1276 				goto out;
1277 			}
1278 			if (i > 100 && !firmware_bug)
1279 				firmware_bug = true;
1280 
1281 			usleep_range(10000, 11000);
1282 		}
1283 		if (firmware_bug)
1284 			e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1285 			       i * 10);
1286 		else
1287 			e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1288 			      i * 10);
1289 
1290 		if (force) {
1291 			mac_reg = er32(H2ME);
1292 			mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1293 			ew32(H2ME, mac_reg);
1294 		} else {
1295 			/* Clear H2ME.ULP after ME ULP configuration */
1296 			mac_reg = er32(H2ME);
1297 			mac_reg &= ~E1000_H2ME_ULP;
1298 			ew32(H2ME, mac_reg);
1299 		}
1300 
1301 		goto out;
1302 	}
1303 
1304 	ret_val = hw->phy.ops.acquire(hw);
1305 	if (ret_val)
1306 		goto out;
1307 
1308 	if (force)
1309 		/* Toggle LANPHYPC Value bit */
1310 		e1000_toggle_lanphypc_pch_lpt(hw);
1311 
1312 	/* Unforce SMBus mode in PHY */
1313 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1314 	if (ret_val) {
1315 		/* The MAC might be in PCIe mode, so temporarily force to
1316 		 * SMBus mode in order to access the PHY.
1317 		 */
1318 		mac_reg = er32(CTRL_EXT);
1319 		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1320 		ew32(CTRL_EXT, mac_reg);
1321 
1322 		msleep(50);
1323 
1324 		ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1325 						       &phy_reg);
1326 		if (ret_val)
1327 			goto release;
1328 	}
1329 	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1330 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1331 
1332 	/* Unforce SMBus mode in MAC */
1333 	mac_reg = er32(CTRL_EXT);
1334 	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1335 	ew32(CTRL_EXT, mac_reg);
1336 
1337 	/* When ULP mode was previously entered, K1 was disabled by the
1338 	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1339 	 */
1340 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1341 	if (ret_val)
1342 		goto release;
1343 	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1344 	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1345 
1346 	/* Clear ULP enabled configuration */
1347 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1348 	if (ret_val)
1349 		goto release;
1350 	phy_reg &= ~(I218_ULP_CONFIG1_IND |
1351 		     I218_ULP_CONFIG1_STICKY_ULP |
1352 		     I218_ULP_CONFIG1_RESET_TO_SMBUS |
1353 		     I218_ULP_CONFIG1_WOL_HOST |
1354 		     I218_ULP_CONFIG1_INBAND_EXIT |
1355 		     I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1356 		     I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1357 		     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1358 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1359 
1360 	/* Commit ULP changes by starting auto ULP configuration */
1361 	phy_reg |= I218_ULP_CONFIG1_START;
1362 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1363 
1364 	/* Clear Disable SMBus Release on PERST# in MAC */
1365 	mac_reg = er32(FEXTNVM7);
1366 	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1367 	ew32(FEXTNVM7, mac_reg);
1368 
1369 release:
1370 	hw->phy.ops.release(hw);
1371 	if (force) {
1372 		e1000_phy_hw_reset(hw);
1373 		msleep(50);
1374 	}
1375 out:
1376 	if (ret_val)
1377 		e_dbg("Error in ULP disable flow: %d\n", ret_val);
1378 	else
1379 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1380 
1381 	return ret_val;
1382 }
1383 
1384 /**
1385  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1386  *  @hw: pointer to the HW structure
1387  *
1388  *  Checks to see of the link status of the hardware has changed.  If a
1389  *  change in link status has been detected, then we read the PHY registers
1390  *  to get the current speed/duplex if link exists.
1391  **/
1392 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1393 {
1394 	struct e1000_mac_info *mac = &hw->mac;
1395 	s32 ret_val, tipg_reg = 0;
1396 	u16 emi_addr, emi_val = 0;
1397 	bool link;
1398 	u16 phy_reg;
1399 
1400 	/* We only want to go out to the PHY registers to see if Auto-Neg
1401 	 * has completed and/or if our link status has changed.  The
1402 	 * get_link_status flag is set upon receiving a Link Status
1403 	 * Change or Rx Sequence Error interrupt.
1404 	 */
1405 	if (!mac->get_link_status)
1406 		return 0;
1407 	mac->get_link_status = false;
1408 
1409 	/* First we want to see if the MII Status Register reports
1410 	 * link.  If so, then we want to get the current speed/duplex
1411 	 * of the PHY.
1412 	 */
1413 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1414 	if (ret_val)
1415 		goto out;
1416 
1417 	if (hw->mac.type == e1000_pchlan) {
1418 		ret_val = e1000_k1_gig_workaround_hv(hw, link);
1419 		if (ret_val)
1420 			goto out;
1421 	}
1422 
1423 	/* When connected at 10Mbps half-duplex, some parts are excessively
1424 	 * aggressive resulting in many collisions. To avoid this, increase
1425 	 * the IPG and reduce Rx latency in the PHY.
1426 	 */
1427 	if ((hw->mac.type >= e1000_pch2lan) && link) {
1428 		u16 speed, duplex;
1429 
1430 		e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1431 		tipg_reg = er32(TIPG);
1432 		tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1433 
1434 		if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1435 			tipg_reg |= 0xFF;
1436 			/* Reduce Rx latency in analog PHY */
1437 			emi_val = 0;
1438 		} else if (hw->mac.type >= e1000_pch_spt &&
1439 			   duplex == FULL_DUPLEX && speed != SPEED_1000) {
1440 			tipg_reg |= 0xC;
1441 			emi_val = 1;
1442 		} else {
1443 
1444 			/* Roll back the default values */
1445 			tipg_reg |= 0x08;
1446 			emi_val = 1;
1447 		}
1448 
1449 		ew32(TIPG, tipg_reg);
1450 
1451 		ret_val = hw->phy.ops.acquire(hw);
1452 		if (ret_val)
1453 			goto out;
1454 
1455 		if (hw->mac.type == e1000_pch2lan)
1456 			emi_addr = I82579_RX_CONFIG;
1457 		else
1458 			emi_addr = I217_RX_CONFIG;
1459 		ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1460 
1461 		if (hw->mac.type >= e1000_pch_lpt) {
1462 			u16 phy_reg;
1463 
1464 			e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1465 			phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1466 			if (speed == SPEED_100 || speed == SPEED_10)
1467 				phy_reg |= 0x3E8;
1468 			else
1469 				phy_reg |= 0xFA;
1470 			e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1471 
1472 			if (speed == SPEED_1000) {
1473 				hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1474 							    &phy_reg);
1475 
1476 				phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1477 
1478 				hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1479 							     phy_reg);
1480 			}
1481 		}
1482 		hw->phy.ops.release(hw);
1483 
1484 		if (ret_val)
1485 			goto out;
1486 
1487 		if (hw->mac.type >= e1000_pch_spt) {
1488 			u16 data;
1489 			u16 ptr_gap;
1490 
1491 			if (speed == SPEED_1000) {
1492 				ret_val = hw->phy.ops.acquire(hw);
1493 				if (ret_val)
1494 					goto out;
1495 
1496 				ret_val = e1e_rphy_locked(hw,
1497 							  PHY_REG(776, 20),
1498 							  &data);
1499 				if (ret_val) {
1500 					hw->phy.ops.release(hw);
1501 					goto out;
1502 				}
1503 
1504 				ptr_gap = (data & (0x3FF << 2)) >> 2;
1505 				if (ptr_gap < 0x18) {
1506 					data &= ~(0x3FF << 2);
1507 					data |= (0x18 << 2);
1508 					ret_val =
1509 					    e1e_wphy_locked(hw,
1510 							    PHY_REG(776, 20),
1511 							    data);
1512 				}
1513 				hw->phy.ops.release(hw);
1514 				if (ret_val)
1515 					goto out;
1516 			} else {
1517 				ret_val = hw->phy.ops.acquire(hw);
1518 				if (ret_val)
1519 					goto out;
1520 
1521 				ret_val = e1e_wphy_locked(hw,
1522 							  PHY_REG(776, 20),
1523 							  0xC023);
1524 				hw->phy.ops.release(hw);
1525 				if (ret_val)
1526 					goto out;
1527 
1528 			}
1529 		}
1530 	}
1531 
1532 	/* I217 Packet Loss issue:
1533 	 * ensure that FEXTNVM4 Beacon Duration is set correctly
1534 	 * on power up.
1535 	 * Set the Beacon Duration for I217 to 8 usec
1536 	 */
1537 	if (hw->mac.type >= e1000_pch_lpt) {
1538 		u32 mac_reg;
1539 
1540 		mac_reg = er32(FEXTNVM4);
1541 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1542 		mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1543 		ew32(FEXTNVM4, mac_reg);
1544 	}
1545 
1546 	/* Work-around I218 hang issue */
1547 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1548 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1549 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1550 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1551 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1552 		if (ret_val)
1553 			goto out;
1554 	}
1555 	if (hw->mac.type >= e1000_pch_lpt) {
1556 		/* Set platform power management values for
1557 		 * Latency Tolerance Reporting (LTR)
1558 		 */
1559 		ret_val = e1000_platform_pm_pch_lpt(hw, link);
1560 		if (ret_val)
1561 			goto out;
1562 	}
1563 
1564 	/* Clear link partner's EEE ability */
1565 	hw->dev_spec.ich8lan.eee_lp_ability = 0;
1566 
1567 	if (hw->mac.type >= e1000_pch_lpt) {
1568 		u32 fextnvm6 = er32(FEXTNVM6);
1569 
1570 		if (hw->mac.type == e1000_pch_spt) {
1571 			/* FEXTNVM6 K1-off workaround - for SPT only */
1572 			u32 pcieanacfg = er32(PCIEANACFG);
1573 
1574 			if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1575 				fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1576 			else
1577 				fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1578 		}
1579 
1580 		ew32(FEXTNVM6, fextnvm6);
1581 	}
1582 
1583 	if (!link)
1584 		goto out;
1585 
1586 	switch (hw->mac.type) {
1587 	case e1000_pch2lan:
1588 		ret_val = e1000_k1_workaround_lv(hw);
1589 		if (ret_val)
1590 			return ret_val;
1591 		fallthrough;
1592 	case e1000_pchlan:
1593 		if (hw->phy.type == e1000_phy_82578) {
1594 			ret_val = e1000_link_stall_workaround_hv(hw);
1595 			if (ret_val)
1596 				return ret_val;
1597 		}
1598 
1599 		/* Workaround for PCHx parts in half-duplex:
1600 		 * Set the number of preambles removed from the packet
1601 		 * when it is passed from the PHY to the MAC to prevent
1602 		 * the MAC from misinterpreting the packet type.
1603 		 */
1604 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1605 		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1606 
1607 		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1608 			phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1609 
1610 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1611 		break;
1612 	default:
1613 		break;
1614 	}
1615 
1616 	/* Check if there was DownShift, must be checked
1617 	 * immediately after link-up
1618 	 */
1619 	e1000e_check_downshift(hw);
1620 
1621 	/* Enable/Disable EEE after link up */
1622 	if (hw->phy.type > e1000_phy_82579) {
1623 		ret_val = e1000_set_eee_pchlan(hw);
1624 		if (ret_val)
1625 			return ret_val;
1626 	}
1627 
1628 	/* If we are forcing speed/duplex, then we simply return since
1629 	 * we have already determined whether we have link or not.
1630 	 */
1631 	if (!mac->autoneg)
1632 		return -E1000_ERR_CONFIG;
1633 
1634 	/* Auto-Neg is enabled.  Auto Speed Detection takes care
1635 	 * of MAC speed/duplex configuration.  So we only need to
1636 	 * configure Collision Distance in the MAC.
1637 	 */
1638 	mac->ops.config_collision_dist(hw);
1639 
1640 	/* Configure Flow Control now that Auto-Neg has completed.
1641 	 * First, we need to restore the desired flow control
1642 	 * settings because we may have had to re-autoneg with a
1643 	 * different link partner.
1644 	 */
1645 	ret_val = e1000e_config_fc_after_link_up(hw);
1646 	if (ret_val)
1647 		e_dbg("Error configuring flow control\n");
1648 
1649 	return ret_val;
1650 
1651 out:
1652 	mac->get_link_status = true;
1653 	return ret_val;
1654 }
1655 
1656 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1657 {
1658 	struct e1000_hw *hw = &adapter->hw;
1659 	s32 rc;
1660 
1661 	rc = e1000_init_mac_params_ich8lan(hw);
1662 	if (rc)
1663 		return rc;
1664 
1665 	rc = e1000_init_nvm_params_ich8lan(hw);
1666 	if (rc)
1667 		return rc;
1668 
1669 	switch (hw->mac.type) {
1670 	case e1000_ich8lan:
1671 	case e1000_ich9lan:
1672 	case e1000_ich10lan:
1673 		rc = e1000_init_phy_params_ich8lan(hw);
1674 		break;
1675 	case e1000_pchlan:
1676 	case e1000_pch2lan:
1677 	case e1000_pch_lpt:
1678 	case e1000_pch_spt:
1679 	case e1000_pch_cnp:
1680 	case e1000_pch_tgp:
1681 	case e1000_pch_adp:
1682 	case e1000_pch_mtp:
1683 	case e1000_pch_lnp:
1684 		rc = e1000_init_phy_params_pchlan(hw);
1685 		break;
1686 	default:
1687 		break;
1688 	}
1689 	if (rc)
1690 		return rc;
1691 
1692 	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1693 	 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1694 	 */
1695 	if ((adapter->hw.phy.type == e1000_phy_ife) ||
1696 	    ((adapter->hw.mac.type >= e1000_pch2lan) &&
1697 	     (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1698 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1699 		adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1700 
1701 		hw->mac.ops.blink_led = NULL;
1702 	}
1703 
1704 	if ((adapter->hw.mac.type == e1000_ich8lan) &&
1705 	    (adapter->hw.phy.type != e1000_phy_ife))
1706 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1707 
1708 	/* Enable workaround for 82579 w/ ME enabled */
1709 	if ((adapter->hw.mac.type == e1000_pch2lan) &&
1710 	    (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1711 		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1712 
1713 	return 0;
1714 }
1715 
1716 static DEFINE_MUTEX(nvm_mutex);
1717 
1718 /**
1719  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Acquires the mutex for performing NVM operations.
1723  **/
1724 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1725 {
1726 	mutex_lock(&nvm_mutex);
1727 
1728 	return 0;
1729 }
1730 
1731 /**
1732  *  e1000_release_nvm_ich8lan - Release NVM mutex
1733  *  @hw: pointer to the HW structure
1734  *
1735  *  Releases the mutex used while performing NVM operations.
1736  **/
1737 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1738 {
1739 	mutex_unlock(&nvm_mutex);
1740 }
1741 
1742 /**
1743  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1744  *  @hw: pointer to the HW structure
1745  *
1746  *  Acquires the software control flag for performing PHY and select
1747  *  MAC CSR accesses.
1748  **/
1749 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1750 {
1751 	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1752 	s32 ret_val = 0;
1753 
1754 	if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1755 			     &hw->adapter->state)) {
1756 		e_dbg("contention for Phy access\n");
1757 		return -E1000_ERR_PHY;
1758 	}
1759 
1760 	while (timeout) {
1761 		extcnf_ctrl = er32(EXTCNF_CTRL);
1762 		if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1763 			break;
1764 
1765 		mdelay(1);
1766 		timeout--;
1767 	}
1768 
1769 	if (!timeout) {
1770 		e_dbg("SW has already locked the resource.\n");
1771 		ret_val = -E1000_ERR_CONFIG;
1772 		goto out;
1773 	}
1774 
1775 	timeout = SW_FLAG_TIMEOUT;
1776 
1777 	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1778 	ew32(EXTCNF_CTRL, extcnf_ctrl);
1779 
1780 	while (timeout) {
1781 		extcnf_ctrl = er32(EXTCNF_CTRL);
1782 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1783 			break;
1784 
1785 		mdelay(1);
1786 		timeout--;
1787 	}
1788 
1789 	if (!timeout) {
1790 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1791 		      er32(FWSM), extcnf_ctrl);
1792 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1793 		ew32(EXTCNF_CTRL, extcnf_ctrl);
1794 		ret_val = -E1000_ERR_CONFIG;
1795 		goto out;
1796 	}
1797 
1798 out:
1799 	if (ret_val)
1800 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1801 
1802 	return ret_val;
1803 }
1804 
1805 /**
1806  *  e1000_release_swflag_ich8lan - Release software control flag
1807  *  @hw: pointer to the HW structure
1808  *
1809  *  Releases the software control flag for performing PHY and select
1810  *  MAC CSR accesses.
1811  **/
1812 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1813 {
1814 	u32 extcnf_ctrl;
1815 
1816 	extcnf_ctrl = er32(EXTCNF_CTRL);
1817 
1818 	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1819 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1820 		ew32(EXTCNF_CTRL, extcnf_ctrl);
1821 	} else {
1822 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1823 	}
1824 
1825 	clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1826 }
1827 
1828 /**
1829  *  e1000_check_mng_mode_ich8lan - Checks management mode
1830  *  @hw: pointer to the HW structure
1831  *
1832  *  This checks if the adapter has any manageability enabled.
1833  *  This is a function pointer entry point only called by read/write
1834  *  routines for the PHY and NVM parts.
1835  **/
1836 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1837 {
1838 	u32 fwsm;
1839 
1840 	fwsm = er32(FWSM);
1841 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1842 		((fwsm & E1000_FWSM_MODE_MASK) ==
1843 		 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1844 }
1845 
1846 /**
1847  *  e1000_check_mng_mode_pchlan - Checks management mode
1848  *  @hw: pointer to the HW structure
1849  *
1850  *  This checks if the adapter has iAMT enabled.
1851  *  This is a function pointer entry point only called by read/write
1852  *  routines for the PHY and NVM parts.
1853  **/
1854 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1855 {
1856 	u32 fwsm;
1857 
1858 	fwsm = er32(FWSM);
1859 	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1860 	    (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1861 }
1862 
1863 /**
1864  *  e1000_rar_set_pch2lan - Set receive address register
1865  *  @hw: pointer to the HW structure
1866  *  @addr: pointer to the receive address
1867  *  @index: receive address array register
1868  *
1869  *  Sets the receive address array register at index to the address passed
1870  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1871  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1872  *  Use SHRA[0-3] in place of those reserved for ME.
1873  **/
1874 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1875 {
1876 	u32 rar_low, rar_high;
1877 
1878 	/* HW expects these in little endian so we reverse the byte order
1879 	 * from network order (big endian) to little endian
1880 	 */
1881 	rar_low = ((u32)addr[0] |
1882 		   ((u32)addr[1] << 8) |
1883 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1884 
1885 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1886 
1887 	/* If MAC address zero, no need to set the AV bit */
1888 	if (rar_low || rar_high)
1889 		rar_high |= E1000_RAH_AV;
1890 
1891 	if (index == 0) {
1892 		ew32(RAL(index), rar_low);
1893 		e1e_flush();
1894 		ew32(RAH(index), rar_high);
1895 		e1e_flush();
1896 		return 0;
1897 	}
1898 
1899 	/* RAR[1-6] are owned by manageability.  Skip those and program the
1900 	 * next address into the SHRA register array.
1901 	 */
1902 	if (index < (u32)(hw->mac.rar_entry_count)) {
1903 		s32 ret_val;
1904 
1905 		ret_val = e1000_acquire_swflag_ich8lan(hw);
1906 		if (ret_val)
1907 			goto out;
1908 
1909 		ew32(SHRAL(index - 1), rar_low);
1910 		e1e_flush();
1911 		ew32(SHRAH(index - 1), rar_high);
1912 		e1e_flush();
1913 
1914 		e1000_release_swflag_ich8lan(hw);
1915 
1916 		/* verify the register updates */
1917 		if ((er32(SHRAL(index - 1)) == rar_low) &&
1918 		    (er32(SHRAH(index - 1)) == rar_high))
1919 			return 0;
1920 
1921 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1922 		      (index - 1), er32(FWSM));
1923 	}
1924 
1925 out:
1926 	e_dbg("Failed to write receive address at index %d\n", index);
1927 	return -E1000_ERR_CONFIG;
1928 }
1929 
1930 /**
1931  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1932  *  @hw: pointer to the HW structure
1933  *
1934  *  Get the number of available receive registers that the Host can
1935  *  program. SHRA[0-10] are the shared receive address registers
1936  *  that are shared between the Host and manageability engine (ME).
1937  *  ME can reserve any number of addresses and the host needs to be
1938  *  able to tell how many available registers it has access to.
1939  **/
1940 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1941 {
1942 	u32 wlock_mac;
1943 	u32 num_entries;
1944 
1945 	wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1946 	wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1947 
1948 	switch (wlock_mac) {
1949 	case 0:
1950 		/* All SHRA[0..10] and RAR[0] available */
1951 		num_entries = hw->mac.rar_entry_count;
1952 		break;
1953 	case 1:
1954 		/* Only RAR[0] available */
1955 		num_entries = 1;
1956 		break;
1957 	default:
1958 		/* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1959 		num_entries = wlock_mac + 1;
1960 		break;
1961 	}
1962 
1963 	return num_entries;
1964 }
1965 
1966 /**
1967  *  e1000_rar_set_pch_lpt - Set receive address registers
1968  *  @hw: pointer to the HW structure
1969  *  @addr: pointer to the receive address
1970  *  @index: receive address array register
1971  *
1972  *  Sets the receive address register array at index to the address passed
1973  *  in by addr. For LPT, RAR[0] is the base address register that is to
1974  *  contain the MAC address. SHRA[0-10] are the shared receive address
1975  *  registers that are shared between the Host and manageability engine (ME).
1976  **/
1977 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1978 {
1979 	u32 rar_low, rar_high;
1980 	u32 wlock_mac;
1981 
1982 	/* HW expects these in little endian so we reverse the byte order
1983 	 * from network order (big endian) to little endian
1984 	 */
1985 	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1986 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1987 
1988 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1989 
1990 	/* If MAC address zero, no need to set the AV bit */
1991 	if (rar_low || rar_high)
1992 		rar_high |= E1000_RAH_AV;
1993 
1994 	if (index == 0) {
1995 		ew32(RAL(index), rar_low);
1996 		e1e_flush();
1997 		ew32(RAH(index), rar_high);
1998 		e1e_flush();
1999 		return 0;
2000 	}
2001 
2002 	/* The manageability engine (ME) can lock certain SHRAR registers that
2003 	 * it is using - those registers are unavailable for use.
2004 	 */
2005 	if (index < hw->mac.rar_entry_count) {
2006 		wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2007 		wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2008 
2009 		/* Check if all SHRAR registers are locked */
2010 		if (wlock_mac == 1)
2011 			goto out;
2012 
2013 		if ((wlock_mac == 0) || (index <= wlock_mac)) {
2014 			s32 ret_val;
2015 
2016 			ret_val = e1000_acquire_swflag_ich8lan(hw);
2017 
2018 			if (ret_val)
2019 				goto out;
2020 
2021 			ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2022 			e1e_flush();
2023 			ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2024 			e1e_flush();
2025 
2026 			e1000_release_swflag_ich8lan(hw);
2027 
2028 			/* verify the register updates */
2029 			if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2030 			    (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2031 				return 0;
2032 		}
2033 	}
2034 
2035 out:
2036 	e_dbg("Failed to write receive address at index %d\n", index);
2037 	return -E1000_ERR_CONFIG;
2038 }
2039 
2040 /**
2041  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2042  *  @hw: pointer to the HW structure
2043  *
2044  *  Checks if firmware is blocking the reset of the PHY.
2045  *  This is a function pointer entry point only called by
2046  *  reset routines.
2047  **/
2048 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2049 {
2050 	bool blocked = false;
2051 	int i = 0;
2052 
2053 	while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2054 	       (i++ < 30))
2055 		usleep_range(10000, 11000);
2056 	return blocked ? E1000_BLK_PHY_RESET : 0;
2057 }
2058 
2059 /**
2060  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2061  *  @hw: pointer to the HW structure
2062  *
2063  *  Assumes semaphore already acquired.
2064  *
2065  **/
2066 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2067 {
2068 	u16 phy_data;
2069 	u32 strap = er32(STRAP);
2070 	u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2071 	    E1000_STRAP_SMT_FREQ_SHIFT;
2072 	s32 ret_val;
2073 
2074 	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2075 
2076 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2077 	if (ret_val)
2078 		return ret_val;
2079 
2080 	phy_data &= ~HV_SMB_ADDR_MASK;
2081 	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2082 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2083 
2084 	if (hw->phy.type == e1000_phy_i217) {
2085 		/* Restore SMBus frequency */
2086 		if (freq--) {
2087 			phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2088 			phy_data |= (freq & BIT(0)) <<
2089 			    HV_SMB_ADDR_FREQ_LOW_SHIFT;
2090 			phy_data |= (freq & BIT(1)) <<
2091 			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2092 		} else {
2093 			e_dbg("Unsupported SMB frequency in PHY\n");
2094 		}
2095 	}
2096 
2097 	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2098 }
2099 
2100 /**
2101  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2102  *  @hw:   pointer to the HW structure
2103  *
2104  *  SW should configure the LCD from the NVM extended configuration region
2105  *  as a workaround for certain parts.
2106  **/
2107 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2108 {
2109 	struct e1000_phy_info *phy = &hw->phy;
2110 	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2111 	s32 ret_val = 0;
2112 	u16 word_addr, reg_data, reg_addr, phy_page = 0;
2113 
2114 	/* Initialize the PHY from the NVM on ICH platforms.  This
2115 	 * is needed due to an issue where the NVM configuration is
2116 	 * not properly autoloaded after power transitions.
2117 	 * Therefore, after each PHY reset, we will load the
2118 	 * configuration data out of the NVM manually.
2119 	 */
2120 	switch (hw->mac.type) {
2121 	case e1000_ich8lan:
2122 		if (phy->type != e1000_phy_igp_3)
2123 			return ret_val;
2124 
2125 		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2126 		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2127 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2128 			break;
2129 		}
2130 		fallthrough;
2131 	case e1000_pchlan:
2132 	case e1000_pch2lan:
2133 	case e1000_pch_lpt:
2134 	case e1000_pch_spt:
2135 	case e1000_pch_cnp:
2136 	case e1000_pch_tgp:
2137 	case e1000_pch_adp:
2138 	case e1000_pch_mtp:
2139 	case e1000_pch_lnp:
2140 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2141 		break;
2142 	default:
2143 		return ret_val;
2144 	}
2145 
2146 	ret_val = hw->phy.ops.acquire(hw);
2147 	if (ret_val)
2148 		return ret_val;
2149 
2150 	data = er32(FEXTNVM);
2151 	if (!(data & sw_cfg_mask))
2152 		goto release;
2153 
2154 	/* Make sure HW does not configure LCD from PHY
2155 	 * extended configuration before SW configuration
2156 	 */
2157 	data = er32(EXTCNF_CTRL);
2158 	if ((hw->mac.type < e1000_pch2lan) &&
2159 	    (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2160 		goto release;
2161 
2162 	cnf_size = er32(EXTCNF_SIZE);
2163 	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2164 	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2165 	if (!cnf_size)
2166 		goto release;
2167 
2168 	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2169 	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2170 
2171 	if (((hw->mac.type == e1000_pchlan) &&
2172 	     !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2173 	    (hw->mac.type > e1000_pchlan)) {
2174 		/* HW configures the SMBus address and LEDs when the
2175 		 * OEM and LCD Write Enable bits are set in the NVM.
2176 		 * When both NVM bits are cleared, SW will configure
2177 		 * them instead.
2178 		 */
2179 		ret_val = e1000_write_smbus_addr(hw);
2180 		if (ret_val)
2181 			goto release;
2182 
2183 		data = er32(LEDCTL);
2184 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2185 							(u16)data);
2186 		if (ret_val)
2187 			goto release;
2188 	}
2189 
2190 	/* Configure LCD from extended configuration region. */
2191 
2192 	/* cnf_base_addr is in DWORD */
2193 	word_addr = (u16)(cnf_base_addr << 1);
2194 
2195 	for (i = 0; i < cnf_size; i++) {
2196 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2197 		if (ret_val)
2198 			goto release;
2199 
2200 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2201 					 1, &reg_addr);
2202 		if (ret_val)
2203 			goto release;
2204 
2205 		/* Save off the PHY page for future writes. */
2206 		if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2207 			phy_page = reg_data;
2208 			continue;
2209 		}
2210 
2211 		reg_addr &= PHY_REG_MASK;
2212 		reg_addr |= phy_page;
2213 
2214 		ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2215 		if (ret_val)
2216 			goto release;
2217 	}
2218 
2219 release:
2220 	hw->phy.ops.release(hw);
2221 	return ret_val;
2222 }
2223 
2224 /**
2225  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2226  *  @hw:   pointer to the HW structure
2227  *  @link: link up bool flag
2228  *
2229  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2230  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2231  *  If link is down, the function will restore the default K1 setting located
2232  *  in the NVM.
2233  **/
2234 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2235 {
2236 	s32 ret_val = 0;
2237 	u16 status_reg = 0;
2238 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2239 
2240 	if (hw->mac.type != e1000_pchlan)
2241 		return 0;
2242 
2243 	/* Wrap the whole flow with the sw flag */
2244 	ret_val = hw->phy.ops.acquire(hw);
2245 	if (ret_val)
2246 		return ret_val;
2247 
2248 	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2249 	if (link) {
2250 		if (hw->phy.type == e1000_phy_82578) {
2251 			ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2252 						  &status_reg);
2253 			if (ret_val)
2254 				goto release;
2255 
2256 			status_reg &= (BM_CS_STATUS_LINK_UP |
2257 				       BM_CS_STATUS_RESOLVED |
2258 				       BM_CS_STATUS_SPEED_MASK);
2259 
2260 			if (status_reg == (BM_CS_STATUS_LINK_UP |
2261 					   BM_CS_STATUS_RESOLVED |
2262 					   BM_CS_STATUS_SPEED_1000))
2263 				k1_enable = false;
2264 		}
2265 
2266 		if (hw->phy.type == e1000_phy_82577) {
2267 			ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2268 			if (ret_val)
2269 				goto release;
2270 
2271 			status_reg &= (HV_M_STATUS_LINK_UP |
2272 				       HV_M_STATUS_AUTONEG_COMPLETE |
2273 				       HV_M_STATUS_SPEED_MASK);
2274 
2275 			if (status_reg == (HV_M_STATUS_LINK_UP |
2276 					   HV_M_STATUS_AUTONEG_COMPLETE |
2277 					   HV_M_STATUS_SPEED_1000))
2278 				k1_enable = false;
2279 		}
2280 
2281 		/* Link stall fix for link up */
2282 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2283 		if (ret_val)
2284 			goto release;
2285 
2286 	} else {
2287 		/* Link stall fix for link down */
2288 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2289 		if (ret_val)
2290 			goto release;
2291 	}
2292 
2293 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2294 
2295 release:
2296 	hw->phy.ops.release(hw);
2297 
2298 	return ret_val;
2299 }
2300 
2301 /**
2302  *  e1000_configure_k1_ich8lan - Configure K1 power state
2303  *  @hw: pointer to the HW structure
2304  *  @k1_enable: K1 state to configure
2305  *
2306  *  Configure the K1 power state based on the provided parameter.
2307  *  Assumes semaphore already acquired.
2308  *
2309  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2310  **/
2311 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2312 {
2313 	s32 ret_val;
2314 	u32 ctrl_reg = 0;
2315 	u32 ctrl_ext = 0;
2316 	u32 reg = 0;
2317 	u16 kmrn_reg = 0;
2318 
2319 	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2320 					      &kmrn_reg);
2321 	if (ret_val)
2322 		return ret_val;
2323 
2324 	if (k1_enable)
2325 		kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2326 	else
2327 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2328 
2329 	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2330 					       kmrn_reg);
2331 	if (ret_val)
2332 		return ret_val;
2333 
2334 	usleep_range(20, 40);
2335 	ctrl_ext = er32(CTRL_EXT);
2336 	ctrl_reg = er32(CTRL);
2337 
2338 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2339 	reg |= E1000_CTRL_FRCSPD;
2340 	ew32(CTRL, reg);
2341 
2342 	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2343 	e1e_flush();
2344 	usleep_range(20, 40);
2345 	ew32(CTRL, ctrl_reg);
2346 	ew32(CTRL_EXT, ctrl_ext);
2347 	e1e_flush();
2348 	usleep_range(20, 40);
2349 
2350 	return 0;
2351 }
2352 
2353 /**
2354  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2355  *  @hw:       pointer to the HW structure
2356  *  @d0_state: boolean if entering d0 or d3 device state
2357  *
2358  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2359  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2360  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2361  **/
2362 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2363 {
2364 	s32 ret_val = 0;
2365 	u32 mac_reg;
2366 	u16 oem_reg;
2367 
2368 	if (hw->mac.type < e1000_pchlan)
2369 		return ret_val;
2370 
2371 	ret_val = hw->phy.ops.acquire(hw);
2372 	if (ret_val)
2373 		return ret_val;
2374 
2375 	if (hw->mac.type == e1000_pchlan) {
2376 		mac_reg = er32(EXTCNF_CTRL);
2377 		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2378 			goto release;
2379 	}
2380 
2381 	mac_reg = er32(FEXTNVM);
2382 	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2383 		goto release;
2384 
2385 	mac_reg = er32(PHY_CTRL);
2386 
2387 	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2388 	if (ret_val)
2389 		goto release;
2390 
2391 	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2392 
2393 	if (d0_state) {
2394 		if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2395 			oem_reg |= HV_OEM_BITS_GBE_DIS;
2396 
2397 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2398 			oem_reg |= HV_OEM_BITS_LPLU;
2399 	} else {
2400 		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2401 			       E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2402 			oem_reg |= HV_OEM_BITS_GBE_DIS;
2403 
2404 		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2405 			       E1000_PHY_CTRL_NOND0A_LPLU))
2406 			oem_reg |= HV_OEM_BITS_LPLU;
2407 	}
2408 
2409 	/* Set Restart auto-neg to activate the bits */
2410 	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2411 	    !hw->phy.ops.check_reset_block(hw))
2412 		oem_reg |= HV_OEM_BITS_RESTART_AN;
2413 
2414 	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2415 
2416 release:
2417 	hw->phy.ops.release(hw);
2418 
2419 	return ret_val;
2420 }
2421 
2422 /**
2423  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2424  *  @hw:   pointer to the HW structure
2425  **/
2426 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2427 {
2428 	s32 ret_val;
2429 	u16 data;
2430 
2431 	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2432 	if (ret_val)
2433 		return ret_val;
2434 
2435 	data |= HV_KMRN_MDIO_SLOW;
2436 
2437 	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2438 
2439 	return ret_val;
2440 }
2441 
2442 /**
2443  *  e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2444  *  @hw: pointer to the HW structure
2445  *
2446  *  A series of PHY workarounds to be done after every PHY reset.
2447  **/
2448 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2449 {
2450 	s32 ret_val = 0;
2451 	u16 phy_data;
2452 
2453 	if (hw->mac.type != e1000_pchlan)
2454 		return 0;
2455 
2456 	/* Set MDIO slow mode before any other MDIO access */
2457 	if (hw->phy.type == e1000_phy_82577) {
2458 		ret_val = e1000_set_mdio_slow_mode_hv(hw);
2459 		if (ret_val)
2460 			return ret_val;
2461 	}
2462 
2463 	if (((hw->phy.type == e1000_phy_82577) &&
2464 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2465 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2466 		/* Disable generation of early preamble */
2467 		ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2468 		if (ret_val)
2469 			return ret_val;
2470 
2471 		/* Preamble tuning for SSC */
2472 		ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2473 		if (ret_val)
2474 			return ret_val;
2475 	}
2476 
2477 	if (hw->phy.type == e1000_phy_82578) {
2478 		/* Return registers to default by doing a soft reset then
2479 		 * writing 0x3140 to the control register.
2480 		 */
2481 		if (hw->phy.revision < 2) {
2482 			e1000e_phy_sw_reset(hw);
2483 			ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2484 			if (ret_val)
2485 				return ret_val;
2486 		}
2487 	}
2488 
2489 	/* Select page 0 */
2490 	ret_val = hw->phy.ops.acquire(hw);
2491 	if (ret_val)
2492 		return ret_val;
2493 
2494 	hw->phy.addr = 1;
2495 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2496 	hw->phy.ops.release(hw);
2497 	if (ret_val)
2498 		return ret_val;
2499 
2500 	/* Configure the K1 Si workaround during phy reset assuming there is
2501 	 * link so that it disables K1 if link is in 1Gbps.
2502 	 */
2503 	ret_val = e1000_k1_gig_workaround_hv(hw, true);
2504 	if (ret_val)
2505 		return ret_val;
2506 
2507 	/* Workaround for link disconnects on a busy hub in half duplex */
2508 	ret_val = hw->phy.ops.acquire(hw);
2509 	if (ret_val)
2510 		return ret_val;
2511 	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2512 	if (ret_val)
2513 		goto release;
2514 	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2515 	if (ret_val)
2516 		goto release;
2517 
2518 	/* set MSE higher to enable link to stay up when noise is high */
2519 	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2520 release:
2521 	hw->phy.ops.release(hw);
2522 
2523 	return ret_val;
2524 }
2525 
2526 /**
2527  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2528  *  @hw:   pointer to the HW structure
2529  **/
2530 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2531 {
2532 	u32 mac_reg;
2533 	u16 i, phy_reg = 0;
2534 	s32 ret_val;
2535 
2536 	ret_val = hw->phy.ops.acquire(hw);
2537 	if (ret_val)
2538 		return;
2539 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2540 	if (ret_val)
2541 		goto release;
2542 
2543 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2544 	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2545 		mac_reg = er32(RAL(i));
2546 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2547 					   (u16)(mac_reg & 0xFFFF));
2548 		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2549 					   (u16)((mac_reg >> 16) & 0xFFFF));
2550 
2551 		mac_reg = er32(RAH(i));
2552 		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2553 					   (u16)(mac_reg & 0xFFFF));
2554 		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2555 					   (u16)((mac_reg & E1000_RAH_AV)
2556 						 >> 16));
2557 	}
2558 
2559 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2560 
2561 release:
2562 	hw->phy.ops.release(hw);
2563 }
2564 
2565 /**
2566  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2567  *  with 82579 PHY
2568  *  @hw: pointer to the HW structure
2569  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2570  **/
2571 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2572 {
2573 	s32 ret_val = 0;
2574 	u16 phy_reg, data;
2575 	u32 mac_reg;
2576 	u16 i;
2577 
2578 	if (hw->mac.type < e1000_pch2lan)
2579 		return 0;
2580 
2581 	/* disable Rx path while enabling/disabling workaround */
2582 	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2583 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2584 	if (ret_val)
2585 		return ret_val;
2586 
2587 	if (enable) {
2588 		/* Write Rx addresses (rar_entry_count for RAL/H, and
2589 		 * SHRAL/H) and initial CRC values to the MAC
2590 		 */
2591 		for (i = 0; i < hw->mac.rar_entry_count; i++) {
2592 			u8 mac_addr[ETH_ALEN] = { 0 };
2593 			u32 addr_high, addr_low;
2594 
2595 			addr_high = er32(RAH(i));
2596 			if (!(addr_high & E1000_RAH_AV))
2597 				continue;
2598 			addr_low = er32(RAL(i));
2599 			mac_addr[0] = (addr_low & 0xFF);
2600 			mac_addr[1] = ((addr_low >> 8) & 0xFF);
2601 			mac_addr[2] = ((addr_low >> 16) & 0xFF);
2602 			mac_addr[3] = ((addr_low >> 24) & 0xFF);
2603 			mac_addr[4] = (addr_high & 0xFF);
2604 			mac_addr[5] = ((addr_high >> 8) & 0xFF);
2605 
2606 			ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2607 		}
2608 
2609 		/* Write Rx addresses to the PHY */
2610 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2611 
2612 		/* Enable jumbo frame workaround in the MAC */
2613 		mac_reg = er32(FFLT_DBG);
2614 		mac_reg &= ~BIT(14);
2615 		mac_reg |= (7 << 15);
2616 		ew32(FFLT_DBG, mac_reg);
2617 
2618 		mac_reg = er32(RCTL);
2619 		mac_reg |= E1000_RCTL_SECRC;
2620 		ew32(RCTL, mac_reg);
2621 
2622 		ret_val = e1000e_read_kmrn_reg(hw,
2623 					       E1000_KMRNCTRLSTA_CTRL_OFFSET,
2624 					       &data);
2625 		if (ret_val)
2626 			return ret_val;
2627 		ret_val = e1000e_write_kmrn_reg(hw,
2628 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
2629 						data | BIT(0));
2630 		if (ret_val)
2631 			return ret_val;
2632 		ret_val = e1000e_read_kmrn_reg(hw,
2633 					       E1000_KMRNCTRLSTA_HD_CTRL,
2634 					       &data);
2635 		if (ret_val)
2636 			return ret_val;
2637 		data &= ~(0xF << 8);
2638 		data |= (0xB << 8);
2639 		ret_val = e1000e_write_kmrn_reg(hw,
2640 						E1000_KMRNCTRLSTA_HD_CTRL,
2641 						data);
2642 		if (ret_val)
2643 			return ret_val;
2644 
2645 		/* Enable jumbo frame workaround in the PHY */
2646 		e1e_rphy(hw, PHY_REG(769, 23), &data);
2647 		data &= ~(0x7F << 5);
2648 		data |= (0x37 << 5);
2649 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2650 		if (ret_val)
2651 			return ret_val;
2652 		e1e_rphy(hw, PHY_REG(769, 16), &data);
2653 		data &= ~BIT(13);
2654 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2655 		if (ret_val)
2656 			return ret_val;
2657 		e1e_rphy(hw, PHY_REG(776, 20), &data);
2658 		data &= ~(0x3FF << 2);
2659 		data |= (E1000_TX_PTR_GAP << 2);
2660 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2661 		if (ret_val)
2662 			return ret_val;
2663 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2664 		if (ret_val)
2665 			return ret_val;
2666 		e1e_rphy(hw, HV_PM_CTRL, &data);
2667 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2668 		if (ret_val)
2669 			return ret_val;
2670 	} else {
2671 		/* Write MAC register values back to h/w defaults */
2672 		mac_reg = er32(FFLT_DBG);
2673 		mac_reg &= ~(0xF << 14);
2674 		ew32(FFLT_DBG, mac_reg);
2675 
2676 		mac_reg = er32(RCTL);
2677 		mac_reg &= ~E1000_RCTL_SECRC;
2678 		ew32(RCTL, mac_reg);
2679 
2680 		ret_val = e1000e_read_kmrn_reg(hw,
2681 					       E1000_KMRNCTRLSTA_CTRL_OFFSET,
2682 					       &data);
2683 		if (ret_val)
2684 			return ret_val;
2685 		ret_val = e1000e_write_kmrn_reg(hw,
2686 						E1000_KMRNCTRLSTA_CTRL_OFFSET,
2687 						data & ~BIT(0));
2688 		if (ret_val)
2689 			return ret_val;
2690 		ret_val = e1000e_read_kmrn_reg(hw,
2691 					       E1000_KMRNCTRLSTA_HD_CTRL,
2692 					       &data);
2693 		if (ret_val)
2694 			return ret_val;
2695 		data &= ~(0xF << 8);
2696 		data |= (0xB << 8);
2697 		ret_val = e1000e_write_kmrn_reg(hw,
2698 						E1000_KMRNCTRLSTA_HD_CTRL,
2699 						data);
2700 		if (ret_val)
2701 			return ret_val;
2702 
2703 		/* Write PHY register values back to h/w defaults */
2704 		e1e_rphy(hw, PHY_REG(769, 23), &data);
2705 		data &= ~(0x7F << 5);
2706 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2707 		if (ret_val)
2708 			return ret_val;
2709 		e1e_rphy(hw, PHY_REG(769, 16), &data);
2710 		data |= BIT(13);
2711 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2712 		if (ret_val)
2713 			return ret_val;
2714 		e1e_rphy(hw, PHY_REG(776, 20), &data);
2715 		data &= ~(0x3FF << 2);
2716 		data |= (0x8 << 2);
2717 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2718 		if (ret_val)
2719 			return ret_val;
2720 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2721 		if (ret_val)
2722 			return ret_val;
2723 		e1e_rphy(hw, HV_PM_CTRL, &data);
2724 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2725 		if (ret_val)
2726 			return ret_val;
2727 	}
2728 
2729 	/* re-enable Rx path after enabling/disabling workaround */
2730 	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2731 }
2732 
2733 /**
2734  *  e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2735  *  @hw: pointer to the HW structure
2736  *
2737  *  A series of PHY workarounds to be done after every PHY reset.
2738  **/
2739 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2740 {
2741 	s32 ret_val = 0;
2742 
2743 	if (hw->mac.type != e1000_pch2lan)
2744 		return 0;
2745 
2746 	/* Set MDIO slow mode before any other MDIO access */
2747 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
2748 	if (ret_val)
2749 		return ret_val;
2750 
2751 	ret_val = hw->phy.ops.acquire(hw);
2752 	if (ret_val)
2753 		return ret_val;
2754 	/* set MSE higher to enable link to stay up when noise is high */
2755 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2756 	if (ret_val)
2757 		goto release;
2758 	/* drop link after 5 times MSE threshold was reached */
2759 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2760 release:
2761 	hw->phy.ops.release(hw);
2762 
2763 	return ret_val;
2764 }
2765 
2766 /**
2767  *  e1000_k1_workaround_lv - K1 Si workaround
2768  *  @hw:   pointer to the HW structure
2769  *
2770  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2771  *  Disable K1 in 1000Mbps and 100Mbps
2772  **/
2773 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2774 {
2775 	s32 ret_val = 0;
2776 	u16 status_reg = 0;
2777 
2778 	if (hw->mac.type != e1000_pch2lan)
2779 		return 0;
2780 
2781 	/* Set K1 beacon duration based on 10Mbs speed */
2782 	ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2783 	if (ret_val)
2784 		return ret_val;
2785 
2786 	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2787 	    == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2788 		if (status_reg &
2789 		    (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2790 			u16 pm_phy_reg;
2791 
2792 			/* LV 1G/100 Packet drop issue wa  */
2793 			ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2794 			if (ret_val)
2795 				return ret_val;
2796 			pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2797 			ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2798 			if (ret_val)
2799 				return ret_val;
2800 		} else {
2801 			u32 mac_reg;
2802 
2803 			mac_reg = er32(FEXTNVM4);
2804 			mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2805 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2806 			ew32(FEXTNVM4, mac_reg);
2807 		}
2808 	}
2809 
2810 	return ret_val;
2811 }
2812 
2813 /**
2814  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2815  *  @hw:   pointer to the HW structure
2816  *  @gate: boolean set to true to gate, false to ungate
2817  *
2818  *  Gate/ungate the automatic PHY configuration via hardware; perform
2819  *  the configuration via software instead.
2820  **/
2821 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2822 {
2823 	u32 extcnf_ctrl;
2824 
2825 	if (hw->mac.type < e1000_pch2lan)
2826 		return;
2827 
2828 	extcnf_ctrl = er32(EXTCNF_CTRL);
2829 
2830 	if (gate)
2831 		extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2832 	else
2833 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2834 
2835 	ew32(EXTCNF_CTRL, extcnf_ctrl);
2836 }
2837 
2838 /**
2839  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2840  *  @hw: pointer to the HW structure
2841  *
2842  *  Check the appropriate indication the MAC has finished configuring the
2843  *  PHY after a software reset.
2844  **/
2845 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2846 {
2847 	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2848 
2849 	/* Wait for basic configuration completes before proceeding */
2850 	do {
2851 		data = er32(STATUS);
2852 		data &= E1000_STATUS_LAN_INIT_DONE;
2853 		usleep_range(100, 200);
2854 	} while ((!data) && --loop);
2855 
2856 	/* If basic configuration is incomplete before the above loop
2857 	 * count reaches 0, loading the configuration from NVM will
2858 	 * leave the PHY in a bad state possibly resulting in no link.
2859 	 */
2860 	if (loop == 0)
2861 		e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2862 
2863 	/* Clear the Init Done bit for the next init event */
2864 	data = er32(STATUS);
2865 	data &= ~E1000_STATUS_LAN_INIT_DONE;
2866 	ew32(STATUS, data);
2867 }
2868 
2869 /**
2870  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2871  *  @hw: pointer to the HW structure
2872  **/
2873 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2874 {
2875 	s32 ret_val = 0;
2876 	u16 reg;
2877 
2878 	if (hw->phy.ops.check_reset_block(hw))
2879 		return 0;
2880 
2881 	/* Allow time for h/w to get to quiescent state after reset */
2882 	usleep_range(10000, 11000);
2883 
2884 	/* Perform any necessary post-reset workarounds */
2885 	switch (hw->mac.type) {
2886 	case e1000_pchlan:
2887 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2888 		if (ret_val)
2889 			return ret_val;
2890 		break;
2891 	case e1000_pch2lan:
2892 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2893 		if (ret_val)
2894 			return ret_val;
2895 		break;
2896 	default:
2897 		break;
2898 	}
2899 
2900 	/* Clear the host wakeup bit after lcd reset */
2901 	if (hw->mac.type >= e1000_pchlan) {
2902 		e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2903 		reg &= ~BM_WUC_HOST_WU_BIT;
2904 		e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2905 	}
2906 
2907 	/* Configure the LCD with the extended configuration region in NVM */
2908 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
2909 	if (ret_val)
2910 		return ret_val;
2911 
2912 	/* Configure the LCD with the OEM bits in NVM */
2913 	ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2914 
2915 	if (hw->mac.type == e1000_pch2lan) {
2916 		/* Ungate automatic PHY configuration on non-managed 82579 */
2917 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2918 			usleep_range(10000, 11000);
2919 			e1000_gate_hw_phy_config_ich8lan(hw, false);
2920 		}
2921 
2922 		/* Set EEE LPI Update Timer to 200usec */
2923 		ret_val = hw->phy.ops.acquire(hw);
2924 		if (ret_val)
2925 			return ret_val;
2926 		ret_val = e1000_write_emi_reg_locked(hw,
2927 						     I82579_LPI_UPDATE_TIMER,
2928 						     0x1387);
2929 		hw->phy.ops.release(hw);
2930 	}
2931 
2932 	return ret_val;
2933 }
2934 
2935 /**
2936  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2937  *  @hw: pointer to the HW structure
2938  *
2939  *  Resets the PHY
2940  *  This is a function pointer entry point called by drivers
2941  *  or other shared routines.
2942  **/
2943 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2944 {
2945 	s32 ret_val = 0;
2946 
2947 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
2948 	if ((hw->mac.type == e1000_pch2lan) &&
2949 	    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2950 		e1000_gate_hw_phy_config_ich8lan(hw, true);
2951 
2952 	ret_val = e1000e_phy_hw_reset_generic(hw);
2953 	if (ret_val)
2954 		return ret_val;
2955 
2956 	return e1000_post_phy_reset_ich8lan(hw);
2957 }
2958 
2959 /**
2960  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2961  *  @hw: pointer to the HW structure
2962  *  @active: true to enable LPLU, false to disable
2963  *
2964  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2965  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2966  *  the phy speed. This function will manually set the LPLU bit and restart
2967  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2968  *  since it configures the same bit.
2969  **/
2970 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2971 {
2972 	s32 ret_val;
2973 	u16 oem_reg;
2974 
2975 	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2976 	if (ret_val)
2977 		return ret_val;
2978 
2979 	if (active)
2980 		oem_reg |= HV_OEM_BITS_LPLU;
2981 	else
2982 		oem_reg &= ~HV_OEM_BITS_LPLU;
2983 
2984 	if (!hw->phy.ops.check_reset_block(hw))
2985 		oem_reg |= HV_OEM_BITS_RESTART_AN;
2986 
2987 	return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2988 }
2989 
2990 /**
2991  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2992  *  @hw: pointer to the HW structure
2993  *  @active: true to enable LPLU, false to disable
2994  *
2995  *  Sets the LPLU D0 state according to the active flag.  When
2996  *  activating LPLU this function also disables smart speed
2997  *  and vice versa.  LPLU will not be activated unless the
2998  *  device autonegotiation advertisement meets standards of
2999  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3000  *  This is a function pointer entry point only called by
3001  *  PHY setup routines.
3002  **/
3003 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3004 {
3005 	struct e1000_phy_info *phy = &hw->phy;
3006 	u32 phy_ctrl;
3007 	s32 ret_val = 0;
3008 	u16 data;
3009 
3010 	if (phy->type == e1000_phy_ife)
3011 		return 0;
3012 
3013 	phy_ctrl = er32(PHY_CTRL);
3014 
3015 	if (active) {
3016 		phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3017 		ew32(PHY_CTRL, phy_ctrl);
3018 
3019 		if (phy->type != e1000_phy_igp_3)
3020 			return 0;
3021 
3022 		/* Call gig speed drop workaround on LPLU before accessing
3023 		 * any PHY registers
3024 		 */
3025 		if (hw->mac.type == e1000_ich8lan)
3026 			e1000e_gig_downshift_workaround_ich8lan(hw);
3027 
3028 		/* When LPLU is enabled, we should disable SmartSpeed */
3029 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3030 		if (ret_val)
3031 			return ret_val;
3032 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3033 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3034 		if (ret_val)
3035 			return ret_val;
3036 	} else {
3037 		phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3038 		ew32(PHY_CTRL, phy_ctrl);
3039 
3040 		if (phy->type != e1000_phy_igp_3)
3041 			return 0;
3042 
3043 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3044 		 * during Dx states where the power conservation is most
3045 		 * important.  During driver activity we should enable
3046 		 * SmartSpeed, so performance is maintained.
3047 		 */
3048 		if (phy->smart_speed == e1000_smart_speed_on) {
3049 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3050 					   &data);
3051 			if (ret_val)
3052 				return ret_val;
3053 
3054 			data |= IGP01E1000_PSCFR_SMART_SPEED;
3055 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3056 					   data);
3057 			if (ret_val)
3058 				return ret_val;
3059 		} else if (phy->smart_speed == e1000_smart_speed_off) {
3060 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3061 					   &data);
3062 			if (ret_val)
3063 				return ret_val;
3064 
3065 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3066 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3067 					   data);
3068 			if (ret_val)
3069 				return ret_val;
3070 		}
3071 	}
3072 
3073 	return 0;
3074 }
3075 
3076 /**
3077  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3078  *  @hw: pointer to the HW structure
3079  *  @active: true to enable LPLU, false to disable
3080  *
3081  *  Sets the LPLU D3 state according to the active flag.  When
3082  *  activating LPLU this function also disables smart speed
3083  *  and vice versa.  LPLU will not be activated unless the
3084  *  device autonegotiation advertisement meets standards of
3085  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3086  *  This is a function pointer entry point only called by
3087  *  PHY setup routines.
3088  **/
3089 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3090 {
3091 	struct e1000_phy_info *phy = &hw->phy;
3092 	u32 phy_ctrl;
3093 	s32 ret_val = 0;
3094 	u16 data;
3095 
3096 	phy_ctrl = er32(PHY_CTRL);
3097 
3098 	if (!active) {
3099 		phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3100 		ew32(PHY_CTRL, phy_ctrl);
3101 
3102 		if (phy->type != e1000_phy_igp_3)
3103 			return 0;
3104 
3105 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3106 		 * during Dx states where the power conservation is most
3107 		 * important.  During driver activity we should enable
3108 		 * SmartSpeed, so performance is maintained.
3109 		 */
3110 		if (phy->smart_speed == e1000_smart_speed_on) {
3111 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3112 					   &data);
3113 			if (ret_val)
3114 				return ret_val;
3115 
3116 			data |= IGP01E1000_PSCFR_SMART_SPEED;
3117 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3118 					   data);
3119 			if (ret_val)
3120 				return ret_val;
3121 		} else if (phy->smart_speed == e1000_smart_speed_off) {
3122 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3123 					   &data);
3124 			if (ret_val)
3125 				return ret_val;
3126 
3127 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3128 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3129 					   data);
3130 			if (ret_val)
3131 				return ret_val;
3132 		}
3133 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3134 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3135 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3136 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3137 		ew32(PHY_CTRL, phy_ctrl);
3138 
3139 		if (phy->type != e1000_phy_igp_3)
3140 			return 0;
3141 
3142 		/* Call gig speed drop workaround on LPLU before accessing
3143 		 * any PHY registers
3144 		 */
3145 		if (hw->mac.type == e1000_ich8lan)
3146 			e1000e_gig_downshift_workaround_ich8lan(hw);
3147 
3148 		/* When LPLU is enabled, we should disable SmartSpeed */
3149 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3150 		if (ret_val)
3151 			return ret_val;
3152 
3153 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3154 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3155 	}
3156 
3157 	return ret_val;
3158 }
3159 
3160 /**
3161  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3162  *  @hw: pointer to the HW structure
3163  *  @bank:  pointer to the variable that returns the active bank
3164  *
3165  *  Reads signature byte from the NVM using the flash access registers.
3166  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3167  **/
3168 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3169 {
3170 	u32 eecd;
3171 	struct e1000_nvm_info *nvm = &hw->nvm;
3172 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3173 	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3174 	u32 nvm_dword = 0;
3175 	u8 sig_byte = 0;
3176 	s32 ret_val;
3177 
3178 	switch (hw->mac.type) {
3179 	case e1000_pch_spt:
3180 	case e1000_pch_cnp:
3181 	case e1000_pch_tgp:
3182 	case e1000_pch_adp:
3183 	case e1000_pch_mtp:
3184 	case e1000_pch_lnp:
3185 		bank1_offset = nvm->flash_bank_size;
3186 		act_offset = E1000_ICH_NVM_SIG_WORD;
3187 
3188 		/* set bank to 0 in case flash read fails */
3189 		*bank = 0;
3190 
3191 		/* Check bank 0 */
3192 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3193 							 &nvm_dword);
3194 		if (ret_val)
3195 			return ret_val;
3196 		sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3197 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3198 		    E1000_ICH_NVM_SIG_VALUE) {
3199 			*bank = 0;
3200 			return 0;
3201 		}
3202 
3203 		/* Check bank 1 */
3204 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3205 							 bank1_offset,
3206 							 &nvm_dword);
3207 		if (ret_val)
3208 			return ret_val;
3209 		sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3210 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3211 		    E1000_ICH_NVM_SIG_VALUE) {
3212 			*bank = 1;
3213 			return 0;
3214 		}
3215 
3216 		e_dbg("ERROR: No valid NVM bank present\n");
3217 		return -E1000_ERR_NVM;
3218 	case e1000_ich8lan:
3219 	case e1000_ich9lan:
3220 		eecd = er32(EECD);
3221 		if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3222 		    E1000_EECD_SEC1VAL_VALID_MASK) {
3223 			if (eecd & E1000_EECD_SEC1VAL)
3224 				*bank = 1;
3225 			else
3226 				*bank = 0;
3227 
3228 			return 0;
3229 		}
3230 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3231 		fallthrough;
3232 	default:
3233 		/* set bank to 0 in case flash read fails */
3234 		*bank = 0;
3235 
3236 		/* Check bank 0 */
3237 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3238 							&sig_byte);
3239 		if (ret_val)
3240 			return ret_val;
3241 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3242 		    E1000_ICH_NVM_SIG_VALUE) {
3243 			*bank = 0;
3244 			return 0;
3245 		}
3246 
3247 		/* Check bank 1 */
3248 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3249 							bank1_offset,
3250 							&sig_byte);
3251 		if (ret_val)
3252 			return ret_val;
3253 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3254 		    E1000_ICH_NVM_SIG_VALUE) {
3255 			*bank = 1;
3256 			return 0;
3257 		}
3258 
3259 		e_dbg("ERROR: No valid NVM bank present\n");
3260 		return -E1000_ERR_NVM;
3261 	}
3262 }
3263 
3264 /**
3265  *  e1000_read_nvm_spt - NVM access for SPT
3266  *  @hw: pointer to the HW structure
3267  *  @offset: The offset (in bytes) of the word(s) to read.
3268  *  @words: Size of data to read in words.
3269  *  @data: pointer to the word(s) to read at offset.
3270  *
3271  *  Reads a word(s) from the NVM
3272  **/
3273 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3274 			      u16 *data)
3275 {
3276 	struct e1000_nvm_info *nvm = &hw->nvm;
3277 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3278 	u32 act_offset;
3279 	s32 ret_val = 0;
3280 	u32 bank = 0;
3281 	u32 dword = 0;
3282 	u16 offset_to_read;
3283 	u16 i;
3284 
3285 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3286 	    (words == 0)) {
3287 		e_dbg("nvm parameter(s) out of bounds\n");
3288 		ret_val = -E1000_ERR_NVM;
3289 		goto out;
3290 	}
3291 
3292 	nvm->ops.acquire(hw);
3293 
3294 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3295 	if (ret_val) {
3296 		e_dbg("Could not detect valid bank, assuming bank 0\n");
3297 		bank = 0;
3298 	}
3299 
3300 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3301 	act_offset += offset;
3302 
3303 	ret_val = 0;
3304 
3305 	for (i = 0; i < words; i += 2) {
3306 		if (words - i == 1) {
3307 			if (dev_spec->shadow_ram[offset + i].modified) {
3308 				data[i] =
3309 				    dev_spec->shadow_ram[offset + i].value;
3310 			} else {
3311 				offset_to_read = act_offset + i -
3312 				    ((act_offset + i) % 2);
3313 				ret_val =
3314 				  e1000_read_flash_dword_ich8lan(hw,
3315 								 offset_to_read,
3316 								 &dword);
3317 				if (ret_val)
3318 					break;
3319 				if ((act_offset + i) % 2 == 0)
3320 					data[i] = (u16)(dword & 0xFFFF);
3321 				else
3322 					data[i] = (u16)((dword >> 16) & 0xFFFF);
3323 			}
3324 		} else {
3325 			offset_to_read = act_offset + i;
3326 			if (!(dev_spec->shadow_ram[offset + i].modified) ||
3327 			    !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3328 				ret_val =
3329 				  e1000_read_flash_dword_ich8lan(hw,
3330 								 offset_to_read,
3331 								 &dword);
3332 				if (ret_val)
3333 					break;
3334 			}
3335 			if (dev_spec->shadow_ram[offset + i].modified)
3336 				data[i] =
3337 				    dev_spec->shadow_ram[offset + i].value;
3338 			else
3339 				data[i] = (u16)(dword & 0xFFFF);
3340 			if (dev_spec->shadow_ram[offset + i].modified)
3341 				data[i + 1] =
3342 				    dev_spec->shadow_ram[offset + i + 1].value;
3343 			else
3344 				data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3345 		}
3346 	}
3347 
3348 	nvm->ops.release(hw);
3349 
3350 out:
3351 	if (ret_val)
3352 		e_dbg("NVM read error: %d\n", ret_val);
3353 
3354 	return ret_val;
3355 }
3356 
3357 /**
3358  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3359  *  @hw: pointer to the HW structure
3360  *  @offset: The offset (in bytes) of the word(s) to read.
3361  *  @words: Size of data to read in words
3362  *  @data: Pointer to the word(s) to read at offset.
3363  *
3364  *  Reads a word(s) from the NVM using the flash access registers.
3365  **/
3366 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3367 				  u16 *data)
3368 {
3369 	struct e1000_nvm_info *nvm = &hw->nvm;
3370 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3371 	u32 act_offset;
3372 	s32 ret_val = 0;
3373 	u32 bank = 0;
3374 	u16 i, word;
3375 
3376 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3377 	    (words == 0)) {
3378 		e_dbg("nvm parameter(s) out of bounds\n");
3379 		ret_val = -E1000_ERR_NVM;
3380 		goto out;
3381 	}
3382 
3383 	nvm->ops.acquire(hw);
3384 
3385 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3386 	if (ret_val) {
3387 		e_dbg("Could not detect valid bank, assuming bank 0\n");
3388 		bank = 0;
3389 	}
3390 
3391 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3392 	act_offset += offset;
3393 
3394 	ret_val = 0;
3395 	for (i = 0; i < words; i++) {
3396 		if (dev_spec->shadow_ram[offset + i].modified) {
3397 			data[i] = dev_spec->shadow_ram[offset + i].value;
3398 		} else {
3399 			ret_val = e1000_read_flash_word_ich8lan(hw,
3400 								act_offset + i,
3401 								&word);
3402 			if (ret_val)
3403 				break;
3404 			data[i] = word;
3405 		}
3406 	}
3407 
3408 	nvm->ops.release(hw);
3409 
3410 out:
3411 	if (ret_val)
3412 		e_dbg("NVM read error: %d\n", ret_val);
3413 
3414 	return ret_val;
3415 }
3416 
3417 /**
3418  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3419  *  @hw: pointer to the HW structure
3420  *
3421  *  This function does initial flash setup so that a new read/write/erase cycle
3422  *  can be started.
3423  **/
3424 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3425 {
3426 	union ich8_hws_flash_status hsfsts;
3427 	s32 ret_val = -E1000_ERR_NVM;
3428 
3429 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3430 
3431 	/* Check if the flash descriptor is valid */
3432 	if (!hsfsts.hsf_status.fldesvalid) {
3433 		e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3434 		return -E1000_ERR_NVM;
3435 	}
3436 
3437 	/* Clear FCERR and DAEL in hw status by writing 1 */
3438 	hsfsts.hsf_status.flcerr = 1;
3439 	hsfsts.hsf_status.dael = 1;
3440 	if (hw->mac.type >= e1000_pch_spt)
3441 		ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3442 	else
3443 		ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3444 
3445 	/* Either we should have a hardware SPI cycle in progress
3446 	 * bit to check against, in order to start a new cycle or
3447 	 * FDONE bit should be changed in the hardware so that it
3448 	 * is 1 after hardware reset, which can then be used as an
3449 	 * indication whether a cycle is in progress or has been
3450 	 * completed.
3451 	 */
3452 
3453 	if (!hsfsts.hsf_status.flcinprog) {
3454 		/* There is no cycle running at present,
3455 		 * so we can start a cycle.
3456 		 * Begin by setting Flash Cycle Done.
3457 		 */
3458 		hsfsts.hsf_status.flcdone = 1;
3459 		if (hw->mac.type >= e1000_pch_spt)
3460 			ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3461 		else
3462 			ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3463 		ret_val = 0;
3464 	} else {
3465 		s32 i;
3466 
3467 		/* Otherwise poll for sometime so the current
3468 		 * cycle has a chance to end before giving up.
3469 		 */
3470 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3471 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3472 			if (!hsfsts.hsf_status.flcinprog) {
3473 				ret_val = 0;
3474 				break;
3475 			}
3476 			udelay(1);
3477 		}
3478 		if (!ret_val) {
3479 			/* Successful in waiting for previous cycle to timeout,
3480 			 * now set the Flash Cycle Done.
3481 			 */
3482 			hsfsts.hsf_status.flcdone = 1;
3483 			if (hw->mac.type >= e1000_pch_spt)
3484 				ew32flash(ICH_FLASH_HSFSTS,
3485 					  hsfsts.regval & 0xFFFF);
3486 			else
3487 				ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3488 		} else {
3489 			e_dbg("Flash controller busy, cannot get access\n");
3490 		}
3491 	}
3492 
3493 	return ret_val;
3494 }
3495 
3496 /**
3497  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3498  *  @hw: pointer to the HW structure
3499  *  @timeout: maximum time to wait for completion
3500  *
3501  *  This function starts a flash cycle and waits for its completion.
3502  **/
3503 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3504 {
3505 	union ich8_hws_flash_ctrl hsflctl;
3506 	union ich8_hws_flash_status hsfsts;
3507 	u32 i = 0;
3508 
3509 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3510 	if (hw->mac.type >= e1000_pch_spt)
3511 		hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3512 	else
3513 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3514 	hsflctl.hsf_ctrl.flcgo = 1;
3515 
3516 	if (hw->mac.type >= e1000_pch_spt)
3517 		ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3518 	else
3519 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3520 
3521 	/* wait till FDONE bit is set to 1 */
3522 	do {
3523 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3524 		if (hsfsts.hsf_status.flcdone)
3525 			break;
3526 		udelay(1);
3527 	} while (i++ < timeout);
3528 
3529 	if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3530 		return 0;
3531 
3532 	return -E1000_ERR_NVM;
3533 }
3534 
3535 /**
3536  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3537  *  @hw: pointer to the HW structure
3538  *  @offset: offset to data location
3539  *  @data: pointer to the location for storing the data
3540  *
3541  *  Reads the flash dword at offset into data.  Offset is converted
3542  *  to bytes before read.
3543  **/
3544 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3545 					  u32 *data)
3546 {
3547 	/* Must convert word offset into bytes. */
3548 	offset <<= 1;
3549 	return e1000_read_flash_data32_ich8lan(hw, offset, data);
3550 }
3551 
3552 /**
3553  *  e1000_read_flash_word_ich8lan - Read word from flash
3554  *  @hw: pointer to the HW structure
3555  *  @offset: offset to data location
3556  *  @data: pointer to the location for storing the data
3557  *
3558  *  Reads the flash word at offset into data.  Offset is converted
3559  *  to bytes before read.
3560  **/
3561 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3562 					 u16 *data)
3563 {
3564 	/* Must convert offset into bytes. */
3565 	offset <<= 1;
3566 
3567 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3568 }
3569 
3570 /**
3571  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3572  *  @hw: pointer to the HW structure
3573  *  @offset: The offset of the byte to read.
3574  *  @data: Pointer to a byte to store the value read.
3575  *
3576  *  Reads a single byte from the NVM using the flash access registers.
3577  **/
3578 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3579 					 u8 *data)
3580 {
3581 	s32 ret_val;
3582 	u16 word = 0;
3583 
3584 	/* In SPT, only 32 bits access is supported,
3585 	 * so this function should not be called.
3586 	 */
3587 	if (hw->mac.type >= e1000_pch_spt)
3588 		return -E1000_ERR_NVM;
3589 	else
3590 		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3591 
3592 	if (ret_val)
3593 		return ret_val;
3594 
3595 	*data = (u8)word;
3596 
3597 	return 0;
3598 }
3599 
3600 /**
3601  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3602  *  @hw: pointer to the HW structure
3603  *  @offset: The offset (in bytes) of the byte or word to read.
3604  *  @size: Size of data to read, 1=byte 2=word
3605  *  @data: Pointer to the word to store the value read.
3606  *
3607  *  Reads a byte or word from the NVM using the flash access registers.
3608  **/
3609 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3610 					 u8 size, u16 *data)
3611 {
3612 	union ich8_hws_flash_status hsfsts;
3613 	union ich8_hws_flash_ctrl hsflctl;
3614 	u32 flash_linear_addr;
3615 	u32 flash_data = 0;
3616 	s32 ret_val = -E1000_ERR_NVM;
3617 	u8 count = 0;
3618 
3619 	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3620 		return -E1000_ERR_NVM;
3621 
3622 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3623 			     hw->nvm.flash_base_addr);
3624 
3625 	do {
3626 		udelay(1);
3627 		/* Steps */
3628 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3629 		if (ret_val)
3630 			break;
3631 
3632 		hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3633 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3634 		hsflctl.hsf_ctrl.fldbcount = size - 1;
3635 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3636 		ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3637 
3638 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3639 
3640 		ret_val =
3641 		    e1000_flash_cycle_ich8lan(hw,
3642 					      ICH_FLASH_READ_COMMAND_TIMEOUT);
3643 
3644 		/* Check if FCERR is set to 1, if set to 1, clear it
3645 		 * and try the whole sequence a few more times, else
3646 		 * read in (shift in) the Flash Data0, the order is
3647 		 * least significant byte first msb to lsb
3648 		 */
3649 		if (!ret_val) {
3650 			flash_data = er32flash(ICH_FLASH_FDATA0);
3651 			if (size == 1)
3652 				*data = (u8)(flash_data & 0x000000FF);
3653 			else if (size == 2)
3654 				*data = (u16)(flash_data & 0x0000FFFF);
3655 			break;
3656 		} else {
3657 			/* If we've gotten here, then things are probably
3658 			 * completely hosed, but if the error condition is
3659 			 * detected, it won't hurt to give it another try...
3660 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3661 			 */
3662 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3663 			if (hsfsts.hsf_status.flcerr) {
3664 				/* Repeat for some time before giving up. */
3665 				continue;
3666 			} else if (!hsfsts.hsf_status.flcdone) {
3667 				e_dbg("Timeout error - flash cycle did not complete.\n");
3668 				break;
3669 			}
3670 		}
3671 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3672 
3673 	return ret_val;
3674 }
3675 
3676 /**
3677  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3678  *  @hw: pointer to the HW structure
3679  *  @offset: The offset (in bytes) of the dword to read.
3680  *  @data: Pointer to the dword to store the value read.
3681  *
3682  *  Reads a byte or word from the NVM using the flash access registers.
3683  **/
3684 
3685 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3686 					   u32 *data)
3687 {
3688 	union ich8_hws_flash_status hsfsts;
3689 	union ich8_hws_flash_ctrl hsflctl;
3690 	u32 flash_linear_addr;
3691 	s32 ret_val = -E1000_ERR_NVM;
3692 	u8 count = 0;
3693 
3694 	if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3695 		return -E1000_ERR_NVM;
3696 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3697 			     hw->nvm.flash_base_addr);
3698 
3699 	do {
3700 		udelay(1);
3701 		/* Steps */
3702 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
3703 		if (ret_val)
3704 			break;
3705 		/* In SPT, This register is in Lan memory space, not flash.
3706 		 * Therefore, only 32 bit access is supported
3707 		 */
3708 		hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3709 
3710 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3711 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3712 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3713 		/* In SPT, This register is in Lan memory space, not flash.
3714 		 * Therefore, only 32 bit access is supported
3715 		 */
3716 		ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3717 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3718 
3719 		ret_val =
3720 		   e1000_flash_cycle_ich8lan(hw,
3721 					     ICH_FLASH_READ_COMMAND_TIMEOUT);
3722 
3723 		/* Check if FCERR is set to 1, if set to 1, clear it
3724 		 * and try the whole sequence a few more times, else
3725 		 * read in (shift in) the Flash Data0, the order is
3726 		 * least significant byte first msb to lsb
3727 		 */
3728 		if (!ret_val) {
3729 			*data = er32flash(ICH_FLASH_FDATA0);
3730 			break;
3731 		} else {
3732 			/* If we've gotten here, then things are probably
3733 			 * completely hosed, but if the error condition is
3734 			 * detected, it won't hurt to give it another try...
3735 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3736 			 */
3737 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3738 			if (hsfsts.hsf_status.flcerr) {
3739 				/* Repeat for some time before giving up. */
3740 				continue;
3741 			} else if (!hsfsts.hsf_status.flcdone) {
3742 				e_dbg("Timeout error - flash cycle did not complete.\n");
3743 				break;
3744 			}
3745 		}
3746 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3747 
3748 	return ret_val;
3749 }
3750 
3751 /**
3752  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3753  *  @hw: pointer to the HW structure
3754  *  @offset: The offset (in bytes) of the word(s) to write.
3755  *  @words: Size of data to write in words
3756  *  @data: Pointer to the word(s) to write at offset.
3757  *
3758  *  Writes a byte or word to the NVM using the flash access registers.
3759  **/
3760 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3761 				   u16 *data)
3762 {
3763 	struct e1000_nvm_info *nvm = &hw->nvm;
3764 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3765 	u16 i;
3766 
3767 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3768 	    (words == 0)) {
3769 		e_dbg("nvm parameter(s) out of bounds\n");
3770 		return -E1000_ERR_NVM;
3771 	}
3772 
3773 	nvm->ops.acquire(hw);
3774 
3775 	for (i = 0; i < words; i++) {
3776 		dev_spec->shadow_ram[offset + i].modified = true;
3777 		dev_spec->shadow_ram[offset + i].value = data[i];
3778 	}
3779 
3780 	nvm->ops.release(hw);
3781 
3782 	return 0;
3783 }
3784 
3785 /**
3786  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3787  *  @hw: pointer to the HW structure
3788  *
3789  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3790  *  which writes the checksum to the shadow ram.  The changes in the shadow
3791  *  ram are then committed to the EEPROM by processing each bank at a time
3792  *  checking for the modified bit and writing only the pending changes.
3793  *  After a successful commit, the shadow ram is cleared and is ready for
3794  *  future writes.
3795  **/
3796 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3797 {
3798 	struct e1000_nvm_info *nvm = &hw->nvm;
3799 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3800 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3801 	s32 ret_val;
3802 	u32 dword = 0;
3803 
3804 	ret_val = e1000e_update_nvm_checksum_generic(hw);
3805 	if (ret_val)
3806 		goto out;
3807 
3808 	if (nvm->type != e1000_nvm_flash_sw)
3809 		goto out;
3810 
3811 	nvm->ops.acquire(hw);
3812 
3813 	/* We're writing to the opposite bank so if we're on bank 1,
3814 	 * write to bank 0 etc.  We also need to erase the segment that
3815 	 * is going to be written
3816 	 */
3817 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3818 	if (ret_val) {
3819 		e_dbg("Could not detect valid bank, assuming bank 0\n");
3820 		bank = 0;
3821 	}
3822 
3823 	if (bank == 0) {
3824 		new_bank_offset = nvm->flash_bank_size;
3825 		old_bank_offset = 0;
3826 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3827 		if (ret_val)
3828 			goto release;
3829 	} else {
3830 		old_bank_offset = nvm->flash_bank_size;
3831 		new_bank_offset = 0;
3832 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3833 		if (ret_val)
3834 			goto release;
3835 	}
3836 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3837 		/* Determine whether to write the value stored
3838 		 * in the other NVM bank or a modified value stored
3839 		 * in the shadow RAM
3840 		 */
3841 		ret_val = e1000_read_flash_dword_ich8lan(hw,
3842 							 i + old_bank_offset,
3843 							 &dword);
3844 
3845 		if (dev_spec->shadow_ram[i].modified) {
3846 			dword &= 0xffff0000;
3847 			dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3848 		}
3849 		if (dev_spec->shadow_ram[i + 1].modified) {
3850 			dword &= 0x0000ffff;
3851 			dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3852 				  << 16);
3853 		}
3854 		if (ret_val)
3855 			break;
3856 
3857 		/* If the word is 0x13, then make sure the signature bits
3858 		 * (15:14) are 11b until the commit has completed.
3859 		 * This will allow us to write 10b which indicates the
3860 		 * signature is valid.  We want to do this after the write
3861 		 * has completed so that we don't mark the segment valid
3862 		 * while the write is still in progress
3863 		 */
3864 		if (i == E1000_ICH_NVM_SIG_WORD - 1)
3865 			dword |= E1000_ICH_NVM_SIG_MASK << 16;
3866 
3867 		/* Convert offset to bytes. */
3868 		act_offset = (i + new_bank_offset) << 1;
3869 
3870 		usleep_range(100, 200);
3871 
3872 		/* Write the data to the new bank. Offset in words */
3873 		act_offset = i + new_bank_offset;
3874 		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3875 								dword);
3876 		if (ret_val)
3877 			break;
3878 	}
3879 
3880 	/* Don't bother writing the segment valid bits if sector
3881 	 * programming failed.
3882 	 */
3883 	if (ret_val) {
3884 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3885 		e_dbg("Flash commit failed.\n");
3886 		goto release;
3887 	}
3888 
3889 	/* Finally validate the new segment by setting bit 15:14
3890 	 * to 10b in word 0x13 , this can be done without an
3891 	 * erase as well since these bits are 11 to start with
3892 	 * and we need to change bit 14 to 0b
3893 	 */
3894 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3895 
3896 	/*offset in words but we read dword */
3897 	--act_offset;
3898 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3899 
3900 	if (ret_val)
3901 		goto release;
3902 
3903 	dword &= 0xBFFFFFFF;
3904 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3905 
3906 	if (ret_val)
3907 		goto release;
3908 
3909 	/* offset in words but we read dword */
3910 	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3911 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3912 
3913 	if (ret_val)
3914 		goto release;
3915 
3916 	dword &= 0x00FFFFFF;
3917 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3918 
3919 	if (ret_val)
3920 		goto release;
3921 
3922 	/* Great!  Everything worked, we can now clear the cached entries. */
3923 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3924 		dev_spec->shadow_ram[i].modified = false;
3925 		dev_spec->shadow_ram[i].value = 0xFFFF;
3926 	}
3927 
3928 release:
3929 	nvm->ops.release(hw);
3930 
3931 	/* Reload the EEPROM, or else modifications will not appear
3932 	 * until after the next adapter reset.
3933 	 */
3934 	if (!ret_val) {
3935 		nvm->ops.reload(hw);
3936 		usleep_range(10000, 11000);
3937 	}
3938 
3939 out:
3940 	if (ret_val)
3941 		e_dbg("NVM update error: %d\n", ret_val);
3942 
3943 	return ret_val;
3944 }
3945 
3946 /**
3947  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3948  *  @hw: pointer to the HW structure
3949  *
3950  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3951  *  which writes the checksum to the shadow ram.  The changes in the shadow
3952  *  ram are then committed to the EEPROM by processing each bank at a time
3953  *  checking for the modified bit and writing only the pending changes.
3954  *  After a successful commit, the shadow ram is cleared and is ready for
3955  *  future writes.
3956  **/
3957 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3958 {
3959 	struct e1000_nvm_info *nvm = &hw->nvm;
3960 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3961 	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3962 	s32 ret_val;
3963 	u16 data = 0;
3964 
3965 	ret_val = e1000e_update_nvm_checksum_generic(hw);
3966 	if (ret_val)
3967 		goto out;
3968 
3969 	if (nvm->type != e1000_nvm_flash_sw)
3970 		goto out;
3971 
3972 	nvm->ops.acquire(hw);
3973 
3974 	/* We're writing to the opposite bank so if we're on bank 1,
3975 	 * write to bank 0 etc.  We also need to erase the segment that
3976 	 * is going to be written
3977 	 */
3978 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3979 	if (ret_val) {
3980 		e_dbg("Could not detect valid bank, assuming bank 0\n");
3981 		bank = 0;
3982 	}
3983 
3984 	if (bank == 0) {
3985 		new_bank_offset = nvm->flash_bank_size;
3986 		old_bank_offset = 0;
3987 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3988 		if (ret_val)
3989 			goto release;
3990 	} else {
3991 		old_bank_offset = nvm->flash_bank_size;
3992 		new_bank_offset = 0;
3993 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3994 		if (ret_val)
3995 			goto release;
3996 	}
3997 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3998 		if (dev_spec->shadow_ram[i].modified) {
3999 			data = dev_spec->shadow_ram[i].value;
4000 		} else {
4001 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
4002 								old_bank_offset,
4003 								&data);
4004 			if (ret_val)
4005 				break;
4006 		}
4007 
4008 		/* If the word is 0x13, then make sure the signature bits
4009 		 * (15:14) are 11b until the commit has completed.
4010 		 * This will allow us to write 10b which indicates the
4011 		 * signature is valid.  We want to do this after the write
4012 		 * has completed so that we don't mark the segment valid
4013 		 * while the write is still in progress
4014 		 */
4015 		if (i == E1000_ICH_NVM_SIG_WORD)
4016 			data |= E1000_ICH_NVM_SIG_MASK;
4017 
4018 		/* Convert offset to bytes. */
4019 		act_offset = (i + new_bank_offset) << 1;
4020 
4021 		usleep_range(100, 200);
4022 		/* Write the bytes to the new bank. */
4023 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4024 							       act_offset,
4025 							       (u8)data);
4026 		if (ret_val)
4027 			break;
4028 
4029 		usleep_range(100, 200);
4030 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4031 							       act_offset + 1,
4032 							       (u8)(data >> 8));
4033 		if (ret_val)
4034 			break;
4035 	}
4036 
4037 	/* Don't bother writing the segment valid bits if sector
4038 	 * programming failed.
4039 	 */
4040 	if (ret_val) {
4041 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4042 		e_dbg("Flash commit failed.\n");
4043 		goto release;
4044 	}
4045 
4046 	/* Finally validate the new segment by setting bit 15:14
4047 	 * to 10b in word 0x13 , this can be done without an
4048 	 * erase as well since these bits are 11 to start with
4049 	 * and we need to change bit 14 to 0b
4050 	 */
4051 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4052 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4053 	if (ret_val)
4054 		goto release;
4055 
4056 	data &= 0xBFFF;
4057 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4058 						       act_offset * 2 + 1,
4059 						       (u8)(data >> 8));
4060 	if (ret_val)
4061 		goto release;
4062 
4063 	/* And invalidate the previously valid segment by setting
4064 	 * its signature word (0x13) high_byte to 0b. This can be
4065 	 * done without an erase because flash erase sets all bits
4066 	 * to 1's. We can write 1's to 0's without an erase
4067 	 */
4068 	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4069 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4070 	if (ret_val)
4071 		goto release;
4072 
4073 	/* Great!  Everything worked, we can now clear the cached entries. */
4074 	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4075 		dev_spec->shadow_ram[i].modified = false;
4076 		dev_spec->shadow_ram[i].value = 0xFFFF;
4077 	}
4078 
4079 release:
4080 	nvm->ops.release(hw);
4081 
4082 	/* Reload the EEPROM, or else modifications will not appear
4083 	 * until after the next adapter reset.
4084 	 */
4085 	if (!ret_val) {
4086 		nvm->ops.reload(hw);
4087 		usleep_range(10000, 11000);
4088 	}
4089 
4090 out:
4091 	if (ret_val)
4092 		e_dbg("NVM update error: %d\n", ret_val);
4093 
4094 	return ret_val;
4095 }
4096 
4097 /**
4098  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4099  *  @hw: pointer to the HW structure
4100  *
4101  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4102  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4103  *  calculated, in which case we need to calculate the checksum and set bit 6.
4104  **/
4105 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4106 {
4107 	s32 ret_val;
4108 	u16 data;
4109 	u16 word;
4110 	u16 valid_csum_mask;
4111 
4112 	/* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4113 	 * the checksum needs to be fixed.  This bit is an indication that
4114 	 * the NVM was prepared by OEM software and did not calculate
4115 	 * the checksum...a likely scenario.
4116 	 */
4117 	switch (hw->mac.type) {
4118 	case e1000_pch_lpt:
4119 	case e1000_pch_spt:
4120 	case e1000_pch_cnp:
4121 	case e1000_pch_tgp:
4122 	case e1000_pch_adp:
4123 	case e1000_pch_mtp:
4124 	case e1000_pch_lnp:
4125 		word = NVM_COMPAT;
4126 		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4127 		break;
4128 	default:
4129 		word = NVM_FUTURE_INIT_WORD1;
4130 		valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4131 		break;
4132 	}
4133 
4134 	ret_val = e1000_read_nvm(hw, word, 1, &data);
4135 	if (ret_val)
4136 		return ret_val;
4137 
4138 	if (!(data & valid_csum_mask)) {
4139 		e_dbg("NVM Checksum Invalid\n");
4140 
4141 		if (hw->mac.type < e1000_pch_cnp) {
4142 			data |= valid_csum_mask;
4143 			ret_val = e1000_write_nvm(hw, word, 1, &data);
4144 			if (ret_val)
4145 				return ret_val;
4146 			ret_val = e1000e_update_nvm_checksum(hw);
4147 			if (ret_val)
4148 				return ret_val;
4149 		}
4150 	}
4151 
4152 	return e1000e_validate_nvm_checksum_generic(hw);
4153 }
4154 
4155 /**
4156  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4157  *  @hw: pointer to the HW structure
4158  *
4159  *  To prevent malicious write/erase of the NVM, set it to be read-only
4160  *  so that the hardware ignores all write/erase cycles of the NVM via
4161  *  the flash control registers.  The shadow-ram copy of the NVM will
4162  *  still be updated, however any updates to this copy will not stick
4163  *  across driver reloads.
4164  **/
4165 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4166 {
4167 	struct e1000_nvm_info *nvm = &hw->nvm;
4168 	union ich8_flash_protected_range pr0;
4169 	union ich8_hws_flash_status hsfsts;
4170 	u32 gfpreg;
4171 
4172 	nvm->ops.acquire(hw);
4173 
4174 	gfpreg = er32flash(ICH_FLASH_GFPREG);
4175 
4176 	/* Write-protect GbE Sector of NVM */
4177 	pr0.regval = er32flash(ICH_FLASH_PR0);
4178 	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4179 	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4180 	pr0.range.wpe = true;
4181 	ew32flash(ICH_FLASH_PR0, pr0.regval);
4182 
4183 	/* Lock down a subset of GbE Flash Control Registers, e.g.
4184 	 * PR0 to prevent the write-protection from being lifted.
4185 	 * Once FLOCKDN is set, the registers protected by it cannot
4186 	 * be written until FLOCKDN is cleared by a hardware reset.
4187 	 */
4188 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4189 	hsfsts.hsf_status.flockdn = true;
4190 	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4191 
4192 	nvm->ops.release(hw);
4193 }
4194 
4195 /**
4196  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4197  *  @hw: pointer to the HW structure
4198  *  @offset: The offset (in bytes) of the byte/word to read.
4199  *  @size: Size of data to read, 1=byte 2=word
4200  *  @data: The byte(s) to write to the NVM.
4201  *
4202  *  Writes one/two bytes to the NVM using the flash access registers.
4203  **/
4204 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4205 					  u8 size, u16 data)
4206 {
4207 	union ich8_hws_flash_status hsfsts;
4208 	union ich8_hws_flash_ctrl hsflctl;
4209 	u32 flash_linear_addr;
4210 	u32 flash_data = 0;
4211 	s32 ret_val;
4212 	u8 count = 0;
4213 
4214 	if (hw->mac.type >= e1000_pch_spt) {
4215 		if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4216 			return -E1000_ERR_NVM;
4217 	} else {
4218 		if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4219 			return -E1000_ERR_NVM;
4220 	}
4221 
4222 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4223 			     hw->nvm.flash_base_addr);
4224 
4225 	do {
4226 		udelay(1);
4227 		/* Steps */
4228 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
4229 		if (ret_val)
4230 			break;
4231 		/* In SPT, This register is in Lan memory space, not
4232 		 * flash.  Therefore, only 32 bit access is supported
4233 		 */
4234 		if (hw->mac.type >= e1000_pch_spt)
4235 			hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4236 		else
4237 			hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4238 
4239 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4240 		hsflctl.hsf_ctrl.fldbcount = size - 1;
4241 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4242 		/* In SPT, This register is in Lan memory space,
4243 		 * not flash.  Therefore, only 32 bit access is
4244 		 * supported
4245 		 */
4246 		if (hw->mac.type >= e1000_pch_spt)
4247 			ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4248 		else
4249 			ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4250 
4251 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4252 
4253 		if (size == 1)
4254 			flash_data = (u32)data & 0x00FF;
4255 		else
4256 			flash_data = (u32)data;
4257 
4258 		ew32flash(ICH_FLASH_FDATA0, flash_data);
4259 
4260 		/* check if FCERR is set to 1 , if set to 1, clear it
4261 		 * and try the whole sequence a few more times else done
4262 		 */
4263 		ret_val =
4264 		    e1000_flash_cycle_ich8lan(hw,
4265 					      ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4266 		if (!ret_val)
4267 			break;
4268 
4269 		/* If we're here, then things are most likely
4270 		 * completely hosed, but if the error condition
4271 		 * is detected, it won't hurt to give it another
4272 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4273 		 */
4274 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4275 		if (hsfsts.hsf_status.flcerr)
4276 			/* Repeat for some time before giving up. */
4277 			continue;
4278 		if (!hsfsts.hsf_status.flcdone) {
4279 			e_dbg("Timeout error - flash cycle did not complete.\n");
4280 			break;
4281 		}
4282 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4283 
4284 	return ret_val;
4285 }
4286 
4287 /**
4288 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4289 *  @hw: pointer to the HW structure
4290 *  @offset: The offset (in bytes) of the dwords to read.
4291 *  @data: The 4 bytes to write to the NVM.
4292 *
4293 *  Writes one/two/four bytes to the NVM using the flash access registers.
4294 **/
4295 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4296 					    u32 data)
4297 {
4298 	union ich8_hws_flash_status hsfsts;
4299 	union ich8_hws_flash_ctrl hsflctl;
4300 	u32 flash_linear_addr;
4301 	s32 ret_val;
4302 	u8 count = 0;
4303 
4304 	if (hw->mac.type >= e1000_pch_spt) {
4305 		if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4306 			return -E1000_ERR_NVM;
4307 	}
4308 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4309 			     hw->nvm.flash_base_addr);
4310 	do {
4311 		udelay(1);
4312 		/* Steps */
4313 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
4314 		if (ret_val)
4315 			break;
4316 
4317 		/* In SPT, This register is in Lan memory space, not
4318 		 * flash.  Therefore, only 32 bit access is supported
4319 		 */
4320 		if (hw->mac.type >= e1000_pch_spt)
4321 			hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4322 			    >> 16;
4323 		else
4324 			hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4325 
4326 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4327 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4328 
4329 		/* In SPT, This register is in Lan memory space,
4330 		 * not flash.  Therefore, only 32 bit access is
4331 		 * supported
4332 		 */
4333 		if (hw->mac.type >= e1000_pch_spt)
4334 			ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4335 		else
4336 			ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4337 
4338 		ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4339 
4340 		ew32flash(ICH_FLASH_FDATA0, data);
4341 
4342 		/* check if FCERR is set to 1 , if set to 1, clear it
4343 		 * and try the whole sequence a few more times else done
4344 		 */
4345 		ret_val =
4346 		   e1000_flash_cycle_ich8lan(hw,
4347 					     ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4348 
4349 		if (!ret_val)
4350 			break;
4351 
4352 		/* If we're here, then things are most likely
4353 		 * completely hosed, but if the error condition
4354 		 * is detected, it won't hurt to give it another
4355 		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4356 		 */
4357 		hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4358 
4359 		if (hsfsts.hsf_status.flcerr)
4360 			/* Repeat for some time before giving up. */
4361 			continue;
4362 		if (!hsfsts.hsf_status.flcdone) {
4363 			e_dbg("Timeout error - flash cycle did not complete.\n");
4364 			break;
4365 		}
4366 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4367 
4368 	return ret_val;
4369 }
4370 
4371 /**
4372  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4373  *  @hw: pointer to the HW structure
4374  *  @offset: The index of the byte to read.
4375  *  @data: The byte to write to the NVM.
4376  *
4377  *  Writes a single byte to the NVM using the flash access registers.
4378  **/
4379 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4380 					  u8 data)
4381 {
4382 	u16 word = (u16)data;
4383 
4384 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4385 }
4386 
4387 /**
4388 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4389 *  @hw: pointer to the HW structure
4390 *  @offset: The offset of the word to write.
4391 *  @dword: The dword to write to the NVM.
4392 *
4393 *  Writes a single dword to the NVM using the flash access registers.
4394 *  Goes through a retry algorithm before giving up.
4395 **/
4396 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4397 						 u32 offset, u32 dword)
4398 {
4399 	s32 ret_val;
4400 	u16 program_retries;
4401 
4402 	/* Must convert word offset into bytes. */
4403 	offset <<= 1;
4404 	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4405 
4406 	if (!ret_val)
4407 		return ret_val;
4408 	for (program_retries = 0; program_retries < 100; program_retries++) {
4409 		e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4410 		usleep_range(100, 200);
4411 		ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4412 		if (!ret_val)
4413 			break;
4414 	}
4415 	if (program_retries == 100)
4416 		return -E1000_ERR_NVM;
4417 
4418 	return 0;
4419 }
4420 
4421 /**
4422  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4423  *  @hw: pointer to the HW structure
4424  *  @offset: The offset of the byte to write.
4425  *  @byte: The byte to write to the NVM.
4426  *
4427  *  Writes a single byte to the NVM using the flash access registers.
4428  *  Goes through a retry algorithm before giving up.
4429  **/
4430 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4431 						u32 offset, u8 byte)
4432 {
4433 	s32 ret_val;
4434 	u16 program_retries;
4435 
4436 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4437 	if (!ret_val)
4438 		return ret_val;
4439 
4440 	for (program_retries = 0; program_retries < 100; program_retries++) {
4441 		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4442 		usleep_range(100, 200);
4443 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4444 		if (!ret_val)
4445 			break;
4446 	}
4447 	if (program_retries == 100)
4448 		return -E1000_ERR_NVM;
4449 
4450 	return 0;
4451 }
4452 
4453 /**
4454  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4455  *  @hw: pointer to the HW structure
4456  *  @bank: 0 for first bank, 1 for second bank, etc.
4457  *
4458  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4459  *  bank N is 4096 * N + flash_reg_addr.
4460  **/
4461 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4462 {
4463 	struct e1000_nvm_info *nvm = &hw->nvm;
4464 	union ich8_hws_flash_status hsfsts;
4465 	union ich8_hws_flash_ctrl hsflctl;
4466 	u32 flash_linear_addr;
4467 	/* bank size is in 16bit words - adjust to bytes */
4468 	u32 flash_bank_size = nvm->flash_bank_size * 2;
4469 	s32 ret_val;
4470 	s32 count = 0;
4471 	s32 j, iteration, sector_size;
4472 
4473 	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4474 
4475 	/* Determine HW Sector size: Read BERASE bits of hw flash status
4476 	 * register
4477 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4478 	 *     consecutive sectors.  The start index for the nth Hw sector
4479 	 *     can be calculated as = bank * 4096 + n * 256
4480 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4481 	 *     The start index for the nth Hw sector can be calculated
4482 	 *     as = bank * 4096
4483 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4484 	 *     (ich9 only, otherwise error condition)
4485 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4486 	 */
4487 	switch (hsfsts.hsf_status.berasesz) {
4488 	case 0:
4489 		/* Hw sector size 256 */
4490 		sector_size = ICH_FLASH_SEG_SIZE_256;
4491 		iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4492 		break;
4493 	case 1:
4494 		sector_size = ICH_FLASH_SEG_SIZE_4K;
4495 		iteration = 1;
4496 		break;
4497 	case 2:
4498 		sector_size = ICH_FLASH_SEG_SIZE_8K;
4499 		iteration = 1;
4500 		break;
4501 	case 3:
4502 		sector_size = ICH_FLASH_SEG_SIZE_64K;
4503 		iteration = 1;
4504 		break;
4505 	default:
4506 		return -E1000_ERR_NVM;
4507 	}
4508 
4509 	/* Start with the base address, then add the sector offset. */
4510 	flash_linear_addr = hw->nvm.flash_base_addr;
4511 	flash_linear_addr += (bank) ? flash_bank_size : 0;
4512 
4513 	for (j = 0; j < iteration; j++) {
4514 		do {
4515 			u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4516 
4517 			/* Steps */
4518 			ret_val = e1000_flash_cycle_init_ich8lan(hw);
4519 			if (ret_val)
4520 				return ret_val;
4521 
4522 			/* Write a value 11 (block Erase) in Flash
4523 			 * Cycle field in hw flash control
4524 			 */
4525 			if (hw->mac.type >= e1000_pch_spt)
4526 				hsflctl.regval =
4527 				    er32flash(ICH_FLASH_HSFSTS) >> 16;
4528 			else
4529 				hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4530 
4531 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4532 			if (hw->mac.type >= e1000_pch_spt)
4533 				ew32flash(ICH_FLASH_HSFSTS,
4534 					  hsflctl.regval << 16);
4535 			else
4536 				ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4537 
4538 			/* Write the last 24 bits of an index within the
4539 			 * block into Flash Linear address field in Flash
4540 			 * Address.
4541 			 */
4542 			flash_linear_addr += (j * sector_size);
4543 			ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4544 
4545 			ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4546 			if (!ret_val)
4547 				break;
4548 
4549 			/* Check if FCERR is set to 1.  If 1,
4550 			 * clear it and try the whole sequence
4551 			 * a few more times else Done
4552 			 */
4553 			hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4554 			if (hsfsts.hsf_status.flcerr)
4555 				/* repeat for some time before giving up */
4556 				continue;
4557 			else if (!hsfsts.hsf_status.flcdone)
4558 				return ret_val;
4559 		} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4560 	}
4561 
4562 	return 0;
4563 }
4564 
4565 /**
4566  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4567  *  @hw: pointer to the HW structure
4568  *  @data: Pointer to the LED settings
4569  *
4570  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4571  *  settings is all 0's or F's, set the LED default to a valid LED default
4572  *  setting.
4573  **/
4574 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4575 {
4576 	s32 ret_val;
4577 
4578 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4579 	if (ret_val) {
4580 		e_dbg("NVM Read Error\n");
4581 		return ret_val;
4582 	}
4583 
4584 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4585 		*data = ID_LED_DEFAULT_ICH8LAN;
4586 
4587 	return 0;
4588 }
4589 
4590 /**
4591  *  e1000_id_led_init_pchlan - store LED configurations
4592  *  @hw: pointer to the HW structure
4593  *
4594  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4595  *  the PHY LED configuration register.
4596  *
4597  *  PCH also does not have an "always on" or "always off" mode which
4598  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4599  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4600  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4601  *  link based on logic in e1000_led_[on|off]_pchlan().
4602  **/
4603 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4604 {
4605 	struct e1000_mac_info *mac = &hw->mac;
4606 	s32 ret_val;
4607 	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4608 	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4609 	u16 data, i, temp, shift;
4610 
4611 	/* Get default ID LED modes */
4612 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4613 	if (ret_val)
4614 		return ret_val;
4615 
4616 	mac->ledctl_default = er32(LEDCTL);
4617 	mac->ledctl_mode1 = mac->ledctl_default;
4618 	mac->ledctl_mode2 = mac->ledctl_default;
4619 
4620 	for (i = 0; i < 4; i++) {
4621 		temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4622 		shift = (i * 5);
4623 		switch (temp) {
4624 		case ID_LED_ON1_DEF2:
4625 		case ID_LED_ON1_ON2:
4626 		case ID_LED_ON1_OFF2:
4627 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4628 			mac->ledctl_mode1 |= (ledctl_on << shift);
4629 			break;
4630 		case ID_LED_OFF1_DEF2:
4631 		case ID_LED_OFF1_ON2:
4632 		case ID_LED_OFF1_OFF2:
4633 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4634 			mac->ledctl_mode1 |= (ledctl_off << shift);
4635 			break;
4636 		default:
4637 			/* Do nothing */
4638 			break;
4639 		}
4640 		switch (temp) {
4641 		case ID_LED_DEF1_ON2:
4642 		case ID_LED_ON1_ON2:
4643 		case ID_LED_OFF1_ON2:
4644 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4645 			mac->ledctl_mode2 |= (ledctl_on << shift);
4646 			break;
4647 		case ID_LED_DEF1_OFF2:
4648 		case ID_LED_ON1_OFF2:
4649 		case ID_LED_OFF1_OFF2:
4650 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4651 			mac->ledctl_mode2 |= (ledctl_off << shift);
4652 			break;
4653 		default:
4654 			/* Do nothing */
4655 			break;
4656 		}
4657 	}
4658 
4659 	return 0;
4660 }
4661 
4662 /**
4663  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4664  *  @hw: pointer to the HW structure
4665  *
4666  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4667  *  register, so the bus width is hard coded.
4668  **/
4669 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4670 {
4671 	struct e1000_bus_info *bus = &hw->bus;
4672 	s32 ret_val;
4673 
4674 	ret_val = e1000e_get_bus_info_pcie(hw);
4675 
4676 	/* ICH devices are "PCI Express"-ish.  They have
4677 	 * a configuration space, but do not contain
4678 	 * PCI Express Capability registers, so bus width
4679 	 * must be hardcoded.
4680 	 */
4681 	if (bus->width == e1000_bus_width_unknown)
4682 		bus->width = e1000_bus_width_pcie_x1;
4683 
4684 	return ret_val;
4685 }
4686 
4687 /**
4688  *  e1000_reset_hw_ich8lan - Reset the hardware
4689  *  @hw: pointer to the HW structure
4690  *
4691  *  Does a full reset of the hardware which includes a reset of the PHY and
4692  *  MAC.
4693  **/
4694 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4695 {
4696 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4697 	u16 kum_cfg;
4698 	u32 ctrl, reg;
4699 	s32 ret_val;
4700 
4701 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
4702 	 * on the last TLP read/write transaction when MAC is reset.
4703 	 */
4704 	ret_val = e1000e_disable_pcie_master(hw);
4705 	if (ret_val)
4706 		e_dbg("PCI-E Master disable polling has failed.\n");
4707 
4708 	e_dbg("Masking off all interrupts\n");
4709 	ew32(IMC, 0xffffffff);
4710 
4711 	/* Disable the Transmit and Receive units.  Then delay to allow
4712 	 * any pending transactions to complete before we hit the MAC
4713 	 * with the global reset.
4714 	 */
4715 	ew32(RCTL, 0);
4716 	ew32(TCTL, E1000_TCTL_PSP);
4717 	e1e_flush();
4718 
4719 	usleep_range(10000, 11000);
4720 
4721 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
4722 	if (hw->mac.type == e1000_ich8lan) {
4723 		/* Set Tx and Rx buffer allocation to 8k apiece. */
4724 		ew32(PBA, E1000_PBA_8K);
4725 		/* Set Packet Buffer Size to 16k. */
4726 		ew32(PBS, E1000_PBS_16K);
4727 	}
4728 
4729 	if (hw->mac.type == e1000_pchlan) {
4730 		/* Save the NVM K1 bit setting */
4731 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4732 		if (ret_val)
4733 			return ret_val;
4734 
4735 		if (kum_cfg & E1000_NVM_K1_ENABLE)
4736 			dev_spec->nvm_k1_enabled = true;
4737 		else
4738 			dev_spec->nvm_k1_enabled = false;
4739 	}
4740 
4741 	ctrl = er32(CTRL);
4742 
4743 	if (!hw->phy.ops.check_reset_block(hw)) {
4744 		/* Full-chip reset requires MAC and PHY reset at the same
4745 		 * time to make sure the interface between MAC and the
4746 		 * external PHY is reset.
4747 		 */
4748 		ctrl |= E1000_CTRL_PHY_RST;
4749 
4750 		/* Gate automatic PHY configuration by hardware on
4751 		 * non-managed 82579
4752 		 */
4753 		if ((hw->mac.type == e1000_pch2lan) &&
4754 		    !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4755 			e1000_gate_hw_phy_config_ich8lan(hw, true);
4756 	}
4757 	ret_val = e1000_acquire_swflag_ich8lan(hw);
4758 	e_dbg("Issuing a global reset to ich8lan\n");
4759 	ew32(CTRL, (ctrl | E1000_CTRL_RST));
4760 	/* cannot issue a flush here because it hangs the hardware */
4761 	msleep(20);
4762 
4763 	/* Set Phy Config Counter to 50msec */
4764 	if (hw->mac.type == e1000_pch2lan) {
4765 		reg = er32(FEXTNVM3);
4766 		reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4767 		reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4768 		ew32(FEXTNVM3, reg);
4769 	}
4770 
4771 	if (!ret_val)
4772 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4773 
4774 	if (ctrl & E1000_CTRL_PHY_RST) {
4775 		ret_val = hw->phy.ops.get_cfg_done(hw);
4776 		if (ret_val)
4777 			return ret_val;
4778 
4779 		ret_val = e1000_post_phy_reset_ich8lan(hw);
4780 		if (ret_val)
4781 			return ret_val;
4782 	}
4783 
4784 	/* For PCH, this write will make sure that any noise
4785 	 * will be detected as a CRC error and be dropped rather than show up
4786 	 * as a bad packet to the DMA engine.
4787 	 */
4788 	if (hw->mac.type == e1000_pchlan)
4789 		ew32(CRC_OFFSET, 0x65656565);
4790 
4791 	ew32(IMC, 0xffffffff);
4792 	er32(ICR);
4793 
4794 	reg = er32(KABGTXD);
4795 	reg |= E1000_KABGTXD_BGSQLBIAS;
4796 	ew32(KABGTXD, reg);
4797 
4798 	return 0;
4799 }
4800 
4801 /**
4802  *  e1000_init_hw_ich8lan - Initialize the hardware
4803  *  @hw: pointer to the HW structure
4804  *
4805  *  Prepares the hardware for transmit and receive by doing the following:
4806  *   - initialize hardware bits
4807  *   - initialize LED identification
4808  *   - setup receive address registers
4809  *   - setup flow control
4810  *   - setup transmit descriptors
4811  *   - clear statistics
4812  **/
4813 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4814 {
4815 	struct e1000_mac_info *mac = &hw->mac;
4816 	u32 ctrl_ext, txdctl, snoop;
4817 	s32 ret_val;
4818 	u16 i;
4819 
4820 	e1000_initialize_hw_bits_ich8lan(hw);
4821 
4822 	/* Initialize identification LED */
4823 	ret_val = mac->ops.id_led_init(hw);
4824 	/* An error is not fatal and we should not stop init due to this */
4825 	if (ret_val)
4826 		e_dbg("Error initializing identification LED\n");
4827 
4828 	/* Setup the receive address. */
4829 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4830 
4831 	/* Zero out the Multicast HASH table */
4832 	e_dbg("Zeroing the MTA\n");
4833 	for (i = 0; i < mac->mta_reg_count; i++)
4834 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4835 
4836 	/* The 82578 Rx buffer will stall if wakeup is enabled in host and
4837 	 * the ME.  Disable wakeup by clearing the host wakeup bit.
4838 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4839 	 */
4840 	if (hw->phy.type == e1000_phy_82578) {
4841 		e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4842 		i &= ~BM_WUC_HOST_WU_BIT;
4843 		e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4844 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
4845 		if (ret_val)
4846 			return ret_val;
4847 	}
4848 
4849 	/* Setup link and flow control */
4850 	ret_val = mac->ops.setup_link(hw);
4851 
4852 	/* Set the transmit descriptor write-back policy for both queues */
4853 	txdctl = er32(TXDCTL(0));
4854 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4855 		  E1000_TXDCTL_FULL_TX_DESC_WB);
4856 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4857 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4858 	ew32(TXDCTL(0), txdctl);
4859 	txdctl = er32(TXDCTL(1));
4860 	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4861 		  E1000_TXDCTL_FULL_TX_DESC_WB);
4862 	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4863 		  E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4864 	ew32(TXDCTL(1), txdctl);
4865 
4866 	/* ICH8 has opposite polarity of no_snoop bits.
4867 	 * By default, we should use snoop behavior.
4868 	 */
4869 	if (mac->type == e1000_ich8lan)
4870 		snoop = PCIE_ICH8_SNOOP_ALL;
4871 	else
4872 		snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4873 	e1000e_set_pcie_no_snoop(hw, snoop);
4874 
4875 	ctrl_ext = er32(CTRL_EXT);
4876 	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4877 	ew32(CTRL_EXT, ctrl_ext);
4878 
4879 	/* Clear all of the statistics registers (clear on read).  It is
4880 	 * important that we do this after we have tried to establish link
4881 	 * because the symbol error count will increment wildly if there
4882 	 * is no link.
4883 	 */
4884 	e1000_clear_hw_cntrs_ich8lan(hw);
4885 
4886 	return ret_val;
4887 }
4888 
4889 /**
4890  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4891  *  @hw: pointer to the HW structure
4892  *
4893  *  Sets/Clears required hardware bits necessary for correctly setting up the
4894  *  hardware for transmit and receive.
4895  **/
4896 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4897 {
4898 	u32 reg;
4899 
4900 	/* Extended Device Control */
4901 	reg = er32(CTRL_EXT);
4902 	reg |= BIT(22);
4903 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
4904 	if (hw->mac.type >= e1000_pchlan)
4905 		reg |= E1000_CTRL_EXT_PHYPDEN;
4906 	ew32(CTRL_EXT, reg);
4907 
4908 	/* Transmit Descriptor Control 0 */
4909 	reg = er32(TXDCTL(0));
4910 	reg |= BIT(22);
4911 	ew32(TXDCTL(0), reg);
4912 
4913 	/* Transmit Descriptor Control 1 */
4914 	reg = er32(TXDCTL(1));
4915 	reg |= BIT(22);
4916 	ew32(TXDCTL(1), reg);
4917 
4918 	/* Transmit Arbitration Control 0 */
4919 	reg = er32(TARC(0));
4920 	if (hw->mac.type == e1000_ich8lan)
4921 		reg |= BIT(28) | BIT(29);
4922 	reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4923 	ew32(TARC(0), reg);
4924 
4925 	/* Transmit Arbitration Control 1 */
4926 	reg = er32(TARC(1));
4927 	if (er32(TCTL) & E1000_TCTL_MULR)
4928 		reg &= ~BIT(28);
4929 	else
4930 		reg |= BIT(28);
4931 	reg |= BIT(24) | BIT(26) | BIT(30);
4932 	ew32(TARC(1), reg);
4933 
4934 	/* Device Status */
4935 	if (hw->mac.type == e1000_ich8lan) {
4936 		reg = er32(STATUS);
4937 		reg &= ~BIT(31);
4938 		ew32(STATUS, reg);
4939 	}
4940 
4941 	/* work-around descriptor data corruption issue during nfs v2 udp
4942 	 * traffic, just disable the nfs filtering capability
4943 	 */
4944 	reg = er32(RFCTL);
4945 	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4946 
4947 	/* Disable IPv6 extension header parsing because some malformed
4948 	 * IPv6 headers can hang the Rx.
4949 	 */
4950 	if (hw->mac.type == e1000_ich8lan)
4951 		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4952 	ew32(RFCTL, reg);
4953 
4954 	/* Enable ECC on Lynxpoint */
4955 	if (hw->mac.type >= e1000_pch_lpt) {
4956 		reg = er32(PBECCSTS);
4957 		reg |= E1000_PBECCSTS_ECC_ENABLE;
4958 		ew32(PBECCSTS, reg);
4959 
4960 		reg = er32(CTRL);
4961 		reg |= E1000_CTRL_MEHE;
4962 		ew32(CTRL, reg);
4963 	}
4964 }
4965 
4966 /**
4967  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4968  *  @hw: pointer to the HW structure
4969  *
4970  *  Determines which flow control settings to use, then configures flow
4971  *  control.  Calls the appropriate media-specific link configuration
4972  *  function.  Assuming the adapter has a valid link partner, a valid link
4973  *  should be established.  Assumes the hardware has previously been reset
4974  *  and the transmitter and receiver are not enabled.
4975  **/
4976 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4977 {
4978 	s32 ret_val;
4979 
4980 	if (hw->phy.ops.check_reset_block(hw))
4981 		return 0;
4982 
4983 	/* ICH parts do not have a word in the NVM to determine
4984 	 * the default flow control setting, so we explicitly
4985 	 * set it to full.
4986 	 */
4987 	if (hw->fc.requested_mode == e1000_fc_default) {
4988 		/* Workaround h/w hang when Tx flow control enabled */
4989 		if (hw->mac.type == e1000_pchlan)
4990 			hw->fc.requested_mode = e1000_fc_rx_pause;
4991 		else
4992 			hw->fc.requested_mode = e1000_fc_full;
4993 	}
4994 
4995 	/* Save off the requested flow control mode for use later.  Depending
4996 	 * on the link partner's capabilities, we may or may not use this mode.
4997 	 */
4998 	hw->fc.current_mode = hw->fc.requested_mode;
4999 
5000 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5001 
5002 	/* Continue to configure the copper link. */
5003 	ret_val = hw->mac.ops.setup_physical_interface(hw);
5004 	if (ret_val)
5005 		return ret_val;
5006 
5007 	ew32(FCTTV, hw->fc.pause_time);
5008 	if ((hw->phy.type == e1000_phy_82578) ||
5009 	    (hw->phy.type == e1000_phy_82579) ||
5010 	    (hw->phy.type == e1000_phy_i217) ||
5011 	    (hw->phy.type == e1000_phy_82577)) {
5012 		ew32(FCRTV_PCH, hw->fc.refresh_time);
5013 
5014 		ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5015 				   hw->fc.pause_time);
5016 		if (ret_val)
5017 			return ret_val;
5018 	}
5019 
5020 	return e1000e_set_fc_watermarks(hw);
5021 }
5022 
5023 /**
5024  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5025  *  @hw: pointer to the HW structure
5026  *
5027  *  Configures the kumeran interface to the PHY to wait the appropriate time
5028  *  when polling the PHY, then call the generic setup_copper_link to finish
5029  *  configuring the copper link.
5030  **/
5031 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5032 {
5033 	u32 ctrl;
5034 	s32 ret_val;
5035 	u16 reg_data;
5036 
5037 	ctrl = er32(CTRL);
5038 	ctrl |= E1000_CTRL_SLU;
5039 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5040 	ew32(CTRL, ctrl);
5041 
5042 	/* Set the mac to wait the maximum time between each iteration
5043 	 * and increase the max iterations when polling the phy;
5044 	 * this fixes erroneous timeouts at 10Mbps.
5045 	 */
5046 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5047 	if (ret_val)
5048 		return ret_val;
5049 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5050 				       &reg_data);
5051 	if (ret_val)
5052 		return ret_val;
5053 	reg_data |= 0x3F;
5054 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5055 					reg_data);
5056 	if (ret_val)
5057 		return ret_val;
5058 
5059 	switch (hw->phy.type) {
5060 	case e1000_phy_igp_3:
5061 		ret_val = e1000e_copper_link_setup_igp(hw);
5062 		if (ret_val)
5063 			return ret_val;
5064 		break;
5065 	case e1000_phy_bm:
5066 	case e1000_phy_82578:
5067 		ret_val = e1000e_copper_link_setup_m88(hw);
5068 		if (ret_val)
5069 			return ret_val;
5070 		break;
5071 	case e1000_phy_82577:
5072 	case e1000_phy_82579:
5073 		ret_val = e1000_copper_link_setup_82577(hw);
5074 		if (ret_val)
5075 			return ret_val;
5076 		break;
5077 	case e1000_phy_ife:
5078 		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5079 		if (ret_val)
5080 			return ret_val;
5081 
5082 		reg_data &= ~IFE_PMC_AUTO_MDIX;
5083 
5084 		switch (hw->phy.mdix) {
5085 		case 1:
5086 			reg_data &= ~IFE_PMC_FORCE_MDIX;
5087 			break;
5088 		case 2:
5089 			reg_data |= IFE_PMC_FORCE_MDIX;
5090 			break;
5091 		case 0:
5092 		default:
5093 			reg_data |= IFE_PMC_AUTO_MDIX;
5094 			break;
5095 		}
5096 		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5097 		if (ret_val)
5098 			return ret_val;
5099 		break;
5100 	default:
5101 		break;
5102 	}
5103 
5104 	return e1000e_setup_copper_link(hw);
5105 }
5106 
5107 /**
5108  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5109  *  @hw: pointer to the HW structure
5110  *
5111  *  Calls the PHY specific link setup function and then calls the
5112  *  generic setup_copper_link to finish configuring the link for
5113  *  Lynxpoint PCH devices
5114  **/
5115 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5116 {
5117 	u32 ctrl;
5118 	s32 ret_val;
5119 
5120 	ctrl = er32(CTRL);
5121 	ctrl |= E1000_CTRL_SLU;
5122 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5123 	ew32(CTRL, ctrl);
5124 
5125 	ret_val = e1000_copper_link_setup_82577(hw);
5126 	if (ret_val)
5127 		return ret_val;
5128 
5129 	return e1000e_setup_copper_link(hw);
5130 }
5131 
5132 /**
5133  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5134  *  @hw: pointer to the HW structure
5135  *  @speed: pointer to store current link speed
5136  *  @duplex: pointer to store the current link duplex
5137  *
5138  *  Calls the generic get_speed_and_duplex to retrieve the current link
5139  *  information and then calls the Kumeran lock loss workaround for links at
5140  *  gigabit speeds.
5141  **/
5142 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5143 					  u16 *duplex)
5144 {
5145 	s32 ret_val;
5146 
5147 	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5148 	if (ret_val)
5149 		return ret_val;
5150 
5151 	if ((hw->mac.type == e1000_ich8lan) &&
5152 	    (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5153 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5154 	}
5155 
5156 	return ret_val;
5157 }
5158 
5159 /**
5160  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5161  *  @hw: pointer to the HW structure
5162  *
5163  *  Work-around for 82566 Kumeran PCS lock loss:
5164  *  On link status change (i.e. PCI reset, speed change) and link is up and
5165  *  speed is gigabit-
5166  *    0) if workaround is optionally disabled do nothing
5167  *    1) wait 1ms for Kumeran link to come up
5168  *    2) check Kumeran Diagnostic register PCS lock loss bit
5169  *    3) if not set the link is locked (all is good), otherwise...
5170  *    4) reset the PHY
5171  *    5) repeat up to 10 times
5172  *  Note: this is only called for IGP3 copper when speed is 1gb.
5173  **/
5174 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5175 {
5176 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5177 	u32 phy_ctrl;
5178 	s32 ret_val;
5179 	u16 i, data;
5180 	bool link;
5181 
5182 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5183 		return 0;
5184 
5185 	/* Make sure link is up before proceeding.  If not just return.
5186 	 * Attempting this while link is negotiating fouled up link
5187 	 * stability
5188 	 */
5189 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5190 	if (!link)
5191 		return 0;
5192 
5193 	for (i = 0; i < 10; i++) {
5194 		/* read once to clear */
5195 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5196 		if (ret_val)
5197 			return ret_val;
5198 		/* and again to get new status */
5199 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5200 		if (ret_val)
5201 			return ret_val;
5202 
5203 		/* check for PCS lock */
5204 		if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5205 			return 0;
5206 
5207 		/* Issue PHY reset */
5208 		e1000_phy_hw_reset(hw);
5209 		mdelay(5);
5210 	}
5211 	/* Disable GigE link negotiation */
5212 	phy_ctrl = er32(PHY_CTRL);
5213 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5214 		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5215 	ew32(PHY_CTRL, phy_ctrl);
5216 
5217 	/* Call gig speed drop workaround on Gig disable before accessing
5218 	 * any PHY registers
5219 	 */
5220 	e1000e_gig_downshift_workaround_ich8lan(hw);
5221 
5222 	/* unable to acquire PCS lock */
5223 	return -E1000_ERR_PHY;
5224 }
5225 
5226 /**
5227  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5228  *  @hw: pointer to the HW structure
5229  *  @state: boolean value used to set the current Kumeran workaround state
5230  *
5231  *  If ICH8, set the current Kumeran workaround state (enabled - true
5232  *  /disabled - false).
5233  **/
5234 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5235 						  bool state)
5236 {
5237 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5238 
5239 	if (hw->mac.type != e1000_ich8lan) {
5240 		e_dbg("Workaround applies to ICH8 only.\n");
5241 		return;
5242 	}
5243 
5244 	dev_spec->kmrn_lock_loss_workaround_enabled = state;
5245 }
5246 
5247 /**
5248  *  e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5249  *  @hw: pointer to the HW structure
5250  *
5251  *  Workaround for 82566 power-down on D3 entry:
5252  *    1) disable gigabit link
5253  *    2) write VR power-down enable
5254  *    3) read it back
5255  *  Continue if successful, else issue LCD reset and repeat
5256  **/
5257 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5258 {
5259 	u32 reg;
5260 	u16 data;
5261 	u8 retry = 0;
5262 
5263 	if (hw->phy.type != e1000_phy_igp_3)
5264 		return;
5265 
5266 	/* Try the workaround twice (if needed) */
5267 	do {
5268 		/* Disable link */
5269 		reg = er32(PHY_CTRL);
5270 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5271 			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5272 		ew32(PHY_CTRL, reg);
5273 
5274 		/* Call gig speed drop workaround on Gig disable before
5275 		 * accessing any PHY registers
5276 		 */
5277 		if (hw->mac.type == e1000_ich8lan)
5278 			e1000e_gig_downshift_workaround_ich8lan(hw);
5279 
5280 		/* Write VR power-down enable */
5281 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
5282 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5283 		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5284 
5285 		/* Read it back and test */
5286 		e1e_rphy(hw, IGP3_VR_CTRL, &data);
5287 		data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5288 		if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5289 			break;
5290 
5291 		/* Issue PHY reset and repeat at most one more time */
5292 		reg = er32(CTRL);
5293 		ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5294 		retry++;
5295 	} while (retry);
5296 }
5297 
5298 /**
5299  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5300  *  @hw: pointer to the HW structure
5301  *
5302  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5303  *  LPLU, Gig disable, MDIC PHY reset):
5304  *    1) Set Kumeran Near-end loopback
5305  *    2) Clear Kumeran Near-end loopback
5306  *  Should only be called for ICH8[m] devices with any 1G Phy.
5307  **/
5308 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5309 {
5310 	s32 ret_val;
5311 	u16 reg_data;
5312 
5313 	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5314 		return;
5315 
5316 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5317 				       &reg_data);
5318 	if (ret_val)
5319 		return;
5320 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5321 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5322 					reg_data);
5323 	if (ret_val)
5324 		return;
5325 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5326 	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5327 }
5328 
5329 /**
5330  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5331  *  @hw: pointer to the HW structure
5332  *
5333  *  During S0 to Sx transition, it is possible the link remains at gig
5334  *  instead of negotiating to a lower speed.  Before going to Sx, set
5335  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5336  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5337  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5338  *  needs to be written.
5339  *  Parts that support (and are linked to a partner which support) EEE in
5340  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5341  *  than 10Mbps w/o EEE.
5342  **/
5343 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5344 {
5345 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5346 	u32 phy_ctrl;
5347 	s32 ret_val;
5348 
5349 	phy_ctrl = er32(PHY_CTRL);
5350 	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5351 
5352 	if (hw->phy.type == e1000_phy_i217) {
5353 		u16 phy_reg, device_id = hw->adapter->pdev->device;
5354 
5355 		if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5356 		    (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5357 		    (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5358 		    (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5359 		    (hw->mac.type >= e1000_pch_spt)) {
5360 			u32 fextnvm6 = er32(FEXTNVM6);
5361 
5362 			ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5363 		}
5364 
5365 		ret_val = hw->phy.ops.acquire(hw);
5366 		if (ret_val)
5367 			goto out;
5368 
5369 		if (!dev_spec->eee_disable) {
5370 			u16 eee_advert;
5371 
5372 			ret_val =
5373 			    e1000_read_emi_reg_locked(hw,
5374 						      I217_EEE_ADVERTISEMENT,
5375 						      &eee_advert);
5376 			if (ret_val)
5377 				goto release;
5378 
5379 			/* Disable LPLU if both link partners support 100BaseT
5380 			 * EEE and 100Full is advertised on both ends of the
5381 			 * link, and enable Auto Enable LPI since there will
5382 			 * be no driver to enable LPI while in Sx.
5383 			 */
5384 			if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5385 			    (dev_spec->eee_lp_ability &
5386 			     I82579_EEE_100_SUPPORTED) &&
5387 			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5388 				phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5389 					      E1000_PHY_CTRL_NOND0A_LPLU);
5390 
5391 				/* Set Auto Enable LPI after link up */
5392 				e1e_rphy_locked(hw,
5393 						I217_LPI_GPIO_CTRL, &phy_reg);
5394 				phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5395 				e1e_wphy_locked(hw,
5396 						I217_LPI_GPIO_CTRL, phy_reg);
5397 			}
5398 		}
5399 
5400 		/* For i217 Intel Rapid Start Technology support,
5401 		 * when the system is going into Sx and no manageability engine
5402 		 * is present, the driver must configure proxy to reset only on
5403 		 * power good.  LPI (Low Power Idle) state must also reset only
5404 		 * on power good, as well as the MTA (Multicast table array).
5405 		 * The SMBus release must also be disabled on LCD reset.
5406 		 */
5407 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5408 			/* Enable proxy to reset only on power good. */
5409 			e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5410 			phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5411 			e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5412 
5413 			/* Set bit enable LPI (EEE) to reset only on
5414 			 * power good.
5415 			 */
5416 			e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5417 			phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5418 			e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5419 
5420 			/* Disable the SMB release on LCD reset. */
5421 			e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5422 			phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5423 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5424 		}
5425 
5426 		/* Enable MTA to reset for Intel Rapid Start Technology
5427 		 * Support
5428 		 */
5429 		e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5430 		phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5431 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5432 
5433 release:
5434 		hw->phy.ops.release(hw);
5435 	}
5436 out:
5437 	ew32(PHY_CTRL, phy_ctrl);
5438 
5439 	if (hw->mac.type == e1000_ich8lan)
5440 		e1000e_gig_downshift_workaround_ich8lan(hw);
5441 
5442 	if (hw->mac.type >= e1000_pchlan) {
5443 		e1000_oem_bits_config_ich8lan(hw, false);
5444 
5445 		/* Reset PHY to activate OEM bits on 82577/8 */
5446 		if (hw->mac.type == e1000_pchlan)
5447 			e1000e_phy_hw_reset_generic(hw);
5448 
5449 		ret_val = hw->phy.ops.acquire(hw);
5450 		if (ret_val)
5451 			return;
5452 		e1000_write_smbus_addr(hw);
5453 		hw->phy.ops.release(hw);
5454 	}
5455 }
5456 
5457 /**
5458  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5459  *  @hw: pointer to the HW structure
5460  *
5461  *  During Sx to S0 transitions on non-managed devices or managed devices
5462  *  on which PHY resets are not blocked, if the PHY registers cannot be
5463  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5464  *  the PHY.
5465  *  On i217, setup Intel Rapid Start Technology.
5466  **/
5467 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5468 {
5469 	s32 ret_val;
5470 
5471 	if (hw->mac.type < e1000_pch2lan)
5472 		return;
5473 
5474 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
5475 	if (ret_val) {
5476 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5477 		return;
5478 	}
5479 
5480 	/* For i217 Intel Rapid Start Technology support when the system
5481 	 * is transitioning from Sx and no manageability engine is present
5482 	 * configure SMBus to restore on reset, disable proxy, and enable
5483 	 * the reset on MTA (Multicast table array).
5484 	 */
5485 	if (hw->phy.type == e1000_phy_i217) {
5486 		u16 phy_reg;
5487 
5488 		ret_val = hw->phy.ops.acquire(hw);
5489 		if (ret_val) {
5490 			e_dbg("Failed to setup iRST\n");
5491 			return;
5492 		}
5493 
5494 		/* Clear Auto Enable LPI after link up */
5495 		e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5496 		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5497 		e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5498 
5499 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5500 			/* Restore clear on SMB if no manageability engine
5501 			 * is present
5502 			 */
5503 			ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5504 			if (ret_val)
5505 				goto release;
5506 			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5507 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5508 
5509 			/* Disable Proxy */
5510 			e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5511 		}
5512 		/* Enable reset on MTA */
5513 		ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5514 		if (ret_val)
5515 			goto release;
5516 		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5517 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5518 release:
5519 		if (ret_val)
5520 			e_dbg("Error %d in resume workarounds\n", ret_val);
5521 		hw->phy.ops.release(hw);
5522 	}
5523 }
5524 
5525 /**
5526  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5527  *  @hw: pointer to the HW structure
5528  *
5529  *  Return the LED back to the default configuration.
5530  **/
5531 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5532 {
5533 	if (hw->phy.type == e1000_phy_ife)
5534 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5535 
5536 	ew32(LEDCTL, hw->mac.ledctl_default);
5537 	return 0;
5538 }
5539 
5540 /**
5541  *  e1000_led_on_ich8lan - Turn LEDs on
5542  *  @hw: pointer to the HW structure
5543  *
5544  *  Turn on the LEDs.
5545  **/
5546 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5547 {
5548 	if (hw->phy.type == e1000_phy_ife)
5549 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5550 				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5551 
5552 	ew32(LEDCTL, hw->mac.ledctl_mode2);
5553 	return 0;
5554 }
5555 
5556 /**
5557  *  e1000_led_off_ich8lan - Turn LEDs off
5558  *  @hw: pointer to the HW structure
5559  *
5560  *  Turn off the LEDs.
5561  **/
5562 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5563 {
5564 	if (hw->phy.type == e1000_phy_ife)
5565 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5566 				(IFE_PSCL_PROBE_MODE |
5567 				 IFE_PSCL_PROBE_LEDS_OFF));
5568 
5569 	ew32(LEDCTL, hw->mac.ledctl_mode1);
5570 	return 0;
5571 }
5572 
5573 /**
5574  *  e1000_setup_led_pchlan - Configures SW controllable LED
5575  *  @hw: pointer to the HW structure
5576  *
5577  *  This prepares the SW controllable LED for use.
5578  **/
5579 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5580 {
5581 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5582 }
5583 
5584 /**
5585  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5586  *  @hw: pointer to the HW structure
5587  *
5588  *  Return the LED back to the default configuration.
5589  **/
5590 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5591 {
5592 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5593 }
5594 
5595 /**
5596  *  e1000_led_on_pchlan - Turn LEDs on
5597  *  @hw: pointer to the HW structure
5598  *
5599  *  Turn on the LEDs.
5600  **/
5601 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5602 {
5603 	u16 data = (u16)hw->mac.ledctl_mode2;
5604 	u32 i, led;
5605 
5606 	/* If no link, then turn LED on by setting the invert bit
5607 	 * for each LED that's mode is "link_up" in ledctl_mode2.
5608 	 */
5609 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5610 		for (i = 0; i < 3; i++) {
5611 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5612 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
5613 			    E1000_LEDCTL_MODE_LINK_UP)
5614 				continue;
5615 			if (led & E1000_PHY_LED0_IVRT)
5616 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5617 			else
5618 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
5619 		}
5620 	}
5621 
5622 	return e1e_wphy(hw, HV_LED_CONFIG, data);
5623 }
5624 
5625 /**
5626  *  e1000_led_off_pchlan - Turn LEDs off
5627  *  @hw: pointer to the HW structure
5628  *
5629  *  Turn off the LEDs.
5630  **/
5631 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5632 {
5633 	u16 data = (u16)hw->mac.ledctl_mode1;
5634 	u32 i, led;
5635 
5636 	/* If no link, then turn LED off by clearing the invert bit
5637 	 * for each LED that's mode is "link_up" in ledctl_mode1.
5638 	 */
5639 	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5640 		for (i = 0; i < 3; i++) {
5641 			led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5642 			if ((led & E1000_PHY_LED0_MODE_MASK) !=
5643 			    E1000_LEDCTL_MODE_LINK_UP)
5644 				continue;
5645 			if (led & E1000_PHY_LED0_IVRT)
5646 				data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5647 			else
5648 				data |= (E1000_PHY_LED0_IVRT << (i * 5));
5649 		}
5650 	}
5651 
5652 	return e1e_wphy(hw, HV_LED_CONFIG, data);
5653 }
5654 
5655 /**
5656  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5657  *  @hw: pointer to the HW structure
5658  *
5659  *  Read appropriate register for the config done bit for completion status
5660  *  and configure the PHY through s/w for EEPROM-less parts.
5661  *
5662  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5663  *  config done bit, so only an error is logged and continues.  If we were
5664  *  to return with error, EEPROM-less silicon would not be able to be reset
5665  *  or change link.
5666  **/
5667 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5668 {
5669 	s32 ret_val = 0;
5670 	u32 bank = 0;
5671 	u32 status;
5672 
5673 	e1000e_get_cfg_done_generic(hw);
5674 
5675 	/* Wait for indication from h/w that it has completed basic config */
5676 	if (hw->mac.type >= e1000_ich10lan) {
5677 		e1000_lan_init_done_ich8lan(hw);
5678 	} else {
5679 		ret_val = e1000e_get_auto_rd_done(hw);
5680 		if (ret_val) {
5681 			/* When auto config read does not complete, do not
5682 			 * return with an error. This can happen in situations
5683 			 * where there is no eeprom and prevents getting link.
5684 			 */
5685 			e_dbg("Auto Read Done did not complete\n");
5686 			ret_val = 0;
5687 		}
5688 	}
5689 
5690 	/* Clear PHY Reset Asserted bit */
5691 	status = er32(STATUS);
5692 	if (status & E1000_STATUS_PHYRA)
5693 		ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5694 	else
5695 		e_dbg("PHY Reset Asserted not set - needs delay\n");
5696 
5697 	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
5698 	if (hw->mac.type <= e1000_ich9lan) {
5699 		if (!(er32(EECD) & E1000_EECD_PRES) &&
5700 		    (hw->phy.type == e1000_phy_igp_3)) {
5701 			e1000e_phy_init_script_igp3(hw);
5702 		}
5703 	} else {
5704 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5705 			/* Maybe we should do a basic PHY config */
5706 			e_dbg("EEPROM not present\n");
5707 			ret_val = -E1000_ERR_CONFIG;
5708 		}
5709 	}
5710 
5711 	return ret_val;
5712 }
5713 
5714 /**
5715  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5716  * @hw: pointer to the HW structure
5717  *
5718  * In the case of a PHY power down to save power, or to turn off link during a
5719  * driver unload, or wake on lan is not enabled, remove the link.
5720  **/
5721 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5722 {
5723 	/* If the management interface is not enabled, then power down */
5724 	if (!(hw->mac.ops.check_mng_mode(hw) ||
5725 	      hw->phy.ops.check_reset_block(hw)))
5726 		e1000_power_down_phy_copper(hw);
5727 }
5728 
5729 /**
5730  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5731  *  @hw: pointer to the HW structure
5732  *
5733  *  Clears hardware counters specific to the silicon family and calls
5734  *  clear_hw_cntrs_generic to clear all general purpose counters.
5735  **/
5736 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5737 {
5738 	u16 phy_data;
5739 	s32 ret_val;
5740 
5741 	e1000e_clear_hw_cntrs_base(hw);
5742 
5743 	er32(ALGNERRC);
5744 	er32(RXERRC);
5745 	er32(TNCRS);
5746 	er32(CEXTERR);
5747 	er32(TSCTC);
5748 	er32(TSCTFC);
5749 
5750 	er32(MGTPRC);
5751 	er32(MGTPDC);
5752 	er32(MGTPTC);
5753 
5754 	er32(IAC);
5755 	er32(ICRXOC);
5756 
5757 	/* Clear PHY statistics registers */
5758 	if ((hw->phy.type == e1000_phy_82578) ||
5759 	    (hw->phy.type == e1000_phy_82579) ||
5760 	    (hw->phy.type == e1000_phy_i217) ||
5761 	    (hw->phy.type == e1000_phy_82577)) {
5762 		ret_val = hw->phy.ops.acquire(hw);
5763 		if (ret_val)
5764 			return;
5765 		ret_val = hw->phy.ops.set_page(hw,
5766 					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
5767 		if (ret_val)
5768 			goto release;
5769 		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5770 		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5771 		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5772 		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5773 		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5774 		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5775 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5776 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5777 		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5778 		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5779 		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5780 		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5781 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5782 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5783 release:
5784 		hw->phy.ops.release(hw);
5785 	}
5786 }
5787 
5788 static const struct e1000_mac_operations ich8_mac_ops = {
5789 	/* check_mng_mode dependent on mac type */
5790 	.check_for_link		= e1000_check_for_copper_link_ich8lan,
5791 	/* cleanup_led dependent on mac type */
5792 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_ich8lan,
5793 	.get_bus_info		= e1000_get_bus_info_ich8lan,
5794 	.set_lan_id		= e1000_set_lan_id_single_port,
5795 	.get_link_up_info	= e1000_get_link_up_info_ich8lan,
5796 	/* led_on dependent on mac type */
5797 	/* led_off dependent on mac type */
5798 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
5799 	.reset_hw		= e1000_reset_hw_ich8lan,
5800 	.init_hw		= e1000_init_hw_ich8lan,
5801 	.setup_link		= e1000_setup_link_ich8lan,
5802 	.setup_physical_interface = e1000_setup_copper_link_ich8lan,
5803 	/* id_led_init dependent on mac type */
5804 	.config_collision_dist	= e1000e_config_collision_dist_generic,
5805 	.rar_set		= e1000e_rar_set_generic,
5806 	.rar_get_count		= e1000e_rar_get_count_generic,
5807 };
5808 
5809 static const struct e1000_phy_operations ich8_phy_ops = {
5810 	.acquire		= e1000_acquire_swflag_ich8lan,
5811 	.check_reset_block	= e1000_check_reset_block_ich8lan,
5812 	.commit			= NULL,
5813 	.get_cfg_done		= e1000_get_cfg_done_ich8lan,
5814 	.get_cable_length	= e1000e_get_cable_length_igp_2,
5815 	.read_reg		= e1000e_read_phy_reg_igp,
5816 	.release		= e1000_release_swflag_ich8lan,
5817 	.reset			= e1000_phy_hw_reset_ich8lan,
5818 	.set_d0_lplu_state	= e1000_set_d0_lplu_state_ich8lan,
5819 	.set_d3_lplu_state	= e1000_set_d3_lplu_state_ich8lan,
5820 	.write_reg		= e1000e_write_phy_reg_igp,
5821 };
5822 
5823 static const struct e1000_nvm_operations ich8_nvm_ops = {
5824 	.acquire		= e1000_acquire_nvm_ich8lan,
5825 	.read			= e1000_read_nvm_ich8lan,
5826 	.release		= e1000_release_nvm_ich8lan,
5827 	.reload			= e1000e_reload_nvm_generic,
5828 	.update			= e1000_update_nvm_checksum_ich8lan,
5829 	.valid_led_default	= e1000_valid_led_default_ich8lan,
5830 	.validate		= e1000_validate_nvm_checksum_ich8lan,
5831 	.write			= e1000_write_nvm_ich8lan,
5832 };
5833 
5834 static const struct e1000_nvm_operations spt_nvm_ops = {
5835 	.acquire		= e1000_acquire_nvm_ich8lan,
5836 	.release		= e1000_release_nvm_ich8lan,
5837 	.read			= e1000_read_nvm_spt,
5838 	.update			= e1000_update_nvm_checksum_spt,
5839 	.reload			= e1000e_reload_nvm_generic,
5840 	.valid_led_default	= e1000_valid_led_default_ich8lan,
5841 	.validate		= e1000_validate_nvm_checksum_ich8lan,
5842 	.write			= e1000_write_nvm_ich8lan,
5843 };
5844 
5845 const struct e1000_info e1000_ich8_info = {
5846 	.mac			= e1000_ich8lan,
5847 	.flags			= FLAG_HAS_WOL
5848 				  | FLAG_IS_ICH
5849 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5850 				  | FLAG_HAS_AMT
5851 				  | FLAG_HAS_FLASH
5852 				  | FLAG_APME_IN_WUC,
5853 	.pba			= 8,
5854 	.max_hw_frame_size	= VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5855 	.get_variants		= e1000_get_variants_ich8lan,
5856 	.mac_ops		= &ich8_mac_ops,
5857 	.phy_ops		= &ich8_phy_ops,
5858 	.nvm_ops		= &ich8_nvm_ops,
5859 };
5860 
5861 const struct e1000_info e1000_ich9_info = {
5862 	.mac			= e1000_ich9lan,
5863 	.flags			= FLAG_HAS_JUMBO_FRAMES
5864 				  | FLAG_IS_ICH
5865 				  | FLAG_HAS_WOL
5866 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5867 				  | FLAG_HAS_AMT
5868 				  | FLAG_HAS_FLASH
5869 				  | FLAG_APME_IN_WUC,
5870 	.pba			= 18,
5871 	.max_hw_frame_size	= DEFAULT_JUMBO,
5872 	.get_variants		= e1000_get_variants_ich8lan,
5873 	.mac_ops		= &ich8_mac_ops,
5874 	.phy_ops		= &ich8_phy_ops,
5875 	.nvm_ops		= &ich8_nvm_ops,
5876 };
5877 
5878 const struct e1000_info e1000_ich10_info = {
5879 	.mac			= e1000_ich10lan,
5880 	.flags			= FLAG_HAS_JUMBO_FRAMES
5881 				  | FLAG_IS_ICH
5882 				  | FLAG_HAS_WOL
5883 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5884 				  | FLAG_HAS_AMT
5885 				  | FLAG_HAS_FLASH
5886 				  | FLAG_APME_IN_WUC,
5887 	.pba			= 18,
5888 	.max_hw_frame_size	= DEFAULT_JUMBO,
5889 	.get_variants		= e1000_get_variants_ich8lan,
5890 	.mac_ops		= &ich8_mac_ops,
5891 	.phy_ops		= &ich8_phy_ops,
5892 	.nvm_ops		= &ich8_nvm_ops,
5893 };
5894 
5895 const struct e1000_info e1000_pch_info = {
5896 	.mac			= e1000_pchlan,
5897 	.flags			= FLAG_IS_ICH
5898 				  | FLAG_HAS_WOL
5899 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5900 				  | FLAG_HAS_AMT
5901 				  | FLAG_HAS_FLASH
5902 				  | FLAG_HAS_JUMBO_FRAMES
5903 				  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5904 				  | FLAG_APME_IN_WUC,
5905 	.flags2			= FLAG2_HAS_PHY_STATS,
5906 	.pba			= 26,
5907 	.max_hw_frame_size	= 4096,
5908 	.get_variants		= e1000_get_variants_ich8lan,
5909 	.mac_ops		= &ich8_mac_ops,
5910 	.phy_ops		= &ich8_phy_ops,
5911 	.nvm_ops		= &ich8_nvm_ops,
5912 };
5913 
5914 const struct e1000_info e1000_pch2_info = {
5915 	.mac			= e1000_pch2lan,
5916 	.flags			= FLAG_IS_ICH
5917 				  | FLAG_HAS_WOL
5918 				  | FLAG_HAS_HW_TIMESTAMP
5919 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5920 				  | FLAG_HAS_AMT
5921 				  | FLAG_HAS_FLASH
5922 				  | FLAG_HAS_JUMBO_FRAMES
5923 				  | FLAG_APME_IN_WUC,
5924 	.flags2			= FLAG2_HAS_PHY_STATS
5925 				  | FLAG2_HAS_EEE
5926 				  | FLAG2_CHECK_SYSTIM_OVERFLOW,
5927 	.pba			= 26,
5928 	.max_hw_frame_size	= 9022,
5929 	.get_variants		= e1000_get_variants_ich8lan,
5930 	.mac_ops		= &ich8_mac_ops,
5931 	.phy_ops		= &ich8_phy_ops,
5932 	.nvm_ops		= &ich8_nvm_ops,
5933 };
5934 
5935 const struct e1000_info e1000_pch_lpt_info = {
5936 	.mac			= e1000_pch_lpt,
5937 	.flags			= FLAG_IS_ICH
5938 				  | FLAG_HAS_WOL
5939 				  | FLAG_HAS_HW_TIMESTAMP
5940 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5941 				  | FLAG_HAS_AMT
5942 				  | FLAG_HAS_FLASH
5943 				  | FLAG_HAS_JUMBO_FRAMES
5944 				  | FLAG_APME_IN_WUC,
5945 	.flags2			= FLAG2_HAS_PHY_STATS
5946 				  | FLAG2_HAS_EEE
5947 				  | FLAG2_CHECK_SYSTIM_OVERFLOW,
5948 	.pba			= 26,
5949 	.max_hw_frame_size	= 9022,
5950 	.get_variants		= e1000_get_variants_ich8lan,
5951 	.mac_ops		= &ich8_mac_ops,
5952 	.phy_ops		= &ich8_phy_ops,
5953 	.nvm_ops		= &ich8_nvm_ops,
5954 };
5955 
5956 const struct e1000_info e1000_pch_spt_info = {
5957 	.mac			= e1000_pch_spt,
5958 	.flags			= FLAG_IS_ICH
5959 				  | FLAG_HAS_WOL
5960 				  | FLAG_HAS_HW_TIMESTAMP
5961 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5962 				  | FLAG_HAS_AMT
5963 				  | FLAG_HAS_FLASH
5964 				  | FLAG_HAS_JUMBO_FRAMES
5965 				  | FLAG_APME_IN_WUC,
5966 	.flags2			= FLAG2_HAS_PHY_STATS
5967 				  | FLAG2_HAS_EEE,
5968 	.pba			= 26,
5969 	.max_hw_frame_size	= 9022,
5970 	.get_variants		= e1000_get_variants_ich8lan,
5971 	.mac_ops		= &ich8_mac_ops,
5972 	.phy_ops		= &ich8_phy_ops,
5973 	.nvm_ops		= &spt_nvm_ops,
5974 };
5975 
5976 const struct e1000_info e1000_pch_cnp_info = {
5977 	.mac			= e1000_pch_cnp,
5978 	.flags			= FLAG_IS_ICH
5979 				  | FLAG_HAS_WOL
5980 				  | FLAG_HAS_HW_TIMESTAMP
5981 				  | FLAG_HAS_CTRLEXT_ON_LOAD
5982 				  | FLAG_HAS_AMT
5983 				  | FLAG_HAS_FLASH
5984 				  | FLAG_HAS_JUMBO_FRAMES
5985 				  | FLAG_APME_IN_WUC,
5986 	.flags2			= FLAG2_HAS_PHY_STATS
5987 				  | FLAG2_HAS_EEE,
5988 	.pba			= 26,
5989 	.max_hw_frame_size	= 9022,
5990 	.get_variants		= e1000_get_variants_ich8lan,
5991 	.mac_ops		= &ich8_mac_ops,
5992 	.phy_ops		= &ich8_phy_ops,
5993 	.nvm_ops		= &spt_nvm_ops,
5994 };
5995