1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 #ifndef _E1000_DEFINES_H_ 24 #define _E1000_DEFINES_H_ 25 26 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 27 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 28 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 29 30 /* Definitions for power management and wakeup registers */ 31 /* Wake Up Control */ 32 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 33 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 34 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 35 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 36 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 37 38 /* Wake Up Filter Control */ 39 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 40 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 41 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 42 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 43 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 44 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 45 46 /* Wake Up Status */ 47 #define E1000_WUS_LNKC E1000_WUFC_LNKC 48 #define E1000_WUS_MAG E1000_WUFC_MAG 49 #define E1000_WUS_EX E1000_WUFC_EX 50 #define E1000_WUS_MC E1000_WUFC_MC 51 #define E1000_WUS_BC E1000_WUFC_BC 52 53 /* Extended Device Control */ 54 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 55 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 56 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 57 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 58 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 59 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 60 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 61 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 62 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 63 #define E1000_CTRL_EXT_EIAME 0x01000000 64 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 65 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 66 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 67 #define E1000_CTRL_EXT_LSECCK 0x00001000 68 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 69 70 /* Receive Descriptor bit definitions */ 71 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 72 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 73 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 74 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 75 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 76 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 77 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 78 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 79 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 80 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 81 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 82 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 83 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 84 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 85 86 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 87 #define E1000_RXDEXT_STATERR_CE 0x01000000 88 #define E1000_RXDEXT_STATERR_SE 0x02000000 89 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 90 #define E1000_RXDEXT_STATERR_CXE 0x10000000 91 #define E1000_RXDEXT_STATERR_RXE 0x80000000 92 93 /* mask to determine if packets should be dropped due to frame errors */ 94 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 95 E1000_RXD_ERR_CE | \ 96 E1000_RXD_ERR_SE | \ 97 E1000_RXD_ERR_SEQ | \ 98 E1000_RXD_ERR_CXE | \ 99 E1000_RXD_ERR_RXE) 100 101 /* Same mask, but for extended and packet split descriptors */ 102 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 103 E1000_RXDEXT_STATERR_CE | \ 104 E1000_RXDEXT_STATERR_SE | \ 105 E1000_RXDEXT_STATERR_SEQ | \ 106 E1000_RXDEXT_STATERR_CXE | \ 107 E1000_RXDEXT_STATERR_RXE) 108 109 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 110 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 111 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 112 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 113 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 114 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 115 116 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 117 118 /* Management Control */ 119 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 120 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 121 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 122 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 123 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 124 /* Enable MAC address filtering */ 125 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 126 /* Enable MNG packets to host memory */ 127 #define E1000_MANC_EN_MNG2HOST 0x00200000 128 129 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 130 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 131 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 132 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 133 134 /* Receive Control */ 135 #define E1000_RCTL_EN 0x00000002 /* enable */ 136 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 137 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 138 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 139 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 140 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 141 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 142 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 143 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 144 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 145 #define E1000_RCTL_RDMTS_HEX 0x00010000 146 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 147 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 148 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 149 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 150 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 151 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 152 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 153 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 154 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 155 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 156 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 157 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 158 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 159 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 160 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 161 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 162 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 163 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 164 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 165 166 /* Use byte values for the following shift parameters 167 * Usage: 168 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 169 * E1000_PSRCTL_BSIZE0_MASK) | 170 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 171 * E1000_PSRCTL_BSIZE1_MASK) | 172 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 173 * E1000_PSRCTL_BSIZE2_MASK) | 174 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 175 * E1000_PSRCTL_BSIZE3_MASK)) 176 * where value0 = [128..16256], default=256 177 * value1 = [1024..64512], default=4096 178 * value2 = [0..64512], default=4096 179 * value3 = [0..64512], default=0 180 */ 181 182 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 183 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 184 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 185 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 186 187 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 188 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 189 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 190 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 191 192 /* SWFW_SYNC Definitions */ 193 #define E1000_SWFW_EEP_SM 0x1 194 #define E1000_SWFW_PHY0_SM 0x2 195 #define E1000_SWFW_PHY1_SM 0x4 196 #define E1000_SWFW_CSR_SM 0x8 197 198 /* Device Control */ 199 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 200 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 201 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 202 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 203 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 204 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 205 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 206 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 207 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 208 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 209 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 210 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 211 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 212 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 213 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 214 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 215 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 216 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 217 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 218 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 219 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 220 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 221 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 222 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 223 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 224 225 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 226 227 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 228 229 /* Device Status */ 230 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 231 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 232 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 233 #define E1000_STATUS_FUNC_SHIFT 2 234 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 235 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 236 #define E1000_STATUS_SPEED_MASK 0x000000C0 237 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 238 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 239 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 240 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 241 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 242 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */ 243 244 #define HALF_DUPLEX 1 245 #define FULL_DUPLEX 2 246 247 #define ADVERTISE_10_HALF 0x0001 248 #define ADVERTISE_10_FULL 0x0002 249 #define ADVERTISE_100_HALF 0x0004 250 #define ADVERTISE_100_FULL 0x0008 251 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 252 #define ADVERTISE_1000_FULL 0x0020 253 254 /* 1000/H is not supported, nor spec-compliant. */ 255 #define E1000_ALL_SPEED_DUPLEX ( \ 256 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 257 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 258 #define E1000_ALL_NOT_GIG ( \ 259 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 260 ADVERTISE_100_FULL) 261 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 262 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 263 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 264 265 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 266 267 /* LED Control */ 268 #define E1000_PHY_LED0_MODE_MASK 0x00000007 269 #define E1000_PHY_LED0_IVRT 0x00000008 270 #define E1000_PHY_LED0_MASK 0x0000001F 271 272 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 273 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 274 #define E1000_LEDCTL_LED0_IVRT 0x00000040 275 #define E1000_LEDCTL_LED0_BLINK 0x00000080 276 277 #define E1000_LEDCTL_MODE_LINK_UP 0x2 278 #define E1000_LEDCTL_MODE_LED_ON 0xE 279 #define E1000_LEDCTL_MODE_LED_OFF 0xF 280 281 /* Transmit Descriptor bit definitions */ 282 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 283 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 284 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 285 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 286 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 287 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 288 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 289 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 290 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 291 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 292 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 293 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 294 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 295 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 296 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 297 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 298 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 299 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 300 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 301 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 302 303 /* Transmit Control */ 304 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 305 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 306 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 307 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 308 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 309 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 310 311 /* SerDes Control */ 312 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 313 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 314 315 /* Receive Checksum Control */ 316 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 317 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 318 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 319 320 /* Header split receive */ 321 #define E1000_RFCTL_NFSW_DIS 0x00000040 322 #define E1000_RFCTL_NFSR_DIS 0x00000080 323 #define E1000_RFCTL_ACK_DIS 0x00001000 324 #define E1000_RFCTL_EXTEN 0x00008000 325 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 326 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 327 328 /* Collision related configuration parameters */ 329 #define E1000_COLLISION_THRESHOLD 15 330 #define E1000_CT_SHIFT 4 331 #define E1000_COLLISION_DISTANCE 63 332 #define E1000_COLD_SHIFT 12 333 334 /* Default values for the transmit IPG register */ 335 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 336 337 #define E1000_TIPG_IPGT_MASK 0x000003FF 338 339 #define DEFAULT_82543_TIPG_IPGR1 8 340 #define E1000_TIPG_IPGR1_SHIFT 10 341 342 #define DEFAULT_82543_TIPG_IPGR2 6 343 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 344 #define E1000_TIPG_IPGR2_SHIFT 20 345 346 #define MAX_JUMBO_FRAME_SIZE 0x3F00 347 #define E1000_TX_PTR_GAP 0x1F 348 349 /* Extended Configuration Control and Size */ 350 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 351 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 352 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 353 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 354 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 355 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 356 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 357 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 358 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 359 360 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 361 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 362 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 363 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 364 365 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 366 367 /* Low Power IDLE Control */ 368 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 369 370 /* PBA constants */ 371 #define E1000_PBA_8K 0x0008 /* 8KB */ 372 #define E1000_PBA_16K 0x0010 /* 16KB */ 373 374 #define E1000_PBA_RXA_MASK 0xFFFF 375 376 #define E1000_PBS_16K E1000_PBA_16K 377 378 /* Uncorrectable/correctable ECC Error counts and enable bits */ 379 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 380 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 381 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 382 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 383 384 #define IFS_MAX 80 385 #define IFS_MIN 40 386 #define IFS_RATIO 4 387 #define IFS_STEP 10 388 #define MIN_NUM_XMITS 1000 389 390 /* SW Semaphore Register */ 391 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 392 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 393 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 394 395 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 396 397 /* Interrupt Cause Read */ 398 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 399 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 400 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 401 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 402 #define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */ 403 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 404 #define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */ 405 #define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */ 406 #define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */ 407 #define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */ 408 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 409 /* If this bit asserted, the driver should claim the interrupt */ 410 #define E1000_ICR_INT_ASSERTED 0x80000000 411 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 412 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 413 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 414 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 415 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */ 416 417 /* PBA ECC Register */ 418 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 419 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 420 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 421 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 422 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 423 424 /* This defines the bits that are set in the Interrupt Mask 425 * Set/Read Register. Each bit is documented below: 426 * o RXT0 = Receiver Timer Interrupt (ring 0) 427 * o TXDW = Transmit Descriptor Written Back 428 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 429 * o RXSEQ = Receive Sequence Error 430 * o LSC = Link Status Change 431 */ 432 #define IMS_ENABLE_MASK ( \ 433 E1000_IMS_RXT0 | \ 434 E1000_IMS_TXDW | \ 435 E1000_IMS_RXDMT0 | \ 436 E1000_IMS_RXSEQ | \ 437 E1000_IMS_LSC) 438 439 /* These are all of the events related to the OTHER interrupt. 440 */ 441 #define IMS_OTHER_MASK ( \ 442 E1000_IMS_LSC | \ 443 E1000_IMS_RXO | \ 444 E1000_IMS_MDAC | \ 445 E1000_IMS_SRPD | \ 446 E1000_IMS_ACK | \ 447 E1000_IMS_MNG) 448 449 /* Interrupt Mask Set */ 450 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 451 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 452 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 453 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 454 #define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */ 455 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 456 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */ 457 #define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */ 458 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */ 459 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */ 460 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 461 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 462 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 463 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 464 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 465 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 466 467 /* Interrupt Cause Set */ 468 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 469 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 470 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 471 #define E1000_ICS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 472 473 /* Transmit Descriptor Control */ 474 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 475 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 476 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 477 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 478 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 479 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 480 /* Enable the counting of desc. still to be processed. */ 481 #define E1000_TXDCTL_COUNT_DESC 0x00400000 482 483 /* Flow Control Constants */ 484 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 485 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 486 #define FLOW_CONTROL_TYPE 0x8808 487 488 /* 802.1q VLAN Packet Size */ 489 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 490 491 /* Receive Address 492 * Number of high/low register pairs in the RAR. The RAR (Receive Address 493 * Registers) holds the directed and multicast addresses that we monitor. 494 * Technically, we have 16 spots. However, we reserve one of these spots 495 * (RAR[15]) for our directed address used by controllers with 496 * manageability enabled, allowing us room for 15 multicast addresses. 497 */ 498 #define E1000_RAR_ENTRIES 15 499 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 500 #define E1000_RAL_MAC_ADDR_LEN 4 501 #define E1000_RAH_MAC_ADDR_LEN 2 502 503 /* Error Codes */ 504 #define E1000_ERR_NVM 1 505 #define E1000_ERR_PHY 2 506 #define E1000_ERR_CONFIG 3 507 #define E1000_ERR_PARAM 4 508 #define E1000_ERR_MAC_INIT 5 509 #define E1000_ERR_PHY_TYPE 6 510 #define E1000_ERR_RESET 9 511 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 512 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 513 #define E1000_BLK_PHY_RESET 12 514 #define E1000_ERR_SWFW_SYNC 13 515 #define E1000_NOT_IMPLEMENTED 14 516 #define E1000_ERR_INVALID_ARGUMENT 16 517 #define E1000_ERR_NO_SPACE 17 518 #define E1000_ERR_NVM_PBA_SECTION 18 519 520 /* Loop limit on how long we wait for auto-negotiation to complete */ 521 #define FIBER_LINK_UP_LIMIT 50 522 #define COPPER_LINK_UP_LIMIT 10 523 #define PHY_AUTO_NEG_LIMIT 45 524 #define PHY_FORCE_LIMIT 20 525 /* Number of 100 microseconds we wait for PCI Express master disable */ 526 #define MASTER_DISABLE_TIMEOUT 800 527 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 528 #define PHY_CFG_TIMEOUT 100 529 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 530 #define MDIO_OWNERSHIP_TIMEOUT 10 531 /* Number of milliseconds for NVM auto read done after MAC reset. */ 532 #define AUTO_READ_DONE_TIMEOUT 10 533 534 /* Flow Control */ 535 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 536 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 537 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 538 539 /* Transmit Configuration Word */ 540 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 541 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 542 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 543 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 544 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 545 546 /* Receive Configuration Word */ 547 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 548 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 549 #define E1000_RXCW_C 0x20000000 /* Receive config */ 550 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 551 552 /* HH Time Sync */ 553 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 554 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 555 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 556 557 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 558 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 559 560 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 561 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 562 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 563 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 564 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 565 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 566 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 567 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 568 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 569 570 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 571 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 572 573 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 574 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 575 576 #define E1000_TIMINCA_INCPERIOD_SHIFT 24 577 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 578 579 /* PCI Express Control */ 580 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 581 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 582 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 583 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 584 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 585 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 586 587 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 588 E1000_GCR_RXDSCW_NO_SNOOP | \ 589 E1000_GCR_RXDSCR_NO_SNOOP | \ 590 E1000_GCR_TXD_NO_SNOOP | \ 591 E1000_GCR_TXDSCW_NO_SNOOP | \ 592 E1000_GCR_TXDSCR_NO_SNOOP) 593 594 /* NVM Control */ 595 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 596 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 597 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 598 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 599 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 600 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 601 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 602 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 603 /* NVM Addressing bits based on type (0-small, 1-large) */ 604 #define E1000_EECD_ADDR_BITS 0x00000400 605 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 606 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 607 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 608 #define E1000_EECD_SIZE_EX_SHIFT 11 609 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 610 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 611 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 612 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 613 614 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */ 615 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 616 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 617 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 618 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */ 619 #define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */ 620 #define E1000_FLASH_UPDATES 2000 621 622 /* NVM Word Offsets */ 623 #define NVM_COMPAT 0x0003 624 #define NVM_ID_LED_SETTINGS 0x0004 625 #define NVM_FUTURE_INIT_WORD1 0x0019 626 #define NVM_COMPAT_VALID_CSUM 0x0001 627 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 628 629 #define NVM_INIT_CONTROL2_REG 0x000F 630 #define NVM_INIT_CONTROL3_PORT_B 0x0014 631 #define NVM_INIT_3GIO_3 0x001A 632 #define NVM_INIT_CONTROL3_PORT_A 0x0024 633 #define NVM_CFG 0x0012 634 #define NVM_ALT_MAC_ADDR_PTR 0x0037 635 #define NVM_CHECKSUM_REG 0x003F 636 637 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 638 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 639 640 /* Mask bits for fields in Word 0x0f of the NVM */ 641 #define NVM_WORD0F_PAUSE_MASK 0x3000 642 #define NVM_WORD0F_PAUSE 0x1000 643 #define NVM_WORD0F_ASM_DIR 0x2000 644 645 /* Mask bits for fields in Word 0x1a of the NVM */ 646 #define NVM_WORD1A_ASPM_MASK 0x000C 647 648 /* Mask bits for fields in Word 0x03 of the EEPROM */ 649 #define NVM_COMPAT_LOM 0x0800 650 651 /* length of string needed to store PBA number */ 652 #define E1000_PBANUM_LENGTH 11 653 654 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 655 #define NVM_SUM 0xBABA 656 657 /* PBA (printed board assembly) number words */ 658 #define NVM_PBA_OFFSET_0 8 659 #define NVM_PBA_OFFSET_1 9 660 #define NVM_PBA_PTR_GUARD 0xFAFA 661 #define NVM_WORD_SIZE_BASE_SHIFT 6 662 663 /* NVM Commands - SPI */ 664 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 665 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 666 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 667 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 668 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 669 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 670 671 /* SPI NVM Status Register */ 672 #define NVM_STATUS_RDY_SPI 0x01 673 674 /* Word definitions for ID LED Settings */ 675 #define ID_LED_RESERVED_0000 0x0000 676 #define ID_LED_RESERVED_FFFF 0xFFFF 677 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 678 (ID_LED_OFF1_OFF2 << 8) | \ 679 (ID_LED_DEF1_DEF2 << 4) | \ 680 (ID_LED_DEF1_DEF2)) 681 #define ID_LED_DEF1_DEF2 0x1 682 #define ID_LED_DEF1_ON2 0x2 683 #define ID_LED_DEF1_OFF2 0x3 684 #define ID_LED_ON1_DEF2 0x4 685 #define ID_LED_ON1_ON2 0x5 686 #define ID_LED_ON1_OFF2 0x6 687 #define ID_LED_OFF1_DEF2 0x7 688 #define ID_LED_OFF1_ON2 0x8 689 #define ID_LED_OFF1_OFF2 0x9 690 691 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 692 #define IGP_ACTIVITY_LED_ENABLE 0x0300 693 #define IGP_LED3_MODE 0x07000000 694 695 /* PCI/PCI-X/PCI-EX Config space */ 696 #define PCI_HEADER_TYPE_REGISTER 0x0E 697 #define PCIE_LINK_STATUS 0x12 698 699 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 700 #define PCIE_LINK_WIDTH_MASK 0x3F0 701 #define PCIE_LINK_WIDTH_SHIFT 4 702 703 #define PHY_REVISION_MASK 0xFFFFFFF0 704 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 705 #define MAX_PHY_MULTI_PAGE_REG 0xF 706 707 /* Bit definitions for valid PHY IDs. 708 * I = Integrated 709 * E = External 710 */ 711 #define M88E1000_E_PHY_ID 0x01410C50 712 #define M88E1000_I_PHY_ID 0x01410C30 713 #define M88E1011_I_PHY_ID 0x01410C20 714 #define IGP01E1000_I_PHY_ID 0x02A80380 715 #define M88E1111_I_PHY_ID 0x01410CC0 716 #define GG82563_E_PHY_ID 0x01410CA0 717 #define IGP03E1000_E_PHY_ID 0x02A80390 718 #define IFE_E_PHY_ID 0x02A80330 719 #define IFE_PLUS_E_PHY_ID 0x02A80320 720 #define IFE_C_E_PHY_ID 0x02A80310 721 #define BME1000_E_PHY_ID 0x01410CB0 722 #define BME1000_E_PHY_ID_R2 0x01410CB1 723 #define I82577_E_PHY_ID 0x01540050 724 #define I82578_E_PHY_ID 0x004DD040 725 #define I82579_E_PHY_ID 0x01540090 726 #define I217_E_PHY_ID 0x015400A0 727 728 /* M88E1000 Specific Registers */ 729 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 730 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 731 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 732 733 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 734 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 735 736 /* M88E1000 PHY Specific Control Register */ 737 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 738 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 739 /* Manual MDI configuration */ 740 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 741 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 742 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 743 /* Auto crossover enabled all speeds */ 744 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 745 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 746 747 /* M88E1000 PHY Specific Status Register */ 748 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 749 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 750 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 751 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 752 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 753 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 754 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 755 756 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 757 758 /* Number of times we will attempt to autonegotiate before downshifting if we 759 * are the master 760 */ 761 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 762 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 763 /* Number of times we will attempt to autonegotiate before downshifting if we 764 * are the slave 765 */ 766 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 767 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 768 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 769 770 /* M88EC018 Rev 2 specific DownShift settings */ 771 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 772 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 773 774 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 775 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 776 777 /* BME1000 PHY Specific Control Register */ 778 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 779 780 /* Bits... 781 * 15-5: page 782 * 4-0: register offset 783 */ 784 #define GG82563_PAGE_SHIFT 5 785 #define GG82563_REG(page, reg) \ 786 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 787 #define GG82563_MIN_ALT_REG 30 788 789 /* GG82563 Specific Registers */ 790 #define GG82563_PHY_SPEC_CTRL \ 791 GG82563_REG(0, 16) /* PHY Specific Control */ 792 #define GG82563_PHY_PAGE_SELECT \ 793 GG82563_REG(0, 22) /* Page Select */ 794 #define GG82563_PHY_SPEC_CTRL_2 \ 795 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 796 #define GG82563_PHY_PAGE_SELECT_ALT \ 797 GG82563_REG(0, 29) /* Alternate Page Select */ 798 799 #define GG82563_PHY_MAC_SPEC_CTRL \ 800 GG82563_REG(2, 21) /* MAC Specific Control Register */ 801 802 #define GG82563_PHY_DSP_DISTANCE \ 803 GG82563_REG(5, 26) /* DSP Distance */ 804 805 /* Page 193 - Port Control Registers */ 806 #define GG82563_PHY_KMRN_MODE_CTRL \ 807 GG82563_REG(193, 16) /* Kumeran Mode Control */ 808 #define GG82563_PHY_PWR_MGMT_CTRL \ 809 GG82563_REG(193, 20) /* Power Management Control */ 810 811 /* Page 194 - KMRN Registers */ 812 #define GG82563_PHY_INBAND_CTRL \ 813 GG82563_REG(194, 18) /* Inband Control */ 814 815 /* MDI Control */ 816 #define E1000_MDIC_REG_MASK 0x001F0000 817 #define E1000_MDIC_REG_SHIFT 16 818 #define E1000_MDIC_PHY_SHIFT 21 819 #define E1000_MDIC_OP_WRITE 0x04000000 820 #define E1000_MDIC_OP_READ 0x08000000 821 #define E1000_MDIC_READY 0x10000000 822 #define E1000_MDIC_ERROR 0x40000000 823 824 /* SerDes Control */ 825 #define E1000_GEN_POLL_TIMEOUT 640 826 827 #endif /* _E1000_DEFINES_H_ */ 828