1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _E1000_DEFINES_H_ 30 #define _E1000_DEFINES_H_ 31 32 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50 51 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 54 55 /* Definitions for power management and wakeup registers */ 56 /* Wake Up Control */ 57 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 58 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 60 61 /* Wake Up Filter Control */ 62 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 63 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 64 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 65 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 66 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 67 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 68 69 /* Wake Up Status */ 70 #define E1000_WUS_LNKC E1000_WUFC_LNKC 71 #define E1000_WUS_MAG E1000_WUFC_MAG 72 #define E1000_WUS_EX E1000_WUFC_EX 73 #define E1000_WUS_MC E1000_WUFC_MC 74 #define E1000_WUS_BC E1000_WUFC_BC 75 76 /* Extended Device Control */ 77 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 78 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 79 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 80 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 81 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 82 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 84 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 85 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 86 #define E1000_CTRL_EXT_EIAME 0x01000000 87 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 88 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 89 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 90 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 91 #define E1000_CTRL_EXT_LSECCK 0x00001000 92 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 93 94 /* Receive Descriptor bit definitions */ 95 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 96 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 97 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 98 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 99 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 100 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 101 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 102 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 103 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 104 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 105 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 106 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 107 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 108 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 109 110 #define E1000_RXDEXT_STATERR_CE 0x01000000 111 #define E1000_RXDEXT_STATERR_SE 0x02000000 112 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 113 #define E1000_RXDEXT_STATERR_CXE 0x10000000 114 #define E1000_RXDEXT_STATERR_RXE 0x80000000 115 116 /* mask to determine if packets should be dropped due to frame errors */ 117 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 118 E1000_RXD_ERR_CE | \ 119 E1000_RXD_ERR_SE | \ 120 E1000_RXD_ERR_SEQ | \ 121 E1000_RXD_ERR_CXE | \ 122 E1000_RXD_ERR_RXE) 123 124 /* Same mask, but for extended and packet split descriptors */ 125 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 126 E1000_RXDEXT_STATERR_CE | \ 127 E1000_RXDEXT_STATERR_SE | \ 128 E1000_RXDEXT_STATERR_SEQ | \ 129 E1000_RXDEXT_STATERR_CXE | \ 130 E1000_RXDEXT_STATERR_RXE) 131 132 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 133 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 134 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 135 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 136 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 137 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 138 139 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 140 141 /* Management Control */ 142 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 143 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 144 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 145 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 146 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 147 /* Enable MAC address filtering */ 148 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 149 /* Enable MNG packets to host memory */ 150 #define E1000_MANC_EN_MNG2HOST 0x00200000 151 152 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 153 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 154 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 155 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 156 157 /* Receive Control */ 158 #define E1000_RCTL_EN 0x00000002 /* enable */ 159 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 160 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 161 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 162 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 163 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 164 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 165 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 166 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 167 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 168 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 169 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 170 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 171 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 172 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 173 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 174 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 175 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 176 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 177 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 178 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 179 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 180 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 181 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 182 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 183 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 184 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 185 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 186 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 187 188 /* 189 * Use byte values for the following shift parameters 190 * Usage: 191 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 192 * E1000_PSRCTL_BSIZE0_MASK) | 193 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 194 * E1000_PSRCTL_BSIZE1_MASK) | 195 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 196 * E1000_PSRCTL_BSIZE2_MASK) | 197 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 198 * E1000_PSRCTL_BSIZE3_MASK)) 199 * where value0 = [128..16256], default=256 200 * value1 = [1024..64512], default=4096 201 * value2 = [0..64512], default=4096 202 * value3 = [0..64512], default=0 203 */ 204 205 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 206 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 207 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 208 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 209 210 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 211 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 212 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 213 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 214 215 /* SWFW_SYNC Definitions */ 216 #define E1000_SWFW_EEP_SM 0x1 217 #define E1000_SWFW_PHY0_SM 0x2 218 #define E1000_SWFW_PHY1_SM 0x4 219 #define E1000_SWFW_CSR_SM 0x8 220 221 /* Device Control */ 222 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 223 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 224 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 225 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 226 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 227 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 228 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 229 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 230 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 231 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 232 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 233 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 234 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 235 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 236 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 237 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 238 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 239 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 240 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 241 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 242 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 243 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 244 245 /* 246 * Bit definitions for the Management Data IO (MDIO) and Management Data 247 * Clock (MDC) pins in the Device Control Register. 248 */ 249 250 /* Device Status */ 251 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 252 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 253 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 254 #define E1000_STATUS_FUNC_SHIFT 2 255 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 256 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 257 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 258 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 259 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 260 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 261 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 262 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 263 264 /* Constants used to interpret the masked PCI-X bus speed. */ 265 266 #define HALF_DUPLEX 1 267 #define FULL_DUPLEX 2 268 269 270 #define ADVERTISE_10_HALF 0x0001 271 #define ADVERTISE_10_FULL 0x0002 272 #define ADVERTISE_100_HALF 0x0004 273 #define ADVERTISE_100_FULL 0x0008 274 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 275 #define ADVERTISE_1000_FULL 0x0020 276 277 /* 1000/H is not supported, nor spec-compliant. */ 278 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 279 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 280 ADVERTISE_1000_FULL) 281 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 282 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 283 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 284 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 285 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 286 287 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 288 289 /* LED Control */ 290 #define E1000_PHY_LED0_MODE_MASK 0x00000007 291 #define E1000_PHY_LED0_IVRT 0x00000008 292 #define E1000_PHY_LED0_MASK 0x0000001F 293 294 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 295 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 296 #define E1000_LEDCTL_LED0_IVRT 0x00000040 297 #define E1000_LEDCTL_LED0_BLINK 0x00000080 298 299 #define E1000_LEDCTL_MODE_LINK_UP 0x2 300 #define E1000_LEDCTL_MODE_LED_ON 0xE 301 #define E1000_LEDCTL_MODE_LED_OFF 0xF 302 303 /* Transmit Descriptor bit definitions */ 304 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 305 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 306 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 307 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 308 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 309 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 310 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 311 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 312 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 313 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 314 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 315 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 316 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 317 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 318 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 319 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 320 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 321 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 322 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 323 324 /* Transmit Control */ 325 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 326 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 327 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 328 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 329 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 330 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 331 332 /* Transmit Arbitration Count */ 333 334 /* SerDes Control */ 335 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 336 337 /* Receive Checksum Control */ 338 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 339 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 340 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 341 342 /* Header split receive */ 343 #define E1000_RFCTL_NFSW_DIS 0x00000040 344 #define E1000_RFCTL_NFSR_DIS 0x00000080 345 #define E1000_RFCTL_ACK_DIS 0x00001000 346 #define E1000_RFCTL_EXTEN 0x00008000 347 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 348 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 349 350 /* Collision related configuration parameters */ 351 #define E1000_COLLISION_THRESHOLD 15 352 #define E1000_CT_SHIFT 4 353 #define E1000_COLLISION_DISTANCE 63 354 #define E1000_COLD_SHIFT 12 355 356 /* Default values for the transmit IPG register */ 357 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 358 359 #define E1000_TIPG_IPGT_MASK 0x000003FF 360 361 #define DEFAULT_82543_TIPG_IPGR1 8 362 #define E1000_TIPG_IPGR1_SHIFT 10 363 364 #define DEFAULT_82543_TIPG_IPGR2 6 365 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 366 #define E1000_TIPG_IPGR2_SHIFT 20 367 368 #define MAX_JUMBO_FRAME_SIZE 0x3F00 369 370 /* Extended Configuration Control and Size */ 371 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 372 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 373 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 374 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 375 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 376 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 377 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 378 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 379 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 380 381 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 382 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 383 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 384 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 385 386 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 387 388 /* PBA constants */ 389 #define E1000_PBA_8K 0x0008 /* 8KB */ 390 #define E1000_PBA_16K 0x0010 /* 16KB */ 391 392 #define E1000_PBS_16K E1000_PBA_16K 393 394 #define IFS_MAX 80 395 #define IFS_MIN 40 396 #define IFS_RATIO 4 397 #define IFS_STEP 10 398 #define MIN_NUM_XMITS 1000 399 400 /* SW Semaphore Register */ 401 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 402 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 403 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 404 405 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 406 407 /* Interrupt Cause Read */ 408 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 409 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 410 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 411 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 412 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 413 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 414 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 415 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 416 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 417 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 418 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 419 420 /* PBA ECC Register */ 421 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 422 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 423 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 424 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 425 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 426 427 /* 428 * This defines the bits that are set in the Interrupt Mask 429 * Set/Read Register. Each bit is documented below: 430 * o RXT0 = Receiver Timer Interrupt (ring 0) 431 * o TXDW = Transmit Descriptor Written Back 432 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 433 * o RXSEQ = Receive Sequence Error 434 * o LSC = Link Status Change 435 */ 436 #define IMS_ENABLE_MASK ( \ 437 E1000_IMS_RXT0 | \ 438 E1000_IMS_TXDW | \ 439 E1000_IMS_RXDMT0 | \ 440 E1000_IMS_RXSEQ | \ 441 E1000_IMS_LSC) 442 443 /* Interrupt Mask Set */ 444 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 445 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 446 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 447 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 448 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 449 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 450 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 451 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 452 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 453 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 454 455 /* Interrupt Cause Set */ 456 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 457 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 458 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 459 460 /* Transmit Descriptor Control */ 461 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 462 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 463 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 464 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 465 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 466 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 467 /* Enable the counting of desc. still to be processed. */ 468 #define E1000_TXDCTL_COUNT_DESC 0x00400000 469 470 /* Flow Control Constants */ 471 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 472 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 473 #define FLOW_CONTROL_TYPE 0x8808 474 475 /* 802.1q VLAN Packet Size */ 476 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 477 478 /* Receive Address */ 479 /* 480 * Number of high/low register pairs in the RAR. The RAR (Receive Address 481 * Registers) holds the directed and multicast addresses that we monitor. 482 * Technically, we have 16 spots. However, we reserve one of these spots 483 * (RAR[15]) for our directed address used by controllers with 484 * manageability enabled, allowing us room for 15 multicast addresses. 485 */ 486 #define E1000_RAR_ENTRIES 15 487 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 488 #define E1000_RAL_MAC_ADDR_LEN 4 489 #define E1000_RAH_MAC_ADDR_LEN 2 490 491 /* Error Codes */ 492 #define E1000_ERR_NVM 1 493 #define E1000_ERR_PHY 2 494 #define E1000_ERR_CONFIG 3 495 #define E1000_ERR_PARAM 4 496 #define E1000_ERR_MAC_INIT 5 497 #define E1000_ERR_PHY_TYPE 6 498 #define E1000_ERR_RESET 9 499 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 500 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 501 #define E1000_BLK_PHY_RESET 12 502 #define E1000_ERR_SWFW_SYNC 13 503 #define E1000_NOT_IMPLEMENTED 14 504 #define E1000_ERR_INVALID_ARGUMENT 16 505 #define E1000_ERR_NO_SPACE 17 506 #define E1000_ERR_NVM_PBA_SECTION 18 507 508 /* Loop limit on how long we wait for auto-negotiation to complete */ 509 #define FIBER_LINK_UP_LIMIT 50 510 #define COPPER_LINK_UP_LIMIT 10 511 #define PHY_AUTO_NEG_LIMIT 45 512 #define PHY_FORCE_LIMIT 20 513 /* Number of 100 microseconds we wait for PCI Express master disable */ 514 #define MASTER_DISABLE_TIMEOUT 800 515 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 516 #define PHY_CFG_TIMEOUT 100 517 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 518 #define MDIO_OWNERSHIP_TIMEOUT 10 519 /* Number of milliseconds for NVM auto read done after MAC reset. */ 520 #define AUTO_READ_DONE_TIMEOUT 10 521 522 /* Flow Control */ 523 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 524 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 525 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 526 527 /* Transmit Configuration Word */ 528 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 529 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 530 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 531 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 532 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 533 534 /* Receive Configuration Word */ 535 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 536 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 537 #define E1000_RXCW_C 0x20000000 /* Receive config */ 538 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 539 540 /* PCI Express Control */ 541 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 542 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 543 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 544 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 545 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 546 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 547 548 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 549 E1000_GCR_RXDSCW_NO_SNOOP | \ 550 E1000_GCR_RXDSCR_NO_SNOOP | \ 551 E1000_GCR_TXD_NO_SNOOP | \ 552 E1000_GCR_TXDSCW_NO_SNOOP | \ 553 E1000_GCR_TXDSCR_NO_SNOOP) 554 555 /* PHY Control Register */ 556 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 557 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 558 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 559 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 560 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 561 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 562 #define MII_CR_SPEED_1000 0x0040 563 #define MII_CR_SPEED_100 0x2000 564 #define MII_CR_SPEED_10 0x0000 565 566 /* PHY Status Register */ 567 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 568 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 569 570 /* Autoneg Advertisement Register */ 571 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 572 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 573 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 574 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 575 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 576 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 577 578 /* Link Partner Ability Register (Base Page) */ 579 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 580 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 581 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 582 583 /* Autoneg Expansion Register */ 584 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 585 586 /* 1000BASE-T Control Register */ 587 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 588 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 589 /* 0=DTE device */ 590 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 591 /* 0=Configure PHY as Slave */ 592 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 593 /* 0=Automatic Master/Slave config */ 594 595 /* 1000BASE-T Status Register */ 596 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 597 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 598 599 600 /* PHY 1000 MII Register/Bit Definitions */ 601 /* PHY Registers defined by IEEE */ 602 #define PHY_CONTROL 0x00 /* Control Register */ 603 #define PHY_STATUS 0x01 /* Status Register */ 604 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 605 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 606 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 607 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 608 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 609 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 610 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 611 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 612 613 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 614 615 /* NVM Control */ 616 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 617 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 618 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 619 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 620 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 621 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 622 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 623 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 624 /* NVM Addressing bits based on type (0-small, 1-large) */ 625 #define E1000_EECD_ADDR_BITS 0x00000400 626 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 627 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 628 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 629 #define E1000_EECD_SIZE_EX_SHIFT 11 630 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 631 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 632 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 633 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 634 635 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 636 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 637 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 638 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 639 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 640 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 641 #define E1000_FLASH_UPDATES 2000 642 643 /* NVM Word Offsets */ 644 #define NVM_COMPAT 0x0003 645 #define NVM_ID_LED_SETTINGS 0x0004 646 #define NVM_INIT_CONTROL2_REG 0x000F 647 #define NVM_INIT_CONTROL3_PORT_B 0x0014 648 #define NVM_INIT_3GIO_3 0x001A 649 #define NVM_INIT_CONTROL3_PORT_A 0x0024 650 #define NVM_CFG 0x0012 651 #define NVM_ALT_MAC_ADDR_PTR 0x0037 652 #define NVM_CHECKSUM_REG 0x003F 653 654 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 655 656 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 657 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 658 659 /* Mask bits for fields in Word 0x0f of the NVM */ 660 #define NVM_WORD0F_PAUSE_MASK 0x3000 661 #define NVM_WORD0F_PAUSE 0x1000 662 #define NVM_WORD0F_ASM_DIR 0x2000 663 664 /* Mask bits for fields in Word 0x1a of the NVM */ 665 #define NVM_WORD1A_ASPM_MASK 0x000C 666 667 /* Mask bits for fields in Word 0x03 of the EEPROM */ 668 #define NVM_COMPAT_LOM 0x0800 669 670 /* length of string needed to store PBA number */ 671 #define E1000_PBANUM_LENGTH 11 672 673 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 674 #define NVM_SUM 0xBABA 675 676 /* PBA (printed board assembly) number words */ 677 #define NVM_PBA_OFFSET_0 8 678 #define NVM_PBA_OFFSET_1 9 679 #define NVM_PBA_PTR_GUARD 0xFAFA 680 #define NVM_WORD_SIZE_BASE_SHIFT 6 681 682 /* NVM Commands - SPI */ 683 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 684 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 685 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 686 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 687 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 688 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 689 690 /* SPI NVM Status Register */ 691 #define NVM_STATUS_RDY_SPI 0x01 692 693 /* Word definitions for ID LED Settings */ 694 #define ID_LED_RESERVED_0000 0x0000 695 #define ID_LED_RESERVED_FFFF 0xFFFF 696 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 697 (ID_LED_OFF1_OFF2 << 8) | \ 698 (ID_LED_DEF1_DEF2 << 4) | \ 699 (ID_LED_DEF1_DEF2)) 700 #define ID_LED_DEF1_DEF2 0x1 701 #define ID_LED_DEF1_ON2 0x2 702 #define ID_LED_DEF1_OFF2 0x3 703 #define ID_LED_ON1_DEF2 0x4 704 #define ID_LED_ON1_ON2 0x5 705 #define ID_LED_ON1_OFF2 0x6 706 #define ID_LED_OFF1_DEF2 0x7 707 #define ID_LED_OFF1_ON2 0x8 708 #define ID_LED_OFF1_OFF2 0x9 709 710 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 711 #define IGP_ACTIVITY_LED_ENABLE 0x0300 712 #define IGP_LED3_MODE 0x07000000 713 714 /* PCI/PCI-X/PCI-EX Config space */ 715 #define PCI_HEADER_TYPE_REGISTER 0x0E 716 #define PCIE_LINK_STATUS 0x12 717 718 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 719 #define PCIE_LINK_WIDTH_MASK 0x3F0 720 #define PCIE_LINK_WIDTH_SHIFT 4 721 722 #define PHY_REVISION_MASK 0xFFFFFFF0 723 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 724 #define MAX_PHY_MULTI_PAGE_REG 0xF 725 726 /* Bit definitions for valid PHY IDs. */ 727 /* 728 * I = Integrated 729 * E = External 730 */ 731 #define M88E1000_E_PHY_ID 0x01410C50 732 #define M88E1000_I_PHY_ID 0x01410C30 733 #define M88E1011_I_PHY_ID 0x01410C20 734 #define IGP01E1000_I_PHY_ID 0x02A80380 735 #define M88E1111_I_PHY_ID 0x01410CC0 736 #define GG82563_E_PHY_ID 0x01410CA0 737 #define IGP03E1000_E_PHY_ID 0x02A80390 738 #define IFE_E_PHY_ID 0x02A80330 739 #define IFE_PLUS_E_PHY_ID 0x02A80320 740 #define IFE_C_E_PHY_ID 0x02A80310 741 #define BME1000_E_PHY_ID 0x01410CB0 742 #define BME1000_E_PHY_ID_R2 0x01410CB1 743 #define I82577_E_PHY_ID 0x01540050 744 #define I82578_E_PHY_ID 0x004DD040 745 #define I82579_E_PHY_ID 0x01540090 746 #define I217_E_PHY_ID 0x015400A0 747 748 /* M88E1000 Specific Registers */ 749 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 750 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 751 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 752 753 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 754 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 755 756 /* M88E1000 PHY Specific Control Register */ 757 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 758 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 759 /* Manual MDI configuration */ 760 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 761 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 762 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 763 /* Auto crossover enabled all speeds */ 764 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 765 /* 766 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 767 * 0=Normal 10BASE-T Rx Threshold 768 */ 769 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 770 771 /* M88E1000 PHY Specific Status Register */ 772 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 773 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 774 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 775 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 776 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 777 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 778 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 779 780 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 781 782 /* 783 * Number of times we will attempt to autonegotiate before downshifting if we 784 * are the master 785 */ 786 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 787 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 788 /* 789 * Number of times we will attempt to autonegotiate before downshifting if we 790 * are the slave 791 */ 792 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 793 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 794 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 795 796 /* M88EC018 Rev 2 specific DownShift settings */ 797 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 798 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 799 800 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 801 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 802 803 /* BME1000 PHY Specific Control Register */ 804 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 805 806 807 #define PHY_PAGE_SHIFT 5 808 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 809 ((reg) & MAX_PHY_REG_ADDRESS)) 810 811 /* 812 * Bits... 813 * 15-5: page 814 * 4-0: register offset 815 */ 816 #define GG82563_PAGE_SHIFT 5 817 #define GG82563_REG(page, reg) \ 818 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 819 #define GG82563_MIN_ALT_REG 30 820 821 /* GG82563 Specific Registers */ 822 #define GG82563_PHY_SPEC_CTRL \ 823 GG82563_REG(0, 16) /* PHY Specific Control */ 824 #define GG82563_PHY_PAGE_SELECT \ 825 GG82563_REG(0, 22) /* Page Select */ 826 #define GG82563_PHY_SPEC_CTRL_2 \ 827 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 828 #define GG82563_PHY_PAGE_SELECT_ALT \ 829 GG82563_REG(0, 29) /* Alternate Page Select */ 830 831 #define GG82563_PHY_MAC_SPEC_CTRL \ 832 GG82563_REG(2, 21) /* MAC Specific Control Register */ 833 834 #define GG82563_PHY_DSP_DISTANCE \ 835 GG82563_REG(5, 26) /* DSP Distance */ 836 837 /* Page 193 - Port Control Registers */ 838 #define GG82563_PHY_KMRN_MODE_CTRL \ 839 GG82563_REG(193, 16) /* Kumeran Mode Control */ 840 #define GG82563_PHY_PWR_MGMT_CTRL \ 841 GG82563_REG(193, 20) /* Power Management Control */ 842 843 /* Page 194 - KMRN Registers */ 844 #define GG82563_PHY_INBAND_CTRL \ 845 GG82563_REG(194, 18) /* Inband Control */ 846 847 /* MDI Control */ 848 #define E1000_MDIC_REG_SHIFT 16 849 #define E1000_MDIC_PHY_SHIFT 21 850 #define E1000_MDIC_OP_WRITE 0x04000000 851 #define E1000_MDIC_OP_READ 0x08000000 852 #define E1000_MDIC_READY 0x10000000 853 #define E1000_MDIC_ERROR 0x40000000 854 855 /* SerDes Control */ 856 #define E1000_GEN_POLL_TIMEOUT 640 857 858 /* FW Semaphore */ 859 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 860 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 861 862 #endif /* _E1000_DEFINES_H_ */ 863