1 /* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22 /* 82571EB Gigabit Ethernet Controller 23 * 82571EB Gigabit Ethernet Controller (Copper) 24 * 82571EB Gigabit Ethernet Controller (Fiber) 25 * 82571EB Dual Port Gigabit Mezzanine Adapter 26 * 82571EB Quad Port Gigabit Mezzanine Adapter 27 * 82571PT Gigabit PT Quad Port Server ExpressModule 28 * 82572EI Gigabit Ethernet Controller (Copper) 29 * 82572EI Gigabit Ethernet Controller (Fiber) 30 * 82572EI Gigabit Ethernet Controller 31 * 82573V Gigabit Ethernet Controller (Copper) 32 * 82573E Gigabit Ethernet Controller (Copper) 33 * 82573L Gigabit Ethernet Controller 34 * 82574L Gigabit Network Connection 35 * 82583V Gigabit Network Connection 36 */ 37 38 #include "e1000.h" 39 40 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 41 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 42 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 43 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 44 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 45 u16 words, u16 *data); 46 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 47 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 48 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 49 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 50 static s32 e1000_led_on_82574(struct e1000_hw *hw); 51 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 52 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 53 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 54 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 55 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 56 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); 57 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); 58 59 /** 60 * e1000_init_phy_params_82571 - Init PHY func ptrs. 61 * @hw: pointer to the HW structure 62 **/ 63 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 64 { 65 struct e1000_phy_info *phy = &hw->phy; 66 s32 ret_val; 67 68 if (hw->phy.media_type != e1000_media_type_copper) { 69 phy->type = e1000_phy_none; 70 return 0; 71 } 72 73 phy->addr = 1; 74 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 75 phy->reset_delay_us = 100; 76 77 phy->ops.power_up = e1000_power_up_phy_copper; 78 phy->ops.power_down = e1000_power_down_phy_copper_82571; 79 80 switch (hw->mac.type) { 81 case e1000_82571: 82 case e1000_82572: 83 phy->type = e1000_phy_igp_2; 84 break; 85 case e1000_82573: 86 phy->type = e1000_phy_m88; 87 break; 88 case e1000_82574: 89 case e1000_82583: 90 phy->type = e1000_phy_bm; 91 phy->ops.acquire = e1000_get_hw_semaphore_82574; 92 phy->ops.release = e1000_put_hw_semaphore_82574; 93 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 94 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 95 break; 96 default: 97 return -E1000_ERR_PHY; 98 break; 99 } 100 101 /* This can only be done after all function pointers are setup. */ 102 ret_val = e1000_get_phy_id_82571(hw); 103 if (ret_val) { 104 e_dbg("Error getting PHY ID\n"); 105 return ret_val; 106 } 107 108 /* Verify phy id */ 109 switch (hw->mac.type) { 110 case e1000_82571: 111 case e1000_82572: 112 if (phy->id != IGP01E1000_I_PHY_ID) 113 ret_val = -E1000_ERR_PHY; 114 break; 115 case e1000_82573: 116 if (phy->id != M88E1111_I_PHY_ID) 117 ret_val = -E1000_ERR_PHY; 118 break; 119 case e1000_82574: 120 case e1000_82583: 121 if (phy->id != BME1000_E_PHY_ID_R2) 122 ret_val = -E1000_ERR_PHY; 123 break; 124 default: 125 ret_val = -E1000_ERR_PHY; 126 break; 127 } 128 129 if (ret_val) 130 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); 131 132 return ret_val; 133 } 134 135 /** 136 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 137 * @hw: pointer to the HW structure 138 **/ 139 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 140 { 141 struct e1000_nvm_info *nvm = &hw->nvm; 142 u32 eecd = er32(EECD); 143 u16 size; 144 145 nvm->opcode_bits = 8; 146 nvm->delay_usec = 1; 147 switch (nvm->override) { 148 case e1000_nvm_override_spi_large: 149 nvm->page_size = 32; 150 nvm->address_bits = 16; 151 break; 152 case e1000_nvm_override_spi_small: 153 nvm->page_size = 8; 154 nvm->address_bits = 8; 155 break; 156 default: 157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 159 break; 160 } 161 162 switch (hw->mac.type) { 163 case e1000_82573: 164 case e1000_82574: 165 case e1000_82583: 166 if (((eecd >> 15) & 0x3) == 0x3) { 167 nvm->type = e1000_nvm_flash_hw; 168 nvm->word_size = 2048; 169 /* Autonomous Flash update bit must be cleared due 170 * to Flash update issue. 171 */ 172 eecd &= ~E1000_EECD_AUPDEN; 173 ew32(EECD, eecd); 174 break; 175 } 176 /* Fall Through */ 177 default: 178 nvm->type = e1000_nvm_eeprom_spi; 179 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 180 E1000_EECD_SIZE_EX_SHIFT); 181 /* Added to a constant, "size" becomes the left-shift value 182 * for setting word_size. 183 */ 184 size += NVM_WORD_SIZE_BASE_SHIFT; 185 186 /* EEPROM access above 16k is unsupported */ 187 if (size > 14) 188 size = 14; 189 nvm->word_size = 1 << size; 190 break; 191 } 192 193 /* Function Pointers */ 194 switch (hw->mac.type) { 195 case e1000_82574: 196 case e1000_82583: 197 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 198 nvm->ops.release = e1000_put_hw_semaphore_82574; 199 break; 200 default: 201 break; 202 } 203 204 return 0; 205 } 206 207 /** 208 * e1000_init_mac_params_82571 - Init MAC func ptrs. 209 * @hw: pointer to the HW structure 210 **/ 211 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 212 { 213 struct e1000_mac_info *mac = &hw->mac; 214 u32 swsm = 0; 215 u32 swsm2 = 0; 216 bool force_clear_smbi = false; 217 218 /* Set media type and media-dependent function pointers */ 219 switch (hw->adapter->pdev->device) { 220 case E1000_DEV_ID_82571EB_FIBER: 221 case E1000_DEV_ID_82572EI_FIBER: 222 case E1000_DEV_ID_82571EB_QUAD_FIBER: 223 hw->phy.media_type = e1000_media_type_fiber; 224 mac->ops.setup_physical_interface = 225 e1000_setup_fiber_serdes_link_82571; 226 mac->ops.check_for_link = e1000e_check_for_fiber_link; 227 mac->ops.get_link_up_info = 228 e1000e_get_speed_and_duplex_fiber_serdes; 229 break; 230 case E1000_DEV_ID_82571EB_SERDES: 231 case E1000_DEV_ID_82571EB_SERDES_DUAL: 232 case E1000_DEV_ID_82571EB_SERDES_QUAD: 233 case E1000_DEV_ID_82572EI_SERDES: 234 hw->phy.media_type = e1000_media_type_internal_serdes; 235 mac->ops.setup_physical_interface = 236 e1000_setup_fiber_serdes_link_82571; 237 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 238 mac->ops.get_link_up_info = 239 e1000e_get_speed_and_duplex_fiber_serdes; 240 break; 241 default: 242 hw->phy.media_type = e1000_media_type_copper; 243 mac->ops.setup_physical_interface = 244 e1000_setup_copper_link_82571; 245 mac->ops.check_for_link = e1000e_check_for_copper_link; 246 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper; 247 break; 248 } 249 250 /* Set mta register count */ 251 mac->mta_reg_count = 128; 252 /* Set rar entry count */ 253 mac->rar_entry_count = E1000_RAR_ENTRIES; 254 /* Adaptive IFS supported */ 255 mac->adaptive_ifs = true; 256 257 /* MAC-specific function pointers */ 258 switch (hw->mac.type) { 259 case e1000_82573: 260 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 261 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 262 mac->ops.led_on = e1000e_led_on_generic; 263 mac->ops.blink_led = e1000e_blink_led_generic; 264 265 /* FWSM register */ 266 mac->has_fwsm = true; 267 /* ARC supported; valid only if manageability features are 268 * enabled. 269 */ 270 mac->arc_subsystem_valid = !!(er32(FWSM) & 271 E1000_FWSM_MODE_MASK); 272 break; 273 case e1000_82574: 274 case e1000_82583: 275 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 276 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 277 mac->ops.led_on = e1000_led_on_82574; 278 break; 279 default: 280 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 281 mac->ops.led_on = e1000e_led_on_generic; 282 mac->ops.blink_led = e1000e_blink_led_generic; 283 284 /* FWSM register */ 285 mac->has_fwsm = true; 286 break; 287 } 288 289 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 290 * first NVM or PHY access. This should be done for single-port 291 * devices, and for one port only on dual-port devices so that 292 * for those devices we can still use the SMBI lock to synchronize 293 * inter-port accesses to the PHY & NVM. 294 */ 295 switch (hw->mac.type) { 296 case e1000_82571: 297 case e1000_82572: 298 swsm2 = er32(SWSM2); 299 300 if (!(swsm2 & E1000_SWSM2_LOCK)) { 301 /* Only do this for the first interface on this card */ 302 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); 303 force_clear_smbi = true; 304 } else { 305 force_clear_smbi = false; 306 } 307 break; 308 default: 309 force_clear_smbi = true; 310 break; 311 } 312 313 if (force_clear_smbi) { 314 /* Make sure SWSM.SMBI is clear */ 315 swsm = er32(SWSM); 316 if (swsm & E1000_SWSM_SMBI) { 317 /* This bit should not be set on a first interface, and 318 * indicates that the bootagent or EFI code has 319 * improperly left this bit enabled 320 */ 321 e_dbg("Please update your 82571 Bootagent\n"); 322 } 323 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 324 } 325 326 /* Initialize device specific counter of SMBI acquisition timeouts. */ 327 hw->dev_spec.e82571.smb_counter = 0; 328 329 return 0; 330 } 331 332 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) 333 { 334 struct e1000_hw *hw = &adapter->hw; 335 static int global_quad_port_a; /* global port a indication */ 336 struct pci_dev *pdev = adapter->pdev; 337 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; 338 s32 rc; 339 340 rc = e1000_init_mac_params_82571(hw); 341 if (rc) 342 return rc; 343 344 rc = e1000_init_nvm_params_82571(hw); 345 if (rc) 346 return rc; 347 348 rc = e1000_init_phy_params_82571(hw); 349 if (rc) 350 return rc; 351 352 /* tag quad port adapters first, it's used below */ 353 switch (pdev->device) { 354 case E1000_DEV_ID_82571EB_QUAD_COPPER: 355 case E1000_DEV_ID_82571EB_QUAD_FIBER: 356 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 357 case E1000_DEV_ID_82571PT_QUAD_COPPER: 358 adapter->flags |= FLAG_IS_QUAD_PORT; 359 /* mark the first port */ 360 if (global_quad_port_a == 0) 361 adapter->flags |= FLAG_IS_QUAD_PORT_A; 362 /* Reset for multiple quad port adapters */ 363 global_quad_port_a++; 364 if (global_quad_port_a == 4) 365 global_quad_port_a = 0; 366 break; 367 default: 368 break; 369 } 370 371 switch (adapter->hw.mac.type) { 372 case e1000_82571: 373 /* these dual ports don't have WoL on port B at all */ 374 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || 375 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || 376 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && 377 (is_port_b)) 378 adapter->flags &= ~FLAG_HAS_WOL; 379 /* quad ports only support WoL on port A */ 380 if (adapter->flags & FLAG_IS_QUAD_PORT && 381 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) 382 adapter->flags &= ~FLAG_HAS_WOL; 383 /* Does not support WoL on any port */ 384 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) 385 adapter->flags &= ~FLAG_HAS_WOL; 386 break; 387 case e1000_82573: 388 if (pdev->device == E1000_DEV_ID_82573L) { 389 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; 390 adapter->max_hw_frame_size = DEFAULT_JUMBO; 391 } 392 break; 393 default: 394 break; 395 } 396 397 return 0; 398 } 399 400 /** 401 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 402 * @hw: pointer to the HW structure 403 * 404 * Reads the PHY registers and stores the PHY ID and possibly the PHY 405 * revision in the hardware structure. 406 **/ 407 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 408 { 409 struct e1000_phy_info *phy = &hw->phy; 410 s32 ret_val; 411 u16 phy_id = 0; 412 413 switch (hw->mac.type) { 414 case e1000_82571: 415 case e1000_82572: 416 /* The 82571 firmware may still be configuring the PHY. 417 * In this case, we cannot access the PHY until the 418 * configuration is done. So we explicitly set the 419 * PHY ID. 420 */ 421 phy->id = IGP01E1000_I_PHY_ID; 422 break; 423 case e1000_82573: 424 return e1000e_get_phy_id(hw); 425 break; 426 case e1000_82574: 427 case e1000_82583: 428 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); 429 if (ret_val) 430 return ret_val; 431 432 phy->id = (u32)(phy_id << 16); 433 usleep_range(20, 40); 434 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); 435 if (ret_val) 436 return ret_val; 437 438 phy->id |= (u32)(phy_id); 439 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 440 break; 441 default: 442 return -E1000_ERR_PHY; 443 break; 444 } 445 446 return 0; 447 } 448 449 /** 450 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 451 * @hw: pointer to the HW structure 452 * 453 * Acquire the HW semaphore to access the PHY or NVM 454 **/ 455 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 456 { 457 u32 swsm; 458 s32 sw_timeout = hw->nvm.word_size + 1; 459 s32 fw_timeout = hw->nvm.word_size + 1; 460 s32 i = 0; 461 462 /* If we have timedout 3 times on trying to acquire 463 * the inter-port SMBI semaphore, there is old code 464 * operating on the other port, and it is not 465 * releasing SMBI. Modify the number of times that 466 * we try for the semaphore to interwork with this 467 * older code. 468 */ 469 if (hw->dev_spec.e82571.smb_counter > 2) 470 sw_timeout = 1; 471 472 /* Get the SW semaphore */ 473 while (i < sw_timeout) { 474 swsm = er32(SWSM); 475 if (!(swsm & E1000_SWSM_SMBI)) 476 break; 477 478 usleep_range(50, 100); 479 i++; 480 } 481 482 if (i == sw_timeout) { 483 e_dbg("Driver can't access device - SMBI bit is set.\n"); 484 hw->dev_spec.e82571.smb_counter++; 485 } 486 /* Get the FW semaphore. */ 487 for (i = 0; i < fw_timeout; i++) { 488 swsm = er32(SWSM); 489 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 490 491 /* Semaphore acquired if bit latched */ 492 if (er32(SWSM) & E1000_SWSM_SWESMBI) 493 break; 494 495 usleep_range(50, 100); 496 } 497 498 if (i == fw_timeout) { 499 /* Release semaphores */ 500 e1000_put_hw_semaphore_82571(hw); 501 e_dbg("Driver can't access the NVM\n"); 502 return -E1000_ERR_NVM; 503 } 504 505 return 0; 506 } 507 508 /** 509 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 510 * @hw: pointer to the HW structure 511 * 512 * Release hardware semaphore used to access the PHY or NVM 513 **/ 514 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 515 { 516 u32 swsm; 517 518 swsm = er32(SWSM); 519 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 520 ew32(SWSM, swsm); 521 } 522 523 /** 524 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 525 * @hw: pointer to the HW structure 526 * 527 * Acquire the HW semaphore during reset. 528 * 529 **/ 530 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 531 { 532 u32 extcnf_ctrl; 533 s32 i = 0; 534 535 extcnf_ctrl = er32(EXTCNF_CTRL); 536 do { 537 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 538 ew32(EXTCNF_CTRL, extcnf_ctrl); 539 extcnf_ctrl = er32(EXTCNF_CTRL); 540 541 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 542 break; 543 544 usleep_range(2000, 4000); 545 i++; 546 } while (i < MDIO_OWNERSHIP_TIMEOUT); 547 548 if (i == MDIO_OWNERSHIP_TIMEOUT) { 549 /* Release semaphores */ 550 e1000_put_hw_semaphore_82573(hw); 551 e_dbg("Driver can't access the PHY\n"); 552 return -E1000_ERR_PHY; 553 } 554 555 return 0; 556 } 557 558 /** 559 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 560 * @hw: pointer to the HW structure 561 * 562 * Release hardware semaphore used during reset. 563 * 564 **/ 565 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 566 { 567 u32 extcnf_ctrl; 568 569 extcnf_ctrl = er32(EXTCNF_CTRL); 570 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 571 ew32(EXTCNF_CTRL, extcnf_ctrl); 572 } 573 574 static DEFINE_MUTEX(swflag_mutex); 575 576 /** 577 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 578 * @hw: pointer to the HW structure 579 * 580 * Acquire the HW semaphore to access the PHY or NVM. 581 * 582 **/ 583 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 584 { 585 s32 ret_val; 586 587 mutex_lock(&swflag_mutex); 588 ret_val = e1000_get_hw_semaphore_82573(hw); 589 if (ret_val) 590 mutex_unlock(&swflag_mutex); 591 return ret_val; 592 } 593 594 /** 595 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 596 * @hw: pointer to the HW structure 597 * 598 * Release hardware semaphore used to access the PHY or NVM 599 * 600 **/ 601 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 602 { 603 e1000_put_hw_semaphore_82573(hw); 604 mutex_unlock(&swflag_mutex); 605 } 606 607 /** 608 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 609 * @hw: pointer to the HW structure 610 * @active: true to enable LPLU, false to disable 611 * 612 * Sets the LPLU D0 state according to the active flag. 613 * LPLU will not be activated unless the 614 * device autonegotiation advertisement meets standards of 615 * either 10 or 10/100 or 10/100/1000 at all duplexes. 616 * This is a function pointer entry point only called by 617 * PHY setup routines. 618 **/ 619 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 620 { 621 u32 data = er32(POEMB); 622 623 if (active) 624 data |= E1000_PHY_CTRL_D0A_LPLU; 625 else 626 data &= ~E1000_PHY_CTRL_D0A_LPLU; 627 628 ew32(POEMB, data); 629 return 0; 630 } 631 632 /** 633 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 634 * @hw: pointer to the HW structure 635 * @active: boolean used to enable/disable lplu 636 * 637 * The low power link up (lplu) state is set to the power management level D3 638 * when active is true, else clear lplu for D3. LPLU 639 * is used during Dx states where the power conservation is most important. 640 * During driver activity, SmartSpeed should be enabled so performance is 641 * maintained. 642 **/ 643 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 644 { 645 u32 data = er32(POEMB); 646 647 if (!active) { 648 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 649 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 650 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 651 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 652 data |= E1000_PHY_CTRL_NOND0A_LPLU; 653 } 654 655 ew32(POEMB, data); 656 return 0; 657 } 658 659 /** 660 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 661 * @hw: pointer to the HW structure 662 * 663 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 664 * Then for non-82573 hardware, set the EEPROM access request bit and wait 665 * for EEPROM access grant bit. If the access grant bit is not set, release 666 * hardware semaphore. 667 **/ 668 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 669 { 670 s32 ret_val; 671 672 ret_val = e1000_get_hw_semaphore_82571(hw); 673 if (ret_val) 674 return ret_val; 675 676 switch (hw->mac.type) { 677 case e1000_82573: 678 break; 679 default: 680 ret_val = e1000e_acquire_nvm(hw); 681 break; 682 } 683 684 if (ret_val) 685 e1000_put_hw_semaphore_82571(hw); 686 687 return ret_val; 688 } 689 690 /** 691 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 692 * @hw: pointer to the HW structure 693 * 694 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 695 **/ 696 static void e1000_release_nvm_82571(struct e1000_hw *hw) 697 { 698 e1000e_release_nvm(hw); 699 e1000_put_hw_semaphore_82571(hw); 700 } 701 702 /** 703 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 704 * @hw: pointer to the HW structure 705 * @offset: offset within the EEPROM to be written to 706 * @words: number of words to write 707 * @data: 16 bit word(s) to be written to the EEPROM 708 * 709 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 710 * 711 * If e1000e_update_nvm_checksum is not called after this function, the 712 * EEPROM will most likely contain an invalid checksum. 713 **/ 714 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 715 u16 *data) 716 { 717 s32 ret_val; 718 719 switch (hw->mac.type) { 720 case e1000_82573: 721 case e1000_82574: 722 case e1000_82583: 723 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 724 break; 725 case e1000_82571: 726 case e1000_82572: 727 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); 728 break; 729 default: 730 ret_val = -E1000_ERR_NVM; 731 break; 732 } 733 734 return ret_val; 735 } 736 737 /** 738 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 739 * @hw: pointer to the HW structure 740 * 741 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 742 * up to the checksum. Then calculates the EEPROM checksum and writes the 743 * value to the EEPROM. 744 **/ 745 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 746 { 747 u32 eecd; 748 s32 ret_val; 749 u16 i; 750 751 ret_val = e1000e_update_nvm_checksum_generic(hw); 752 if (ret_val) 753 return ret_val; 754 755 /* If our nvm is an EEPROM, then we're done 756 * otherwise, commit the checksum to the flash NVM. 757 */ 758 if (hw->nvm.type != e1000_nvm_flash_hw) 759 return 0; 760 761 /* Check for pending operations. */ 762 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 763 usleep_range(1000, 2000); 764 if (!(er32(EECD) & E1000_EECD_FLUPD)) 765 break; 766 } 767 768 if (i == E1000_FLASH_UPDATES) 769 return -E1000_ERR_NVM; 770 771 /* Reset the firmware if using STM opcode. */ 772 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 773 /* The enabling of and the actual reset must be done 774 * in two write cycles. 775 */ 776 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 777 e1e_flush(); 778 ew32(HICR, E1000_HICR_FW_RESET); 779 } 780 781 /* Commit the write to flash */ 782 eecd = er32(EECD) | E1000_EECD_FLUPD; 783 ew32(EECD, eecd); 784 785 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 786 usleep_range(1000, 2000); 787 if (!(er32(EECD) & E1000_EECD_FLUPD)) 788 break; 789 } 790 791 if (i == E1000_FLASH_UPDATES) 792 return -E1000_ERR_NVM; 793 794 return 0; 795 } 796 797 /** 798 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 799 * @hw: pointer to the HW structure 800 * 801 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 802 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 803 **/ 804 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 805 { 806 if (hw->nvm.type == e1000_nvm_flash_hw) 807 e1000_fix_nvm_checksum_82571(hw); 808 809 return e1000e_validate_nvm_checksum_generic(hw); 810 } 811 812 /** 813 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 814 * @hw: pointer to the HW structure 815 * @offset: offset within the EEPROM to be written to 816 * @words: number of words to write 817 * @data: 16 bit word(s) to be written to the EEPROM 818 * 819 * After checking for invalid values, poll the EEPROM to ensure the previous 820 * command has completed before trying to write the next word. After write 821 * poll for completion. 822 * 823 * If e1000e_update_nvm_checksum is not called after this function, the 824 * EEPROM will most likely contain an invalid checksum. 825 **/ 826 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 827 u16 words, u16 *data) 828 { 829 struct e1000_nvm_info *nvm = &hw->nvm; 830 u32 i, eewr = 0; 831 s32 ret_val = 0; 832 833 /* A check for invalid values: offset too large, too many words, 834 * and not enough words. 835 */ 836 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 837 (words == 0)) { 838 e_dbg("nvm parameter(s) out of bounds\n"); 839 return -E1000_ERR_NVM; 840 } 841 842 for (i = 0; i < words; i++) { 843 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) | 844 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | 845 E1000_NVM_RW_REG_START); 846 847 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 848 if (ret_val) 849 break; 850 851 ew32(EEWR, eewr); 852 853 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 854 if (ret_val) 855 break; 856 } 857 858 return ret_val; 859 } 860 861 /** 862 * e1000_get_cfg_done_82571 - Poll for configuration done 863 * @hw: pointer to the HW structure 864 * 865 * Reads the management control register for the config done bit to be set. 866 **/ 867 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 868 { 869 s32 timeout = PHY_CFG_TIMEOUT; 870 871 while (timeout) { 872 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 873 break; 874 usleep_range(1000, 2000); 875 timeout--; 876 } 877 if (!timeout) { 878 e_dbg("MNG configuration cycle has not completed.\n"); 879 return -E1000_ERR_RESET; 880 } 881 882 return 0; 883 } 884 885 /** 886 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 887 * @hw: pointer to the HW structure 888 * @active: true to enable LPLU, false to disable 889 * 890 * Sets the LPLU D0 state according to the active flag. When activating LPLU 891 * this function also disables smart speed and vice versa. LPLU will not be 892 * activated unless the device autonegotiation advertisement meets standards 893 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 894 * pointer entry point only called by PHY setup routines. 895 **/ 896 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 897 { 898 struct e1000_phy_info *phy = &hw->phy; 899 s32 ret_val; 900 u16 data; 901 902 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 903 if (ret_val) 904 return ret_val; 905 906 if (active) { 907 data |= IGP02E1000_PM_D0_LPLU; 908 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 909 if (ret_val) 910 return ret_val; 911 912 /* When LPLU is enabled, we should disable SmartSpeed */ 913 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 914 if (ret_val) 915 return ret_val; 916 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 917 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 918 if (ret_val) 919 return ret_val; 920 } else { 921 data &= ~IGP02E1000_PM_D0_LPLU; 922 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 923 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 924 * during Dx states where the power conservation is most 925 * important. During driver activity we should enable 926 * SmartSpeed, so performance is maintained. 927 */ 928 if (phy->smart_speed == e1000_smart_speed_on) { 929 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 930 &data); 931 if (ret_val) 932 return ret_val; 933 934 data |= IGP01E1000_PSCFR_SMART_SPEED; 935 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 936 data); 937 if (ret_val) 938 return ret_val; 939 } else if (phy->smart_speed == e1000_smart_speed_off) { 940 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 941 &data); 942 if (ret_val) 943 return ret_val; 944 945 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 946 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 947 data); 948 if (ret_val) 949 return ret_val; 950 } 951 } 952 953 return 0; 954 } 955 956 /** 957 * e1000_reset_hw_82571 - Reset hardware 958 * @hw: pointer to the HW structure 959 * 960 * This resets the hardware into a known state. 961 **/ 962 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 963 { 964 u32 ctrl, ctrl_ext, eecd, tctl; 965 s32 ret_val; 966 967 /* Prevent the PCI-E bus from sticking if there is no TLP connection 968 * on the last TLP read/write transaction when MAC is reset. 969 */ 970 ret_val = e1000e_disable_pcie_master(hw); 971 if (ret_val) 972 e_dbg("PCI-E Master disable polling has failed.\n"); 973 974 e_dbg("Masking off all interrupts\n"); 975 ew32(IMC, 0xffffffff); 976 977 ew32(RCTL, 0); 978 tctl = er32(TCTL); 979 tctl &= ~E1000_TCTL_EN; 980 ew32(TCTL, tctl); 981 e1e_flush(); 982 983 usleep_range(10000, 20000); 984 985 /* Must acquire the MDIO ownership before MAC reset. 986 * Ownership defaults to firmware after a reset. 987 */ 988 switch (hw->mac.type) { 989 case e1000_82573: 990 ret_val = e1000_get_hw_semaphore_82573(hw); 991 break; 992 case e1000_82574: 993 case e1000_82583: 994 ret_val = e1000_get_hw_semaphore_82574(hw); 995 break; 996 default: 997 break; 998 } 999 1000 ctrl = er32(CTRL); 1001 1002 e_dbg("Issuing a global reset to MAC\n"); 1003 ew32(CTRL, ctrl | E1000_CTRL_RST); 1004 1005 /* Must release MDIO ownership and mutex after MAC reset. */ 1006 switch (hw->mac.type) { 1007 case e1000_82573: 1008 /* Release mutex only if the hw semaphore is acquired */ 1009 if (!ret_val) 1010 e1000_put_hw_semaphore_82573(hw); 1011 break; 1012 case e1000_82574: 1013 case e1000_82583: 1014 /* Release mutex only if the hw semaphore is acquired */ 1015 if (!ret_val) 1016 e1000_put_hw_semaphore_82574(hw); 1017 break; 1018 default: 1019 break; 1020 } 1021 1022 if (hw->nvm.type == e1000_nvm_flash_hw) { 1023 usleep_range(10, 20); 1024 ctrl_ext = er32(CTRL_EXT); 1025 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1026 ew32(CTRL_EXT, ctrl_ext); 1027 e1e_flush(); 1028 } 1029 1030 ret_val = e1000e_get_auto_rd_done(hw); 1031 if (ret_val) 1032 /* We don't want to continue accessing MAC registers. */ 1033 return ret_val; 1034 1035 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1036 * Need to wait for Phy configuration completion before accessing 1037 * NVM and Phy. 1038 */ 1039 1040 switch (hw->mac.type) { 1041 case e1000_82571: 1042 case e1000_82572: 1043 /* REQ and GNT bits need to be cleared when using AUTO_RD 1044 * to access the EEPROM. 1045 */ 1046 eecd = er32(EECD); 1047 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1048 ew32(EECD, eecd); 1049 break; 1050 case e1000_82573: 1051 case e1000_82574: 1052 case e1000_82583: 1053 msleep(25); 1054 break; 1055 default: 1056 break; 1057 } 1058 1059 /* Clear any pending interrupt events. */ 1060 ew32(IMC, 0xffffffff); 1061 er32(ICR); 1062 1063 if (hw->mac.type == e1000_82571) { 1064 /* Install any alternate MAC address into RAR0 */ 1065 ret_val = e1000_check_alt_mac_addr_generic(hw); 1066 if (ret_val) 1067 return ret_val; 1068 1069 e1000e_set_laa_state_82571(hw, true); 1070 } 1071 1072 /* Reinitialize the 82571 serdes link state machine */ 1073 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1074 hw->mac.serdes_link_state = e1000_serdes_link_down; 1075 1076 return 0; 1077 } 1078 1079 /** 1080 * e1000_init_hw_82571 - Initialize hardware 1081 * @hw: pointer to the HW structure 1082 * 1083 * This inits the hardware readying it for operation. 1084 **/ 1085 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1086 { 1087 struct e1000_mac_info *mac = &hw->mac; 1088 u32 reg_data; 1089 s32 ret_val; 1090 u16 i, rar_count = mac->rar_entry_count; 1091 1092 e1000_initialize_hw_bits_82571(hw); 1093 1094 /* Initialize identification LED */ 1095 ret_val = mac->ops.id_led_init(hw); 1096 /* An error is not fatal and we should not stop init due to this */ 1097 if (ret_val) 1098 e_dbg("Error initializing identification LED\n"); 1099 1100 /* Disabling VLAN filtering */ 1101 e_dbg("Initializing the IEEE VLAN\n"); 1102 mac->ops.clear_vfta(hw); 1103 1104 /* Setup the receive address. 1105 * If, however, a locally administered address was assigned to the 1106 * 82571, we must reserve a RAR for it to work around an issue where 1107 * resetting one port will reload the MAC on the other port. 1108 */ 1109 if (e1000e_get_laa_state_82571(hw)) 1110 rar_count--; 1111 e1000e_init_rx_addrs(hw, rar_count); 1112 1113 /* Zero out the Multicast HASH table */ 1114 e_dbg("Zeroing the MTA\n"); 1115 for (i = 0; i < mac->mta_reg_count; i++) 1116 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1117 1118 /* Setup link and flow control */ 1119 ret_val = mac->ops.setup_link(hw); 1120 1121 /* Set the transmit descriptor write-back policy */ 1122 reg_data = er32(TXDCTL(0)); 1123 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1124 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 1125 ew32(TXDCTL(0), reg_data); 1126 1127 /* ...for both queues. */ 1128 switch (mac->type) { 1129 case e1000_82573: 1130 e1000e_enable_tx_pkt_filtering(hw); 1131 /* fall through */ 1132 case e1000_82574: 1133 case e1000_82583: 1134 reg_data = er32(GCR); 1135 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1136 ew32(GCR, reg_data); 1137 break; 1138 default: 1139 reg_data = er32(TXDCTL(1)); 1140 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1141 E1000_TXDCTL_FULL_TX_DESC_WB | 1142 E1000_TXDCTL_COUNT_DESC); 1143 ew32(TXDCTL(1), reg_data); 1144 break; 1145 } 1146 1147 /* Clear all of the statistics registers (clear on read). It is 1148 * important that we do this after we have tried to establish link 1149 * because the symbol error count will increment wildly if there 1150 * is no link. 1151 */ 1152 e1000_clear_hw_cntrs_82571(hw); 1153 1154 return ret_val; 1155 } 1156 1157 /** 1158 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1159 * @hw: pointer to the HW structure 1160 * 1161 * Initializes required hardware-dependent bits needed for normal operation. 1162 **/ 1163 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1164 { 1165 u32 reg; 1166 1167 /* Transmit Descriptor Control 0 */ 1168 reg = er32(TXDCTL(0)); 1169 reg |= (1 << 22); 1170 ew32(TXDCTL(0), reg); 1171 1172 /* Transmit Descriptor Control 1 */ 1173 reg = er32(TXDCTL(1)); 1174 reg |= (1 << 22); 1175 ew32(TXDCTL(1), reg); 1176 1177 /* Transmit Arbitration Control 0 */ 1178 reg = er32(TARC(0)); 1179 reg &= ~(0xF << 27); /* 30:27 */ 1180 switch (hw->mac.type) { 1181 case e1000_82571: 1182 case e1000_82572: 1183 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1184 break; 1185 case e1000_82574: 1186 case e1000_82583: 1187 reg |= (1 << 26); 1188 break; 1189 default: 1190 break; 1191 } 1192 ew32(TARC(0), reg); 1193 1194 /* Transmit Arbitration Control 1 */ 1195 reg = er32(TARC(1)); 1196 switch (hw->mac.type) { 1197 case e1000_82571: 1198 case e1000_82572: 1199 reg &= ~((1 << 29) | (1 << 30)); 1200 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1201 if (er32(TCTL) & E1000_TCTL_MULR) 1202 reg &= ~(1 << 28); 1203 else 1204 reg |= (1 << 28); 1205 ew32(TARC(1), reg); 1206 break; 1207 default: 1208 break; 1209 } 1210 1211 /* Device Control */ 1212 switch (hw->mac.type) { 1213 case e1000_82573: 1214 case e1000_82574: 1215 case e1000_82583: 1216 reg = er32(CTRL); 1217 reg &= ~(1 << 29); 1218 ew32(CTRL, reg); 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 /* Extended Device Control */ 1225 switch (hw->mac.type) { 1226 case e1000_82573: 1227 case e1000_82574: 1228 case e1000_82583: 1229 reg = er32(CTRL_EXT); 1230 reg &= ~(1 << 23); 1231 reg |= (1 << 22); 1232 ew32(CTRL_EXT, reg); 1233 break; 1234 default: 1235 break; 1236 } 1237 1238 if (hw->mac.type == e1000_82571) { 1239 reg = er32(PBA_ECC); 1240 reg |= E1000_PBA_ECC_CORR_EN; 1241 ew32(PBA_ECC, reg); 1242 } 1243 1244 /* Workaround for hardware errata. 1245 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1246 */ 1247 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 1248 reg = er32(CTRL_EXT); 1249 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1250 ew32(CTRL_EXT, reg); 1251 } 1252 1253 /* Disable IPv6 extension header parsing because some malformed 1254 * IPv6 headers can hang the Rx. 1255 */ 1256 if (hw->mac.type <= e1000_82573) { 1257 reg = er32(RFCTL); 1258 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1259 ew32(RFCTL, reg); 1260 } 1261 1262 /* PCI-Ex Control Registers */ 1263 switch (hw->mac.type) { 1264 case e1000_82574: 1265 case e1000_82583: 1266 reg = er32(GCR); 1267 reg |= (1 << 22); 1268 ew32(GCR, reg); 1269 1270 /* Workaround for hardware errata. 1271 * apply workaround for hardware errata documented in errata 1272 * docs Fixes issue where some error prone or unreliable PCIe 1273 * completions are occurring, particularly with ASPM enabled. 1274 * Without fix, issue can cause Tx timeouts. 1275 */ 1276 reg = er32(GCR2); 1277 reg |= 1; 1278 ew32(GCR2, reg); 1279 break; 1280 default: 1281 break; 1282 } 1283 } 1284 1285 /** 1286 * e1000_clear_vfta_82571 - Clear VLAN filter table 1287 * @hw: pointer to the HW structure 1288 * 1289 * Clears the register array which contains the VLAN filter table by 1290 * setting all the values to 0. 1291 **/ 1292 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1293 { 1294 u32 offset; 1295 u32 vfta_value = 0; 1296 u32 vfta_offset = 0; 1297 u32 vfta_bit_in_reg = 0; 1298 1299 switch (hw->mac.type) { 1300 case e1000_82573: 1301 case e1000_82574: 1302 case e1000_82583: 1303 if (hw->mng_cookie.vlan_id != 0) { 1304 /* The VFTA is a 4096b bit-field, each identifying 1305 * a single VLAN ID. The following operations 1306 * determine which 32b entry (i.e. offset) into the 1307 * array we want to set the VLAN ID (i.e. bit) of 1308 * the manageability unit. 1309 */ 1310 vfta_offset = (hw->mng_cookie.vlan_id >> 1311 E1000_VFTA_ENTRY_SHIFT) & 1312 E1000_VFTA_ENTRY_MASK; 1313 vfta_bit_in_reg = 1314 1 << (hw->mng_cookie.vlan_id & 1315 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1316 } 1317 break; 1318 default: 1319 break; 1320 } 1321 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1322 /* If the offset we want to clear is the same offset of the 1323 * manageability VLAN ID, then clear all bits except that of 1324 * the manageability unit. 1325 */ 1326 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1328 e1e_flush(); 1329 } 1330 } 1331 1332 /** 1333 * e1000_check_mng_mode_82574 - Check manageability is enabled 1334 * @hw: pointer to the HW structure 1335 * 1336 * Reads the NVM Initialization Control Word 2 and returns true 1337 * (>0) if any manageability is enabled, else false (0). 1338 **/ 1339 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1340 { 1341 u16 data; 1342 1343 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1344 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1345 } 1346 1347 /** 1348 * e1000_led_on_82574 - Turn LED on 1349 * @hw: pointer to the HW structure 1350 * 1351 * Turn LED on. 1352 **/ 1353 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1354 { 1355 u32 ctrl; 1356 u32 i; 1357 1358 ctrl = hw->mac.ledctl_mode2; 1359 if (!(E1000_STATUS_LU & er32(STATUS))) { 1360 /* If no link, then turn LED on by setting the invert bit 1361 * for each LED that's "on" (0x0E) in ledctl_mode2. 1362 */ 1363 for (i = 0; i < 4; i++) 1364 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1365 E1000_LEDCTL_MODE_LED_ON) 1366 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1367 } 1368 ew32(LEDCTL, ctrl); 1369 1370 return 0; 1371 } 1372 1373 /** 1374 * e1000_check_phy_82574 - check 82574 phy hung state 1375 * @hw: pointer to the HW structure 1376 * 1377 * Returns whether phy is hung or not 1378 **/ 1379 bool e1000_check_phy_82574(struct e1000_hw *hw) 1380 { 1381 u16 status_1kbt = 0; 1382 u16 receive_errors = 0; 1383 s32 ret_val; 1384 1385 /* Read PHY Receive Error counter first, if its is max - all F's then 1386 * read the Base1000T status register If both are max then PHY is hung. 1387 */ 1388 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); 1389 if (ret_val) 1390 return false; 1391 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1392 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); 1393 if (ret_val) 1394 return false; 1395 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1396 E1000_IDLE_ERROR_COUNT_MASK) 1397 return true; 1398 } 1399 1400 return false; 1401 } 1402 1403 /** 1404 * e1000_setup_link_82571 - Setup flow control and link settings 1405 * @hw: pointer to the HW structure 1406 * 1407 * Determines which flow control settings to use, then configures flow 1408 * control. Calls the appropriate media-specific link configuration 1409 * function. Assuming the adapter has a valid link partner, a valid link 1410 * should be established. Assumes the hardware has previously been reset 1411 * and the transmitter and receiver are not enabled. 1412 **/ 1413 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1414 { 1415 /* 82573 does not have a word in the NVM to determine 1416 * the default flow control setting, so we explicitly 1417 * set it to full. 1418 */ 1419 switch (hw->mac.type) { 1420 case e1000_82573: 1421 case e1000_82574: 1422 case e1000_82583: 1423 if (hw->fc.requested_mode == e1000_fc_default) 1424 hw->fc.requested_mode = e1000_fc_full; 1425 break; 1426 default: 1427 break; 1428 } 1429 1430 return e1000e_setup_link_generic(hw); 1431 } 1432 1433 /** 1434 * e1000_setup_copper_link_82571 - Configure copper link settings 1435 * @hw: pointer to the HW structure 1436 * 1437 * Configures the link for auto-neg or forced speed and duplex. Then we check 1438 * for link, once link is established calls to configure collision distance 1439 * and flow control are called. 1440 **/ 1441 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1442 { 1443 u32 ctrl; 1444 s32 ret_val; 1445 1446 ctrl = er32(CTRL); 1447 ctrl |= E1000_CTRL_SLU; 1448 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1449 ew32(CTRL, ctrl); 1450 1451 switch (hw->phy.type) { 1452 case e1000_phy_m88: 1453 case e1000_phy_bm: 1454 ret_val = e1000e_copper_link_setup_m88(hw); 1455 break; 1456 case e1000_phy_igp_2: 1457 ret_val = e1000e_copper_link_setup_igp(hw); 1458 break; 1459 default: 1460 return -E1000_ERR_PHY; 1461 break; 1462 } 1463 1464 if (ret_val) 1465 return ret_val; 1466 1467 return e1000e_setup_copper_link(hw); 1468 } 1469 1470 /** 1471 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1472 * @hw: pointer to the HW structure 1473 * 1474 * Configures collision distance and flow control for fiber and serdes links. 1475 * Upon successful setup, poll for link. 1476 **/ 1477 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1478 { 1479 switch (hw->mac.type) { 1480 case e1000_82571: 1481 case e1000_82572: 1482 /* If SerDes loopback mode is entered, there is no form 1483 * of reset to take the adapter out of that mode. So we 1484 * have to explicitly take the adapter out of loopback 1485 * mode. This prevents drivers from twiddling their thumbs 1486 * if another tool failed to take it out of loopback mode. 1487 */ 1488 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1489 break; 1490 default: 1491 break; 1492 } 1493 1494 return e1000e_setup_fiber_serdes_link(hw); 1495 } 1496 1497 /** 1498 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1499 * @hw: pointer to the HW structure 1500 * 1501 * Reports the link state as up or down. 1502 * 1503 * If autonegotiation is supported by the link partner, the link state is 1504 * determined by the result of autonegotiation. This is the most likely case. 1505 * If autonegotiation is not supported by the link partner, and the link 1506 * has a valid signal, force the link up. 1507 * 1508 * The link state is represented internally here by 4 states: 1509 * 1510 * 1) down 1511 * 2) autoneg_progress 1512 * 3) autoneg_complete (the link successfully autonegotiated) 1513 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1514 * 1515 **/ 1516 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1517 { 1518 struct e1000_mac_info *mac = &hw->mac; 1519 u32 rxcw; 1520 u32 ctrl; 1521 u32 status; 1522 u32 txcw; 1523 u32 i; 1524 s32 ret_val = 0; 1525 1526 ctrl = er32(CTRL); 1527 status = er32(STATUS); 1528 er32(RXCW); 1529 /* SYNCH bit and IV bit are sticky */ 1530 usleep_range(10, 20); 1531 rxcw = er32(RXCW); 1532 1533 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1534 /* Receiver is synchronized with no invalid bits. */ 1535 switch (mac->serdes_link_state) { 1536 case e1000_serdes_link_autoneg_complete: 1537 if (!(status & E1000_STATUS_LU)) { 1538 /* We have lost link, retry autoneg before 1539 * reporting link failure 1540 */ 1541 mac->serdes_link_state = 1542 e1000_serdes_link_autoneg_progress; 1543 mac->serdes_has_link = false; 1544 e_dbg("AN_UP -> AN_PROG\n"); 1545 } else { 1546 mac->serdes_has_link = true; 1547 } 1548 break; 1549 1550 case e1000_serdes_link_forced_up: 1551 /* If we are receiving /C/ ordered sets, re-enable 1552 * auto-negotiation in the TXCW register and disable 1553 * forced link in the Device Control register in an 1554 * attempt to auto-negotiate with our link partner. 1555 */ 1556 if (rxcw & E1000_RXCW_C) { 1557 /* Enable autoneg, and unforce link up */ 1558 ew32(TXCW, mac->txcw); 1559 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1560 mac->serdes_link_state = 1561 e1000_serdes_link_autoneg_progress; 1562 mac->serdes_has_link = false; 1563 e_dbg("FORCED_UP -> AN_PROG\n"); 1564 } else { 1565 mac->serdes_has_link = true; 1566 } 1567 break; 1568 1569 case e1000_serdes_link_autoneg_progress: 1570 if (rxcw & E1000_RXCW_C) { 1571 /* We received /C/ ordered sets, meaning the 1572 * link partner has autonegotiated, and we can 1573 * trust the Link Up (LU) status bit. 1574 */ 1575 if (status & E1000_STATUS_LU) { 1576 mac->serdes_link_state = 1577 e1000_serdes_link_autoneg_complete; 1578 e_dbg("AN_PROG -> AN_UP\n"); 1579 mac->serdes_has_link = true; 1580 } else { 1581 /* Autoneg completed, but failed. */ 1582 mac->serdes_link_state = 1583 e1000_serdes_link_down; 1584 e_dbg("AN_PROG -> DOWN\n"); 1585 } 1586 } else { 1587 /* The link partner did not autoneg. 1588 * Force link up and full duplex, and change 1589 * state to forced. 1590 */ 1591 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1592 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1593 ew32(CTRL, ctrl); 1594 1595 /* Configure Flow Control after link up. */ 1596 ret_val = e1000e_config_fc_after_link_up(hw); 1597 if (ret_val) { 1598 e_dbg("Error config flow control\n"); 1599 break; 1600 } 1601 mac->serdes_link_state = 1602 e1000_serdes_link_forced_up; 1603 mac->serdes_has_link = true; 1604 e_dbg("AN_PROG -> FORCED_UP\n"); 1605 } 1606 break; 1607 1608 case e1000_serdes_link_down: 1609 default: 1610 /* The link was down but the receiver has now gained 1611 * valid sync, so lets see if we can bring the link 1612 * up. 1613 */ 1614 ew32(TXCW, mac->txcw); 1615 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1616 mac->serdes_link_state = 1617 e1000_serdes_link_autoneg_progress; 1618 mac->serdes_has_link = false; 1619 e_dbg("DOWN -> AN_PROG\n"); 1620 break; 1621 } 1622 } else { 1623 if (!(rxcw & E1000_RXCW_SYNCH)) { 1624 mac->serdes_has_link = false; 1625 mac->serdes_link_state = e1000_serdes_link_down; 1626 e_dbg("ANYSTATE -> DOWN\n"); 1627 } else { 1628 /* Check several times, if SYNCH bit and CONFIG 1629 * bit both are consistently 1 then simply ignore 1630 * the IV bit and restart Autoneg 1631 */ 1632 for (i = 0; i < AN_RETRY_COUNT; i++) { 1633 usleep_range(10, 20); 1634 rxcw = er32(RXCW); 1635 if ((rxcw & E1000_RXCW_SYNCH) && 1636 (rxcw & E1000_RXCW_C)) 1637 continue; 1638 1639 if (rxcw & E1000_RXCW_IV) { 1640 mac->serdes_has_link = false; 1641 mac->serdes_link_state = 1642 e1000_serdes_link_down; 1643 e_dbg("ANYSTATE -> DOWN\n"); 1644 break; 1645 } 1646 } 1647 1648 if (i == AN_RETRY_COUNT) { 1649 txcw = er32(TXCW); 1650 txcw |= E1000_TXCW_ANE; 1651 ew32(TXCW, txcw); 1652 mac->serdes_link_state = 1653 e1000_serdes_link_autoneg_progress; 1654 mac->serdes_has_link = false; 1655 e_dbg("ANYSTATE -> AN_PROG\n"); 1656 } 1657 } 1658 } 1659 1660 return ret_val; 1661 } 1662 1663 /** 1664 * e1000_valid_led_default_82571 - Verify a valid default LED config 1665 * @hw: pointer to the HW structure 1666 * @data: pointer to the NVM (EEPROM) 1667 * 1668 * Read the EEPROM for the current default LED configuration. If the 1669 * LED configuration is not valid, set to a valid LED configuration. 1670 **/ 1671 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1672 { 1673 s32 ret_val; 1674 1675 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1676 if (ret_val) { 1677 e_dbg("NVM Read Error\n"); 1678 return ret_val; 1679 } 1680 1681 switch (hw->mac.type) { 1682 case e1000_82573: 1683 case e1000_82574: 1684 case e1000_82583: 1685 if (*data == ID_LED_RESERVED_F746) 1686 *data = ID_LED_DEFAULT_82573; 1687 break; 1688 default: 1689 if (*data == ID_LED_RESERVED_0000 || 1690 *data == ID_LED_RESERVED_FFFF) 1691 *data = ID_LED_DEFAULT; 1692 break; 1693 } 1694 1695 return 0; 1696 } 1697 1698 /** 1699 * e1000e_get_laa_state_82571 - Get locally administered address state 1700 * @hw: pointer to the HW structure 1701 * 1702 * Retrieve and return the current locally administered address state. 1703 **/ 1704 bool e1000e_get_laa_state_82571(struct e1000_hw *hw) 1705 { 1706 if (hw->mac.type != e1000_82571) 1707 return false; 1708 1709 return hw->dev_spec.e82571.laa_is_present; 1710 } 1711 1712 /** 1713 * e1000e_set_laa_state_82571 - Set locally administered address state 1714 * @hw: pointer to the HW structure 1715 * @state: enable/disable locally administered address 1716 * 1717 * Enable/Disable the current locally administered address state. 1718 **/ 1719 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 1720 { 1721 if (hw->mac.type != e1000_82571) 1722 return; 1723 1724 hw->dev_spec.e82571.laa_is_present = state; 1725 1726 /* If workaround is activated... */ 1727 if (state) 1728 /* Hold a copy of the LAA in RAR[14] This is done so that 1729 * between the time RAR[0] gets clobbered and the time it 1730 * gets fixed, the actual LAA is in one of the RARs and no 1731 * incoming packets directed to this port are dropped. 1732 * Eventually the LAA will be in RAR[0] and RAR[14]. 1733 */ 1734 hw->mac.ops.rar_set(hw, hw->mac.addr, 1735 hw->mac.rar_entry_count - 1); 1736 } 1737 1738 /** 1739 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1740 * @hw: pointer to the HW structure 1741 * 1742 * Verifies that the EEPROM has completed the update. After updating the 1743 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1744 * the checksum fix is not implemented, we need to set the bit and update 1745 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1746 * we need to return bad checksum. 1747 **/ 1748 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1749 { 1750 struct e1000_nvm_info *nvm = &hw->nvm; 1751 s32 ret_val; 1752 u16 data; 1753 1754 if (nvm->type != e1000_nvm_flash_hw) 1755 return 0; 1756 1757 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1758 * 10h-12h. Checksum may need to be fixed. 1759 */ 1760 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1761 if (ret_val) 1762 return ret_val; 1763 1764 if (!(data & 0x10)) { 1765 /* Read 0x23 and check bit 15. This bit is a 1 1766 * when the checksum has already been fixed. If 1767 * the checksum is still wrong and this bit is a 1768 * 1, we need to return bad checksum. Otherwise, 1769 * we need to set this bit to a 1 and update the 1770 * checksum. 1771 */ 1772 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1773 if (ret_val) 1774 return ret_val; 1775 1776 if (!(data & 0x8000)) { 1777 data |= 0x8000; 1778 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1779 if (ret_val) 1780 return ret_val; 1781 ret_val = e1000e_update_nvm_checksum(hw); 1782 if (ret_val) 1783 return ret_val; 1784 } 1785 } 1786 1787 return 0; 1788 } 1789 1790 /** 1791 * e1000_read_mac_addr_82571 - Read device MAC address 1792 * @hw: pointer to the HW structure 1793 **/ 1794 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1795 { 1796 if (hw->mac.type == e1000_82571) { 1797 s32 ret_val; 1798 1799 /* If there's an alternate MAC address place it in RAR0 1800 * so that it will override the Si installed default perm 1801 * address. 1802 */ 1803 ret_val = e1000_check_alt_mac_addr_generic(hw); 1804 if (ret_val) 1805 return ret_val; 1806 } 1807 1808 return e1000_read_mac_addr_generic(hw); 1809 } 1810 1811 /** 1812 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1813 * @hw: pointer to the HW structure 1814 * 1815 * In the case of a PHY power down to save power, or to turn off link during a 1816 * driver unload, or wake on lan is not enabled, remove the link. 1817 **/ 1818 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1819 { 1820 struct e1000_phy_info *phy = &hw->phy; 1821 struct e1000_mac_info *mac = &hw->mac; 1822 1823 if (!phy->ops.check_reset_block) 1824 return; 1825 1826 /* If the management interface is not enabled, then power down */ 1827 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1828 e1000_power_down_phy_copper(hw); 1829 } 1830 1831 /** 1832 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1833 * @hw: pointer to the HW structure 1834 * 1835 * Clears the hardware counters by reading the counter registers. 1836 **/ 1837 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1838 { 1839 e1000e_clear_hw_cntrs_base(hw); 1840 1841 er32(PRC64); 1842 er32(PRC127); 1843 er32(PRC255); 1844 er32(PRC511); 1845 er32(PRC1023); 1846 er32(PRC1522); 1847 er32(PTC64); 1848 er32(PTC127); 1849 er32(PTC255); 1850 er32(PTC511); 1851 er32(PTC1023); 1852 er32(PTC1522); 1853 1854 er32(ALGNERRC); 1855 er32(RXERRC); 1856 er32(TNCRS); 1857 er32(CEXTERR); 1858 er32(TSCTC); 1859 er32(TSCTFC); 1860 1861 er32(MGTPRC); 1862 er32(MGTPDC); 1863 er32(MGTPTC); 1864 1865 er32(IAC); 1866 er32(ICRXOC); 1867 1868 er32(ICRXPTC); 1869 er32(ICRXATC); 1870 er32(ICTXPTC); 1871 er32(ICTXATC); 1872 er32(ICTXQEC); 1873 er32(ICTXQMTC); 1874 er32(ICRXDMTC); 1875 } 1876 1877 static const struct e1000_mac_operations e82571_mac_ops = { 1878 /* .check_mng_mode: mac type dependent */ 1879 /* .check_for_link: media type dependent */ 1880 .id_led_init = e1000e_id_led_init_generic, 1881 .cleanup_led = e1000e_cleanup_led_generic, 1882 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, 1883 .get_bus_info = e1000e_get_bus_info_pcie, 1884 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1885 /* .get_link_up_info: media type dependent */ 1886 /* .led_on: mac type dependent */ 1887 .led_off = e1000e_led_off_generic, 1888 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1889 .write_vfta = e1000_write_vfta_generic, 1890 .clear_vfta = e1000_clear_vfta_82571, 1891 .reset_hw = e1000_reset_hw_82571, 1892 .init_hw = e1000_init_hw_82571, 1893 .setup_link = e1000_setup_link_82571, 1894 /* .setup_physical_interface: media type dependent */ 1895 .setup_led = e1000e_setup_led_generic, 1896 .config_collision_dist = e1000e_config_collision_dist_generic, 1897 .read_mac_addr = e1000_read_mac_addr_82571, 1898 .rar_set = e1000e_rar_set_generic, 1899 }; 1900 1901 static const struct e1000_phy_operations e82_phy_ops_igp = { 1902 .acquire = e1000_get_hw_semaphore_82571, 1903 .check_polarity = e1000_check_polarity_igp, 1904 .check_reset_block = e1000e_check_reset_block_generic, 1905 .commit = NULL, 1906 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, 1907 .get_cfg_done = e1000_get_cfg_done_82571, 1908 .get_cable_length = e1000e_get_cable_length_igp_2, 1909 .get_info = e1000e_get_phy_info_igp, 1910 .read_reg = e1000e_read_phy_reg_igp, 1911 .release = e1000_put_hw_semaphore_82571, 1912 .reset = e1000e_phy_hw_reset_generic, 1913 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1914 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1915 .write_reg = e1000e_write_phy_reg_igp, 1916 .cfg_on_link_up = NULL, 1917 }; 1918 1919 static const struct e1000_phy_operations e82_phy_ops_m88 = { 1920 .acquire = e1000_get_hw_semaphore_82571, 1921 .check_polarity = e1000_check_polarity_m88, 1922 .check_reset_block = e1000e_check_reset_block_generic, 1923 .commit = e1000e_phy_sw_reset, 1924 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1925 .get_cfg_done = e1000e_get_cfg_done_generic, 1926 .get_cable_length = e1000e_get_cable_length_m88, 1927 .get_info = e1000e_get_phy_info_m88, 1928 .read_reg = e1000e_read_phy_reg_m88, 1929 .release = e1000_put_hw_semaphore_82571, 1930 .reset = e1000e_phy_hw_reset_generic, 1931 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1932 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1933 .write_reg = e1000e_write_phy_reg_m88, 1934 .cfg_on_link_up = NULL, 1935 }; 1936 1937 static const struct e1000_phy_operations e82_phy_ops_bm = { 1938 .acquire = e1000_get_hw_semaphore_82571, 1939 .check_polarity = e1000_check_polarity_m88, 1940 .check_reset_block = e1000e_check_reset_block_generic, 1941 .commit = e1000e_phy_sw_reset, 1942 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1943 .get_cfg_done = e1000e_get_cfg_done_generic, 1944 .get_cable_length = e1000e_get_cable_length_m88, 1945 .get_info = e1000e_get_phy_info_m88, 1946 .read_reg = e1000e_read_phy_reg_bm2, 1947 .release = e1000_put_hw_semaphore_82571, 1948 .reset = e1000e_phy_hw_reset_generic, 1949 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1950 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1951 .write_reg = e1000e_write_phy_reg_bm2, 1952 .cfg_on_link_up = NULL, 1953 }; 1954 1955 static const struct e1000_nvm_operations e82571_nvm_ops = { 1956 .acquire = e1000_acquire_nvm_82571, 1957 .read = e1000e_read_nvm_eerd, 1958 .release = e1000_release_nvm_82571, 1959 .reload = e1000e_reload_nvm_generic, 1960 .update = e1000_update_nvm_checksum_82571, 1961 .valid_led_default = e1000_valid_led_default_82571, 1962 .validate = e1000_validate_nvm_checksum_82571, 1963 .write = e1000_write_nvm_82571, 1964 }; 1965 1966 const struct e1000_info e1000_82571_info = { 1967 .mac = e1000_82571, 1968 .flags = FLAG_HAS_HW_VLAN_FILTER 1969 | FLAG_HAS_JUMBO_FRAMES 1970 | FLAG_HAS_WOL 1971 | FLAG_APME_IN_CTRL3 1972 | FLAG_HAS_CTRLEXT_ON_LOAD 1973 | FLAG_HAS_SMART_POWER_DOWN 1974 | FLAG_RESET_OVERWRITES_LAA /* errata */ 1975 | FLAG_TARC_SPEED_MODE_BIT /* errata */ 1976 | FLAG_APME_CHECK_PORT_B, 1977 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1978 | FLAG2_DMA_BURST, 1979 .pba = 38, 1980 .max_hw_frame_size = DEFAULT_JUMBO, 1981 .get_variants = e1000_get_variants_82571, 1982 .mac_ops = &e82571_mac_ops, 1983 .phy_ops = &e82_phy_ops_igp, 1984 .nvm_ops = &e82571_nvm_ops, 1985 }; 1986 1987 const struct e1000_info e1000_82572_info = { 1988 .mac = e1000_82572, 1989 .flags = FLAG_HAS_HW_VLAN_FILTER 1990 | FLAG_HAS_JUMBO_FRAMES 1991 | FLAG_HAS_WOL 1992 | FLAG_APME_IN_CTRL3 1993 | FLAG_HAS_CTRLEXT_ON_LOAD 1994 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ 1995 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1996 | FLAG2_DMA_BURST, 1997 .pba = 38, 1998 .max_hw_frame_size = DEFAULT_JUMBO, 1999 .get_variants = e1000_get_variants_82571, 2000 .mac_ops = &e82571_mac_ops, 2001 .phy_ops = &e82_phy_ops_igp, 2002 .nvm_ops = &e82571_nvm_ops, 2003 }; 2004 2005 const struct e1000_info e1000_82573_info = { 2006 .mac = e1000_82573, 2007 .flags = FLAG_HAS_HW_VLAN_FILTER 2008 | FLAG_HAS_WOL 2009 | FLAG_APME_IN_CTRL3 2010 | FLAG_HAS_SMART_POWER_DOWN 2011 | FLAG_HAS_AMT 2012 | FLAG_HAS_SWSM_ON_LOAD, 2013 .flags2 = FLAG2_DISABLE_ASPM_L1 2014 | FLAG2_DISABLE_ASPM_L0S, 2015 .pba = 20, 2016 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 2017 .get_variants = e1000_get_variants_82571, 2018 .mac_ops = &e82571_mac_ops, 2019 .phy_ops = &e82_phy_ops_m88, 2020 .nvm_ops = &e82571_nvm_ops, 2021 }; 2022 2023 const struct e1000_info e1000_82574_info = { 2024 .mac = e1000_82574, 2025 .flags = FLAG_HAS_HW_VLAN_FILTER 2026 | FLAG_HAS_MSIX 2027 | FLAG_HAS_JUMBO_FRAMES 2028 | FLAG_HAS_WOL 2029 | FLAG_HAS_HW_TIMESTAMP 2030 | FLAG_APME_IN_CTRL3 2031 | FLAG_HAS_SMART_POWER_DOWN 2032 | FLAG_HAS_AMT 2033 | FLAG_HAS_CTRLEXT_ON_LOAD, 2034 .flags2 = FLAG2_CHECK_PHY_HANG 2035 | FLAG2_DISABLE_ASPM_L0S 2036 | FLAG2_DISABLE_ASPM_L1 2037 | FLAG2_NO_DISABLE_RX 2038 | FLAG2_DMA_BURST, 2039 .pba = 32, 2040 .max_hw_frame_size = DEFAULT_JUMBO, 2041 .get_variants = e1000_get_variants_82571, 2042 .mac_ops = &e82571_mac_ops, 2043 .phy_ops = &e82_phy_ops_bm, 2044 .nvm_ops = &e82571_nvm_ops, 2045 }; 2046 2047 const struct e1000_info e1000_82583_info = { 2048 .mac = e1000_82583, 2049 .flags = FLAG_HAS_HW_VLAN_FILTER 2050 | FLAG_HAS_WOL 2051 | FLAG_HAS_HW_TIMESTAMP 2052 | FLAG_APME_IN_CTRL3 2053 | FLAG_HAS_SMART_POWER_DOWN 2054 | FLAG_HAS_AMT 2055 | FLAG_HAS_JUMBO_FRAMES 2056 | FLAG_HAS_CTRLEXT_ON_LOAD, 2057 .flags2 = FLAG2_DISABLE_ASPM_L0S 2058 | FLAG2_DISABLE_ASPM_L1 2059 | FLAG2_NO_DISABLE_RX, 2060 .pba = 32, 2061 .max_hw_frame_size = DEFAULT_JUMBO, 2062 .get_variants = e1000_get_variants_82571, 2063 .mac_ops = &e82571_mac_ops, 2064 .phy_ops = &e82_phy_ops_bm, 2065 .nvm_ops = &e82571_nvm_ops, 2066 }; 2067