1 // SPDX-License-Identifier: GPL-2.0 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 /* 82571EB Gigabit Ethernet Controller 24 * 82571EB Gigabit Ethernet Controller (Copper) 25 * 82571EB Gigabit Ethernet Controller (Fiber) 26 * 82571EB Dual Port Gigabit Mezzanine Adapter 27 * 82571EB Quad Port Gigabit Mezzanine Adapter 28 * 82571PT Gigabit PT Quad Port Server ExpressModule 29 * 82572EI Gigabit Ethernet Controller (Copper) 30 * 82572EI Gigabit Ethernet Controller (Fiber) 31 * 82572EI Gigabit Ethernet Controller 32 * 82573V Gigabit Ethernet Controller (Copper) 33 * 82573E Gigabit Ethernet Controller (Copper) 34 * 82573L Gigabit Ethernet Controller 35 * 82574L Gigabit Network Connection 36 * 82583V Gigabit Network Connection 37 */ 38 39 #include "e1000.h" 40 41 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 42 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 43 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 44 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 45 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 46 u16 words, u16 *data); 47 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 48 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 49 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 50 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 51 static s32 e1000_led_on_82574(struct e1000_hw *hw); 52 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 53 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 54 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 55 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 56 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 57 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); 58 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); 59 60 /** 61 * e1000_init_phy_params_82571 - Init PHY func ptrs. 62 * @hw: pointer to the HW structure 63 **/ 64 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 65 { 66 struct e1000_phy_info *phy = &hw->phy; 67 s32 ret_val; 68 69 if (hw->phy.media_type != e1000_media_type_copper) { 70 phy->type = e1000_phy_none; 71 return 0; 72 } 73 74 phy->addr = 1; 75 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 76 phy->reset_delay_us = 100; 77 78 phy->ops.power_up = e1000_power_up_phy_copper; 79 phy->ops.power_down = e1000_power_down_phy_copper_82571; 80 81 switch (hw->mac.type) { 82 case e1000_82571: 83 case e1000_82572: 84 phy->type = e1000_phy_igp_2; 85 break; 86 case e1000_82573: 87 phy->type = e1000_phy_m88; 88 break; 89 case e1000_82574: 90 case e1000_82583: 91 phy->type = e1000_phy_bm; 92 phy->ops.acquire = e1000_get_hw_semaphore_82574; 93 phy->ops.release = e1000_put_hw_semaphore_82574; 94 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 95 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 96 break; 97 default: 98 return -E1000_ERR_PHY; 99 } 100 101 /* This can only be done after all function pointers are setup. */ 102 ret_val = e1000_get_phy_id_82571(hw); 103 if (ret_val) { 104 e_dbg("Error getting PHY ID\n"); 105 return ret_val; 106 } 107 108 /* Verify phy id */ 109 switch (hw->mac.type) { 110 case e1000_82571: 111 case e1000_82572: 112 if (phy->id != IGP01E1000_I_PHY_ID) 113 ret_val = -E1000_ERR_PHY; 114 break; 115 case e1000_82573: 116 if (phy->id != M88E1111_I_PHY_ID) 117 ret_val = -E1000_ERR_PHY; 118 break; 119 case e1000_82574: 120 case e1000_82583: 121 if (phy->id != BME1000_E_PHY_ID_R2) 122 ret_val = -E1000_ERR_PHY; 123 break; 124 default: 125 ret_val = -E1000_ERR_PHY; 126 break; 127 } 128 129 if (ret_val) 130 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); 131 132 return ret_val; 133 } 134 135 /** 136 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 137 * @hw: pointer to the HW structure 138 **/ 139 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 140 { 141 struct e1000_nvm_info *nvm = &hw->nvm; 142 u32 eecd = er32(EECD); 143 u16 size; 144 145 nvm->opcode_bits = 8; 146 nvm->delay_usec = 1; 147 switch (nvm->override) { 148 case e1000_nvm_override_spi_large: 149 nvm->page_size = 32; 150 nvm->address_bits = 16; 151 break; 152 case e1000_nvm_override_spi_small: 153 nvm->page_size = 8; 154 nvm->address_bits = 8; 155 break; 156 default: 157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 159 break; 160 } 161 162 switch (hw->mac.type) { 163 case e1000_82573: 164 case e1000_82574: 165 case e1000_82583: 166 if (((eecd >> 15) & 0x3) == 0x3) { 167 nvm->type = e1000_nvm_flash_hw; 168 nvm->word_size = 2048; 169 /* Autonomous Flash update bit must be cleared due 170 * to Flash update issue. 171 */ 172 eecd &= ~E1000_EECD_AUPDEN; 173 ew32(EECD, eecd); 174 break; 175 } 176 /* Fall Through */ 177 default: 178 nvm->type = e1000_nvm_eeprom_spi; 179 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 180 E1000_EECD_SIZE_EX_SHIFT); 181 /* Added to a constant, "size" becomes the left-shift value 182 * for setting word_size. 183 */ 184 size += NVM_WORD_SIZE_BASE_SHIFT; 185 186 /* EEPROM access above 16k is unsupported */ 187 if (size > 14) 188 size = 14; 189 nvm->word_size = BIT(size); 190 break; 191 } 192 193 /* Function Pointers */ 194 switch (hw->mac.type) { 195 case e1000_82574: 196 case e1000_82583: 197 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 198 nvm->ops.release = e1000_put_hw_semaphore_82574; 199 break; 200 default: 201 break; 202 } 203 204 return 0; 205 } 206 207 /** 208 * e1000_init_mac_params_82571 - Init MAC func ptrs. 209 * @hw: pointer to the HW structure 210 **/ 211 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 212 { 213 struct e1000_mac_info *mac = &hw->mac; 214 u32 swsm = 0; 215 u32 swsm2 = 0; 216 bool force_clear_smbi = false; 217 218 /* Set media type and media-dependent function pointers */ 219 switch (hw->adapter->pdev->device) { 220 case E1000_DEV_ID_82571EB_FIBER: 221 case E1000_DEV_ID_82572EI_FIBER: 222 case E1000_DEV_ID_82571EB_QUAD_FIBER: 223 hw->phy.media_type = e1000_media_type_fiber; 224 mac->ops.setup_physical_interface = 225 e1000_setup_fiber_serdes_link_82571; 226 mac->ops.check_for_link = e1000e_check_for_fiber_link; 227 mac->ops.get_link_up_info = 228 e1000e_get_speed_and_duplex_fiber_serdes; 229 break; 230 case E1000_DEV_ID_82571EB_SERDES: 231 case E1000_DEV_ID_82571EB_SERDES_DUAL: 232 case E1000_DEV_ID_82571EB_SERDES_QUAD: 233 case E1000_DEV_ID_82572EI_SERDES: 234 hw->phy.media_type = e1000_media_type_internal_serdes; 235 mac->ops.setup_physical_interface = 236 e1000_setup_fiber_serdes_link_82571; 237 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 238 mac->ops.get_link_up_info = 239 e1000e_get_speed_and_duplex_fiber_serdes; 240 break; 241 default: 242 hw->phy.media_type = e1000_media_type_copper; 243 mac->ops.setup_physical_interface = 244 e1000_setup_copper_link_82571; 245 mac->ops.check_for_link = e1000e_check_for_copper_link; 246 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper; 247 break; 248 } 249 250 /* Set mta register count */ 251 mac->mta_reg_count = 128; 252 /* Set rar entry count */ 253 mac->rar_entry_count = E1000_RAR_ENTRIES; 254 /* Adaptive IFS supported */ 255 mac->adaptive_ifs = true; 256 257 /* MAC-specific function pointers */ 258 switch (hw->mac.type) { 259 case e1000_82573: 260 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 261 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 262 mac->ops.led_on = e1000e_led_on_generic; 263 mac->ops.blink_led = e1000e_blink_led_generic; 264 265 /* FWSM register */ 266 mac->has_fwsm = true; 267 /* ARC supported; valid only if manageability features are 268 * enabled. 269 */ 270 mac->arc_subsystem_valid = !!(er32(FWSM) & 271 E1000_FWSM_MODE_MASK); 272 break; 273 case e1000_82574: 274 case e1000_82583: 275 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 276 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 277 mac->ops.led_on = e1000_led_on_82574; 278 break; 279 default: 280 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 281 mac->ops.led_on = e1000e_led_on_generic; 282 mac->ops.blink_led = e1000e_blink_led_generic; 283 284 /* FWSM register */ 285 mac->has_fwsm = true; 286 break; 287 } 288 289 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 290 * first NVM or PHY access. This should be done for single-port 291 * devices, and for one port only on dual-port devices so that 292 * for those devices we can still use the SMBI lock to synchronize 293 * inter-port accesses to the PHY & NVM. 294 */ 295 switch (hw->mac.type) { 296 case e1000_82571: 297 case e1000_82572: 298 swsm2 = er32(SWSM2); 299 300 if (!(swsm2 & E1000_SWSM2_LOCK)) { 301 /* Only do this for the first interface on this card */ 302 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); 303 force_clear_smbi = true; 304 } else { 305 force_clear_smbi = false; 306 } 307 break; 308 default: 309 force_clear_smbi = true; 310 break; 311 } 312 313 if (force_clear_smbi) { 314 /* Make sure SWSM.SMBI is clear */ 315 swsm = er32(SWSM); 316 if (swsm & E1000_SWSM_SMBI) { 317 /* This bit should not be set on a first interface, and 318 * indicates that the bootagent or EFI code has 319 * improperly left this bit enabled 320 */ 321 e_dbg("Please update your 82571 Bootagent\n"); 322 } 323 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 324 } 325 326 /* Initialize device specific counter of SMBI acquisition timeouts. */ 327 hw->dev_spec.e82571.smb_counter = 0; 328 329 return 0; 330 } 331 332 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) 333 { 334 struct e1000_hw *hw = &adapter->hw; 335 static int global_quad_port_a; /* global port a indication */ 336 struct pci_dev *pdev = adapter->pdev; 337 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; 338 s32 rc; 339 340 rc = e1000_init_mac_params_82571(hw); 341 if (rc) 342 return rc; 343 344 rc = e1000_init_nvm_params_82571(hw); 345 if (rc) 346 return rc; 347 348 rc = e1000_init_phy_params_82571(hw); 349 if (rc) 350 return rc; 351 352 /* tag quad port adapters first, it's used below */ 353 switch (pdev->device) { 354 case E1000_DEV_ID_82571EB_QUAD_COPPER: 355 case E1000_DEV_ID_82571EB_QUAD_FIBER: 356 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 357 case E1000_DEV_ID_82571PT_QUAD_COPPER: 358 adapter->flags |= FLAG_IS_QUAD_PORT; 359 /* mark the first port */ 360 if (global_quad_port_a == 0) 361 adapter->flags |= FLAG_IS_QUAD_PORT_A; 362 /* Reset for multiple quad port adapters */ 363 global_quad_port_a++; 364 if (global_quad_port_a == 4) 365 global_quad_port_a = 0; 366 break; 367 default: 368 break; 369 } 370 371 switch (adapter->hw.mac.type) { 372 case e1000_82571: 373 /* these dual ports don't have WoL on port B at all */ 374 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || 375 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || 376 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && 377 (is_port_b)) 378 adapter->flags &= ~FLAG_HAS_WOL; 379 /* quad ports only support WoL on port A */ 380 if (adapter->flags & FLAG_IS_QUAD_PORT && 381 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) 382 adapter->flags &= ~FLAG_HAS_WOL; 383 /* Does not support WoL on any port */ 384 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) 385 adapter->flags &= ~FLAG_HAS_WOL; 386 break; 387 case e1000_82573: 388 if (pdev->device == E1000_DEV_ID_82573L) { 389 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; 390 adapter->max_hw_frame_size = DEFAULT_JUMBO; 391 } 392 break; 393 default: 394 break; 395 } 396 397 return 0; 398 } 399 400 /** 401 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 402 * @hw: pointer to the HW structure 403 * 404 * Reads the PHY registers and stores the PHY ID and possibly the PHY 405 * revision in the hardware structure. 406 **/ 407 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 408 { 409 struct e1000_phy_info *phy = &hw->phy; 410 s32 ret_val; 411 u16 phy_id = 0; 412 413 switch (hw->mac.type) { 414 case e1000_82571: 415 case e1000_82572: 416 /* The 82571 firmware may still be configuring the PHY. 417 * In this case, we cannot access the PHY until the 418 * configuration is done. So we explicitly set the 419 * PHY ID. 420 */ 421 phy->id = IGP01E1000_I_PHY_ID; 422 break; 423 case e1000_82573: 424 return e1000e_get_phy_id(hw); 425 case e1000_82574: 426 case e1000_82583: 427 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); 428 if (ret_val) 429 return ret_val; 430 431 phy->id = (u32)(phy_id << 16); 432 usleep_range(20, 40); 433 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); 434 if (ret_val) 435 return ret_val; 436 437 phy->id |= (u32)(phy_id); 438 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 439 break; 440 default: 441 return -E1000_ERR_PHY; 442 } 443 444 return 0; 445 } 446 447 /** 448 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 449 * @hw: pointer to the HW structure 450 * 451 * Acquire the HW semaphore to access the PHY or NVM 452 **/ 453 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 454 { 455 u32 swsm; 456 s32 sw_timeout = hw->nvm.word_size + 1; 457 s32 fw_timeout = hw->nvm.word_size + 1; 458 s32 i = 0; 459 460 /* If we have timedout 3 times on trying to acquire 461 * the inter-port SMBI semaphore, there is old code 462 * operating on the other port, and it is not 463 * releasing SMBI. Modify the number of times that 464 * we try for the semaphore to interwork with this 465 * older code. 466 */ 467 if (hw->dev_spec.e82571.smb_counter > 2) 468 sw_timeout = 1; 469 470 /* Get the SW semaphore */ 471 while (i < sw_timeout) { 472 swsm = er32(SWSM); 473 if (!(swsm & E1000_SWSM_SMBI)) 474 break; 475 476 usleep_range(50, 100); 477 i++; 478 } 479 480 if (i == sw_timeout) { 481 e_dbg("Driver can't access device - SMBI bit is set.\n"); 482 hw->dev_spec.e82571.smb_counter++; 483 } 484 /* Get the FW semaphore. */ 485 for (i = 0; i < fw_timeout; i++) { 486 swsm = er32(SWSM); 487 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 488 489 /* Semaphore acquired if bit latched */ 490 if (er32(SWSM) & E1000_SWSM_SWESMBI) 491 break; 492 493 usleep_range(50, 100); 494 } 495 496 if (i == fw_timeout) { 497 /* Release semaphores */ 498 e1000_put_hw_semaphore_82571(hw); 499 e_dbg("Driver can't access the NVM\n"); 500 return -E1000_ERR_NVM; 501 } 502 503 return 0; 504 } 505 506 /** 507 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 508 * @hw: pointer to the HW structure 509 * 510 * Release hardware semaphore used to access the PHY or NVM 511 **/ 512 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 513 { 514 u32 swsm; 515 516 swsm = er32(SWSM); 517 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 518 ew32(SWSM, swsm); 519 } 520 521 /** 522 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 523 * @hw: pointer to the HW structure 524 * 525 * Acquire the HW semaphore during reset. 526 * 527 **/ 528 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 529 { 530 u32 extcnf_ctrl; 531 s32 i = 0; 532 533 extcnf_ctrl = er32(EXTCNF_CTRL); 534 do { 535 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 536 ew32(EXTCNF_CTRL, extcnf_ctrl); 537 extcnf_ctrl = er32(EXTCNF_CTRL); 538 539 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 540 break; 541 542 usleep_range(2000, 4000); 543 i++; 544 } while (i < MDIO_OWNERSHIP_TIMEOUT); 545 546 if (i == MDIO_OWNERSHIP_TIMEOUT) { 547 /* Release semaphores */ 548 e1000_put_hw_semaphore_82573(hw); 549 e_dbg("Driver can't access the PHY\n"); 550 return -E1000_ERR_PHY; 551 } 552 553 return 0; 554 } 555 556 /** 557 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 558 * @hw: pointer to the HW structure 559 * 560 * Release hardware semaphore used during reset. 561 * 562 **/ 563 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 564 { 565 u32 extcnf_ctrl; 566 567 extcnf_ctrl = er32(EXTCNF_CTRL); 568 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 569 ew32(EXTCNF_CTRL, extcnf_ctrl); 570 } 571 572 static DEFINE_MUTEX(swflag_mutex); 573 574 /** 575 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 576 * @hw: pointer to the HW structure 577 * 578 * Acquire the HW semaphore to access the PHY or NVM. 579 * 580 **/ 581 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 582 { 583 s32 ret_val; 584 585 mutex_lock(&swflag_mutex); 586 ret_val = e1000_get_hw_semaphore_82573(hw); 587 if (ret_val) 588 mutex_unlock(&swflag_mutex); 589 return ret_val; 590 } 591 592 /** 593 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 594 * @hw: pointer to the HW structure 595 * 596 * Release hardware semaphore used to access the PHY or NVM 597 * 598 **/ 599 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 600 { 601 e1000_put_hw_semaphore_82573(hw); 602 mutex_unlock(&swflag_mutex); 603 } 604 605 /** 606 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 607 * @hw: pointer to the HW structure 608 * @active: true to enable LPLU, false to disable 609 * 610 * Sets the LPLU D0 state according to the active flag. 611 * LPLU will not be activated unless the 612 * device autonegotiation advertisement meets standards of 613 * either 10 or 10/100 or 10/100/1000 at all duplexes. 614 * This is a function pointer entry point only called by 615 * PHY setup routines. 616 **/ 617 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 618 { 619 u32 data = er32(POEMB); 620 621 if (active) 622 data |= E1000_PHY_CTRL_D0A_LPLU; 623 else 624 data &= ~E1000_PHY_CTRL_D0A_LPLU; 625 626 ew32(POEMB, data); 627 return 0; 628 } 629 630 /** 631 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 632 * @hw: pointer to the HW structure 633 * @active: boolean used to enable/disable lplu 634 * 635 * The low power link up (lplu) state is set to the power management level D3 636 * when active is true, else clear lplu for D3. LPLU 637 * is used during Dx states where the power conservation is most important. 638 * During driver activity, SmartSpeed should be enabled so performance is 639 * maintained. 640 **/ 641 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 642 { 643 u32 data = er32(POEMB); 644 645 if (!active) { 646 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 647 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 648 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 649 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 650 data |= E1000_PHY_CTRL_NOND0A_LPLU; 651 } 652 653 ew32(POEMB, data); 654 return 0; 655 } 656 657 /** 658 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 659 * @hw: pointer to the HW structure 660 * 661 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 662 * Then for non-82573 hardware, set the EEPROM access request bit and wait 663 * for EEPROM access grant bit. If the access grant bit is not set, release 664 * hardware semaphore. 665 **/ 666 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 667 { 668 s32 ret_val; 669 670 ret_val = e1000_get_hw_semaphore_82571(hw); 671 if (ret_val) 672 return ret_val; 673 674 switch (hw->mac.type) { 675 case e1000_82573: 676 break; 677 default: 678 ret_val = e1000e_acquire_nvm(hw); 679 break; 680 } 681 682 if (ret_val) 683 e1000_put_hw_semaphore_82571(hw); 684 685 return ret_val; 686 } 687 688 /** 689 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 690 * @hw: pointer to the HW structure 691 * 692 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 693 **/ 694 static void e1000_release_nvm_82571(struct e1000_hw *hw) 695 { 696 e1000e_release_nvm(hw); 697 e1000_put_hw_semaphore_82571(hw); 698 } 699 700 /** 701 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 702 * @hw: pointer to the HW structure 703 * @offset: offset within the EEPROM to be written to 704 * @words: number of words to write 705 * @data: 16 bit word(s) to be written to the EEPROM 706 * 707 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 708 * 709 * If e1000e_update_nvm_checksum is not called after this function, the 710 * EEPROM will most likely contain an invalid checksum. 711 **/ 712 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 713 u16 *data) 714 { 715 s32 ret_val; 716 717 switch (hw->mac.type) { 718 case e1000_82573: 719 case e1000_82574: 720 case e1000_82583: 721 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 722 break; 723 case e1000_82571: 724 case e1000_82572: 725 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); 726 break; 727 default: 728 ret_val = -E1000_ERR_NVM; 729 break; 730 } 731 732 return ret_val; 733 } 734 735 /** 736 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 737 * @hw: pointer to the HW structure 738 * 739 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 740 * up to the checksum. Then calculates the EEPROM checksum and writes the 741 * value to the EEPROM. 742 **/ 743 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 744 { 745 u32 eecd; 746 s32 ret_val; 747 u16 i; 748 749 ret_val = e1000e_update_nvm_checksum_generic(hw); 750 if (ret_val) 751 return ret_val; 752 753 /* If our nvm is an EEPROM, then we're done 754 * otherwise, commit the checksum to the flash NVM. 755 */ 756 if (hw->nvm.type != e1000_nvm_flash_hw) 757 return 0; 758 759 /* Check for pending operations. */ 760 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 761 usleep_range(1000, 2000); 762 if (!(er32(EECD) & E1000_EECD_FLUPD)) 763 break; 764 } 765 766 if (i == E1000_FLASH_UPDATES) 767 return -E1000_ERR_NVM; 768 769 /* Reset the firmware if using STM opcode. */ 770 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 771 /* The enabling of and the actual reset must be done 772 * in two write cycles. 773 */ 774 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 775 e1e_flush(); 776 ew32(HICR, E1000_HICR_FW_RESET); 777 } 778 779 /* Commit the write to flash */ 780 eecd = er32(EECD) | E1000_EECD_FLUPD; 781 ew32(EECD, eecd); 782 783 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 784 usleep_range(1000, 2000); 785 if (!(er32(EECD) & E1000_EECD_FLUPD)) 786 break; 787 } 788 789 if (i == E1000_FLASH_UPDATES) 790 return -E1000_ERR_NVM; 791 792 return 0; 793 } 794 795 /** 796 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 797 * @hw: pointer to the HW structure 798 * 799 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 800 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 801 **/ 802 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 803 { 804 if (hw->nvm.type == e1000_nvm_flash_hw) 805 e1000_fix_nvm_checksum_82571(hw); 806 807 return e1000e_validate_nvm_checksum_generic(hw); 808 } 809 810 /** 811 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 812 * @hw: pointer to the HW structure 813 * @offset: offset within the EEPROM to be written to 814 * @words: number of words to write 815 * @data: 16 bit word(s) to be written to the EEPROM 816 * 817 * After checking for invalid values, poll the EEPROM to ensure the previous 818 * command has completed before trying to write the next word. After write 819 * poll for completion. 820 * 821 * If e1000e_update_nvm_checksum is not called after this function, the 822 * EEPROM will most likely contain an invalid checksum. 823 **/ 824 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 825 u16 words, u16 *data) 826 { 827 struct e1000_nvm_info *nvm = &hw->nvm; 828 u32 i, eewr = 0; 829 s32 ret_val = 0; 830 831 /* A check for invalid values: offset too large, too many words, 832 * and not enough words. 833 */ 834 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 835 (words == 0)) { 836 e_dbg("nvm parameter(s) out of bounds\n"); 837 return -E1000_ERR_NVM; 838 } 839 840 for (i = 0; i < words; i++) { 841 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) | 842 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | 843 E1000_NVM_RW_REG_START); 844 845 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 846 if (ret_val) 847 break; 848 849 ew32(EEWR, eewr); 850 851 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 852 if (ret_val) 853 break; 854 } 855 856 return ret_val; 857 } 858 859 /** 860 * e1000_get_cfg_done_82571 - Poll for configuration done 861 * @hw: pointer to the HW structure 862 * 863 * Reads the management control register for the config done bit to be set. 864 **/ 865 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 866 { 867 s32 timeout = PHY_CFG_TIMEOUT; 868 869 while (timeout) { 870 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 871 break; 872 usleep_range(1000, 2000); 873 timeout--; 874 } 875 if (!timeout) { 876 e_dbg("MNG configuration cycle has not completed.\n"); 877 return -E1000_ERR_RESET; 878 } 879 880 return 0; 881 } 882 883 /** 884 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 885 * @hw: pointer to the HW structure 886 * @active: true to enable LPLU, false to disable 887 * 888 * Sets the LPLU D0 state according to the active flag. When activating LPLU 889 * this function also disables smart speed and vice versa. LPLU will not be 890 * activated unless the device autonegotiation advertisement meets standards 891 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 892 * pointer entry point only called by PHY setup routines. 893 **/ 894 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 895 { 896 struct e1000_phy_info *phy = &hw->phy; 897 s32 ret_val; 898 u16 data; 899 900 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 901 if (ret_val) 902 return ret_val; 903 904 if (active) { 905 data |= IGP02E1000_PM_D0_LPLU; 906 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 907 if (ret_val) 908 return ret_val; 909 910 /* When LPLU is enabled, we should disable SmartSpeed */ 911 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 912 if (ret_val) 913 return ret_val; 914 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 915 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 916 if (ret_val) 917 return ret_val; 918 } else { 919 data &= ~IGP02E1000_PM_D0_LPLU; 920 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 921 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 922 * during Dx states where the power conservation is most 923 * important. During driver activity we should enable 924 * SmartSpeed, so performance is maintained. 925 */ 926 if (phy->smart_speed == e1000_smart_speed_on) { 927 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 928 &data); 929 if (ret_val) 930 return ret_val; 931 932 data |= IGP01E1000_PSCFR_SMART_SPEED; 933 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 934 data); 935 if (ret_val) 936 return ret_val; 937 } else if (phy->smart_speed == e1000_smart_speed_off) { 938 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 939 &data); 940 if (ret_val) 941 return ret_val; 942 943 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 944 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 945 data); 946 if (ret_val) 947 return ret_val; 948 } 949 } 950 951 return 0; 952 } 953 954 /** 955 * e1000_reset_hw_82571 - Reset hardware 956 * @hw: pointer to the HW structure 957 * 958 * This resets the hardware into a known state. 959 **/ 960 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 961 { 962 u32 ctrl, ctrl_ext, eecd, tctl; 963 s32 ret_val; 964 965 /* Prevent the PCI-E bus from sticking if there is no TLP connection 966 * on the last TLP read/write transaction when MAC is reset. 967 */ 968 ret_val = e1000e_disable_pcie_master(hw); 969 if (ret_val) 970 e_dbg("PCI-E Master disable polling has failed.\n"); 971 972 e_dbg("Masking off all interrupts\n"); 973 ew32(IMC, 0xffffffff); 974 975 ew32(RCTL, 0); 976 tctl = er32(TCTL); 977 tctl &= ~E1000_TCTL_EN; 978 ew32(TCTL, tctl); 979 e1e_flush(); 980 981 usleep_range(10000, 20000); 982 983 /* Must acquire the MDIO ownership before MAC reset. 984 * Ownership defaults to firmware after a reset. 985 */ 986 switch (hw->mac.type) { 987 case e1000_82573: 988 ret_val = e1000_get_hw_semaphore_82573(hw); 989 break; 990 case e1000_82574: 991 case e1000_82583: 992 ret_val = e1000_get_hw_semaphore_82574(hw); 993 break; 994 default: 995 break; 996 } 997 998 ctrl = er32(CTRL); 999 1000 e_dbg("Issuing a global reset to MAC\n"); 1001 ew32(CTRL, ctrl | E1000_CTRL_RST); 1002 1003 /* Must release MDIO ownership and mutex after MAC reset. */ 1004 switch (hw->mac.type) { 1005 case e1000_82573: 1006 /* Release mutex only if the hw semaphore is acquired */ 1007 if (!ret_val) 1008 e1000_put_hw_semaphore_82573(hw); 1009 break; 1010 case e1000_82574: 1011 case e1000_82583: 1012 /* Release mutex only if the hw semaphore is acquired */ 1013 if (!ret_val) 1014 e1000_put_hw_semaphore_82574(hw); 1015 break; 1016 default: 1017 break; 1018 } 1019 1020 if (hw->nvm.type == e1000_nvm_flash_hw) { 1021 usleep_range(10, 20); 1022 ctrl_ext = er32(CTRL_EXT); 1023 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1024 ew32(CTRL_EXT, ctrl_ext); 1025 e1e_flush(); 1026 } 1027 1028 ret_val = e1000e_get_auto_rd_done(hw); 1029 if (ret_val) 1030 /* We don't want to continue accessing MAC registers. */ 1031 return ret_val; 1032 1033 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1034 * Need to wait for Phy configuration completion before accessing 1035 * NVM and Phy. 1036 */ 1037 1038 switch (hw->mac.type) { 1039 case e1000_82571: 1040 case e1000_82572: 1041 /* REQ and GNT bits need to be cleared when using AUTO_RD 1042 * to access the EEPROM. 1043 */ 1044 eecd = er32(EECD); 1045 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1046 ew32(EECD, eecd); 1047 break; 1048 case e1000_82573: 1049 case e1000_82574: 1050 case e1000_82583: 1051 msleep(25); 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 /* Clear any pending interrupt events. */ 1058 ew32(IMC, 0xffffffff); 1059 er32(ICR); 1060 1061 if (hw->mac.type == e1000_82571) { 1062 /* Install any alternate MAC address into RAR0 */ 1063 ret_val = e1000_check_alt_mac_addr_generic(hw); 1064 if (ret_val) 1065 return ret_val; 1066 1067 e1000e_set_laa_state_82571(hw, true); 1068 } 1069 1070 /* Reinitialize the 82571 serdes link state machine */ 1071 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1072 hw->mac.serdes_link_state = e1000_serdes_link_down; 1073 1074 return 0; 1075 } 1076 1077 /** 1078 * e1000_init_hw_82571 - Initialize hardware 1079 * @hw: pointer to the HW structure 1080 * 1081 * This inits the hardware readying it for operation. 1082 **/ 1083 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1084 { 1085 struct e1000_mac_info *mac = &hw->mac; 1086 u32 reg_data; 1087 s32 ret_val; 1088 u16 i, rar_count = mac->rar_entry_count; 1089 1090 e1000_initialize_hw_bits_82571(hw); 1091 1092 /* Initialize identification LED */ 1093 ret_val = mac->ops.id_led_init(hw); 1094 /* An error is not fatal and we should not stop init due to this */ 1095 if (ret_val) 1096 e_dbg("Error initializing identification LED\n"); 1097 1098 /* Disabling VLAN filtering */ 1099 e_dbg("Initializing the IEEE VLAN\n"); 1100 mac->ops.clear_vfta(hw); 1101 1102 /* Setup the receive address. 1103 * If, however, a locally administered address was assigned to the 1104 * 82571, we must reserve a RAR for it to work around an issue where 1105 * resetting one port will reload the MAC on the other port. 1106 */ 1107 if (e1000e_get_laa_state_82571(hw)) 1108 rar_count--; 1109 e1000e_init_rx_addrs(hw, rar_count); 1110 1111 /* Zero out the Multicast HASH table */ 1112 e_dbg("Zeroing the MTA\n"); 1113 for (i = 0; i < mac->mta_reg_count; i++) 1114 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1115 1116 /* Setup link and flow control */ 1117 ret_val = mac->ops.setup_link(hw); 1118 1119 /* Set the transmit descriptor write-back policy */ 1120 reg_data = er32(TXDCTL(0)); 1121 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1122 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 1123 ew32(TXDCTL(0), reg_data); 1124 1125 /* ...for both queues. */ 1126 switch (mac->type) { 1127 case e1000_82573: 1128 e1000e_enable_tx_pkt_filtering(hw); 1129 /* fall through */ 1130 case e1000_82574: 1131 case e1000_82583: 1132 reg_data = er32(GCR); 1133 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1134 ew32(GCR, reg_data); 1135 break; 1136 default: 1137 reg_data = er32(TXDCTL(1)); 1138 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1139 E1000_TXDCTL_FULL_TX_DESC_WB | 1140 E1000_TXDCTL_COUNT_DESC); 1141 ew32(TXDCTL(1), reg_data); 1142 break; 1143 } 1144 1145 /* Clear all of the statistics registers (clear on read). It is 1146 * important that we do this after we have tried to establish link 1147 * because the symbol error count will increment wildly if there 1148 * is no link. 1149 */ 1150 e1000_clear_hw_cntrs_82571(hw); 1151 1152 return ret_val; 1153 } 1154 1155 /** 1156 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1157 * @hw: pointer to the HW structure 1158 * 1159 * Initializes required hardware-dependent bits needed for normal operation. 1160 **/ 1161 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1162 { 1163 u32 reg; 1164 1165 /* Transmit Descriptor Control 0 */ 1166 reg = er32(TXDCTL(0)); 1167 reg |= BIT(22); 1168 ew32(TXDCTL(0), reg); 1169 1170 /* Transmit Descriptor Control 1 */ 1171 reg = er32(TXDCTL(1)); 1172 reg |= BIT(22); 1173 ew32(TXDCTL(1), reg); 1174 1175 /* Transmit Arbitration Control 0 */ 1176 reg = er32(TARC(0)); 1177 reg &= ~(0xF << 27); /* 30:27 */ 1178 switch (hw->mac.type) { 1179 case e1000_82571: 1180 case e1000_82572: 1181 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26); 1182 break; 1183 case e1000_82574: 1184 case e1000_82583: 1185 reg |= BIT(26); 1186 break; 1187 default: 1188 break; 1189 } 1190 ew32(TARC(0), reg); 1191 1192 /* Transmit Arbitration Control 1 */ 1193 reg = er32(TARC(1)); 1194 switch (hw->mac.type) { 1195 case e1000_82571: 1196 case e1000_82572: 1197 reg &= ~(BIT(29) | BIT(30)); 1198 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26); 1199 if (er32(TCTL) & E1000_TCTL_MULR) 1200 reg &= ~BIT(28); 1201 else 1202 reg |= BIT(28); 1203 ew32(TARC(1), reg); 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 /* Device Control */ 1210 switch (hw->mac.type) { 1211 case e1000_82573: 1212 case e1000_82574: 1213 case e1000_82583: 1214 reg = er32(CTRL); 1215 reg &= ~BIT(29); 1216 ew32(CTRL, reg); 1217 break; 1218 default: 1219 break; 1220 } 1221 1222 /* Extended Device Control */ 1223 switch (hw->mac.type) { 1224 case e1000_82573: 1225 case e1000_82574: 1226 case e1000_82583: 1227 reg = er32(CTRL_EXT); 1228 reg &= ~BIT(23); 1229 reg |= BIT(22); 1230 ew32(CTRL_EXT, reg); 1231 break; 1232 default: 1233 break; 1234 } 1235 1236 if (hw->mac.type == e1000_82571) { 1237 reg = er32(PBA_ECC); 1238 reg |= E1000_PBA_ECC_CORR_EN; 1239 ew32(PBA_ECC, reg); 1240 } 1241 1242 /* Workaround for hardware errata. 1243 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1244 */ 1245 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 1246 reg = er32(CTRL_EXT); 1247 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1248 ew32(CTRL_EXT, reg); 1249 } 1250 1251 /* Disable IPv6 extension header parsing because some malformed 1252 * IPv6 headers can hang the Rx. 1253 */ 1254 if (hw->mac.type <= e1000_82573) { 1255 reg = er32(RFCTL); 1256 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1257 ew32(RFCTL, reg); 1258 } 1259 1260 /* PCI-Ex Control Registers */ 1261 switch (hw->mac.type) { 1262 case e1000_82574: 1263 case e1000_82583: 1264 reg = er32(GCR); 1265 reg |= BIT(22); 1266 ew32(GCR, reg); 1267 1268 /* Workaround for hardware errata. 1269 * apply workaround for hardware errata documented in errata 1270 * docs Fixes issue where some error prone or unreliable PCIe 1271 * completions are occurring, particularly with ASPM enabled. 1272 * Without fix, issue can cause Tx timeouts. 1273 */ 1274 reg = er32(GCR2); 1275 reg |= 1; 1276 ew32(GCR2, reg); 1277 break; 1278 default: 1279 break; 1280 } 1281 } 1282 1283 /** 1284 * e1000_clear_vfta_82571 - Clear VLAN filter table 1285 * @hw: pointer to the HW structure 1286 * 1287 * Clears the register array which contains the VLAN filter table by 1288 * setting all the values to 0. 1289 **/ 1290 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1291 { 1292 u32 offset; 1293 u32 vfta_value = 0; 1294 u32 vfta_offset = 0; 1295 u32 vfta_bit_in_reg = 0; 1296 1297 switch (hw->mac.type) { 1298 case e1000_82573: 1299 case e1000_82574: 1300 case e1000_82583: 1301 if (hw->mng_cookie.vlan_id != 0) { 1302 /* The VFTA is a 4096b bit-field, each identifying 1303 * a single VLAN ID. The following operations 1304 * determine which 32b entry (i.e. offset) into the 1305 * array we want to set the VLAN ID (i.e. bit) of 1306 * the manageability unit. 1307 */ 1308 vfta_offset = (hw->mng_cookie.vlan_id >> 1309 E1000_VFTA_ENTRY_SHIFT) & 1310 E1000_VFTA_ENTRY_MASK; 1311 vfta_bit_in_reg = 1312 BIT(hw->mng_cookie.vlan_id & 1313 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1314 } 1315 break; 1316 default: 1317 break; 1318 } 1319 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1320 /* If the offset we want to clear is the same offset of the 1321 * manageability VLAN ID, then clear all bits except that of 1322 * the manageability unit. 1323 */ 1324 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1325 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1326 e1e_flush(); 1327 } 1328 } 1329 1330 /** 1331 * e1000_check_mng_mode_82574 - Check manageability is enabled 1332 * @hw: pointer to the HW structure 1333 * 1334 * Reads the NVM Initialization Control Word 2 and returns true 1335 * (>0) if any manageability is enabled, else false (0). 1336 **/ 1337 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1338 { 1339 u16 data; 1340 1341 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1342 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1343 } 1344 1345 /** 1346 * e1000_led_on_82574 - Turn LED on 1347 * @hw: pointer to the HW structure 1348 * 1349 * Turn LED on. 1350 **/ 1351 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1352 { 1353 u32 ctrl; 1354 u32 i; 1355 1356 ctrl = hw->mac.ledctl_mode2; 1357 if (!(E1000_STATUS_LU & er32(STATUS))) { 1358 /* If no link, then turn LED on by setting the invert bit 1359 * for each LED that's "on" (0x0E) in ledctl_mode2. 1360 */ 1361 for (i = 0; i < 4; i++) 1362 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1363 E1000_LEDCTL_MODE_LED_ON) 1364 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1365 } 1366 ew32(LEDCTL, ctrl); 1367 1368 return 0; 1369 } 1370 1371 /** 1372 * e1000_check_phy_82574 - check 82574 phy hung state 1373 * @hw: pointer to the HW structure 1374 * 1375 * Returns whether phy is hung or not 1376 **/ 1377 bool e1000_check_phy_82574(struct e1000_hw *hw) 1378 { 1379 u16 status_1kbt = 0; 1380 u16 receive_errors = 0; 1381 s32 ret_val; 1382 1383 /* Read PHY Receive Error counter first, if its is max - all F's then 1384 * read the Base1000T status register If both are max then PHY is hung. 1385 */ 1386 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); 1387 if (ret_val) 1388 return false; 1389 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1390 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); 1391 if (ret_val) 1392 return false; 1393 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1394 E1000_IDLE_ERROR_COUNT_MASK) 1395 return true; 1396 } 1397 1398 return false; 1399 } 1400 1401 /** 1402 * e1000_setup_link_82571 - Setup flow control and link settings 1403 * @hw: pointer to the HW structure 1404 * 1405 * Determines which flow control settings to use, then configures flow 1406 * control. Calls the appropriate media-specific link configuration 1407 * function. Assuming the adapter has a valid link partner, a valid link 1408 * should be established. Assumes the hardware has previously been reset 1409 * and the transmitter and receiver are not enabled. 1410 **/ 1411 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1412 { 1413 /* 82573 does not have a word in the NVM to determine 1414 * the default flow control setting, so we explicitly 1415 * set it to full. 1416 */ 1417 switch (hw->mac.type) { 1418 case e1000_82573: 1419 case e1000_82574: 1420 case e1000_82583: 1421 if (hw->fc.requested_mode == e1000_fc_default) 1422 hw->fc.requested_mode = e1000_fc_full; 1423 break; 1424 default: 1425 break; 1426 } 1427 1428 return e1000e_setup_link_generic(hw); 1429 } 1430 1431 /** 1432 * e1000_setup_copper_link_82571 - Configure copper link settings 1433 * @hw: pointer to the HW structure 1434 * 1435 * Configures the link for auto-neg or forced speed and duplex. Then we check 1436 * for link, once link is established calls to configure collision distance 1437 * and flow control are called. 1438 **/ 1439 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1440 { 1441 u32 ctrl; 1442 s32 ret_val; 1443 1444 ctrl = er32(CTRL); 1445 ctrl |= E1000_CTRL_SLU; 1446 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1447 ew32(CTRL, ctrl); 1448 1449 switch (hw->phy.type) { 1450 case e1000_phy_m88: 1451 case e1000_phy_bm: 1452 ret_val = e1000e_copper_link_setup_m88(hw); 1453 break; 1454 case e1000_phy_igp_2: 1455 ret_val = e1000e_copper_link_setup_igp(hw); 1456 break; 1457 default: 1458 return -E1000_ERR_PHY; 1459 } 1460 1461 if (ret_val) 1462 return ret_val; 1463 1464 return e1000e_setup_copper_link(hw); 1465 } 1466 1467 /** 1468 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1469 * @hw: pointer to the HW structure 1470 * 1471 * Configures collision distance and flow control for fiber and serdes links. 1472 * Upon successful setup, poll for link. 1473 **/ 1474 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1475 { 1476 switch (hw->mac.type) { 1477 case e1000_82571: 1478 case e1000_82572: 1479 /* If SerDes loopback mode is entered, there is no form 1480 * of reset to take the adapter out of that mode. So we 1481 * have to explicitly take the adapter out of loopback 1482 * mode. This prevents drivers from twiddling their thumbs 1483 * if another tool failed to take it out of loopback mode. 1484 */ 1485 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 return e1000e_setup_fiber_serdes_link(hw); 1492 } 1493 1494 /** 1495 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1496 * @hw: pointer to the HW structure 1497 * 1498 * Reports the link state as up or down. 1499 * 1500 * If autonegotiation is supported by the link partner, the link state is 1501 * determined by the result of autonegotiation. This is the most likely case. 1502 * If autonegotiation is not supported by the link partner, and the link 1503 * has a valid signal, force the link up. 1504 * 1505 * The link state is represented internally here by 4 states: 1506 * 1507 * 1) down 1508 * 2) autoneg_progress 1509 * 3) autoneg_complete (the link successfully autonegotiated) 1510 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1511 * 1512 **/ 1513 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1514 { 1515 struct e1000_mac_info *mac = &hw->mac; 1516 u32 rxcw; 1517 u32 ctrl; 1518 u32 status; 1519 u32 txcw; 1520 u32 i; 1521 s32 ret_val = 0; 1522 1523 ctrl = er32(CTRL); 1524 status = er32(STATUS); 1525 er32(RXCW); 1526 /* SYNCH bit and IV bit are sticky */ 1527 usleep_range(10, 20); 1528 rxcw = er32(RXCW); 1529 1530 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1531 /* Receiver is synchronized with no invalid bits. */ 1532 switch (mac->serdes_link_state) { 1533 case e1000_serdes_link_autoneg_complete: 1534 if (!(status & E1000_STATUS_LU)) { 1535 /* We have lost link, retry autoneg before 1536 * reporting link failure 1537 */ 1538 mac->serdes_link_state = 1539 e1000_serdes_link_autoneg_progress; 1540 mac->serdes_has_link = false; 1541 e_dbg("AN_UP -> AN_PROG\n"); 1542 } else { 1543 mac->serdes_has_link = true; 1544 } 1545 break; 1546 1547 case e1000_serdes_link_forced_up: 1548 /* If we are receiving /C/ ordered sets, re-enable 1549 * auto-negotiation in the TXCW register and disable 1550 * forced link in the Device Control register in an 1551 * attempt to auto-negotiate with our link partner. 1552 */ 1553 if (rxcw & E1000_RXCW_C) { 1554 /* Enable autoneg, and unforce link up */ 1555 ew32(TXCW, mac->txcw); 1556 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1557 mac->serdes_link_state = 1558 e1000_serdes_link_autoneg_progress; 1559 mac->serdes_has_link = false; 1560 e_dbg("FORCED_UP -> AN_PROG\n"); 1561 } else { 1562 mac->serdes_has_link = true; 1563 } 1564 break; 1565 1566 case e1000_serdes_link_autoneg_progress: 1567 if (rxcw & E1000_RXCW_C) { 1568 /* We received /C/ ordered sets, meaning the 1569 * link partner has autonegotiated, and we can 1570 * trust the Link Up (LU) status bit. 1571 */ 1572 if (status & E1000_STATUS_LU) { 1573 mac->serdes_link_state = 1574 e1000_serdes_link_autoneg_complete; 1575 e_dbg("AN_PROG -> AN_UP\n"); 1576 mac->serdes_has_link = true; 1577 } else { 1578 /* Autoneg completed, but failed. */ 1579 mac->serdes_link_state = 1580 e1000_serdes_link_down; 1581 e_dbg("AN_PROG -> DOWN\n"); 1582 } 1583 } else { 1584 /* The link partner did not autoneg. 1585 * Force link up and full duplex, and change 1586 * state to forced. 1587 */ 1588 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1589 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1590 ew32(CTRL, ctrl); 1591 1592 /* Configure Flow Control after link up. */ 1593 ret_val = e1000e_config_fc_after_link_up(hw); 1594 if (ret_val) { 1595 e_dbg("Error config flow control\n"); 1596 break; 1597 } 1598 mac->serdes_link_state = 1599 e1000_serdes_link_forced_up; 1600 mac->serdes_has_link = true; 1601 e_dbg("AN_PROG -> FORCED_UP\n"); 1602 } 1603 break; 1604 1605 case e1000_serdes_link_down: 1606 default: 1607 /* The link was down but the receiver has now gained 1608 * valid sync, so lets see if we can bring the link 1609 * up. 1610 */ 1611 ew32(TXCW, mac->txcw); 1612 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1613 mac->serdes_link_state = 1614 e1000_serdes_link_autoneg_progress; 1615 mac->serdes_has_link = false; 1616 e_dbg("DOWN -> AN_PROG\n"); 1617 break; 1618 } 1619 } else { 1620 if (!(rxcw & E1000_RXCW_SYNCH)) { 1621 mac->serdes_has_link = false; 1622 mac->serdes_link_state = e1000_serdes_link_down; 1623 e_dbg("ANYSTATE -> DOWN\n"); 1624 } else { 1625 /* Check several times, if SYNCH bit and CONFIG 1626 * bit both are consistently 1 then simply ignore 1627 * the IV bit and restart Autoneg 1628 */ 1629 for (i = 0; i < AN_RETRY_COUNT; i++) { 1630 usleep_range(10, 20); 1631 rxcw = er32(RXCW); 1632 if ((rxcw & E1000_RXCW_SYNCH) && 1633 (rxcw & E1000_RXCW_C)) 1634 continue; 1635 1636 if (rxcw & E1000_RXCW_IV) { 1637 mac->serdes_has_link = false; 1638 mac->serdes_link_state = 1639 e1000_serdes_link_down; 1640 e_dbg("ANYSTATE -> DOWN\n"); 1641 break; 1642 } 1643 } 1644 1645 if (i == AN_RETRY_COUNT) { 1646 txcw = er32(TXCW); 1647 txcw |= E1000_TXCW_ANE; 1648 ew32(TXCW, txcw); 1649 mac->serdes_link_state = 1650 e1000_serdes_link_autoneg_progress; 1651 mac->serdes_has_link = false; 1652 e_dbg("ANYSTATE -> AN_PROG\n"); 1653 } 1654 } 1655 } 1656 1657 return ret_val; 1658 } 1659 1660 /** 1661 * e1000_valid_led_default_82571 - Verify a valid default LED config 1662 * @hw: pointer to the HW structure 1663 * @data: pointer to the NVM (EEPROM) 1664 * 1665 * Read the EEPROM for the current default LED configuration. If the 1666 * LED configuration is not valid, set to a valid LED configuration. 1667 **/ 1668 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1669 { 1670 s32 ret_val; 1671 1672 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1673 if (ret_val) { 1674 e_dbg("NVM Read Error\n"); 1675 return ret_val; 1676 } 1677 1678 switch (hw->mac.type) { 1679 case e1000_82573: 1680 case e1000_82574: 1681 case e1000_82583: 1682 if (*data == ID_LED_RESERVED_F746) 1683 *data = ID_LED_DEFAULT_82573; 1684 break; 1685 default: 1686 if (*data == ID_LED_RESERVED_0000 || 1687 *data == ID_LED_RESERVED_FFFF) 1688 *data = ID_LED_DEFAULT; 1689 break; 1690 } 1691 1692 return 0; 1693 } 1694 1695 /** 1696 * e1000e_get_laa_state_82571 - Get locally administered address state 1697 * @hw: pointer to the HW structure 1698 * 1699 * Retrieve and return the current locally administered address state. 1700 **/ 1701 bool e1000e_get_laa_state_82571(struct e1000_hw *hw) 1702 { 1703 if (hw->mac.type != e1000_82571) 1704 return false; 1705 1706 return hw->dev_spec.e82571.laa_is_present; 1707 } 1708 1709 /** 1710 * e1000e_set_laa_state_82571 - Set locally administered address state 1711 * @hw: pointer to the HW structure 1712 * @state: enable/disable locally administered address 1713 * 1714 * Enable/Disable the current locally administered address state. 1715 **/ 1716 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 1717 { 1718 if (hw->mac.type != e1000_82571) 1719 return; 1720 1721 hw->dev_spec.e82571.laa_is_present = state; 1722 1723 /* If workaround is activated... */ 1724 if (state) 1725 /* Hold a copy of the LAA in RAR[14] This is done so that 1726 * between the time RAR[0] gets clobbered and the time it 1727 * gets fixed, the actual LAA is in one of the RARs and no 1728 * incoming packets directed to this port are dropped. 1729 * Eventually the LAA will be in RAR[0] and RAR[14]. 1730 */ 1731 hw->mac.ops.rar_set(hw, hw->mac.addr, 1732 hw->mac.rar_entry_count - 1); 1733 } 1734 1735 /** 1736 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1737 * @hw: pointer to the HW structure 1738 * 1739 * Verifies that the EEPROM has completed the update. After updating the 1740 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1741 * the checksum fix is not implemented, we need to set the bit and update 1742 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1743 * we need to return bad checksum. 1744 **/ 1745 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1746 { 1747 struct e1000_nvm_info *nvm = &hw->nvm; 1748 s32 ret_val; 1749 u16 data; 1750 1751 if (nvm->type != e1000_nvm_flash_hw) 1752 return 0; 1753 1754 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1755 * 10h-12h. Checksum may need to be fixed. 1756 */ 1757 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1758 if (ret_val) 1759 return ret_val; 1760 1761 if (!(data & 0x10)) { 1762 /* Read 0x23 and check bit 15. This bit is a 1 1763 * when the checksum has already been fixed. If 1764 * the checksum is still wrong and this bit is a 1765 * 1, we need to return bad checksum. Otherwise, 1766 * we need to set this bit to a 1 and update the 1767 * checksum. 1768 */ 1769 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1770 if (ret_val) 1771 return ret_val; 1772 1773 if (!(data & 0x8000)) { 1774 data |= 0x8000; 1775 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1776 if (ret_val) 1777 return ret_val; 1778 ret_val = e1000e_update_nvm_checksum(hw); 1779 if (ret_val) 1780 return ret_val; 1781 } 1782 } 1783 1784 return 0; 1785 } 1786 1787 /** 1788 * e1000_read_mac_addr_82571 - Read device MAC address 1789 * @hw: pointer to the HW structure 1790 **/ 1791 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1792 { 1793 if (hw->mac.type == e1000_82571) { 1794 s32 ret_val; 1795 1796 /* If there's an alternate MAC address place it in RAR0 1797 * so that it will override the Si installed default perm 1798 * address. 1799 */ 1800 ret_val = e1000_check_alt_mac_addr_generic(hw); 1801 if (ret_val) 1802 return ret_val; 1803 } 1804 1805 return e1000_read_mac_addr_generic(hw); 1806 } 1807 1808 /** 1809 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1810 * @hw: pointer to the HW structure 1811 * 1812 * In the case of a PHY power down to save power, or to turn off link during a 1813 * driver unload, or wake on lan is not enabled, remove the link. 1814 **/ 1815 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1816 { 1817 struct e1000_phy_info *phy = &hw->phy; 1818 struct e1000_mac_info *mac = &hw->mac; 1819 1820 if (!phy->ops.check_reset_block) 1821 return; 1822 1823 /* If the management interface is not enabled, then power down */ 1824 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1825 e1000_power_down_phy_copper(hw); 1826 } 1827 1828 /** 1829 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1830 * @hw: pointer to the HW structure 1831 * 1832 * Clears the hardware counters by reading the counter registers. 1833 **/ 1834 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1835 { 1836 e1000e_clear_hw_cntrs_base(hw); 1837 1838 er32(PRC64); 1839 er32(PRC127); 1840 er32(PRC255); 1841 er32(PRC511); 1842 er32(PRC1023); 1843 er32(PRC1522); 1844 er32(PTC64); 1845 er32(PTC127); 1846 er32(PTC255); 1847 er32(PTC511); 1848 er32(PTC1023); 1849 er32(PTC1522); 1850 1851 er32(ALGNERRC); 1852 er32(RXERRC); 1853 er32(TNCRS); 1854 er32(CEXTERR); 1855 er32(TSCTC); 1856 er32(TSCTFC); 1857 1858 er32(MGTPRC); 1859 er32(MGTPDC); 1860 er32(MGTPTC); 1861 1862 er32(IAC); 1863 er32(ICRXOC); 1864 1865 er32(ICRXPTC); 1866 er32(ICRXATC); 1867 er32(ICTXPTC); 1868 er32(ICTXATC); 1869 er32(ICTXQEC); 1870 er32(ICTXQMTC); 1871 er32(ICRXDMTC); 1872 } 1873 1874 static const struct e1000_mac_operations e82571_mac_ops = { 1875 /* .check_mng_mode: mac type dependent */ 1876 /* .check_for_link: media type dependent */ 1877 .id_led_init = e1000e_id_led_init_generic, 1878 .cleanup_led = e1000e_cleanup_led_generic, 1879 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, 1880 .get_bus_info = e1000e_get_bus_info_pcie, 1881 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1882 /* .get_link_up_info: media type dependent */ 1883 /* .led_on: mac type dependent */ 1884 .led_off = e1000e_led_off_generic, 1885 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1886 .write_vfta = e1000_write_vfta_generic, 1887 .clear_vfta = e1000_clear_vfta_82571, 1888 .reset_hw = e1000_reset_hw_82571, 1889 .init_hw = e1000_init_hw_82571, 1890 .setup_link = e1000_setup_link_82571, 1891 /* .setup_physical_interface: media type dependent */ 1892 .setup_led = e1000e_setup_led_generic, 1893 .config_collision_dist = e1000e_config_collision_dist_generic, 1894 .read_mac_addr = e1000_read_mac_addr_82571, 1895 .rar_set = e1000e_rar_set_generic, 1896 .rar_get_count = e1000e_rar_get_count_generic, 1897 }; 1898 1899 static const struct e1000_phy_operations e82_phy_ops_igp = { 1900 .acquire = e1000_get_hw_semaphore_82571, 1901 .check_polarity = e1000_check_polarity_igp, 1902 .check_reset_block = e1000e_check_reset_block_generic, 1903 .commit = NULL, 1904 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, 1905 .get_cfg_done = e1000_get_cfg_done_82571, 1906 .get_cable_length = e1000e_get_cable_length_igp_2, 1907 .get_info = e1000e_get_phy_info_igp, 1908 .read_reg = e1000e_read_phy_reg_igp, 1909 .release = e1000_put_hw_semaphore_82571, 1910 .reset = e1000e_phy_hw_reset_generic, 1911 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1912 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1913 .write_reg = e1000e_write_phy_reg_igp, 1914 .cfg_on_link_up = NULL, 1915 }; 1916 1917 static const struct e1000_phy_operations e82_phy_ops_m88 = { 1918 .acquire = e1000_get_hw_semaphore_82571, 1919 .check_polarity = e1000_check_polarity_m88, 1920 .check_reset_block = e1000e_check_reset_block_generic, 1921 .commit = e1000e_phy_sw_reset, 1922 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1923 .get_cfg_done = e1000e_get_cfg_done_generic, 1924 .get_cable_length = e1000e_get_cable_length_m88, 1925 .get_info = e1000e_get_phy_info_m88, 1926 .read_reg = e1000e_read_phy_reg_m88, 1927 .release = e1000_put_hw_semaphore_82571, 1928 .reset = e1000e_phy_hw_reset_generic, 1929 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1930 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1931 .write_reg = e1000e_write_phy_reg_m88, 1932 .cfg_on_link_up = NULL, 1933 }; 1934 1935 static const struct e1000_phy_operations e82_phy_ops_bm = { 1936 .acquire = e1000_get_hw_semaphore_82571, 1937 .check_polarity = e1000_check_polarity_m88, 1938 .check_reset_block = e1000e_check_reset_block_generic, 1939 .commit = e1000e_phy_sw_reset, 1940 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1941 .get_cfg_done = e1000e_get_cfg_done_generic, 1942 .get_cable_length = e1000e_get_cable_length_m88, 1943 .get_info = e1000e_get_phy_info_m88, 1944 .read_reg = e1000e_read_phy_reg_bm2, 1945 .release = e1000_put_hw_semaphore_82571, 1946 .reset = e1000e_phy_hw_reset_generic, 1947 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1948 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1949 .write_reg = e1000e_write_phy_reg_bm2, 1950 .cfg_on_link_up = NULL, 1951 }; 1952 1953 static const struct e1000_nvm_operations e82571_nvm_ops = { 1954 .acquire = e1000_acquire_nvm_82571, 1955 .read = e1000e_read_nvm_eerd, 1956 .release = e1000_release_nvm_82571, 1957 .reload = e1000e_reload_nvm_generic, 1958 .update = e1000_update_nvm_checksum_82571, 1959 .valid_led_default = e1000_valid_led_default_82571, 1960 .validate = e1000_validate_nvm_checksum_82571, 1961 .write = e1000_write_nvm_82571, 1962 }; 1963 1964 const struct e1000_info e1000_82571_info = { 1965 .mac = e1000_82571, 1966 .flags = FLAG_HAS_HW_VLAN_FILTER 1967 | FLAG_HAS_JUMBO_FRAMES 1968 | FLAG_HAS_WOL 1969 | FLAG_APME_IN_CTRL3 1970 | FLAG_HAS_CTRLEXT_ON_LOAD 1971 | FLAG_HAS_SMART_POWER_DOWN 1972 | FLAG_RESET_OVERWRITES_LAA /* errata */ 1973 | FLAG_TARC_SPEED_MODE_BIT /* errata */ 1974 | FLAG_APME_CHECK_PORT_B, 1975 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1976 | FLAG2_DMA_BURST, 1977 .pba = 38, 1978 .max_hw_frame_size = DEFAULT_JUMBO, 1979 .get_variants = e1000_get_variants_82571, 1980 .mac_ops = &e82571_mac_ops, 1981 .phy_ops = &e82_phy_ops_igp, 1982 .nvm_ops = &e82571_nvm_ops, 1983 }; 1984 1985 const struct e1000_info e1000_82572_info = { 1986 .mac = e1000_82572, 1987 .flags = FLAG_HAS_HW_VLAN_FILTER 1988 | FLAG_HAS_JUMBO_FRAMES 1989 | FLAG_HAS_WOL 1990 | FLAG_APME_IN_CTRL3 1991 | FLAG_HAS_CTRLEXT_ON_LOAD 1992 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ 1993 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ 1994 | FLAG2_DMA_BURST, 1995 .pba = 38, 1996 .max_hw_frame_size = DEFAULT_JUMBO, 1997 .get_variants = e1000_get_variants_82571, 1998 .mac_ops = &e82571_mac_ops, 1999 .phy_ops = &e82_phy_ops_igp, 2000 .nvm_ops = &e82571_nvm_ops, 2001 }; 2002 2003 const struct e1000_info e1000_82573_info = { 2004 .mac = e1000_82573, 2005 .flags = FLAG_HAS_HW_VLAN_FILTER 2006 | FLAG_HAS_WOL 2007 | FLAG_APME_IN_CTRL3 2008 | FLAG_HAS_SMART_POWER_DOWN 2009 | FLAG_HAS_AMT 2010 | FLAG_HAS_SWSM_ON_LOAD, 2011 .flags2 = FLAG2_DISABLE_ASPM_L1 2012 | FLAG2_DISABLE_ASPM_L0S, 2013 .pba = 20, 2014 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 2015 .get_variants = e1000_get_variants_82571, 2016 .mac_ops = &e82571_mac_ops, 2017 .phy_ops = &e82_phy_ops_m88, 2018 .nvm_ops = &e82571_nvm_ops, 2019 }; 2020 2021 const struct e1000_info e1000_82574_info = { 2022 .mac = e1000_82574, 2023 .flags = FLAG_HAS_HW_VLAN_FILTER 2024 | FLAG_HAS_MSIX 2025 | FLAG_HAS_JUMBO_FRAMES 2026 | FLAG_HAS_WOL 2027 | FLAG_HAS_HW_TIMESTAMP 2028 | FLAG_APME_IN_CTRL3 2029 | FLAG_HAS_SMART_POWER_DOWN 2030 | FLAG_HAS_AMT 2031 | FLAG_HAS_CTRLEXT_ON_LOAD, 2032 .flags2 = FLAG2_CHECK_PHY_HANG 2033 | FLAG2_DISABLE_ASPM_L0S 2034 | FLAG2_DISABLE_ASPM_L1 2035 | FLAG2_NO_DISABLE_RX 2036 | FLAG2_DMA_BURST 2037 | FLAG2_CHECK_SYSTIM_OVERFLOW, 2038 .pba = 32, 2039 .max_hw_frame_size = DEFAULT_JUMBO, 2040 .get_variants = e1000_get_variants_82571, 2041 .mac_ops = &e82571_mac_ops, 2042 .phy_ops = &e82_phy_ops_bm, 2043 .nvm_ops = &e82571_nvm_ops, 2044 }; 2045 2046 const struct e1000_info e1000_82583_info = { 2047 .mac = e1000_82583, 2048 .flags = FLAG_HAS_HW_VLAN_FILTER 2049 | FLAG_HAS_WOL 2050 | FLAG_HAS_HW_TIMESTAMP 2051 | FLAG_APME_IN_CTRL3 2052 | FLAG_HAS_SMART_POWER_DOWN 2053 | FLAG_HAS_AMT 2054 | FLAG_HAS_JUMBO_FRAMES 2055 | FLAG_HAS_CTRLEXT_ON_LOAD, 2056 .flags2 = FLAG2_DISABLE_ASPM_L0S 2057 | FLAG2_DISABLE_ASPM_L1 2058 | FLAG2_NO_DISABLE_RX 2059 | FLAG2_CHECK_SYSTIM_OVERFLOW, 2060 .pba = 32, 2061 .max_hw_frame_size = DEFAULT_JUMBO, 2062 .get_variants = e1000_get_variants_82571, 2063 .mac_ops = &e82571_mac_ops, 2064 .phy_ops = &e82_phy_ops_bm, 2065 .nvm_ops = &e82571_nvm_ops, 2066 }; 2067