1 // SPDX-License-Identifier: GPL-2.0 2 /* Intel PRO/1000 Linux driver 3 * Copyright(c) 1999 - 2015 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in 15 * the file called "COPYING". 16 * 17 * Contact Information: 18 * Linux NICS <linux.nics@intel.com> 19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 21 */ 22 23 /* 80003ES2LAN Gigabit Ethernet Controller (Copper) 24 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 25 */ 26 27 #include "e1000.h" 28 29 /* A table for the GG82563 cable length where the range is defined 30 * with a lower bound at "index" and the upper bound at 31 * "index + 5". 32 */ 33 static const u16 e1000_gg82563_cable_length_table[] = { 34 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF 35 }; 36 37 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 38 ARRAY_SIZE(e1000_gg82563_cable_length_table) 39 40 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 41 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 42 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 43 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 44 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 45 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 46 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 47 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 48 u16 *data); 49 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 50 u16 data); 51 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 52 53 /** 54 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 55 * @hw: pointer to the HW structure 56 **/ 57 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 58 { 59 struct e1000_phy_info *phy = &hw->phy; 60 s32 ret_val; 61 62 if (hw->phy.media_type != e1000_media_type_copper) { 63 phy->type = e1000_phy_none; 64 return 0; 65 } else { 66 phy->ops.power_up = e1000_power_up_phy_copper; 67 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 68 } 69 70 phy->addr = 1; 71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 72 phy->reset_delay_us = 100; 73 phy->type = e1000_phy_gg82563; 74 75 /* This can only be done after all function pointers are setup. */ 76 ret_val = e1000e_get_phy_id(hw); 77 78 /* Verify phy id */ 79 if (phy->id != GG82563_E_PHY_ID) 80 return -E1000_ERR_PHY; 81 82 return ret_val; 83 } 84 85 /** 86 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 87 * @hw: pointer to the HW structure 88 **/ 89 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 90 { 91 struct e1000_nvm_info *nvm = &hw->nvm; 92 u32 eecd = er32(EECD); 93 u16 size; 94 95 nvm->opcode_bits = 8; 96 nvm->delay_usec = 1; 97 switch (nvm->override) { 98 case e1000_nvm_override_spi_large: 99 nvm->page_size = 32; 100 nvm->address_bits = 16; 101 break; 102 case e1000_nvm_override_spi_small: 103 nvm->page_size = 8; 104 nvm->address_bits = 8; 105 break; 106 default: 107 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 108 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 109 break; 110 } 111 112 nvm->type = e1000_nvm_eeprom_spi; 113 114 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 115 E1000_EECD_SIZE_EX_SHIFT); 116 117 /* Added to a constant, "size" becomes the left-shift value 118 * for setting word_size. 119 */ 120 size += NVM_WORD_SIZE_BASE_SHIFT; 121 122 /* EEPROM access above 16k is unsupported */ 123 if (size > 14) 124 size = 14; 125 nvm->word_size = BIT(size); 126 127 return 0; 128 } 129 130 /** 131 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 132 * @hw: pointer to the HW structure 133 **/ 134 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 135 { 136 struct e1000_mac_info *mac = &hw->mac; 137 138 /* Set media type and media-dependent function pointers */ 139 switch (hw->adapter->pdev->device) { 140 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 141 hw->phy.media_type = e1000_media_type_internal_serdes; 142 mac->ops.check_for_link = e1000e_check_for_serdes_link; 143 mac->ops.setup_physical_interface = 144 e1000e_setup_fiber_serdes_link; 145 break; 146 default: 147 hw->phy.media_type = e1000_media_type_copper; 148 mac->ops.check_for_link = e1000e_check_for_copper_link; 149 mac->ops.setup_physical_interface = 150 e1000_setup_copper_link_80003es2lan; 151 break; 152 } 153 154 /* Set mta register count */ 155 mac->mta_reg_count = 128; 156 /* Set rar entry count */ 157 mac->rar_entry_count = E1000_RAR_ENTRIES; 158 /* FWSM register */ 159 mac->has_fwsm = true; 160 /* ARC supported; valid only if manageability features are enabled. */ 161 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK); 162 /* Adaptive IFS not supported */ 163 mac->adaptive_ifs = false; 164 165 /* set lan id for port to determine which phy lock to use */ 166 hw->mac.ops.set_lan_id(hw); 167 168 return 0; 169 } 170 171 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) 172 { 173 struct e1000_hw *hw = &adapter->hw; 174 s32 rc; 175 176 rc = e1000_init_mac_params_80003es2lan(hw); 177 if (rc) 178 return rc; 179 180 rc = e1000_init_nvm_params_80003es2lan(hw); 181 if (rc) 182 return rc; 183 184 rc = e1000_init_phy_params_80003es2lan(hw); 185 if (rc) 186 return rc; 187 188 return 0; 189 } 190 191 /** 192 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 193 * @hw: pointer to the HW structure 194 * 195 * A wrapper to acquire access rights to the correct PHY. 196 **/ 197 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 198 { 199 u16 mask; 200 201 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 202 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 203 } 204 205 /** 206 * e1000_release_phy_80003es2lan - Release rights to access PHY 207 * @hw: pointer to the HW structure 208 * 209 * A wrapper to release access rights to the correct PHY. 210 **/ 211 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 212 { 213 u16 mask; 214 215 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 216 e1000_release_swfw_sync_80003es2lan(hw, mask); 217 } 218 219 /** 220 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 221 * @hw: pointer to the HW structure 222 * 223 * Acquire the semaphore to access the Kumeran interface. 224 * 225 **/ 226 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 227 { 228 u16 mask; 229 230 mask = E1000_SWFW_CSR_SM; 231 232 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 233 } 234 235 /** 236 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 237 * @hw: pointer to the HW structure 238 * 239 * Release the semaphore used to access the Kumeran interface 240 **/ 241 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 242 { 243 u16 mask; 244 245 mask = E1000_SWFW_CSR_SM; 246 247 e1000_release_swfw_sync_80003es2lan(hw, mask); 248 } 249 250 /** 251 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 252 * @hw: pointer to the HW structure 253 * 254 * Acquire the semaphore to access the EEPROM. 255 **/ 256 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 257 { 258 s32 ret_val; 259 260 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 261 if (ret_val) 262 return ret_val; 263 264 ret_val = e1000e_acquire_nvm(hw); 265 266 if (ret_val) 267 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 268 269 return ret_val; 270 } 271 272 /** 273 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 274 * @hw: pointer to the HW structure 275 * 276 * Release the semaphore used to access the EEPROM. 277 **/ 278 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 279 { 280 e1000e_release_nvm(hw); 281 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 282 } 283 284 /** 285 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 286 * @hw: pointer to the HW structure 287 * @mask: specifies which semaphore to acquire 288 * 289 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 290 * will also specify which port we're acquiring the lock for. 291 **/ 292 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 293 { 294 u32 swfw_sync; 295 u32 swmask = mask; 296 u32 fwmask = mask << 16; 297 s32 i = 0; 298 s32 timeout = 50; 299 300 while (i < timeout) { 301 if (e1000e_get_hw_semaphore(hw)) 302 return -E1000_ERR_SWFW_SYNC; 303 304 swfw_sync = er32(SW_FW_SYNC); 305 if (!(swfw_sync & (fwmask | swmask))) 306 break; 307 308 /* Firmware currently using resource (fwmask) 309 * or other software thread using resource (swmask) 310 */ 311 e1000e_put_hw_semaphore(hw); 312 mdelay(5); 313 i++; 314 } 315 316 if (i == timeout) { 317 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 318 return -E1000_ERR_SWFW_SYNC; 319 } 320 321 swfw_sync |= swmask; 322 ew32(SW_FW_SYNC, swfw_sync); 323 324 e1000e_put_hw_semaphore(hw); 325 326 return 0; 327 } 328 329 /** 330 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 331 * @hw: pointer to the HW structure 332 * @mask: specifies which semaphore to acquire 333 * 334 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 335 * will also specify which port we're releasing the lock for. 336 **/ 337 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 338 { 339 u32 swfw_sync; 340 341 while (e1000e_get_hw_semaphore(hw) != 0) 342 ; /* Empty */ 343 344 swfw_sync = er32(SW_FW_SYNC); 345 swfw_sync &= ~mask; 346 ew32(SW_FW_SYNC, swfw_sync); 347 348 e1000e_put_hw_semaphore(hw); 349 } 350 351 /** 352 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 353 * @hw: pointer to the HW structure 354 * @offset: offset of the register to read 355 * @data: pointer to the data returned from the operation 356 * 357 * Read the GG82563 PHY register. 358 **/ 359 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 360 u32 offset, u16 *data) 361 { 362 s32 ret_val; 363 u32 page_select; 364 u16 temp; 365 366 ret_val = e1000_acquire_phy_80003es2lan(hw); 367 if (ret_val) 368 return ret_val; 369 370 /* Select Configuration Page */ 371 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 372 page_select = GG82563_PHY_PAGE_SELECT; 373 } else { 374 /* Use Alternative Page Select register to access 375 * registers 30 and 31 376 */ 377 page_select = GG82563_PHY_PAGE_SELECT_ALT; 378 } 379 380 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 381 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 382 if (ret_val) { 383 e1000_release_phy_80003es2lan(hw); 384 return ret_val; 385 } 386 387 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 388 /* The "ready" bit in the MDIC register may be incorrectly set 389 * before the device has completed the "Page Select" MDI 390 * transaction. So we wait 200us after each MDI command... 391 */ 392 usleep_range(200, 400); 393 394 /* ...and verify the command was successful. */ 395 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 396 397 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 398 e1000_release_phy_80003es2lan(hw); 399 return -E1000_ERR_PHY; 400 } 401 402 usleep_range(200, 400); 403 404 ret_val = e1000e_read_phy_reg_mdic(hw, 405 MAX_PHY_REG_ADDRESS & offset, 406 data); 407 408 usleep_range(200, 400); 409 } else { 410 ret_val = e1000e_read_phy_reg_mdic(hw, 411 MAX_PHY_REG_ADDRESS & offset, 412 data); 413 } 414 415 e1000_release_phy_80003es2lan(hw); 416 417 return ret_val; 418 } 419 420 /** 421 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 422 * @hw: pointer to the HW structure 423 * @offset: offset of the register to read 424 * @data: value to write to the register 425 * 426 * Write to the GG82563 PHY register. 427 **/ 428 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 429 u32 offset, u16 data) 430 { 431 s32 ret_val; 432 u32 page_select; 433 u16 temp; 434 435 ret_val = e1000_acquire_phy_80003es2lan(hw); 436 if (ret_val) 437 return ret_val; 438 439 /* Select Configuration Page */ 440 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 441 page_select = GG82563_PHY_PAGE_SELECT; 442 } else { 443 /* Use Alternative Page Select register to access 444 * registers 30 and 31 445 */ 446 page_select = GG82563_PHY_PAGE_SELECT_ALT; 447 } 448 449 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 450 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 451 if (ret_val) { 452 e1000_release_phy_80003es2lan(hw); 453 return ret_val; 454 } 455 456 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 457 /* The "ready" bit in the MDIC register may be incorrectly set 458 * before the device has completed the "Page Select" MDI 459 * transaction. So we wait 200us after each MDI command... 460 */ 461 usleep_range(200, 400); 462 463 /* ...and verify the command was successful. */ 464 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 465 466 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 467 e1000_release_phy_80003es2lan(hw); 468 return -E1000_ERR_PHY; 469 } 470 471 usleep_range(200, 400); 472 473 ret_val = e1000e_write_phy_reg_mdic(hw, 474 MAX_PHY_REG_ADDRESS & 475 offset, data); 476 477 usleep_range(200, 400); 478 } else { 479 ret_val = e1000e_write_phy_reg_mdic(hw, 480 MAX_PHY_REG_ADDRESS & 481 offset, data); 482 } 483 484 e1000_release_phy_80003es2lan(hw); 485 486 return ret_val; 487 } 488 489 /** 490 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 491 * @hw: pointer to the HW structure 492 * @offset: offset of the register to read 493 * @words: number of words to write 494 * @data: buffer of data to write to the NVM 495 * 496 * Write "words" of data to the ESB2 NVM. 497 **/ 498 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 499 u16 words, u16 *data) 500 { 501 return e1000e_write_nvm_spi(hw, offset, words, data); 502 } 503 504 /** 505 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 506 * @hw: pointer to the HW structure 507 * 508 * Wait a specific amount of time for manageability processes to complete. 509 * This is a function pointer entry point called by the phy module. 510 **/ 511 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 512 { 513 s32 timeout = PHY_CFG_TIMEOUT; 514 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 515 516 if (hw->bus.func == 1) 517 mask = E1000_NVM_CFG_DONE_PORT_1; 518 519 while (timeout) { 520 if (er32(EEMNGCTL) & mask) 521 break; 522 usleep_range(1000, 2000); 523 timeout--; 524 } 525 if (!timeout) { 526 e_dbg("MNG configuration cycle has not completed.\n"); 527 return -E1000_ERR_RESET; 528 } 529 530 return 0; 531 } 532 533 /** 534 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 535 * @hw: pointer to the HW structure 536 * 537 * Force the speed and duplex settings onto the PHY. This is a 538 * function pointer entry point called by the phy module. 539 **/ 540 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 541 { 542 s32 ret_val; 543 u16 phy_data; 544 bool link; 545 546 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 547 * forced whenever speed and duplex are forced. 548 */ 549 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 550 if (ret_val) 551 return ret_val; 552 553 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 554 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); 555 if (ret_val) 556 return ret_val; 557 558 e_dbg("GG82563 PSCR: %X\n", phy_data); 559 560 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); 561 if (ret_val) 562 return ret_val; 563 564 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 565 566 /* Reset the phy to commit changes. */ 567 phy_data |= BMCR_RESET; 568 569 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); 570 if (ret_val) 571 return ret_val; 572 573 udelay(1); 574 575 if (hw->phy.autoneg_wait_to_complete) { 576 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n"); 577 578 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 579 100000, &link); 580 if (ret_val) 581 return ret_val; 582 583 if (!link) { 584 /* We didn't get link. 585 * Reset the DSP and cross our fingers. 586 */ 587 ret_val = e1000e_phy_reset_dsp(hw); 588 if (ret_val) 589 return ret_val; 590 } 591 592 /* Try once more */ 593 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 594 100000, &link); 595 if (ret_val) 596 return ret_val; 597 } 598 599 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 600 if (ret_val) 601 return ret_val; 602 603 /* Resetting the phy means we need to verify the TX_CLK corresponds 604 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 605 */ 606 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 607 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 608 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 609 else 610 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 611 612 /* In addition, we must re-enable CRS on Tx for both half and full 613 * duplex. 614 */ 615 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 616 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 617 618 return ret_val; 619 } 620 621 /** 622 * e1000_get_cable_length_80003es2lan - Set approximate cable length 623 * @hw: pointer to the HW structure 624 * 625 * Find the approximate cable length as measured by the GG82563 PHY. 626 * This is a function pointer entry point called by the phy module. 627 **/ 628 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 629 { 630 struct e1000_phy_info *phy = &hw->phy; 631 s32 ret_val; 632 u16 phy_data, index; 633 634 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 635 if (ret_val) 636 return ret_val; 637 638 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 639 640 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 641 return -E1000_ERR_PHY; 642 643 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 644 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 645 646 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 647 648 return 0; 649 } 650 651 /** 652 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 653 * @hw: pointer to the HW structure 654 * @speed: pointer to speed buffer 655 * @duplex: pointer to duplex buffer 656 * 657 * Retrieve the current speed and duplex configuration. 658 **/ 659 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 660 u16 *duplex) 661 { 662 s32 ret_val; 663 664 if (hw->phy.media_type == e1000_media_type_copper) { 665 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 666 hw->phy.ops.cfg_on_link_up(hw); 667 } else { 668 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, 669 speed, 670 duplex); 671 } 672 673 return ret_val; 674 } 675 676 /** 677 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 678 * @hw: pointer to the HW structure 679 * 680 * Perform a global reset to the ESB2 controller. 681 **/ 682 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 683 { 684 u32 ctrl; 685 s32 ret_val; 686 u16 kum_reg_data; 687 688 /* Prevent the PCI-E bus from sticking if there is no TLP connection 689 * on the last TLP read/write transaction when MAC is reset. 690 */ 691 ret_val = e1000e_disable_pcie_master(hw); 692 if (ret_val) 693 e_dbg("PCI-E Master disable polling has failed.\n"); 694 695 e_dbg("Masking off all interrupts\n"); 696 ew32(IMC, 0xffffffff); 697 698 ew32(RCTL, 0); 699 ew32(TCTL, E1000_TCTL_PSP); 700 e1e_flush(); 701 702 usleep_range(10000, 20000); 703 704 ctrl = er32(CTRL); 705 706 ret_val = e1000_acquire_phy_80003es2lan(hw); 707 if (ret_val) 708 return ret_val; 709 710 e_dbg("Issuing a global reset to MAC\n"); 711 ew32(CTRL, ctrl | E1000_CTRL_RST); 712 e1000_release_phy_80003es2lan(hw); 713 714 /* Disable IBIST slave mode (far-end loopback) */ 715 ret_val = 716 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 717 &kum_reg_data); 718 if (ret_val) 719 return ret_val; 720 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 721 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 722 kum_reg_data); 723 724 ret_val = e1000e_get_auto_rd_done(hw); 725 if (ret_val) 726 /* We don't want to continue accessing MAC registers. */ 727 return ret_val; 728 729 /* Clear any pending interrupt events. */ 730 ew32(IMC, 0xffffffff); 731 er32(ICR); 732 733 return e1000_check_alt_mac_addr_generic(hw); 734 } 735 736 /** 737 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 738 * @hw: pointer to the HW structure 739 * 740 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 741 **/ 742 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 743 { 744 struct e1000_mac_info *mac = &hw->mac; 745 u32 reg_data; 746 s32 ret_val; 747 u16 kum_reg_data; 748 u16 i; 749 750 e1000_initialize_hw_bits_80003es2lan(hw); 751 752 /* Initialize identification LED */ 753 ret_val = mac->ops.id_led_init(hw); 754 /* An error is not fatal and we should not stop init due to this */ 755 if (ret_val) 756 e_dbg("Error initializing identification LED\n"); 757 758 /* Disabling VLAN filtering */ 759 e_dbg("Initializing the IEEE VLAN\n"); 760 mac->ops.clear_vfta(hw); 761 762 /* Setup the receive address. */ 763 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 764 765 /* Zero out the Multicast HASH table */ 766 e_dbg("Zeroing the MTA\n"); 767 for (i = 0; i < mac->mta_reg_count; i++) 768 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 769 770 /* Setup link and flow control */ 771 ret_val = mac->ops.setup_link(hw); 772 if (ret_val) 773 return ret_val; 774 775 /* Disable IBIST slave mode (far-end loopback) */ 776 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 777 &kum_reg_data); 778 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 779 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 780 kum_reg_data); 781 782 /* Set the transmit descriptor write-back policy */ 783 reg_data = er32(TXDCTL(0)); 784 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 785 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 786 ew32(TXDCTL(0), reg_data); 787 788 /* ...for both queues. */ 789 reg_data = er32(TXDCTL(1)); 790 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 791 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 792 ew32(TXDCTL(1), reg_data); 793 794 /* Enable retransmit on late collisions */ 795 reg_data = er32(TCTL); 796 reg_data |= E1000_TCTL_RTLC; 797 ew32(TCTL, reg_data); 798 799 /* Configure Gigabit Carry Extend Padding */ 800 reg_data = er32(TCTL_EXT); 801 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 802 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 803 ew32(TCTL_EXT, reg_data); 804 805 /* Configure Transmit Inter-Packet Gap */ 806 reg_data = er32(TIPG); 807 reg_data &= ~E1000_TIPG_IPGT_MASK; 808 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 809 ew32(TIPG, reg_data); 810 811 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 812 reg_data &= ~0x00100000; 813 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 814 815 /* default to true to enable the MDIC W/A */ 816 hw->dev_spec.e80003es2lan.mdic_wa_enable = true; 817 818 ret_val = 819 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> 820 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); 821 if (!ret_val) { 822 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 823 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 824 hw->dev_spec.e80003es2lan.mdic_wa_enable = false; 825 } 826 827 /* Clear all of the statistics registers (clear on read). It is 828 * important that we do this after we have tried to establish link 829 * because the symbol error count will increment wildly if there 830 * is no link. 831 */ 832 e1000_clear_hw_cntrs_80003es2lan(hw); 833 834 return ret_val; 835 } 836 837 /** 838 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 839 * @hw: pointer to the HW structure 840 * 841 * Initializes required hardware-dependent bits needed for normal operation. 842 **/ 843 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 844 { 845 u32 reg; 846 847 /* Transmit Descriptor Control 0 */ 848 reg = er32(TXDCTL(0)); 849 reg |= BIT(22); 850 ew32(TXDCTL(0), reg); 851 852 /* Transmit Descriptor Control 1 */ 853 reg = er32(TXDCTL(1)); 854 reg |= BIT(22); 855 ew32(TXDCTL(1), reg); 856 857 /* Transmit Arbitration Control 0 */ 858 reg = er32(TARC(0)); 859 reg &= ~(0xF << 27); /* 30:27 */ 860 if (hw->phy.media_type != e1000_media_type_copper) 861 reg &= ~BIT(20); 862 ew32(TARC(0), reg); 863 864 /* Transmit Arbitration Control 1 */ 865 reg = er32(TARC(1)); 866 if (er32(TCTL) & E1000_TCTL_MULR) 867 reg &= ~BIT(28); 868 else 869 reg |= BIT(28); 870 ew32(TARC(1), reg); 871 872 /* Disable IPv6 extension header parsing because some malformed 873 * IPv6 headers can hang the Rx. 874 */ 875 reg = er32(RFCTL); 876 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 877 ew32(RFCTL, reg); 878 } 879 880 /** 881 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 882 * @hw: pointer to the HW structure 883 * 884 * Setup some GG82563 PHY registers for obtaining link 885 **/ 886 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 887 { 888 struct e1000_phy_info *phy = &hw->phy; 889 s32 ret_val; 890 u32 reg; 891 u16 data; 892 893 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 894 if (ret_val) 895 return ret_val; 896 897 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 898 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 899 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 900 901 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 902 if (ret_val) 903 return ret_val; 904 905 /* Options: 906 * MDI/MDI-X = 0 (default) 907 * 0 - Auto for all speeds 908 * 1 - MDI mode 909 * 2 - MDI-X mode 910 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 911 */ 912 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); 913 if (ret_val) 914 return ret_val; 915 916 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 917 918 switch (phy->mdix) { 919 case 1: 920 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 921 break; 922 case 2: 923 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 924 break; 925 case 0: 926 default: 927 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 928 break; 929 } 930 931 /* Options: 932 * disable_polarity_correction = 0 (default) 933 * Automatic Correction for Reversed Cable Polarity 934 * 0 - Disabled 935 * 1 - Enabled 936 */ 937 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 938 if (phy->disable_polarity_correction) 939 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 940 941 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); 942 if (ret_val) 943 return ret_val; 944 945 /* SW Reset the PHY so all changes take effect */ 946 ret_val = hw->phy.ops.commit(hw); 947 if (ret_val) { 948 e_dbg("Error Resetting the PHY\n"); 949 return ret_val; 950 } 951 952 /* Bypass Rx and Tx FIFO's */ 953 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; 954 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 955 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 956 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 957 if (ret_val) 958 return ret_val; 959 960 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; 961 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); 962 if (ret_val) 963 return ret_val; 964 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 965 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); 966 if (ret_val) 967 return ret_val; 968 969 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); 970 if (ret_val) 971 return ret_val; 972 973 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 974 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); 975 if (ret_val) 976 return ret_val; 977 978 reg = er32(CTRL_EXT); 979 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 980 ew32(CTRL_EXT, reg); 981 982 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 983 if (ret_val) 984 return ret_val; 985 986 /* Do not init these registers when the HW is in IAMT mode, since the 987 * firmware will have already initialized them. We only initialize 988 * them if the HW is not in IAMT mode. 989 */ 990 if (!hw->mac.ops.check_mng_mode(hw)) { 991 /* Enable Electrical Idle on the PHY */ 992 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 993 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); 994 if (ret_val) 995 return ret_val; 996 997 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); 998 if (ret_val) 999 return ret_val; 1000 1001 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1002 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); 1003 if (ret_val) 1004 return ret_val; 1005 } 1006 1007 /* Workaround: Disable padding in Kumeran interface in the MAC 1008 * and in the PHY to avoid CRC errors. 1009 */ 1010 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); 1011 if (ret_val) 1012 return ret_val; 1013 1014 data |= GG82563_ICR_DIS_PADDING; 1015 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); 1016 if (ret_val) 1017 return ret_val; 1018 1019 return 0; 1020 } 1021 1022 /** 1023 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1024 * @hw: pointer to the HW structure 1025 * 1026 * Essentially a wrapper for setting up all things "copper" related. 1027 * This is a function pointer entry point called by the mac module. 1028 **/ 1029 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1030 { 1031 u32 ctrl; 1032 s32 ret_val; 1033 u16 reg_data; 1034 1035 ctrl = er32(CTRL); 1036 ctrl |= E1000_CTRL_SLU; 1037 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1038 ew32(CTRL, ctrl); 1039 1040 /* Set the mac to wait the maximum time between each 1041 * iteration and increase the max iterations when 1042 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1043 */ 1044 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1045 0xFFFF); 1046 if (ret_val) 1047 return ret_val; 1048 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1049 ®_data); 1050 if (ret_val) 1051 return ret_val; 1052 reg_data |= 0x3F; 1053 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1054 reg_data); 1055 if (ret_val) 1056 return ret_val; 1057 ret_val = 1058 e1000_read_kmrn_reg_80003es2lan(hw, 1059 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1060 ®_data); 1061 if (ret_val) 1062 return ret_val; 1063 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1064 ret_val = 1065 e1000_write_kmrn_reg_80003es2lan(hw, 1066 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1067 reg_data); 1068 if (ret_val) 1069 return ret_val; 1070 1071 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1072 if (ret_val) 1073 return ret_val; 1074 1075 return e1000e_setup_copper_link(hw); 1076 } 1077 1078 /** 1079 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1080 * @hw: pointer to the HW structure 1081 * @duplex: current duplex setting 1082 * 1083 * Configure the KMRN interface by applying last minute quirks for 1084 * 10/100 operation. 1085 **/ 1086 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1087 { 1088 s32 ret_val = 0; 1089 u16 speed; 1090 u16 duplex; 1091 1092 if (hw->phy.media_type == e1000_media_type_copper) { 1093 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, 1094 &duplex); 1095 if (ret_val) 1096 return ret_val; 1097 1098 if (speed == SPEED_1000) 1099 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1100 else 1101 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1102 } 1103 1104 return ret_val; 1105 } 1106 1107 /** 1108 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1109 * @hw: pointer to the HW structure 1110 * @duplex: current duplex setting 1111 * 1112 * Configure the KMRN interface by applying last minute quirks for 1113 * 10/100 operation. 1114 **/ 1115 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1116 { 1117 s32 ret_val; 1118 u32 tipg; 1119 u32 i = 0; 1120 u16 reg_data, reg_data2; 1121 1122 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1123 ret_val = 1124 e1000_write_kmrn_reg_80003es2lan(hw, 1125 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1126 reg_data); 1127 if (ret_val) 1128 return ret_val; 1129 1130 /* Configure Transmit Inter-Packet Gap */ 1131 tipg = er32(TIPG); 1132 tipg &= ~E1000_TIPG_IPGT_MASK; 1133 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1134 ew32(TIPG, tipg); 1135 1136 do { 1137 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1138 if (ret_val) 1139 return ret_val; 1140 1141 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); 1142 if (ret_val) 1143 return ret_val; 1144 i++; 1145 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1146 1147 if (duplex == HALF_DUPLEX) 1148 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1149 else 1150 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1151 1152 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1153 } 1154 1155 /** 1156 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1157 * @hw: pointer to the HW structure 1158 * 1159 * Configure the KMRN interface by applying last minute quirks for 1160 * gigabit operation. 1161 **/ 1162 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1163 { 1164 s32 ret_val; 1165 u16 reg_data, reg_data2; 1166 u32 tipg; 1167 u32 i = 0; 1168 1169 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1170 ret_val = 1171 e1000_write_kmrn_reg_80003es2lan(hw, 1172 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1173 reg_data); 1174 if (ret_val) 1175 return ret_val; 1176 1177 /* Configure Transmit Inter-Packet Gap */ 1178 tipg = er32(TIPG); 1179 tipg &= ~E1000_TIPG_IPGT_MASK; 1180 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1181 ew32(TIPG, tipg); 1182 1183 do { 1184 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 1185 if (ret_val) 1186 return ret_val; 1187 1188 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); 1189 if (ret_val) 1190 return ret_val; 1191 i++; 1192 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1193 1194 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1195 1196 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1197 } 1198 1199 /** 1200 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1201 * @hw: pointer to the HW structure 1202 * @offset: register offset to be read 1203 * @data: pointer to the read data 1204 * 1205 * Acquire semaphore, then read the PHY register at offset 1206 * using the kumeran interface. The information retrieved is stored in data. 1207 * Release the semaphore before exiting. 1208 **/ 1209 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1210 u16 *data) 1211 { 1212 u32 kmrnctrlsta; 1213 s32 ret_val; 1214 1215 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1216 if (ret_val) 1217 return ret_val; 1218 1219 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1220 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1221 ew32(KMRNCTRLSTA, kmrnctrlsta); 1222 e1e_flush(); 1223 1224 udelay(2); 1225 1226 kmrnctrlsta = er32(KMRNCTRLSTA); 1227 *data = (u16)kmrnctrlsta; 1228 1229 e1000_release_mac_csr_80003es2lan(hw); 1230 1231 return ret_val; 1232 } 1233 1234 /** 1235 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1236 * @hw: pointer to the HW structure 1237 * @offset: register offset to write to 1238 * @data: data to write at register offset 1239 * 1240 * Acquire semaphore, then write the data to PHY register 1241 * at the offset using the kumeran interface. Release semaphore 1242 * before exiting. 1243 **/ 1244 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1245 u16 data) 1246 { 1247 u32 kmrnctrlsta; 1248 s32 ret_val; 1249 1250 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1251 if (ret_val) 1252 return ret_val; 1253 1254 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1255 E1000_KMRNCTRLSTA_OFFSET) | data; 1256 ew32(KMRNCTRLSTA, kmrnctrlsta); 1257 e1e_flush(); 1258 1259 udelay(2); 1260 1261 e1000_release_mac_csr_80003es2lan(hw); 1262 1263 return ret_val; 1264 } 1265 1266 /** 1267 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1268 * @hw: pointer to the HW structure 1269 **/ 1270 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1271 { 1272 s32 ret_val; 1273 1274 /* If there's an alternate MAC address place it in RAR0 1275 * so that it will override the Si installed default perm 1276 * address. 1277 */ 1278 ret_val = e1000_check_alt_mac_addr_generic(hw); 1279 if (ret_val) 1280 return ret_val; 1281 1282 return e1000_read_mac_addr_generic(hw); 1283 } 1284 1285 /** 1286 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1287 * @hw: pointer to the HW structure 1288 * 1289 * In the case of a PHY power down to save power, or to turn off link during a 1290 * driver unload, or wake on lan is not enabled, remove the link. 1291 **/ 1292 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1293 { 1294 /* If the management interface is not enabled, then power down */ 1295 if (!(hw->mac.ops.check_mng_mode(hw) || 1296 hw->phy.ops.check_reset_block(hw))) 1297 e1000_power_down_phy_copper(hw); 1298 } 1299 1300 /** 1301 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1302 * @hw: pointer to the HW structure 1303 * 1304 * Clears the hardware counters by reading the counter registers. 1305 **/ 1306 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1307 { 1308 e1000e_clear_hw_cntrs_base(hw); 1309 1310 er32(PRC64); 1311 er32(PRC127); 1312 er32(PRC255); 1313 er32(PRC511); 1314 er32(PRC1023); 1315 er32(PRC1522); 1316 er32(PTC64); 1317 er32(PTC127); 1318 er32(PTC255); 1319 er32(PTC511); 1320 er32(PTC1023); 1321 er32(PTC1522); 1322 1323 er32(ALGNERRC); 1324 er32(RXERRC); 1325 er32(TNCRS); 1326 er32(CEXTERR); 1327 er32(TSCTC); 1328 er32(TSCTFC); 1329 1330 er32(MGTPRC); 1331 er32(MGTPDC); 1332 er32(MGTPTC); 1333 1334 er32(IAC); 1335 er32(ICRXOC); 1336 1337 er32(ICRXPTC); 1338 er32(ICRXATC); 1339 er32(ICTXPTC); 1340 er32(ICTXATC); 1341 er32(ICTXQEC); 1342 er32(ICTXQMTC); 1343 er32(ICRXDMTC); 1344 } 1345 1346 static const struct e1000_mac_operations es2_mac_ops = { 1347 .read_mac_addr = e1000_read_mac_addr_80003es2lan, 1348 .id_led_init = e1000e_id_led_init_generic, 1349 .blink_led = e1000e_blink_led_generic, 1350 .check_mng_mode = e1000e_check_mng_mode_generic, 1351 /* check_for_link dependent on media type */ 1352 .cleanup_led = e1000e_cleanup_led_generic, 1353 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, 1354 .get_bus_info = e1000e_get_bus_info_pcie, 1355 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1356 .get_link_up_info = e1000_get_link_up_info_80003es2lan, 1357 .led_on = e1000e_led_on_generic, 1358 .led_off = e1000e_led_off_generic, 1359 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1360 .write_vfta = e1000_write_vfta_generic, 1361 .clear_vfta = e1000_clear_vfta_generic, 1362 .reset_hw = e1000_reset_hw_80003es2lan, 1363 .init_hw = e1000_init_hw_80003es2lan, 1364 .setup_link = e1000e_setup_link_generic, 1365 /* setup_physical_interface dependent on media type */ 1366 .setup_led = e1000e_setup_led_generic, 1367 .config_collision_dist = e1000e_config_collision_dist_generic, 1368 .rar_set = e1000e_rar_set_generic, 1369 .rar_get_count = e1000e_rar_get_count_generic, 1370 }; 1371 1372 static const struct e1000_phy_operations es2_phy_ops = { 1373 .acquire = e1000_acquire_phy_80003es2lan, 1374 .check_polarity = e1000_check_polarity_m88, 1375 .check_reset_block = e1000e_check_reset_block_generic, 1376 .commit = e1000e_phy_sw_reset, 1377 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, 1378 .get_cfg_done = e1000_get_cfg_done_80003es2lan, 1379 .get_cable_length = e1000_get_cable_length_80003es2lan, 1380 .get_info = e1000e_get_phy_info_m88, 1381 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, 1382 .release = e1000_release_phy_80003es2lan, 1383 .reset = e1000e_phy_hw_reset_generic, 1384 .set_d0_lplu_state = NULL, 1385 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1386 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, 1387 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, 1388 }; 1389 1390 static const struct e1000_nvm_operations es2_nvm_ops = { 1391 .acquire = e1000_acquire_nvm_80003es2lan, 1392 .read = e1000e_read_nvm_eerd, 1393 .release = e1000_release_nvm_80003es2lan, 1394 .reload = e1000e_reload_nvm_generic, 1395 .update = e1000e_update_nvm_checksum_generic, 1396 .valid_led_default = e1000e_valid_led_default, 1397 .validate = e1000e_validate_nvm_checksum_generic, 1398 .write = e1000_write_nvm_80003es2lan, 1399 }; 1400 1401 const struct e1000_info e1000_es2_info = { 1402 .mac = e1000_80003es2lan, 1403 .flags = FLAG_HAS_HW_VLAN_FILTER 1404 | FLAG_HAS_JUMBO_FRAMES 1405 | FLAG_HAS_WOL 1406 | FLAG_APME_IN_CTRL3 1407 | FLAG_HAS_CTRLEXT_ON_LOAD 1408 | FLAG_RX_NEEDS_RESTART /* errata */ 1409 | FLAG_TARC_SET_BIT_ZERO /* errata */ 1410 | FLAG_APME_CHECK_PORT_B 1411 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */ 1412 .flags2 = FLAG2_DMA_BURST, 1413 .pba = 38, 1414 .max_hw_frame_size = DEFAULT_JUMBO, 1415 .get_variants = e1000_get_variants_80003es2lan, 1416 .mac_ops = &es2_mac_ops, 1417 .phy_ops = &es2_phy_ops, 1418 .nvm_ops = &es2_nvm_ops, 1419 }; 1420