1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
5  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
6  */
7 
8 #include "e1000.h"
9 
10 /* A table for the GG82563 cable length where the range is defined
11  * with a lower bound at "index" and the upper bound at
12  * "index + 5".
13  */
14 static const u16 e1000_gg82563_cable_length_table[] = {
15 	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
16 };
17 
18 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
19 		ARRAY_SIZE(e1000_gg82563_cable_length_table)
20 
21 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
22 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
23 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
24 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
25 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
26 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
27 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
28 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
29 					   u16 *data);
30 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
31 					    u16 data);
32 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
33 
34 /**
35  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
36  *  @hw: pointer to the HW structure
37  **/
38 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
39 {
40 	struct e1000_phy_info *phy = &hw->phy;
41 	s32 ret_val;
42 
43 	if (hw->phy.media_type != e1000_media_type_copper) {
44 		phy->type = e1000_phy_none;
45 		return 0;
46 	} else {
47 		phy->ops.power_up = e1000_power_up_phy_copper;
48 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
49 	}
50 
51 	phy->addr = 1;
52 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
53 	phy->reset_delay_us = 100;
54 	phy->type = e1000_phy_gg82563;
55 
56 	/* This can only be done after all function pointers are setup. */
57 	ret_val = e1000e_get_phy_id(hw);
58 
59 	/* Verify phy id */
60 	if (phy->id != GG82563_E_PHY_ID)
61 		return -E1000_ERR_PHY;
62 
63 	return ret_val;
64 }
65 
66 /**
67  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
68  *  @hw: pointer to the HW structure
69  **/
70 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
71 {
72 	struct e1000_nvm_info *nvm = &hw->nvm;
73 	u32 eecd = er32(EECD);
74 	u16 size;
75 
76 	nvm->opcode_bits = 8;
77 	nvm->delay_usec = 1;
78 	switch (nvm->override) {
79 	case e1000_nvm_override_spi_large:
80 		nvm->page_size = 32;
81 		nvm->address_bits = 16;
82 		break;
83 	case e1000_nvm_override_spi_small:
84 		nvm->page_size = 8;
85 		nvm->address_bits = 8;
86 		break;
87 	default:
88 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
89 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
90 		break;
91 	}
92 
93 	nvm->type = e1000_nvm_eeprom_spi;
94 
95 	size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
96 
97 	/* Added to a constant, "size" becomes the left-shift value
98 	 * for setting word_size.
99 	 */
100 	size += NVM_WORD_SIZE_BASE_SHIFT;
101 
102 	/* EEPROM access above 16k is unsupported */
103 	if (size > 14)
104 		size = 14;
105 	nvm->word_size = BIT(size);
106 
107 	return 0;
108 }
109 
110 /**
111  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
112  *  @hw: pointer to the HW structure
113  **/
114 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
115 {
116 	struct e1000_mac_info *mac = &hw->mac;
117 
118 	/* Set media type and media-dependent function pointers */
119 	switch (hw->adapter->pdev->device) {
120 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
121 		hw->phy.media_type = e1000_media_type_internal_serdes;
122 		mac->ops.check_for_link = e1000e_check_for_serdes_link;
123 		mac->ops.setup_physical_interface =
124 		    e1000e_setup_fiber_serdes_link;
125 		break;
126 	default:
127 		hw->phy.media_type = e1000_media_type_copper;
128 		mac->ops.check_for_link = e1000e_check_for_copper_link;
129 		mac->ops.setup_physical_interface =
130 		    e1000_setup_copper_link_80003es2lan;
131 		break;
132 	}
133 
134 	/* Set mta register count */
135 	mac->mta_reg_count = 128;
136 	/* Set rar entry count */
137 	mac->rar_entry_count = E1000_RAR_ENTRIES;
138 	/* FWSM register */
139 	mac->has_fwsm = true;
140 	/* ARC supported; valid only if manageability features are enabled. */
141 	mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
142 	/* Adaptive IFS not supported */
143 	mac->adaptive_ifs = false;
144 
145 	/* set lan id for port to determine which phy lock to use */
146 	hw->mac.ops.set_lan_id(hw);
147 
148 	return 0;
149 }
150 
151 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
152 {
153 	struct e1000_hw *hw = &adapter->hw;
154 	s32 rc;
155 
156 	rc = e1000_init_mac_params_80003es2lan(hw);
157 	if (rc)
158 		return rc;
159 
160 	rc = e1000_init_nvm_params_80003es2lan(hw);
161 	if (rc)
162 		return rc;
163 
164 	rc = e1000_init_phy_params_80003es2lan(hw);
165 	if (rc)
166 		return rc;
167 
168 	return 0;
169 }
170 
171 /**
172  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
173  *  @hw: pointer to the HW structure
174  *
175  *  A wrapper to acquire access rights to the correct PHY.
176  **/
177 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
178 {
179 	u16 mask;
180 
181 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
182 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
183 }
184 
185 /**
186  *  e1000_release_phy_80003es2lan - Release rights to access PHY
187  *  @hw: pointer to the HW structure
188  *
189  *  A wrapper to release access rights to the correct PHY.
190  **/
191 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
192 {
193 	u16 mask;
194 
195 	mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
196 	e1000_release_swfw_sync_80003es2lan(hw, mask);
197 }
198 
199 /**
200  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
201  *  @hw: pointer to the HW structure
202  *
203  *  Acquire the semaphore to access the Kumeran interface.
204  *
205  **/
206 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
207 {
208 	u16 mask;
209 
210 	mask = E1000_SWFW_CSR_SM;
211 
212 	return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
213 }
214 
215 /**
216  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
217  *  @hw: pointer to the HW structure
218  *
219  *  Release the semaphore used to access the Kumeran interface
220  **/
221 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
222 {
223 	u16 mask;
224 
225 	mask = E1000_SWFW_CSR_SM;
226 
227 	e1000_release_swfw_sync_80003es2lan(hw, mask);
228 }
229 
230 /**
231  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
232  *  @hw: pointer to the HW structure
233  *
234  *  Acquire the semaphore to access the EEPROM.
235  **/
236 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
237 {
238 	s32 ret_val;
239 
240 	ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
241 	if (ret_val)
242 		return ret_val;
243 
244 	ret_val = e1000e_acquire_nvm(hw);
245 
246 	if (ret_val)
247 		e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
248 
249 	return ret_val;
250 }
251 
252 /**
253  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
254  *  @hw: pointer to the HW structure
255  *
256  *  Release the semaphore used to access the EEPROM.
257  **/
258 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
259 {
260 	e1000e_release_nvm(hw);
261 	e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
262 }
263 
264 /**
265  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
266  *  @hw: pointer to the HW structure
267  *  @mask: specifies which semaphore to acquire
268  *
269  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
270  *  will also specify which port we're acquiring the lock for.
271  **/
272 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
273 {
274 	u32 swfw_sync;
275 	u32 swmask = mask;
276 	u32 fwmask = mask << 16;
277 	s32 i = 0;
278 	s32 timeout = 50;
279 
280 	while (i < timeout) {
281 		if (e1000e_get_hw_semaphore(hw))
282 			return -E1000_ERR_SWFW_SYNC;
283 
284 		swfw_sync = er32(SW_FW_SYNC);
285 		if (!(swfw_sync & (fwmask | swmask)))
286 			break;
287 
288 		/* Firmware currently using resource (fwmask)
289 		 * or other software thread using resource (swmask)
290 		 */
291 		e1000e_put_hw_semaphore(hw);
292 		mdelay(5);
293 		i++;
294 	}
295 
296 	if (i == timeout) {
297 		e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
298 		return -E1000_ERR_SWFW_SYNC;
299 	}
300 
301 	swfw_sync |= swmask;
302 	ew32(SW_FW_SYNC, swfw_sync);
303 
304 	e1000e_put_hw_semaphore(hw);
305 
306 	return 0;
307 }
308 
309 /**
310  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
311  *  @hw: pointer to the HW structure
312  *  @mask: specifies which semaphore to acquire
313  *
314  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
315  *  will also specify which port we're releasing the lock for.
316  **/
317 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
318 {
319 	u32 swfw_sync;
320 
321 	while (e1000e_get_hw_semaphore(hw) != 0)
322 		; /* Empty */
323 
324 	swfw_sync = er32(SW_FW_SYNC);
325 	swfw_sync &= ~mask;
326 	ew32(SW_FW_SYNC, swfw_sync);
327 
328 	e1000e_put_hw_semaphore(hw);
329 }
330 
331 /**
332  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
333  *  @hw: pointer to the HW structure
334  *  @offset: offset of the register to read
335  *  @data: pointer to the data returned from the operation
336  *
337  *  Read the GG82563 PHY register.
338  **/
339 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
340 						  u32 offset, u16 *data)
341 {
342 	s32 ret_val;
343 	u32 page_select;
344 	u16 temp;
345 
346 	ret_val = e1000_acquire_phy_80003es2lan(hw);
347 	if (ret_val)
348 		return ret_val;
349 
350 	/* Select Configuration Page */
351 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
352 		page_select = GG82563_PHY_PAGE_SELECT;
353 	} else {
354 		/* Use Alternative Page Select register to access
355 		 * registers 30 and 31
356 		 */
357 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
358 	}
359 
360 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
361 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
362 	if (ret_val) {
363 		e1000_release_phy_80003es2lan(hw);
364 		return ret_val;
365 	}
366 
367 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
368 		/* The "ready" bit in the MDIC register may be incorrectly set
369 		 * before the device has completed the "Page Select" MDI
370 		 * transaction.  So we wait 200us after each MDI command...
371 		 */
372 		usleep_range(200, 400);
373 
374 		/* ...and verify the command was successful. */
375 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
376 
377 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
378 			e1000_release_phy_80003es2lan(hw);
379 			return -E1000_ERR_PHY;
380 		}
381 
382 		usleep_range(200, 400);
383 
384 		ret_val = e1000e_read_phy_reg_mdic(hw,
385 						   MAX_PHY_REG_ADDRESS & offset,
386 						   data);
387 
388 		usleep_range(200, 400);
389 	} else {
390 		ret_val = e1000e_read_phy_reg_mdic(hw,
391 						   MAX_PHY_REG_ADDRESS & offset,
392 						   data);
393 	}
394 
395 	e1000_release_phy_80003es2lan(hw);
396 
397 	return ret_val;
398 }
399 
400 /**
401  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
402  *  @hw: pointer to the HW structure
403  *  @offset: offset of the register to read
404  *  @data: value to write to the register
405  *
406  *  Write to the GG82563 PHY register.
407  **/
408 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
409 						   u32 offset, u16 data)
410 {
411 	s32 ret_val;
412 	u32 page_select;
413 	u16 temp;
414 
415 	ret_val = e1000_acquire_phy_80003es2lan(hw);
416 	if (ret_val)
417 		return ret_val;
418 
419 	/* Select Configuration Page */
420 	if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
421 		page_select = GG82563_PHY_PAGE_SELECT;
422 	} else {
423 		/* Use Alternative Page Select register to access
424 		 * registers 30 and 31
425 		 */
426 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
427 	}
428 
429 	temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
430 	ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
431 	if (ret_val) {
432 		e1000_release_phy_80003es2lan(hw);
433 		return ret_val;
434 	}
435 
436 	if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
437 		/* The "ready" bit in the MDIC register may be incorrectly set
438 		 * before the device has completed the "Page Select" MDI
439 		 * transaction.  So we wait 200us after each MDI command...
440 		 */
441 		usleep_range(200, 400);
442 
443 		/* ...and verify the command was successful. */
444 		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
445 
446 		if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
447 			e1000_release_phy_80003es2lan(hw);
448 			return -E1000_ERR_PHY;
449 		}
450 
451 		usleep_range(200, 400);
452 
453 		ret_val = e1000e_write_phy_reg_mdic(hw,
454 						    MAX_PHY_REG_ADDRESS &
455 						    offset, data);
456 
457 		usleep_range(200, 400);
458 	} else {
459 		ret_val = e1000e_write_phy_reg_mdic(hw,
460 						    MAX_PHY_REG_ADDRESS &
461 						    offset, data);
462 	}
463 
464 	e1000_release_phy_80003es2lan(hw);
465 
466 	return ret_val;
467 }
468 
469 /**
470  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
471  *  @hw: pointer to the HW structure
472  *  @offset: offset of the register to read
473  *  @words: number of words to write
474  *  @data: buffer of data to write to the NVM
475  *
476  *  Write "words" of data to the ESB2 NVM.
477  **/
478 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
479 				       u16 words, u16 *data)
480 {
481 	return e1000e_write_nvm_spi(hw, offset, words, data);
482 }
483 
484 /**
485  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
486  *  @hw: pointer to the HW structure
487  *
488  *  Wait a specific amount of time for manageability processes to complete.
489  *  This is a function pointer entry point called by the phy module.
490  **/
491 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
492 {
493 	s32 timeout = PHY_CFG_TIMEOUT;
494 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
495 
496 	if (hw->bus.func == 1)
497 		mask = E1000_NVM_CFG_DONE_PORT_1;
498 
499 	while (timeout) {
500 		if (er32(EEMNGCTL) & mask)
501 			break;
502 		usleep_range(1000, 2000);
503 		timeout--;
504 	}
505 	if (!timeout) {
506 		e_dbg("MNG configuration cycle has not completed.\n");
507 		return -E1000_ERR_RESET;
508 	}
509 
510 	return 0;
511 }
512 
513 /**
514  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
515  *  @hw: pointer to the HW structure
516  *
517  *  Force the speed and duplex settings onto the PHY.  This is a
518  *  function pointer entry point called by the phy module.
519  **/
520 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
521 {
522 	s32 ret_val;
523 	u16 phy_data;
524 	bool link;
525 
526 	/* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
527 	 * forced whenever speed and duplex are forced.
528 	 */
529 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
530 	if (ret_val)
531 		return ret_val;
532 
533 	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
534 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
535 	if (ret_val)
536 		return ret_val;
537 
538 	e_dbg("GG82563 PSCR: %X\n", phy_data);
539 
540 	ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
541 	if (ret_val)
542 		return ret_val;
543 
544 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
545 
546 	/* Reset the phy to commit changes. */
547 	phy_data |= BMCR_RESET;
548 
549 	ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
550 	if (ret_val)
551 		return ret_val;
552 
553 	udelay(1);
554 
555 	if (hw->phy.autoneg_wait_to_complete) {
556 		e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
557 
558 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
559 						      100000, &link);
560 		if (ret_val)
561 			return ret_val;
562 
563 		if (!link) {
564 			/* We didn't get link.
565 			 * Reset the DSP and cross our fingers.
566 			 */
567 			ret_val = e1000e_phy_reset_dsp(hw);
568 			if (ret_val)
569 				return ret_val;
570 		}
571 
572 		/* Try once more */
573 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
574 						      100000, &link);
575 		if (ret_val)
576 			return ret_val;
577 	}
578 
579 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
580 	if (ret_val)
581 		return ret_val;
582 
583 	/* Resetting the phy means we need to verify the TX_CLK corresponds
584 	 * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
585 	 */
586 	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
587 	if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
588 		phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
589 	else
590 		phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
591 
592 	/* In addition, we must re-enable CRS on Tx for both half and full
593 	 * duplex.
594 	 */
595 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
596 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
597 
598 	return ret_val;
599 }
600 
601 /**
602  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
603  *  @hw: pointer to the HW structure
604  *
605  *  Find the approximate cable length as measured by the GG82563 PHY.
606  *  This is a function pointer entry point called by the phy module.
607  **/
608 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
609 {
610 	struct e1000_phy_info *phy = &hw->phy;
611 	s32 ret_val;
612 	u16 phy_data, index;
613 
614 	ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
615 	if (ret_val)
616 		return ret_val;
617 
618 	index = phy_data & GG82563_DSPD_CABLE_LENGTH;
619 
620 	if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
621 		return -E1000_ERR_PHY;
622 
623 	phy->min_cable_length = e1000_gg82563_cable_length_table[index];
624 	phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
625 
626 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
627 
628 	return 0;
629 }
630 
631 /**
632  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
633  *  @hw: pointer to the HW structure
634  *  @speed: pointer to speed buffer
635  *  @duplex: pointer to duplex buffer
636  *
637  *  Retrieve the current speed and duplex configuration.
638  **/
639 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
640 					      u16 *duplex)
641 {
642 	s32 ret_val;
643 
644 	if (hw->phy.media_type == e1000_media_type_copper) {
645 		ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
646 		hw->phy.ops.cfg_on_link_up(hw);
647 	} else {
648 		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
649 								   speed,
650 								   duplex);
651 	}
652 
653 	return ret_val;
654 }
655 
656 /**
657  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
658  *  @hw: pointer to the HW structure
659  *
660  *  Perform a global reset to the ESB2 controller.
661  **/
662 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
663 {
664 	u32 ctrl;
665 	s32 ret_val;
666 	u16 kum_reg_data;
667 
668 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
669 	 * on the last TLP read/write transaction when MAC is reset.
670 	 */
671 	ret_val = e1000e_disable_pcie_master(hw);
672 	if (ret_val)
673 		e_dbg("PCI-E Master disable polling has failed.\n");
674 
675 	e_dbg("Masking off all interrupts\n");
676 	ew32(IMC, 0xffffffff);
677 
678 	ew32(RCTL, 0);
679 	ew32(TCTL, E1000_TCTL_PSP);
680 	e1e_flush();
681 
682 	usleep_range(10000, 11000);
683 
684 	ctrl = er32(CTRL);
685 
686 	ret_val = e1000_acquire_phy_80003es2lan(hw);
687 	if (ret_val)
688 		return ret_val;
689 
690 	e_dbg("Issuing a global reset to MAC\n");
691 	ew32(CTRL, ctrl | E1000_CTRL_RST);
692 	e1000_release_phy_80003es2lan(hw);
693 
694 	/* Disable IBIST slave mode (far-end loopback) */
695 	ret_val =
696 	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
697 					    &kum_reg_data);
698 	if (!ret_val) {
699 		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
700 		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
701 						 E1000_KMRNCTRLSTA_INBAND_PARAM,
702 						 kum_reg_data);
703 		if (ret_val)
704 			e_dbg("Error disabling far-end loopback\n");
705 	} else {
706 		e_dbg("Error disabling far-end loopback\n");
707 	}
708 
709 	ret_val = e1000e_get_auto_rd_done(hw);
710 	if (ret_val)
711 		/* We don't want to continue accessing MAC registers. */
712 		return ret_val;
713 
714 	/* Clear any pending interrupt events. */
715 	ew32(IMC, 0xffffffff);
716 	er32(ICR);
717 
718 	return e1000_check_alt_mac_addr_generic(hw);
719 }
720 
721 /**
722  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
723  *  @hw: pointer to the HW structure
724  *
725  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
726  **/
727 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
728 {
729 	struct e1000_mac_info *mac = &hw->mac;
730 	u32 reg_data;
731 	s32 ret_val;
732 	u16 kum_reg_data;
733 	u16 i;
734 
735 	e1000_initialize_hw_bits_80003es2lan(hw);
736 
737 	/* Initialize identification LED */
738 	ret_val = mac->ops.id_led_init(hw);
739 	/* An error is not fatal and we should not stop init due to this */
740 	if (ret_val)
741 		e_dbg("Error initializing identification LED\n");
742 
743 	/* Disabling VLAN filtering */
744 	e_dbg("Initializing the IEEE VLAN\n");
745 	mac->ops.clear_vfta(hw);
746 
747 	/* Setup the receive address. */
748 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);
749 
750 	/* Zero out the Multicast HASH table */
751 	e_dbg("Zeroing the MTA\n");
752 	for (i = 0; i < mac->mta_reg_count; i++)
753 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
754 
755 	/* Setup link and flow control */
756 	ret_val = mac->ops.setup_link(hw);
757 	if (ret_val)
758 		return ret_val;
759 
760 	/* Disable IBIST slave mode (far-end loopback) */
761 	ret_val =
762 	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
763 					    &kum_reg_data);
764 	if (!ret_val) {
765 		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
766 		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
767 						 E1000_KMRNCTRLSTA_INBAND_PARAM,
768 						 kum_reg_data);
769 		if (ret_val)
770 			e_dbg("Error disabling far-end loopback\n");
771 	} else {
772 		e_dbg("Error disabling far-end loopback\n");
773 	}
774 
775 	/* Set the transmit descriptor write-back policy */
776 	reg_data = er32(TXDCTL(0));
777 	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
778 		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
779 	ew32(TXDCTL(0), reg_data);
780 
781 	/* ...for both queues. */
782 	reg_data = er32(TXDCTL(1));
783 	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
784 		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
785 	ew32(TXDCTL(1), reg_data);
786 
787 	/* Enable retransmit on late collisions */
788 	reg_data = er32(TCTL);
789 	reg_data |= E1000_TCTL_RTLC;
790 	ew32(TCTL, reg_data);
791 
792 	/* Configure Gigabit Carry Extend Padding */
793 	reg_data = er32(TCTL_EXT);
794 	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
795 	reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
796 	ew32(TCTL_EXT, reg_data);
797 
798 	/* Configure Transmit Inter-Packet Gap */
799 	reg_data = er32(TIPG);
800 	reg_data &= ~E1000_TIPG_IPGT_MASK;
801 	reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
802 	ew32(TIPG, reg_data);
803 
804 	reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
805 	reg_data &= ~0x00100000;
806 	E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
807 
808 	/* default to true to enable the MDIC W/A */
809 	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
810 
811 	ret_val =
812 	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
813 					    E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
814 	if (!ret_val) {
815 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
816 		    E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
817 			hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
818 	}
819 
820 	/* Clear all of the statistics registers (clear on read).  It is
821 	 * important that we do this after we have tried to establish link
822 	 * because the symbol error count will increment wildly if there
823 	 * is no link.
824 	 */
825 	e1000_clear_hw_cntrs_80003es2lan(hw);
826 
827 	return ret_val;
828 }
829 
830 /**
831  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
832  *  @hw: pointer to the HW structure
833  *
834  *  Initializes required hardware-dependent bits needed for normal operation.
835  **/
836 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
837 {
838 	u32 reg;
839 
840 	/* Transmit Descriptor Control 0 */
841 	reg = er32(TXDCTL(0));
842 	reg |= BIT(22);
843 	ew32(TXDCTL(0), reg);
844 
845 	/* Transmit Descriptor Control 1 */
846 	reg = er32(TXDCTL(1));
847 	reg |= BIT(22);
848 	ew32(TXDCTL(1), reg);
849 
850 	/* Transmit Arbitration Control 0 */
851 	reg = er32(TARC(0));
852 	reg &= ~(0xF << 27);	/* 30:27 */
853 	if (hw->phy.media_type != e1000_media_type_copper)
854 		reg &= ~BIT(20);
855 	ew32(TARC(0), reg);
856 
857 	/* Transmit Arbitration Control 1 */
858 	reg = er32(TARC(1));
859 	if (er32(TCTL) & E1000_TCTL_MULR)
860 		reg &= ~BIT(28);
861 	else
862 		reg |= BIT(28);
863 	ew32(TARC(1), reg);
864 
865 	/* Disable IPv6 extension header parsing because some malformed
866 	 * IPv6 headers can hang the Rx.
867 	 */
868 	reg = er32(RFCTL);
869 	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
870 	ew32(RFCTL, reg);
871 }
872 
873 /**
874  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
875  *  @hw: pointer to the HW structure
876  *
877  *  Setup some GG82563 PHY registers for obtaining link
878  **/
879 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
880 {
881 	struct e1000_phy_info *phy = &hw->phy;
882 	s32 ret_val;
883 	u32 reg;
884 	u16 data;
885 
886 	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
887 	if (ret_val)
888 		return ret_val;
889 
890 	data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
891 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
892 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
893 
894 	ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
895 	if (ret_val)
896 		return ret_val;
897 
898 	/* Options:
899 	 *   MDI/MDI-X = 0 (default)
900 	 *   0 - Auto for all speeds
901 	 *   1 - MDI mode
902 	 *   2 - MDI-X mode
903 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
904 	 */
905 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
906 	if (ret_val)
907 		return ret_val;
908 
909 	data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
910 
911 	switch (phy->mdix) {
912 	case 1:
913 		data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
914 		break;
915 	case 2:
916 		data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
917 		break;
918 	case 0:
919 	default:
920 		data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
921 		break;
922 	}
923 
924 	/* Options:
925 	 *   disable_polarity_correction = 0 (default)
926 	 *       Automatic Correction for Reversed Cable Polarity
927 	 *   0 - Disabled
928 	 *   1 - Enabled
929 	 */
930 	data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
931 	if (phy->disable_polarity_correction)
932 		data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
933 
934 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
935 	if (ret_val)
936 		return ret_val;
937 
938 	/* SW Reset the PHY so all changes take effect */
939 	ret_val = hw->phy.ops.commit(hw);
940 	if (ret_val) {
941 		e_dbg("Error Resetting the PHY\n");
942 		return ret_val;
943 	}
944 
945 	/* Bypass Rx and Tx FIFO's */
946 	reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
947 	data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
948 		E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
949 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
950 	if (ret_val)
951 		return ret_val;
952 
953 	reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
954 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
955 	if (ret_val)
956 		return ret_val;
957 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
958 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
959 	if (ret_val)
960 		return ret_val;
961 
962 	ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
963 	if (ret_val)
964 		return ret_val;
965 
966 	data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
967 	ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
968 	if (ret_val)
969 		return ret_val;
970 
971 	reg = er32(CTRL_EXT);
972 	reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
973 	ew32(CTRL_EXT, reg);
974 
975 	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
976 	if (ret_val)
977 		return ret_val;
978 
979 	/* Do not init these registers when the HW is in IAMT mode, since the
980 	 * firmware will have already initialized them.  We only initialize
981 	 * them if the HW is not in IAMT mode.
982 	 */
983 	if (!hw->mac.ops.check_mng_mode(hw)) {
984 		/* Enable Electrical Idle on the PHY */
985 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
986 		ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
987 		if (ret_val)
988 			return ret_val;
989 
990 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
991 		if (ret_val)
992 			return ret_val;
993 
994 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
995 		ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
996 		if (ret_val)
997 			return ret_val;
998 	}
999 
1000 	/* Workaround: Disable padding in Kumeran interface in the MAC
1001 	 * and in the PHY to avoid CRC errors.
1002 	 */
1003 	ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1004 	if (ret_val)
1005 		return ret_val;
1006 
1007 	data |= GG82563_ICR_DIS_PADDING;
1008 	ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1009 	if (ret_val)
1010 		return ret_val;
1011 
1012 	return 0;
1013 }
1014 
1015 /**
1016  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1017  *  @hw: pointer to the HW structure
1018  *
1019  *  Essentially a wrapper for setting up all things "copper" related.
1020  *  This is a function pointer entry point called by the mac module.
1021  **/
1022 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1023 {
1024 	u32 ctrl;
1025 	s32 ret_val;
1026 	u16 reg_data;
1027 
1028 	ctrl = er32(CTRL);
1029 	ctrl |= E1000_CTRL_SLU;
1030 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1031 	ew32(CTRL, ctrl);
1032 
1033 	/* Set the mac to wait the maximum time between each
1034 	 * iteration and increase the max iterations when
1035 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1036 	 */
1037 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1038 						   0xFFFF);
1039 	if (ret_val)
1040 		return ret_val;
1041 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1042 						  &reg_data);
1043 	if (ret_val)
1044 		return ret_val;
1045 	reg_data |= 0x3F;
1046 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1047 						   reg_data);
1048 	if (ret_val)
1049 		return ret_val;
1050 	ret_val =
1051 	    e1000_read_kmrn_reg_80003es2lan(hw,
1052 					    E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1053 					    &reg_data);
1054 	if (ret_val)
1055 		return ret_val;
1056 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1057 	ret_val =
1058 	    e1000_write_kmrn_reg_80003es2lan(hw,
1059 					     E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1060 					     reg_data);
1061 	if (ret_val)
1062 		return ret_val;
1063 
1064 	ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1065 	if (ret_val)
1066 		return ret_val;
1067 
1068 	return e1000e_setup_copper_link(hw);
1069 }
1070 
1071 /**
1072  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1073  *  @hw: pointer to the HW structure
1074  *
1075  *  Configure the KMRN interface by applying last minute quirks for
1076  *  10/100 operation.
1077  **/
1078 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1079 {
1080 	s32 ret_val = 0;
1081 	u16 speed;
1082 	u16 duplex;
1083 
1084 	if (hw->phy.media_type == e1000_media_type_copper) {
1085 		ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1086 							     &duplex);
1087 		if (ret_val)
1088 			return ret_val;
1089 
1090 		if (speed == SPEED_1000)
1091 			ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1092 		else
1093 			ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1094 	}
1095 
1096 	return ret_val;
1097 }
1098 
1099 /**
1100  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1101  *  @hw: pointer to the HW structure
1102  *  @duplex: current duplex setting
1103  *
1104  *  Configure the KMRN interface by applying last minute quirks for
1105  *  10/100 operation.
1106  **/
1107 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1108 {
1109 	s32 ret_val;
1110 	u32 tipg;
1111 	u32 i = 0;
1112 	u16 reg_data, reg_data2;
1113 
1114 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1115 	ret_val =
1116 	    e1000_write_kmrn_reg_80003es2lan(hw,
1117 					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1118 					     reg_data);
1119 	if (ret_val)
1120 		return ret_val;
1121 
1122 	/* Configure Transmit Inter-Packet Gap */
1123 	tipg = er32(TIPG);
1124 	tipg &= ~E1000_TIPG_IPGT_MASK;
1125 	tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1126 	ew32(TIPG, tipg);
1127 
1128 	do {
1129 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1130 		if (ret_val)
1131 			return ret_val;
1132 
1133 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1134 		if (ret_val)
1135 			return ret_val;
1136 		i++;
1137 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1138 
1139 	if (duplex == HALF_DUPLEX)
1140 		reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1141 	else
1142 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1143 
1144 	return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1145 }
1146 
1147 /**
1148  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1149  *  @hw: pointer to the HW structure
1150  *
1151  *  Configure the KMRN interface by applying last minute quirks for
1152  *  gigabit operation.
1153  **/
1154 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1155 {
1156 	s32 ret_val;
1157 	u16 reg_data, reg_data2;
1158 	u32 tipg;
1159 	u32 i = 0;
1160 
1161 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1162 	ret_val =
1163 	    e1000_write_kmrn_reg_80003es2lan(hw,
1164 					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1165 					     reg_data);
1166 	if (ret_val)
1167 		return ret_val;
1168 
1169 	/* Configure Transmit Inter-Packet Gap */
1170 	tipg = er32(TIPG);
1171 	tipg &= ~E1000_TIPG_IPGT_MASK;
1172 	tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1173 	ew32(TIPG, tipg);
1174 
1175 	do {
1176 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1177 		if (ret_val)
1178 			return ret_val;
1179 
1180 		ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1181 		if (ret_val)
1182 			return ret_val;
1183 		i++;
1184 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1185 
1186 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1187 
1188 	return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1189 }
1190 
1191 /**
1192  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1193  *  @hw: pointer to the HW structure
1194  *  @offset: register offset to be read
1195  *  @data: pointer to the read data
1196  *
1197  *  Acquire semaphore, then read the PHY register at offset
1198  *  using the kumeran interface.  The information retrieved is stored in data.
1199  *  Release the semaphore before exiting.
1200  **/
1201 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1202 					   u16 *data)
1203 {
1204 	u32 kmrnctrlsta;
1205 	s32 ret_val;
1206 
1207 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1208 	if (ret_val)
1209 		return ret_val;
1210 
1211 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1212 		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1213 	ew32(KMRNCTRLSTA, kmrnctrlsta);
1214 	e1e_flush();
1215 
1216 	udelay(2);
1217 
1218 	kmrnctrlsta = er32(KMRNCTRLSTA);
1219 	*data = (u16)kmrnctrlsta;
1220 
1221 	e1000_release_mac_csr_80003es2lan(hw);
1222 
1223 	return ret_val;
1224 }
1225 
1226 /**
1227  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1228  *  @hw: pointer to the HW structure
1229  *  @offset: register offset to write to
1230  *  @data: data to write at register offset
1231  *
1232  *  Acquire semaphore, then write the data to PHY register
1233  *  at the offset using the kumeran interface.  Release semaphore
1234  *  before exiting.
1235  **/
1236 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1237 					    u16 data)
1238 {
1239 	u32 kmrnctrlsta;
1240 	s32 ret_val;
1241 
1242 	ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1243 	if (ret_val)
1244 		return ret_val;
1245 
1246 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1247 		       E1000_KMRNCTRLSTA_OFFSET) | data;
1248 	ew32(KMRNCTRLSTA, kmrnctrlsta);
1249 	e1e_flush();
1250 
1251 	udelay(2);
1252 
1253 	e1000_release_mac_csr_80003es2lan(hw);
1254 
1255 	return ret_val;
1256 }
1257 
1258 /**
1259  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1260  *  @hw: pointer to the HW structure
1261  **/
1262 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1263 {
1264 	s32 ret_val;
1265 
1266 	/* If there's an alternate MAC address place it in RAR0
1267 	 * so that it will override the Si installed default perm
1268 	 * address.
1269 	 */
1270 	ret_val = e1000_check_alt_mac_addr_generic(hw);
1271 	if (ret_val)
1272 		return ret_val;
1273 
1274 	return e1000_read_mac_addr_generic(hw);
1275 }
1276 
1277 /**
1278  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1279  * @hw: pointer to the HW structure
1280  *
1281  * In the case of a PHY power down to save power, or to turn off link during a
1282  * driver unload, or wake on lan is not enabled, remove the link.
1283  **/
1284 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1285 {
1286 	/* If the management interface is not enabled, then power down */
1287 	if (!(hw->mac.ops.check_mng_mode(hw) ||
1288 	      hw->phy.ops.check_reset_block(hw)))
1289 		e1000_power_down_phy_copper(hw);
1290 }
1291 
1292 /**
1293  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1294  *  @hw: pointer to the HW structure
1295  *
1296  *  Clears the hardware counters by reading the counter registers.
1297  **/
1298 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1299 {
1300 	e1000e_clear_hw_cntrs_base(hw);
1301 
1302 	er32(PRC64);
1303 	er32(PRC127);
1304 	er32(PRC255);
1305 	er32(PRC511);
1306 	er32(PRC1023);
1307 	er32(PRC1522);
1308 	er32(PTC64);
1309 	er32(PTC127);
1310 	er32(PTC255);
1311 	er32(PTC511);
1312 	er32(PTC1023);
1313 	er32(PTC1522);
1314 
1315 	er32(ALGNERRC);
1316 	er32(RXERRC);
1317 	er32(TNCRS);
1318 	er32(CEXTERR);
1319 	er32(TSCTC);
1320 	er32(TSCTFC);
1321 
1322 	er32(MGTPRC);
1323 	er32(MGTPDC);
1324 	er32(MGTPTC);
1325 
1326 	er32(IAC);
1327 	er32(ICRXOC);
1328 
1329 	er32(ICRXPTC);
1330 	er32(ICRXATC);
1331 	er32(ICTXPTC);
1332 	er32(ICTXATC);
1333 	er32(ICTXQEC);
1334 	er32(ICTXQMTC);
1335 	er32(ICRXDMTC);
1336 }
1337 
1338 static const struct e1000_mac_operations es2_mac_ops = {
1339 	.read_mac_addr		= e1000_read_mac_addr_80003es2lan,
1340 	.id_led_init		= e1000e_id_led_init_generic,
1341 	.blink_led		= e1000e_blink_led_generic,
1342 	.check_mng_mode		= e1000e_check_mng_mode_generic,
1343 	/* check_for_link dependent on media type */
1344 	.cleanup_led		= e1000e_cleanup_led_generic,
1345 	.clear_hw_cntrs		= e1000_clear_hw_cntrs_80003es2lan,
1346 	.get_bus_info		= e1000e_get_bus_info_pcie,
1347 	.set_lan_id		= e1000_set_lan_id_multi_port_pcie,
1348 	.get_link_up_info	= e1000_get_link_up_info_80003es2lan,
1349 	.led_on			= e1000e_led_on_generic,
1350 	.led_off		= e1000e_led_off_generic,
1351 	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
1352 	.write_vfta		= e1000_write_vfta_generic,
1353 	.clear_vfta		= e1000_clear_vfta_generic,
1354 	.reset_hw		= e1000_reset_hw_80003es2lan,
1355 	.init_hw		= e1000_init_hw_80003es2lan,
1356 	.setup_link		= e1000e_setup_link_generic,
1357 	/* setup_physical_interface dependent on media type */
1358 	.setup_led		= e1000e_setup_led_generic,
1359 	.config_collision_dist	= e1000e_config_collision_dist_generic,
1360 	.rar_set		= e1000e_rar_set_generic,
1361 	.rar_get_count		= e1000e_rar_get_count_generic,
1362 };
1363 
1364 static const struct e1000_phy_operations es2_phy_ops = {
1365 	.acquire		= e1000_acquire_phy_80003es2lan,
1366 	.check_polarity		= e1000_check_polarity_m88,
1367 	.check_reset_block	= e1000e_check_reset_block_generic,
1368 	.commit			= e1000e_phy_sw_reset,
1369 	.force_speed_duplex	= e1000_phy_force_speed_duplex_80003es2lan,
1370 	.get_cfg_done		= e1000_get_cfg_done_80003es2lan,
1371 	.get_cable_length	= e1000_get_cable_length_80003es2lan,
1372 	.get_info		= e1000e_get_phy_info_m88,
1373 	.read_reg		= e1000_read_phy_reg_gg82563_80003es2lan,
1374 	.release		= e1000_release_phy_80003es2lan,
1375 	.reset			= e1000e_phy_hw_reset_generic,
1376 	.set_d0_lplu_state	= NULL,
1377 	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1378 	.write_reg		= e1000_write_phy_reg_gg82563_80003es2lan,
1379 	.cfg_on_link_up		= e1000_cfg_on_link_up_80003es2lan,
1380 };
1381 
1382 static const struct e1000_nvm_operations es2_nvm_ops = {
1383 	.acquire		= e1000_acquire_nvm_80003es2lan,
1384 	.read			= e1000e_read_nvm_eerd,
1385 	.release		= e1000_release_nvm_80003es2lan,
1386 	.reload			= e1000e_reload_nvm_generic,
1387 	.update			= e1000e_update_nvm_checksum_generic,
1388 	.valid_led_default	= e1000e_valid_led_default,
1389 	.validate		= e1000e_validate_nvm_checksum_generic,
1390 	.write			= e1000_write_nvm_80003es2lan,
1391 };
1392 
1393 const struct e1000_info e1000_es2_info = {
1394 	.mac			= e1000_80003es2lan,
1395 	.flags			= FLAG_HAS_HW_VLAN_FILTER
1396 				  | FLAG_HAS_JUMBO_FRAMES
1397 				  | FLAG_HAS_WOL
1398 				  | FLAG_APME_IN_CTRL3
1399 				  | FLAG_HAS_CTRLEXT_ON_LOAD
1400 				  | FLAG_RX_NEEDS_RESTART /* errata */
1401 				  | FLAG_TARC_SET_BIT_ZERO /* errata */
1402 				  | FLAG_APME_CHECK_PORT_B
1403 				  | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1404 	.flags2			= FLAG2_DMA_BURST,
1405 	.pba			= 38,
1406 	.max_hw_frame_size	= DEFAULT_JUMBO,
1407 	.get_variants		= e1000_get_variants_80003es2lan,
1408 	.mac_ops		= &es2_mac_ops,
1409 	.phy_ops		= &es2_phy_ops,
1410 	.nvm_ops		= &es2_nvm_ops,
1411 };
1412