1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 */ 28 29 /* e1000_hw.c 30 * Shared functions for accessing and configuring the MAC 31 */ 32 33 #include "e1000.h" 34 35 static s32 e1000_check_downshift(struct e1000_hw *hw); 36 static s32 e1000_check_polarity(struct e1000_hw *hw, 37 e1000_rev_polarity *polarity); 38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 39 static void e1000_clear_vfta(struct e1000_hw *hw); 40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 41 bool link_up); 42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 46 u16 *max_length); 47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 48 static s32 e1000_id_led_init(struct e1000_hw *hw); 49 static void e1000_init_rx_addrs(struct e1000_hw *hw); 50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 51 struct e1000_phy_info *phy_info); 52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 53 struct e1000_phy_info *phy_info); 54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 55 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 57 static s32 e1000_set_phy_type(struct e1000_hw *hw); 58 static void e1000_phy_init_script(struct e1000_hw *hw); 59 static s32 e1000_setup_copper_link(struct e1000_hw *hw); 60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); 67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 70 u16 words, u16 *data); 71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 72 u16 words, u16 *data); 73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 78 u16 phy_data); 79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 80 u16 *phy_data); 81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 83 static void e1000_release_eeprom(struct e1000_hw *hw); 84 static void e1000_standby_eeprom(struct e1000_hw *hw); 85 static s32 e1000_set_vco_speed(struct e1000_hw *hw); 86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 87 static s32 e1000_set_phy_mode(struct e1000_hw *hw); 88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 89 u16 *data); 90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 91 u16 *data); 92 93 /* IGP cable length table */ 94 static const 95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 102 100, 103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 104 110, 110, 105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 106 120, 120 107 }; 108 109 static DEFINE_SPINLOCK(e1000_eeprom_lock); 110 static DEFINE_SPINLOCK(e1000_phy_lock); 111 112 /** 113 * e1000_set_phy_type - Set the phy type member in the hw struct. 114 * @hw: Struct containing variables accessed by shared code 115 */ 116 static s32 e1000_set_phy_type(struct e1000_hw *hw) 117 { 118 e_dbg("e1000_set_phy_type"); 119 120 if (hw->mac_type == e1000_undefined) 121 return -E1000_ERR_PHY_TYPE; 122 123 switch (hw->phy_id) { 124 case M88E1000_E_PHY_ID: 125 case M88E1000_I_PHY_ID: 126 case M88E1011_I_PHY_ID: 127 case M88E1111_I_PHY_ID: 128 case M88E1118_E_PHY_ID: 129 hw->phy_type = e1000_phy_m88; 130 break; 131 case IGP01E1000_I_PHY_ID: 132 if (hw->mac_type == e1000_82541 || 133 hw->mac_type == e1000_82541_rev_2 || 134 hw->mac_type == e1000_82547 || 135 hw->mac_type == e1000_82547_rev_2) 136 hw->phy_type = e1000_phy_igp; 137 break; 138 case RTL8211B_PHY_ID: 139 hw->phy_type = e1000_phy_8211; 140 break; 141 case RTL8201N_PHY_ID: 142 hw->phy_type = e1000_phy_8201; 143 break; 144 default: 145 /* Should never have loaded on this device */ 146 hw->phy_type = e1000_phy_undefined; 147 return -E1000_ERR_PHY_TYPE; 148 } 149 150 return E1000_SUCCESS; 151 } 152 153 /** 154 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY 155 * @hw: Struct containing variables accessed by shared code 156 */ 157 static void e1000_phy_init_script(struct e1000_hw *hw) 158 { 159 u32 ret_val; 160 u16 phy_saved_data; 161 162 e_dbg("e1000_phy_init_script"); 163 164 if (hw->phy_init_script) { 165 msleep(20); 166 167 /* Save off the current value of register 0x2F5B to be restored at 168 * the end of this routine. */ 169 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 170 171 /* Disabled the PHY transmitter */ 172 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 173 msleep(20); 174 175 e1000_write_phy_reg(hw, 0x0000, 0x0140); 176 msleep(5); 177 178 switch (hw->mac_type) { 179 case e1000_82541: 180 case e1000_82547: 181 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 182 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 183 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 184 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 185 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 186 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 187 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 188 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 189 e1000_write_phy_reg(hw, 0x2010, 0x0008); 190 break; 191 192 case e1000_82541_rev_2: 193 case e1000_82547_rev_2: 194 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 195 break; 196 default: 197 break; 198 } 199 200 e1000_write_phy_reg(hw, 0x0000, 0x3300); 201 msleep(20); 202 203 /* Now enable the transmitter */ 204 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 205 206 if (hw->mac_type == e1000_82547) { 207 u16 fused, fine, coarse; 208 209 /* Move to analog registers page */ 210 e1000_read_phy_reg(hw, 211 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 212 &fused); 213 214 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 215 e1000_read_phy_reg(hw, 216 IGP01E1000_ANALOG_FUSE_STATUS, 217 &fused); 218 219 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 220 coarse = 221 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 222 223 if (coarse > 224 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 225 coarse -= 226 IGP01E1000_ANALOG_FUSE_COARSE_10; 227 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 228 } else if (coarse == 229 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 230 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 231 232 fused = 233 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 234 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 235 (coarse & 236 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 237 238 e1000_write_phy_reg(hw, 239 IGP01E1000_ANALOG_FUSE_CONTROL, 240 fused); 241 e1000_write_phy_reg(hw, 242 IGP01E1000_ANALOG_FUSE_BYPASS, 243 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 244 } 245 } 246 } 247 } 248 249 /** 250 * e1000_set_mac_type - Set the mac type member in the hw struct. 251 * @hw: Struct containing variables accessed by shared code 252 */ 253 s32 e1000_set_mac_type(struct e1000_hw *hw) 254 { 255 e_dbg("e1000_set_mac_type"); 256 257 switch (hw->device_id) { 258 case E1000_DEV_ID_82542: 259 switch (hw->revision_id) { 260 case E1000_82542_2_0_REV_ID: 261 hw->mac_type = e1000_82542_rev2_0; 262 break; 263 case E1000_82542_2_1_REV_ID: 264 hw->mac_type = e1000_82542_rev2_1; 265 break; 266 default: 267 /* Invalid 82542 revision ID */ 268 return -E1000_ERR_MAC_TYPE; 269 } 270 break; 271 case E1000_DEV_ID_82543GC_FIBER: 272 case E1000_DEV_ID_82543GC_COPPER: 273 hw->mac_type = e1000_82543; 274 break; 275 case E1000_DEV_ID_82544EI_COPPER: 276 case E1000_DEV_ID_82544EI_FIBER: 277 case E1000_DEV_ID_82544GC_COPPER: 278 case E1000_DEV_ID_82544GC_LOM: 279 hw->mac_type = e1000_82544; 280 break; 281 case E1000_DEV_ID_82540EM: 282 case E1000_DEV_ID_82540EM_LOM: 283 case E1000_DEV_ID_82540EP: 284 case E1000_DEV_ID_82540EP_LOM: 285 case E1000_DEV_ID_82540EP_LP: 286 hw->mac_type = e1000_82540; 287 break; 288 case E1000_DEV_ID_82545EM_COPPER: 289 case E1000_DEV_ID_82545EM_FIBER: 290 hw->mac_type = e1000_82545; 291 break; 292 case E1000_DEV_ID_82545GM_COPPER: 293 case E1000_DEV_ID_82545GM_FIBER: 294 case E1000_DEV_ID_82545GM_SERDES: 295 hw->mac_type = e1000_82545_rev_3; 296 break; 297 case E1000_DEV_ID_82546EB_COPPER: 298 case E1000_DEV_ID_82546EB_FIBER: 299 case E1000_DEV_ID_82546EB_QUAD_COPPER: 300 hw->mac_type = e1000_82546; 301 break; 302 case E1000_DEV_ID_82546GB_COPPER: 303 case E1000_DEV_ID_82546GB_FIBER: 304 case E1000_DEV_ID_82546GB_SERDES: 305 case E1000_DEV_ID_82546GB_PCIE: 306 case E1000_DEV_ID_82546GB_QUAD_COPPER: 307 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 308 hw->mac_type = e1000_82546_rev_3; 309 break; 310 case E1000_DEV_ID_82541EI: 311 case E1000_DEV_ID_82541EI_MOBILE: 312 case E1000_DEV_ID_82541ER_LOM: 313 hw->mac_type = e1000_82541; 314 break; 315 case E1000_DEV_ID_82541ER: 316 case E1000_DEV_ID_82541GI: 317 case E1000_DEV_ID_82541GI_LF: 318 case E1000_DEV_ID_82541GI_MOBILE: 319 hw->mac_type = e1000_82541_rev_2; 320 break; 321 case E1000_DEV_ID_82547EI: 322 case E1000_DEV_ID_82547EI_MOBILE: 323 hw->mac_type = e1000_82547; 324 break; 325 case E1000_DEV_ID_82547GI: 326 hw->mac_type = e1000_82547_rev_2; 327 break; 328 case E1000_DEV_ID_INTEL_CE4100_GBE: 329 hw->mac_type = e1000_ce4100; 330 break; 331 default: 332 /* Should never have loaded on this device */ 333 return -E1000_ERR_MAC_TYPE; 334 } 335 336 switch (hw->mac_type) { 337 case e1000_82541: 338 case e1000_82547: 339 case e1000_82541_rev_2: 340 case e1000_82547_rev_2: 341 hw->asf_firmware_present = true; 342 break; 343 default: 344 break; 345 } 346 347 /* The 82543 chip does not count tx_carrier_errors properly in 348 * FD mode 349 */ 350 if (hw->mac_type == e1000_82543) 351 hw->bad_tx_carr_stats_fd = true; 352 353 if (hw->mac_type > e1000_82544) 354 hw->has_smbus = true; 355 356 return E1000_SUCCESS; 357 } 358 359 /** 360 * e1000_set_media_type - Set media type and TBI compatibility. 361 * @hw: Struct containing variables accessed by shared code 362 */ 363 void e1000_set_media_type(struct e1000_hw *hw) 364 { 365 u32 status; 366 367 e_dbg("e1000_set_media_type"); 368 369 if (hw->mac_type != e1000_82543) { 370 /* tbi_compatibility is only valid on 82543 */ 371 hw->tbi_compatibility_en = false; 372 } 373 374 switch (hw->device_id) { 375 case E1000_DEV_ID_82545GM_SERDES: 376 case E1000_DEV_ID_82546GB_SERDES: 377 hw->media_type = e1000_media_type_internal_serdes; 378 break; 379 default: 380 switch (hw->mac_type) { 381 case e1000_82542_rev2_0: 382 case e1000_82542_rev2_1: 383 hw->media_type = e1000_media_type_fiber; 384 break; 385 case e1000_ce4100: 386 hw->media_type = e1000_media_type_copper; 387 break; 388 default: 389 status = er32(STATUS); 390 if (status & E1000_STATUS_TBIMODE) { 391 hw->media_type = e1000_media_type_fiber; 392 /* tbi_compatibility not valid on fiber */ 393 hw->tbi_compatibility_en = false; 394 } else { 395 hw->media_type = e1000_media_type_copper; 396 } 397 break; 398 } 399 } 400 } 401 402 /** 403 * e1000_reset_hw - reset the hardware completely 404 * @hw: Struct containing variables accessed by shared code 405 * 406 * Reset the transmit and receive units; mask and clear all interrupts. 407 */ 408 s32 e1000_reset_hw(struct e1000_hw *hw) 409 { 410 u32 ctrl; 411 u32 ctrl_ext; 412 u32 icr; 413 u32 manc; 414 u32 led_ctrl; 415 s32 ret_val; 416 417 e_dbg("e1000_reset_hw"); 418 419 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 420 if (hw->mac_type == e1000_82542_rev2_0) { 421 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 422 e1000_pci_clear_mwi(hw); 423 } 424 425 /* Clear interrupt mask to stop board from generating interrupts */ 426 e_dbg("Masking off all interrupts\n"); 427 ew32(IMC, 0xffffffff); 428 429 /* Disable the Transmit and Receive units. Then delay to allow 430 * any pending transactions to complete before we hit the MAC with 431 * the global reset. 432 */ 433 ew32(RCTL, 0); 434 ew32(TCTL, E1000_TCTL_PSP); 435 E1000_WRITE_FLUSH(); 436 437 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 438 hw->tbi_compatibility_on = false; 439 440 /* Delay to allow any outstanding PCI transactions to complete before 441 * resetting the device 442 */ 443 msleep(10); 444 445 ctrl = er32(CTRL); 446 447 /* Must reset the PHY before resetting the MAC */ 448 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 449 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 450 E1000_WRITE_FLUSH(); 451 msleep(5); 452 } 453 454 /* Issue a global reset to the MAC. This will reset the chip's 455 * transmit, receive, DMA, and link units. It will not effect 456 * the current PCI configuration. The global reset bit is self- 457 * clearing, and should clear within a microsecond. 458 */ 459 e_dbg("Issuing a global reset to MAC\n"); 460 461 switch (hw->mac_type) { 462 case e1000_82544: 463 case e1000_82540: 464 case e1000_82545: 465 case e1000_82546: 466 case e1000_82541: 467 case e1000_82541_rev_2: 468 /* These controllers can't ack the 64-bit write when issuing the 469 * reset, so use IO-mapping as a workaround to issue the reset */ 470 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 471 break; 472 case e1000_82545_rev_3: 473 case e1000_82546_rev_3: 474 /* Reset is performed on a shadow of the control register */ 475 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 476 break; 477 case e1000_ce4100: 478 default: 479 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 480 break; 481 } 482 483 /* After MAC reset, force reload of EEPROM to restore power-on settings to 484 * device. Later controllers reload the EEPROM automatically, so just wait 485 * for reload to complete. 486 */ 487 switch (hw->mac_type) { 488 case e1000_82542_rev2_0: 489 case e1000_82542_rev2_1: 490 case e1000_82543: 491 case e1000_82544: 492 /* Wait for reset to complete */ 493 udelay(10); 494 ctrl_ext = er32(CTRL_EXT); 495 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 496 ew32(CTRL_EXT, ctrl_ext); 497 E1000_WRITE_FLUSH(); 498 /* Wait for EEPROM reload */ 499 msleep(2); 500 break; 501 case e1000_82541: 502 case e1000_82541_rev_2: 503 case e1000_82547: 504 case e1000_82547_rev_2: 505 /* Wait for EEPROM reload */ 506 msleep(20); 507 break; 508 default: 509 /* Auto read done will delay 5ms or poll based on mac type */ 510 ret_val = e1000_get_auto_rd_done(hw); 511 if (ret_val) 512 return ret_val; 513 break; 514 } 515 516 /* Disable HW ARPs on ASF enabled adapters */ 517 if (hw->mac_type >= e1000_82540) { 518 manc = er32(MANC); 519 manc &= ~(E1000_MANC_ARP_EN); 520 ew32(MANC, manc); 521 } 522 523 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 524 e1000_phy_init_script(hw); 525 526 /* Configure activity LED after PHY reset */ 527 led_ctrl = er32(LEDCTL); 528 led_ctrl &= IGP_ACTIVITY_LED_MASK; 529 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 530 ew32(LEDCTL, led_ctrl); 531 } 532 533 /* Clear interrupt mask to stop board from generating interrupts */ 534 e_dbg("Masking off all interrupts\n"); 535 ew32(IMC, 0xffffffff); 536 537 /* Clear any pending interrupt events. */ 538 icr = er32(ICR); 539 540 /* If MWI was previously enabled, reenable it. */ 541 if (hw->mac_type == e1000_82542_rev2_0) { 542 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 543 e1000_pci_set_mwi(hw); 544 } 545 546 return E1000_SUCCESS; 547 } 548 549 /** 550 * e1000_init_hw - Performs basic configuration of the adapter. 551 * @hw: Struct containing variables accessed by shared code 552 * 553 * Assumes that the controller has previously been reset and is in a 554 * post-reset uninitialized state. Initializes the receive address registers, 555 * multicast table, and VLAN filter table. Calls routines to setup link 556 * configuration and flow control settings. Clears all on-chip counters. Leaves 557 * the transmit and receive units disabled and uninitialized. 558 */ 559 s32 e1000_init_hw(struct e1000_hw *hw) 560 { 561 u32 ctrl; 562 u32 i; 563 s32 ret_val; 564 u32 mta_size; 565 u32 ctrl_ext; 566 567 e_dbg("e1000_init_hw"); 568 569 /* Initialize Identification LED */ 570 ret_val = e1000_id_led_init(hw); 571 if (ret_val) { 572 e_dbg("Error Initializing Identification LED\n"); 573 return ret_val; 574 } 575 576 /* Set the media type and TBI compatibility */ 577 e1000_set_media_type(hw); 578 579 /* Disabling VLAN filtering. */ 580 e_dbg("Initializing the IEEE VLAN\n"); 581 if (hw->mac_type < e1000_82545_rev_3) 582 ew32(VET, 0); 583 e1000_clear_vfta(hw); 584 585 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 586 if (hw->mac_type == e1000_82542_rev2_0) { 587 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 588 e1000_pci_clear_mwi(hw); 589 ew32(RCTL, E1000_RCTL_RST); 590 E1000_WRITE_FLUSH(); 591 msleep(5); 592 } 593 594 /* Setup the receive address. This involves initializing all of the Receive 595 * Address Registers (RARs 0 - 15). 596 */ 597 e1000_init_rx_addrs(hw); 598 599 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 600 if (hw->mac_type == e1000_82542_rev2_0) { 601 ew32(RCTL, 0); 602 E1000_WRITE_FLUSH(); 603 msleep(1); 604 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 605 e1000_pci_set_mwi(hw); 606 } 607 608 /* Zero out the Multicast HASH table */ 609 e_dbg("Zeroing the MTA\n"); 610 mta_size = E1000_MC_TBL_SIZE; 611 for (i = 0; i < mta_size; i++) { 612 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 613 /* use write flush to prevent Memory Write Block (MWB) from 614 * occurring when accessing our register space */ 615 E1000_WRITE_FLUSH(); 616 } 617 618 /* Set the PCI priority bit correctly in the CTRL register. This 619 * determines if the adapter gives priority to receives, or if it 620 * gives equal priority to transmits and receives. Valid only on 621 * 82542 and 82543 silicon. 622 */ 623 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 624 ctrl = er32(CTRL); 625 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 626 } 627 628 switch (hw->mac_type) { 629 case e1000_82545_rev_3: 630 case e1000_82546_rev_3: 631 break; 632 default: 633 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 634 if (hw->bus_type == e1000_bus_type_pcix 635 && e1000_pcix_get_mmrbc(hw) > 2048) 636 e1000_pcix_set_mmrbc(hw, 2048); 637 break; 638 } 639 640 /* Call a subroutine to configure the link and setup flow control. */ 641 ret_val = e1000_setup_link(hw); 642 643 /* Set the transmit descriptor write-back policy */ 644 if (hw->mac_type > e1000_82544) { 645 ctrl = er32(TXDCTL); 646 ctrl = 647 (ctrl & ~E1000_TXDCTL_WTHRESH) | 648 E1000_TXDCTL_FULL_TX_DESC_WB; 649 ew32(TXDCTL, ctrl); 650 } 651 652 /* Clear all of the statistics registers (clear on read). It is 653 * important that we do this after we have tried to establish link 654 * because the symbol error count will increment wildly if there 655 * is no link. 656 */ 657 e1000_clear_hw_cntrs(hw); 658 659 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 660 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 661 ctrl_ext = er32(CTRL_EXT); 662 /* Relaxed ordering must be disabled to avoid a parity 663 * error crash in a PCI slot. */ 664 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 665 ew32(CTRL_EXT, ctrl_ext); 666 } 667 668 return ret_val; 669 } 670 671 /** 672 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. 673 * @hw: Struct containing variables accessed by shared code. 674 */ 675 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 676 { 677 u16 eeprom_data; 678 s32 ret_val; 679 680 e_dbg("e1000_adjust_serdes_amplitude"); 681 682 if (hw->media_type != e1000_media_type_internal_serdes) 683 return E1000_SUCCESS; 684 685 switch (hw->mac_type) { 686 case e1000_82545_rev_3: 687 case e1000_82546_rev_3: 688 break; 689 default: 690 return E1000_SUCCESS; 691 } 692 693 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 694 &eeprom_data); 695 if (ret_val) { 696 return ret_val; 697 } 698 699 if (eeprom_data != EEPROM_RESERVED_WORD) { 700 /* Adjust SERDES output amplitude only. */ 701 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 702 ret_val = 703 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 704 if (ret_val) 705 return ret_val; 706 } 707 708 return E1000_SUCCESS; 709 } 710 711 /** 712 * e1000_setup_link - Configures flow control and link settings. 713 * @hw: Struct containing variables accessed by shared code 714 * 715 * Determines which flow control settings to use. Calls the appropriate media- 716 * specific link configuration function. Configures the flow control settings. 717 * Assuming the adapter has a valid link partner, a valid link should be 718 * established. Assumes the hardware has previously been reset and the 719 * transmitter and receiver are not enabled. 720 */ 721 s32 e1000_setup_link(struct e1000_hw *hw) 722 { 723 u32 ctrl_ext; 724 s32 ret_val; 725 u16 eeprom_data; 726 727 e_dbg("e1000_setup_link"); 728 729 /* Read and store word 0x0F of the EEPROM. This word contains bits 730 * that determine the hardware's default PAUSE (flow control) mode, 731 * a bit that determines whether the HW defaults to enabling or 732 * disabling auto-negotiation, and the direction of the 733 * SW defined pins. If there is no SW over-ride of the flow 734 * control setting, then the variable hw->fc will 735 * be initialized based on a value in the EEPROM. 736 */ 737 if (hw->fc == E1000_FC_DEFAULT) { 738 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 739 1, &eeprom_data); 740 if (ret_val) { 741 e_dbg("EEPROM Read Error\n"); 742 return -E1000_ERR_EEPROM; 743 } 744 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 745 hw->fc = E1000_FC_NONE; 746 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 747 EEPROM_WORD0F_ASM_DIR) 748 hw->fc = E1000_FC_TX_PAUSE; 749 else 750 hw->fc = E1000_FC_FULL; 751 } 752 753 /* We want to save off the original Flow Control configuration just 754 * in case we get disconnected and then reconnected into a different 755 * hub or switch with different Flow Control capabilities. 756 */ 757 if (hw->mac_type == e1000_82542_rev2_0) 758 hw->fc &= (~E1000_FC_TX_PAUSE); 759 760 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 761 hw->fc &= (~E1000_FC_RX_PAUSE); 762 763 hw->original_fc = hw->fc; 764 765 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); 766 767 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 768 * polarity value for the SW controlled pins, and setup the 769 * Extended Device Control reg with that info. 770 * This is needed because one of the SW controlled pins is used for 771 * signal detection. So this should be done before e1000_setup_pcs_link() 772 * or e1000_phy_setup() is called. 773 */ 774 if (hw->mac_type == e1000_82543) { 775 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 776 1, &eeprom_data); 777 if (ret_val) { 778 e_dbg("EEPROM Read Error\n"); 779 return -E1000_ERR_EEPROM; 780 } 781 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 782 SWDPIO__EXT_SHIFT); 783 ew32(CTRL_EXT, ctrl_ext); 784 } 785 786 /* Call the necessary subroutine to configure the link. */ 787 ret_val = (hw->media_type == e1000_media_type_copper) ? 788 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); 789 790 /* Initialize the flow control address, type, and PAUSE timer 791 * registers to their default values. This is done even if flow 792 * control is disabled, because it does not hurt anything to 793 * initialize these registers. 794 */ 795 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 796 797 ew32(FCT, FLOW_CONTROL_TYPE); 798 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 799 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 800 801 ew32(FCTTV, hw->fc_pause_time); 802 803 /* Set the flow control receive threshold registers. Normally, 804 * these registers will be set to a default threshold that may be 805 * adjusted later by the driver's runtime code. However, if the 806 * ability to transmit pause frames in not enabled, then these 807 * registers will be set to 0. 808 */ 809 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 810 ew32(FCRTL, 0); 811 ew32(FCRTH, 0); 812 } else { 813 /* We need to set up the Receive Threshold high and low water marks 814 * as well as (optionally) enabling the transmission of XON frames. 815 */ 816 if (hw->fc_send_xon) { 817 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 818 ew32(FCRTH, hw->fc_high_water); 819 } else { 820 ew32(FCRTL, hw->fc_low_water); 821 ew32(FCRTH, hw->fc_high_water); 822 } 823 } 824 return ret_val; 825 } 826 827 /** 828 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link 829 * @hw: Struct containing variables accessed by shared code 830 * 831 * Manipulates Physical Coding Sublayer functions in order to configure 832 * link. Assumes the hardware has been previously reset and the transmitter 833 * and receiver are not enabled. 834 */ 835 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 836 { 837 u32 ctrl; 838 u32 status; 839 u32 txcw = 0; 840 u32 i; 841 u32 signal = 0; 842 s32 ret_val; 843 844 e_dbg("e1000_setup_fiber_serdes_link"); 845 846 /* On adapters with a MAC newer than 82544, SWDP 1 will be 847 * set when the optics detect a signal. On older adapters, it will be 848 * cleared when there is a signal. This applies to fiber media only. 849 * If we're on serdes media, adjust the output amplitude to value 850 * set in the EEPROM. 851 */ 852 ctrl = er32(CTRL); 853 if (hw->media_type == e1000_media_type_fiber) 854 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 855 856 ret_val = e1000_adjust_serdes_amplitude(hw); 857 if (ret_val) 858 return ret_val; 859 860 /* Take the link out of reset */ 861 ctrl &= ~(E1000_CTRL_LRST); 862 863 /* Adjust VCO speed to improve BER performance */ 864 ret_val = e1000_set_vco_speed(hw); 865 if (ret_val) 866 return ret_val; 867 868 e1000_config_collision_dist(hw); 869 870 /* Check for a software override of the flow control settings, and setup 871 * the device accordingly. If auto-negotiation is enabled, then software 872 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 873 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 874 * auto-negotiation is disabled, then software will have to manually 875 * configure the two flow control enable bits in the CTRL register. 876 * 877 * The possible values of the "fc" parameter are: 878 * 0: Flow control is completely disabled 879 * 1: Rx flow control is enabled (we can receive pause frames, but 880 * not send pause frames). 881 * 2: Tx flow control is enabled (we can send pause frames but we do 882 * not support receiving pause frames). 883 * 3: Both Rx and TX flow control (symmetric) are enabled. 884 */ 885 switch (hw->fc) { 886 case E1000_FC_NONE: 887 /* Flow control is completely disabled by a software over-ride. */ 888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 889 break; 890 case E1000_FC_RX_PAUSE: 891 /* RX Flow control is enabled and TX Flow control is disabled by a 892 * software over-ride. Since there really isn't a way to advertise 893 * that we are capable of RX Pause ONLY, we will advertise that we 894 * support both symmetric and asymmetric RX PAUSE. Later, we will 895 * disable the adapter's ability to send PAUSE frames. 896 */ 897 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 898 break; 899 case E1000_FC_TX_PAUSE: 900 /* TX Flow control is enabled, and RX Flow control is disabled, by a 901 * software over-ride. 902 */ 903 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 904 break; 905 case E1000_FC_FULL: 906 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 907 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 908 break; 909 default: 910 e_dbg("Flow control param set incorrectly\n"); 911 return -E1000_ERR_CONFIG; 912 break; 913 } 914 915 /* Since auto-negotiation is enabled, take the link out of reset (the link 916 * will be in reset, because we previously reset the chip). This will 917 * restart auto-negotiation. If auto-negotiation is successful then the 918 * link-up status bit will be set and the flow control enable bits (RFCE 919 * and TFCE) will be set according to their negotiated value. 920 */ 921 e_dbg("Auto-negotiation enabled\n"); 922 923 ew32(TXCW, txcw); 924 ew32(CTRL, ctrl); 925 E1000_WRITE_FLUSH(); 926 927 hw->txcw = txcw; 928 msleep(1); 929 930 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 931 * indication in the Device Status Register. Time-out if a link isn't 932 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 933 * less than 500 milliseconds even if the other end is doing it in SW). 934 * For internal serdes, we just assume a signal is present, then poll. 935 */ 936 if (hw->media_type == e1000_media_type_internal_serdes || 937 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 938 e_dbg("Looking for Link\n"); 939 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 940 msleep(10); 941 status = er32(STATUS); 942 if (status & E1000_STATUS_LU) 943 break; 944 } 945 if (i == (LINK_UP_TIMEOUT / 10)) { 946 e_dbg("Never got a valid link from auto-neg!!!\n"); 947 hw->autoneg_failed = 1; 948 /* AutoNeg failed to achieve a link, so we'll call 949 * e1000_check_for_link. This routine will force the link up if 950 * we detect a signal. This will allow us to communicate with 951 * non-autonegotiating link partners. 952 */ 953 ret_val = e1000_check_for_link(hw); 954 if (ret_val) { 955 e_dbg("Error while checking for link\n"); 956 return ret_val; 957 } 958 hw->autoneg_failed = 0; 959 } else { 960 hw->autoneg_failed = 0; 961 e_dbg("Valid Link Found\n"); 962 } 963 } else { 964 e_dbg("No Signal Detected\n"); 965 } 966 return E1000_SUCCESS; 967 } 968 969 /** 970 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. 971 * @hw: Struct containing variables accessed by shared code 972 * 973 * Commits changes to PHY configuration by calling e1000_phy_reset(). 974 */ 975 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) 976 { 977 s32 ret_val; 978 979 /* SW reset the PHY so all changes take effect */ 980 ret_val = e1000_phy_reset(hw); 981 if (ret_val) { 982 e_dbg("Error Resetting the PHY\n"); 983 return ret_val; 984 } 985 986 return E1000_SUCCESS; 987 } 988 989 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) 990 { 991 s32 ret_val; 992 u32 ctrl_aux; 993 994 switch (hw->phy_type) { 995 case e1000_phy_8211: 996 ret_val = e1000_copper_link_rtl_setup(hw); 997 if (ret_val) { 998 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 999 return ret_val; 1000 } 1001 break; 1002 case e1000_phy_8201: 1003 /* Set RMII mode */ 1004 ctrl_aux = er32(CTL_AUX); 1005 ctrl_aux |= E1000_CTL_AUX_RMII; 1006 ew32(CTL_AUX, ctrl_aux); 1007 E1000_WRITE_FLUSH(); 1008 1009 /* Disable the J/K bits required for receive */ 1010 ctrl_aux = er32(CTL_AUX); 1011 ctrl_aux |= 0x4; 1012 ctrl_aux &= ~0x2; 1013 ew32(CTL_AUX, ctrl_aux); 1014 E1000_WRITE_FLUSH(); 1015 ret_val = e1000_copper_link_rtl_setup(hw); 1016 1017 if (ret_val) { 1018 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 1019 return ret_val; 1020 } 1021 break; 1022 default: 1023 e_dbg("Error Resetting the PHY\n"); 1024 return E1000_ERR_PHY_TYPE; 1025 } 1026 1027 return E1000_SUCCESS; 1028 } 1029 1030 /** 1031 * e1000_copper_link_preconfig - early configuration for copper 1032 * @hw: Struct containing variables accessed by shared code 1033 * 1034 * Make sure we have a valid PHY and change PHY mode before link setup. 1035 */ 1036 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 1037 { 1038 u32 ctrl; 1039 s32 ret_val; 1040 u16 phy_data; 1041 1042 e_dbg("e1000_copper_link_preconfig"); 1043 1044 ctrl = er32(CTRL); 1045 /* With 82543, we need to force speed and duplex on the MAC equal to what 1046 * the PHY speed and duplex configuration is. In addition, we need to 1047 * perform a hardware reset on the PHY to take it out of reset. 1048 */ 1049 if (hw->mac_type > e1000_82543) { 1050 ctrl |= E1000_CTRL_SLU; 1051 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1052 ew32(CTRL, ctrl); 1053 } else { 1054 ctrl |= 1055 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1056 ew32(CTRL, ctrl); 1057 ret_val = e1000_phy_hw_reset(hw); 1058 if (ret_val) 1059 return ret_val; 1060 } 1061 1062 /* Make sure we have a valid PHY */ 1063 ret_val = e1000_detect_gig_phy(hw); 1064 if (ret_val) { 1065 e_dbg("Error, did not detect valid phy.\n"); 1066 return ret_val; 1067 } 1068 e_dbg("Phy ID = %x\n", hw->phy_id); 1069 1070 /* Set PHY to class A mode (if necessary) */ 1071 ret_val = e1000_set_phy_mode(hw); 1072 if (ret_val) 1073 return ret_val; 1074 1075 if ((hw->mac_type == e1000_82545_rev_3) || 1076 (hw->mac_type == e1000_82546_rev_3)) { 1077 ret_val = 1078 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1079 phy_data |= 0x00000008; 1080 ret_val = 1081 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1082 } 1083 1084 if (hw->mac_type <= e1000_82543 || 1085 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1086 hw->mac_type == e1000_82541_rev_2 1087 || hw->mac_type == e1000_82547_rev_2) 1088 hw->phy_reset_disable = false; 1089 1090 return E1000_SUCCESS; 1091 } 1092 1093 /** 1094 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. 1095 * @hw: Struct containing variables accessed by shared code 1096 */ 1097 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1098 { 1099 u32 led_ctrl; 1100 s32 ret_val; 1101 u16 phy_data; 1102 1103 e_dbg("e1000_copper_link_igp_setup"); 1104 1105 if (hw->phy_reset_disable) 1106 return E1000_SUCCESS; 1107 1108 ret_val = e1000_phy_reset(hw); 1109 if (ret_val) { 1110 e_dbg("Error Resetting the PHY\n"); 1111 return ret_val; 1112 } 1113 1114 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1115 msleep(15); 1116 /* Configure activity LED after PHY reset */ 1117 led_ctrl = er32(LEDCTL); 1118 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1119 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1120 ew32(LEDCTL, led_ctrl); 1121 1122 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1123 if (hw->phy_type == e1000_phy_igp) { 1124 /* disable lplu d3 during driver init */ 1125 ret_val = e1000_set_d3_lplu_state(hw, false); 1126 if (ret_val) { 1127 e_dbg("Error Disabling LPLU D3\n"); 1128 return ret_val; 1129 } 1130 } 1131 1132 /* Configure mdi-mdix settings */ 1133 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1134 if (ret_val) 1135 return ret_val; 1136 1137 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1138 hw->dsp_config_state = e1000_dsp_config_disabled; 1139 /* Force MDI for earlier revs of the IGP PHY */ 1140 phy_data &= 1141 ~(IGP01E1000_PSCR_AUTO_MDIX | 1142 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1143 hw->mdix = 1; 1144 1145 } else { 1146 hw->dsp_config_state = e1000_dsp_config_enabled; 1147 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1148 1149 switch (hw->mdix) { 1150 case 1: 1151 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1152 break; 1153 case 2: 1154 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1155 break; 1156 case 0: 1157 default: 1158 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1159 break; 1160 } 1161 } 1162 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1163 if (ret_val) 1164 return ret_val; 1165 1166 /* set auto-master slave resolution settings */ 1167 if (hw->autoneg) { 1168 e1000_ms_type phy_ms_setting = hw->master_slave; 1169 1170 if (hw->ffe_config_state == e1000_ffe_config_active) 1171 hw->ffe_config_state = e1000_ffe_config_enabled; 1172 1173 if (hw->dsp_config_state == e1000_dsp_config_activated) 1174 hw->dsp_config_state = e1000_dsp_config_enabled; 1175 1176 /* when autonegotiation advertisement is only 1000Mbps then we 1177 * should disable SmartSpeed and enable Auto MasterSlave 1178 * resolution as hardware default. */ 1179 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1180 /* Disable SmartSpeed */ 1181 ret_val = 1182 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1183 &phy_data); 1184 if (ret_val) 1185 return ret_val; 1186 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1187 ret_val = 1188 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1189 phy_data); 1190 if (ret_val) 1191 return ret_val; 1192 /* Set auto Master/Slave resolution process */ 1193 ret_val = 1194 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1195 if (ret_val) 1196 return ret_val; 1197 phy_data &= ~CR_1000T_MS_ENABLE; 1198 ret_val = 1199 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1200 if (ret_val) 1201 return ret_val; 1202 } 1203 1204 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1205 if (ret_val) 1206 return ret_val; 1207 1208 /* load defaults for future use */ 1209 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1210 ((phy_data & CR_1000T_MS_VALUE) ? 1211 e1000_ms_force_master : 1212 e1000_ms_force_slave) : e1000_ms_auto; 1213 1214 switch (phy_ms_setting) { 1215 case e1000_ms_force_master: 1216 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1217 break; 1218 case e1000_ms_force_slave: 1219 phy_data |= CR_1000T_MS_ENABLE; 1220 phy_data &= ~(CR_1000T_MS_VALUE); 1221 break; 1222 case e1000_ms_auto: 1223 phy_data &= ~CR_1000T_MS_ENABLE; 1224 default: 1225 break; 1226 } 1227 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1228 if (ret_val) 1229 return ret_val; 1230 } 1231 1232 return E1000_SUCCESS; 1233 } 1234 1235 /** 1236 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. 1237 * @hw: Struct containing variables accessed by shared code 1238 */ 1239 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1240 { 1241 s32 ret_val; 1242 u16 phy_data; 1243 1244 e_dbg("e1000_copper_link_mgp_setup"); 1245 1246 if (hw->phy_reset_disable) 1247 return E1000_SUCCESS; 1248 1249 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1250 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1251 if (ret_val) 1252 return ret_val; 1253 1254 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1255 1256 /* Options: 1257 * MDI/MDI-X = 0 (default) 1258 * 0 - Auto for all speeds 1259 * 1 - MDI mode 1260 * 2 - MDI-X mode 1261 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1262 */ 1263 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1264 1265 switch (hw->mdix) { 1266 case 1: 1267 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1268 break; 1269 case 2: 1270 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1271 break; 1272 case 3: 1273 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1274 break; 1275 case 0: 1276 default: 1277 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1278 break; 1279 } 1280 1281 /* Options: 1282 * disable_polarity_correction = 0 (default) 1283 * Automatic Correction for Reversed Cable Polarity 1284 * 0 - Disabled 1285 * 1 - Enabled 1286 */ 1287 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1288 if (hw->disable_polarity_correction == 1) 1289 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1290 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1291 if (ret_val) 1292 return ret_val; 1293 1294 if (hw->phy_revision < M88E1011_I_REV_4) { 1295 /* Force TX_CLK in the Extended PHY Specific Control Register 1296 * to 25MHz clock. 1297 */ 1298 ret_val = 1299 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1300 &phy_data); 1301 if (ret_val) 1302 return ret_val; 1303 1304 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1305 1306 if ((hw->phy_revision == E1000_REVISION_2) && 1307 (hw->phy_id == M88E1111_I_PHY_ID)) { 1308 /* Vidalia Phy, set the downshift counter to 5x */ 1309 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1310 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1311 ret_val = e1000_write_phy_reg(hw, 1312 M88E1000_EXT_PHY_SPEC_CTRL, 1313 phy_data); 1314 if (ret_val) 1315 return ret_val; 1316 } else { 1317 /* Configure Master and Slave downshift values */ 1318 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1319 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1320 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1321 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1322 ret_val = e1000_write_phy_reg(hw, 1323 M88E1000_EXT_PHY_SPEC_CTRL, 1324 phy_data); 1325 if (ret_val) 1326 return ret_val; 1327 } 1328 } 1329 1330 /* SW Reset the PHY so all changes take effect */ 1331 ret_val = e1000_phy_reset(hw); 1332 if (ret_val) { 1333 e_dbg("Error Resetting the PHY\n"); 1334 return ret_val; 1335 } 1336 1337 return E1000_SUCCESS; 1338 } 1339 1340 /** 1341 * e1000_copper_link_autoneg - setup auto-neg 1342 * @hw: Struct containing variables accessed by shared code 1343 * 1344 * Setup auto-negotiation and flow control advertisements, 1345 * and then perform auto-negotiation. 1346 */ 1347 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1348 { 1349 s32 ret_val; 1350 u16 phy_data; 1351 1352 e_dbg("e1000_copper_link_autoneg"); 1353 1354 /* Perform some bounds checking on the hw->autoneg_advertised 1355 * parameter. If this variable is zero, then set it to the default. 1356 */ 1357 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1358 1359 /* If autoneg_advertised is zero, we assume it was not defaulted 1360 * by the calling code so we set to advertise full capability. 1361 */ 1362 if (hw->autoneg_advertised == 0) 1363 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1364 1365 /* IFE/RTL8201N PHY only supports 10/100 */ 1366 if (hw->phy_type == e1000_phy_8201) 1367 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1368 1369 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1370 ret_val = e1000_phy_setup_autoneg(hw); 1371 if (ret_val) { 1372 e_dbg("Error Setting up Auto-Negotiation\n"); 1373 return ret_val; 1374 } 1375 e_dbg("Restarting Auto-Neg\n"); 1376 1377 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1378 * the Auto Neg Restart bit in the PHY control register. 1379 */ 1380 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1381 if (ret_val) 1382 return ret_val; 1383 1384 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1385 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1386 if (ret_val) 1387 return ret_val; 1388 1389 /* Does the user want to wait for Auto-Neg to complete here, or 1390 * check at a later time (for example, callback routine). 1391 */ 1392 if (hw->wait_autoneg_complete) { 1393 ret_val = e1000_wait_autoneg(hw); 1394 if (ret_val) { 1395 e_dbg 1396 ("Error while waiting for autoneg to complete\n"); 1397 return ret_val; 1398 } 1399 } 1400 1401 hw->get_link_status = true; 1402 1403 return E1000_SUCCESS; 1404 } 1405 1406 /** 1407 * e1000_copper_link_postconfig - post link setup 1408 * @hw: Struct containing variables accessed by shared code 1409 * 1410 * Config the MAC and the PHY after link is up. 1411 * 1) Set up the MAC to the current PHY speed/duplex 1412 * if we are on 82543. If we 1413 * are on newer silicon, we only need to configure 1414 * collision distance in the Transmit Control Register. 1415 * 2) Set up flow control on the MAC to that established with 1416 * the link partner. 1417 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1418 */ 1419 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1420 { 1421 s32 ret_val; 1422 e_dbg("e1000_copper_link_postconfig"); 1423 1424 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { 1425 e1000_config_collision_dist(hw); 1426 } else { 1427 ret_val = e1000_config_mac_to_phy(hw); 1428 if (ret_val) { 1429 e_dbg("Error configuring MAC to PHY settings\n"); 1430 return ret_val; 1431 } 1432 } 1433 ret_val = e1000_config_fc_after_link_up(hw); 1434 if (ret_val) { 1435 e_dbg("Error Configuring Flow Control\n"); 1436 return ret_val; 1437 } 1438 1439 /* Config DSP to improve Giga link quality */ 1440 if (hw->phy_type == e1000_phy_igp) { 1441 ret_val = e1000_config_dsp_after_link_change(hw, true); 1442 if (ret_val) { 1443 e_dbg("Error Configuring DSP after link up\n"); 1444 return ret_val; 1445 } 1446 } 1447 1448 return E1000_SUCCESS; 1449 } 1450 1451 /** 1452 * e1000_setup_copper_link - phy/speed/duplex setting 1453 * @hw: Struct containing variables accessed by shared code 1454 * 1455 * Detects which PHY is present and sets up the speed and duplex 1456 */ 1457 static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1458 { 1459 s32 ret_val; 1460 u16 i; 1461 u16 phy_data; 1462 1463 e_dbg("e1000_setup_copper_link"); 1464 1465 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1466 ret_val = e1000_copper_link_preconfig(hw); 1467 if (ret_val) 1468 return ret_val; 1469 1470 if (hw->phy_type == e1000_phy_igp) { 1471 ret_val = e1000_copper_link_igp_setup(hw); 1472 if (ret_val) 1473 return ret_val; 1474 } else if (hw->phy_type == e1000_phy_m88) { 1475 ret_val = e1000_copper_link_mgp_setup(hw); 1476 if (ret_val) 1477 return ret_val; 1478 } else { 1479 ret_val = gbe_dhg_phy_setup(hw); 1480 if (ret_val) { 1481 e_dbg("gbe_dhg_phy_setup failed!\n"); 1482 return ret_val; 1483 } 1484 } 1485 1486 if (hw->autoneg) { 1487 /* Setup autoneg and flow control advertisement 1488 * and perform autonegotiation */ 1489 ret_val = e1000_copper_link_autoneg(hw); 1490 if (ret_val) 1491 return ret_val; 1492 } else { 1493 /* PHY will be set to 10H, 10F, 100H,or 100F 1494 * depending on value from forced_speed_duplex. */ 1495 e_dbg("Forcing speed and duplex\n"); 1496 ret_val = e1000_phy_force_speed_duplex(hw); 1497 if (ret_val) { 1498 e_dbg("Error Forcing Speed and Duplex\n"); 1499 return ret_val; 1500 } 1501 } 1502 1503 /* Check link status. Wait up to 100 microseconds for link to become 1504 * valid. 1505 */ 1506 for (i = 0; i < 10; i++) { 1507 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1508 if (ret_val) 1509 return ret_val; 1510 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1511 if (ret_val) 1512 return ret_val; 1513 1514 if (phy_data & MII_SR_LINK_STATUS) { 1515 /* Config the MAC and PHY after link is up */ 1516 ret_val = e1000_copper_link_postconfig(hw); 1517 if (ret_val) 1518 return ret_val; 1519 1520 e_dbg("Valid link established!!!\n"); 1521 return E1000_SUCCESS; 1522 } 1523 udelay(10); 1524 } 1525 1526 e_dbg("Unable to establish link!!!\n"); 1527 return E1000_SUCCESS; 1528 } 1529 1530 /** 1531 * e1000_phy_setup_autoneg - phy settings 1532 * @hw: Struct containing variables accessed by shared code 1533 * 1534 * Configures PHY autoneg and flow control advertisement settings 1535 */ 1536 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1537 { 1538 s32 ret_val; 1539 u16 mii_autoneg_adv_reg; 1540 u16 mii_1000t_ctrl_reg; 1541 1542 e_dbg("e1000_phy_setup_autoneg"); 1543 1544 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1545 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1546 if (ret_val) 1547 return ret_val; 1548 1549 /* Read the MII 1000Base-T Control Register (Address 9). */ 1550 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1551 if (ret_val) 1552 return ret_val; 1553 else if (hw->phy_type == e1000_phy_8201) 1554 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1555 1556 /* Need to parse both autoneg_advertised and fc and set up 1557 * the appropriate PHY registers. First we will parse for 1558 * autoneg_advertised software override. Since we can advertise 1559 * a plethora of combinations, we need to check each bit 1560 * individually. 1561 */ 1562 1563 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1564 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1565 * the 1000Base-T Control Register (Address 9). 1566 */ 1567 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1568 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1569 1570 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); 1571 1572 /* Do we want to advertise 10 Mb Half Duplex? */ 1573 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1574 e_dbg("Advertise 10mb Half duplex\n"); 1575 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1576 } 1577 1578 /* Do we want to advertise 10 Mb Full Duplex? */ 1579 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1580 e_dbg("Advertise 10mb Full duplex\n"); 1581 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1582 } 1583 1584 /* Do we want to advertise 100 Mb Half Duplex? */ 1585 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1586 e_dbg("Advertise 100mb Half duplex\n"); 1587 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1588 } 1589 1590 /* Do we want to advertise 100 Mb Full Duplex? */ 1591 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1592 e_dbg("Advertise 100mb Full duplex\n"); 1593 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1594 } 1595 1596 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1597 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1598 e_dbg 1599 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1600 } 1601 1602 /* Do we want to advertise 1000 Mb Full Duplex? */ 1603 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1604 e_dbg("Advertise 1000mb Full duplex\n"); 1605 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1606 } 1607 1608 /* Check for a software override of the flow control settings, and 1609 * setup the PHY advertisement registers accordingly. If 1610 * auto-negotiation is enabled, then software will have to set the 1611 * "PAUSE" bits to the correct value in the Auto-Negotiation 1612 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1613 * 1614 * The possible values of the "fc" parameter are: 1615 * 0: Flow control is completely disabled 1616 * 1: Rx flow control is enabled (we can receive pause frames 1617 * but not send pause frames). 1618 * 2: Tx flow control is enabled (we can send pause frames 1619 * but we do not support receiving pause frames). 1620 * 3: Both Rx and TX flow control (symmetric) are enabled. 1621 * other: No software override. The flow control configuration 1622 * in the EEPROM is used. 1623 */ 1624 switch (hw->fc) { 1625 case E1000_FC_NONE: /* 0 */ 1626 /* Flow control (RX & TX) is completely disabled by a 1627 * software over-ride. 1628 */ 1629 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1630 break; 1631 case E1000_FC_RX_PAUSE: /* 1 */ 1632 /* RX Flow control is enabled, and TX Flow control is 1633 * disabled, by a software over-ride. 1634 */ 1635 /* Since there really isn't a way to advertise that we are 1636 * capable of RX Pause ONLY, we will advertise that we 1637 * support both symmetric and asymmetric RX PAUSE. Later 1638 * (in e1000_config_fc_after_link_up) we will disable the 1639 *hw's ability to send PAUSE frames. 1640 */ 1641 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1642 break; 1643 case E1000_FC_TX_PAUSE: /* 2 */ 1644 /* TX Flow control is enabled, and RX Flow control is 1645 * disabled, by a software over-ride. 1646 */ 1647 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1648 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1649 break; 1650 case E1000_FC_FULL: /* 3 */ 1651 /* Flow control (both RX and TX) is enabled by a software 1652 * over-ride. 1653 */ 1654 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1655 break; 1656 default: 1657 e_dbg("Flow control param set incorrectly\n"); 1658 return -E1000_ERR_CONFIG; 1659 } 1660 1661 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1662 if (ret_val) 1663 return ret_val; 1664 1665 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1666 1667 if (hw->phy_type == e1000_phy_8201) { 1668 mii_1000t_ctrl_reg = 0; 1669 } else { 1670 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1671 mii_1000t_ctrl_reg); 1672 if (ret_val) 1673 return ret_val; 1674 } 1675 1676 return E1000_SUCCESS; 1677 } 1678 1679 /** 1680 * e1000_phy_force_speed_duplex - force link settings 1681 * @hw: Struct containing variables accessed by shared code 1682 * 1683 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1684 */ 1685 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1686 { 1687 u32 ctrl; 1688 s32 ret_val; 1689 u16 mii_ctrl_reg; 1690 u16 mii_status_reg; 1691 u16 phy_data; 1692 u16 i; 1693 1694 e_dbg("e1000_phy_force_speed_duplex"); 1695 1696 /* Turn off Flow control if we are forcing speed and duplex. */ 1697 hw->fc = E1000_FC_NONE; 1698 1699 e_dbg("hw->fc = %d\n", hw->fc); 1700 1701 /* Read the Device Control Register. */ 1702 ctrl = er32(CTRL); 1703 1704 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1705 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1706 ctrl &= ~(DEVICE_SPEED_MASK); 1707 1708 /* Clear the Auto Speed Detect Enable bit. */ 1709 ctrl &= ~E1000_CTRL_ASDE; 1710 1711 /* Read the MII Control Register. */ 1712 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1713 if (ret_val) 1714 return ret_val; 1715 1716 /* We need to disable autoneg in order to force link and duplex. */ 1717 1718 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1719 1720 /* Are we forcing Full or Half Duplex? */ 1721 if (hw->forced_speed_duplex == e1000_100_full || 1722 hw->forced_speed_duplex == e1000_10_full) { 1723 /* We want to force full duplex so we SET the full duplex bits in the 1724 * Device and MII Control Registers. 1725 */ 1726 ctrl |= E1000_CTRL_FD; 1727 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1728 e_dbg("Full Duplex\n"); 1729 } else { 1730 /* We want to force half duplex so we CLEAR the full duplex bits in 1731 * the Device and MII Control Registers. 1732 */ 1733 ctrl &= ~E1000_CTRL_FD; 1734 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1735 e_dbg("Half Duplex\n"); 1736 } 1737 1738 /* Are we forcing 100Mbps??? */ 1739 if (hw->forced_speed_duplex == e1000_100_full || 1740 hw->forced_speed_duplex == e1000_100_half) { 1741 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1742 ctrl |= E1000_CTRL_SPD_100; 1743 mii_ctrl_reg |= MII_CR_SPEED_100; 1744 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1745 e_dbg("Forcing 100mb "); 1746 } else { 1747 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1748 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1749 mii_ctrl_reg |= MII_CR_SPEED_10; 1750 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1751 e_dbg("Forcing 10mb "); 1752 } 1753 1754 e1000_config_collision_dist(hw); 1755 1756 /* Write the configured values back to the Device Control Reg. */ 1757 ew32(CTRL, ctrl); 1758 1759 if (hw->phy_type == e1000_phy_m88) { 1760 ret_val = 1761 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1762 if (ret_val) 1763 return ret_val; 1764 1765 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1766 * forced whenever speed are duplex are forced. 1767 */ 1768 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1769 ret_val = 1770 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1771 if (ret_val) 1772 return ret_val; 1773 1774 e_dbg("M88E1000 PSCR: %x\n", phy_data); 1775 1776 /* Need to reset the PHY or these changes will be ignored */ 1777 mii_ctrl_reg |= MII_CR_RESET; 1778 1779 /* Disable MDI-X support for 10/100 */ 1780 } else { 1781 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1782 * forced whenever speed or duplex are forced. 1783 */ 1784 ret_val = 1785 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1786 if (ret_val) 1787 return ret_val; 1788 1789 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1790 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1791 1792 ret_val = 1793 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1794 if (ret_val) 1795 return ret_val; 1796 } 1797 1798 /* Write back the modified PHY MII control register. */ 1799 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1800 if (ret_val) 1801 return ret_val; 1802 1803 udelay(1); 1804 1805 /* The wait_autoneg_complete flag may be a little misleading here. 1806 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1807 * But we do want to delay for a period while forcing only so we 1808 * don't generate false No Link messages. So we will wait here 1809 * only if the user has set wait_autoneg_complete to 1, which is 1810 * the default. 1811 */ 1812 if (hw->wait_autoneg_complete) { 1813 /* We will wait for autoneg to complete. */ 1814 e_dbg("Waiting for forced speed/duplex link.\n"); 1815 mii_status_reg = 0; 1816 1817 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1818 for (i = PHY_FORCE_TIME; i > 0; i--) { 1819 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1820 * to be set. 1821 */ 1822 ret_val = 1823 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1824 if (ret_val) 1825 return ret_val; 1826 1827 ret_val = 1828 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1829 if (ret_val) 1830 return ret_val; 1831 1832 if (mii_status_reg & MII_SR_LINK_STATUS) 1833 break; 1834 msleep(100); 1835 } 1836 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { 1837 /* We didn't get link. Reset the DSP and wait again for link. */ 1838 ret_val = e1000_phy_reset_dsp(hw); 1839 if (ret_val) { 1840 e_dbg("Error Resetting PHY DSP\n"); 1841 return ret_val; 1842 } 1843 } 1844 /* This loop will early-out if the link condition has been met. */ 1845 for (i = PHY_FORCE_TIME; i > 0; i--) { 1846 if (mii_status_reg & MII_SR_LINK_STATUS) 1847 break; 1848 msleep(100); 1849 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1850 * to be set. 1851 */ 1852 ret_val = 1853 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1854 if (ret_val) 1855 return ret_val; 1856 1857 ret_val = 1858 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1859 if (ret_val) 1860 return ret_val; 1861 } 1862 } 1863 1864 if (hw->phy_type == e1000_phy_m88) { 1865 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1866 * Extended PHY Specific Control Register to 25MHz clock. This value 1867 * defaults back to a 2.5MHz clock when the PHY is reset. 1868 */ 1869 ret_val = 1870 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1871 &phy_data); 1872 if (ret_val) 1873 return ret_val; 1874 1875 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1876 ret_val = 1877 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1878 phy_data); 1879 if (ret_val) 1880 return ret_val; 1881 1882 /* In addition, because of the s/w reset above, we need to enable CRS on 1883 * TX. This must be set for both full and half duplex operation. 1884 */ 1885 ret_val = 1886 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1887 if (ret_val) 1888 return ret_val; 1889 1890 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1891 ret_val = 1892 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1893 if (ret_val) 1894 return ret_val; 1895 1896 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) 1897 && (!hw->autoneg) 1898 && (hw->forced_speed_duplex == e1000_10_full 1899 || hw->forced_speed_duplex == e1000_10_half)) { 1900 ret_val = e1000_polarity_reversal_workaround(hw); 1901 if (ret_val) 1902 return ret_val; 1903 } 1904 } 1905 return E1000_SUCCESS; 1906 } 1907 1908 /** 1909 * e1000_config_collision_dist - set collision distance register 1910 * @hw: Struct containing variables accessed by shared code 1911 * 1912 * Sets the collision distance in the Transmit Control register. 1913 * Link should have been established previously. Reads the speed and duplex 1914 * information from the Device Status register. 1915 */ 1916 void e1000_config_collision_dist(struct e1000_hw *hw) 1917 { 1918 u32 tctl, coll_dist; 1919 1920 e_dbg("e1000_config_collision_dist"); 1921 1922 if (hw->mac_type < e1000_82543) 1923 coll_dist = E1000_COLLISION_DISTANCE_82542; 1924 else 1925 coll_dist = E1000_COLLISION_DISTANCE; 1926 1927 tctl = er32(TCTL); 1928 1929 tctl &= ~E1000_TCTL_COLD; 1930 tctl |= coll_dist << E1000_COLD_SHIFT; 1931 1932 ew32(TCTL, tctl); 1933 E1000_WRITE_FLUSH(); 1934 } 1935 1936 /** 1937 * e1000_config_mac_to_phy - sync phy and mac settings 1938 * @hw: Struct containing variables accessed by shared code 1939 * @mii_reg: data to write to the MII control register 1940 * 1941 * Sets MAC speed and duplex settings to reflect the those in the PHY 1942 * The contents of the PHY register containing the needed information need to 1943 * be passed in. 1944 */ 1945 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1946 { 1947 u32 ctrl; 1948 s32 ret_val; 1949 u16 phy_data; 1950 1951 e_dbg("e1000_config_mac_to_phy"); 1952 1953 /* 82544 or newer MAC, Auto Speed Detection takes care of 1954 * MAC speed/duplex configuration.*/ 1955 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) 1956 return E1000_SUCCESS; 1957 1958 /* Read the Device Control Register and set the bits to Force Speed 1959 * and Duplex. 1960 */ 1961 ctrl = er32(CTRL); 1962 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1963 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1964 1965 switch (hw->phy_type) { 1966 case e1000_phy_8201: 1967 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1968 if (ret_val) 1969 return ret_val; 1970 1971 if (phy_data & RTL_PHY_CTRL_FD) 1972 ctrl |= E1000_CTRL_FD; 1973 else 1974 ctrl &= ~E1000_CTRL_FD; 1975 1976 if (phy_data & RTL_PHY_CTRL_SPD_100) 1977 ctrl |= E1000_CTRL_SPD_100; 1978 else 1979 ctrl |= E1000_CTRL_SPD_10; 1980 1981 e1000_config_collision_dist(hw); 1982 break; 1983 default: 1984 /* Set up duplex in the Device Control and Transmit Control 1985 * registers depending on negotiated values. 1986 */ 1987 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 1988 &phy_data); 1989 if (ret_val) 1990 return ret_val; 1991 1992 if (phy_data & M88E1000_PSSR_DPLX) 1993 ctrl |= E1000_CTRL_FD; 1994 else 1995 ctrl &= ~E1000_CTRL_FD; 1996 1997 e1000_config_collision_dist(hw); 1998 1999 /* Set up speed in the Device Control register depending on 2000 * negotiated values. 2001 */ 2002 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2003 ctrl |= E1000_CTRL_SPD_1000; 2004 else if ((phy_data & M88E1000_PSSR_SPEED) == 2005 M88E1000_PSSR_100MBS) 2006 ctrl |= E1000_CTRL_SPD_100; 2007 } 2008 2009 /* Write the configured values back to the Device Control Reg. */ 2010 ew32(CTRL, ctrl); 2011 return E1000_SUCCESS; 2012 } 2013 2014 /** 2015 * e1000_force_mac_fc - force flow control settings 2016 * @hw: Struct containing variables accessed by shared code 2017 * 2018 * Forces the MAC's flow control settings. 2019 * Sets the TFCE and RFCE bits in the device control register to reflect 2020 * the adapter settings. TFCE and RFCE need to be explicitly set by 2021 * software when a Copper PHY is used because autonegotiation is managed 2022 * by the PHY rather than the MAC. Software must also configure these 2023 * bits when link is forced on a fiber connection. 2024 */ 2025 s32 e1000_force_mac_fc(struct e1000_hw *hw) 2026 { 2027 u32 ctrl; 2028 2029 e_dbg("e1000_force_mac_fc"); 2030 2031 /* Get the current configuration of the Device Control Register */ 2032 ctrl = er32(CTRL); 2033 2034 /* Because we didn't get link via the internal auto-negotiation 2035 * mechanism (we either forced link or we got link via PHY 2036 * auto-neg), we have to manually enable/disable transmit an 2037 * receive flow control. 2038 * 2039 * The "Case" statement below enables/disable flow control 2040 * according to the "hw->fc" parameter. 2041 * 2042 * The possible values of the "fc" parameter are: 2043 * 0: Flow control is completely disabled 2044 * 1: Rx flow control is enabled (we can receive pause 2045 * frames but not send pause frames). 2046 * 2: Tx flow control is enabled (we can send pause frames 2047 * frames but we do not receive pause frames). 2048 * 3: Both Rx and TX flow control (symmetric) is enabled. 2049 * other: No other values should be possible at this point. 2050 */ 2051 2052 switch (hw->fc) { 2053 case E1000_FC_NONE: 2054 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2055 break; 2056 case E1000_FC_RX_PAUSE: 2057 ctrl &= (~E1000_CTRL_TFCE); 2058 ctrl |= E1000_CTRL_RFCE; 2059 break; 2060 case E1000_FC_TX_PAUSE: 2061 ctrl &= (~E1000_CTRL_RFCE); 2062 ctrl |= E1000_CTRL_TFCE; 2063 break; 2064 case E1000_FC_FULL: 2065 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2066 break; 2067 default: 2068 e_dbg("Flow control param set incorrectly\n"); 2069 return -E1000_ERR_CONFIG; 2070 } 2071 2072 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2073 if (hw->mac_type == e1000_82542_rev2_0) 2074 ctrl &= (~E1000_CTRL_TFCE); 2075 2076 ew32(CTRL, ctrl); 2077 return E1000_SUCCESS; 2078 } 2079 2080 /** 2081 * e1000_config_fc_after_link_up - configure flow control after autoneg 2082 * @hw: Struct containing variables accessed by shared code 2083 * 2084 * Configures flow control settings after link is established 2085 * Should be called immediately after a valid link has been established. 2086 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2087 * and autonegotiation is enabled, the MAC flow control settings will be set 2088 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2089 * and RFCE bits will be automatically set to the negotiated flow control mode. 2090 */ 2091 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 2092 { 2093 s32 ret_val; 2094 u16 mii_status_reg; 2095 u16 mii_nway_adv_reg; 2096 u16 mii_nway_lp_ability_reg; 2097 u16 speed; 2098 u16 duplex; 2099 2100 e_dbg("e1000_config_fc_after_link_up"); 2101 2102 /* Check for the case where we have fiber media and auto-neg failed 2103 * so we had to force link. In this case, we need to force the 2104 * configuration of the MAC to match the "fc" parameter. 2105 */ 2106 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 2107 || ((hw->media_type == e1000_media_type_internal_serdes) 2108 && (hw->autoneg_failed)) 2109 || ((hw->media_type == e1000_media_type_copper) 2110 && (!hw->autoneg))) { 2111 ret_val = e1000_force_mac_fc(hw); 2112 if (ret_val) { 2113 e_dbg("Error forcing flow control settings\n"); 2114 return ret_val; 2115 } 2116 } 2117 2118 /* Check for the case where we have copper media and auto-neg is 2119 * enabled. In this case, we need to check and see if Auto-Neg 2120 * has completed, and if so, how the PHY and link partner has 2121 * flow control configured. 2122 */ 2123 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2124 /* Read the MII Status Register and check to see if AutoNeg 2125 * has completed. We read this twice because this reg has 2126 * some "sticky" (latched) bits. 2127 */ 2128 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2129 if (ret_val) 2130 return ret_val; 2131 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2132 if (ret_val) 2133 return ret_val; 2134 2135 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2136 /* The AutoNeg process has completed, so we now need to 2137 * read both the Auto Negotiation Advertisement Register 2138 * (Address 4) and the Auto_Negotiation Base Page Ability 2139 * Register (Address 5) to determine how flow control was 2140 * negotiated. 2141 */ 2142 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2143 &mii_nway_adv_reg); 2144 if (ret_val) 2145 return ret_val; 2146 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2147 &mii_nway_lp_ability_reg); 2148 if (ret_val) 2149 return ret_val; 2150 2151 /* Two bits in the Auto Negotiation Advertisement Register 2152 * (Address 4) and two bits in the Auto Negotiation Base 2153 * Page Ability Register (Address 5) determine flow control 2154 * for both the PHY and the link partner. The following 2155 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2156 * 1999, describes these PAUSE resolution bits and how flow 2157 * control is determined based upon these settings. 2158 * NOTE: DC = Don't Care 2159 * 2160 * LOCAL DEVICE | LINK PARTNER 2161 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2162 *-------|---------|-------|---------|-------------------- 2163 * 0 | 0 | DC | DC | E1000_FC_NONE 2164 * 0 | 1 | 0 | DC | E1000_FC_NONE 2165 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2166 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2167 * 1 | 0 | 0 | DC | E1000_FC_NONE 2168 * 1 | DC | 1 | DC | E1000_FC_FULL 2169 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2170 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2171 * 2172 */ 2173 /* Are both PAUSE bits set to 1? If so, this implies 2174 * Symmetric Flow Control is enabled at both ends. The 2175 * ASM_DIR bits are irrelevant per the spec. 2176 * 2177 * For Symmetric Flow Control: 2178 * 2179 * LOCAL DEVICE | LINK PARTNER 2180 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2181 *-------|---------|-------|---------|-------------------- 2182 * 1 | DC | 1 | DC | E1000_FC_FULL 2183 * 2184 */ 2185 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2186 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2187 /* Now we need to check if the user selected RX ONLY 2188 * of pause frames. In this case, we had to advertise 2189 * FULL flow control because we could not advertise RX 2190 * ONLY. Hence, we must now check to see if we need to 2191 * turn OFF the TRANSMISSION of PAUSE frames. 2192 */ 2193 if (hw->original_fc == E1000_FC_FULL) { 2194 hw->fc = E1000_FC_FULL; 2195 e_dbg("Flow Control = FULL.\n"); 2196 } else { 2197 hw->fc = E1000_FC_RX_PAUSE; 2198 e_dbg 2199 ("Flow Control = RX PAUSE frames only.\n"); 2200 } 2201 } 2202 /* For receiving PAUSE frames ONLY. 2203 * 2204 * LOCAL DEVICE | LINK PARTNER 2205 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2206 *-------|---------|-------|---------|-------------------- 2207 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2208 * 2209 */ 2210 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2211 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2212 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2213 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2214 { 2215 hw->fc = E1000_FC_TX_PAUSE; 2216 e_dbg 2217 ("Flow Control = TX PAUSE frames only.\n"); 2218 } 2219 /* For transmitting PAUSE frames ONLY. 2220 * 2221 * LOCAL DEVICE | LINK PARTNER 2222 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2223 *-------|---------|-------|---------|-------------------- 2224 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2225 * 2226 */ 2227 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2228 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2229 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2230 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2231 { 2232 hw->fc = E1000_FC_RX_PAUSE; 2233 e_dbg 2234 ("Flow Control = RX PAUSE frames only.\n"); 2235 } 2236 /* Per the IEEE spec, at this point flow control should be 2237 * disabled. However, we want to consider that we could 2238 * be connected to a legacy switch that doesn't advertise 2239 * desired flow control, but can be forced on the link 2240 * partner. So if we advertised no flow control, that is 2241 * what we will resolve to. If we advertised some kind of 2242 * receive capability (Rx Pause Only or Full Flow Control) 2243 * and the link partner advertised none, we will configure 2244 * ourselves to enable Rx Flow Control only. We can do 2245 * this safely for two reasons: If the link partner really 2246 * didn't want flow control enabled, and we enable Rx, no 2247 * harm done since we won't be receiving any PAUSE frames 2248 * anyway. If the intent on the link partner was to have 2249 * flow control enabled, then by us enabling RX only, we 2250 * can at least receive pause frames and process them. 2251 * This is a good idea because in most cases, since we are 2252 * predominantly a server NIC, more times than not we will 2253 * be asked to delay transmission of packets than asking 2254 * our link partner to pause transmission of frames. 2255 */ 2256 else if ((hw->original_fc == E1000_FC_NONE || 2257 hw->original_fc == E1000_FC_TX_PAUSE) || 2258 hw->fc_strict_ieee) { 2259 hw->fc = E1000_FC_NONE; 2260 e_dbg("Flow Control = NONE.\n"); 2261 } else { 2262 hw->fc = E1000_FC_RX_PAUSE; 2263 e_dbg 2264 ("Flow Control = RX PAUSE frames only.\n"); 2265 } 2266 2267 /* Now we need to do one last check... If we auto- 2268 * negotiated to HALF DUPLEX, flow control should not be 2269 * enabled per IEEE 802.3 spec. 2270 */ 2271 ret_val = 2272 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2273 if (ret_val) { 2274 e_dbg 2275 ("Error getting link speed and duplex\n"); 2276 return ret_val; 2277 } 2278 2279 if (duplex == HALF_DUPLEX) 2280 hw->fc = E1000_FC_NONE; 2281 2282 /* Now we call a subroutine to actually force the MAC 2283 * controller to use the correct flow control settings. 2284 */ 2285 ret_val = e1000_force_mac_fc(hw); 2286 if (ret_val) { 2287 e_dbg 2288 ("Error forcing flow control settings\n"); 2289 return ret_val; 2290 } 2291 } else { 2292 e_dbg 2293 ("Copper PHY and Auto Neg has not completed.\n"); 2294 } 2295 } 2296 return E1000_SUCCESS; 2297 } 2298 2299 /** 2300 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2301 * @hw: pointer to the HW structure 2302 * 2303 * Checks for link up on the hardware. If link is not up and we have 2304 * a signal, then we need to force link up. 2305 */ 2306 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2307 { 2308 u32 rxcw; 2309 u32 ctrl; 2310 u32 status; 2311 s32 ret_val = E1000_SUCCESS; 2312 2313 e_dbg("e1000_check_for_serdes_link_generic"); 2314 2315 ctrl = er32(CTRL); 2316 status = er32(STATUS); 2317 rxcw = er32(RXCW); 2318 2319 /* 2320 * If we don't have link (auto-negotiation failed or link partner 2321 * cannot auto-negotiate), and our link partner is not trying to 2322 * auto-negotiate with us (we are receiving idles or data), 2323 * we need to force link up. We also need to give auto-negotiation 2324 * time to complete. 2325 */ 2326 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 2327 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 2328 if (hw->autoneg_failed == 0) { 2329 hw->autoneg_failed = 1; 2330 goto out; 2331 } 2332 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 2333 2334 /* Disable auto-negotiation in the TXCW register */ 2335 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2336 2337 /* Force link-up and also force full-duplex. */ 2338 ctrl = er32(CTRL); 2339 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2340 ew32(CTRL, ctrl); 2341 2342 /* Configure Flow Control after forcing link up. */ 2343 ret_val = e1000_config_fc_after_link_up(hw); 2344 if (ret_val) { 2345 e_dbg("Error configuring flow control\n"); 2346 goto out; 2347 } 2348 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2349 /* 2350 * If we are forcing link and we are receiving /C/ ordered 2351 * sets, re-enable auto-negotiation in the TXCW register 2352 * and disable forced link in the Device Control register 2353 * in an attempt to auto-negotiate with our link partner. 2354 */ 2355 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2356 ew32(TXCW, hw->txcw); 2357 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2358 2359 hw->serdes_has_link = true; 2360 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 2361 /* 2362 * If we force link for non-auto-negotiation switch, check 2363 * link status based on MAC synchronization for internal 2364 * serdes media type. 2365 */ 2366 /* SYNCH bit and IV bit are sticky. */ 2367 udelay(10); 2368 rxcw = er32(RXCW); 2369 if (rxcw & E1000_RXCW_SYNCH) { 2370 if (!(rxcw & E1000_RXCW_IV)) { 2371 hw->serdes_has_link = true; 2372 e_dbg("SERDES: Link up - forced.\n"); 2373 } 2374 } else { 2375 hw->serdes_has_link = false; 2376 e_dbg("SERDES: Link down - force failed.\n"); 2377 } 2378 } 2379 2380 if (E1000_TXCW_ANE & er32(TXCW)) { 2381 status = er32(STATUS); 2382 if (status & E1000_STATUS_LU) { 2383 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 2384 udelay(10); 2385 rxcw = er32(RXCW); 2386 if (rxcw & E1000_RXCW_SYNCH) { 2387 if (!(rxcw & E1000_RXCW_IV)) { 2388 hw->serdes_has_link = true; 2389 e_dbg("SERDES: Link up - autoneg " 2390 "completed successfully.\n"); 2391 } else { 2392 hw->serdes_has_link = false; 2393 e_dbg("SERDES: Link down - invalid" 2394 "codewords detected in autoneg.\n"); 2395 } 2396 } else { 2397 hw->serdes_has_link = false; 2398 e_dbg("SERDES: Link down - no sync.\n"); 2399 } 2400 } else { 2401 hw->serdes_has_link = false; 2402 e_dbg("SERDES: Link down - autoneg failed\n"); 2403 } 2404 } 2405 2406 out: 2407 return ret_val; 2408 } 2409 2410 /** 2411 * e1000_check_for_link 2412 * @hw: Struct containing variables accessed by shared code 2413 * 2414 * Checks to see if the link status of the hardware has changed. 2415 * Called by any function that needs to check the link status of the adapter. 2416 */ 2417 s32 e1000_check_for_link(struct e1000_hw *hw) 2418 { 2419 u32 rxcw = 0; 2420 u32 ctrl; 2421 u32 status; 2422 u32 rctl; 2423 u32 icr; 2424 u32 signal = 0; 2425 s32 ret_val; 2426 u16 phy_data; 2427 2428 e_dbg("e1000_check_for_link"); 2429 2430 ctrl = er32(CTRL); 2431 status = er32(STATUS); 2432 2433 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be 2434 * set when the optics detect a signal. On older adapters, it will be 2435 * cleared when there is a signal. This applies to fiber media only. 2436 */ 2437 if ((hw->media_type == e1000_media_type_fiber) || 2438 (hw->media_type == e1000_media_type_internal_serdes)) { 2439 rxcw = er32(RXCW); 2440 2441 if (hw->media_type == e1000_media_type_fiber) { 2442 signal = 2443 (hw->mac_type > 2444 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2445 if (status & E1000_STATUS_LU) 2446 hw->get_link_status = false; 2447 } 2448 } 2449 2450 /* If we have a copper PHY then we only want to go out to the PHY 2451 * registers to see if Auto-Neg has completed and/or if our link 2452 * status has changed. The get_link_status flag will be set if we 2453 * receive a Link Status Change interrupt or we have Rx Sequence 2454 * Errors. 2455 */ 2456 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2457 /* First we want to see if the MII Status Register reports 2458 * link. If so, then we want to get the current speed/duplex 2459 * of the PHY. 2460 * Read the register twice since the link bit is sticky. 2461 */ 2462 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2463 if (ret_val) 2464 return ret_val; 2465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2466 if (ret_val) 2467 return ret_val; 2468 2469 if (phy_data & MII_SR_LINK_STATUS) { 2470 hw->get_link_status = false; 2471 /* Check if there was DownShift, must be checked immediately after 2472 * link-up */ 2473 e1000_check_downshift(hw); 2474 2475 /* If we are on 82544 or 82543 silicon and speed/duplex 2476 * are forced to 10H or 10F, then we will implement the polarity 2477 * reversal workaround. We disable interrupts first, and upon 2478 * returning, place the devices interrupt state to its previous 2479 * value except for the link status change interrupt which will 2480 * happen due to the execution of this workaround. 2481 */ 2482 2483 if ((hw->mac_type == e1000_82544 2484 || hw->mac_type == e1000_82543) && (!hw->autoneg) 2485 && (hw->forced_speed_duplex == e1000_10_full 2486 || hw->forced_speed_duplex == e1000_10_half)) { 2487 ew32(IMC, 0xffffffff); 2488 ret_val = 2489 e1000_polarity_reversal_workaround(hw); 2490 icr = er32(ICR); 2491 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2492 ew32(IMS, IMS_ENABLE_MASK); 2493 } 2494 2495 } else { 2496 /* No link detected */ 2497 e1000_config_dsp_after_link_change(hw, false); 2498 return 0; 2499 } 2500 2501 /* If we are forcing speed/duplex, then we simply return since 2502 * we have already determined whether we have link or not. 2503 */ 2504 if (!hw->autoneg) 2505 return -E1000_ERR_CONFIG; 2506 2507 /* optimize the dsp settings for the igp phy */ 2508 e1000_config_dsp_after_link_change(hw, true); 2509 2510 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2511 * have Si on board that is 82544 or newer, Auto 2512 * Speed Detection takes care of MAC speed/duplex 2513 * configuration. So we only need to configure Collision 2514 * Distance in the MAC. Otherwise, we need to force 2515 * speed/duplex on the MAC to the current PHY speed/duplex 2516 * settings. 2517 */ 2518 if ((hw->mac_type >= e1000_82544) && 2519 (hw->mac_type != e1000_ce4100)) 2520 e1000_config_collision_dist(hw); 2521 else { 2522 ret_val = e1000_config_mac_to_phy(hw); 2523 if (ret_val) { 2524 e_dbg 2525 ("Error configuring MAC to PHY settings\n"); 2526 return ret_val; 2527 } 2528 } 2529 2530 /* Configure Flow Control now that Auto-Neg has completed. First, we 2531 * need to restore the desired flow control settings because we may 2532 * have had to re-autoneg with a different link partner. 2533 */ 2534 ret_val = e1000_config_fc_after_link_up(hw); 2535 if (ret_val) { 2536 e_dbg("Error configuring flow control\n"); 2537 return ret_val; 2538 } 2539 2540 /* At this point we know that we are on copper and we have 2541 * auto-negotiated link. These are conditions for checking the link 2542 * partner capability register. We use the link speed to determine if 2543 * TBI compatibility needs to be turned on or off. If the link is not 2544 * at gigabit speed, then TBI compatibility is not needed. If we are 2545 * at gigabit speed, we turn on TBI compatibility. 2546 */ 2547 if (hw->tbi_compatibility_en) { 2548 u16 speed, duplex; 2549 ret_val = 2550 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2551 if (ret_val) { 2552 e_dbg 2553 ("Error getting link speed and duplex\n"); 2554 return ret_val; 2555 } 2556 if (speed != SPEED_1000) { 2557 /* If link speed is not set to gigabit speed, we do not need 2558 * to enable TBI compatibility. 2559 */ 2560 if (hw->tbi_compatibility_on) { 2561 /* If we previously were in the mode, turn it off. */ 2562 rctl = er32(RCTL); 2563 rctl &= ~E1000_RCTL_SBP; 2564 ew32(RCTL, rctl); 2565 hw->tbi_compatibility_on = false; 2566 } 2567 } else { 2568 /* If TBI compatibility is was previously off, turn it on. For 2569 * compatibility with a TBI link partner, we will store bad 2570 * packets. Some frames have an additional byte on the end and 2571 * will look like CRC errors to to the hardware. 2572 */ 2573 if (!hw->tbi_compatibility_on) { 2574 hw->tbi_compatibility_on = true; 2575 rctl = er32(RCTL); 2576 rctl |= E1000_RCTL_SBP; 2577 ew32(RCTL, rctl); 2578 } 2579 } 2580 } 2581 } 2582 2583 if ((hw->media_type == e1000_media_type_fiber) || 2584 (hw->media_type == e1000_media_type_internal_serdes)) 2585 e1000_check_for_serdes_link_generic(hw); 2586 2587 return E1000_SUCCESS; 2588 } 2589 2590 /** 2591 * e1000_get_speed_and_duplex 2592 * @hw: Struct containing variables accessed by shared code 2593 * @speed: Speed of the connection 2594 * @duplex: Duplex setting of the connection 2595 * 2596 * Detects the current speed and duplex settings of the hardware. 2597 */ 2598 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2599 { 2600 u32 status; 2601 s32 ret_val; 2602 u16 phy_data; 2603 2604 e_dbg("e1000_get_speed_and_duplex"); 2605 2606 if (hw->mac_type >= e1000_82543) { 2607 status = er32(STATUS); 2608 if (status & E1000_STATUS_SPEED_1000) { 2609 *speed = SPEED_1000; 2610 e_dbg("1000 Mbs, "); 2611 } else if (status & E1000_STATUS_SPEED_100) { 2612 *speed = SPEED_100; 2613 e_dbg("100 Mbs, "); 2614 } else { 2615 *speed = SPEED_10; 2616 e_dbg("10 Mbs, "); 2617 } 2618 2619 if (status & E1000_STATUS_FD) { 2620 *duplex = FULL_DUPLEX; 2621 e_dbg("Full Duplex\n"); 2622 } else { 2623 *duplex = HALF_DUPLEX; 2624 e_dbg(" Half Duplex\n"); 2625 } 2626 } else { 2627 e_dbg("1000 Mbs, Full Duplex\n"); 2628 *speed = SPEED_1000; 2629 *duplex = FULL_DUPLEX; 2630 } 2631 2632 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 2633 * if it is operating at half duplex. Here we set the duplex settings to 2634 * match the duplex in the link partner's capabilities. 2635 */ 2636 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2637 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2638 if (ret_val) 2639 return ret_val; 2640 2641 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2642 *duplex = HALF_DUPLEX; 2643 else { 2644 ret_val = 2645 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2646 if (ret_val) 2647 return ret_val; 2648 if ((*speed == SPEED_100 2649 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 2650 || (*speed == SPEED_10 2651 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2652 *duplex = HALF_DUPLEX; 2653 } 2654 } 2655 2656 return E1000_SUCCESS; 2657 } 2658 2659 /** 2660 * e1000_wait_autoneg 2661 * @hw: Struct containing variables accessed by shared code 2662 * 2663 * Blocks until autoneg completes or times out (~4.5 seconds) 2664 */ 2665 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2666 { 2667 s32 ret_val; 2668 u16 i; 2669 u16 phy_data; 2670 2671 e_dbg("e1000_wait_autoneg"); 2672 e_dbg("Waiting for Auto-Neg to complete.\n"); 2673 2674 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2675 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2676 /* Read the MII Status Register and wait for Auto-Neg 2677 * Complete bit to be set. 2678 */ 2679 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2680 if (ret_val) 2681 return ret_val; 2682 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2683 if (ret_val) 2684 return ret_val; 2685 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2686 return E1000_SUCCESS; 2687 } 2688 msleep(100); 2689 } 2690 return E1000_SUCCESS; 2691 } 2692 2693 /** 2694 * e1000_raise_mdi_clk - Raises the Management Data Clock 2695 * @hw: Struct containing variables accessed by shared code 2696 * @ctrl: Device control register's current value 2697 */ 2698 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2699 { 2700 /* Raise the clock input to the Management Data Clock (by setting the MDC 2701 * bit), and then delay 10 microseconds. 2702 */ 2703 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2704 E1000_WRITE_FLUSH(); 2705 udelay(10); 2706 } 2707 2708 /** 2709 * e1000_lower_mdi_clk - Lowers the Management Data Clock 2710 * @hw: Struct containing variables accessed by shared code 2711 * @ctrl: Device control register's current value 2712 */ 2713 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2714 { 2715 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2716 * bit), and then delay 10 microseconds. 2717 */ 2718 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2719 E1000_WRITE_FLUSH(); 2720 udelay(10); 2721 } 2722 2723 /** 2724 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY 2725 * @hw: Struct containing variables accessed by shared code 2726 * @data: Data to send out to the PHY 2727 * @count: Number of bits to shift out 2728 * 2729 * Bits are shifted out in MSB to LSB order. 2730 */ 2731 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2732 { 2733 u32 ctrl; 2734 u32 mask; 2735 2736 /* We need to shift "count" number of bits out to the PHY. So, the value 2737 * in the "data" parameter will be shifted out to the PHY one bit at a 2738 * time. In order to do this, "data" must be broken down into bits. 2739 */ 2740 mask = 0x01; 2741 mask <<= (count - 1); 2742 2743 ctrl = er32(CTRL); 2744 2745 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2746 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2747 2748 while (mask) { 2749 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2750 * then raising and lowering the Management Data Clock. A "0" is 2751 * shifted out to the PHY by setting the MDIO bit to "0" and then 2752 * raising and lowering the clock. 2753 */ 2754 if (data & mask) 2755 ctrl |= E1000_CTRL_MDIO; 2756 else 2757 ctrl &= ~E1000_CTRL_MDIO; 2758 2759 ew32(CTRL, ctrl); 2760 E1000_WRITE_FLUSH(); 2761 2762 udelay(10); 2763 2764 e1000_raise_mdi_clk(hw, &ctrl); 2765 e1000_lower_mdi_clk(hw, &ctrl); 2766 2767 mask = mask >> 1; 2768 } 2769 } 2770 2771 /** 2772 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY 2773 * @hw: Struct containing variables accessed by shared code 2774 * 2775 * Bits are shifted in in MSB to LSB order. 2776 */ 2777 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2778 { 2779 u32 ctrl; 2780 u16 data = 0; 2781 u8 i; 2782 2783 /* In order to read a register from the PHY, we need to shift in a total 2784 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2785 * to avoid contention on the MDIO pin when a read operation is performed. 2786 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2787 * by raising the input to the Management Data Clock (setting the MDC bit), 2788 * and then reading the value of the MDIO bit. 2789 */ 2790 ctrl = er32(CTRL); 2791 2792 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2793 ctrl &= ~E1000_CTRL_MDIO_DIR; 2794 ctrl &= ~E1000_CTRL_MDIO; 2795 2796 ew32(CTRL, ctrl); 2797 E1000_WRITE_FLUSH(); 2798 2799 /* Raise and Lower the clock before reading in the data. This accounts for 2800 * the turnaround bits. The first clock occurred when we clocked out the 2801 * last bit of the Register Address. 2802 */ 2803 e1000_raise_mdi_clk(hw, &ctrl); 2804 e1000_lower_mdi_clk(hw, &ctrl); 2805 2806 for (data = 0, i = 0; i < 16; i++) { 2807 data = data << 1; 2808 e1000_raise_mdi_clk(hw, &ctrl); 2809 ctrl = er32(CTRL); 2810 /* Check to see if we shifted in a "1". */ 2811 if (ctrl & E1000_CTRL_MDIO) 2812 data |= 1; 2813 e1000_lower_mdi_clk(hw, &ctrl); 2814 } 2815 2816 e1000_raise_mdi_clk(hw, &ctrl); 2817 e1000_lower_mdi_clk(hw, &ctrl); 2818 2819 return data; 2820 } 2821 2822 2823 /** 2824 * e1000_read_phy_reg - read a phy register 2825 * @hw: Struct containing variables accessed by shared code 2826 * @reg_addr: address of the PHY register to read 2827 * 2828 * Reads the value from a PHY register, if the value is on a specific non zero 2829 * page, sets the page first. 2830 */ 2831 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2832 { 2833 u32 ret_val; 2834 unsigned long flags; 2835 2836 e_dbg("e1000_read_phy_reg"); 2837 2838 spin_lock_irqsave(&e1000_phy_lock, flags); 2839 2840 if ((hw->phy_type == e1000_phy_igp) && 2841 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2842 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2843 (u16) reg_addr); 2844 if (ret_val) { 2845 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2846 return ret_val; 2847 } 2848 } 2849 2850 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2851 phy_data); 2852 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2853 2854 return ret_val; 2855 } 2856 2857 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2858 u16 *phy_data) 2859 { 2860 u32 i; 2861 u32 mdic = 0; 2862 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2863 2864 e_dbg("e1000_read_phy_reg_ex"); 2865 2866 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2867 e_dbg("PHY Address %d is out of range\n", reg_addr); 2868 return -E1000_ERR_PARAM; 2869 } 2870 2871 if (hw->mac_type > e1000_82543) { 2872 /* Set up Op-code, Phy Address, and register address in the MDI 2873 * Control register. The MAC will take care of interfacing with the 2874 * PHY to retrieve the desired data. 2875 */ 2876 if (hw->mac_type == e1000_ce4100) { 2877 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2878 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2879 (INTEL_CE_GBE_MDIC_OP_READ) | 2880 (INTEL_CE_GBE_MDIC_GO)); 2881 2882 writel(mdic, E1000_MDIO_CMD); 2883 2884 /* Poll the ready bit to see if the MDI read 2885 * completed 2886 */ 2887 for (i = 0; i < 64; i++) { 2888 udelay(50); 2889 mdic = readl(E1000_MDIO_CMD); 2890 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 2891 break; 2892 } 2893 2894 if (mdic & INTEL_CE_GBE_MDIC_GO) { 2895 e_dbg("MDI Read did not complete\n"); 2896 return -E1000_ERR_PHY; 2897 } 2898 2899 mdic = readl(E1000_MDIO_STS); 2900 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { 2901 e_dbg("MDI Read Error\n"); 2902 return -E1000_ERR_PHY; 2903 } 2904 *phy_data = (u16) mdic; 2905 } else { 2906 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2907 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2908 (E1000_MDIC_OP_READ)); 2909 2910 ew32(MDIC, mdic); 2911 2912 /* Poll the ready bit to see if the MDI read 2913 * completed 2914 */ 2915 for (i = 0; i < 64; i++) { 2916 udelay(50); 2917 mdic = er32(MDIC); 2918 if (mdic & E1000_MDIC_READY) 2919 break; 2920 } 2921 if (!(mdic & E1000_MDIC_READY)) { 2922 e_dbg("MDI Read did not complete\n"); 2923 return -E1000_ERR_PHY; 2924 } 2925 if (mdic & E1000_MDIC_ERROR) { 2926 e_dbg("MDI Error\n"); 2927 return -E1000_ERR_PHY; 2928 } 2929 *phy_data = (u16) mdic; 2930 } 2931 } else { 2932 /* We must first send a preamble through the MDIO pin to signal the 2933 * beginning of an MII instruction. This is done by sending 32 2934 * consecutive "1" bits. 2935 */ 2936 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2937 2938 /* Now combine the next few fields that are required for a read 2939 * operation. We use this method instead of calling the 2940 * e1000_shift_out_mdi_bits routine five different times. The format of 2941 * a MII read instruction consists of a shift out of 14 bits and is 2942 * defined as follows: 2943 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2944 * followed by a shift in of 18 bits. This first two bits shifted in 2945 * are TurnAround bits used to avoid contention on the MDIO pin when a 2946 * READ operation is performed. These two bits are thrown away 2947 * followed by a shift in of 16 bits which contains the desired data. 2948 */ 2949 mdic = ((reg_addr) | (phy_addr << 5) | 2950 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2951 2952 e1000_shift_out_mdi_bits(hw, mdic, 14); 2953 2954 /* Now that we've shifted out the read command to the MII, we need to 2955 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2956 * register address. 2957 */ 2958 *phy_data = e1000_shift_in_mdi_bits(hw); 2959 } 2960 return E1000_SUCCESS; 2961 } 2962 2963 /** 2964 * e1000_write_phy_reg - write a phy register 2965 * 2966 * @hw: Struct containing variables accessed by shared code 2967 * @reg_addr: address of the PHY register to write 2968 * @data: data to write to the PHY 2969 * 2970 * Writes a value to a PHY register 2971 */ 2972 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2973 { 2974 u32 ret_val; 2975 unsigned long flags; 2976 2977 e_dbg("e1000_write_phy_reg"); 2978 2979 spin_lock_irqsave(&e1000_phy_lock, flags); 2980 2981 if ((hw->phy_type == e1000_phy_igp) && 2982 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2983 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2984 (u16) reg_addr); 2985 if (ret_val) { 2986 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2987 return ret_val; 2988 } 2989 } 2990 2991 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2992 phy_data); 2993 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2994 2995 return ret_val; 2996 } 2997 2998 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2999 u16 phy_data) 3000 { 3001 u32 i; 3002 u32 mdic = 0; 3003 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 3004 3005 e_dbg("e1000_write_phy_reg_ex"); 3006 3007 if (reg_addr > MAX_PHY_REG_ADDRESS) { 3008 e_dbg("PHY Address %d is out of range\n", reg_addr); 3009 return -E1000_ERR_PARAM; 3010 } 3011 3012 if (hw->mac_type > e1000_82543) { 3013 /* Set up Op-code, Phy Address, register address, and data 3014 * intended for the PHY register in the MDI Control register. 3015 * The MAC will take care of interfacing with the PHY to send 3016 * the desired data. 3017 */ 3018 if (hw->mac_type == e1000_ce4100) { 3019 mdic = (((u32) phy_data) | 3020 (reg_addr << E1000_MDIC_REG_SHIFT) | 3021 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3022 (INTEL_CE_GBE_MDIC_OP_WRITE) | 3023 (INTEL_CE_GBE_MDIC_GO)); 3024 3025 writel(mdic, E1000_MDIO_CMD); 3026 3027 /* Poll the ready bit to see if the MDI read 3028 * completed 3029 */ 3030 for (i = 0; i < 640; i++) { 3031 udelay(5); 3032 mdic = readl(E1000_MDIO_CMD); 3033 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 3034 break; 3035 } 3036 if (mdic & INTEL_CE_GBE_MDIC_GO) { 3037 e_dbg("MDI Write did not complete\n"); 3038 return -E1000_ERR_PHY; 3039 } 3040 } else { 3041 mdic = (((u32) phy_data) | 3042 (reg_addr << E1000_MDIC_REG_SHIFT) | 3043 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3044 (E1000_MDIC_OP_WRITE)); 3045 3046 ew32(MDIC, mdic); 3047 3048 /* Poll the ready bit to see if the MDI read 3049 * completed 3050 */ 3051 for (i = 0; i < 641; i++) { 3052 udelay(5); 3053 mdic = er32(MDIC); 3054 if (mdic & E1000_MDIC_READY) 3055 break; 3056 } 3057 if (!(mdic & E1000_MDIC_READY)) { 3058 e_dbg("MDI Write did not complete\n"); 3059 return -E1000_ERR_PHY; 3060 } 3061 } 3062 } else { 3063 /* We'll need to use the SW defined pins to shift the write command 3064 * out to the PHY. We first send a preamble to the PHY to signal the 3065 * beginning of the MII instruction. This is done by sending 32 3066 * consecutive "1" bits. 3067 */ 3068 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3069 3070 /* Now combine the remaining required fields that will indicate a 3071 * write operation. We use this method instead of calling the 3072 * e1000_shift_out_mdi_bits routine for each field in the command. The 3073 * format of a MII write instruction is as follows: 3074 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 3075 */ 3076 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3077 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3078 mdic <<= 16; 3079 mdic |= (u32) phy_data; 3080 3081 e1000_shift_out_mdi_bits(hw, mdic, 32); 3082 } 3083 3084 return E1000_SUCCESS; 3085 } 3086 3087 /** 3088 * e1000_phy_hw_reset - reset the phy, hardware style 3089 * @hw: Struct containing variables accessed by shared code 3090 * 3091 * Returns the PHY to the power-on reset state 3092 */ 3093 s32 e1000_phy_hw_reset(struct e1000_hw *hw) 3094 { 3095 u32 ctrl, ctrl_ext; 3096 u32 led_ctrl; 3097 3098 e_dbg("e1000_phy_hw_reset"); 3099 3100 e_dbg("Resetting Phy...\n"); 3101 3102 if (hw->mac_type > e1000_82543) { 3103 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3104 * bit. Then, take it out of reset. 3105 * For e1000 hardware, we delay for 10ms between the assert 3106 * and deassert. 3107 */ 3108 ctrl = er32(CTRL); 3109 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 3110 E1000_WRITE_FLUSH(); 3111 3112 msleep(10); 3113 3114 ew32(CTRL, ctrl); 3115 E1000_WRITE_FLUSH(); 3116 3117 } else { 3118 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3119 * bit to put the PHY into reset. Then, take it out of reset. 3120 */ 3121 ctrl_ext = er32(CTRL_EXT); 3122 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3123 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3124 ew32(CTRL_EXT, ctrl_ext); 3125 E1000_WRITE_FLUSH(); 3126 msleep(10); 3127 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3128 ew32(CTRL_EXT, ctrl_ext); 3129 E1000_WRITE_FLUSH(); 3130 } 3131 udelay(150); 3132 3133 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3134 /* Configure activity LED after PHY reset */ 3135 led_ctrl = er32(LEDCTL); 3136 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3137 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3138 ew32(LEDCTL, led_ctrl); 3139 } 3140 3141 /* Wait for FW to finish PHY configuration. */ 3142 return e1000_get_phy_cfg_done(hw); 3143 } 3144 3145 /** 3146 * e1000_phy_reset - reset the phy to commit settings 3147 * @hw: Struct containing variables accessed by shared code 3148 * 3149 * Resets the PHY 3150 * Sets bit 15 of the MII Control register 3151 */ 3152 s32 e1000_phy_reset(struct e1000_hw *hw) 3153 { 3154 s32 ret_val; 3155 u16 phy_data; 3156 3157 e_dbg("e1000_phy_reset"); 3158 3159 switch (hw->phy_type) { 3160 case e1000_phy_igp: 3161 ret_val = e1000_phy_hw_reset(hw); 3162 if (ret_val) 3163 return ret_val; 3164 break; 3165 default: 3166 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3167 if (ret_val) 3168 return ret_val; 3169 3170 phy_data |= MII_CR_RESET; 3171 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3172 if (ret_val) 3173 return ret_val; 3174 3175 udelay(1); 3176 break; 3177 } 3178 3179 if (hw->phy_type == e1000_phy_igp) 3180 e1000_phy_init_script(hw); 3181 3182 return E1000_SUCCESS; 3183 } 3184 3185 /** 3186 * e1000_detect_gig_phy - check the phy type 3187 * @hw: Struct containing variables accessed by shared code 3188 * 3189 * Probes the expected PHY address for known PHY IDs 3190 */ 3191 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3192 { 3193 s32 phy_init_status, ret_val; 3194 u16 phy_id_high, phy_id_low; 3195 bool match = false; 3196 3197 e_dbg("e1000_detect_gig_phy"); 3198 3199 if (hw->phy_id != 0) 3200 return E1000_SUCCESS; 3201 3202 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3203 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3204 if (ret_val) 3205 return ret_val; 3206 3207 hw->phy_id = (u32) (phy_id_high << 16); 3208 udelay(20); 3209 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3210 if (ret_val) 3211 return ret_val; 3212 3213 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); 3214 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; 3215 3216 switch (hw->mac_type) { 3217 case e1000_82543: 3218 if (hw->phy_id == M88E1000_E_PHY_ID) 3219 match = true; 3220 break; 3221 case e1000_82544: 3222 if (hw->phy_id == M88E1000_I_PHY_ID) 3223 match = true; 3224 break; 3225 case e1000_82540: 3226 case e1000_82545: 3227 case e1000_82545_rev_3: 3228 case e1000_82546: 3229 case e1000_82546_rev_3: 3230 if (hw->phy_id == M88E1011_I_PHY_ID) 3231 match = true; 3232 break; 3233 case e1000_ce4100: 3234 if ((hw->phy_id == RTL8211B_PHY_ID) || 3235 (hw->phy_id == RTL8201N_PHY_ID) || 3236 (hw->phy_id == M88E1118_E_PHY_ID)) 3237 match = true; 3238 break; 3239 case e1000_82541: 3240 case e1000_82541_rev_2: 3241 case e1000_82547: 3242 case e1000_82547_rev_2: 3243 if (hw->phy_id == IGP01E1000_I_PHY_ID) 3244 match = true; 3245 break; 3246 default: 3247 e_dbg("Invalid MAC type %d\n", hw->mac_type); 3248 return -E1000_ERR_CONFIG; 3249 } 3250 phy_init_status = e1000_set_phy_type(hw); 3251 3252 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3253 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); 3254 return E1000_SUCCESS; 3255 } 3256 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); 3257 return -E1000_ERR_PHY; 3258 } 3259 3260 /** 3261 * e1000_phy_reset_dsp - reset DSP 3262 * @hw: Struct containing variables accessed by shared code 3263 * 3264 * Resets the PHY's DSP 3265 */ 3266 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3267 { 3268 s32 ret_val; 3269 e_dbg("e1000_phy_reset_dsp"); 3270 3271 do { 3272 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3273 if (ret_val) 3274 break; 3275 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3276 if (ret_val) 3277 break; 3278 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3279 if (ret_val) 3280 break; 3281 ret_val = E1000_SUCCESS; 3282 } while (0); 3283 3284 return ret_val; 3285 } 3286 3287 /** 3288 * e1000_phy_igp_get_info - get igp specific registers 3289 * @hw: Struct containing variables accessed by shared code 3290 * @phy_info: PHY information structure 3291 * 3292 * Get PHY information from various PHY registers for igp PHY only. 3293 */ 3294 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3295 struct e1000_phy_info *phy_info) 3296 { 3297 s32 ret_val; 3298 u16 phy_data, min_length, max_length, average; 3299 e1000_rev_polarity polarity; 3300 3301 e_dbg("e1000_phy_igp_get_info"); 3302 3303 /* The downshift status is checked only once, after link is established, 3304 * and it stored in the hw->speed_downgraded parameter. */ 3305 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3306 3307 /* IGP01E1000 does not need to support it. */ 3308 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3309 3310 /* IGP01E1000 always correct polarity reversal */ 3311 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3312 3313 /* Check polarity status */ 3314 ret_val = e1000_check_polarity(hw, &polarity); 3315 if (ret_val) 3316 return ret_val; 3317 3318 phy_info->cable_polarity = polarity; 3319 3320 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3321 if (ret_val) 3322 return ret_val; 3323 3324 phy_info->mdix_mode = 3325 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3326 IGP01E1000_PSSR_MDIX_SHIFT); 3327 3328 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3329 IGP01E1000_PSSR_SPEED_1000MBPS) { 3330 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 3331 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3332 if (ret_val) 3333 return ret_val; 3334 3335 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3336 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3337 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3338 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3339 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3340 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3341 3342 /* Get cable length */ 3343 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3344 if (ret_val) 3345 return ret_val; 3346 3347 /* Translate to old method */ 3348 average = (max_length + min_length) / 2; 3349 3350 if (average <= e1000_igp_cable_length_50) 3351 phy_info->cable_length = e1000_cable_length_50; 3352 else if (average <= e1000_igp_cable_length_80) 3353 phy_info->cable_length = e1000_cable_length_50_80; 3354 else if (average <= e1000_igp_cable_length_110) 3355 phy_info->cable_length = e1000_cable_length_80_110; 3356 else if (average <= e1000_igp_cable_length_140) 3357 phy_info->cable_length = e1000_cable_length_110_140; 3358 else 3359 phy_info->cable_length = e1000_cable_length_140; 3360 } 3361 3362 return E1000_SUCCESS; 3363 } 3364 3365 /** 3366 * e1000_phy_m88_get_info - get m88 specific registers 3367 * @hw: Struct containing variables accessed by shared code 3368 * @phy_info: PHY information structure 3369 * 3370 * Get PHY information from various PHY registers for m88 PHY only. 3371 */ 3372 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3373 struct e1000_phy_info *phy_info) 3374 { 3375 s32 ret_val; 3376 u16 phy_data; 3377 e1000_rev_polarity polarity; 3378 3379 e_dbg("e1000_phy_m88_get_info"); 3380 3381 /* The downshift status is checked only once, after link is established, 3382 * and it stored in the hw->speed_downgraded parameter. */ 3383 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3384 3385 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3386 if (ret_val) 3387 return ret_val; 3388 3389 phy_info->extended_10bt_distance = 3390 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3391 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3392 e1000_10bt_ext_dist_enable_lower : 3393 e1000_10bt_ext_dist_enable_normal; 3394 3395 phy_info->polarity_correction = 3396 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3397 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3398 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3399 3400 /* Check polarity status */ 3401 ret_val = e1000_check_polarity(hw, &polarity); 3402 if (ret_val) 3403 return ret_val; 3404 phy_info->cable_polarity = polarity; 3405 3406 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3407 if (ret_val) 3408 return ret_val; 3409 3410 phy_info->mdix_mode = 3411 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3412 M88E1000_PSSR_MDIX_SHIFT); 3413 3414 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3415 /* Cable Length Estimation and Local/Remote Receiver Information 3416 * are only valid at 1000 Mbps. 3417 */ 3418 phy_info->cable_length = 3419 (e1000_cable_length) ((phy_data & 3420 M88E1000_PSSR_CABLE_LENGTH) >> 3421 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3422 3423 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3424 if (ret_val) 3425 return ret_val; 3426 3427 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3428 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3429 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3430 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3431 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3432 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3433 3434 } 3435 3436 return E1000_SUCCESS; 3437 } 3438 3439 /** 3440 * e1000_phy_get_info - request phy info 3441 * @hw: Struct containing variables accessed by shared code 3442 * @phy_info: PHY information structure 3443 * 3444 * Get PHY information from various PHY registers 3445 */ 3446 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3447 { 3448 s32 ret_val; 3449 u16 phy_data; 3450 3451 e_dbg("e1000_phy_get_info"); 3452 3453 phy_info->cable_length = e1000_cable_length_undefined; 3454 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3455 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3456 phy_info->downshift = e1000_downshift_undefined; 3457 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3458 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3459 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3460 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3461 3462 if (hw->media_type != e1000_media_type_copper) { 3463 e_dbg("PHY info is only valid for copper media\n"); 3464 return -E1000_ERR_CONFIG; 3465 } 3466 3467 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3468 if (ret_val) 3469 return ret_val; 3470 3471 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3472 if (ret_val) 3473 return ret_val; 3474 3475 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3476 e_dbg("PHY info is only valid if link is up\n"); 3477 return -E1000_ERR_CONFIG; 3478 } 3479 3480 if (hw->phy_type == e1000_phy_igp) 3481 return e1000_phy_igp_get_info(hw, phy_info); 3482 else if ((hw->phy_type == e1000_phy_8211) || 3483 (hw->phy_type == e1000_phy_8201)) 3484 return E1000_SUCCESS; 3485 else 3486 return e1000_phy_m88_get_info(hw, phy_info); 3487 } 3488 3489 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3490 { 3491 e_dbg("e1000_validate_mdi_settings"); 3492 3493 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3494 e_dbg("Invalid MDI setting detected\n"); 3495 hw->mdix = 1; 3496 return -E1000_ERR_CONFIG; 3497 } 3498 return E1000_SUCCESS; 3499 } 3500 3501 /** 3502 * e1000_init_eeprom_params - initialize sw eeprom vars 3503 * @hw: Struct containing variables accessed by shared code 3504 * 3505 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3506 * is configured. 3507 */ 3508 s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3509 { 3510 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3511 u32 eecd = er32(EECD); 3512 s32 ret_val = E1000_SUCCESS; 3513 u16 eeprom_size; 3514 3515 e_dbg("e1000_init_eeprom_params"); 3516 3517 switch (hw->mac_type) { 3518 case e1000_82542_rev2_0: 3519 case e1000_82542_rev2_1: 3520 case e1000_82543: 3521 case e1000_82544: 3522 eeprom->type = e1000_eeprom_microwire; 3523 eeprom->word_size = 64; 3524 eeprom->opcode_bits = 3; 3525 eeprom->address_bits = 6; 3526 eeprom->delay_usec = 50; 3527 break; 3528 case e1000_82540: 3529 case e1000_82545: 3530 case e1000_82545_rev_3: 3531 case e1000_82546: 3532 case e1000_82546_rev_3: 3533 eeprom->type = e1000_eeprom_microwire; 3534 eeprom->opcode_bits = 3; 3535 eeprom->delay_usec = 50; 3536 if (eecd & E1000_EECD_SIZE) { 3537 eeprom->word_size = 256; 3538 eeprom->address_bits = 8; 3539 } else { 3540 eeprom->word_size = 64; 3541 eeprom->address_bits = 6; 3542 } 3543 break; 3544 case e1000_82541: 3545 case e1000_82541_rev_2: 3546 case e1000_82547: 3547 case e1000_82547_rev_2: 3548 if (eecd & E1000_EECD_TYPE) { 3549 eeprom->type = e1000_eeprom_spi; 3550 eeprom->opcode_bits = 8; 3551 eeprom->delay_usec = 1; 3552 if (eecd & E1000_EECD_ADDR_BITS) { 3553 eeprom->page_size = 32; 3554 eeprom->address_bits = 16; 3555 } else { 3556 eeprom->page_size = 8; 3557 eeprom->address_bits = 8; 3558 } 3559 } else { 3560 eeprom->type = e1000_eeprom_microwire; 3561 eeprom->opcode_bits = 3; 3562 eeprom->delay_usec = 50; 3563 if (eecd & E1000_EECD_ADDR_BITS) { 3564 eeprom->word_size = 256; 3565 eeprom->address_bits = 8; 3566 } else { 3567 eeprom->word_size = 64; 3568 eeprom->address_bits = 6; 3569 } 3570 } 3571 break; 3572 default: 3573 break; 3574 } 3575 3576 if (eeprom->type == e1000_eeprom_spi) { 3577 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 3578 * 32KB (incremented by powers of 2). 3579 */ 3580 /* Set to default value for initial eeprom read. */ 3581 eeprom->word_size = 64; 3582 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3583 if (ret_val) 3584 return ret_val; 3585 eeprom_size = 3586 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3587 /* 256B eeprom size was not supported in earlier hardware, so we 3588 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 3589 * is never the result used in the shifting logic below. */ 3590 if (eeprom_size) 3591 eeprom_size++; 3592 3593 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3594 } 3595 return ret_val; 3596 } 3597 3598 /** 3599 * e1000_raise_ee_clk - Raises the EEPROM's clock input. 3600 * @hw: Struct containing variables accessed by shared code 3601 * @eecd: EECD's current value 3602 */ 3603 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3604 { 3605 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3606 * wait <delay> microseconds. 3607 */ 3608 *eecd = *eecd | E1000_EECD_SK; 3609 ew32(EECD, *eecd); 3610 E1000_WRITE_FLUSH(); 3611 udelay(hw->eeprom.delay_usec); 3612 } 3613 3614 /** 3615 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. 3616 * @hw: Struct containing variables accessed by shared code 3617 * @eecd: EECD's current value 3618 */ 3619 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3620 { 3621 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 3622 * wait 50 microseconds. 3623 */ 3624 *eecd = *eecd & ~E1000_EECD_SK; 3625 ew32(EECD, *eecd); 3626 E1000_WRITE_FLUSH(); 3627 udelay(hw->eeprom.delay_usec); 3628 } 3629 3630 /** 3631 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. 3632 * @hw: Struct containing variables accessed by shared code 3633 * @data: data to send to the EEPROM 3634 * @count: number of bits to shift out 3635 */ 3636 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3637 { 3638 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3639 u32 eecd; 3640 u32 mask; 3641 3642 /* We need to shift "count" bits out to the EEPROM. So, value in the 3643 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3644 * In order to do this, "data" must be broken down into bits. 3645 */ 3646 mask = 0x01 << (count - 1); 3647 eecd = er32(EECD); 3648 if (eeprom->type == e1000_eeprom_microwire) { 3649 eecd &= ~E1000_EECD_DO; 3650 } else if (eeprom->type == e1000_eeprom_spi) { 3651 eecd |= E1000_EECD_DO; 3652 } 3653 do { 3654 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 3655 * and then raising and then lowering the clock (the SK bit controls 3656 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 3657 * by setting "DI" to "0" and then raising and then lowering the clock. 3658 */ 3659 eecd &= ~E1000_EECD_DI; 3660 3661 if (data & mask) 3662 eecd |= E1000_EECD_DI; 3663 3664 ew32(EECD, eecd); 3665 E1000_WRITE_FLUSH(); 3666 3667 udelay(eeprom->delay_usec); 3668 3669 e1000_raise_ee_clk(hw, &eecd); 3670 e1000_lower_ee_clk(hw, &eecd); 3671 3672 mask = mask >> 1; 3673 3674 } while (mask); 3675 3676 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3677 eecd &= ~E1000_EECD_DI; 3678 ew32(EECD, eecd); 3679 } 3680 3681 /** 3682 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM 3683 * @hw: Struct containing variables accessed by shared code 3684 * @count: number of bits to shift in 3685 */ 3686 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3687 { 3688 u32 eecd; 3689 u32 i; 3690 u16 data; 3691 3692 /* In order to read a register from the EEPROM, we need to shift 'count' 3693 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3694 * input to the EEPROM (setting the SK bit), and then reading the value of 3695 * the "DO" bit. During this "shifting in" process the "DI" bit should 3696 * always be clear. 3697 */ 3698 3699 eecd = er32(EECD); 3700 3701 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3702 data = 0; 3703 3704 for (i = 0; i < count; i++) { 3705 data = data << 1; 3706 e1000_raise_ee_clk(hw, &eecd); 3707 3708 eecd = er32(EECD); 3709 3710 eecd &= ~(E1000_EECD_DI); 3711 if (eecd & E1000_EECD_DO) 3712 data |= 1; 3713 3714 e1000_lower_ee_clk(hw, &eecd); 3715 } 3716 3717 return data; 3718 } 3719 3720 /** 3721 * e1000_acquire_eeprom - Prepares EEPROM for access 3722 * @hw: Struct containing variables accessed by shared code 3723 * 3724 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3725 * function should be called before issuing a command to the EEPROM. 3726 */ 3727 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3728 { 3729 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3730 u32 eecd, i = 0; 3731 3732 e_dbg("e1000_acquire_eeprom"); 3733 3734 eecd = er32(EECD); 3735 3736 /* Request EEPROM Access */ 3737 if (hw->mac_type > e1000_82544) { 3738 eecd |= E1000_EECD_REQ; 3739 ew32(EECD, eecd); 3740 eecd = er32(EECD); 3741 while ((!(eecd & E1000_EECD_GNT)) && 3742 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3743 i++; 3744 udelay(5); 3745 eecd = er32(EECD); 3746 } 3747 if (!(eecd & E1000_EECD_GNT)) { 3748 eecd &= ~E1000_EECD_REQ; 3749 ew32(EECD, eecd); 3750 e_dbg("Could not acquire EEPROM grant\n"); 3751 return -E1000_ERR_EEPROM; 3752 } 3753 } 3754 3755 /* Setup EEPROM for Read/Write */ 3756 3757 if (eeprom->type == e1000_eeprom_microwire) { 3758 /* Clear SK and DI */ 3759 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3760 ew32(EECD, eecd); 3761 3762 /* Set CS */ 3763 eecd |= E1000_EECD_CS; 3764 ew32(EECD, eecd); 3765 } else if (eeprom->type == e1000_eeprom_spi) { 3766 /* Clear SK and CS */ 3767 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3768 ew32(EECD, eecd); 3769 E1000_WRITE_FLUSH(); 3770 udelay(1); 3771 } 3772 3773 return E1000_SUCCESS; 3774 } 3775 3776 /** 3777 * e1000_standby_eeprom - Returns EEPROM to a "standby" state 3778 * @hw: Struct containing variables accessed by shared code 3779 */ 3780 static void e1000_standby_eeprom(struct e1000_hw *hw) 3781 { 3782 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3783 u32 eecd; 3784 3785 eecd = er32(EECD); 3786 3787 if (eeprom->type == e1000_eeprom_microwire) { 3788 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3789 ew32(EECD, eecd); 3790 E1000_WRITE_FLUSH(); 3791 udelay(eeprom->delay_usec); 3792 3793 /* Clock high */ 3794 eecd |= E1000_EECD_SK; 3795 ew32(EECD, eecd); 3796 E1000_WRITE_FLUSH(); 3797 udelay(eeprom->delay_usec); 3798 3799 /* Select EEPROM */ 3800 eecd |= E1000_EECD_CS; 3801 ew32(EECD, eecd); 3802 E1000_WRITE_FLUSH(); 3803 udelay(eeprom->delay_usec); 3804 3805 /* Clock low */ 3806 eecd &= ~E1000_EECD_SK; 3807 ew32(EECD, eecd); 3808 E1000_WRITE_FLUSH(); 3809 udelay(eeprom->delay_usec); 3810 } else if (eeprom->type == e1000_eeprom_spi) { 3811 /* Toggle CS to flush commands */ 3812 eecd |= E1000_EECD_CS; 3813 ew32(EECD, eecd); 3814 E1000_WRITE_FLUSH(); 3815 udelay(eeprom->delay_usec); 3816 eecd &= ~E1000_EECD_CS; 3817 ew32(EECD, eecd); 3818 E1000_WRITE_FLUSH(); 3819 udelay(eeprom->delay_usec); 3820 } 3821 } 3822 3823 /** 3824 * e1000_release_eeprom - drop chip select 3825 * @hw: Struct containing variables accessed by shared code 3826 * 3827 * Terminates a command by inverting the EEPROM's chip select pin 3828 */ 3829 static void e1000_release_eeprom(struct e1000_hw *hw) 3830 { 3831 u32 eecd; 3832 3833 e_dbg("e1000_release_eeprom"); 3834 3835 eecd = er32(EECD); 3836 3837 if (hw->eeprom.type == e1000_eeprom_spi) { 3838 eecd |= E1000_EECD_CS; /* Pull CS high */ 3839 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3840 3841 ew32(EECD, eecd); 3842 E1000_WRITE_FLUSH(); 3843 3844 udelay(hw->eeprom.delay_usec); 3845 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3846 /* cleanup eeprom */ 3847 3848 /* CS on Microwire is active-high */ 3849 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3850 3851 ew32(EECD, eecd); 3852 3853 /* Rising edge of clock */ 3854 eecd |= E1000_EECD_SK; 3855 ew32(EECD, eecd); 3856 E1000_WRITE_FLUSH(); 3857 udelay(hw->eeprom.delay_usec); 3858 3859 /* Falling edge of clock */ 3860 eecd &= ~E1000_EECD_SK; 3861 ew32(EECD, eecd); 3862 E1000_WRITE_FLUSH(); 3863 udelay(hw->eeprom.delay_usec); 3864 } 3865 3866 /* Stop requesting EEPROM access */ 3867 if (hw->mac_type > e1000_82544) { 3868 eecd &= ~E1000_EECD_REQ; 3869 ew32(EECD, eecd); 3870 } 3871 } 3872 3873 /** 3874 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. 3875 * @hw: Struct containing variables accessed by shared code 3876 */ 3877 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3878 { 3879 u16 retry_count = 0; 3880 u8 spi_stat_reg; 3881 3882 e_dbg("e1000_spi_eeprom_ready"); 3883 3884 /* Read "Status Register" repeatedly until the LSB is cleared. The 3885 * EEPROM will signal that the command has been completed by clearing 3886 * bit 0 of the internal status register. If it's not cleared within 3887 * 5 milliseconds, then error out. 3888 */ 3889 retry_count = 0; 3890 do { 3891 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3892 hw->eeprom.opcode_bits); 3893 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); 3894 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3895 break; 3896 3897 udelay(5); 3898 retry_count += 5; 3899 3900 e1000_standby_eeprom(hw); 3901 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3902 3903 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3904 * only 0-5mSec on 5V devices) 3905 */ 3906 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3907 e_dbg("SPI EEPROM Status error\n"); 3908 return -E1000_ERR_EEPROM; 3909 } 3910 3911 return E1000_SUCCESS; 3912 } 3913 3914 /** 3915 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. 3916 * @hw: Struct containing variables accessed by shared code 3917 * @offset: offset of word in the EEPROM to read 3918 * @data: word read from the EEPROM 3919 * @words: number of words to read 3920 */ 3921 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3922 { 3923 s32 ret; 3924 spin_lock(&e1000_eeprom_lock); 3925 ret = e1000_do_read_eeprom(hw, offset, words, data); 3926 spin_unlock(&e1000_eeprom_lock); 3927 return ret; 3928 } 3929 3930 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3931 u16 *data) 3932 { 3933 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3934 u32 i = 0; 3935 3936 e_dbg("e1000_read_eeprom"); 3937 3938 if (hw->mac_type == e1000_ce4100) { 3939 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, 3940 data); 3941 return E1000_SUCCESS; 3942 } 3943 3944 /* If eeprom is not yet detected, do so now */ 3945 if (eeprom->word_size == 0) 3946 e1000_init_eeprom_params(hw); 3947 3948 /* A check for invalid values: offset too large, too many words, and not 3949 * enough words. 3950 */ 3951 if ((offset >= eeprom->word_size) 3952 || (words > eeprom->word_size - offset) || (words == 0)) { 3953 e_dbg("\"words\" parameter out of bounds. Words = %d," 3954 "size = %d\n", offset, eeprom->word_size); 3955 return -E1000_ERR_EEPROM; 3956 } 3957 3958 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3959 * directly. In this case, we need to acquire the EEPROM so that 3960 * FW or other port software does not interrupt. 3961 */ 3962 /* Prepare the EEPROM for bit-bang reading */ 3963 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3964 return -E1000_ERR_EEPROM; 3965 3966 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3967 * acquired the EEPROM at this point, so any returns should release it */ 3968 if (eeprom->type == e1000_eeprom_spi) { 3969 u16 word_in; 3970 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3971 3972 if (e1000_spi_eeprom_ready(hw)) { 3973 e1000_release_eeprom(hw); 3974 return -E1000_ERR_EEPROM; 3975 } 3976 3977 e1000_standby_eeprom(hw); 3978 3979 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3980 if ((eeprom->address_bits == 8) && (offset >= 128)) 3981 read_opcode |= EEPROM_A8_OPCODE_SPI; 3982 3983 /* Send the READ command (opcode + addr) */ 3984 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3985 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), 3986 eeprom->address_bits); 3987 3988 /* Read the data. The address of the eeprom internally increments with 3989 * each byte (spi) being read, saving on the overhead of eeprom setup 3990 * and tear-down. The address counter will roll over if reading beyond 3991 * the size of the eeprom, thus allowing the entire memory to be read 3992 * starting from any offset. */ 3993 for (i = 0; i < words; i++) { 3994 word_in = e1000_shift_in_ee_bits(hw, 16); 3995 data[i] = (word_in >> 8) | (word_in << 8); 3996 } 3997 } else if (eeprom->type == e1000_eeprom_microwire) { 3998 for (i = 0; i < words; i++) { 3999 /* Send the READ command (opcode + addr) */ 4000 e1000_shift_out_ee_bits(hw, 4001 EEPROM_READ_OPCODE_MICROWIRE, 4002 eeprom->opcode_bits); 4003 e1000_shift_out_ee_bits(hw, (u16) (offset + i), 4004 eeprom->address_bits); 4005 4006 /* Read the data. For microwire, each word requires the overhead 4007 * of eeprom setup and tear-down. */ 4008 data[i] = e1000_shift_in_ee_bits(hw, 16); 4009 e1000_standby_eeprom(hw); 4010 } 4011 } 4012 4013 /* End this read operation */ 4014 e1000_release_eeprom(hw); 4015 4016 return E1000_SUCCESS; 4017 } 4018 4019 /** 4020 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum 4021 * @hw: Struct containing variables accessed by shared code 4022 * 4023 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 4024 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 4025 * valid. 4026 */ 4027 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 4028 { 4029 u16 checksum = 0; 4030 u16 i, eeprom_data; 4031 4032 e_dbg("e1000_validate_eeprom_checksum"); 4033 4034 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 4035 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4036 e_dbg("EEPROM Read Error\n"); 4037 return -E1000_ERR_EEPROM; 4038 } 4039 checksum += eeprom_data; 4040 } 4041 4042 #ifdef CONFIG_PARISC 4043 /* This is a signature and not a checksum on HP c8000 */ 4044 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) 4045 return E1000_SUCCESS; 4046 4047 #endif 4048 if (checksum == (u16) EEPROM_SUM) 4049 return E1000_SUCCESS; 4050 else { 4051 e_dbg("EEPROM Checksum Invalid\n"); 4052 return -E1000_ERR_EEPROM; 4053 } 4054 } 4055 4056 /** 4057 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum 4058 * @hw: Struct containing variables accessed by shared code 4059 * 4060 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 4061 * Writes the difference to word offset 63 of the EEPROM. 4062 */ 4063 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 4064 { 4065 u16 checksum = 0; 4066 u16 i, eeprom_data; 4067 4068 e_dbg("e1000_update_eeprom_checksum"); 4069 4070 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 4071 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4072 e_dbg("EEPROM Read Error\n"); 4073 return -E1000_ERR_EEPROM; 4074 } 4075 checksum += eeprom_data; 4076 } 4077 checksum = (u16) EEPROM_SUM - checksum; 4078 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4079 e_dbg("EEPROM Write Error\n"); 4080 return -E1000_ERR_EEPROM; 4081 } 4082 return E1000_SUCCESS; 4083 } 4084 4085 /** 4086 * e1000_write_eeprom - write words to the different EEPROM types. 4087 * @hw: Struct containing variables accessed by shared code 4088 * @offset: offset within the EEPROM to be written to 4089 * @words: number of words to write 4090 * @data: 16 bit word to be written to the EEPROM 4091 * 4092 * If e1000_update_eeprom_checksum is not called after this function, the 4093 * EEPROM will most likely contain an invalid checksum. 4094 */ 4095 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4096 { 4097 s32 ret; 4098 spin_lock(&e1000_eeprom_lock); 4099 ret = e1000_do_write_eeprom(hw, offset, words, data); 4100 spin_unlock(&e1000_eeprom_lock); 4101 return ret; 4102 } 4103 4104 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 4105 u16 *data) 4106 { 4107 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4108 s32 status = 0; 4109 4110 e_dbg("e1000_write_eeprom"); 4111 4112 if (hw->mac_type == e1000_ce4100) { 4113 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, 4114 data); 4115 return E1000_SUCCESS; 4116 } 4117 4118 /* If eeprom is not yet detected, do so now */ 4119 if (eeprom->word_size == 0) 4120 e1000_init_eeprom_params(hw); 4121 4122 /* A check for invalid values: offset too large, too many words, and not 4123 * enough words. 4124 */ 4125 if ((offset >= eeprom->word_size) 4126 || (words > eeprom->word_size - offset) || (words == 0)) { 4127 e_dbg("\"words\" parameter out of bounds\n"); 4128 return -E1000_ERR_EEPROM; 4129 } 4130 4131 /* Prepare the EEPROM for writing */ 4132 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4133 return -E1000_ERR_EEPROM; 4134 4135 if (eeprom->type == e1000_eeprom_microwire) { 4136 status = e1000_write_eeprom_microwire(hw, offset, words, data); 4137 } else { 4138 status = e1000_write_eeprom_spi(hw, offset, words, data); 4139 msleep(10); 4140 } 4141 4142 /* Done with writing */ 4143 e1000_release_eeprom(hw); 4144 4145 return status; 4146 } 4147 4148 /** 4149 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. 4150 * @hw: Struct containing variables accessed by shared code 4151 * @offset: offset within the EEPROM to be written to 4152 * @words: number of words to write 4153 * @data: pointer to array of 8 bit words to be written to the EEPROM 4154 */ 4155 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 4156 u16 *data) 4157 { 4158 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4159 u16 widx = 0; 4160 4161 e_dbg("e1000_write_eeprom_spi"); 4162 4163 while (widx < words) { 4164 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 4165 4166 if (e1000_spi_eeprom_ready(hw)) 4167 return -E1000_ERR_EEPROM; 4168 4169 e1000_standby_eeprom(hw); 4170 4171 /* Send the WRITE ENABLE command (8 bit opcode ) */ 4172 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 4173 eeprom->opcode_bits); 4174 4175 e1000_standby_eeprom(hw); 4176 4177 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4178 if ((eeprom->address_bits == 8) && (offset >= 128)) 4179 write_opcode |= EEPROM_A8_OPCODE_SPI; 4180 4181 /* Send the Write command (8-bit opcode + addr) */ 4182 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 4183 4184 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), 4185 eeprom->address_bits); 4186 4187 /* Send the data */ 4188 4189 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 4190 while (widx < words) { 4191 u16 word_out = data[widx]; 4192 word_out = (word_out >> 8) | (word_out << 8); 4193 e1000_shift_out_ee_bits(hw, word_out, 16); 4194 widx++; 4195 4196 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 4197 * operation, while the smaller eeproms are capable of an 8-byte 4198 * PAGE WRITE operation. Break the inner loop to pass new address 4199 */ 4200 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 4201 e1000_standby_eeprom(hw); 4202 break; 4203 } 4204 } 4205 } 4206 4207 return E1000_SUCCESS; 4208 } 4209 4210 /** 4211 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. 4212 * @hw: Struct containing variables accessed by shared code 4213 * @offset: offset within the EEPROM to be written to 4214 * @words: number of words to write 4215 * @data: pointer to array of 8 bit words to be written to the EEPROM 4216 */ 4217 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4218 u16 words, u16 *data) 4219 { 4220 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4221 u32 eecd; 4222 u16 words_written = 0; 4223 u16 i = 0; 4224 4225 e_dbg("e1000_write_eeprom_microwire"); 4226 4227 /* Send the write enable command to the EEPROM (3-bit opcode plus 4228 * 6/8-bit dummy address beginning with 11). It's less work to include 4229 * the 11 of the dummy address as part of the opcode than it is to shift 4230 * it over the correct number of bits for the address. This puts the 4231 * EEPROM into write/erase mode. 4232 */ 4233 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4234 (u16) (eeprom->opcode_bits + 2)); 4235 4236 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4237 4238 /* Prepare the EEPROM */ 4239 e1000_standby_eeprom(hw); 4240 4241 while (words_written < words) { 4242 /* Send the Write command (3-bit opcode + addr) */ 4243 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4244 eeprom->opcode_bits); 4245 4246 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), 4247 eeprom->address_bits); 4248 4249 /* Send the data */ 4250 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4251 4252 /* Toggle the CS line. This in effect tells the EEPROM to execute 4253 * the previous command. 4254 */ 4255 e1000_standby_eeprom(hw); 4256 4257 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 4258 * signal that the command has been completed by raising the DO signal. 4259 * If DO does not go high in 10 milliseconds, then error out. 4260 */ 4261 for (i = 0; i < 200; i++) { 4262 eecd = er32(EECD); 4263 if (eecd & E1000_EECD_DO) 4264 break; 4265 udelay(50); 4266 } 4267 if (i == 200) { 4268 e_dbg("EEPROM Write did not complete\n"); 4269 return -E1000_ERR_EEPROM; 4270 } 4271 4272 /* Recover from write */ 4273 e1000_standby_eeprom(hw); 4274 4275 words_written++; 4276 } 4277 4278 /* Send the write disable command to the EEPROM (3-bit opcode plus 4279 * 6/8-bit dummy address beginning with 10). It's less work to include 4280 * the 10 of the dummy address as part of the opcode than it is to shift 4281 * it over the correct number of bits for the address. This takes the 4282 * EEPROM out of write/erase mode. 4283 */ 4284 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4285 (u16) (eeprom->opcode_bits + 2)); 4286 4287 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4288 4289 return E1000_SUCCESS; 4290 } 4291 4292 /** 4293 * e1000_read_mac_addr - read the adapters MAC from eeprom 4294 * @hw: Struct containing variables accessed by shared code 4295 * 4296 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4297 * second function of dual function devices 4298 */ 4299 s32 e1000_read_mac_addr(struct e1000_hw *hw) 4300 { 4301 u16 offset; 4302 u16 eeprom_data, i; 4303 4304 e_dbg("e1000_read_mac_addr"); 4305 4306 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4307 offset = i >> 1; 4308 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4309 e_dbg("EEPROM Read Error\n"); 4310 return -E1000_ERR_EEPROM; 4311 } 4312 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 4313 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); 4314 } 4315 4316 switch (hw->mac_type) { 4317 default: 4318 break; 4319 case e1000_82546: 4320 case e1000_82546_rev_3: 4321 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4322 hw->perm_mac_addr[5] ^= 0x01; 4323 break; 4324 } 4325 4326 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4327 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4328 return E1000_SUCCESS; 4329 } 4330 4331 /** 4332 * e1000_init_rx_addrs - Initializes receive address filters. 4333 * @hw: Struct containing variables accessed by shared code 4334 * 4335 * Places the MAC address in receive address register 0 and clears the rest 4336 * of the receive address registers. Clears the multicast table. Assumes 4337 * the receiver is in reset when the routine is called. 4338 */ 4339 static void e1000_init_rx_addrs(struct e1000_hw *hw) 4340 { 4341 u32 i; 4342 u32 rar_num; 4343 4344 e_dbg("e1000_init_rx_addrs"); 4345 4346 /* Setup the receive address. */ 4347 e_dbg("Programming MAC Address into RAR[0]\n"); 4348 4349 e1000_rar_set(hw, hw->mac_addr, 0); 4350 4351 rar_num = E1000_RAR_ENTRIES; 4352 4353 /* Zero out the other 15 receive addresses. */ 4354 e_dbg("Clearing RAR[1-15]\n"); 4355 for (i = 1; i < rar_num; i++) { 4356 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4357 E1000_WRITE_FLUSH(); 4358 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4359 E1000_WRITE_FLUSH(); 4360 } 4361 } 4362 4363 /** 4364 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table 4365 * @hw: Struct containing variables accessed by shared code 4366 * @mc_addr: the multicast address to hash 4367 */ 4368 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4369 { 4370 u32 hash_value = 0; 4371 4372 /* The portion of the address that is used for the hash table is 4373 * determined by the mc_filter_type setting. 4374 */ 4375 switch (hw->mc_filter_type) { 4376 /* [0] [1] [2] [3] [4] [5] 4377 * 01 AA 00 12 34 56 4378 * LSB MSB 4379 */ 4380 case 0: 4381 /* [47:36] i.e. 0x563 for above example address */ 4382 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 4383 break; 4384 case 1: 4385 /* [46:35] i.e. 0xAC6 for above example address */ 4386 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); 4387 break; 4388 case 2: 4389 /* [45:34] i.e. 0x5D8 for above example address */ 4390 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 4391 break; 4392 case 3: 4393 /* [43:32] i.e. 0x634 for above example address */ 4394 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); 4395 break; 4396 } 4397 4398 hash_value &= 0xFFF; 4399 return hash_value; 4400 } 4401 4402 /** 4403 * e1000_rar_set - Puts an ethernet address into a receive address register. 4404 * @hw: Struct containing variables accessed by shared code 4405 * @addr: Address to put into receive address register 4406 * @index: Receive address register to write 4407 */ 4408 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4409 { 4410 u32 rar_low, rar_high; 4411 4412 /* HW expects these in little endian so we reverse the byte order 4413 * from network order (big endian) to little endian 4414 */ 4415 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 4416 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 4417 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 4418 4419 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4420 * unit hang. 4421 * 4422 * Description: 4423 * If there are any Rx frames queued up or otherwise present in the HW 4424 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4425 * hang. To work around this issue, we have to disable receives and 4426 * flush out all Rx frames before we enable RSS. To do so, we modify we 4427 * redirect all Rx traffic to manageability and then reset the HW. 4428 * This flushes away Rx frames, and (since the redirections to 4429 * manageability persists across resets) keeps new ones from coming in 4430 * while we work. Then, we clear the Address Valid AV bit for all MAC 4431 * addresses and undo the re-direction to manageability. 4432 * Now, frames are coming in again, but the MAC won't accept them, so 4433 * far so good. We now proceed to initialize RSS (if necessary) and 4434 * configure the Rx unit. Last, we re-enable the AV bits and continue 4435 * on our merry way. 4436 */ 4437 switch (hw->mac_type) { 4438 default: 4439 /* Indicate to hardware the Address is Valid. */ 4440 rar_high |= E1000_RAH_AV; 4441 break; 4442 } 4443 4444 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4445 E1000_WRITE_FLUSH(); 4446 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4447 E1000_WRITE_FLUSH(); 4448 } 4449 4450 /** 4451 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. 4452 * @hw: Struct containing variables accessed by shared code 4453 * @offset: Offset in VLAN filer table to write 4454 * @value: Value to write into VLAN filter table 4455 */ 4456 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4457 { 4458 u32 temp; 4459 4460 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4461 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4462 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4463 E1000_WRITE_FLUSH(); 4464 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4465 E1000_WRITE_FLUSH(); 4466 } else { 4467 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4468 E1000_WRITE_FLUSH(); 4469 } 4470 } 4471 4472 /** 4473 * e1000_clear_vfta - Clears the VLAN filer table 4474 * @hw: Struct containing variables accessed by shared code 4475 */ 4476 static void e1000_clear_vfta(struct e1000_hw *hw) 4477 { 4478 u32 offset; 4479 u32 vfta_value = 0; 4480 u32 vfta_offset = 0; 4481 u32 vfta_bit_in_reg = 0; 4482 4483 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4484 /* If the offset we want to clear is the same offset of the 4485 * manageability VLAN ID, then clear all bits except that of the 4486 * manageability unit */ 4487 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4488 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4489 E1000_WRITE_FLUSH(); 4490 } 4491 } 4492 4493 static s32 e1000_id_led_init(struct e1000_hw *hw) 4494 { 4495 u32 ledctl; 4496 const u32 ledctl_mask = 0x000000FF; 4497 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4498 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4499 u16 eeprom_data, i, temp; 4500 const u16 led_mask = 0x0F; 4501 4502 e_dbg("e1000_id_led_init"); 4503 4504 if (hw->mac_type < e1000_82540) { 4505 /* Nothing to do */ 4506 return E1000_SUCCESS; 4507 } 4508 4509 ledctl = er32(LEDCTL); 4510 hw->ledctl_default = ledctl; 4511 hw->ledctl_mode1 = hw->ledctl_default; 4512 hw->ledctl_mode2 = hw->ledctl_default; 4513 4514 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4515 e_dbg("EEPROM Read Error\n"); 4516 return -E1000_ERR_EEPROM; 4517 } 4518 4519 if ((eeprom_data == ID_LED_RESERVED_0000) || 4520 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4521 eeprom_data = ID_LED_DEFAULT; 4522 } 4523 4524 for (i = 0; i < 4; i++) { 4525 temp = (eeprom_data >> (i << 2)) & led_mask; 4526 switch (temp) { 4527 case ID_LED_ON1_DEF2: 4528 case ID_LED_ON1_ON2: 4529 case ID_LED_ON1_OFF2: 4530 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4531 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4532 break; 4533 case ID_LED_OFF1_DEF2: 4534 case ID_LED_OFF1_ON2: 4535 case ID_LED_OFF1_OFF2: 4536 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4537 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4538 break; 4539 default: 4540 /* Do nothing */ 4541 break; 4542 } 4543 switch (temp) { 4544 case ID_LED_DEF1_ON2: 4545 case ID_LED_ON1_ON2: 4546 case ID_LED_OFF1_ON2: 4547 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4548 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4549 break; 4550 case ID_LED_DEF1_OFF2: 4551 case ID_LED_ON1_OFF2: 4552 case ID_LED_OFF1_OFF2: 4553 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4554 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4555 break; 4556 default: 4557 /* Do nothing */ 4558 break; 4559 } 4560 } 4561 return E1000_SUCCESS; 4562 } 4563 4564 /** 4565 * e1000_setup_led 4566 * @hw: Struct containing variables accessed by shared code 4567 * 4568 * Prepares SW controlable LED for use and saves the current state of the LED. 4569 */ 4570 s32 e1000_setup_led(struct e1000_hw *hw) 4571 { 4572 u32 ledctl; 4573 s32 ret_val = E1000_SUCCESS; 4574 4575 e_dbg("e1000_setup_led"); 4576 4577 switch (hw->mac_type) { 4578 case e1000_82542_rev2_0: 4579 case e1000_82542_rev2_1: 4580 case e1000_82543: 4581 case e1000_82544: 4582 /* No setup necessary */ 4583 break; 4584 case e1000_82541: 4585 case e1000_82547: 4586 case e1000_82541_rev_2: 4587 case e1000_82547_rev_2: 4588 /* Turn off PHY Smart Power Down (if enabled) */ 4589 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4590 &hw->phy_spd_default); 4591 if (ret_val) 4592 return ret_val; 4593 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4594 (u16) (hw->phy_spd_default & 4595 ~IGP01E1000_GMII_SPD)); 4596 if (ret_val) 4597 return ret_val; 4598 /* Fall Through */ 4599 default: 4600 if (hw->media_type == e1000_media_type_fiber) { 4601 ledctl = er32(LEDCTL); 4602 /* Save current LEDCTL settings */ 4603 hw->ledctl_default = ledctl; 4604 /* Turn off LED0 */ 4605 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4606 E1000_LEDCTL_LED0_BLINK | 4607 E1000_LEDCTL_LED0_MODE_MASK); 4608 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4609 E1000_LEDCTL_LED0_MODE_SHIFT); 4610 ew32(LEDCTL, ledctl); 4611 } else if (hw->media_type == e1000_media_type_copper) 4612 ew32(LEDCTL, hw->ledctl_mode1); 4613 break; 4614 } 4615 4616 return E1000_SUCCESS; 4617 } 4618 4619 /** 4620 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. 4621 * @hw: Struct containing variables accessed by shared code 4622 */ 4623 s32 e1000_cleanup_led(struct e1000_hw *hw) 4624 { 4625 s32 ret_val = E1000_SUCCESS; 4626 4627 e_dbg("e1000_cleanup_led"); 4628 4629 switch (hw->mac_type) { 4630 case e1000_82542_rev2_0: 4631 case e1000_82542_rev2_1: 4632 case e1000_82543: 4633 case e1000_82544: 4634 /* No cleanup necessary */ 4635 break; 4636 case e1000_82541: 4637 case e1000_82547: 4638 case e1000_82541_rev_2: 4639 case e1000_82547_rev_2: 4640 /* Turn on PHY Smart Power Down (if previously enabled) */ 4641 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4642 hw->phy_spd_default); 4643 if (ret_val) 4644 return ret_val; 4645 /* Fall Through */ 4646 default: 4647 /* Restore LEDCTL settings */ 4648 ew32(LEDCTL, hw->ledctl_default); 4649 break; 4650 } 4651 4652 return E1000_SUCCESS; 4653 } 4654 4655 /** 4656 * e1000_led_on - Turns on the software controllable LED 4657 * @hw: Struct containing variables accessed by shared code 4658 */ 4659 s32 e1000_led_on(struct e1000_hw *hw) 4660 { 4661 u32 ctrl = er32(CTRL); 4662 4663 e_dbg("e1000_led_on"); 4664 4665 switch (hw->mac_type) { 4666 case e1000_82542_rev2_0: 4667 case e1000_82542_rev2_1: 4668 case e1000_82543: 4669 /* Set SW Defineable Pin 0 to turn on the LED */ 4670 ctrl |= E1000_CTRL_SWDPIN0; 4671 ctrl |= E1000_CTRL_SWDPIO0; 4672 break; 4673 case e1000_82544: 4674 if (hw->media_type == e1000_media_type_fiber) { 4675 /* Set SW Defineable Pin 0 to turn on the LED */ 4676 ctrl |= E1000_CTRL_SWDPIN0; 4677 ctrl |= E1000_CTRL_SWDPIO0; 4678 } else { 4679 /* Clear SW Defineable Pin 0 to turn on the LED */ 4680 ctrl &= ~E1000_CTRL_SWDPIN0; 4681 ctrl |= E1000_CTRL_SWDPIO0; 4682 } 4683 break; 4684 default: 4685 if (hw->media_type == e1000_media_type_fiber) { 4686 /* Clear SW Defineable Pin 0 to turn on the LED */ 4687 ctrl &= ~E1000_CTRL_SWDPIN0; 4688 ctrl |= E1000_CTRL_SWDPIO0; 4689 } else if (hw->media_type == e1000_media_type_copper) { 4690 ew32(LEDCTL, hw->ledctl_mode2); 4691 return E1000_SUCCESS; 4692 } 4693 break; 4694 } 4695 4696 ew32(CTRL, ctrl); 4697 4698 return E1000_SUCCESS; 4699 } 4700 4701 /** 4702 * e1000_led_off - Turns off the software controllable LED 4703 * @hw: Struct containing variables accessed by shared code 4704 */ 4705 s32 e1000_led_off(struct e1000_hw *hw) 4706 { 4707 u32 ctrl = er32(CTRL); 4708 4709 e_dbg("e1000_led_off"); 4710 4711 switch (hw->mac_type) { 4712 case e1000_82542_rev2_0: 4713 case e1000_82542_rev2_1: 4714 case e1000_82543: 4715 /* Clear SW Defineable Pin 0 to turn off the LED */ 4716 ctrl &= ~E1000_CTRL_SWDPIN0; 4717 ctrl |= E1000_CTRL_SWDPIO0; 4718 break; 4719 case e1000_82544: 4720 if (hw->media_type == e1000_media_type_fiber) { 4721 /* Clear SW Defineable Pin 0 to turn off the LED */ 4722 ctrl &= ~E1000_CTRL_SWDPIN0; 4723 ctrl |= E1000_CTRL_SWDPIO0; 4724 } else { 4725 /* Set SW Defineable Pin 0 to turn off the LED */ 4726 ctrl |= E1000_CTRL_SWDPIN0; 4727 ctrl |= E1000_CTRL_SWDPIO0; 4728 } 4729 break; 4730 default: 4731 if (hw->media_type == e1000_media_type_fiber) { 4732 /* Set SW Defineable Pin 0 to turn off the LED */ 4733 ctrl |= E1000_CTRL_SWDPIN0; 4734 ctrl |= E1000_CTRL_SWDPIO0; 4735 } else if (hw->media_type == e1000_media_type_copper) { 4736 ew32(LEDCTL, hw->ledctl_mode1); 4737 return E1000_SUCCESS; 4738 } 4739 break; 4740 } 4741 4742 ew32(CTRL, ctrl); 4743 4744 return E1000_SUCCESS; 4745 } 4746 4747 /** 4748 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. 4749 * @hw: Struct containing variables accessed by shared code 4750 */ 4751 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4752 { 4753 volatile u32 temp; 4754 4755 temp = er32(CRCERRS); 4756 temp = er32(SYMERRS); 4757 temp = er32(MPC); 4758 temp = er32(SCC); 4759 temp = er32(ECOL); 4760 temp = er32(MCC); 4761 temp = er32(LATECOL); 4762 temp = er32(COLC); 4763 temp = er32(DC); 4764 temp = er32(SEC); 4765 temp = er32(RLEC); 4766 temp = er32(XONRXC); 4767 temp = er32(XONTXC); 4768 temp = er32(XOFFRXC); 4769 temp = er32(XOFFTXC); 4770 temp = er32(FCRUC); 4771 4772 temp = er32(PRC64); 4773 temp = er32(PRC127); 4774 temp = er32(PRC255); 4775 temp = er32(PRC511); 4776 temp = er32(PRC1023); 4777 temp = er32(PRC1522); 4778 4779 temp = er32(GPRC); 4780 temp = er32(BPRC); 4781 temp = er32(MPRC); 4782 temp = er32(GPTC); 4783 temp = er32(GORCL); 4784 temp = er32(GORCH); 4785 temp = er32(GOTCL); 4786 temp = er32(GOTCH); 4787 temp = er32(RNBC); 4788 temp = er32(RUC); 4789 temp = er32(RFC); 4790 temp = er32(ROC); 4791 temp = er32(RJC); 4792 temp = er32(TORL); 4793 temp = er32(TORH); 4794 temp = er32(TOTL); 4795 temp = er32(TOTH); 4796 temp = er32(TPR); 4797 temp = er32(TPT); 4798 4799 temp = er32(PTC64); 4800 temp = er32(PTC127); 4801 temp = er32(PTC255); 4802 temp = er32(PTC511); 4803 temp = er32(PTC1023); 4804 temp = er32(PTC1522); 4805 4806 temp = er32(MPTC); 4807 temp = er32(BPTC); 4808 4809 if (hw->mac_type < e1000_82543) 4810 return; 4811 4812 temp = er32(ALGNERRC); 4813 temp = er32(RXERRC); 4814 temp = er32(TNCRS); 4815 temp = er32(CEXTERR); 4816 temp = er32(TSCTC); 4817 temp = er32(TSCTFC); 4818 4819 if (hw->mac_type <= e1000_82544) 4820 return; 4821 4822 temp = er32(MGTPRC); 4823 temp = er32(MGTPDC); 4824 temp = er32(MGTPTC); 4825 } 4826 4827 /** 4828 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. 4829 * @hw: Struct containing variables accessed by shared code 4830 * 4831 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4832 * hw->ifs_params_forced to true. However, you must initialize hw-> 4833 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4834 * before calling this function. 4835 */ 4836 void e1000_reset_adaptive(struct e1000_hw *hw) 4837 { 4838 e_dbg("e1000_reset_adaptive"); 4839 4840 if (hw->adaptive_ifs) { 4841 if (!hw->ifs_params_forced) { 4842 hw->current_ifs_val = 0; 4843 hw->ifs_min_val = IFS_MIN; 4844 hw->ifs_max_val = IFS_MAX; 4845 hw->ifs_step_size = IFS_STEP; 4846 hw->ifs_ratio = IFS_RATIO; 4847 } 4848 hw->in_ifs_mode = false; 4849 ew32(AIT, 0); 4850 } else { 4851 e_dbg("Not in Adaptive IFS mode!\n"); 4852 } 4853 } 4854 4855 /** 4856 * e1000_update_adaptive - update adaptive IFS 4857 * @hw: Struct containing variables accessed by shared code 4858 * @tx_packets: Number of transmits since last callback 4859 * @total_collisions: Number of collisions since last callback 4860 * 4861 * Called during the callback/watchdog routine to update IFS value based on 4862 * the ratio of transmits to collisions. 4863 */ 4864 void e1000_update_adaptive(struct e1000_hw *hw) 4865 { 4866 e_dbg("e1000_update_adaptive"); 4867 4868 if (hw->adaptive_ifs) { 4869 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { 4870 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4871 hw->in_ifs_mode = true; 4872 if (hw->current_ifs_val < hw->ifs_max_val) { 4873 if (hw->current_ifs_val == 0) 4874 hw->current_ifs_val = 4875 hw->ifs_min_val; 4876 else 4877 hw->current_ifs_val += 4878 hw->ifs_step_size; 4879 ew32(AIT, hw->current_ifs_val); 4880 } 4881 } 4882 } else { 4883 if (hw->in_ifs_mode 4884 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4885 hw->current_ifs_val = 0; 4886 hw->in_ifs_mode = false; 4887 ew32(AIT, 0); 4888 } 4889 } 4890 } else { 4891 e_dbg("Not in Adaptive IFS mode!\n"); 4892 } 4893 } 4894 4895 /** 4896 * e1000_tbi_adjust_stats 4897 * @hw: Struct containing variables accessed by shared code 4898 * @frame_len: The length of the frame in question 4899 * @mac_addr: The Ethernet destination address of the frame in question 4900 * 4901 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4902 */ 4903 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, 4904 u32 frame_len, u8 *mac_addr) 4905 { 4906 u64 carry_bit; 4907 4908 /* First adjust the frame length. */ 4909 frame_len--; 4910 /* We need to adjust the statistics counters, since the hardware 4911 * counters overcount this packet as a CRC error and undercount 4912 * the packet as a good packet 4913 */ 4914 /* This packet should not be counted as a CRC error. */ 4915 stats->crcerrs--; 4916 /* This packet does count as a Good Packet Received. */ 4917 stats->gprc++; 4918 4919 /* Adjust the Good Octets received counters */ 4920 carry_bit = 0x80000000 & stats->gorcl; 4921 stats->gorcl += frame_len; 4922 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4923 * Received Count) was one before the addition, 4924 * AND it is zero after, then we lost the carry out, 4925 * need to add one to Gorch (Good Octets Received Count High). 4926 * This could be simplified if all environments supported 4927 * 64-bit integers. 4928 */ 4929 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4930 stats->gorch++; 4931 /* Is this a broadcast or multicast? Check broadcast first, 4932 * since the test for a multicast frame will test positive on 4933 * a broadcast frame. 4934 */ 4935 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) 4936 /* Broadcast packet */ 4937 stats->bprc++; 4938 else if (*mac_addr & 0x01) 4939 /* Multicast packet */ 4940 stats->mprc++; 4941 4942 if (frame_len == hw->max_frame_size) { 4943 /* In this case, the hardware has overcounted the number of 4944 * oversize frames. 4945 */ 4946 if (stats->roc > 0) 4947 stats->roc--; 4948 } 4949 4950 /* Adjust the bin counters when the extra byte put the frame in the 4951 * wrong bin. Remember that the frame_len was adjusted above. 4952 */ 4953 if (frame_len == 64) { 4954 stats->prc64++; 4955 stats->prc127--; 4956 } else if (frame_len == 127) { 4957 stats->prc127++; 4958 stats->prc255--; 4959 } else if (frame_len == 255) { 4960 stats->prc255++; 4961 stats->prc511--; 4962 } else if (frame_len == 511) { 4963 stats->prc511++; 4964 stats->prc1023--; 4965 } else if (frame_len == 1023) { 4966 stats->prc1023++; 4967 stats->prc1522--; 4968 } else if (frame_len == 1522) { 4969 stats->prc1522++; 4970 } 4971 } 4972 4973 /** 4974 * e1000_get_bus_info 4975 * @hw: Struct containing variables accessed by shared code 4976 * 4977 * Gets the current PCI bus type, speed, and width of the hardware 4978 */ 4979 void e1000_get_bus_info(struct e1000_hw *hw) 4980 { 4981 u32 status; 4982 4983 switch (hw->mac_type) { 4984 case e1000_82542_rev2_0: 4985 case e1000_82542_rev2_1: 4986 hw->bus_type = e1000_bus_type_pci; 4987 hw->bus_speed = e1000_bus_speed_unknown; 4988 hw->bus_width = e1000_bus_width_unknown; 4989 break; 4990 default: 4991 status = er32(STATUS); 4992 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4993 e1000_bus_type_pcix : e1000_bus_type_pci; 4994 4995 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4996 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4997 e1000_bus_speed_66 : e1000_bus_speed_120; 4998 } else if (hw->bus_type == e1000_bus_type_pci) { 4999 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 5000 e1000_bus_speed_66 : e1000_bus_speed_33; 5001 } else { 5002 switch (status & E1000_STATUS_PCIX_SPEED) { 5003 case E1000_STATUS_PCIX_SPEED_66: 5004 hw->bus_speed = e1000_bus_speed_66; 5005 break; 5006 case E1000_STATUS_PCIX_SPEED_100: 5007 hw->bus_speed = e1000_bus_speed_100; 5008 break; 5009 case E1000_STATUS_PCIX_SPEED_133: 5010 hw->bus_speed = e1000_bus_speed_133; 5011 break; 5012 default: 5013 hw->bus_speed = e1000_bus_speed_reserved; 5014 break; 5015 } 5016 } 5017 hw->bus_width = (status & E1000_STATUS_BUS64) ? 5018 e1000_bus_width_64 : e1000_bus_width_32; 5019 break; 5020 } 5021 } 5022 5023 /** 5024 * e1000_write_reg_io 5025 * @hw: Struct containing variables accessed by shared code 5026 * @offset: offset to write to 5027 * @value: value to write 5028 * 5029 * Writes a value to one of the devices registers using port I/O (as opposed to 5030 * memory mapped I/O). Only 82544 and newer devices support port I/O. 5031 */ 5032 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 5033 { 5034 unsigned long io_addr = hw->io_base; 5035 unsigned long io_data = hw->io_base + 4; 5036 5037 e1000_io_write(hw, io_addr, offset); 5038 e1000_io_write(hw, io_data, value); 5039 } 5040 5041 /** 5042 * e1000_get_cable_length - Estimates the cable length. 5043 * @hw: Struct containing variables accessed by shared code 5044 * @min_length: The estimated minimum length 5045 * @max_length: The estimated maximum length 5046 * 5047 * returns: - E1000_ERR_XXX 5048 * E1000_SUCCESS 5049 * 5050 * This function always returns a ranged length (minimum & maximum). 5051 * So for M88 phy's, this function interprets the one value returned from the 5052 * register to the minimum and maximum range. 5053 * For IGP phy's, the function calculates the range by the AGC registers. 5054 */ 5055 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 5056 u16 *max_length) 5057 { 5058 s32 ret_val; 5059 u16 agc_value = 0; 5060 u16 i, phy_data; 5061 u16 cable_length; 5062 5063 e_dbg("e1000_get_cable_length"); 5064 5065 *min_length = *max_length = 0; 5066 5067 /* Use old method for Phy older than IGP */ 5068 if (hw->phy_type == e1000_phy_m88) { 5069 5070 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5071 &phy_data); 5072 if (ret_val) 5073 return ret_val; 5074 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 5075 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 5076 5077 /* Convert the enum value to ranged values */ 5078 switch (cable_length) { 5079 case e1000_cable_length_50: 5080 *min_length = 0; 5081 *max_length = e1000_igp_cable_length_50; 5082 break; 5083 case e1000_cable_length_50_80: 5084 *min_length = e1000_igp_cable_length_50; 5085 *max_length = e1000_igp_cable_length_80; 5086 break; 5087 case e1000_cable_length_80_110: 5088 *min_length = e1000_igp_cable_length_80; 5089 *max_length = e1000_igp_cable_length_110; 5090 break; 5091 case e1000_cable_length_110_140: 5092 *min_length = e1000_igp_cable_length_110; 5093 *max_length = e1000_igp_cable_length_140; 5094 break; 5095 case e1000_cable_length_140: 5096 *min_length = e1000_igp_cable_length_140; 5097 *max_length = e1000_igp_cable_length_170; 5098 break; 5099 default: 5100 return -E1000_ERR_PHY; 5101 break; 5102 } 5103 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 5104 u16 cur_agc_value; 5105 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 5106 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5107 IGP01E1000_PHY_AGC_A, 5108 IGP01E1000_PHY_AGC_B, 5109 IGP01E1000_PHY_AGC_C, 5110 IGP01E1000_PHY_AGC_D 5111 }; 5112 /* Read the AGC registers for all channels */ 5113 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5114 5115 ret_val = 5116 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 5117 if (ret_val) 5118 return ret_val; 5119 5120 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 5121 5122 /* Value bound check. */ 5123 if ((cur_agc_value >= 5124 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) 5125 || (cur_agc_value == 0)) 5126 return -E1000_ERR_PHY; 5127 5128 agc_value += cur_agc_value; 5129 5130 /* Update minimal AGC value. */ 5131 if (min_agc_value > cur_agc_value) 5132 min_agc_value = cur_agc_value; 5133 } 5134 5135 /* Remove the minimal AGC result for length < 50m */ 5136 if (agc_value < 5137 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 5138 agc_value -= min_agc_value; 5139 5140 /* Get the average length of the remaining 3 channels */ 5141 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 5142 } else { 5143 /* Get the average length of all the 4 channels. */ 5144 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 5145 } 5146 5147 /* Set the range of the calculated length. */ 5148 *min_length = ((e1000_igp_cable_length_table[agc_value] - 5149 IGP01E1000_AGC_RANGE) > 0) ? 5150 (e1000_igp_cable_length_table[agc_value] - 5151 IGP01E1000_AGC_RANGE) : 0; 5152 *max_length = e1000_igp_cable_length_table[agc_value] + 5153 IGP01E1000_AGC_RANGE; 5154 } 5155 5156 return E1000_SUCCESS; 5157 } 5158 5159 /** 5160 * e1000_check_polarity - Check the cable polarity 5161 * @hw: Struct containing variables accessed by shared code 5162 * @polarity: output parameter : 0 - Polarity is not reversed 5163 * 1 - Polarity is reversed. 5164 * 5165 * returns: - E1000_ERR_XXX 5166 * E1000_SUCCESS 5167 * 5168 * For phy's older than IGP, this function simply reads the polarity bit in the 5169 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 5170 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 5171 * return 0. If the link speed is 1000 Mbps the polarity status is in the 5172 * IGP01E1000_PHY_PCS_INIT_REG. 5173 */ 5174 static s32 e1000_check_polarity(struct e1000_hw *hw, 5175 e1000_rev_polarity *polarity) 5176 { 5177 s32 ret_val; 5178 u16 phy_data; 5179 5180 e_dbg("e1000_check_polarity"); 5181 5182 if (hw->phy_type == e1000_phy_m88) { 5183 /* return the Polarity bit in the Status register. */ 5184 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5185 &phy_data); 5186 if (ret_val) 5187 return ret_val; 5188 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5189 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5190 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5191 5192 } else if (hw->phy_type == e1000_phy_igp) { 5193 /* Read the Status register to check the speed */ 5194 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5195 &phy_data); 5196 if (ret_val) 5197 return ret_val; 5198 5199 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 5200 * find the polarity status */ 5201 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 5202 IGP01E1000_PSSR_SPEED_1000MBPS) { 5203 5204 /* Read the GIG initialization PCS register (0x00B4) */ 5205 ret_val = 5206 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 5207 &phy_data); 5208 if (ret_val) 5209 return ret_val; 5210 5211 /* Check the polarity bits */ 5212 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5213 e1000_rev_polarity_reversed : 5214 e1000_rev_polarity_normal; 5215 } else { 5216 /* For 10 Mbps, read the polarity bit in the status register. (for 5217 * 100 Mbps this bit is always 0) */ 5218 *polarity = 5219 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5220 e1000_rev_polarity_reversed : 5221 e1000_rev_polarity_normal; 5222 } 5223 } 5224 return E1000_SUCCESS; 5225 } 5226 5227 /** 5228 * e1000_check_downshift - Check if Downshift occurred 5229 * @hw: Struct containing variables accessed by shared code 5230 * @downshift: output parameter : 0 - No Downshift occurred. 5231 * 1 - Downshift occurred. 5232 * 5233 * returns: - E1000_ERR_XXX 5234 * E1000_SUCCESS 5235 * 5236 * For phy's older than IGP, this function reads the Downshift bit in the Phy 5237 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5238 * Link Health register. In IGP this bit is latched high, so the driver must 5239 * read it immediately after link is established. 5240 */ 5241 static s32 e1000_check_downshift(struct e1000_hw *hw) 5242 { 5243 s32 ret_val; 5244 u16 phy_data; 5245 5246 e_dbg("e1000_check_downshift"); 5247 5248 if (hw->phy_type == e1000_phy_igp) { 5249 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5250 &phy_data); 5251 if (ret_val) 5252 return ret_val; 5253 5254 hw->speed_downgraded = 5255 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5256 } else if (hw->phy_type == e1000_phy_m88) { 5257 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5258 &phy_data); 5259 if (ret_val) 5260 return ret_val; 5261 5262 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5263 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5264 } 5265 5266 return E1000_SUCCESS; 5267 } 5268 5269 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5270 IGP01E1000_PHY_AGC_PARAM_A, 5271 IGP01E1000_PHY_AGC_PARAM_B, 5272 IGP01E1000_PHY_AGC_PARAM_C, 5273 IGP01E1000_PHY_AGC_PARAM_D 5274 }; 5275 5276 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) 5277 { 5278 u16 min_length, max_length; 5279 u16 phy_data, i; 5280 s32 ret_val; 5281 5282 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 5283 if (ret_val) 5284 return ret_val; 5285 5286 if (hw->dsp_config_state != e1000_dsp_config_enabled) 5287 return 0; 5288 5289 if (min_length >= e1000_igp_cable_length_50) { 5290 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5291 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 5292 &phy_data); 5293 if (ret_val) 5294 return ret_val; 5295 5296 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5297 5298 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 5299 phy_data); 5300 if (ret_val) 5301 return ret_val; 5302 } 5303 hw->dsp_config_state = e1000_dsp_config_activated; 5304 } else { 5305 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5306 u32 idle_errs = 0; 5307 5308 /* clear previous idle error counts */ 5309 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 5310 if (ret_val) 5311 return ret_val; 5312 5313 for (i = 0; i < ffe_idle_err_timeout; i++) { 5314 udelay(1000); 5315 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5316 &phy_data); 5317 if (ret_val) 5318 return ret_val; 5319 5320 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 5321 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 5322 hw->ffe_config_state = e1000_ffe_config_active; 5323 5324 ret_val = e1000_write_phy_reg(hw, 5325 IGP01E1000_PHY_DSP_FFE, 5326 IGP01E1000_PHY_DSP_FFE_CM_CP); 5327 if (ret_val) 5328 return ret_val; 5329 break; 5330 } 5331 5332 if (idle_errs) 5333 ffe_idle_err_timeout = 5334 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5335 } 5336 } 5337 5338 return 0; 5339 } 5340 5341 /** 5342 * e1000_config_dsp_after_link_change 5343 * @hw: Struct containing variables accessed by shared code 5344 * @link_up: was link up at the time this was called 5345 * 5346 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5347 * E1000_SUCCESS at any other case. 5348 * 5349 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5350 * gigabit link is achieved to improve link quality. 5351 */ 5352 5353 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5354 { 5355 s32 ret_val; 5356 u16 phy_data, phy_saved_data, speed, duplex, i; 5357 5358 e_dbg("e1000_config_dsp_after_link_change"); 5359 5360 if (hw->phy_type != e1000_phy_igp) 5361 return E1000_SUCCESS; 5362 5363 if (link_up) { 5364 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5365 if (ret_val) { 5366 e_dbg("Error getting link speed and duplex\n"); 5367 return ret_val; 5368 } 5369 5370 if (speed == SPEED_1000) { 5371 ret_val = e1000_1000Mb_check_cable_length(hw); 5372 if (ret_val) 5373 return ret_val; 5374 } 5375 } else { 5376 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5377 /* Save off the current value of register 0x2F5B to be restored at 5378 * the end of the routines. */ 5379 ret_val = 5380 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5381 5382 if (ret_val) 5383 return ret_val; 5384 5385 /* Disable the PHY transmitter */ 5386 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5387 5388 if (ret_val) 5389 return ret_val; 5390 5391 msleep(20); 5392 5393 ret_val = e1000_write_phy_reg(hw, 0x0000, 5394 IGP01E1000_IEEE_FORCE_GIGA); 5395 if (ret_val) 5396 return ret_val; 5397 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5398 ret_val = 5399 e1000_read_phy_reg(hw, dsp_reg_array[i], 5400 &phy_data); 5401 if (ret_val) 5402 return ret_val; 5403 5404 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5405 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5406 5407 ret_val = 5408 e1000_write_phy_reg(hw, dsp_reg_array[i], 5409 phy_data); 5410 if (ret_val) 5411 return ret_val; 5412 } 5413 5414 ret_val = e1000_write_phy_reg(hw, 0x0000, 5415 IGP01E1000_IEEE_RESTART_AUTONEG); 5416 if (ret_val) 5417 return ret_val; 5418 5419 msleep(20); 5420 5421 /* Now enable the transmitter */ 5422 ret_val = 5423 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5424 5425 if (ret_val) 5426 return ret_val; 5427 5428 hw->dsp_config_state = e1000_dsp_config_enabled; 5429 } 5430 5431 if (hw->ffe_config_state == e1000_ffe_config_active) { 5432 /* Save off the current value of register 0x2F5B to be restored at 5433 * the end of the routines. */ 5434 ret_val = 5435 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5436 5437 if (ret_val) 5438 return ret_val; 5439 5440 /* Disable the PHY transmitter */ 5441 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5442 5443 if (ret_val) 5444 return ret_val; 5445 5446 msleep(20); 5447 5448 ret_val = e1000_write_phy_reg(hw, 0x0000, 5449 IGP01E1000_IEEE_FORCE_GIGA); 5450 if (ret_val) 5451 return ret_val; 5452 ret_val = 5453 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5454 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5455 if (ret_val) 5456 return ret_val; 5457 5458 ret_val = e1000_write_phy_reg(hw, 0x0000, 5459 IGP01E1000_IEEE_RESTART_AUTONEG); 5460 if (ret_val) 5461 return ret_val; 5462 5463 msleep(20); 5464 5465 /* Now enable the transmitter */ 5466 ret_val = 5467 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5468 5469 if (ret_val) 5470 return ret_val; 5471 5472 hw->ffe_config_state = e1000_ffe_config_enabled; 5473 } 5474 } 5475 return E1000_SUCCESS; 5476 } 5477 5478 /** 5479 * e1000_set_phy_mode - Set PHY to class A mode 5480 * @hw: Struct containing variables accessed by shared code 5481 * 5482 * Assumes the following operations will follow to enable the new class mode. 5483 * 1. Do a PHY soft reset 5484 * 2. Restart auto-negotiation or force link. 5485 */ 5486 static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5487 { 5488 s32 ret_val; 5489 u16 eeprom_data; 5490 5491 e_dbg("e1000_set_phy_mode"); 5492 5493 if ((hw->mac_type == e1000_82545_rev_3) && 5494 (hw->media_type == e1000_media_type_copper)) { 5495 ret_val = 5496 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 5497 &eeprom_data); 5498 if (ret_val) { 5499 return ret_val; 5500 } 5501 5502 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5503 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5504 ret_val = 5505 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 5506 0x000B); 5507 if (ret_val) 5508 return ret_val; 5509 ret_val = 5510 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 5511 0x8104); 5512 if (ret_val) 5513 return ret_val; 5514 5515 hw->phy_reset_disable = false; 5516 } 5517 } 5518 5519 return E1000_SUCCESS; 5520 } 5521 5522 /** 5523 * e1000_set_d3_lplu_state - set d3 link power state 5524 * @hw: Struct containing variables accessed by shared code 5525 * @active: true to enable lplu false to disable lplu. 5526 * 5527 * This function sets the lplu state according to the active flag. When 5528 * activating lplu this function also disables smart speed and vise versa. 5529 * lplu will not be activated unless the device autonegotiation advertisement 5530 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5531 * 5532 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5533 * E1000_SUCCESS at any other case. 5534 */ 5535 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5536 { 5537 s32 ret_val; 5538 u16 phy_data; 5539 e_dbg("e1000_set_d3_lplu_state"); 5540 5541 if (hw->phy_type != e1000_phy_igp) 5542 return E1000_SUCCESS; 5543 5544 /* During driver activity LPLU should not be used or it will attain link 5545 * from the lowest speeds starting from 10Mbps. The capability is used for 5546 * Dx transitions and states */ 5547 if (hw->mac_type == e1000_82541_rev_2 5548 || hw->mac_type == e1000_82547_rev_2) { 5549 ret_val = 5550 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5551 if (ret_val) 5552 return ret_val; 5553 } 5554 5555 if (!active) { 5556 if (hw->mac_type == e1000_82541_rev_2 || 5557 hw->mac_type == e1000_82547_rev_2) { 5558 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5559 ret_val = 5560 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5561 phy_data); 5562 if (ret_val) 5563 return ret_val; 5564 } 5565 5566 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5567 * Dx states where the power conservation is most important. During 5568 * driver activity we should enable SmartSpeed, so performance is 5569 * maintained. */ 5570 if (hw->smart_speed == e1000_smart_speed_on) { 5571 ret_val = 5572 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5573 &phy_data); 5574 if (ret_val) 5575 return ret_val; 5576 5577 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5578 ret_val = 5579 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5580 phy_data); 5581 if (ret_val) 5582 return ret_val; 5583 } else if (hw->smart_speed == e1000_smart_speed_off) { 5584 ret_val = 5585 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5586 &phy_data); 5587 if (ret_val) 5588 return ret_val; 5589 5590 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5591 ret_val = 5592 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5593 phy_data); 5594 if (ret_val) 5595 return ret_val; 5596 } 5597 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 5598 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) 5599 || (hw->autoneg_advertised == 5600 AUTONEG_ADVERTISE_10_100_ALL)) { 5601 5602 if (hw->mac_type == e1000_82541_rev_2 || 5603 hw->mac_type == e1000_82547_rev_2) { 5604 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5605 ret_val = 5606 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5607 phy_data); 5608 if (ret_val) 5609 return ret_val; 5610 } 5611 5612 /* When LPLU is enabled we should disable SmartSpeed */ 5613 ret_val = 5614 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5615 &phy_data); 5616 if (ret_val) 5617 return ret_val; 5618 5619 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5620 ret_val = 5621 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5622 phy_data); 5623 if (ret_val) 5624 return ret_val; 5625 5626 } 5627 return E1000_SUCCESS; 5628 } 5629 5630 /** 5631 * e1000_set_vco_speed 5632 * @hw: Struct containing variables accessed by shared code 5633 * 5634 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5635 */ 5636 static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5637 { 5638 s32 ret_val; 5639 u16 default_page = 0; 5640 u16 phy_data; 5641 5642 e_dbg("e1000_set_vco_speed"); 5643 5644 switch (hw->mac_type) { 5645 case e1000_82545_rev_3: 5646 case e1000_82546_rev_3: 5647 break; 5648 default: 5649 return E1000_SUCCESS; 5650 } 5651 5652 /* Set PHY register 30, page 5, bit 8 to 0 */ 5653 5654 ret_val = 5655 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5656 if (ret_val) 5657 return ret_val; 5658 5659 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5660 if (ret_val) 5661 return ret_val; 5662 5663 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5664 if (ret_val) 5665 return ret_val; 5666 5667 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5668 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5669 if (ret_val) 5670 return ret_val; 5671 5672 /* Set PHY register 30, page 4, bit 11 to 1 */ 5673 5674 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5675 if (ret_val) 5676 return ret_val; 5677 5678 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5679 if (ret_val) 5680 return ret_val; 5681 5682 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5683 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5684 if (ret_val) 5685 return ret_val; 5686 5687 ret_val = 5688 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5689 if (ret_val) 5690 return ret_val; 5691 5692 return E1000_SUCCESS; 5693 } 5694 5695 5696 /** 5697 * e1000_enable_mng_pass_thru - check for bmc pass through 5698 * @hw: Struct containing variables accessed by shared code 5699 * 5700 * Verifies the hardware needs to allow ARPs to be processed by the host 5701 * returns: - true/false 5702 */ 5703 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5704 { 5705 u32 manc; 5706 5707 if (hw->asf_firmware_present) { 5708 manc = er32(MANC); 5709 5710 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5711 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5712 return false; 5713 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5714 return true; 5715 } 5716 return false; 5717 } 5718 5719 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5720 { 5721 s32 ret_val; 5722 u16 mii_status_reg; 5723 u16 i; 5724 5725 /* Polarity reversal workaround for forced 10F/10H links. */ 5726 5727 /* Disable the transmitter on the PHY */ 5728 5729 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5730 if (ret_val) 5731 return ret_val; 5732 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5733 if (ret_val) 5734 return ret_val; 5735 5736 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5737 if (ret_val) 5738 return ret_val; 5739 5740 /* This loop will early-out if the NO link condition has been met. */ 5741 for (i = PHY_FORCE_TIME; i > 0; i--) { 5742 /* Read the MII Status Register and wait for Link Status bit 5743 * to be clear. 5744 */ 5745 5746 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5747 if (ret_val) 5748 return ret_val; 5749 5750 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5751 if (ret_val) 5752 return ret_val; 5753 5754 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 5755 break; 5756 msleep(100); 5757 } 5758 5759 /* Recommended delay time after link has been lost */ 5760 msleep(1000); 5761 5762 /* Now we will re-enable th transmitter on the PHY */ 5763 5764 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5765 if (ret_val) 5766 return ret_val; 5767 msleep(50); 5768 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5769 if (ret_val) 5770 return ret_val; 5771 msleep(50); 5772 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5773 if (ret_val) 5774 return ret_val; 5775 msleep(50); 5776 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5777 if (ret_val) 5778 return ret_val; 5779 5780 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5781 if (ret_val) 5782 return ret_val; 5783 5784 /* This loop will early-out if the link condition has been met. */ 5785 for (i = PHY_FORCE_TIME; i > 0; i--) { 5786 /* Read the MII Status Register and wait for Link Status bit 5787 * to be set. 5788 */ 5789 5790 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5791 if (ret_val) 5792 return ret_val; 5793 5794 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5795 if (ret_val) 5796 return ret_val; 5797 5798 if (mii_status_reg & MII_SR_LINK_STATUS) 5799 break; 5800 msleep(100); 5801 } 5802 return E1000_SUCCESS; 5803 } 5804 5805 /** 5806 * e1000_get_auto_rd_done 5807 * @hw: Struct containing variables accessed by shared code 5808 * 5809 * Check for EEPROM Auto Read bit done. 5810 * returns: - E1000_ERR_RESET if fail to reset MAC 5811 * E1000_SUCCESS at any other case. 5812 */ 5813 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5814 { 5815 e_dbg("e1000_get_auto_rd_done"); 5816 msleep(5); 5817 return E1000_SUCCESS; 5818 } 5819 5820 /** 5821 * e1000_get_phy_cfg_done 5822 * @hw: Struct containing variables accessed by shared code 5823 * 5824 * Checks if the PHY configuration is done 5825 * returns: - E1000_ERR_RESET if fail to reset MAC 5826 * E1000_SUCCESS at any other case. 5827 */ 5828 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5829 { 5830 e_dbg("e1000_get_phy_cfg_done"); 5831 msleep(10); 5832 return E1000_SUCCESS; 5833 } 5834