1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 */ 28 29 /* e1000_hw.c 30 * Shared functions for accessing and configuring the MAC 31 */ 32 33 #include "e1000.h" 34 35 static s32 e1000_check_downshift(struct e1000_hw *hw); 36 static s32 e1000_check_polarity(struct e1000_hw *hw, 37 e1000_rev_polarity *polarity); 38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 39 static void e1000_clear_vfta(struct e1000_hw *hw); 40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 41 bool link_up); 42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 46 u16 *max_length); 47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 48 static s32 e1000_id_led_init(struct e1000_hw *hw); 49 static void e1000_init_rx_addrs(struct e1000_hw *hw); 50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 51 struct e1000_phy_info *phy_info); 52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 53 struct e1000_phy_info *phy_info); 54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 55 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 57 static s32 e1000_set_phy_type(struct e1000_hw *hw); 58 static void e1000_phy_init_script(struct e1000_hw *hw); 59 static s32 e1000_setup_copper_link(struct e1000_hw *hw); 60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); 67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 70 u16 words, u16 *data); 71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 72 u16 words, u16 *data); 73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 78 u16 phy_data); 79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 80 u16 *phy_data); 81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 83 static void e1000_release_eeprom(struct e1000_hw *hw); 84 static void e1000_standby_eeprom(struct e1000_hw *hw); 85 static s32 e1000_set_vco_speed(struct e1000_hw *hw); 86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 87 static s32 e1000_set_phy_mode(struct e1000_hw *hw); 88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 89 u16 *data); 90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 91 u16 *data); 92 93 /* IGP cable length table */ 94 static const 95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 102 100, 103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 104 110, 110, 105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 106 120, 120 107 }; 108 109 static DEFINE_SPINLOCK(e1000_eeprom_lock); 110 static DEFINE_SPINLOCK(e1000_phy_lock); 111 112 /** 113 * e1000_set_phy_type - Set the phy type member in the hw struct. 114 * @hw: Struct containing variables accessed by shared code 115 */ 116 static s32 e1000_set_phy_type(struct e1000_hw *hw) 117 { 118 if (hw->mac_type == e1000_undefined) 119 return -E1000_ERR_PHY_TYPE; 120 121 switch (hw->phy_id) { 122 case M88E1000_E_PHY_ID: 123 case M88E1000_I_PHY_ID: 124 case M88E1011_I_PHY_ID: 125 case M88E1111_I_PHY_ID: 126 case M88E1118_E_PHY_ID: 127 hw->phy_type = e1000_phy_m88; 128 break; 129 case IGP01E1000_I_PHY_ID: 130 if (hw->mac_type == e1000_82541 || 131 hw->mac_type == e1000_82541_rev_2 || 132 hw->mac_type == e1000_82547 || 133 hw->mac_type == e1000_82547_rev_2) 134 hw->phy_type = e1000_phy_igp; 135 break; 136 case RTL8211B_PHY_ID: 137 hw->phy_type = e1000_phy_8211; 138 break; 139 case RTL8201N_PHY_ID: 140 hw->phy_type = e1000_phy_8201; 141 break; 142 default: 143 /* Should never have loaded on this device */ 144 hw->phy_type = e1000_phy_undefined; 145 return -E1000_ERR_PHY_TYPE; 146 } 147 148 return E1000_SUCCESS; 149 } 150 151 /** 152 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY 153 * @hw: Struct containing variables accessed by shared code 154 */ 155 static void e1000_phy_init_script(struct e1000_hw *hw) 156 { 157 u32 ret_val; 158 u16 phy_saved_data; 159 160 if (hw->phy_init_script) { 161 msleep(20); 162 163 /* Save off the current value of register 0x2F5B to be restored 164 * at the end of this routine. 165 */ 166 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 167 168 /* Disabled the PHY transmitter */ 169 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 170 msleep(20); 171 172 e1000_write_phy_reg(hw, 0x0000, 0x0140); 173 msleep(5); 174 175 switch (hw->mac_type) { 176 case e1000_82541: 177 case e1000_82547: 178 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 179 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 180 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 181 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 182 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 183 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 184 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 185 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 186 e1000_write_phy_reg(hw, 0x2010, 0x0008); 187 break; 188 189 case e1000_82541_rev_2: 190 case e1000_82547_rev_2: 191 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 192 break; 193 default: 194 break; 195 } 196 197 e1000_write_phy_reg(hw, 0x0000, 0x3300); 198 msleep(20); 199 200 /* Now enable the transmitter */ 201 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 202 203 if (hw->mac_type == e1000_82547) { 204 u16 fused, fine, coarse; 205 206 /* Move to analog registers page */ 207 e1000_read_phy_reg(hw, 208 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 209 &fused); 210 211 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 212 e1000_read_phy_reg(hw, 213 IGP01E1000_ANALOG_FUSE_STATUS, 214 &fused); 215 216 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 217 coarse = 218 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 219 220 if (coarse > 221 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 222 coarse -= 223 IGP01E1000_ANALOG_FUSE_COARSE_10; 224 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 225 } else if (coarse == 226 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 227 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 228 229 fused = 230 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 231 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 232 (coarse & 233 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 234 235 e1000_write_phy_reg(hw, 236 IGP01E1000_ANALOG_FUSE_CONTROL, 237 fused); 238 e1000_write_phy_reg(hw, 239 IGP01E1000_ANALOG_FUSE_BYPASS, 240 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 241 } 242 } 243 } 244 } 245 246 /** 247 * e1000_set_mac_type - Set the mac type member in the hw struct. 248 * @hw: Struct containing variables accessed by shared code 249 */ 250 s32 e1000_set_mac_type(struct e1000_hw *hw) 251 { 252 switch (hw->device_id) { 253 case E1000_DEV_ID_82542: 254 switch (hw->revision_id) { 255 case E1000_82542_2_0_REV_ID: 256 hw->mac_type = e1000_82542_rev2_0; 257 break; 258 case E1000_82542_2_1_REV_ID: 259 hw->mac_type = e1000_82542_rev2_1; 260 break; 261 default: 262 /* Invalid 82542 revision ID */ 263 return -E1000_ERR_MAC_TYPE; 264 } 265 break; 266 case E1000_DEV_ID_82543GC_FIBER: 267 case E1000_DEV_ID_82543GC_COPPER: 268 hw->mac_type = e1000_82543; 269 break; 270 case E1000_DEV_ID_82544EI_COPPER: 271 case E1000_DEV_ID_82544EI_FIBER: 272 case E1000_DEV_ID_82544GC_COPPER: 273 case E1000_DEV_ID_82544GC_LOM: 274 hw->mac_type = e1000_82544; 275 break; 276 case E1000_DEV_ID_82540EM: 277 case E1000_DEV_ID_82540EM_LOM: 278 case E1000_DEV_ID_82540EP: 279 case E1000_DEV_ID_82540EP_LOM: 280 case E1000_DEV_ID_82540EP_LP: 281 hw->mac_type = e1000_82540; 282 break; 283 case E1000_DEV_ID_82545EM_COPPER: 284 case E1000_DEV_ID_82545EM_FIBER: 285 hw->mac_type = e1000_82545; 286 break; 287 case E1000_DEV_ID_82545GM_COPPER: 288 case E1000_DEV_ID_82545GM_FIBER: 289 case E1000_DEV_ID_82545GM_SERDES: 290 hw->mac_type = e1000_82545_rev_3; 291 break; 292 case E1000_DEV_ID_82546EB_COPPER: 293 case E1000_DEV_ID_82546EB_FIBER: 294 case E1000_DEV_ID_82546EB_QUAD_COPPER: 295 hw->mac_type = e1000_82546; 296 break; 297 case E1000_DEV_ID_82546GB_COPPER: 298 case E1000_DEV_ID_82546GB_FIBER: 299 case E1000_DEV_ID_82546GB_SERDES: 300 case E1000_DEV_ID_82546GB_PCIE: 301 case E1000_DEV_ID_82546GB_QUAD_COPPER: 302 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 303 hw->mac_type = e1000_82546_rev_3; 304 break; 305 case E1000_DEV_ID_82541EI: 306 case E1000_DEV_ID_82541EI_MOBILE: 307 case E1000_DEV_ID_82541ER_LOM: 308 hw->mac_type = e1000_82541; 309 break; 310 case E1000_DEV_ID_82541ER: 311 case E1000_DEV_ID_82541GI: 312 case E1000_DEV_ID_82541GI_LF: 313 case E1000_DEV_ID_82541GI_MOBILE: 314 hw->mac_type = e1000_82541_rev_2; 315 break; 316 case E1000_DEV_ID_82547EI: 317 case E1000_DEV_ID_82547EI_MOBILE: 318 hw->mac_type = e1000_82547; 319 break; 320 case E1000_DEV_ID_82547GI: 321 hw->mac_type = e1000_82547_rev_2; 322 break; 323 case E1000_DEV_ID_INTEL_CE4100_GBE: 324 hw->mac_type = e1000_ce4100; 325 break; 326 default: 327 /* Should never have loaded on this device */ 328 return -E1000_ERR_MAC_TYPE; 329 } 330 331 switch (hw->mac_type) { 332 case e1000_82541: 333 case e1000_82547: 334 case e1000_82541_rev_2: 335 case e1000_82547_rev_2: 336 hw->asf_firmware_present = true; 337 break; 338 default: 339 break; 340 } 341 342 /* The 82543 chip does not count tx_carrier_errors properly in 343 * FD mode 344 */ 345 if (hw->mac_type == e1000_82543) 346 hw->bad_tx_carr_stats_fd = true; 347 348 if (hw->mac_type > e1000_82544) 349 hw->has_smbus = true; 350 351 return E1000_SUCCESS; 352 } 353 354 /** 355 * e1000_set_media_type - Set media type and TBI compatibility. 356 * @hw: Struct containing variables accessed by shared code 357 */ 358 void e1000_set_media_type(struct e1000_hw *hw) 359 { 360 u32 status; 361 362 if (hw->mac_type != e1000_82543) { 363 /* tbi_compatibility is only valid on 82543 */ 364 hw->tbi_compatibility_en = false; 365 } 366 367 switch (hw->device_id) { 368 case E1000_DEV_ID_82545GM_SERDES: 369 case E1000_DEV_ID_82546GB_SERDES: 370 hw->media_type = e1000_media_type_internal_serdes; 371 break; 372 default: 373 switch (hw->mac_type) { 374 case e1000_82542_rev2_0: 375 case e1000_82542_rev2_1: 376 hw->media_type = e1000_media_type_fiber; 377 break; 378 case e1000_ce4100: 379 hw->media_type = e1000_media_type_copper; 380 break; 381 default: 382 status = er32(STATUS); 383 if (status & E1000_STATUS_TBIMODE) { 384 hw->media_type = e1000_media_type_fiber; 385 /* tbi_compatibility not valid on fiber */ 386 hw->tbi_compatibility_en = false; 387 } else { 388 hw->media_type = e1000_media_type_copper; 389 } 390 break; 391 } 392 } 393 } 394 395 /** 396 * e1000_reset_hw - reset the hardware completely 397 * @hw: Struct containing variables accessed by shared code 398 * 399 * Reset the transmit and receive units; mask and clear all interrupts. 400 */ 401 s32 e1000_reset_hw(struct e1000_hw *hw) 402 { 403 u32 ctrl; 404 u32 ctrl_ext; 405 u32 icr; 406 u32 manc; 407 u32 led_ctrl; 408 s32 ret_val; 409 410 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 411 if (hw->mac_type == e1000_82542_rev2_0) { 412 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 413 e1000_pci_clear_mwi(hw); 414 } 415 416 /* Clear interrupt mask to stop board from generating interrupts */ 417 e_dbg("Masking off all interrupts\n"); 418 ew32(IMC, 0xffffffff); 419 420 /* Disable the Transmit and Receive units. Then delay to allow 421 * any pending transactions to complete before we hit the MAC with 422 * the global reset. 423 */ 424 ew32(RCTL, 0); 425 ew32(TCTL, E1000_TCTL_PSP); 426 E1000_WRITE_FLUSH(); 427 428 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 429 hw->tbi_compatibility_on = false; 430 431 /* Delay to allow any outstanding PCI transactions to complete before 432 * resetting the device 433 */ 434 msleep(10); 435 436 ctrl = er32(CTRL); 437 438 /* Must reset the PHY before resetting the MAC */ 439 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 440 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 441 E1000_WRITE_FLUSH(); 442 msleep(5); 443 } 444 445 /* Issue a global reset to the MAC. This will reset the chip's 446 * transmit, receive, DMA, and link units. It will not effect 447 * the current PCI configuration. The global reset bit is self- 448 * clearing, and should clear within a microsecond. 449 */ 450 e_dbg("Issuing a global reset to MAC\n"); 451 452 switch (hw->mac_type) { 453 case e1000_82544: 454 case e1000_82540: 455 case e1000_82545: 456 case e1000_82546: 457 case e1000_82541: 458 case e1000_82541_rev_2: 459 /* These controllers can't ack the 64-bit write when issuing the 460 * reset, so use IO-mapping as a workaround to issue the reset 461 */ 462 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 463 break; 464 case e1000_82545_rev_3: 465 case e1000_82546_rev_3: 466 /* Reset is performed on a shadow of the control register */ 467 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 468 break; 469 case e1000_ce4100: 470 default: 471 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 472 break; 473 } 474 475 /* After MAC reset, force reload of EEPROM to restore power-on settings 476 * to device. Later controllers reload the EEPROM automatically, so 477 * just wait for reload to complete. 478 */ 479 switch (hw->mac_type) { 480 case e1000_82542_rev2_0: 481 case e1000_82542_rev2_1: 482 case e1000_82543: 483 case e1000_82544: 484 /* Wait for reset to complete */ 485 udelay(10); 486 ctrl_ext = er32(CTRL_EXT); 487 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 488 ew32(CTRL_EXT, ctrl_ext); 489 E1000_WRITE_FLUSH(); 490 /* Wait for EEPROM reload */ 491 msleep(2); 492 break; 493 case e1000_82541: 494 case e1000_82541_rev_2: 495 case e1000_82547: 496 case e1000_82547_rev_2: 497 /* Wait for EEPROM reload */ 498 msleep(20); 499 break; 500 default: 501 /* Auto read done will delay 5ms or poll based on mac type */ 502 ret_val = e1000_get_auto_rd_done(hw); 503 if (ret_val) 504 return ret_val; 505 break; 506 } 507 508 /* Disable HW ARPs on ASF enabled adapters */ 509 if (hw->mac_type >= e1000_82540) { 510 manc = er32(MANC); 511 manc &= ~(E1000_MANC_ARP_EN); 512 ew32(MANC, manc); 513 } 514 515 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 516 e1000_phy_init_script(hw); 517 518 /* Configure activity LED after PHY reset */ 519 led_ctrl = er32(LEDCTL); 520 led_ctrl &= IGP_ACTIVITY_LED_MASK; 521 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 522 ew32(LEDCTL, led_ctrl); 523 } 524 525 /* Clear interrupt mask to stop board from generating interrupts */ 526 e_dbg("Masking off all interrupts\n"); 527 ew32(IMC, 0xffffffff); 528 529 /* Clear any pending interrupt events. */ 530 icr = er32(ICR); 531 532 /* If MWI was previously enabled, reenable it. */ 533 if (hw->mac_type == e1000_82542_rev2_0) { 534 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 535 e1000_pci_set_mwi(hw); 536 } 537 538 return E1000_SUCCESS; 539 } 540 541 /** 542 * e1000_init_hw - Performs basic configuration of the adapter. 543 * @hw: Struct containing variables accessed by shared code 544 * 545 * Assumes that the controller has previously been reset and is in a 546 * post-reset uninitialized state. Initializes the receive address registers, 547 * multicast table, and VLAN filter table. Calls routines to setup link 548 * configuration and flow control settings. Clears all on-chip counters. Leaves 549 * the transmit and receive units disabled and uninitialized. 550 */ 551 s32 e1000_init_hw(struct e1000_hw *hw) 552 { 553 u32 ctrl; 554 u32 i; 555 s32 ret_val; 556 u32 mta_size; 557 u32 ctrl_ext; 558 559 /* Initialize Identification LED */ 560 ret_val = e1000_id_led_init(hw); 561 if (ret_val) { 562 e_dbg("Error Initializing Identification LED\n"); 563 return ret_val; 564 } 565 566 /* Set the media type and TBI compatibility */ 567 e1000_set_media_type(hw); 568 569 /* Disabling VLAN filtering. */ 570 e_dbg("Initializing the IEEE VLAN\n"); 571 if (hw->mac_type < e1000_82545_rev_3) 572 ew32(VET, 0); 573 e1000_clear_vfta(hw); 574 575 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 576 if (hw->mac_type == e1000_82542_rev2_0) { 577 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 578 e1000_pci_clear_mwi(hw); 579 ew32(RCTL, E1000_RCTL_RST); 580 E1000_WRITE_FLUSH(); 581 msleep(5); 582 } 583 584 /* Setup the receive address. This involves initializing all of the 585 * Receive Address Registers (RARs 0 - 15). 586 */ 587 e1000_init_rx_addrs(hw); 588 589 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 590 if (hw->mac_type == e1000_82542_rev2_0) { 591 ew32(RCTL, 0); 592 E1000_WRITE_FLUSH(); 593 msleep(1); 594 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 595 e1000_pci_set_mwi(hw); 596 } 597 598 /* Zero out the Multicast HASH table */ 599 e_dbg("Zeroing the MTA\n"); 600 mta_size = E1000_MC_TBL_SIZE; 601 for (i = 0; i < mta_size; i++) { 602 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 603 /* use write flush to prevent Memory Write Block (MWB) from 604 * occurring when accessing our register space 605 */ 606 E1000_WRITE_FLUSH(); 607 } 608 609 /* Set the PCI priority bit correctly in the CTRL register. This 610 * determines if the adapter gives priority to receives, or if it 611 * gives equal priority to transmits and receives. Valid only on 612 * 82542 and 82543 silicon. 613 */ 614 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 615 ctrl = er32(CTRL); 616 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 617 } 618 619 switch (hw->mac_type) { 620 case e1000_82545_rev_3: 621 case e1000_82546_rev_3: 622 break; 623 default: 624 /* Workaround for PCI-X problem when BIOS sets MMRBC 625 * incorrectly. 626 */ 627 if (hw->bus_type == e1000_bus_type_pcix 628 && e1000_pcix_get_mmrbc(hw) > 2048) 629 e1000_pcix_set_mmrbc(hw, 2048); 630 break; 631 } 632 633 /* Call a subroutine to configure the link and setup flow control. */ 634 ret_val = e1000_setup_link(hw); 635 636 /* Set the transmit descriptor write-back policy */ 637 if (hw->mac_type > e1000_82544) { 638 ctrl = er32(TXDCTL); 639 ctrl = 640 (ctrl & ~E1000_TXDCTL_WTHRESH) | 641 E1000_TXDCTL_FULL_TX_DESC_WB; 642 ew32(TXDCTL, ctrl); 643 } 644 645 /* Clear all of the statistics registers (clear on read). It is 646 * important that we do this after we have tried to establish link 647 * because the symbol error count will increment wildly if there 648 * is no link. 649 */ 650 e1000_clear_hw_cntrs(hw); 651 652 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 653 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 654 ctrl_ext = er32(CTRL_EXT); 655 /* Relaxed ordering must be disabled to avoid a parity 656 * error crash in a PCI slot. 657 */ 658 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 659 ew32(CTRL_EXT, ctrl_ext); 660 } 661 662 return ret_val; 663 } 664 665 /** 666 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. 667 * @hw: Struct containing variables accessed by shared code. 668 */ 669 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 670 { 671 u16 eeprom_data; 672 s32 ret_val; 673 674 if (hw->media_type != e1000_media_type_internal_serdes) 675 return E1000_SUCCESS; 676 677 switch (hw->mac_type) { 678 case e1000_82545_rev_3: 679 case e1000_82546_rev_3: 680 break; 681 default: 682 return E1000_SUCCESS; 683 } 684 685 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 686 &eeprom_data); 687 if (ret_val) { 688 return ret_val; 689 } 690 691 if (eeprom_data != EEPROM_RESERVED_WORD) { 692 /* Adjust SERDES output amplitude only. */ 693 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 694 ret_val = 695 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 696 if (ret_val) 697 return ret_val; 698 } 699 700 return E1000_SUCCESS; 701 } 702 703 /** 704 * e1000_setup_link - Configures flow control and link settings. 705 * @hw: Struct containing variables accessed by shared code 706 * 707 * Determines which flow control settings to use. Calls the appropriate media- 708 * specific link configuration function. Configures the flow control settings. 709 * Assuming the adapter has a valid link partner, a valid link should be 710 * established. Assumes the hardware has previously been reset and the 711 * transmitter and receiver are not enabled. 712 */ 713 s32 e1000_setup_link(struct e1000_hw *hw) 714 { 715 u32 ctrl_ext; 716 s32 ret_val; 717 u16 eeprom_data; 718 719 /* Read and store word 0x0F of the EEPROM. This word contains bits 720 * that determine the hardware's default PAUSE (flow control) mode, 721 * a bit that determines whether the HW defaults to enabling or 722 * disabling auto-negotiation, and the direction of the 723 * SW defined pins. If there is no SW over-ride of the flow 724 * control setting, then the variable hw->fc will 725 * be initialized based on a value in the EEPROM. 726 */ 727 if (hw->fc == E1000_FC_DEFAULT) { 728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 729 1, &eeprom_data); 730 if (ret_val) { 731 e_dbg("EEPROM Read Error\n"); 732 return -E1000_ERR_EEPROM; 733 } 734 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 735 hw->fc = E1000_FC_NONE; 736 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 737 EEPROM_WORD0F_ASM_DIR) 738 hw->fc = E1000_FC_TX_PAUSE; 739 else 740 hw->fc = E1000_FC_FULL; 741 } 742 743 /* We want to save off the original Flow Control configuration just 744 * in case we get disconnected and then reconnected into a different 745 * hub or switch with different Flow Control capabilities. 746 */ 747 if (hw->mac_type == e1000_82542_rev2_0) 748 hw->fc &= (~E1000_FC_TX_PAUSE); 749 750 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 751 hw->fc &= (~E1000_FC_RX_PAUSE); 752 753 hw->original_fc = hw->fc; 754 755 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); 756 757 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 758 * polarity value for the SW controlled pins, and setup the 759 * Extended Device Control reg with that info. 760 * This is needed because one of the SW controlled pins is used for 761 * signal detection. So this should be done before e1000_setup_pcs_link() 762 * or e1000_phy_setup() is called. 763 */ 764 if (hw->mac_type == e1000_82543) { 765 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 766 1, &eeprom_data); 767 if (ret_val) { 768 e_dbg("EEPROM Read Error\n"); 769 return -E1000_ERR_EEPROM; 770 } 771 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 772 SWDPIO__EXT_SHIFT); 773 ew32(CTRL_EXT, ctrl_ext); 774 } 775 776 /* Call the necessary subroutine to configure the link. */ 777 ret_val = (hw->media_type == e1000_media_type_copper) ? 778 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); 779 780 /* Initialize the flow control address, type, and PAUSE timer 781 * registers to their default values. This is done even if flow 782 * control is disabled, because it does not hurt anything to 783 * initialize these registers. 784 */ 785 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 786 787 ew32(FCT, FLOW_CONTROL_TYPE); 788 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 789 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 790 791 ew32(FCTTV, hw->fc_pause_time); 792 793 /* Set the flow control receive threshold registers. Normally, 794 * these registers will be set to a default threshold that may be 795 * adjusted later by the driver's runtime code. However, if the 796 * ability to transmit pause frames in not enabled, then these 797 * registers will be set to 0. 798 */ 799 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 800 ew32(FCRTL, 0); 801 ew32(FCRTH, 0); 802 } else { 803 /* We need to set up the Receive Threshold high and low water 804 * marks as well as (optionally) enabling the transmission of 805 * XON frames. 806 */ 807 if (hw->fc_send_xon) { 808 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 809 ew32(FCRTH, hw->fc_high_water); 810 } else { 811 ew32(FCRTL, hw->fc_low_water); 812 ew32(FCRTH, hw->fc_high_water); 813 } 814 } 815 return ret_val; 816 } 817 818 /** 819 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link 820 * @hw: Struct containing variables accessed by shared code 821 * 822 * Manipulates Physical Coding Sublayer functions in order to configure 823 * link. Assumes the hardware has been previously reset and the transmitter 824 * and receiver are not enabled. 825 */ 826 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 827 { 828 u32 ctrl; 829 u32 status; 830 u32 txcw = 0; 831 u32 i; 832 u32 signal = 0; 833 s32 ret_val; 834 835 /* On adapters with a MAC newer than 82544, SWDP 1 will be 836 * set when the optics detect a signal. On older adapters, it will be 837 * cleared when there is a signal. This applies to fiber media only. 838 * If we're on serdes media, adjust the output amplitude to value 839 * set in the EEPROM. 840 */ 841 ctrl = er32(CTRL); 842 if (hw->media_type == e1000_media_type_fiber) 843 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 844 845 ret_val = e1000_adjust_serdes_amplitude(hw); 846 if (ret_val) 847 return ret_val; 848 849 /* Take the link out of reset */ 850 ctrl &= ~(E1000_CTRL_LRST); 851 852 /* Adjust VCO speed to improve BER performance */ 853 ret_val = e1000_set_vco_speed(hw); 854 if (ret_val) 855 return ret_val; 856 857 e1000_config_collision_dist(hw); 858 859 /* Check for a software override of the flow control settings, and setup 860 * the device accordingly. If auto-negotiation is enabled, then 861 * software will have to set the "PAUSE" bits to the correct value in 862 * the Tranmsit Config Word Register (TXCW) and re-start 863 * auto-negotiation. However, if auto-negotiation is disabled, then 864 * software will have to manually configure the two flow control enable 865 * bits in the CTRL register. 866 * 867 * The possible values of the "fc" parameter are: 868 * 0: Flow control is completely disabled 869 * 1: Rx flow control is enabled (we can receive pause frames, but 870 * not send pause frames). 871 * 2: Tx flow control is enabled (we can send pause frames but we do 872 * not support receiving pause frames). 873 * 3: Both Rx and TX flow control (symmetric) are enabled. 874 */ 875 switch (hw->fc) { 876 case E1000_FC_NONE: 877 /* Flow ctrl is completely disabled by a software over-ride */ 878 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 879 break; 880 case E1000_FC_RX_PAUSE: 881 /* Rx Flow control is enabled and Tx Flow control is disabled by 882 * a software over-ride. Since there really isn't a way to 883 * advertise that we are capable of Rx Pause ONLY, we will 884 * advertise that we support both symmetric and asymmetric Rx 885 * PAUSE. Later, we will disable the adapter's ability to send 886 * PAUSE frames. 887 */ 888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 889 break; 890 case E1000_FC_TX_PAUSE: 891 /* Tx Flow control is enabled, and Rx Flow control is disabled, 892 * by a software over-ride. 893 */ 894 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 895 break; 896 case E1000_FC_FULL: 897 /* Flow control (both Rx and Tx) is enabled by a software 898 * over-ride. 899 */ 900 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 901 break; 902 default: 903 e_dbg("Flow control param set incorrectly\n"); 904 return -E1000_ERR_CONFIG; 905 break; 906 } 907 908 /* Since auto-negotiation is enabled, take the link out of reset (the 909 * link will be in reset, because we previously reset the chip). This 910 * will restart auto-negotiation. If auto-negotiation is successful 911 * then the link-up status bit will be set and the flow control enable 912 * bits (RFCE and TFCE) will be set according to their negotiated value. 913 */ 914 e_dbg("Auto-negotiation enabled\n"); 915 916 ew32(TXCW, txcw); 917 ew32(CTRL, ctrl); 918 E1000_WRITE_FLUSH(); 919 920 hw->txcw = txcw; 921 msleep(1); 922 923 /* If we have a signal (the cable is plugged in) then poll for a 924 * "Link-Up" indication in the Device Status Register. Time-out if a 925 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should 926 * complete in less than 500 milliseconds even if the other end is doing 927 * it in SW). For internal serdes, we just assume a signal is present, 928 * then poll. 929 */ 930 if (hw->media_type == e1000_media_type_internal_serdes || 931 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 932 e_dbg("Looking for Link\n"); 933 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 934 msleep(10); 935 status = er32(STATUS); 936 if (status & E1000_STATUS_LU) 937 break; 938 } 939 if (i == (LINK_UP_TIMEOUT / 10)) { 940 e_dbg("Never got a valid link from auto-neg!!!\n"); 941 hw->autoneg_failed = 1; 942 /* AutoNeg failed to achieve a link, so we'll call 943 * e1000_check_for_link. This routine will force the 944 * link up if we detect a signal. This will allow us to 945 * communicate with non-autonegotiating link partners. 946 */ 947 ret_val = e1000_check_for_link(hw); 948 if (ret_val) { 949 e_dbg("Error while checking for link\n"); 950 return ret_val; 951 } 952 hw->autoneg_failed = 0; 953 } else { 954 hw->autoneg_failed = 0; 955 e_dbg("Valid Link Found\n"); 956 } 957 } else { 958 e_dbg("No Signal Detected\n"); 959 } 960 return E1000_SUCCESS; 961 } 962 963 /** 964 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. 965 * @hw: Struct containing variables accessed by shared code 966 * 967 * Commits changes to PHY configuration by calling e1000_phy_reset(). 968 */ 969 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) 970 { 971 s32 ret_val; 972 973 /* SW reset the PHY so all changes take effect */ 974 ret_val = e1000_phy_reset(hw); 975 if (ret_val) { 976 e_dbg("Error Resetting the PHY\n"); 977 return ret_val; 978 } 979 980 return E1000_SUCCESS; 981 } 982 983 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) 984 { 985 s32 ret_val; 986 u32 ctrl_aux; 987 988 switch (hw->phy_type) { 989 case e1000_phy_8211: 990 ret_val = e1000_copper_link_rtl_setup(hw); 991 if (ret_val) { 992 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 993 return ret_val; 994 } 995 break; 996 case e1000_phy_8201: 997 /* Set RMII mode */ 998 ctrl_aux = er32(CTL_AUX); 999 ctrl_aux |= E1000_CTL_AUX_RMII; 1000 ew32(CTL_AUX, ctrl_aux); 1001 E1000_WRITE_FLUSH(); 1002 1003 /* Disable the J/K bits required for receive */ 1004 ctrl_aux = er32(CTL_AUX); 1005 ctrl_aux |= 0x4; 1006 ctrl_aux &= ~0x2; 1007 ew32(CTL_AUX, ctrl_aux); 1008 E1000_WRITE_FLUSH(); 1009 ret_val = e1000_copper_link_rtl_setup(hw); 1010 1011 if (ret_val) { 1012 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 1013 return ret_val; 1014 } 1015 break; 1016 default: 1017 e_dbg("Error Resetting the PHY\n"); 1018 return E1000_ERR_PHY_TYPE; 1019 } 1020 1021 return E1000_SUCCESS; 1022 } 1023 1024 /** 1025 * e1000_copper_link_preconfig - early configuration for copper 1026 * @hw: Struct containing variables accessed by shared code 1027 * 1028 * Make sure we have a valid PHY and change PHY mode before link setup. 1029 */ 1030 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 1031 { 1032 u32 ctrl; 1033 s32 ret_val; 1034 u16 phy_data; 1035 1036 ctrl = er32(CTRL); 1037 /* With 82543, we need to force speed and duplex on the MAC equal to 1038 * what the PHY speed and duplex configuration is. In addition, we need 1039 * to perform a hardware reset on the PHY to take it out of reset. 1040 */ 1041 if (hw->mac_type > e1000_82543) { 1042 ctrl |= E1000_CTRL_SLU; 1043 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1044 ew32(CTRL, ctrl); 1045 } else { 1046 ctrl |= 1047 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1048 ew32(CTRL, ctrl); 1049 ret_val = e1000_phy_hw_reset(hw); 1050 if (ret_val) 1051 return ret_val; 1052 } 1053 1054 /* Make sure we have a valid PHY */ 1055 ret_val = e1000_detect_gig_phy(hw); 1056 if (ret_val) { 1057 e_dbg("Error, did not detect valid phy.\n"); 1058 return ret_val; 1059 } 1060 e_dbg("Phy ID = %x\n", hw->phy_id); 1061 1062 /* Set PHY to class A mode (if necessary) */ 1063 ret_val = e1000_set_phy_mode(hw); 1064 if (ret_val) 1065 return ret_val; 1066 1067 if ((hw->mac_type == e1000_82545_rev_3) || 1068 (hw->mac_type == e1000_82546_rev_3)) { 1069 ret_val = 1070 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1071 phy_data |= 0x00000008; 1072 ret_val = 1073 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1074 } 1075 1076 if (hw->mac_type <= e1000_82543 || 1077 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1078 hw->mac_type == e1000_82541_rev_2 1079 || hw->mac_type == e1000_82547_rev_2) 1080 hw->phy_reset_disable = false; 1081 1082 return E1000_SUCCESS; 1083 } 1084 1085 /** 1086 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. 1087 * @hw: Struct containing variables accessed by shared code 1088 */ 1089 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1090 { 1091 u32 led_ctrl; 1092 s32 ret_val; 1093 u16 phy_data; 1094 1095 if (hw->phy_reset_disable) 1096 return E1000_SUCCESS; 1097 1098 ret_val = e1000_phy_reset(hw); 1099 if (ret_val) { 1100 e_dbg("Error Resetting the PHY\n"); 1101 return ret_val; 1102 } 1103 1104 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1105 msleep(15); 1106 /* Configure activity LED after PHY reset */ 1107 led_ctrl = er32(LEDCTL); 1108 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1109 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1110 ew32(LEDCTL, led_ctrl); 1111 1112 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1113 if (hw->phy_type == e1000_phy_igp) { 1114 /* disable lplu d3 during driver init */ 1115 ret_val = e1000_set_d3_lplu_state(hw, false); 1116 if (ret_val) { 1117 e_dbg("Error Disabling LPLU D3\n"); 1118 return ret_val; 1119 } 1120 } 1121 1122 /* Configure mdi-mdix settings */ 1123 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1124 if (ret_val) 1125 return ret_val; 1126 1127 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1128 hw->dsp_config_state = e1000_dsp_config_disabled; 1129 /* Force MDI for earlier revs of the IGP PHY */ 1130 phy_data &= 1131 ~(IGP01E1000_PSCR_AUTO_MDIX | 1132 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1133 hw->mdix = 1; 1134 1135 } else { 1136 hw->dsp_config_state = e1000_dsp_config_enabled; 1137 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1138 1139 switch (hw->mdix) { 1140 case 1: 1141 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1142 break; 1143 case 2: 1144 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1145 break; 1146 case 0: 1147 default: 1148 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1149 break; 1150 } 1151 } 1152 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1153 if (ret_val) 1154 return ret_val; 1155 1156 /* set auto-master slave resolution settings */ 1157 if (hw->autoneg) { 1158 e1000_ms_type phy_ms_setting = hw->master_slave; 1159 1160 if (hw->ffe_config_state == e1000_ffe_config_active) 1161 hw->ffe_config_state = e1000_ffe_config_enabled; 1162 1163 if (hw->dsp_config_state == e1000_dsp_config_activated) 1164 hw->dsp_config_state = e1000_dsp_config_enabled; 1165 1166 /* when autonegotiation advertisement is only 1000Mbps then we 1167 * should disable SmartSpeed and enable Auto MasterSlave 1168 * resolution as hardware default. 1169 */ 1170 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1171 /* Disable SmartSpeed */ 1172 ret_val = 1173 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1174 &phy_data); 1175 if (ret_val) 1176 return ret_val; 1177 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1178 ret_val = 1179 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1180 phy_data); 1181 if (ret_val) 1182 return ret_val; 1183 /* Set auto Master/Slave resolution process */ 1184 ret_val = 1185 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1186 if (ret_val) 1187 return ret_val; 1188 phy_data &= ~CR_1000T_MS_ENABLE; 1189 ret_val = 1190 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1191 if (ret_val) 1192 return ret_val; 1193 } 1194 1195 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1196 if (ret_val) 1197 return ret_val; 1198 1199 /* load defaults for future use */ 1200 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1201 ((phy_data & CR_1000T_MS_VALUE) ? 1202 e1000_ms_force_master : 1203 e1000_ms_force_slave) : e1000_ms_auto; 1204 1205 switch (phy_ms_setting) { 1206 case e1000_ms_force_master: 1207 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1208 break; 1209 case e1000_ms_force_slave: 1210 phy_data |= CR_1000T_MS_ENABLE; 1211 phy_data &= ~(CR_1000T_MS_VALUE); 1212 break; 1213 case e1000_ms_auto: 1214 phy_data &= ~CR_1000T_MS_ENABLE; 1215 default: 1216 break; 1217 } 1218 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1219 if (ret_val) 1220 return ret_val; 1221 } 1222 1223 return E1000_SUCCESS; 1224 } 1225 1226 /** 1227 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. 1228 * @hw: Struct containing variables accessed by shared code 1229 */ 1230 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1231 { 1232 s32 ret_val; 1233 u16 phy_data; 1234 1235 if (hw->phy_reset_disable) 1236 return E1000_SUCCESS; 1237 1238 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1239 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1240 if (ret_val) 1241 return ret_val; 1242 1243 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1244 1245 /* Options: 1246 * MDI/MDI-X = 0 (default) 1247 * 0 - Auto for all speeds 1248 * 1 - MDI mode 1249 * 2 - MDI-X mode 1250 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1251 */ 1252 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1253 1254 switch (hw->mdix) { 1255 case 1: 1256 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1257 break; 1258 case 2: 1259 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1260 break; 1261 case 3: 1262 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1263 break; 1264 case 0: 1265 default: 1266 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1267 break; 1268 } 1269 1270 /* Options: 1271 * disable_polarity_correction = 0 (default) 1272 * Automatic Correction for Reversed Cable Polarity 1273 * 0 - Disabled 1274 * 1 - Enabled 1275 */ 1276 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1277 if (hw->disable_polarity_correction == 1) 1278 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1279 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1280 if (ret_val) 1281 return ret_val; 1282 1283 if (hw->phy_revision < M88E1011_I_REV_4) { 1284 /* Force TX_CLK in the Extended PHY Specific Control Register 1285 * to 25MHz clock. 1286 */ 1287 ret_val = 1288 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1289 &phy_data); 1290 if (ret_val) 1291 return ret_val; 1292 1293 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1294 1295 if ((hw->phy_revision == E1000_REVISION_2) && 1296 (hw->phy_id == M88E1111_I_PHY_ID)) { 1297 /* Vidalia Phy, set the downshift counter to 5x */ 1298 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1299 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1300 ret_val = e1000_write_phy_reg(hw, 1301 M88E1000_EXT_PHY_SPEC_CTRL, 1302 phy_data); 1303 if (ret_val) 1304 return ret_val; 1305 } else { 1306 /* Configure Master and Slave downshift values */ 1307 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1308 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1309 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1310 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1311 ret_val = e1000_write_phy_reg(hw, 1312 M88E1000_EXT_PHY_SPEC_CTRL, 1313 phy_data); 1314 if (ret_val) 1315 return ret_val; 1316 } 1317 } 1318 1319 /* SW Reset the PHY so all changes take effect */ 1320 ret_val = e1000_phy_reset(hw); 1321 if (ret_val) { 1322 e_dbg("Error Resetting the PHY\n"); 1323 return ret_val; 1324 } 1325 1326 return E1000_SUCCESS; 1327 } 1328 1329 /** 1330 * e1000_copper_link_autoneg - setup auto-neg 1331 * @hw: Struct containing variables accessed by shared code 1332 * 1333 * Setup auto-negotiation and flow control advertisements, 1334 * and then perform auto-negotiation. 1335 */ 1336 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1337 { 1338 s32 ret_val; 1339 u16 phy_data; 1340 1341 /* Perform some bounds checking on the hw->autoneg_advertised 1342 * parameter. If this variable is zero, then set it to the default. 1343 */ 1344 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1345 1346 /* If autoneg_advertised is zero, we assume it was not defaulted 1347 * by the calling code so we set to advertise full capability. 1348 */ 1349 if (hw->autoneg_advertised == 0) 1350 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1351 1352 /* IFE/RTL8201N PHY only supports 10/100 */ 1353 if (hw->phy_type == e1000_phy_8201) 1354 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1355 1356 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1357 ret_val = e1000_phy_setup_autoneg(hw); 1358 if (ret_val) { 1359 e_dbg("Error Setting up Auto-Negotiation\n"); 1360 return ret_val; 1361 } 1362 e_dbg("Restarting Auto-Neg\n"); 1363 1364 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1365 * the Auto Neg Restart bit in the PHY control register. 1366 */ 1367 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1368 if (ret_val) 1369 return ret_val; 1370 1371 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1372 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1373 if (ret_val) 1374 return ret_val; 1375 1376 /* Does the user want to wait for Auto-Neg to complete here, or 1377 * check at a later time (for example, callback routine). 1378 */ 1379 if (hw->wait_autoneg_complete) { 1380 ret_val = e1000_wait_autoneg(hw); 1381 if (ret_val) { 1382 e_dbg 1383 ("Error while waiting for autoneg to complete\n"); 1384 return ret_val; 1385 } 1386 } 1387 1388 hw->get_link_status = true; 1389 1390 return E1000_SUCCESS; 1391 } 1392 1393 /** 1394 * e1000_copper_link_postconfig - post link setup 1395 * @hw: Struct containing variables accessed by shared code 1396 * 1397 * Config the MAC and the PHY after link is up. 1398 * 1) Set up the MAC to the current PHY speed/duplex 1399 * if we are on 82543. If we 1400 * are on newer silicon, we only need to configure 1401 * collision distance in the Transmit Control Register. 1402 * 2) Set up flow control on the MAC to that established with 1403 * the link partner. 1404 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1405 */ 1406 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1407 { 1408 s32 ret_val; 1409 1410 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { 1411 e1000_config_collision_dist(hw); 1412 } else { 1413 ret_val = e1000_config_mac_to_phy(hw); 1414 if (ret_val) { 1415 e_dbg("Error configuring MAC to PHY settings\n"); 1416 return ret_val; 1417 } 1418 } 1419 ret_val = e1000_config_fc_after_link_up(hw); 1420 if (ret_val) { 1421 e_dbg("Error Configuring Flow Control\n"); 1422 return ret_val; 1423 } 1424 1425 /* Config DSP to improve Giga link quality */ 1426 if (hw->phy_type == e1000_phy_igp) { 1427 ret_val = e1000_config_dsp_after_link_change(hw, true); 1428 if (ret_val) { 1429 e_dbg("Error Configuring DSP after link up\n"); 1430 return ret_val; 1431 } 1432 } 1433 1434 return E1000_SUCCESS; 1435 } 1436 1437 /** 1438 * e1000_setup_copper_link - phy/speed/duplex setting 1439 * @hw: Struct containing variables accessed by shared code 1440 * 1441 * Detects which PHY is present and sets up the speed and duplex 1442 */ 1443 static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1444 { 1445 s32 ret_val; 1446 u16 i; 1447 u16 phy_data; 1448 1449 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1450 ret_val = e1000_copper_link_preconfig(hw); 1451 if (ret_val) 1452 return ret_val; 1453 1454 if (hw->phy_type == e1000_phy_igp) { 1455 ret_val = e1000_copper_link_igp_setup(hw); 1456 if (ret_val) 1457 return ret_val; 1458 } else if (hw->phy_type == e1000_phy_m88) { 1459 ret_val = e1000_copper_link_mgp_setup(hw); 1460 if (ret_val) 1461 return ret_val; 1462 } else { 1463 ret_val = gbe_dhg_phy_setup(hw); 1464 if (ret_val) { 1465 e_dbg("gbe_dhg_phy_setup failed!\n"); 1466 return ret_val; 1467 } 1468 } 1469 1470 if (hw->autoneg) { 1471 /* Setup autoneg and flow control advertisement 1472 * and perform autonegotiation 1473 */ 1474 ret_val = e1000_copper_link_autoneg(hw); 1475 if (ret_val) 1476 return ret_val; 1477 } else { 1478 /* PHY will be set to 10H, 10F, 100H,or 100F 1479 * depending on value from forced_speed_duplex. 1480 */ 1481 e_dbg("Forcing speed and duplex\n"); 1482 ret_val = e1000_phy_force_speed_duplex(hw); 1483 if (ret_val) { 1484 e_dbg("Error Forcing Speed and Duplex\n"); 1485 return ret_val; 1486 } 1487 } 1488 1489 /* Check link status. Wait up to 100 microseconds for link to become 1490 * valid. 1491 */ 1492 for (i = 0; i < 10; i++) { 1493 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1494 if (ret_val) 1495 return ret_val; 1496 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1497 if (ret_val) 1498 return ret_val; 1499 1500 if (phy_data & MII_SR_LINK_STATUS) { 1501 /* Config the MAC and PHY after link is up */ 1502 ret_val = e1000_copper_link_postconfig(hw); 1503 if (ret_val) 1504 return ret_val; 1505 1506 e_dbg("Valid link established!!!\n"); 1507 return E1000_SUCCESS; 1508 } 1509 udelay(10); 1510 } 1511 1512 e_dbg("Unable to establish link!!!\n"); 1513 return E1000_SUCCESS; 1514 } 1515 1516 /** 1517 * e1000_phy_setup_autoneg - phy settings 1518 * @hw: Struct containing variables accessed by shared code 1519 * 1520 * Configures PHY autoneg and flow control advertisement settings 1521 */ 1522 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1523 { 1524 s32 ret_val; 1525 u16 mii_autoneg_adv_reg; 1526 u16 mii_1000t_ctrl_reg; 1527 1528 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1529 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1530 if (ret_val) 1531 return ret_val; 1532 1533 /* Read the MII 1000Base-T Control Register (Address 9). */ 1534 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1535 if (ret_val) 1536 return ret_val; 1537 else if (hw->phy_type == e1000_phy_8201) 1538 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1539 1540 /* Need to parse both autoneg_advertised and fc and set up 1541 * the appropriate PHY registers. First we will parse for 1542 * autoneg_advertised software override. Since we can advertise 1543 * a plethora of combinations, we need to check each bit 1544 * individually. 1545 */ 1546 1547 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1548 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1549 * the 1000Base-T Control Register (Address 9). 1550 */ 1551 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1552 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1553 1554 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); 1555 1556 /* Do we want to advertise 10 Mb Half Duplex? */ 1557 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1558 e_dbg("Advertise 10mb Half duplex\n"); 1559 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1560 } 1561 1562 /* Do we want to advertise 10 Mb Full Duplex? */ 1563 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1564 e_dbg("Advertise 10mb Full duplex\n"); 1565 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1566 } 1567 1568 /* Do we want to advertise 100 Mb Half Duplex? */ 1569 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1570 e_dbg("Advertise 100mb Half duplex\n"); 1571 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1572 } 1573 1574 /* Do we want to advertise 100 Mb Full Duplex? */ 1575 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1576 e_dbg("Advertise 100mb Full duplex\n"); 1577 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1578 } 1579 1580 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1581 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1582 e_dbg 1583 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1584 } 1585 1586 /* Do we want to advertise 1000 Mb Full Duplex? */ 1587 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1588 e_dbg("Advertise 1000mb Full duplex\n"); 1589 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1590 } 1591 1592 /* Check for a software override of the flow control settings, and 1593 * setup the PHY advertisement registers accordingly. If 1594 * auto-negotiation is enabled, then software will have to set the 1595 * "PAUSE" bits to the correct value in the Auto-Negotiation 1596 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 1597 * auto-negotiation. 1598 * 1599 * The possible values of the "fc" parameter are: 1600 * 0: Flow control is completely disabled 1601 * 1: Rx flow control is enabled (we can receive pause frames 1602 * but not send pause frames). 1603 * 2: Tx flow control is enabled (we can send pause frames 1604 * but we do not support receiving pause frames). 1605 * 3: Both Rx and TX flow control (symmetric) are enabled. 1606 * other: No software override. The flow control configuration 1607 * in the EEPROM is used. 1608 */ 1609 switch (hw->fc) { 1610 case E1000_FC_NONE: /* 0 */ 1611 /* Flow control (RX & TX) is completely disabled by a 1612 * software over-ride. 1613 */ 1614 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1615 break; 1616 case E1000_FC_RX_PAUSE: /* 1 */ 1617 /* RX Flow control is enabled, and TX Flow control is 1618 * disabled, by a software over-ride. 1619 */ 1620 /* Since there really isn't a way to advertise that we are 1621 * capable of RX Pause ONLY, we will advertise that we 1622 * support both symmetric and asymmetric RX PAUSE. Later 1623 * (in e1000_config_fc_after_link_up) we will disable the 1624 * hw's ability to send PAUSE frames. 1625 */ 1626 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1627 break; 1628 case E1000_FC_TX_PAUSE: /* 2 */ 1629 /* TX Flow control is enabled, and RX Flow control is 1630 * disabled, by a software over-ride. 1631 */ 1632 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1633 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1634 break; 1635 case E1000_FC_FULL: /* 3 */ 1636 /* Flow control (both RX and TX) is enabled by a software 1637 * over-ride. 1638 */ 1639 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1640 break; 1641 default: 1642 e_dbg("Flow control param set incorrectly\n"); 1643 return -E1000_ERR_CONFIG; 1644 } 1645 1646 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1647 if (ret_val) 1648 return ret_val; 1649 1650 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1651 1652 if (hw->phy_type == e1000_phy_8201) { 1653 mii_1000t_ctrl_reg = 0; 1654 } else { 1655 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1656 mii_1000t_ctrl_reg); 1657 if (ret_val) 1658 return ret_val; 1659 } 1660 1661 return E1000_SUCCESS; 1662 } 1663 1664 /** 1665 * e1000_phy_force_speed_duplex - force link settings 1666 * @hw: Struct containing variables accessed by shared code 1667 * 1668 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1669 */ 1670 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1671 { 1672 u32 ctrl; 1673 s32 ret_val; 1674 u16 mii_ctrl_reg; 1675 u16 mii_status_reg; 1676 u16 phy_data; 1677 u16 i; 1678 1679 /* Turn off Flow control if we are forcing speed and duplex. */ 1680 hw->fc = E1000_FC_NONE; 1681 1682 e_dbg("hw->fc = %d\n", hw->fc); 1683 1684 /* Read the Device Control Register. */ 1685 ctrl = er32(CTRL); 1686 1687 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1688 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1689 ctrl &= ~(DEVICE_SPEED_MASK); 1690 1691 /* Clear the Auto Speed Detect Enable bit. */ 1692 ctrl &= ~E1000_CTRL_ASDE; 1693 1694 /* Read the MII Control Register. */ 1695 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1696 if (ret_val) 1697 return ret_val; 1698 1699 /* We need to disable autoneg in order to force link and duplex. */ 1700 1701 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1702 1703 /* Are we forcing Full or Half Duplex? */ 1704 if (hw->forced_speed_duplex == e1000_100_full || 1705 hw->forced_speed_duplex == e1000_10_full) { 1706 /* We want to force full duplex so we SET the full duplex bits 1707 * in the Device and MII Control Registers. 1708 */ 1709 ctrl |= E1000_CTRL_FD; 1710 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1711 e_dbg("Full Duplex\n"); 1712 } else { 1713 /* We want to force half duplex so we CLEAR the full duplex bits 1714 * in the Device and MII Control Registers. 1715 */ 1716 ctrl &= ~E1000_CTRL_FD; 1717 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1718 e_dbg("Half Duplex\n"); 1719 } 1720 1721 /* Are we forcing 100Mbps??? */ 1722 if (hw->forced_speed_duplex == e1000_100_full || 1723 hw->forced_speed_duplex == e1000_100_half) { 1724 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1725 ctrl |= E1000_CTRL_SPD_100; 1726 mii_ctrl_reg |= MII_CR_SPEED_100; 1727 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1728 e_dbg("Forcing 100mb "); 1729 } else { 1730 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1731 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1732 mii_ctrl_reg |= MII_CR_SPEED_10; 1733 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1734 e_dbg("Forcing 10mb "); 1735 } 1736 1737 e1000_config_collision_dist(hw); 1738 1739 /* Write the configured values back to the Device Control Reg. */ 1740 ew32(CTRL, ctrl); 1741 1742 if (hw->phy_type == e1000_phy_m88) { 1743 ret_val = 1744 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1745 if (ret_val) 1746 return ret_val; 1747 1748 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires 1749 * MDI forced whenever speed are duplex are forced. 1750 */ 1751 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1752 ret_val = 1753 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1754 if (ret_val) 1755 return ret_val; 1756 1757 e_dbg("M88E1000 PSCR: %x\n", phy_data); 1758 1759 /* Need to reset the PHY or these changes will be ignored */ 1760 mii_ctrl_reg |= MII_CR_RESET; 1761 1762 /* Disable MDI-X support for 10/100 */ 1763 } else { 1764 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1765 * forced whenever speed or duplex are forced. 1766 */ 1767 ret_val = 1768 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1769 if (ret_val) 1770 return ret_val; 1771 1772 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1773 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1774 1775 ret_val = 1776 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1777 if (ret_val) 1778 return ret_val; 1779 } 1780 1781 /* Write back the modified PHY MII control register. */ 1782 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1783 if (ret_val) 1784 return ret_val; 1785 1786 udelay(1); 1787 1788 /* The wait_autoneg_complete flag may be a little misleading here. 1789 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1790 * But we do want to delay for a period while forcing only so we 1791 * don't generate false No Link messages. So we will wait here 1792 * only if the user has set wait_autoneg_complete to 1, which is 1793 * the default. 1794 */ 1795 if (hw->wait_autoneg_complete) { 1796 /* We will wait for autoneg to complete. */ 1797 e_dbg("Waiting for forced speed/duplex link.\n"); 1798 mii_status_reg = 0; 1799 1800 /* Wait for autoneg to complete or 4.5 seconds to expire */ 1801 for (i = PHY_FORCE_TIME; i > 0; i--) { 1802 /* Read the MII Status Register and wait for Auto-Neg 1803 * Complete bit to be set. 1804 */ 1805 ret_val = 1806 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1807 if (ret_val) 1808 return ret_val; 1809 1810 ret_val = 1811 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1812 if (ret_val) 1813 return ret_val; 1814 1815 if (mii_status_reg & MII_SR_LINK_STATUS) 1816 break; 1817 msleep(100); 1818 } 1819 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { 1820 /* We didn't get link. Reset the DSP and wait again 1821 * for link. 1822 */ 1823 ret_val = e1000_phy_reset_dsp(hw); 1824 if (ret_val) { 1825 e_dbg("Error Resetting PHY DSP\n"); 1826 return ret_val; 1827 } 1828 } 1829 /* This loop will early-out if the link condition has been 1830 * met 1831 */ 1832 for (i = PHY_FORCE_TIME; i > 0; i--) { 1833 if (mii_status_reg & MII_SR_LINK_STATUS) 1834 break; 1835 msleep(100); 1836 /* Read the MII Status Register and wait for Auto-Neg 1837 * Complete bit to be set. 1838 */ 1839 ret_val = 1840 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1841 if (ret_val) 1842 return ret_val; 1843 1844 ret_val = 1845 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1846 if (ret_val) 1847 return ret_val; 1848 } 1849 } 1850 1851 if (hw->phy_type == e1000_phy_m88) { 1852 /* Because we reset the PHY above, we need to re-force TX_CLK in 1853 * the Extended PHY Specific Control Register to 25MHz clock. 1854 * This value defaults back to a 2.5MHz clock when the PHY is 1855 * reset. 1856 */ 1857 ret_val = 1858 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1859 &phy_data); 1860 if (ret_val) 1861 return ret_val; 1862 1863 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1864 ret_val = 1865 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1866 phy_data); 1867 if (ret_val) 1868 return ret_val; 1869 1870 /* In addition, because of the s/w reset above, we need to 1871 * enable CRS on Tx. This must be set for both full and half 1872 * duplex operation. 1873 */ 1874 ret_val = 1875 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1876 if (ret_val) 1877 return ret_val; 1878 1879 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1880 ret_val = 1881 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1882 if (ret_val) 1883 return ret_val; 1884 1885 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) 1886 && (!hw->autoneg) 1887 && (hw->forced_speed_duplex == e1000_10_full 1888 || hw->forced_speed_duplex == e1000_10_half)) { 1889 ret_val = e1000_polarity_reversal_workaround(hw); 1890 if (ret_val) 1891 return ret_val; 1892 } 1893 } 1894 return E1000_SUCCESS; 1895 } 1896 1897 /** 1898 * e1000_config_collision_dist - set collision distance register 1899 * @hw: Struct containing variables accessed by shared code 1900 * 1901 * Sets the collision distance in the Transmit Control register. 1902 * Link should have been established previously. Reads the speed and duplex 1903 * information from the Device Status register. 1904 */ 1905 void e1000_config_collision_dist(struct e1000_hw *hw) 1906 { 1907 u32 tctl, coll_dist; 1908 1909 if (hw->mac_type < e1000_82543) 1910 coll_dist = E1000_COLLISION_DISTANCE_82542; 1911 else 1912 coll_dist = E1000_COLLISION_DISTANCE; 1913 1914 tctl = er32(TCTL); 1915 1916 tctl &= ~E1000_TCTL_COLD; 1917 tctl |= coll_dist << E1000_COLD_SHIFT; 1918 1919 ew32(TCTL, tctl); 1920 E1000_WRITE_FLUSH(); 1921 } 1922 1923 /** 1924 * e1000_config_mac_to_phy - sync phy and mac settings 1925 * @hw: Struct containing variables accessed by shared code 1926 * @mii_reg: data to write to the MII control register 1927 * 1928 * Sets MAC speed and duplex settings to reflect the those in the PHY 1929 * The contents of the PHY register containing the needed information need to 1930 * be passed in. 1931 */ 1932 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1933 { 1934 u32 ctrl; 1935 s32 ret_val; 1936 u16 phy_data; 1937 1938 /* 82544 or newer MAC, Auto Speed Detection takes care of 1939 * MAC speed/duplex configuration. 1940 */ 1941 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) 1942 return E1000_SUCCESS; 1943 1944 /* Read the Device Control Register and set the bits to Force Speed 1945 * and Duplex. 1946 */ 1947 ctrl = er32(CTRL); 1948 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1949 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1950 1951 switch (hw->phy_type) { 1952 case e1000_phy_8201: 1953 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1954 if (ret_val) 1955 return ret_val; 1956 1957 if (phy_data & RTL_PHY_CTRL_FD) 1958 ctrl |= E1000_CTRL_FD; 1959 else 1960 ctrl &= ~E1000_CTRL_FD; 1961 1962 if (phy_data & RTL_PHY_CTRL_SPD_100) 1963 ctrl |= E1000_CTRL_SPD_100; 1964 else 1965 ctrl |= E1000_CTRL_SPD_10; 1966 1967 e1000_config_collision_dist(hw); 1968 break; 1969 default: 1970 /* Set up duplex in the Device Control and Transmit Control 1971 * registers depending on negotiated values. 1972 */ 1973 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 1974 &phy_data); 1975 if (ret_val) 1976 return ret_val; 1977 1978 if (phy_data & M88E1000_PSSR_DPLX) 1979 ctrl |= E1000_CTRL_FD; 1980 else 1981 ctrl &= ~E1000_CTRL_FD; 1982 1983 e1000_config_collision_dist(hw); 1984 1985 /* Set up speed in the Device Control register depending on 1986 * negotiated values. 1987 */ 1988 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1989 ctrl |= E1000_CTRL_SPD_1000; 1990 else if ((phy_data & M88E1000_PSSR_SPEED) == 1991 M88E1000_PSSR_100MBS) 1992 ctrl |= E1000_CTRL_SPD_100; 1993 } 1994 1995 /* Write the configured values back to the Device Control Reg. */ 1996 ew32(CTRL, ctrl); 1997 return E1000_SUCCESS; 1998 } 1999 2000 /** 2001 * e1000_force_mac_fc - force flow control settings 2002 * @hw: Struct containing variables accessed by shared code 2003 * 2004 * Forces the MAC's flow control settings. 2005 * Sets the TFCE and RFCE bits in the device control register to reflect 2006 * the adapter settings. TFCE and RFCE need to be explicitly set by 2007 * software when a Copper PHY is used because autonegotiation is managed 2008 * by the PHY rather than the MAC. Software must also configure these 2009 * bits when link is forced on a fiber connection. 2010 */ 2011 s32 e1000_force_mac_fc(struct e1000_hw *hw) 2012 { 2013 u32 ctrl; 2014 2015 /* Get the current configuration of the Device Control Register */ 2016 ctrl = er32(CTRL); 2017 2018 /* Because we didn't get link via the internal auto-negotiation 2019 * mechanism (we either forced link or we got link via PHY 2020 * auto-neg), we have to manually enable/disable transmit an 2021 * receive flow control. 2022 * 2023 * The "Case" statement below enables/disable flow control 2024 * according to the "hw->fc" parameter. 2025 * 2026 * The possible values of the "fc" parameter are: 2027 * 0: Flow control is completely disabled 2028 * 1: Rx flow control is enabled (we can receive pause 2029 * frames but not send pause frames). 2030 * 2: Tx flow control is enabled (we can send pause frames 2031 * frames but we do not receive pause frames). 2032 * 3: Both Rx and TX flow control (symmetric) is enabled. 2033 * other: No other values should be possible at this point. 2034 */ 2035 2036 switch (hw->fc) { 2037 case E1000_FC_NONE: 2038 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2039 break; 2040 case E1000_FC_RX_PAUSE: 2041 ctrl &= (~E1000_CTRL_TFCE); 2042 ctrl |= E1000_CTRL_RFCE; 2043 break; 2044 case E1000_FC_TX_PAUSE: 2045 ctrl &= (~E1000_CTRL_RFCE); 2046 ctrl |= E1000_CTRL_TFCE; 2047 break; 2048 case E1000_FC_FULL: 2049 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2050 break; 2051 default: 2052 e_dbg("Flow control param set incorrectly\n"); 2053 return -E1000_ERR_CONFIG; 2054 } 2055 2056 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2057 if (hw->mac_type == e1000_82542_rev2_0) 2058 ctrl &= (~E1000_CTRL_TFCE); 2059 2060 ew32(CTRL, ctrl); 2061 return E1000_SUCCESS; 2062 } 2063 2064 /** 2065 * e1000_config_fc_after_link_up - configure flow control after autoneg 2066 * @hw: Struct containing variables accessed by shared code 2067 * 2068 * Configures flow control settings after link is established 2069 * Should be called immediately after a valid link has been established. 2070 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2071 * and autonegotiation is enabled, the MAC flow control settings will be set 2072 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2073 * and RFCE bits will be automatically set to the negotiated flow control mode. 2074 */ 2075 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 2076 { 2077 s32 ret_val; 2078 u16 mii_status_reg; 2079 u16 mii_nway_adv_reg; 2080 u16 mii_nway_lp_ability_reg; 2081 u16 speed; 2082 u16 duplex; 2083 2084 /* Check for the case where we have fiber media and auto-neg failed 2085 * so we had to force link. In this case, we need to force the 2086 * configuration of the MAC to match the "fc" parameter. 2087 */ 2088 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 2089 || ((hw->media_type == e1000_media_type_internal_serdes) 2090 && (hw->autoneg_failed)) 2091 || ((hw->media_type == e1000_media_type_copper) 2092 && (!hw->autoneg))) { 2093 ret_val = e1000_force_mac_fc(hw); 2094 if (ret_val) { 2095 e_dbg("Error forcing flow control settings\n"); 2096 return ret_val; 2097 } 2098 } 2099 2100 /* Check for the case where we have copper media and auto-neg is 2101 * enabled. In this case, we need to check and see if Auto-Neg 2102 * has completed, and if so, how the PHY and link partner has 2103 * flow control configured. 2104 */ 2105 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2106 /* Read the MII Status Register and check to see if AutoNeg 2107 * has completed. We read this twice because this reg has 2108 * some "sticky" (latched) bits. 2109 */ 2110 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2111 if (ret_val) 2112 return ret_val; 2113 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2114 if (ret_val) 2115 return ret_val; 2116 2117 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2118 /* The AutoNeg process has completed, so we now need to 2119 * read both the Auto Negotiation Advertisement Register 2120 * (Address 4) and the Auto_Negotiation Base Page 2121 * Ability Register (Address 5) to determine how flow 2122 * control was negotiated. 2123 */ 2124 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2125 &mii_nway_adv_reg); 2126 if (ret_val) 2127 return ret_val; 2128 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2129 &mii_nway_lp_ability_reg); 2130 if (ret_val) 2131 return ret_val; 2132 2133 /* Two bits in the Auto Negotiation Advertisement 2134 * Register (Address 4) and two bits in the Auto 2135 * Negotiation Base Page Ability Register (Address 5) 2136 * determine flow control for both the PHY and the link 2137 * partner. The following table, taken out of the IEEE 2138 * 802.3ab/D6.0 dated March 25, 1999, describes these 2139 * PAUSE resolution bits and how flow control is 2140 * determined based upon these settings. 2141 * NOTE: DC = Don't Care 2142 * 2143 * LOCAL DEVICE | LINK PARTNER 2144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2145 *-------|---------|-------|---------|------------------ 2146 * 0 | 0 | DC | DC | E1000_FC_NONE 2147 * 0 | 1 | 0 | DC | E1000_FC_NONE 2148 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2149 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2150 * 1 | 0 | 0 | DC | E1000_FC_NONE 2151 * 1 | DC | 1 | DC | E1000_FC_FULL 2152 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2153 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2154 * 2155 */ 2156 /* Are both PAUSE bits set to 1? If so, this implies 2157 * Symmetric Flow Control is enabled at both ends. The 2158 * ASM_DIR bits are irrelevant per the spec. 2159 * 2160 * For Symmetric Flow Control: 2161 * 2162 * LOCAL DEVICE | LINK PARTNER 2163 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2164 *-------|---------|-------|---------|------------------ 2165 * 1 | DC | 1 | DC | E1000_FC_FULL 2166 * 2167 */ 2168 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2169 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2170 /* Now we need to check if the user selected Rx 2171 * ONLY of pause frames. In this case, we had 2172 * to advertise FULL flow control because we 2173 * could not advertise Rx ONLY. Hence, we must 2174 * now check to see if we need to turn OFF the 2175 * TRANSMISSION of PAUSE frames. 2176 */ 2177 if (hw->original_fc == E1000_FC_FULL) { 2178 hw->fc = E1000_FC_FULL; 2179 e_dbg("Flow Control = FULL.\n"); 2180 } else { 2181 hw->fc = E1000_FC_RX_PAUSE; 2182 e_dbg 2183 ("Flow Control = RX PAUSE frames only.\n"); 2184 } 2185 } 2186 /* For receiving PAUSE frames ONLY. 2187 * 2188 * LOCAL DEVICE | LINK PARTNER 2189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2190 *-------|---------|-------|---------|------------------ 2191 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2192 * 2193 */ 2194 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2195 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2196 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2197 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2198 { 2199 hw->fc = E1000_FC_TX_PAUSE; 2200 e_dbg 2201 ("Flow Control = TX PAUSE frames only.\n"); 2202 } 2203 /* For transmitting PAUSE frames ONLY. 2204 * 2205 * LOCAL DEVICE | LINK PARTNER 2206 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2207 *-------|---------|-------|---------|------------------ 2208 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2209 * 2210 */ 2211 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2212 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2213 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2214 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2215 { 2216 hw->fc = E1000_FC_RX_PAUSE; 2217 e_dbg 2218 ("Flow Control = RX PAUSE frames only.\n"); 2219 } 2220 /* Per the IEEE spec, at this point flow control should 2221 * be disabled. However, we want to consider that we 2222 * could be connected to a legacy switch that doesn't 2223 * advertise desired flow control, but can be forced on 2224 * the link partner. So if we advertised no flow 2225 * control, that is what we will resolve to. If we 2226 * advertised some kind of receive capability (Rx Pause 2227 * Only or Full Flow Control) and the link partner 2228 * advertised none, we will configure ourselves to 2229 * enable Rx Flow Control only. We can do this safely 2230 * for two reasons: If the link partner really 2231 * didn't want flow control enabled, and we enable Rx, 2232 * no harm done since we won't be receiving any PAUSE 2233 * frames anyway. If the intent on the link partner was 2234 * to have flow control enabled, then by us enabling Rx 2235 * only, we can at least receive pause frames and 2236 * process them. This is a good idea because in most 2237 * cases, since we are predominantly a server NIC, more 2238 * times than not we will be asked to delay transmission 2239 * of packets than asking our link partner to pause 2240 * transmission of frames. 2241 */ 2242 else if ((hw->original_fc == E1000_FC_NONE || 2243 hw->original_fc == E1000_FC_TX_PAUSE) || 2244 hw->fc_strict_ieee) { 2245 hw->fc = E1000_FC_NONE; 2246 e_dbg("Flow Control = NONE.\n"); 2247 } else { 2248 hw->fc = E1000_FC_RX_PAUSE; 2249 e_dbg 2250 ("Flow Control = RX PAUSE frames only.\n"); 2251 } 2252 2253 /* Now we need to do one last check... If we auto- 2254 * negotiated to HALF DUPLEX, flow control should not be 2255 * enabled per IEEE 802.3 spec. 2256 */ 2257 ret_val = 2258 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2259 if (ret_val) { 2260 e_dbg 2261 ("Error getting link speed and duplex\n"); 2262 return ret_val; 2263 } 2264 2265 if (duplex == HALF_DUPLEX) 2266 hw->fc = E1000_FC_NONE; 2267 2268 /* Now we call a subroutine to actually force the MAC 2269 * controller to use the correct flow control settings. 2270 */ 2271 ret_val = e1000_force_mac_fc(hw); 2272 if (ret_val) { 2273 e_dbg 2274 ("Error forcing flow control settings\n"); 2275 return ret_val; 2276 } 2277 } else { 2278 e_dbg 2279 ("Copper PHY and Auto Neg has not completed.\n"); 2280 } 2281 } 2282 return E1000_SUCCESS; 2283 } 2284 2285 /** 2286 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2287 * @hw: pointer to the HW structure 2288 * 2289 * Checks for link up on the hardware. If link is not up and we have 2290 * a signal, then we need to force link up. 2291 */ 2292 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2293 { 2294 u32 rxcw; 2295 u32 ctrl; 2296 u32 status; 2297 s32 ret_val = E1000_SUCCESS; 2298 2299 ctrl = er32(CTRL); 2300 status = er32(STATUS); 2301 rxcw = er32(RXCW); 2302 2303 /* If we don't have link (auto-negotiation failed or link partner 2304 * cannot auto-negotiate), and our link partner is not trying to 2305 * auto-negotiate with us (we are receiving idles or data), 2306 * we need to force link up. We also need to give auto-negotiation 2307 * time to complete. 2308 */ 2309 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 2310 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 2311 if (hw->autoneg_failed == 0) { 2312 hw->autoneg_failed = 1; 2313 goto out; 2314 } 2315 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 2316 2317 /* Disable auto-negotiation in the TXCW register */ 2318 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2319 2320 /* Force link-up and also force full-duplex. */ 2321 ctrl = er32(CTRL); 2322 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2323 ew32(CTRL, ctrl); 2324 2325 /* Configure Flow Control after forcing link up. */ 2326 ret_val = e1000_config_fc_after_link_up(hw); 2327 if (ret_val) { 2328 e_dbg("Error configuring flow control\n"); 2329 goto out; 2330 } 2331 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2332 /* If we are forcing link and we are receiving /C/ ordered 2333 * sets, re-enable auto-negotiation in the TXCW register 2334 * and disable forced link in the Device Control register 2335 * in an attempt to auto-negotiate with our link partner. 2336 */ 2337 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2338 ew32(TXCW, hw->txcw); 2339 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2340 2341 hw->serdes_has_link = true; 2342 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 2343 /* If we force link for non-auto-negotiation switch, check 2344 * link status based on MAC synchronization for internal 2345 * serdes media type. 2346 */ 2347 /* SYNCH bit and IV bit are sticky. */ 2348 udelay(10); 2349 rxcw = er32(RXCW); 2350 if (rxcw & E1000_RXCW_SYNCH) { 2351 if (!(rxcw & E1000_RXCW_IV)) { 2352 hw->serdes_has_link = true; 2353 e_dbg("SERDES: Link up - forced.\n"); 2354 } 2355 } else { 2356 hw->serdes_has_link = false; 2357 e_dbg("SERDES: Link down - force failed.\n"); 2358 } 2359 } 2360 2361 if (E1000_TXCW_ANE & er32(TXCW)) { 2362 status = er32(STATUS); 2363 if (status & E1000_STATUS_LU) { 2364 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 2365 udelay(10); 2366 rxcw = er32(RXCW); 2367 if (rxcw & E1000_RXCW_SYNCH) { 2368 if (!(rxcw & E1000_RXCW_IV)) { 2369 hw->serdes_has_link = true; 2370 e_dbg("SERDES: Link up - autoneg " 2371 "completed successfully.\n"); 2372 } else { 2373 hw->serdes_has_link = false; 2374 e_dbg("SERDES: Link down - invalid" 2375 "codewords detected in autoneg.\n"); 2376 } 2377 } else { 2378 hw->serdes_has_link = false; 2379 e_dbg("SERDES: Link down - no sync.\n"); 2380 } 2381 } else { 2382 hw->serdes_has_link = false; 2383 e_dbg("SERDES: Link down - autoneg failed\n"); 2384 } 2385 } 2386 2387 out: 2388 return ret_val; 2389 } 2390 2391 /** 2392 * e1000_check_for_link 2393 * @hw: Struct containing variables accessed by shared code 2394 * 2395 * Checks to see if the link status of the hardware has changed. 2396 * Called by any function that needs to check the link status of the adapter. 2397 */ 2398 s32 e1000_check_for_link(struct e1000_hw *hw) 2399 { 2400 u32 rxcw = 0; 2401 u32 ctrl; 2402 u32 status; 2403 u32 rctl; 2404 u32 icr; 2405 u32 signal = 0; 2406 s32 ret_val; 2407 u16 phy_data; 2408 2409 ctrl = er32(CTRL); 2410 status = er32(STATUS); 2411 2412 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be 2413 * set when the optics detect a signal. On older adapters, it will be 2414 * cleared when there is a signal. This applies to fiber media only. 2415 */ 2416 if ((hw->media_type == e1000_media_type_fiber) || 2417 (hw->media_type == e1000_media_type_internal_serdes)) { 2418 rxcw = er32(RXCW); 2419 2420 if (hw->media_type == e1000_media_type_fiber) { 2421 signal = 2422 (hw->mac_type > 2423 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2424 if (status & E1000_STATUS_LU) 2425 hw->get_link_status = false; 2426 } 2427 } 2428 2429 /* If we have a copper PHY then we only want to go out to the PHY 2430 * registers to see if Auto-Neg has completed and/or if our link 2431 * status has changed. The get_link_status flag will be set if we 2432 * receive a Link Status Change interrupt or we have Rx Sequence 2433 * Errors. 2434 */ 2435 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2436 /* First we want to see if the MII Status Register reports 2437 * link. If so, then we want to get the current speed/duplex 2438 * of the PHY. 2439 * Read the register twice since the link bit is sticky. 2440 */ 2441 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2442 if (ret_val) 2443 return ret_val; 2444 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2445 if (ret_val) 2446 return ret_val; 2447 2448 if (phy_data & MII_SR_LINK_STATUS) { 2449 hw->get_link_status = false; 2450 /* Check if there was DownShift, must be checked 2451 * immediately after link-up 2452 */ 2453 e1000_check_downshift(hw); 2454 2455 /* If we are on 82544 or 82543 silicon and speed/duplex 2456 * are forced to 10H or 10F, then we will implement the 2457 * polarity reversal workaround. We disable interrupts 2458 * first, and upon returning, place the devices 2459 * interrupt state to its previous value except for the 2460 * link status change interrupt which will 2461 * happen due to the execution of this workaround. 2462 */ 2463 2464 if ((hw->mac_type == e1000_82544 2465 || hw->mac_type == e1000_82543) && (!hw->autoneg) 2466 && (hw->forced_speed_duplex == e1000_10_full 2467 || hw->forced_speed_duplex == e1000_10_half)) { 2468 ew32(IMC, 0xffffffff); 2469 ret_val = 2470 e1000_polarity_reversal_workaround(hw); 2471 icr = er32(ICR); 2472 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2473 ew32(IMS, IMS_ENABLE_MASK); 2474 } 2475 2476 } else { 2477 /* No link detected */ 2478 e1000_config_dsp_after_link_change(hw, false); 2479 return 0; 2480 } 2481 2482 /* If we are forcing speed/duplex, then we simply return since 2483 * we have already determined whether we have link or not. 2484 */ 2485 if (!hw->autoneg) 2486 return -E1000_ERR_CONFIG; 2487 2488 /* optimize the dsp settings for the igp phy */ 2489 e1000_config_dsp_after_link_change(hw, true); 2490 2491 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2492 * have Si on board that is 82544 or newer, Auto 2493 * Speed Detection takes care of MAC speed/duplex 2494 * configuration. So we only need to configure Collision 2495 * Distance in the MAC. Otherwise, we need to force 2496 * speed/duplex on the MAC to the current PHY speed/duplex 2497 * settings. 2498 */ 2499 if ((hw->mac_type >= e1000_82544) && 2500 (hw->mac_type != e1000_ce4100)) 2501 e1000_config_collision_dist(hw); 2502 else { 2503 ret_val = e1000_config_mac_to_phy(hw); 2504 if (ret_val) { 2505 e_dbg 2506 ("Error configuring MAC to PHY settings\n"); 2507 return ret_val; 2508 } 2509 } 2510 2511 /* Configure Flow Control now that Auto-Neg has completed. 2512 * First, we need to restore the desired flow control settings 2513 * because we may have had to re-autoneg with a different link 2514 * partner. 2515 */ 2516 ret_val = e1000_config_fc_after_link_up(hw); 2517 if (ret_val) { 2518 e_dbg("Error configuring flow control\n"); 2519 return ret_val; 2520 } 2521 2522 /* At this point we know that we are on copper and we have 2523 * auto-negotiated link. These are conditions for checking the 2524 * link partner capability register. We use the link speed to 2525 * determine if TBI compatibility needs to be turned on or off. 2526 * If the link is not at gigabit speed, then TBI compatibility 2527 * is not needed. If we are at gigabit speed, we turn on TBI 2528 * compatibility. 2529 */ 2530 if (hw->tbi_compatibility_en) { 2531 u16 speed, duplex; 2532 ret_val = 2533 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2534 if (ret_val) { 2535 e_dbg 2536 ("Error getting link speed and duplex\n"); 2537 return ret_val; 2538 } 2539 if (speed != SPEED_1000) { 2540 /* If link speed is not set to gigabit speed, we 2541 * do not need to enable TBI compatibility. 2542 */ 2543 if (hw->tbi_compatibility_on) { 2544 /* If we previously were in the mode, 2545 * turn it off. 2546 */ 2547 rctl = er32(RCTL); 2548 rctl &= ~E1000_RCTL_SBP; 2549 ew32(RCTL, rctl); 2550 hw->tbi_compatibility_on = false; 2551 } 2552 } else { 2553 /* If TBI compatibility is was previously off, 2554 * turn it on. For compatibility with a TBI link 2555 * partner, we will store bad packets. Some 2556 * frames have an additional byte on the end and 2557 * will look like CRC errors to to the hardware. 2558 */ 2559 if (!hw->tbi_compatibility_on) { 2560 hw->tbi_compatibility_on = true; 2561 rctl = er32(RCTL); 2562 rctl |= E1000_RCTL_SBP; 2563 ew32(RCTL, rctl); 2564 } 2565 } 2566 } 2567 } 2568 2569 if ((hw->media_type == e1000_media_type_fiber) || 2570 (hw->media_type == e1000_media_type_internal_serdes)) 2571 e1000_check_for_serdes_link_generic(hw); 2572 2573 return E1000_SUCCESS; 2574 } 2575 2576 /** 2577 * e1000_get_speed_and_duplex 2578 * @hw: Struct containing variables accessed by shared code 2579 * @speed: Speed of the connection 2580 * @duplex: Duplex setting of the connection 2581 * 2582 * Detects the current speed and duplex settings of the hardware. 2583 */ 2584 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2585 { 2586 u32 status; 2587 s32 ret_val; 2588 u16 phy_data; 2589 2590 if (hw->mac_type >= e1000_82543) { 2591 status = er32(STATUS); 2592 if (status & E1000_STATUS_SPEED_1000) { 2593 *speed = SPEED_1000; 2594 e_dbg("1000 Mbs, "); 2595 } else if (status & E1000_STATUS_SPEED_100) { 2596 *speed = SPEED_100; 2597 e_dbg("100 Mbs, "); 2598 } else { 2599 *speed = SPEED_10; 2600 e_dbg("10 Mbs, "); 2601 } 2602 2603 if (status & E1000_STATUS_FD) { 2604 *duplex = FULL_DUPLEX; 2605 e_dbg("Full Duplex\n"); 2606 } else { 2607 *duplex = HALF_DUPLEX; 2608 e_dbg(" Half Duplex\n"); 2609 } 2610 } else { 2611 e_dbg("1000 Mbs, Full Duplex\n"); 2612 *speed = SPEED_1000; 2613 *duplex = FULL_DUPLEX; 2614 } 2615 2616 /* IGP01 PHY may advertise full duplex operation after speed downgrade 2617 * even if it is operating at half duplex. Here we set the duplex 2618 * settings to match the duplex in the link partner's capabilities. 2619 */ 2620 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2621 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2622 if (ret_val) 2623 return ret_val; 2624 2625 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2626 *duplex = HALF_DUPLEX; 2627 else { 2628 ret_val = 2629 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2630 if (ret_val) 2631 return ret_val; 2632 if ((*speed == SPEED_100 2633 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 2634 || (*speed == SPEED_10 2635 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2636 *duplex = HALF_DUPLEX; 2637 } 2638 } 2639 2640 return E1000_SUCCESS; 2641 } 2642 2643 /** 2644 * e1000_wait_autoneg 2645 * @hw: Struct containing variables accessed by shared code 2646 * 2647 * Blocks until autoneg completes or times out (~4.5 seconds) 2648 */ 2649 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2650 { 2651 s32 ret_val; 2652 u16 i; 2653 u16 phy_data; 2654 2655 e_dbg("Waiting for Auto-Neg to complete.\n"); 2656 2657 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2658 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2659 /* Read the MII Status Register and wait for Auto-Neg 2660 * Complete bit to be set. 2661 */ 2662 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2663 if (ret_val) 2664 return ret_val; 2665 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2666 if (ret_val) 2667 return ret_val; 2668 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2669 return E1000_SUCCESS; 2670 } 2671 msleep(100); 2672 } 2673 return E1000_SUCCESS; 2674 } 2675 2676 /** 2677 * e1000_raise_mdi_clk - Raises the Management Data Clock 2678 * @hw: Struct containing variables accessed by shared code 2679 * @ctrl: Device control register's current value 2680 */ 2681 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2682 { 2683 /* Raise the clock input to the Management Data Clock (by setting the 2684 * MDC bit), and then delay 10 microseconds. 2685 */ 2686 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2687 E1000_WRITE_FLUSH(); 2688 udelay(10); 2689 } 2690 2691 /** 2692 * e1000_lower_mdi_clk - Lowers the Management Data Clock 2693 * @hw: Struct containing variables accessed by shared code 2694 * @ctrl: Device control register's current value 2695 */ 2696 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2697 { 2698 /* Lower the clock input to the Management Data Clock (by clearing the 2699 * MDC bit), and then delay 10 microseconds. 2700 */ 2701 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2702 E1000_WRITE_FLUSH(); 2703 udelay(10); 2704 } 2705 2706 /** 2707 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY 2708 * @hw: Struct containing variables accessed by shared code 2709 * @data: Data to send out to the PHY 2710 * @count: Number of bits to shift out 2711 * 2712 * Bits are shifted out in MSB to LSB order. 2713 */ 2714 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2715 { 2716 u32 ctrl; 2717 u32 mask; 2718 2719 /* We need to shift "count" number of bits out to the PHY. So, the value 2720 * in the "data" parameter will be shifted out to the PHY one bit at a 2721 * time. In order to do this, "data" must be broken down into bits. 2722 */ 2723 mask = 0x01; 2724 mask <<= (count - 1); 2725 2726 ctrl = er32(CTRL); 2727 2728 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2729 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2730 2731 while (mask) { 2732 /* A "1" is shifted out to the PHY by setting the MDIO bit to 2733 * "1" and then raising and lowering the Management Data Clock. 2734 * A "0" is shifted out to the PHY by setting the MDIO bit to 2735 * "0" and then raising and lowering the clock. 2736 */ 2737 if (data & mask) 2738 ctrl |= E1000_CTRL_MDIO; 2739 else 2740 ctrl &= ~E1000_CTRL_MDIO; 2741 2742 ew32(CTRL, ctrl); 2743 E1000_WRITE_FLUSH(); 2744 2745 udelay(10); 2746 2747 e1000_raise_mdi_clk(hw, &ctrl); 2748 e1000_lower_mdi_clk(hw, &ctrl); 2749 2750 mask = mask >> 1; 2751 } 2752 } 2753 2754 /** 2755 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY 2756 * @hw: Struct containing variables accessed by shared code 2757 * 2758 * Bits are shifted in in MSB to LSB order. 2759 */ 2760 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2761 { 2762 u32 ctrl; 2763 u16 data = 0; 2764 u8 i; 2765 2766 /* In order to read a register from the PHY, we need to shift in a total 2767 * of 18 bits from the PHY. The first two bit (turnaround) times are 2768 * used to avoid contention on the MDIO pin when a read operation is 2769 * performed. These two bits are ignored by us and thrown away. Bits are 2770 * "shifted in" by raising the input to the Management Data Clock 2771 * (setting the MDC bit), and then reading the value of the MDIO bit. 2772 */ 2773 ctrl = er32(CTRL); 2774 2775 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 2776 * input. 2777 */ 2778 ctrl &= ~E1000_CTRL_MDIO_DIR; 2779 ctrl &= ~E1000_CTRL_MDIO; 2780 2781 ew32(CTRL, ctrl); 2782 E1000_WRITE_FLUSH(); 2783 2784 /* Raise and Lower the clock before reading in the data. This accounts 2785 * for the turnaround bits. The first clock occurred when we clocked out 2786 * the last bit of the Register Address. 2787 */ 2788 e1000_raise_mdi_clk(hw, &ctrl); 2789 e1000_lower_mdi_clk(hw, &ctrl); 2790 2791 for (data = 0, i = 0; i < 16; i++) { 2792 data = data << 1; 2793 e1000_raise_mdi_clk(hw, &ctrl); 2794 ctrl = er32(CTRL); 2795 /* Check to see if we shifted in a "1". */ 2796 if (ctrl & E1000_CTRL_MDIO) 2797 data |= 1; 2798 e1000_lower_mdi_clk(hw, &ctrl); 2799 } 2800 2801 e1000_raise_mdi_clk(hw, &ctrl); 2802 e1000_lower_mdi_clk(hw, &ctrl); 2803 2804 return data; 2805 } 2806 2807 2808 /** 2809 * e1000_read_phy_reg - read a phy register 2810 * @hw: Struct containing variables accessed by shared code 2811 * @reg_addr: address of the PHY register to read 2812 * 2813 * Reads the value from a PHY register, if the value is on a specific non zero 2814 * page, sets the page first. 2815 */ 2816 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2817 { 2818 u32 ret_val; 2819 unsigned long flags; 2820 2821 spin_lock_irqsave(&e1000_phy_lock, flags); 2822 2823 if ((hw->phy_type == e1000_phy_igp) && 2824 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2825 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2826 (u16) reg_addr); 2827 if (ret_val) { 2828 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2829 return ret_val; 2830 } 2831 } 2832 2833 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2834 phy_data); 2835 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2836 2837 return ret_val; 2838 } 2839 2840 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2841 u16 *phy_data) 2842 { 2843 u32 i; 2844 u32 mdic = 0; 2845 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2846 2847 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2848 e_dbg("PHY Address %d is out of range\n", reg_addr); 2849 return -E1000_ERR_PARAM; 2850 } 2851 2852 if (hw->mac_type > e1000_82543) { 2853 /* Set up Op-code, Phy Address, and register address in the MDI 2854 * Control register. The MAC will take care of interfacing with 2855 * the PHY to retrieve the desired data. 2856 */ 2857 if (hw->mac_type == e1000_ce4100) { 2858 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2859 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2860 (INTEL_CE_GBE_MDIC_OP_READ) | 2861 (INTEL_CE_GBE_MDIC_GO)); 2862 2863 writel(mdic, E1000_MDIO_CMD); 2864 2865 /* Poll the ready bit to see if the MDI read 2866 * completed 2867 */ 2868 for (i = 0; i < 64; i++) { 2869 udelay(50); 2870 mdic = readl(E1000_MDIO_CMD); 2871 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 2872 break; 2873 } 2874 2875 if (mdic & INTEL_CE_GBE_MDIC_GO) { 2876 e_dbg("MDI Read did not complete\n"); 2877 return -E1000_ERR_PHY; 2878 } 2879 2880 mdic = readl(E1000_MDIO_STS); 2881 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { 2882 e_dbg("MDI Read Error\n"); 2883 return -E1000_ERR_PHY; 2884 } 2885 *phy_data = (u16) mdic; 2886 } else { 2887 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2888 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2889 (E1000_MDIC_OP_READ)); 2890 2891 ew32(MDIC, mdic); 2892 2893 /* Poll the ready bit to see if the MDI read 2894 * completed 2895 */ 2896 for (i = 0; i < 64; i++) { 2897 udelay(50); 2898 mdic = er32(MDIC); 2899 if (mdic & E1000_MDIC_READY) 2900 break; 2901 } 2902 if (!(mdic & E1000_MDIC_READY)) { 2903 e_dbg("MDI Read did not complete\n"); 2904 return -E1000_ERR_PHY; 2905 } 2906 if (mdic & E1000_MDIC_ERROR) { 2907 e_dbg("MDI Error\n"); 2908 return -E1000_ERR_PHY; 2909 } 2910 *phy_data = (u16) mdic; 2911 } 2912 } else { 2913 /* We must first send a preamble through the MDIO pin to signal 2914 * the beginning of an MII instruction. This is done by sending 2915 * 32 consecutive "1" bits. 2916 */ 2917 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2918 2919 /* Now combine the next few fields that are required for a read 2920 * operation. We use this method instead of calling the 2921 * e1000_shift_out_mdi_bits routine five different times. The 2922 * format of a MII read instruction consists of a shift out of 2923 * 14 bits and is defined as follows: 2924 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2925 * followed by a shift in of 18 bits. This first two bits 2926 * shifted in are TurnAround bits used to avoid contention on 2927 * the MDIO pin when a READ operation is performed. These two 2928 * bits are thrown away followed by a shift in of 16 bits which 2929 * contains the desired data. 2930 */ 2931 mdic = ((reg_addr) | (phy_addr << 5) | 2932 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2933 2934 e1000_shift_out_mdi_bits(hw, mdic, 14); 2935 2936 /* Now that we've shifted out the read command to the MII, we 2937 * need to "shift in" the 16-bit value (18 total bits) of the 2938 * requested PHY register address. 2939 */ 2940 *phy_data = e1000_shift_in_mdi_bits(hw); 2941 } 2942 return E1000_SUCCESS; 2943 } 2944 2945 /** 2946 * e1000_write_phy_reg - write a phy register 2947 * 2948 * @hw: Struct containing variables accessed by shared code 2949 * @reg_addr: address of the PHY register to write 2950 * @data: data to write to the PHY 2951 * 2952 * Writes a value to a PHY register 2953 */ 2954 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2955 { 2956 u32 ret_val; 2957 unsigned long flags; 2958 2959 spin_lock_irqsave(&e1000_phy_lock, flags); 2960 2961 if ((hw->phy_type == e1000_phy_igp) && 2962 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2963 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2964 (u16) reg_addr); 2965 if (ret_val) { 2966 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2967 return ret_val; 2968 } 2969 } 2970 2971 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2972 phy_data); 2973 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2974 2975 return ret_val; 2976 } 2977 2978 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2979 u16 phy_data) 2980 { 2981 u32 i; 2982 u32 mdic = 0; 2983 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2984 2985 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2986 e_dbg("PHY Address %d is out of range\n", reg_addr); 2987 return -E1000_ERR_PARAM; 2988 } 2989 2990 if (hw->mac_type > e1000_82543) { 2991 /* Set up Op-code, Phy Address, register address, and data 2992 * intended for the PHY register in the MDI Control register. 2993 * The MAC will take care of interfacing with the PHY to send 2994 * the desired data. 2995 */ 2996 if (hw->mac_type == e1000_ce4100) { 2997 mdic = (((u32) phy_data) | 2998 (reg_addr << E1000_MDIC_REG_SHIFT) | 2999 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3000 (INTEL_CE_GBE_MDIC_OP_WRITE) | 3001 (INTEL_CE_GBE_MDIC_GO)); 3002 3003 writel(mdic, E1000_MDIO_CMD); 3004 3005 /* Poll the ready bit to see if the MDI read 3006 * completed 3007 */ 3008 for (i = 0; i < 640; i++) { 3009 udelay(5); 3010 mdic = readl(E1000_MDIO_CMD); 3011 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 3012 break; 3013 } 3014 if (mdic & INTEL_CE_GBE_MDIC_GO) { 3015 e_dbg("MDI Write did not complete\n"); 3016 return -E1000_ERR_PHY; 3017 } 3018 } else { 3019 mdic = (((u32) phy_data) | 3020 (reg_addr << E1000_MDIC_REG_SHIFT) | 3021 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3022 (E1000_MDIC_OP_WRITE)); 3023 3024 ew32(MDIC, mdic); 3025 3026 /* Poll the ready bit to see if the MDI read 3027 * completed 3028 */ 3029 for (i = 0; i < 641; i++) { 3030 udelay(5); 3031 mdic = er32(MDIC); 3032 if (mdic & E1000_MDIC_READY) 3033 break; 3034 } 3035 if (!(mdic & E1000_MDIC_READY)) { 3036 e_dbg("MDI Write did not complete\n"); 3037 return -E1000_ERR_PHY; 3038 } 3039 } 3040 } else { 3041 /* We'll need to use the SW defined pins to shift the write 3042 * command out to the PHY. We first send a preamble to the PHY 3043 * to signal the beginning of the MII instruction. This is done 3044 * by sending 32 consecutive "1" bits. 3045 */ 3046 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3047 3048 /* Now combine the remaining required fields that will indicate 3049 * a write operation. We use this method instead of calling the 3050 * e1000_shift_out_mdi_bits routine for each field in the 3051 * command. The format of a MII write instruction is as follows: 3052 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>. 3053 */ 3054 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3055 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3056 mdic <<= 16; 3057 mdic |= (u32) phy_data; 3058 3059 e1000_shift_out_mdi_bits(hw, mdic, 32); 3060 } 3061 3062 return E1000_SUCCESS; 3063 } 3064 3065 /** 3066 * e1000_phy_hw_reset - reset the phy, hardware style 3067 * @hw: Struct containing variables accessed by shared code 3068 * 3069 * Returns the PHY to the power-on reset state 3070 */ 3071 s32 e1000_phy_hw_reset(struct e1000_hw *hw) 3072 { 3073 u32 ctrl, ctrl_ext; 3074 u32 led_ctrl; 3075 3076 e_dbg("Resetting Phy...\n"); 3077 3078 if (hw->mac_type > e1000_82543) { 3079 /* Read the device control register and assert the 3080 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. 3081 * For e1000 hardware, we delay for 10ms between the assert 3082 * and de-assert. 3083 */ 3084 ctrl = er32(CTRL); 3085 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 3086 E1000_WRITE_FLUSH(); 3087 3088 msleep(10); 3089 3090 ew32(CTRL, ctrl); 3091 E1000_WRITE_FLUSH(); 3092 3093 } else { 3094 /* Read the Extended Device Control Register, assert the 3095 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 3096 * out of reset. 3097 */ 3098 ctrl_ext = er32(CTRL_EXT); 3099 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3100 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3101 ew32(CTRL_EXT, ctrl_ext); 3102 E1000_WRITE_FLUSH(); 3103 msleep(10); 3104 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3105 ew32(CTRL_EXT, ctrl_ext); 3106 E1000_WRITE_FLUSH(); 3107 } 3108 udelay(150); 3109 3110 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3111 /* Configure activity LED after PHY reset */ 3112 led_ctrl = er32(LEDCTL); 3113 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3114 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3115 ew32(LEDCTL, led_ctrl); 3116 } 3117 3118 /* Wait for FW to finish PHY configuration. */ 3119 return e1000_get_phy_cfg_done(hw); 3120 } 3121 3122 /** 3123 * e1000_phy_reset - reset the phy to commit settings 3124 * @hw: Struct containing variables accessed by shared code 3125 * 3126 * Resets the PHY 3127 * Sets bit 15 of the MII Control register 3128 */ 3129 s32 e1000_phy_reset(struct e1000_hw *hw) 3130 { 3131 s32 ret_val; 3132 u16 phy_data; 3133 3134 switch (hw->phy_type) { 3135 case e1000_phy_igp: 3136 ret_val = e1000_phy_hw_reset(hw); 3137 if (ret_val) 3138 return ret_val; 3139 break; 3140 default: 3141 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3142 if (ret_val) 3143 return ret_val; 3144 3145 phy_data |= MII_CR_RESET; 3146 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3147 if (ret_val) 3148 return ret_val; 3149 3150 udelay(1); 3151 break; 3152 } 3153 3154 if (hw->phy_type == e1000_phy_igp) 3155 e1000_phy_init_script(hw); 3156 3157 return E1000_SUCCESS; 3158 } 3159 3160 /** 3161 * e1000_detect_gig_phy - check the phy type 3162 * @hw: Struct containing variables accessed by shared code 3163 * 3164 * Probes the expected PHY address for known PHY IDs 3165 */ 3166 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3167 { 3168 s32 phy_init_status, ret_val; 3169 u16 phy_id_high, phy_id_low; 3170 bool match = false; 3171 3172 if (hw->phy_id != 0) 3173 return E1000_SUCCESS; 3174 3175 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3176 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3177 if (ret_val) 3178 return ret_val; 3179 3180 hw->phy_id = (u32) (phy_id_high << 16); 3181 udelay(20); 3182 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3183 if (ret_val) 3184 return ret_val; 3185 3186 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); 3187 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; 3188 3189 switch (hw->mac_type) { 3190 case e1000_82543: 3191 if (hw->phy_id == M88E1000_E_PHY_ID) 3192 match = true; 3193 break; 3194 case e1000_82544: 3195 if (hw->phy_id == M88E1000_I_PHY_ID) 3196 match = true; 3197 break; 3198 case e1000_82540: 3199 case e1000_82545: 3200 case e1000_82545_rev_3: 3201 case e1000_82546: 3202 case e1000_82546_rev_3: 3203 if (hw->phy_id == M88E1011_I_PHY_ID) 3204 match = true; 3205 break; 3206 case e1000_ce4100: 3207 if ((hw->phy_id == RTL8211B_PHY_ID) || 3208 (hw->phy_id == RTL8201N_PHY_ID) || 3209 (hw->phy_id == M88E1118_E_PHY_ID)) 3210 match = true; 3211 break; 3212 case e1000_82541: 3213 case e1000_82541_rev_2: 3214 case e1000_82547: 3215 case e1000_82547_rev_2: 3216 if (hw->phy_id == IGP01E1000_I_PHY_ID) 3217 match = true; 3218 break; 3219 default: 3220 e_dbg("Invalid MAC type %d\n", hw->mac_type); 3221 return -E1000_ERR_CONFIG; 3222 } 3223 phy_init_status = e1000_set_phy_type(hw); 3224 3225 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3226 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); 3227 return E1000_SUCCESS; 3228 } 3229 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); 3230 return -E1000_ERR_PHY; 3231 } 3232 3233 /** 3234 * e1000_phy_reset_dsp - reset DSP 3235 * @hw: Struct containing variables accessed by shared code 3236 * 3237 * Resets the PHY's DSP 3238 */ 3239 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3240 { 3241 s32 ret_val; 3242 3243 do { 3244 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3245 if (ret_val) 3246 break; 3247 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3248 if (ret_val) 3249 break; 3250 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3251 if (ret_val) 3252 break; 3253 ret_val = E1000_SUCCESS; 3254 } while (0); 3255 3256 return ret_val; 3257 } 3258 3259 /** 3260 * e1000_phy_igp_get_info - get igp specific registers 3261 * @hw: Struct containing variables accessed by shared code 3262 * @phy_info: PHY information structure 3263 * 3264 * Get PHY information from various PHY registers for igp PHY only. 3265 */ 3266 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3267 struct e1000_phy_info *phy_info) 3268 { 3269 s32 ret_val; 3270 u16 phy_data, min_length, max_length, average; 3271 e1000_rev_polarity polarity; 3272 3273 /* The downshift status is checked only once, after link is established, 3274 * and it stored in the hw->speed_downgraded parameter. 3275 */ 3276 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3277 3278 /* IGP01E1000 does not need to support it. */ 3279 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3280 3281 /* IGP01E1000 always correct polarity reversal */ 3282 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3283 3284 /* Check polarity status */ 3285 ret_val = e1000_check_polarity(hw, &polarity); 3286 if (ret_val) 3287 return ret_val; 3288 3289 phy_info->cable_polarity = polarity; 3290 3291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3292 if (ret_val) 3293 return ret_val; 3294 3295 phy_info->mdix_mode = 3296 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3297 IGP01E1000_PSSR_MDIX_SHIFT); 3298 3299 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3300 IGP01E1000_PSSR_SPEED_1000MBPS) { 3301 /* Local/Remote Receiver Information are only valid @ 1000 3302 * Mbps 3303 */ 3304 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3305 if (ret_val) 3306 return ret_val; 3307 3308 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3309 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3310 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3311 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3312 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3313 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3314 3315 /* Get cable length */ 3316 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3317 if (ret_val) 3318 return ret_val; 3319 3320 /* Translate to old method */ 3321 average = (max_length + min_length) / 2; 3322 3323 if (average <= e1000_igp_cable_length_50) 3324 phy_info->cable_length = e1000_cable_length_50; 3325 else if (average <= e1000_igp_cable_length_80) 3326 phy_info->cable_length = e1000_cable_length_50_80; 3327 else if (average <= e1000_igp_cable_length_110) 3328 phy_info->cable_length = e1000_cable_length_80_110; 3329 else if (average <= e1000_igp_cable_length_140) 3330 phy_info->cable_length = e1000_cable_length_110_140; 3331 else 3332 phy_info->cable_length = e1000_cable_length_140; 3333 } 3334 3335 return E1000_SUCCESS; 3336 } 3337 3338 /** 3339 * e1000_phy_m88_get_info - get m88 specific registers 3340 * @hw: Struct containing variables accessed by shared code 3341 * @phy_info: PHY information structure 3342 * 3343 * Get PHY information from various PHY registers for m88 PHY only. 3344 */ 3345 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3346 struct e1000_phy_info *phy_info) 3347 { 3348 s32 ret_val; 3349 u16 phy_data; 3350 e1000_rev_polarity polarity; 3351 3352 /* The downshift status is checked only once, after link is established, 3353 * and it stored in the hw->speed_downgraded parameter. 3354 */ 3355 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3356 3357 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3358 if (ret_val) 3359 return ret_val; 3360 3361 phy_info->extended_10bt_distance = 3362 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3363 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3364 e1000_10bt_ext_dist_enable_lower : 3365 e1000_10bt_ext_dist_enable_normal; 3366 3367 phy_info->polarity_correction = 3368 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3369 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3370 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3371 3372 /* Check polarity status */ 3373 ret_val = e1000_check_polarity(hw, &polarity); 3374 if (ret_val) 3375 return ret_val; 3376 phy_info->cable_polarity = polarity; 3377 3378 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3379 if (ret_val) 3380 return ret_val; 3381 3382 phy_info->mdix_mode = 3383 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3384 M88E1000_PSSR_MDIX_SHIFT); 3385 3386 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3387 /* Cable Length Estimation and Local/Remote Receiver Information 3388 * are only valid at 1000 Mbps. 3389 */ 3390 phy_info->cable_length = 3391 (e1000_cable_length) ((phy_data & 3392 M88E1000_PSSR_CABLE_LENGTH) >> 3393 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3394 3395 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3396 if (ret_val) 3397 return ret_val; 3398 3399 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3400 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3401 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3402 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3403 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3404 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3405 3406 } 3407 3408 return E1000_SUCCESS; 3409 } 3410 3411 /** 3412 * e1000_phy_get_info - request phy info 3413 * @hw: Struct containing variables accessed by shared code 3414 * @phy_info: PHY information structure 3415 * 3416 * Get PHY information from various PHY registers 3417 */ 3418 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3419 { 3420 s32 ret_val; 3421 u16 phy_data; 3422 3423 phy_info->cable_length = e1000_cable_length_undefined; 3424 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3425 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3426 phy_info->downshift = e1000_downshift_undefined; 3427 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3428 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3429 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3430 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3431 3432 if (hw->media_type != e1000_media_type_copper) { 3433 e_dbg("PHY info is only valid for copper media\n"); 3434 return -E1000_ERR_CONFIG; 3435 } 3436 3437 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3438 if (ret_val) 3439 return ret_val; 3440 3441 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3442 if (ret_val) 3443 return ret_val; 3444 3445 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3446 e_dbg("PHY info is only valid if link is up\n"); 3447 return -E1000_ERR_CONFIG; 3448 } 3449 3450 if (hw->phy_type == e1000_phy_igp) 3451 return e1000_phy_igp_get_info(hw, phy_info); 3452 else if ((hw->phy_type == e1000_phy_8211) || 3453 (hw->phy_type == e1000_phy_8201)) 3454 return E1000_SUCCESS; 3455 else 3456 return e1000_phy_m88_get_info(hw, phy_info); 3457 } 3458 3459 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3460 { 3461 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3462 e_dbg("Invalid MDI setting detected\n"); 3463 hw->mdix = 1; 3464 return -E1000_ERR_CONFIG; 3465 } 3466 return E1000_SUCCESS; 3467 } 3468 3469 /** 3470 * e1000_init_eeprom_params - initialize sw eeprom vars 3471 * @hw: Struct containing variables accessed by shared code 3472 * 3473 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3474 * is configured. 3475 */ 3476 s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3477 { 3478 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3479 u32 eecd = er32(EECD); 3480 s32 ret_val = E1000_SUCCESS; 3481 u16 eeprom_size; 3482 3483 switch (hw->mac_type) { 3484 case e1000_82542_rev2_0: 3485 case e1000_82542_rev2_1: 3486 case e1000_82543: 3487 case e1000_82544: 3488 eeprom->type = e1000_eeprom_microwire; 3489 eeprom->word_size = 64; 3490 eeprom->opcode_bits = 3; 3491 eeprom->address_bits = 6; 3492 eeprom->delay_usec = 50; 3493 break; 3494 case e1000_82540: 3495 case e1000_82545: 3496 case e1000_82545_rev_3: 3497 case e1000_82546: 3498 case e1000_82546_rev_3: 3499 eeprom->type = e1000_eeprom_microwire; 3500 eeprom->opcode_bits = 3; 3501 eeprom->delay_usec = 50; 3502 if (eecd & E1000_EECD_SIZE) { 3503 eeprom->word_size = 256; 3504 eeprom->address_bits = 8; 3505 } else { 3506 eeprom->word_size = 64; 3507 eeprom->address_bits = 6; 3508 } 3509 break; 3510 case e1000_82541: 3511 case e1000_82541_rev_2: 3512 case e1000_82547: 3513 case e1000_82547_rev_2: 3514 if (eecd & E1000_EECD_TYPE) { 3515 eeprom->type = e1000_eeprom_spi; 3516 eeprom->opcode_bits = 8; 3517 eeprom->delay_usec = 1; 3518 if (eecd & E1000_EECD_ADDR_BITS) { 3519 eeprom->page_size = 32; 3520 eeprom->address_bits = 16; 3521 } else { 3522 eeprom->page_size = 8; 3523 eeprom->address_bits = 8; 3524 } 3525 } else { 3526 eeprom->type = e1000_eeprom_microwire; 3527 eeprom->opcode_bits = 3; 3528 eeprom->delay_usec = 50; 3529 if (eecd & E1000_EECD_ADDR_BITS) { 3530 eeprom->word_size = 256; 3531 eeprom->address_bits = 8; 3532 } else { 3533 eeprom->word_size = 64; 3534 eeprom->address_bits = 6; 3535 } 3536 } 3537 break; 3538 default: 3539 break; 3540 } 3541 3542 if (eeprom->type == e1000_eeprom_spi) { 3543 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 3544 * 128B to 32KB (incremented by powers of 2). 3545 */ 3546 /* Set to default value for initial eeprom read. */ 3547 eeprom->word_size = 64; 3548 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3549 if (ret_val) 3550 return ret_val; 3551 eeprom_size = 3552 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3553 /* 256B eeprom size was not supported in earlier hardware, so we 3554 * bump eeprom_size up one to ensure that "1" (which maps to 3555 * 256B) is never the result used in the shifting logic below. 3556 */ 3557 if (eeprom_size) 3558 eeprom_size++; 3559 3560 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3561 } 3562 return ret_val; 3563 } 3564 3565 /** 3566 * e1000_raise_ee_clk - Raises the EEPROM's clock input. 3567 * @hw: Struct containing variables accessed by shared code 3568 * @eecd: EECD's current value 3569 */ 3570 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3571 { 3572 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3573 * wait <delay> microseconds. 3574 */ 3575 *eecd = *eecd | E1000_EECD_SK; 3576 ew32(EECD, *eecd); 3577 E1000_WRITE_FLUSH(); 3578 udelay(hw->eeprom.delay_usec); 3579 } 3580 3581 /** 3582 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. 3583 * @hw: Struct containing variables accessed by shared code 3584 * @eecd: EECD's current value 3585 */ 3586 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3587 { 3588 /* Lower the clock input to the EEPROM (by clearing the SK bit), and 3589 * then wait 50 microseconds. 3590 */ 3591 *eecd = *eecd & ~E1000_EECD_SK; 3592 ew32(EECD, *eecd); 3593 E1000_WRITE_FLUSH(); 3594 udelay(hw->eeprom.delay_usec); 3595 } 3596 3597 /** 3598 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. 3599 * @hw: Struct containing variables accessed by shared code 3600 * @data: data to send to the EEPROM 3601 * @count: number of bits to shift out 3602 */ 3603 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3604 { 3605 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3606 u32 eecd; 3607 u32 mask; 3608 3609 /* We need to shift "count" bits out to the EEPROM. So, value in the 3610 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3611 * In order to do this, "data" must be broken down into bits. 3612 */ 3613 mask = 0x01 << (count - 1); 3614 eecd = er32(EECD); 3615 if (eeprom->type == e1000_eeprom_microwire) { 3616 eecd &= ~E1000_EECD_DO; 3617 } else if (eeprom->type == e1000_eeprom_spi) { 3618 eecd |= E1000_EECD_DO; 3619 } 3620 do { 3621 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a 3622 * "1", and then raising and then lowering the clock (the SK bit 3623 * controls the clock input to the EEPROM). A "0" is shifted 3624 * out to the EEPROM by setting "DI" to "0" and then raising and 3625 * then lowering the clock. 3626 */ 3627 eecd &= ~E1000_EECD_DI; 3628 3629 if (data & mask) 3630 eecd |= E1000_EECD_DI; 3631 3632 ew32(EECD, eecd); 3633 E1000_WRITE_FLUSH(); 3634 3635 udelay(eeprom->delay_usec); 3636 3637 e1000_raise_ee_clk(hw, &eecd); 3638 e1000_lower_ee_clk(hw, &eecd); 3639 3640 mask = mask >> 1; 3641 3642 } while (mask); 3643 3644 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3645 eecd &= ~E1000_EECD_DI; 3646 ew32(EECD, eecd); 3647 } 3648 3649 /** 3650 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM 3651 * @hw: Struct containing variables accessed by shared code 3652 * @count: number of bits to shift in 3653 */ 3654 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3655 { 3656 u32 eecd; 3657 u32 i; 3658 u16 data; 3659 3660 /* In order to read a register from the EEPROM, we need to shift 'count' 3661 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3662 * input to the EEPROM (setting the SK bit), and then reading the value 3663 * of the "DO" bit. During this "shifting in" process the "DI" bit 3664 * should always be clear. 3665 */ 3666 3667 eecd = er32(EECD); 3668 3669 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3670 data = 0; 3671 3672 for (i = 0; i < count; i++) { 3673 data = data << 1; 3674 e1000_raise_ee_clk(hw, &eecd); 3675 3676 eecd = er32(EECD); 3677 3678 eecd &= ~(E1000_EECD_DI); 3679 if (eecd & E1000_EECD_DO) 3680 data |= 1; 3681 3682 e1000_lower_ee_clk(hw, &eecd); 3683 } 3684 3685 return data; 3686 } 3687 3688 /** 3689 * e1000_acquire_eeprom - Prepares EEPROM for access 3690 * @hw: Struct containing variables accessed by shared code 3691 * 3692 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3693 * function should be called before issuing a command to the EEPROM. 3694 */ 3695 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3696 { 3697 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3698 u32 eecd, i = 0; 3699 3700 eecd = er32(EECD); 3701 3702 /* Request EEPROM Access */ 3703 if (hw->mac_type > e1000_82544) { 3704 eecd |= E1000_EECD_REQ; 3705 ew32(EECD, eecd); 3706 eecd = er32(EECD); 3707 while ((!(eecd & E1000_EECD_GNT)) && 3708 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3709 i++; 3710 udelay(5); 3711 eecd = er32(EECD); 3712 } 3713 if (!(eecd & E1000_EECD_GNT)) { 3714 eecd &= ~E1000_EECD_REQ; 3715 ew32(EECD, eecd); 3716 e_dbg("Could not acquire EEPROM grant\n"); 3717 return -E1000_ERR_EEPROM; 3718 } 3719 } 3720 3721 /* Setup EEPROM for Read/Write */ 3722 3723 if (eeprom->type == e1000_eeprom_microwire) { 3724 /* Clear SK and DI */ 3725 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3726 ew32(EECD, eecd); 3727 3728 /* Set CS */ 3729 eecd |= E1000_EECD_CS; 3730 ew32(EECD, eecd); 3731 } else if (eeprom->type == e1000_eeprom_spi) { 3732 /* Clear SK and CS */ 3733 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3734 ew32(EECD, eecd); 3735 E1000_WRITE_FLUSH(); 3736 udelay(1); 3737 } 3738 3739 return E1000_SUCCESS; 3740 } 3741 3742 /** 3743 * e1000_standby_eeprom - Returns EEPROM to a "standby" state 3744 * @hw: Struct containing variables accessed by shared code 3745 */ 3746 static void e1000_standby_eeprom(struct e1000_hw *hw) 3747 { 3748 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3749 u32 eecd; 3750 3751 eecd = er32(EECD); 3752 3753 if (eeprom->type == e1000_eeprom_microwire) { 3754 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3755 ew32(EECD, eecd); 3756 E1000_WRITE_FLUSH(); 3757 udelay(eeprom->delay_usec); 3758 3759 /* Clock high */ 3760 eecd |= E1000_EECD_SK; 3761 ew32(EECD, eecd); 3762 E1000_WRITE_FLUSH(); 3763 udelay(eeprom->delay_usec); 3764 3765 /* Select EEPROM */ 3766 eecd |= E1000_EECD_CS; 3767 ew32(EECD, eecd); 3768 E1000_WRITE_FLUSH(); 3769 udelay(eeprom->delay_usec); 3770 3771 /* Clock low */ 3772 eecd &= ~E1000_EECD_SK; 3773 ew32(EECD, eecd); 3774 E1000_WRITE_FLUSH(); 3775 udelay(eeprom->delay_usec); 3776 } else if (eeprom->type == e1000_eeprom_spi) { 3777 /* Toggle CS to flush commands */ 3778 eecd |= E1000_EECD_CS; 3779 ew32(EECD, eecd); 3780 E1000_WRITE_FLUSH(); 3781 udelay(eeprom->delay_usec); 3782 eecd &= ~E1000_EECD_CS; 3783 ew32(EECD, eecd); 3784 E1000_WRITE_FLUSH(); 3785 udelay(eeprom->delay_usec); 3786 } 3787 } 3788 3789 /** 3790 * e1000_release_eeprom - drop chip select 3791 * @hw: Struct containing variables accessed by shared code 3792 * 3793 * Terminates a command by inverting the EEPROM's chip select pin 3794 */ 3795 static void e1000_release_eeprom(struct e1000_hw *hw) 3796 { 3797 u32 eecd; 3798 3799 eecd = er32(EECD); 3800 3801 if (hw->eeprom.type == e1000_eeprom_spi) { 3802 eecd |= E1000_EECD_CS; /* Pull CS high */ 3803 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3804 3805 ew32(EECD, eecd); 3806 E1000_WRITE_FLUSH(); 3807 3808 udelay(hw->eeprom.delay_usec); 3809 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3810 /* cleanup eeprom */ 3811 3812 /* CS on Microwire is active-high */ 3813 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3814 3815 ew32(EECD, eecd); 3816 3817 /* Rising edge of clock */ 3818 eecd |= E1000_EECD_SK; 3819 ew32(EECD, eecd); 3820 E1000_WRITE_FLUSH(); 3821 udelay(hw->eeprom.delay_usec); 3822 3823 /* Falling edge of clock */ 3824 eecd &= ~E1000_EECD_SK; 3825 ew32(EECD, eecd); 3826 E1000_WRITE_FLUSH(); 3827 udelay(hw->eeprom.delay_usec); 3828 } 3829 3830 /* Stop requesting EEPROM access */ 3831 if (hw->mac_type > e1000_82544) { 3832 eecd &= ~E1000_EECD_REQ; 3833 ew32(EECD, eecd); 3834 } 3835 } 3836 3837 /** 3838 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. 3839 * @hw: Struct containing variables accessed by shared code 3840 */ 3841 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3842 { 3843 u16 retry_count = 0; 3844 u8 spi_stat_reg; 3845 3846 /* Read "Status Register" repeatedly until the LSB is cleared. The 3847 * EEPROM will signal that the command has been completed by clearing 3848 * bit 0 of the internal status register. If it's not cleared within 3849 * 5 milliseconds, then error out. 3850 */ 3851 retry_count = 0; 3852 do { 3853 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3854 hw->eeprom.opcode_bits); 3855 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); 3856 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3857 break; 3858 3859 udelay(5); 3860 retry_count += 5; 3861 3862 e1000_standby_eeprom(hw); 3863 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3864 3865 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3866 * only 0-5mSec on 5V devices) 3867 */ 3868 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3869 e_dbg("SPI EEPROM Status error\n"); 3870 return -E1000_ERR_EEPROM; 3871 } 3872 3873 return E1000_SUCCESS; 3874 } 3875 3876 /** 3877 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. 3878 * @hw: Struct containing variables accessed by shared code 3879 * @offset: offset of word in the EEPROM to read 3880 * @data: word read from the EEPROM 3881 * @words: number of words to read 3882 */ 3883 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3884 { 3885 s32 ret; 3886 spin_lock(&e1000_eeprom_lock); 3887 ret = e1000_do_read_eeprom(hw, offset, words, data); 3888 spin_unlock(&e1000_eeprom_lock); 3889 return ret; 3890 } 3891 3892 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3893 u16 *data) 3894 { 3895 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3896 u32 i = 0; 3897 3898 if (hw->mac_type == e1000_ce4100) { 3899 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, 3900 data); 3901 return E1000_SUCCESS; 3902 } 3903 3904 /* If eeprom is not yet detected, do so now */ 3905 if (eeprom->word_size == 0) 3906 e1000_init_eeprom_params(hw); 3907 3908 /* A check for invalid values: offset too large, too many words, and 3909 * not enough words. 3910 */ 3911 if ((offset >= eeprom->word_size) 3912 || (words > eeprom->word_size - offset) || (words == 0)) { 3913 e_dbg("\"words\" parameter out of bounds. Words = %d," 3914 "size = %d\n", offset, eeprom->word_size); 3915 return -E1000_ERR_EEPROM; 3916 } 3917 3918 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3919 * directly. In this case, we need to acquire the EEPROM so that 3920 * FW or other port software does not interrupt. 3921 */ 3922 /* Prepare the EEPROM for bit-bang reading */ 3923 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3924 return -E1000_ERR_EEPROM; 3925 3926 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3927 * acquired the EEPROM at this point, so any returns should release it 3928 */ 3929 if (eeprom->type == e1000_eeprom_spi) { 3930 u16 word_in; 3931 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3932 3933 if (e1000_spi_eeprom_ready(hw)) { 3934 e1000_release_eeprom(hw); 3935 return -E1000_ERR_EEPROM; 3936 } 3937 3938 e1000_standby_eeprom(hw); 3939 3940 /* Some SPI eeproms use the 8th address bit embedded in the 3941 * opcode 3942 */ 3943 if ((eeprom->address_bits == 8) && (offset >= 128)) 3944 read_opcode |= EEPROM_A8_OPCODE_SPI; 3945 3946 /* Send the READ command (opcode + addr) */ 3947 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3948 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), 3949 eeprom->address_bits); 3950 3951 /* Read the data. The address of the eeprom internally 3952 * increments with each byte (spi) being read, saving on the 3953 * overhead of eeprom setup and tear-down. The address counter 3954 * will roll over if reading beyond the size of the eeprom, thus 3955 * allowing the entire memory to be read starting from any 3956 * offset. 3957 */ 3958 for (i = 0; i < words; i++) { 3959 word_in = e1000_shift_in_ee_bits(hw, 16); 3960 data[i] = (word_in >> 8) | (word_in << 8); 3961 } 3962 } else if (eeprom->type == e1000_eeprom_microwire) { 3963 for (i = 0; i < words; i++) { 3964 /* Send the READ command (opcode + addr) */ 3965 e1000_shift_out_ee_bits(hw, 3966 EEPROM_READ_OPCODE_MICROWIRE, 3967 eeprom->opcode_bits); 3968 e1000_shift_out_ee_bits(hw, (u16) (offset + i), 3969 eeprom->address_bits); 3970 3971 /* Read the data. For microwire, each word requires the 3972 * overhead of eeprom setup and tear-down. 3973 */ 3974 data[i] = e1000_shift_in_ee_bits(hw, 16); 3975 e1000_standby_eeprom(hw); 3976 } 3977 } 3978 3979 /* End this read operation */ 3980 e1000_release_eeprom(hw); 3981 3982 return E1000_SUCCESS; 3983 } 3984 3985 /** 3986 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum 3987 * @hw: Struct containing variables accessed by shared code 3988 * 3989 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3990 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3991 * valid. 3992 */ 3993 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3994 { 3995 u16 checksum = 0; 3996 u16 i, eeprom_data; 3997 3998 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3999 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4000 e_dbg("EEPROM Read Error\n"); 4001 return -E1000_ERR_EEPROM; 4002 } 4003 checksum += eeprom_data; 4004 } 4005 4006 #ifdef CONFIG_PARISC 4007 /* This is a signature and not a checksum on HP c8000 */ 4008 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) 4009 return E1000_SUCCESS; 4010 4011 #endif 4012 if (checksum == (u16) EEPROM_SUM) 4013 return E1000_SUCCESS; 4014 else { 4015 e_dbg("EEPROM Checksum Invalid\n"); 4016 return -E1000_ERR_EEPROM; 4017 } 4018 } 4019 4020 /** 4021 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum 4022 * @hw: Struct containing variables accessed by shared code 4023 * 4024 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 4025 * Writes the difference to word offset 63 of the EEPROM. 4026 */ 4027 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 4028 { 4029 u16 checksum = 0; 4030 u16 i, eeprom_data; 4031 4032 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 4033 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4034 e_dbg("EEPROM Read Error\n"); 4035 return -E1000_ERR_EEPROM; 4036 } 4037 checksum += eeprom_data; 4038 } 4039 checksum = (u16) EEPROM_SUM - checksum; 4040 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4041 e_dbg("EEPROM Write Error\n"); 4042 return -E1000_ERR_EEPROM; 4043 } 4044 return E1000_SUCCESS; 4045 } 4046 4047 /** 4048 * e1000_write_eeprom - write words to the different EEPROM types. 4049 * @hw: Struct containing variables accessed by shared code 4050 * @offset: offset within the EEPROM to be written to 4051 * @words: number of words to write 4052 * @data: 16 bit word to be written to the EEPROM 4053 * 4054 * If e1000_update_eeprom_checksum is not called after this function, the 4055 * EEPROM will most likely contain an invalid checksum. 4056 */ 4057 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4058 { 4059 s32 ret; 4060 spin_lock(&e1000_eeprom_lock); 4061 ret = e1000_do_write_eeprom(hw, offset, words, data); 4062 spin_unlock(&e1000_eeprom_lock); 4063 return ret; 4064 } 4065 4066 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 4067 u16 *data) 4068 { 4069 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4070 s32 status = 0; 4071 4072 if (hw->mac_type == e1000_ce4100) { 4073 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, 4074 data); 4075 return E1000_SUCCESS; 4076 } 4077 4078 /* If eeprom is not yet detected, do so now */ 4079 if (eeprom->word_size == 0) 4080 e1000_init_eeprom_params(hw); 4081 4082 /* A check for invalid values: offset too large, too many words, and 4083 * not enough words. 4084 */ 4085 if ((offset >= eeprom->word_size) 4086 || (words > eeprom->word_size - offset) || (words == 0)) { 4087 e_dbg("\"words\" parameter out of bounds\n"); 4088 return -E1000_ERR_EEPROM; 4089 } 4090 4091 /* Prepare the EEPROM for writing */ 4092 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4093 return -E1000_ERR_EEPROM; 4094 4095 if (eeprom->type == e1000_eeprom_microwire) { 4096 status = e1000_write_eeprom_microwire(hw, offset, words, data); 4097 } else { 4098 status = e1000_write_eeprom_spi(hw, offset, words, data); 4099 msleep(10); 4100 } 4101 4102 /* Done with writing */ 4103 e1000_release_eeprom(hw); 4104 4105 return status; 4106 } 4107 4108 /** 4109 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. 4110 * @hw: Struct containing variables accessed by shared code 4111 * @offset: offset within the EEPROM to be written to 4112 * @words: number of words to write 4113 * @data: pointer to array of 8 bit words to be written to the EEPROM 4114 */ 4115 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 4116 u16 *data) 4117 { 4118 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4119 u16 widx = 0; 4120 4121 while (widx < words) { 4122 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 4123 4124 if (e1000_spi_eeprom_ready(hw)) 4125 return -E1000_ERR_EEPROM; 4126 4127 e1000_standby_eeprom(hw); 4128 4129 /* Send the WRITE ENABLE command (8 bit opcode ) */ 4130 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 4131 eeprom->opcode_bits); 4132 4133 e1000_standby_eeprom(hw); 4134 4135 /* Some SPI eeproms use the 8th address bit embedded in the 4136 * opcode 4137 */ 4138 if ((eeprom->address_bits == 8) && (offset >= 128)) 4139 write_opcode |= EEPROM_A8_OPCODE_SPI; 4140 4141 /* Send the Write command (8-bit opcode + addr) */ 4142 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 4143 4144 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), 4145 eeprom->address_bits); 4146 4147 /* Send the data */ 4148 4149 /* Loop to allow for up to whole page write (32 bytes) of 4150 * eeprom 4151 */ 4152 while (widx < words) { 4153 u16 word_out = data[widx]; 4154 word_out = (word_out >> 8) | (word_out << 8); 4155 e1000_shift_out_ee_bits(hw, word_out, 16); 4156 widx++; 4157 4158 /* Some larger eeprom sizes are capable of a 32-byte 4159 * PAGE WRITE operation, while the smaller eeproms are 4160 * capable of an 8-byte PAGE WRITE operation. Break the 4161 * inner loop to pass new address 4162 */ 4163 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 4164 e1000_standby_eeprom(hw); 4165 break; 4166 } 4167 } 4168 } 4169 4170 return E1000_SUCCESS; 4171 } 4172 4173 /** 4174 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. 4175 * @hw: Struct containing variables accessed by shared code 4176 * @offset: offset within the EEPROM to be written to 4177 * @words: number of words to write 4178 * @data: pointer to array of 8 bit words to be written to the EEPROM 4179 */ 4180 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4181 u16 words, u16 *data) 4182 { 4183 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4184 u32 eecd; 4185 u16 words_written = 0; 4186 u16 i = 0; 4187 4188 /* Send the write enable command to the EEPROM (3-bit opcode plus 4189 * 6/8-bit dummy address beginning with 11). It's less work to include 4190 * the 11 of the dummy address as part of the opcode than it is to shift 4191 * it over the correct number of bits for the address. This puts the 4192 * EEPROM into write/erase mode. 4193 */ 4194 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4195 (u16) (eeprom->opcode_bits + 2)); 4196 4197 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4198 4199 /* Prepare the EEPROM */ 4200 e1000_standby_eeprom(hw); 4201 4202 while (words_written < words) { 4203 /* Send the Write command (3-bit opcode + addr) */ 4204 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4205 eeprom->opcode_bits); 4206 4207 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), 4208 eeprom->address_bits); 4209 4210 /* Send the data */ 4211 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4212 4213 /* Toggle the CS line. This in effect tells the EEPROM to 4214 * execute the previous command. 4215 */ 4216 e1000_standby_eeprom(hw); 4217 4218 /* Read DO repeatedly until it is high (equal to '1'). The 4219 * EEPROM will signal that the command has been completed by 4220 * raising the DO signal. If DO does not go high in 10 4221 * milliseconds, then error out. 4222 */ 4223 for (i = 0; i < 200; i++) { 4224 eecd = er32(EECD); 4225 if (eecd & E1000_EECD_DO) 4226 break; 4227 udelay(50); 4228 } 4229 if (i == 200) { 4230 e_dbg("EEPROM Write did not complete\n"); 4231 return -E1000_ERR_EEPROM; 4232 } 4233 4234 /* Recover from write */ 4235 e1000_standby_eeprom(hw); 4236 4237 words_written++; 4238 } 4239 4240 /* Send the write disable command to the EEPROM (3-bit opcode plus 4241 * 6/8-bit dummy address beginning with 10). It's less work to include 4242 * the 10 of the dummy address as part of the opcode than it is to shift 4243 * it over the correct number of bits for the address. This takes the 4244 * EEPROM out of write/erase mode. 4245 */ 4246 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4247 (u16) (eeprom->opcode_bits + 2)); 4248 4249 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4250 4251 return E1000_SUCCESS; 4252 } 4253 4254 /** 4255 * e1000_read_mac_addr - read the adapters MAC from eeprom 4256 * @hw: Struct containing variables accessed by shared code 4257 * 4258 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4259 * second function of dual function devices 4260 */ 4261 s32 e1000_read_mac_addr(struct e1000_hw *hw) 4262 { 4263 u16 offset; 4264 u16 eeprom_data, i; 4265 4266 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4267 offset = i >> 1; 4268 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4269 e_dbg("EEPROM Read Error\n"); 4270 return -E1000_ERR_EEPROM; 4271 } 4272 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 4273 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); 4274 } 4275 4276 switch (hw->mac_type) { 4277 default: 4278 break; 4279 case e1000_82546: 4280 case e1000_82546_rev_3: 4281 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4282 hw->perm_mac_addr[5] ^= 0x01; 4283 break; 4284 } 4285 4286 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4287 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4288 return E1000_SUCCESS; 4289 } 4290 4291 /** 4292 * e1000_init_rx_addrs - Initializes receive address filters. 4293 * @hw: Struct containing variables accessed by shared code 4294 * 4295 * Places the MAC address in receive address register 0 and clears the rest 4296 * of the receive address registers. Clears the multicast table. Assumes 4297 * the receiver is in reset when the routine is called. 4298 */ 4299 static void e1000_init_rx_addrs(struct e1000_hw *hw) 4300 { 4301 u32 i; 4302 u32 rar_num; 4303 4304 /* Setup the receive address. */ 4305 e_dbg("Programming MAC Address into RAR[0]\n"); 4306 4307 e1000_rar_set(hw, hw->mac_addr, 0); 4308 4309 rar_num = E1000_RAR_ENTRIES; 4310 4311 /* Zero out the other 15 receive addresses. */ 4312 e_dbg("Clearing RAR[1-15]\n"); 4313 for (i = 1; i < rar_num; i++) { 4314 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4315 E1000_WRITE_FLUSH(); 4316 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4317 E1000_WRITE_FLUSH(); 4318 } 4319 } 4320 4321 /** 4322 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table 4323 * @hw: Struct containing variables accessed by shared code 4324 * @mc_addr: the multicast address to hash 4325 */ 4326 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4327 { 4328 u32 hash_value = 0; 4329 4330 /* The portion of the address that is used for the hash table is 4331 * determined by the mc_filter_type setting. 4332 */ 4333 switch (hw->mc_filter_type) { 4334 /* [0] [1] [2] [3] [4] [5] 4335 * 01 AA 00 12 34 56 4336 * LSB MSB 4337 */ 4338 case 0: 4339 /* [47:36] i.e. 0x563 for above example address */ 4340 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 4341 break; 4342 case 1: 4343 /* [46:35] i.e. 0xAC6 for above example address */ 4344 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); 4345 break; 4346 case 2: 4347 /* [45:34] i.e. 0x5D8 for above example address */ 4348 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 4349 break; 4350 case 3: 4351 /* [43:32] i.e. 0x634 for above example address */ 4352 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); 4353 break; 4354 } 4355 4356 hash_value &= 0xFFF; 4357 return hash_value; 4358 } 4359 4360 /** 4361 * e1000_rar_set - Puts an ethernet address into a receive address register. 4362 * @hw: Struct containing variables accessed by shared code 4363 * @addr: Address to put into receive address register 4364 * @index: Receive address register to write 4365 */ 4366 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4367 { 4368 u32 rar_low, rar_high; 4369 4370 /* HW expects these in little endian so we reverse the byte order 4371 * from network order (big endian) to little endian 4372 */ 4373 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 4374 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 4375 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 4376 4377 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4378 * unit hang. 4379 * 4380 * Description: 4381 * If there are any Rx frames queued up or otherwise present in the HW 4382 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4383 * hang. To work around this issue, we have to disable receives and 4384 * flush out all Rx frames before we enable RSS. To do so, we modify we 4385 * redirect all Rx traffic to manageability and then reset the HW. 4386 * This flushes away Rx frames, and (since the redirections to 4387 * manageability persists across resets) keeps new ones from coming in 4388 * while we work. Then, we clear the Address Valid AV bit for all MAC 4389 * addresses and undo the re-direction to manageability. 4390 * Now, frames are coming in again, but the MAC won't accept them, so 4391 * far so good. We now proceed to initialize RSS (if necessary) and 4392 * configure the Rx unit. Last, we re-enable the AV bits and continue 4393 * on our merry way. 4394 */ 4395 switch (hw->mac_type) { 4396 default: 4397 /* Indicate to hardware the Address is Valid. */ 4398 rar_high |= E1000_RAH_AV; 4399 break; 4400 } 4401 4402 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4403 E1000_WRITE_FLUSH(); 4404 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4405 E1000_WRITE_FLUSH(); 4406 } 4407 4408 /** 4409 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. 4410 * @hw: Struct containing variables accessed by shared code 4411 * @offset: Offset in VLAN filer table to write 4412 * @value: Value to write into VLAN filter table 4413 */ 4414 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4415 { 4416 u32 temp; 4417 4418 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4419 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4420 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4421 E1000_WRITE_FLUSH(); 4422 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4423 E1000_WRITE_FLUSH(); 4424 } else { 4425 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4426 E1000_WRITE_FLUSH(); 4427 } 4428 } 4429 4430 /** 4431 * e1000_clear_vfta - Clears the VLAN filer table 4432 * @hw: Struct containing variables accessed by shared code 4433 */ 4434 static void e1000_clear_vfta(struct e1000_hw *hw) 4435 { 4436 u32 offset; 4437 u32 vfta_value = 0; 4438 u32 vfta_offset = 0; 4439 u32 vfta_bit_in_reg = 0; 4440 4441 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4442 /* If the offset we want to clear is the same offset of the 4443 * manageability VLAN ID, then clear all bits except that of the 4444 * manageability unit 4445 */ 4446 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4447 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4448 E1000_WRITE_FLUSH(); 4449 } 4450 } 4451 4452 static s32 e1000_id_led_init(struct e1000_hw *hw) 4453 { 4454 u32 ledctl; 4455 const u32 ledctl_mask = 0x000000FF; 4456 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4457 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4458 u16 eeprom_data, i, temp; 4459 const u16 led_mask = 0x0F; 4460 4461 if (hw->mac_type < e1000_82540) { 4462 /* Nothing to do */ 4463 return E1000_SUCCESS; 4464 } 4465 4466 ledctl = er32(LEDCTL); 4467 hw->ledctl_default = ledctl; 4468 hw->ledctl_mode1 = hw->ledctl_default; 4469 hw->ledctl_mode2 = hw->ledctl_default; 4470 4471 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4472 e_dbg("EEPROM Read Error\n"); 4473 return -E1000_ERR_EEPROM; 4474 } 4475 4476 if ((eeprom_data == ID_LED_RESERVED_0000) || 4477 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4478 eeprom_data = ID_LED_DEFAULT; 4479 } 4480 4481 for (i = 0; i < 4; i++) { 4482 temp = (eeprom_data >> (i << 2)) & led_mask; 4483 switch (temp) { 4484 case ID_LED_ON1_DEF2: 4485 case ID_LED_ON1_ON2: 4486 case ID_LED_ON1_OFF2: 4487 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4488 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4489 break; 4490 case ID_LED_OFF1_DEF2: 4491 case ID_LED_OFF1_ON2: 4492 case ID_LED_OFF1_OFF2: 4493 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4494 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4495 break; 4496 default: 4497 /* Do nothing */ 4498 break; 4499 } 4500 switch (temp) { 4501 case ID_LED_DEF1_ON2: 4502 case ID_LED_ON1_ON2: 4503 case ID_LED_OFF1_ON2: 4504 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4505 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4506 break; 4507 case ID_LED_DEF1_OFF2: 4508 case ID_LED_ON1_OFF2: 4509 case ID_LED_OFF1_OFF2: 4510 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4511 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4512 break; 4513 default: 4514 /* Do nothing */ 4515 break; 4516 } 4517 } 4518 return E1000_SUCCESS; 4519 } 4520 4521 /** 4522 * e1000_setup_led 4523 * @hw: Struct containing variables accessed by shared code 4524 * 4525 * Prepares SW controlable LED for use and saves the current state of the LED. 4526 */ 4527 s32 e1000_setup_led(struct e1000_hw *hw) 4528 { 4529 u32 ledctl; 4530 s32 ret_val = E1000_SUCCESS; 4531 4532 switch (hw->mac_type) { 4533 case e1000_82542_rev2_0: 4534 case e1000_82542_rev2_1: 4535 case e1000_82543: 4536 case e1000_82544: 4537 /* No setup necessary */ 4538 break; 4539 case e1000_82541: 4540 case e1000_82547: 4541 case e1000_82541_rev_2: 4542 case e1000_82547_rev_2: 4543 /* Turn off PHY Smart Power Down (if enabled) */ 4544 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4545 &hw->phy_spd_default); 4546 if (ret_val) 4547 return ret_val; 4548 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4549 (u16) (hw->phy_spd_default & 4550 ~IGP01E1000_GMII_SPD)); 4551 if (ret_val) 4552 return ret_val; 4553 /* Fall Through */ 4554 default: 4555 if (hw->media_type == e1000_media_type_fiber) { 4556 ledctl = er32(LEDCTL); 4557 /* Save current LEDCTL settings */ 4558 hw->ledctl_default = ledctl; 4559 /* Turn off LED0 */ 4560 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4561 E1000_LEDCTL_LED0_BLINK | 4562 E1000_LEDCTL_LED0_MODE_MASK); 4563 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4564 E1000_LEDCTL_LED0_MODE_SHIFT); 4565 ew32(LEDCTL, ledctl); 4566 } else if (hw->media_type == e1000_media_type_copper) 4567 ew32(LEDCTL, hw->ledctl_mode1); 4568 break; 4569 } 4570 4571 return E1000_SUCCESS; 4572 } 4573 4574 /** 4575 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. 4576 * @hw: Struct containing variables accessed by shared code 4577 */ 4578 s32 e1000_cleanup_led(struct e1000_hw *hw) 4579 { 4580 s32 ret_val = E1000_SUCCESS; 4581 4582 switch (hw->mac_type) { 4583 case e1000_82542_rev2_0: 4584 case e1000_82542_rev2_1: 4585 case e1000_82543: 4586 case e1000_82544: 4587 /* No cleanup necessary */ 4588 break; 4589 case e1000_82541: 4590 case e1000_82547: 4591 case e1000_82541_rev_2: 4592 case e1000_82547_rev_2: 4593 /* Turn on PHY Smart Power Down (if previously enabled) */ 4594 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4595 hw->phy_spd_default); 4596 if (ret_val) 4597 return ret_val; 4598 /* Fall Through */ 4599 default: 4600 /* Restore LEDCTL settings */ 4601 ew32(LEDCTL, hw->ledctl_default); 4602 break; 4603 } 4604 4605 return E1000_SUCCESS; 4606 } 4607 4608 /** 4609 * e1000_led_on - Turns on the software controllable LED 4610 * @hw: Struct containing variables accessed by shared code 4611 */ 4612 s32 e1000_led_on(struct e1000_hw *hw) 4613 { 4614 u32 ctrl = er32(CTRL); 4615 4616 switch (hw->mac_type) { 4617 case e1000_82542_rev2_0: 4618 case e1000_82542_rev2_1: 4619 case e1000_82543: 4620 /* Set SW Defineable Pin 0 to turn on the LED */ 4621 ctrl |= E1000_CTRL_SWDPIN0; 4622 ctrl |= E1000_CTRL_SWDPIO0; 4623 break; 4624 case e1000_82544: 4625 if (hw->media_type == e1000_media_type_fiber) { 4626 /* Set SW Defineable Pin 0 to turn on the LED */ 4627 ctrl |= E1000_CTRL_SWDPIN0; 4628 ctrl |= E1000_CTRL_SWDPIO0; 4629 } else { 4630 /* Clear SW Defineable Pin 0 to turn on the LED */ 4631 ctrl &= ~E1000_CTRL_SWDPIN0; 4632 ctrl |= E1000_CTRL_SWDPIO0; 4633 } 4634 break; 4635 default: 4636 if (hw->media_type == e1000_media_type_fiber) { 4637 /* Clear SW Defineable Pin 0 to turn on the LED */ 4638 ctrl &= ~E1000_CTRL_SWDPIN0; 4639 ctrl |= E1000_CTRL_SWDPIO0; 4640 } else if (hw->media_type == e1000_media_type_copper) { 4641 ew32(LEDCTL, hw->ledctl_mode2); 4642 return E1000_SUCCESS; 4643 } 4644 break; 4645 } 4646 4647 ew32(CTRL, ctrl); 4648 4649 return E1000_SUCCESS; 4650 } 4651 4652 /** 4653 * e1000_led_off - Turns off the software controllable LED 4654 * @hw: Struct containing variables accessed by shared code 4655 */ 4656 s32 e1000_led_off(struct e1000_hw *hw) 4657 { 4658 u32 ctrl = er32(CTRL); 4659 4660 switch (hw->mac_type) { 4661 case e1000_82542_rev2_0: 4662 case e1000_82542_rev2_1: 4663 case e1000_82543: 4664 /* Clear SW Defineable Pin 0 to turn off the LED */ 4665 ctrl &= ~E1000_CTRL_SWDPIN0; 4666 ctrl |= E1000_CTRL_SWDPIO0; 4667 break; 4668 case e1000_82544: 4669 if (hw->media_type == e1000_media_type_fiber) { 4670 /* Clear SW Defineable Pin 0 to turn off the LED */ 4671 ctrl &= ~E1000_CTRL_SWDPIN0; 4672 ctrl |= E1000_CTRL_SWDPIO0; 4673 } else { 4674 /* Set SW Defineable Pin 0 to turn off the LED */ 4675 ctrl |= E1000_CTRL_SWDPIN0; 4676 ctrl |= E1000_CTRL_SWDPIO0; 4677 } 4678 break; 4679 default: 4680 if (hw->media_type == e1000_media_type_fiber) { 4681 /* Set SW Defineable Pin 0 to turn off the LED */ 4682 ctrl |= E1000_CTRL_SWDPIN0; 4683 ctrl |= E1000_CTRL_SWDPIO0; 4684 } else if (hw->media_type == e1000_media_type_copper) { 4685 ew32(LEDCTL, hw->ledctl_mode1); 4686 return E1000_SUCCESS; 4687 } 4688 break; 4689 } 4690 4691 ew32(CTRL, ctrl); 4692 4693 return E1000_SUCCESS; 4694 } 4695 4696 /** 4697 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. 4698 * @hw: Struct containing variables accessed by shared code 4699 */ 4700 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4701 { 4702 volatile u32 temp; 4703 4704 temp = er32(CRCERRS); 4705 temp = er32(SYMERRS); 4706 temp = er32(MPC); 4707 temp = er32(SCC); 4708 temp = er32(ECOL); 4709 temp = er32(MCC); 4710 temp = er32(LATECOL); 4711 temp = er32(COLC); 4712 temp = er32(DC); 4713 temp = er32(SEC); 4714 temp = er32(RLEC); 4715 temp = er32(XONRXC); 4716 temp = er32(XONTXC); 4717 temp = er32(XOFFRXC); 4718 temp = er32(XOFFTXC); 4719 temp = er32(FCRUC); 4720 4721 temp = er32(PRC64); 4722 temp = er32(PRC127); 4723 temp = er32(PRC255); 4724 temp = er32(PRC511); 4725 temp = er32(PRC1023); 4726 temp = er32(PRC1522); 4727 4728 temp = er32(GPRC); 4729 temp = er32(BPRC); 4730 temp = er32(MPRC); 4731 temp = er32(GPTC); 4732 temp = er32(GORCL); 4733 temp = er32(GORCH); 4734 temp = er32(GOTCL); 4735 temp = er32(GOTCH); 4736 temp = er32(RNBC); 4737 temp = er32(RUC); 4738 temp = er32(RFC); 4739 temp = er32(ROC); 4740 temp = er32(RJC); 4741 temp = er32(TORL); 4742 temp = er32(TORH); 4743 temp = er32(TOTL); 4744 temp = er32(TOTH); 4745 temp = er32(TPR); 4746 temp = er32(TPT); 4747 4748 temp = er32(PTC64); 4749 temp = er32(PTC127); 4750 temp = er32(PTC255); 4751 temp = er32(PTC511); 4752 temp = er32(PTC1023); 4753 temp = er32(PTC1522); 4754 4755 temp = er32(MPTC); 4756 temp = er32(BPTC); 4757 4758 if (hw->mac_type < e1000_82543) 4759 return; 4760 4761 temp = er32(ALGNERRC); 4762 temp = er32(RXERRC); 4763 temp = er32(TNCRS); 4764 temp = er32(CEXTERR); 4765 temp = er32(TSCTC); 4766 temp = er32(TSCTFC); 4767 4768 if (hw->mac_type <= e1000_82544) 4769 return; 4770 4771 temp = er32(MGTPRC); 4772 temp = er32(MGTPDC); 4773 temp = er32(MGTPTC); 4774 } 4775 4776 /** 4777 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. 4778 * @hw: Struct containing variables accessed by shared code 4779 * 4780 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4781 * hw->ifs_params_forced to true. However, you must initialize hw-> 4782 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4783 * before calling this function. 4784 */ 4785 void e1000_reset_adaptive(struct e1000_hw *hw) 4786 { 4787 if (hw->adaptive_ifs) { 4788 if (!hw->ifs_params_forced) { 4789 hw->current_ifs_val = 0; 4790 hw->ifs_min_val = IFS_MIN; 4791 hw->ifs_max_val = IFS_MAX; 4792 hw->ifs_step_size = IFS_STEP; 4793 hw->ifs_ratio = IFS_RATIO; 4794 } 4795 hw->in_ifs_mode = false; 4796 ew32(AIT, 0); 4797 } else { 4798 e_dbg("Not in Adaptive IFS mode!\n"); 4799 } 4800 } 4801 4802 /** 4803 * e1000_update_adaptive - update adaptive IFS 4804 * @hw: Struct containing variables accessed by shared code 4805 * @tx_packets: Number of transmits since last callback 4806 * @total_collisions: Number of collisions since last callback 4807 * 4808 * Called during the callback/watchdog routine to update IFS value based on 4809 * the ratio of transmits to collisions. 4810 */ 4811 void e1000_update_adaptive(struct e1000_hw *hw) 4812 { 4813 if (hw->adaptive_ifs) { 4814 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { 4815 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4816 hw->in_ifs_mode = true; 4817 if (hw->current_ifs_val < hw->ifs_max_val) { 4818 if (hw->current_ifs_val == 0) 4819 hw->current_ifs_val = 4820 hw->ifs_min_val; 4821 else 4822 hw->current_ifs_val += 4823 hw->ifs_step_size; 4824 ew32(AIT, hw->current_ifs_val); 4825 } 4826 } 4827 } else { 4828 if (hw->in_ifs_mode 4829 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4830 hw->current_ifs_val = 0; 4831 hw->in_ifs_mode = false; 4832 ew32(AIT, 0); 4833 } 4834 } 4835 } else { 4836 e_dbg("Not in Adaptive IFS mode!\n"); 4837 } 4838 } 4839 4840 /** 4841 * e1000_tbi_adjust_stats 4842 * @hw: Struct containing variables accessed by shared code 4843 * @frame_len: The length of the frame in question 4844 * @mac_addr: The Ethernet destination address of the frame in question 4845 * 4846 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4847 */ 4848 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, 4849 u32 frame_len, u8 *mac_addr) 4850 { 4851 u64 carry_bit; 4852 4853 /* First adjust the frame length. */ 4854 frame_len--; 4855 /* We need to adjust the statistics counters, since the hardware 4856 * counters overcount this packet as a CRC error and undercount 4857 * the packet as a good packet 4858 */ 4859 /* This packet should not be counted as a CRC error. */ 4860 stats->crcerrs--; 4861 /* This packet does count as a Good Packet Received. */ 4862 stats->gprc++; 4863 4864 /* Adjust the Good Octets received counters */ 4865 carry_bit = 0x80000000 & stats->gorcl; 4866 stats->gorcl += frame_len; 4867 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4868 * Received Count) was one before the addition, 4869 * AND it is zero after, then we lost the carry out, 4870 * need to add one to Gorch (Good Octets Received Count High). 4871 * This could be simplified if all environments supported 4872 * 64-bit integers. 4873 */ 4874 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4875 stats->gorch++; 4876 /* Is this a broadcast or multicast? Check broadcast first, 4877 * since the test for a multicast frame will test positive on 4878 * a broadcast frame. 4879 */ 4880 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) 4881 /* Broadcast packet */ 4882 stats->bprc++; 4883 else if (*mac_addr & 0x01) 4884 /* Multicast packet */ 4885 stats->mprc++; 4886 4887 if (frame_len == hw->max_frame_size) { 4888 /* In this case, the hardware has overcounted the number of 4889 * oversize frames. 4890 */ 4891 if (stats->roc > 0) 4892 stats->roc--; 4893 } 4894 4895 /* Adjust the bin counters when the extra byte put the frame in the 4896 * wrong bin. Remember that the frame_len was adjusted above. 4897 */ 4898 if (frame_len == 64) { 4899 stats->prc64++; 4900 stats->prc127--; 4901 } else if (frame_len == 127) { 4902 stats->prc127++; 4903 stats->prc255--; 4904 } else if (frame_len == 255) { 4905 stats->prc255++; 4906 stats->prc511--; 4907 } else if (frame_len == 511) { 4908 stats->prc511++; 4909 stats->prc1023--; 4910 } else if (frame_len == 1023) { 4911 stats->prc1023++; 4912 stats->prc1522--; 4913 } else if (frame_len == 1522) { 4914 stats->prc1522++; 4915 } 4916 } 4917 4918 /** 4919 * e1000_get_bus_info 4920 * @hw: Struct containing variables accessed by shared code 4921 * 4922 * Gets the current PCI bus type, speed, and width of the hardware 4923 */ 4924 void e1000_get_bus_info(struct e1000_hw *hw) 4925 { 4926 u32 status; 4927 4928 switch (hw->mac_type) { 4929 case e1000_82542_rev2_0: 4930 case e1000_82542_rev2_1: 4931 hw->bus_type = e1000_bus_type_pci; 4932 hw->bus_speed = e1000_bus_speed_unknown; 4933 hw->bus_width = e1000_bus_width_unknown; 4934 break; 4935 default: 4936 status = er32(STATUS); 4937 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4938 e1000_bus_type_pcix : e1000_bus_type_pci; 4939 4940 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4941 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4942 e1000_bus_speed_66 : e1000_bus_speed_120; 4943 } else if (hw->bus_type == e1000_bus_type_pci) { 4944 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4945 e1000_bus_speed_66 : e1000_bus_speed_33; 4946 } else { 4947 switch (status & E1000_STATUS_PCIX_SPEED) { 4948 case E1000_STATUS_PCIX_SPEED_66: 4949 hw->bus_speed = e1000_bus_speed_66; 4950 break; 4951 case E1000_STATUS_PCIX_SPEED_100: 4952 hw->bus_speed = e1000_bus_speed_100; 4953 break; 4954 case E1000_STATUS_PCIX_SPEED_133: 4955 hw->bus_speed = e1000_bus_speed_133; 4956 break; 4957 default: 4958 hw->bus_speed = e1000_bus_speed_reserved; 4959 break; 4960 } 4961 } 4962 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4963 e1000_bus_width_64 : e1000_bus_width_32; 4964 break; 4965 } 4966 } 4967 4968 /** 4969 * e1000_write_reg_io 4970 * @hw: Struct containing variables accessed by shared code 4971 * @offset: offset to write to 4972 * @value: value to write 4973 * 4974 * Writes a value to one of the devices registers using port I/O (as opposed to 4975 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4976 */ 4977 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4978 { 4979 unsigned long io_addr = hw->io_base; 4980 unsigned long io_data = hw->io_base + 4; 4981 4982 e1000_io_write(hw, io_addr, offset); 4983 e1000_io_write(hw, io_data, value); 4984 } 4985 4986 /** 4987 * e1000_get_cable_length - Estimates the cable length. 4988 * @hw: Struct containing variables accessed by shared code 4989 * @min_length: The estimated minimum length 4990 * @max_length: The estimated maximum length 4991 * 4992 * returns: - E1000_ERR_XXX 4993 * E1000_SUCCESS 4994 * 4995 * This function always returns a ranged length (minimum & maximum). 4996 * So for M88 phy's, this function interprets the one value returned from the 4997 * register to the minimum and maximum range. 4998 * For IGP phy's, the function calculates the range by the AGC registers. 4999 */ 5000 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 5001 u16 *max_length) 5002 { 5003 s32 ret_val; 5004 u16 agc_value = 0; 5005 u16 i, phy_data; 5006 u16 cable_length; 5007 5008 *min_length = *max_length = 0; 5009 5010 /* Use old method for Phy older than IGP */ 5011 if (hw->phy_type == e1000_phy_m88) { 5012 5013 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5014 &phy_data); 5015 if (ret_val) 5016 return ret_val; 5017 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 5018 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 5019 5020 /* Convert the enum value to ranged values */ 5021 switch (cable_length) { 5022 case e1000_cable_length_50: 5023 *min_length = 0; 5024 *max_length = e1000_igp_cable_length_50; 5025 break; 5026 case e1000_cable_length_50_80: 5027 *min_length = e1000_igp_cable_length_50; 5028 *max_length = e1000_igp_cable_length_80; 5029 break; 5030 case e1000_cable_length_80_110: 5031 *min_length = e1000_igp_cable_length_80; 5032 *max_length = e1000_igp_cable_length_110; 5033 break; 5034 case e1000_cable_length_110_140: 5035 *min_length = e1000_igp_cable_length_110; 5036 *max_length = e1000_igp_cable_length_140; 5037 break; 5038 case e1000_cable_length_140: 5039 *min_length = e1000_igp_cable_length_140; 5040 *max_length = e1000_igp_cable_length_170; 5041 break; 5042 default: 5043 return -E1000_ERR_PHY; 5044 break; 5045 } 5046 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 5047 u16 cur_agc_value; 5048 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 5049 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5050 IGP01E1000_PHY_AGC_A, 5051 IGP01E1000_PHY_AGC_B, 5052 IGP01E1000_PHY_AGC_C, 5053 IGP01E1000_PHY_AGC_D 5054 }; 5055 /* Read the AGC registers for all channels */ 5056 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5057 5058 ret_val = 5059 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 5060 if (ret_val) 5061 return ret_val; 5062 5063 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 5064 5065 /* Value bound check. */ 5066 if ((cur_agc_value >= 5067 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) 5068 || (cur_agc_value == 0)) 5069 return -E1000_ERR_PHY; 5070 5071 agc_value += cur_agc_value; 5072 5073 /* Update minimal AGC value. */ 5074 if (min_agc_value > cur_agc_value) 5075 min_agc_value = cur_agc_value; 5076 } 5077 5078 /* Remove the minimal AGC result for length < 50m */ 5079 if (agc_value < 5080 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 5081 agc_value -= min_agc_value; 5082 5083 /* Get the average length of the remaining 3 channels */ 5084 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 5085 } else { 5086 /* Get the average length of all the 4 channels. */ 5087 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 5088 } 5089 5090 /* Set the range of the calculated length. */ 5091 *min_length = ((e1000_igp_cable_length_table[agc_value] - 5092 IGP01E1000_AGC_RANGE) > 0) ? 5093 (e1000_igp_cable_length_table[agc_value] - 5094 IGP01E1000_AGC_RANGE) : 0; 5095 *max_length = e1000_igp_cable_length_table[agc_value] + 5096 IGP01E1000_AGC_RANGE; 5097 } 5098 5099 return E1000_SUCCESS; 5100 } 5101 5102 /** 5103 * e1000_check_polarity - Check the cable polarity 5104 * @hw: Struct containing variables accessed by shared code 5105 * @polarity: output parameter : 0 - Polarity is not reversed 5106 * 1 - Polarity is reversed. 5107 * 5108 * returns: - E1000_ERR_XXX 5109 * E1000_SUCCESS 5110 * 5111 * For phy's older than IGP, this function simply reads the polarity bit in the 5112 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 5113 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 5114 * return 0. If the link speed is 1000 Mbps the polarity status is in the 5115 * IGP01E1000_PHY_PCS_INIT_REG. 5116 */ 5117 static s32 e1000_check_polarity(struct e1000_hw *hw, 5118 e1000_rev_polarity *polarity) 5119 { 5120 s32 ret_val; 5121 u16 phy_data; 5122 5123 if (hw->phy_type == e1000_phy_m88) { 5124 /* return the Polarity bit in the Status register. */ 5125 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5126 &phy_data); 5127 if (ret_val) 5128 return ret_val; 5129 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5130 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5131 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5132 5133 } else if (hw->phy_type == e1000_phy_igp) { 5134 /* Read the Status register to check the speed */ 5135 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5136 &phy_data); 5137 if (ret_val) 5138 return ret_val; 5139 5140 /* If speed is 1000 Mbps, must read the 5141 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status 5142 */ 5143 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 5144 IGP01E1000_PSSR_SPEED_1000MBPS) { 5145 5146 /* Read the GIG initialization PCS register (0x00B4) */ 5147 ret_val = 5148 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 5149 &phy_data); 5150 if (ret_val) 5151 return ret_val; 5152 5153 /* Check the polarity bits */ 5154 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5155 e1000_rev_polarity_reversed : 5156 e1000_rev_polarity_normal; 5157 } else { 5158 /* For 10 Mbps, read the polarity bit in the status 5159 * register. (for 100 Mbps this bit is always 0) 5160 */ 5161 *polarity = 5162 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5163 e1000_rev_polarity_reversed : 5164 e1000_rev_polarity_normal; 5165 } 5166 } 5167 return E1000_SUCCESS; 5168 } 5169 5170 /** 5171 * e1000_check_downshift - Check if Downshift occurred 5172 * @hw: Struct containing variables accessed by shared code 5173 * @downshift: output parameter : 0 - No Downshift occurred. 5174 * 1 - Downshift occurred. 5175 * 5176 * returns: - E1000_ERR_XXX 5177 * E1000_SUCCESS 5178 * 5179 * For phy's older than IGP, this function reads the Downshift bit in the Phy 5180 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5181 * Link Health register. In IGP this bit is latched high, so the driver must 5182 * read it immediately after link is established. 5183 */ 5184 static s32 e1000_check_downshift(struct e1000_hw *hw) 5185 { 5186 s32 ret_val; 5187 u16 phy_data; 5188 5189 if (hw->phy_type == e1000_phy_igp) { 5190 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5191 &phy_data); 5192 if (ret_val) 5193 return ret_val; 5194 5195 hw->speed_downgraded = 5196 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5197 } else if (hw->phy_type == e1000_phy_m88) { 5198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5199 &phy_data); 5200 if (ret_val) 5201 return ret_val; 5202 5203 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5204 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5205 } 5206 5207 return E1000_SUCCESS; 5208 } 5209 5210 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5211 IGP01E1000_PHY_AGC_PARAM_A, 5212 IGP01E1000_PHY_AGC_PARAM_B, 5213 IGP01E1000_PHY_AGC_PARAM_C, 5214 IGP01E1000_PHY_AGC_PARAM_D 5215 }; 5216 5217 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) 5218 { 5219 u16 min_length, max_length; 5220 u16 phy_data, i; 5221 s32 ret_val; 5222 5223 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 5224 if (ret_val) 5225 return ret_val; 5226 5227 if (hw->dsp_config_state != e1000_dsp_config_enabled) 5228 return 0; 5229 5230 if (min_length >= e1000_igp_cable_length_50) { 5231 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5232 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 5233 &phy_data); 5234 if (ret_val) 5235 return ret_val; 5236 5237 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5238 5239 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 5240 phy_data); 5241 if (ret_val) 5242 return ret_val; 5243 } 5244 hw->dsp_config_state = e1000_dsp_config_activated; 5245 } else { 5246 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5247 u32 idle_errs = 0; 5248 5249 /* clear previous idle error counts */ 5250 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 5251 if (ret_val) 5252 return ret_val; 5253 5254 for (i = 0; i < ffe_idle_err_timeout; i++) { 5255 udelay(1000); 5256 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5257 &phy_data); 5258 if (ret_val) 5259 return ret_val; 5260 5261 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 5262 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 5263 hw->ffe_config_state = e1000_ffe_config_active; 5264 5265 ret_val = e1000_write_phy_reg(hw, 5266 IGP01E1000_PHY_DSP_FFE, 5267 IGP01E1000_PHY_DSP_FFE_CM_CP); 5268 if (ret_val) 5269 return ret_val; 5270 break; 5271 } 5272 5273 if (idle_errs) 5274 ffe_idle_err_timeout = 5275 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5276 } 5277 } 5278 5279 return 0; 5280 } 5281 5282 /** 5283 * e1000_config_dsp_after_link_change 5284 * @hw: Struct containing variables accessed by shared code 5285 * @link_up: was link up at the time this was called 5286 * 5287 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5288 * E1000_SUCCESS at any other case. 5289 * 5290 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5291 * gigabit link is achieved to improve link quality. 5292 */ 5293 5294 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5295 { 5296 s32 ret_val; 5297 u16 phy_data, phy_saved_data, speed, duplex, i; 5298 5299 if (hw->phy_type != e1000_phy_igp) 5300 return E1000_SUCCESS; 5301 5302 if (link_up) { 5303 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5304 if (ret_val) { 5305 e_dbg("Error getting link speed and duplex\n"); 5306 return ret_val; 5307 } 5308 5309 if (speed == SPEED_1000) { 5310 ret_val = e1000_1000Mb_check_cable_length(hw); 5311 if (ret_val) 5312 return ret_val; 5313 } 5314 } else { 5315 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5316 /* Save off the current value of register 0x2F5B to be 5317 * restored at the end of the routines. 5318 */ 5319 ret_val = 5320 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5321 5322 if (ret_val) 5323 return ret_val; 5324 5325 /* Disable the PHY transmitter */ 5326 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5327 5328 if (ret_val) 5329 return ret_val; 5330 5331 msleep(20); 5332 5333 ret_val = e1000_write_phy_reg(hw, 0x0000, 5334 IGP01E1000_IEEE_FORCE_GIGA); 5335 if (ret_val) 5336 return ret_val; 5337 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5338 ret_val = 5339 e1000_read_phy_reg(hw, dsp_reg_array[i], 5340 &phy_data); 5341 if (ret_val) 5342 return ret_val; 5343 5344 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5345 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5346 5347 ret_val = 5348 e1000_write_phy_reg(hw, dsp_reg_array[i], 5349 phy_data); 5350 if (ret_val) 5351 return ret_val; 5352 } 5353 5354 ret_val = e1000_write_phy_reg(hw, 0x0000, 5355 IGP01E1000_IEEE_RESTART_AUTONEG); 5356 if (ret_val) 5357 return ret_val; 5358 5359 msleep(20); 5360 5361 /* Now enable the transmitter */ 5362 ret_val = 5363 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5364 5365 if (ret_val) 5366 return ret_val; 5367 5368 hw->dsp_config_state = e1000_dsp_config_enabled; 5369 } 5370 5371 if (hw->ffe_config_state == e1000_ffe_config_active) { 5372 /* Save off the current value of register 0x2F5B to be 5373 * restored at the end of the routines. 5374 */ 5375 ret_val = 5376 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5377 5378 if (ret_val) 5379 return ret_val; 5380 5381 /* Disable the PHY transmitter */ 5382 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5383 5384 if (ret_val) 5385 return ret_val; 5386 5387 msleep(20); 5388 5389 ret_val = e1000_write_phy_reg(hw, 0x0000, 5390 IGP01E1000_IEEE_FORCE_GIGA); 5391 if (ret_val) 5392 return ret_val; 5393 ret_val = 5394 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5395 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5396 if (ret_val) 5397 return ret_val; 5398 5399 ret_val = e1000_write_phy_reg(hw, 0x0000, 5400 IGP01E1000_IEEE_RESTART_AUTONEG); 5401 if (ret_val) 5402 return ret_val; 5403 5404 msleep(20); 5405 5406 /* Now enable the transmitter */ 5407 ret_val = 5408 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5409 5410 if (ret_val) 5411 return ret_val; 5412 5413 hw->ffe_config_state = e1000_ffe_config_enabled; 5414 } 5415 } 5416 return E1000_SUCCESS; 5417 } 5418 5419 /** 5420 * e1000_set_phy_mode - Set PHY to class A mode 5421 * @hw: Struct containing variables accessed by shared code 5422 * 5423 * Assumes the following operations will follow to enable the new class mode. 5424 * 1. Do a PHY soft reset 5425 * 2. Restart auto-negotiation or force link. 5426 */ 5427 static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5428 { 5429 s32 ret_val; 5430 u16 eeprom_data; 5431 5432 if ((hw->mac_type == e1000_82545_rev_3) && 5433 (hw->media_type == e1000_media_type_copper)) { 5434 ret_val = 5435 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 5436 &eeprom_data); 5437 if (ret_val) { 5438 return ret_val; 5439 } 5440 5441 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5442 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5443 ret_val = 5444 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 5445 0x000B); 5446 if (ret_val) 5447 return ret_val; 5448 ret_val = 5449 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 5450 0x8104); 5451 if (ret_val) 5452 return ret_val; 5453 5454 hw->phy_reset_disable = false; 5455 } 5456 } 5457 5458 return E1000_SUCCESS; 5459 } 5460 5461 /** 5462 * e1000_set_d3_lplu_state - set d3 link power state 5463 * @hw: Struct containing variables accessed by shared code 5464 * @active: true to enable lplu false to disable lplu. 5465 * 5466 * This function sets the lplu state according to the active flag. When 5467 * activating lplu this function also disables smart speed and vise versa. 5468 * lplu will not be activated unless the device autonegotiation advertisement 5469 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5470 * 5471 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5472 * E1000_SUCCESS at any other case. 5473 */ 5474 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5475 { 5476 s32 ret_val; 5477 u16 phy_data; 5478 5479 if (hw->phy_type != e1000_phy_igp) 5480 return E1000_SUCCESS; 5481 5482 /* During driver activity LPLU should not be used or it will attain link 5483 * from the lowest speeds starting from 10Mbps. The capability is used 5484 * for Dx transitions and states 5485 */ 5486 if (hw->mac_type == e1000_82541_rev_2 5487 || hw->mac_type == e1000_82547_rev_2) { 5488 ret_val = 5489 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5490 if (ret_val) 5491 return ret_val; 5492 } 5493 5494 if (!active) { 5495 if (hw->mac_type == e1000_82541_rev_2 || 5496 hw->mac_type == e1000_82547_rev_2) { 5497 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5498 ret_val = 5499 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5500 phy_data); 5501 if (ret_val) 5502 return ret_val; 5503 } 5504 5505 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 5506 * during Dx states where the power conservation is most 5507 * important. During driver activity we should enable 5508 * SmartSpeed, so performance is maintained. 5509 */ 5510 if (hw->smart_speed == e1000_smart_speed_on) { 5511 ret_val = 5512 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5513 &phy_data); 5514 if (ret_val) 5515 return ret_val; 5516 5517 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5518 ret_val = 5519 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5520 phy_data); 5521 if (ret_val) 5522 return ret_val; 5523 } else if (hw->smart_speed == e1000_smart_speed_off) { 5524 ret_val = 5525 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5526 &phy_data); 5527 if (ret_val) 5528 return ret_val; 5529 5530 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5531 ret_val = 5532 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5533 phy_data); 5534 if (ret_val) 5535 return ret_val; 5536 } 5537 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 5538 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) 5539 || (hw->autoneg_advertised == 5540 AUTONEG_ADVERTISE_10_100_ALL)) { 5541 5542 if (hw->mac_type == e1000_82541_rev_2 || 5543 hw->mac_type == e1000_82547_rev_2) { 5544 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5545 ret_val = 5546 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5547 phy_data); 5548 if (ret_val) 5549 return ret_val; 5550 } 5551 5552 /* When LPLU is enabled we should disable SmartSpeed */ 5553 ret_val = 5554 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5555 &phy_data); 5556 if (ret_val) 5557 return ret_val; 5558 5559 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5560 ret_val = 5561 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5562 phy_data); 5563 if (ret_val) 5564 return ret_val; 5565 5566 } 5567 return E1000_SUCCESS; 5568 } 5569 5570 /** 5571 * e1000_set_vco_speed 5572 * @hw: Struct containing variables accessed by shared code 5573 * 5574 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5575 */ 5576 static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5577 { 5578 s32 ret_val; 5579 u16 default_page = 0; 5580 u16 phy_data; 5581 5582 switch (hw->mac_type) { 5583 case e1000_82545_rev_3: 5584 case e1000_82546_rev_3: 5585 break; 5586 default: 5587 return E1000_SUCCESS; 5588 } 5589 5590 /* Set PHY register 30, page 5, bit 8 to 0 */ 5591 5592 ret_val = 5593 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5594 if (ret_val) 5595 return ret_val; 5596 5597 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5598 if (ret_val) 5599 return ret_val; 5600 5601 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5602 if (ret_val) 5603 return ret_val; 5604 5605 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5606 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5607 if (ret_val) 5608 return ret_val; 5609 5610 /* Set PHY register 30, page 4, bit 11 to 1 */ 5611 5612 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5613 if (ret_val) 5614 return ret_val; 5615 5616 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5617 if (ret_val) 5618 return ret_val; 5619 5620 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5621 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5622 if (ret_val) 5623 return ret_val; 5624 5625 ret_val = 5626 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5627 if (ret_val) 5628 return ret_val; 5629 5630 return E1000_SUCCESS; 5631 } 5632 5633 5634 /** 5635 * e1000_enable_mng_pass_thru - check for bmc pass through 5636 * @hw: Struct containing variables accessed by shared code 5637 * 5638 * Verifies the hardware needs to allow ARPs to be processed by the host 5639 * returns: - true/false 5640 */ 5641 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5642 { 5643 u32 manc; 5644 5645 if (hw->asf_firmware_present) { 5646 manc = er32(MANC); 5647 5648 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5649 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5650 return false; 5651 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5652 return true; 5653 } 5654 return false; 5655 } 5656 5657 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5658 { 5659 s32 ret_val; 5660 u16 mii_status_reg; 5661 u16 i; 5662 5663 /* Polarity reversal workaround for forced 10F/10H links. */ 5664 5665 /* Disable the transmitter on the PHY */ 5666 5667 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5668 if (ret_val) 5669 return ret_val; 5670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5671 if (ret_val) 5672 return ret_val; 5673 5674 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5675 if (ret_val) 5676 return ret_val; 5677 5678 /* This loop will early-out if the NO link condition has been met. */ 5679 for (i = PHY_FORCE_TIME; i > 0; i--) { 5680 /* Read the MII Status Register and wait for Link Status bit 5681 * to be clear. 5682 */ 5683 5684 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5685 if (ret_val) 5686 return ret_val; 5687 5688 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5689 if (ret_val) 5690 return ret_val; 5691 5692 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 5693 break; 5694 msleep(100); 5695 } 5696 5697 /* Recommended delay time after link has been lost */ 5698 msleep(1000); 5699 5700 /* Now we will re-enable th transmitter on the PHY */ 5701 5702 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5703 if (ret_val) 5704 return ret_val; 5705 msleep(50); 5706 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5707 if (ret_val) 5708 return ret_val; 5709 msleep(50); 5710 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5711 if (ret_val) 5712 return ret_val; 5713 msleep(50); 5714 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5715 if (ret_val) 5716 return ret_val; 5717 5718 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5719 if (ret_val) 5720 return ret_val; 5721 5722 /* This loop will early-out if the link condition has been met. */ 5723 for (i = PHY_FORCE_TIME; i > 0; i--) { 5724 /* Read the MII Status Register and wait for Link Status bit 5725 * to be set. 5726 */ 5727 5728 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5729 if (ret_val) 5730 return ret_val; 5731 5732 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5733 if (ret_val) 5734 return ret_val; 5735 5736 if (mii_status_reg & MII_SR_LINK_STATUS) 5737 break; 5738 msleep(100); 5739 } 5740 return E1000_SUCCESS; 5741 } 5742 5743 /** 5744 * e1000_get_auto_rd_done 5745 * @hw: Struct containing variables accessed by shared code 5746 * 5747 * Check for EEPROM Auto Read bit done. 5748 * returns: - E1000_ERR_RESET if fail to reset MAC 5749 * E1000_SUCCESS at any other case. 5750 */ 5751 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5752 { 5753 msleep(5); 5754 return E1000_SUCCESS; 5755 } 5756 5757 /** 5758 * e1000_get_phy_cfg_done 5759 * @hw: Struct containing variables accessed by shared code 5760 * 5761 * Checks if the PHY configuration is done 5762 * returns: - E1000_ERR_RESET if fail to reset MAC 5763 * E1000_SUCCESS at any other case. 5764 */ 5765 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5766 { 5767 msleep(10); 5768 return E1000_SUCCESS; 5769 } 5770