xref: /openbmc/linux/drivers/net/ethernet/ibm/emac/mal.h (revision 12eb4683)
1 /*
2  * drivers/net/ethernet/ibm/emac/mal.h
3  *
4  * Memory Access Layer (MAL) support
5  *
6  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7  *                <benh@kernel.crashing.org>
8  *
9  * Based on the arch/ppc version of the driver:
10  *
11  * Copyright (c) 2004, 2005 Zultys Technologies.
12  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13  *
14  * Based on original work by
15  *      Armin Kuster <akuster@mvista.com>
16  *      Copyright 2002 MontaVista Softare Inc.
17  *
18  * This program is free software; you can redistribute  it and/or modify it
19  * under  the terms of  the GNU General  Public License as published by the
20  * Free Software Foundation;  either version 2 of the  License, or (at your
21  * option) any later version.
22  *
23  */
24 #ifndef __IBM_NEWEMAC_MAL_H
25 #define __IBM_NEWEMAC_MAL_H
26 
27 /*
28  * There are some variations on the MAL, we express them in this driver as
29  * MAL Version 1 and 2 though that doesn't match any IBM terminology.
30  *
31  * We call MAL 1 the version in 405GP, 405GPR, 405EP, 440EP, 440GR and
32  * NP405H.
33  *
34  * We call MAL 2 the version in 440GP, 440GX, 440SP, 440SPE and Axon
35  *
36  * The driver expects a "version" property in the emac node containing
37  * a number 1 or 2. New device-trees for EMAC capable platforms are thus
38  * required to include that when porting to arch/powerpc.
39  */
40 
41 /* MALx DCR registers */
42 #define	MAL_CFG			0x00
43 #define	  MAL_CFG_SR		0x80000000
44 #define   MAL_CFG_PLBB		0x00004000
45 #define   MAL_CFG_OPBBL		0x00000080
46 #define   MAL_CFG_EOPIE		0x00000004
47 #define   MAL_CFG_LEA		0x00000002
48 #define   MAL_CFG_SD		0x00000001
49 
50 /* MAL V1 CFG bits */
51 #define   MAL1_CFG_PLBP_MASK	0x00c00000
52 #define   MAL1_CFG_PLBP_10	0x00800000
53 #define   MAL1_CFG_GA		0x00200000
54 #define   MAL1_CFG_OA		0x00100000
55 #define   MAL1_CFG_PLBLE	0x00080000
56 #define   MAL1_CFG_PLBT_MASK	0x00078000
57 #define   MAL1_CFG_DEFAULT	(MAL1_CFG_PLBP_10 | MAL1_CFG_PLBT_MASK)
58 
59 /* MAL V2 CFG bits */
60 #define   MAL2_CFG_RPP_MASK	0x00c00000
61 #define   MAL2_CFG_RPP_10	0x00800000
62 #define   MAL2_CFG_RMBS_MASK	0x00300000
63 #define   MAL2_CFG_WPP_MASK	0x000c0000
64 #define   MAL2_CFG_WPP_10	0x00080000
65 #define   MAL2_CFG_WMBS_MASK	0x00030000
66 #define   MAL2_CFG_PLBLE	0x00008000
67 #define   MAL2_CFG_DEFAULT	(MAL2_CFG_RMBS_MASK | MAL2_CFG_WMBS_MASK | \
68 				 MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10)
69 
70 #define MAL_ESR			0x01
71 #define   MAL_ESR_EVB		0x80000000
72 #define   MAL_ESR_CIDT		0x40000000
73 #define   MAL_ESR_CID_MASK	0x3e000000
74 #define   MAL_ESR_CID_SHIFT	25
75 #define   MAL_ESR_DE		0x00100000
76 #define   MAL_ESR_OTE		0x00040000
77 #define   MAL_ESR_OSE		0x00020000
78 #define   MAL_ESR_PEIN		0x00010000
79 #define   MAL_ESR_DEI		0x00000010
80 #define   MAL_ESR_OTEI		0x00000004
81 #define   MAL_ESR_OSEI		0x00000002
82 #define   MAL_ESR_PBEI		0x00000001
83 
84 /* MAL V1 ESR bits */
85 #define   MAL1_ESR_ONE		0x00080000
86 #define   MAL1_ESR_ONEI		0x00000008
87 
88 /* MAL V2 ESR bits */
89 #define   MAL2_ESR_PTE		0x00800000
90 #define   MAL2_ESR_PRE		0x00400000
91 #define   MAL2_ESR_PWE		0x00200000
92 #define   MAL2_ESR_PTEI		0x00000080
93 #define   MAL2_ESR_PREI		0x00000040
94 #define   MAL2_ESR_PWEI		0x00000020
95 
96 
97 #define MAL_IER			0x02
98 #define   MAL_IER_DE		0x00000010
99 #define   MAL_IER_OTE		0x00000004
100 #define   MAL_IER_OE		0x00000002
101 #define   MAL_IER_PE		0x00000001
102 /* MAL V1 IER bits */
103 #define   MAL1_IER_NWE		0x00000008
104 #define   MAL1_IER_SOC_EVENTS	MAL1_IER_NWE
105 #define   MAL1_IER_EVENTS	(MAL1_IER_SOC_EVENTS | MAL_IER_DE | \
106 				 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
107 
108 /* MAL V2 IER bits */
109 #define   MAL2_IER_PT		0x00000080
110 #define   MAL2_IER_PRE		0x00000040
111 #define   MAL2_IER_PWE		0x00000020
112 #define   MAL2_IER_SOC_EVENTS	(MAL2_IER_PT | MAL2_IER_PRE | MAL2_IER_PWE)
113 #define   MAL2_IER_EVENTS	(MAL2_IER_SOC_EVENTS | MAL_IER_DE | \
114 				 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
115 
116 
117 #define MAL_TXCASR		0x04
118 #define MAL_TXCARR		0x05
119 #define MAL_TXEOBISR		0x06
120 #define MAL_TXDEIR		0x07
121 #define MAL_RXCASR		0x10
122 #define MAL_RXCARR		0x11
123 #define MAL_RXEOBISR		0x12
124 #define MAL_RXDEIR		0x13
125 #define MAL_TXCTPR(n)		((n) + 0x20)
126 #define MAL_RXCTPR(n)		((n) + 0x40)
127 #define MAL_RCBS(n)		((n) + 0x60)
128 
129 /* In reality MAL can handle TX buffers up to 4095 bytes long,
130  * but this isn't a good round number :) 		 --ebs
131  */
132 #define MAL_MAX_TX_SIZE		4080
133 #define MAL_MAX_RX_SIZE		4080
134 
135 static inline int mal_rx_size(int len)
136 {
137 	len = (len + 0xf) & ~0xf;
138 	return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
139 }
140 
141 static inline int mal_tx_chunks(int len)
142 {
143 	return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
144 }
145 
146 #define MAL_CHAN_MASK(n)	(0x80000000 >> (n))
147 
148 /* MAL Buffer Descriptor structure */
149 struct mal_descriptor {
150 	u16 ctrl;		/* MAL / Commac status control bits */
151 	u16 data_len;		/* Max length is 4K-1 (12 bits)     */
152 	u32 data_ptr;		/* pointer to actual data buffer    */
153 };
154 
155 /* the following defines are for the MadMAL status and control registers. */
156 /* MADMAL transmit and receive status/control bits  */
157 #define MAL_RX_CTRL_EMPTY	0x8000
158 #define MAL_RX_CTRL_WRAP	0x4000
159 #define MAL_RX_CTRL_CM		0x2000
160 #define MAL_RX_CTRL_LAST	0x1000
161 #define MAL_RX_CTRL_FIRST	0x0800
162 #define MAL_RX_CTRL_INTR	0x0400
163 #define MAL_RX_CTRL_SINGLE	(MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
164 #define MAL_IS_SINGLE_RX(ctrl)	(((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
165 
166 #define MAL_TX_CTRL_READY	0x8000
167 #define MAL_TX_CTRL_WRAP	0x4000
168 #define MAL_TX_CTRL_CM		0x2000
169 #define MAL_TX_CTRL_LAST	0x1000
170 #define MAL_TX_CTRL_INTR	0x0400
171 
172 struct mal_commac_ops {
173 	void	(*poll_tx) (void *dev);
174 	int	(*poll_rx) (void *dev, int budget);
175 	int	(*peek_rx) (void *dev);
176 	void	(*rxde) (void *dev);
177 };
178 
179 struct mal_commac {
180 	struct mal_commac_ops	*ops;
181 	void			*dev;
182 	struct list_head	poll_list;
183 	long       		flags;
184 #define MAL_COMMAC_RX_STOPPED		0
185 #define MAL_COMMAC_POLL_DISABLED	1
186 	u32			tx_chan_mask;
187 	u32			rx_chan_mask;
188 	struct list_head	list;
189 };
190 
191 struct mal_instance {
192 	int			version;
193 	dcr_host_t		dcr_host;
194 
195 	int			num_tx_chans;	/* Number of TX channels */
196 	int			num_rx_chans;	/* Number of RX channels */
197 	int 			txeob_irq;	/* TX End Of Buffer IRQ  */
198 	int 			rxeob_irq;	/* RX End Of Buffer IRQ  */
199 	int			txde_irq;	/* TX Descriptor Error IRQ */
200 	int			rxde_irq;	/* RX Descriptor Error IRQ */
201 	int			serr_irq;	/* MAL System Error IRQ    */
202 
203 	struct list_head	poll_list;
204 	struct napi_struct	napi;
205 
206 	struct list_head	list;
207 	u32			tx_chan_mask;
208 	u32			rx_chan_mask;
209 
210 	dma_addr_t		bd_dma;
211 	struct mal_descriptor	*bd_virt;
212 
213 	struct platform_device	*ofdev;
214 	int			index;
215 	spinlock_t		lock;
216 
217 	struct net_device	dummy_dev;
218 
219 	unsigned int features;
220 };
221 
222 static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
223 {
224 	return dcr_read(mal->dcr_host, reg);
225 }
226 
227 static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
228 {
229 	dcr_write(mal->dcr_host, reg, val);
230 }
231 
232 /* Features of various MAL implementations */
233 
234 /* Set if you have interrupt coalescing and you have to clear the SDR
235  * register for TXEOB and RXEOB interrupts to work
236  */
237 #define MAL_FTR_CLEAR_ICINTSTAT	0x00000001
238 
239 /* Set if your MAL has SERR, TXDE, and RXDE OR'd into a single UIC
240  * interrupt
241  */
242 #define MAL_FTR_COMMON_ERR_INT	0x00000002
243 
244 enum {
245 	MAL_FTRS_ALWAYS = 0,
246 
247 	MAL_FTRS_POSSIBLE =
248 #ifdef CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT
249 		MAL_FTR_CLEAR_ICINTSTAT |
250 #endif
251 #ifdef CONFIG_IBM_EMAC_MAL_COMMON_ERR
252 		MAL_FTR_COMMON_ERR_INT |
253 #endif
254 		0,
255 };
256 
257 static inline int mal_has_feature(struct mal_instance *dev,
258 		unsigned long feature)
259 {
260 	return (MAL_FTRS_ALWAYS & feature) ||
261 		(MAL_FTRS_POSSIBLE & dev->features & feature);
262 }
263 
264 /* Register MAL devices */
265 int mal_init(void);
266 void mal_exit(void);
267 
268 int mal_register_commac(struct mal_instance *mal,
269 			struct mal_commac *commac);
270 void mal_unregister_commac(struct mal_instance *mal,
271 			   struct mal_commac *commac);
272 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size);
273 
274 /* Returns BD ring offset for a particular channel
275    (in 'struct mal_descriptor' elements)
276 */
277 int mal_tx_bd_offset(struct mal_instance *mal, int channel);
278 int mal_rx_bd_offset(struct mal_instance *mal, int channel);
279 
280 void mal_enable_tx_channel(struct mal_instance *mal, int channel);
281 void mal_disable_tx_channel(struct mal_instance *mal, int channel);
282 void mal_enable_rx_channel(struct mal_instance *mal, int channel);
283 void mal_disable_rx_channel(struct mal_instance *mal, int channel);
284 
285 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac);
286 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac);
287 
288 /* Add/remove EMAC to/from MAL polling list */
289 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac);
290 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac);
291 
292 /* Ethtool MAL registers */
293 struct mal_regs {
294 	u32 tx_count;
295 	u32 rx_count;
296 
297 	u32 cfg;
298 	u32 esr;
299 	u32 ier;
300 	u32 tx_casr;
301 	u32 tx_carr;
302 	u32 tx_eobisr;
303 	u32 tx_deir;
304 	u32 rx_casr;
305 	u32 rx_carr;
306 	u32 rx_eobisr;
307 	u32 rx_deir;
308 	u32 tx_ctpr[32];
309 	u32 rx_ctpr[32];
310 	u32 rcbs[32];
311 };
312 
313 int mal_get_regs_len(struct mal_instance *mal);
314 void *mal_dump_regs(struct mal_instance *mal, void *buf);
315 
316 #endif /* __IBM_NEWEMAC_MAL_H */
317