1 /* 2 * drivers/net/ethernet/ibm/emac/mal.c 3 * 4 * Memory Access Layer (MAL) support 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies. 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * Based on original work by 15 * Benjamin Herrenschmidt <benh@kernel.crashing.org>, 16 * David Gibson <hermes@gibson.dropbear.id.au>, 17 * 18 * Armin Kuster <akuster@mvista.com> 19 * Copyright 2002 MontaVista Softare Inc. 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms of the GNU General Public License as published by the 23 * Free Software Foundation; either version 2 of the License, or (at your 24 * option) any later version. 25 * 26 */ 27 28 #include <linux/delay.h> 29 #include <linux/slab.h> 30 31 #include "core.h" 32 #include <asm/dcr-regs.h> 33 34 static int mal_count; 35 36 int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac) 37 { 38 unsigned long flags; 39 40 spin_lock_irqsave(&mal->lock, flags); 41 42 MAL_DBG(mal, "reg(%08x, %08x)" NL, 43 commac->tx_chan_mask, commac->rx_chan_mask); 44 45 /* Don't let multiple commacs claim the same channel(s) */ 46 if ((mal->tx_chan_mask & commac->tx_chan_mask) || 47 (mal->rx_chan_mask & commac->rx_chan_mask)) { 48 spin_unlock_irqrestore(&mal->lock, flags); 49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n", 50 mal->index); 51 return -EBUSY; 52 } 53 54 if (list_empty(&mal->list)) 55 napi_enable(&mal->napi); 56 mal->tx_chan_mask |= commac->tx_chan_mask; 57 mal->rx_chan_mask |= commac->rx_chan_mask; 58 list_add(&commac->list, &mal->list); 59 60 spin_unlock_irqrestore(&mal->lock, flags); 61 62 return 0; 63 } 64 65 void mal_unregister_commac(struct mal_instance *mal, 66 struct mal_commac *commac) 67 { 68 unsigned long flags; 69 70 spin_lock_irqsave(&mal->lock, flags); 71 72 MAL_DBG(mal, "unreg(%08x, %08x)" NL, 73 commac->tx_chan_mask, commac->rx_chan_mask); 74 75 mal->tx_chan_mask &= ~commac->tx_chan_mask; 76 mal->rx_chan_mask &= ~commac->rx_chan_mask; 77 list_del_init(&commac->list); 78 if (list_empty(&mal->list)) 79 napi_disable(&mal->napi); 80 81 spin_unlock_irqrestore(&mal->lock, flags); 82 } 83 84 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size) 85 { 86 BUG_ON(channel < 0 || channel >= mal->num_rx_chans || 87 size > MAL_MAX_RX_SIZE); 88 89 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size); 90 91 if (size & 0xf) { 92 printk(KERN_WARNING 93 "mal%d: incorrect RX size %lu for the channel %d\n", 94 mal->index, size, channel); 95 return -EINVAL; 96 } 97 98 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4); 99 return 0; 100 } 101 102 int mal_tx_bd_offset(struct mal_instance *mal, int channel) 103 { 104 BUG_ON(channel < 0 || channel >= mal->num_tx_chans); 105 106 return channel * NUM_TX_BUFF; 107 } 108 109 int mal_rx_bd_offset(struct mal_instance *mal, int channel) 110 { 111 BUG_ON(channel < 0 || channel >= mal->num_rx_chans); 112 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF; 113 } 114 115 void mal_enable_tx_channel(struct mal_instance *mal, int channel) 116 { 117 unsigned long flags; 118 119 spin_lock_irqsave(&mal->lock, flags); 120 121 MAL_DBG(mal, "enable_tx(%d)" NL, channel); 122 123 set_mal_dcrn(mal, MAL_TXCASR, 124 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel)); 125 126 spin_unlock_irqrestore(&mal->lock, flags); 127 } 128 129 void mal_disable_tx_channel(struct mal_instance *mal, int channel) 130 { 131 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel)); 132 133 MAL_DBG(mal, "disable_tx(%d)" NL, channel); 134 } 135 136 void mal_enable_rx_channel(struct mal_instance *mal, int channel) 137 { 138 unsigned long flags; 139 140 /* 141 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple 142 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value 143 * for the bitmask 144 */ 145 if (!(channel % 8)) 146 channel >>= 3; 147 148 spin_lock_irqsave(&mal->lock, flags); 149 150 MAL_DBG(mal, "enable_rx(%d)" NL, channel); 151 152 set_mal_dcrn(mal, MAL_RXCASR, 153 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel)); 154 155 spin_unlock_irqrestore(&mal->lock, flags); 156 } 157 158 void mal_disable_rx_channel(struct mal_instance *mal, int channel) 159 { 160 /* 161 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple 162 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value 163 * for the bitmask 164 */ 165 if (!(channel % 8)) 166 channel >>= 3; 167 168 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); 169 170 MAL_DBG(mal, "disable_rx(%d)" NL, channel); 171 } 172 173 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac) 174 { 175 unsigned long flags; 176 177 spin_lock_irqsave(&mal->lock, flags); 178 179 MAL_DBG(mal, "poll_add(%p)" NL, commac); 180 181 /* starts disabled */ 182 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); 183 184 list_add_tail(&commac->poll_list, &mal->poll_list); 185 186 spin_unlock_irqrestore(&mal->lock, flags); 187 } 188 189 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac) 190 { 191 unsigned long flags; 192 193 spin_lock_irqsave(&mal->lock, flags); 194 195 MAL_DBG(mal, "poll_del(%p)" NL, commac); 196 197 list_del(&commac->poll_list); 198 199 spin_unlock_irqrestore(&mal->lock, flags); 200 } 201 202 /* synchronized by mal_poll() */ 203 static inline void mal_enable_eob_irq(struct mal_instance *mal) 204 { 205 MAL_DBG2(mal, "enable_irq" NL); 206 207 // XXX might want to cache MAL_CFG as the DCR read can be slooooow 208 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE); 209 } 210 211 /* synchronized by NAPI state */ 212 static inline void mal_disable_eob_irq(struct mal_instance *mal) 213 { 214 // XXX might want to cache MAL_CFG as the DCR read can be slooooow 215 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE); 216 217 MAL_DBG2(mal, "disable_irq" NL); 218 } 219 220 static irqreturn_t mal_serr(int irq, void *dev_instance) 221 { 222 struct mal_instance *mal = dev_instance; 223 224 u32 esr = get_mal_dcrn(mal, MAL_ESR); 225 226 /* Clear the error status register */ 227 set_mal_dcrn(mal, MAL_ESR, esr); 228 229 MAL_DBG(mal, "SERR %08x" NL, esr); 230 231 if (esr & MAL_ESR_EVB) { 232 if (esr & MAL_ESR_DE) { 233 /* We ignore Descriptor error, 234 * TXDE or RXDE interrupt will be generated anyway. 235 */ 236 return IRQ_HANDLED; 237 } 238 239 if (esr & MAL_ESR_PEIN) { 240 /* PLB error, it's probably buggy hardware or 241 * incorrect physical address in BD (i.e. bug) 242 */ 243 if (net_ratelimit()) 244 printk(KERN_ERR 245 "mal%d: system error, " 246 "PLB (ESR = 0x%08x)\n", 247 mal->index, esr); 248 return IRQ_HANDLED; 249 } 250 251 /* OPB error, it's probably buggy hardware or incorrect 252 * EBC setup 253 */ 254 if (net_ratelimit()) 255 printk(KERN_ERR 256 "mal%d: system error, OPB (ESR = 0x%08x)\n", 257 mal->index, esr); 258 } 259 return IRQ_HANDLED; 260 } 261 262 static inline void mal_schedule_poll(struct mal_instance *mal) 263 { 264 if (likely(napi_schedule_prep(&mal->napi))) { 265 MAL_DBG2(mal, "schedule_poll" NL); 266 mal_disable_eob_irq(mal); 267 __napi_schedule(&mal->napi); 268 } else 269 MAL_DBG2(mal, "already in poll" NL); 270 } 271 272 static irqreturn_t mal_txeob(int irq, void *dev_instance) 273 { 274 struct mal_instance *mal = dev_instance; 275 276 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR); 277 278 MAL_DBG2(mal, "txeob %08x" NL, r); 279 280 mal_schedule_poll(mal); 281 set_mal_dcrn(mal, MAL_TXEOBISR, r); 282 283 #ifdef CONFIG_PPC_DCR_NATIVE 284 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) 285 mtdcri(SDR0, DCRN_SDR_ICINTSTAT, 286 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX)); 287 #endif 288 289 return IRQ_HANDLED; 290 } 291 292 static irqreturn_t mal_rxeob(int irq, void *dev_instance) 293 { 294 struct mal_instance *mal = dev_instance; 295 296 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR); 297 298 MAL_DBG2(mal, "rxeob %08x" NL, r); 299 300 mal_schedule_poll(mal); 301 set_mal_dcrn(mal, MAL_RXEOBISR, r); 302 303 #ifdef CONFIG_PPC_DCR_NATIVE 304 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT)) 305 mtdcri(SDR0, DCRN_SDR_ICINTSTAT, 306 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX)); 307 #endif 308 309 return IRQ_HANDLED; 310 } 311 312 static irqreturn_t mal_txde(int irq, void *dev_instance) 313 { 314 struct mal_instance *mal = dev_instance; 315 316 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR); 317 set_mal_dcrn(mal, MAL_TXDEIR, deir); 318 319 MAL_DBG(mal, "txde %08x" NL, deir); 320 321 if (net_ratelimit()) 322 printk(KERN_ERR 323 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n", 324 mal->index, deir); 325 326 return IRQ_HANDLED; 327 } 328 329 static irqreturn_t mal_rxde(int irq, void *dev_instance) 330 { 331 struct mal_instance *mal = dev_instance; 332 struct list_head *l; 333 334 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR); 335 336 MAL_DBG(mal, "rxde %08x" NL, deir); 337 338 list_for_each(l, &mal->list) { 339 struct mal_commac *mc = list_entry(l, struct mal_commac, list); 340 if (deir & mc->rx_chan_mask) { 341 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags); 342 mc->ops->rxde(mc->dev); 343 } 344 } 345 346 mal_schedule_poll(mal); 347 set_mal_dcrn(mal, MAL_RXDEIR, deir); 348 349 return IRQ_HANDLED; 350 } 351 352 static irqreturn_t mal_int(int irq, void *dev_instance) 353 { 354 struct mal_instance *mal = dev_instance; 355 u32 esr = get_mal_dcrn(mal, MAL_ESR); 356 357 if (esr & MAL_ESR_EVB) { 358 /* descriptor error */ 359 if (esr & MAL_ESR_DE) { 360 if (esr & MAL_ESR_CIDT) 361 return mal_rxde(irq, dev_instance); 362 else 363 return mal_txde(irq, dev_instance); 364 } else { /* SERR */ 365 return mal_serr(irq, dev_instance); 366 } 367 } 368 return IRQ_HANDLED; 369 } 370 371 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac) 372 { 373 /* Spinlock-type semantics: only one caller disable poll at a time */ 374 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags)) 375 msleep(1); 376 377 /* Synchronize with the MAL NAPI poller */ 378 napi_synchronize(&mal->napi); 379 } 380 381 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac) 382 { 383 smp_wmb(); 384 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags); 385 386 /* Feels better to trigger a poll here to catch up with events that 387 * may have happened on this channel while disabled. It will most 388 * probably be delayed until the next interrupt but that's mostly a 389 * non-issue in the context where this is called. 390 */ 391 napi_schedule(&mal->napi); 392 } 393 394 static int mal_poll(struct napi_struct *napi, int budget) 395 { 396 struct mal_instance *mal = container_of(napi, struct mal_instance, napi); 397 struct list_head *l; 398 int received = 0; 399 unsigned long flags; 400 401 MAL_DBG2(mal, "poll(%d)" NL, budget); 402 again: 403 /* Process TX skbs */ 404 list_for_each(l, &mal->poll_list) { 405 struct mal_commac *mc = 406 list_entry(l, struct mal_commac, poll_list); 407 mc->ops->poll_tx(mc->dev); 408 } 409 410 /* Process RX skbs. 411 * 412 * We _might_ need something more smart here to enforce polling 413 * fairness. 414 */ 415 list_for_each(l, &mal->poll_list) { 416 struct mal_commac *mc = 417 list_entry(l, struct mal_commac, poll_list); 418 int n; 419 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) 420 continue; 421 n = mc->ops->poll_rx(mc->dev, budget); 422 if (n) { 423 received += n; 424 budget -= n; 425 if (budget <= 0) 426 goto more_work; // XXX What if this is the last one ? 427 } 428 } 429 430 /* We need to disable IRQs to protect from RXDE IRQ here */ 431 spin_lock_irqsave(&mal->lock, flags); 432 __napi_complete(napi); 433 mal_enable_eob_irq(mal); 434 spin_unlock_irqrestore(&mal->lock, flags); 435 436 /* Check for "rotting" packet(s) */ 437 list_for_each(l, &mal->poll_list) { 438 struct mal_commac *mc = 439 list_entry(l, struct mal_commac, poll_list); 440 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags))) 441 continue; 442 if (unlikely(mc->ops->peek_rx(mc->dev) || 443 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) { 444 MAL_DBG2(mal, "rotting packet" NL); 445 if (napi_reschedule(napi)) 446 mal_disable_eob_irq(mal); 447 else 448 MAL_DBG2(mal, "already in poll list" NL); 449 450 if (budget > 0) 451 goto again; 452 else 453 goto more_work; 454 } 455 mc->ops->poll_tx(mc->dev); 456 } 457 458 more_work: 459 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received); 460 return received; 461 } 462 463 static void mal_reset(struct mal_instance *mal) 464 { 465 int n = 10; 466 467 MAL_DBG(mal, "reset" NL); 468 469 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR); 470 471 /* Wait for reset to complete (1 system clock) */ 472 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n) 473 --n; 474 475 if (unlikely(!n)) 476 printk(KERN_ERR "mal%d: reset timeout\n", mal->index); 477 } 478 479 int mal_get_regs_len(struct mal_instance *mal) 480 { 481 return sizeof(struct emac_ethtool_regs_subhdr) + 482 sizeof(struct mal_regs); 483 } 484 485 void *mal_dump_regs(struct mal_instance *mal, void *buf) 486 { 487 struct emac_ethtool_regs_subhdr *hdr = buf; 488 struct mal_regs *regs = (struct mal_regs *)(hdr + 1); 489 int i; 490 491 hdr->version = mal->version; 492 hdr->index = mal->index; 493 494 regs->tx_count = mal->num_tx_chans; 495 regs->rx_count = mal->num_rx_chans; 496 497 regs->cfg = get_mal_dcrn(mal, MAL_CFG); 498 regs->esr = get_mal_dcrn(mal, MAL_ESR); 499 regs->ier = get_mal_dcrn(mal, MAL_IER); 500 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR); 501 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR); 502 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR); 503 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR); 504 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR); 505 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR); 506 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR); 507 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR); 508 509 for (i = 0; i < regs->tx_count; ++i) 510 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i)); 511 512 for (i = 0; i < regs->rx_count; ++i) { 513 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i)); 514 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i)); 515 } 516 return regs + 1; 517 } 518 519 static int mal_probe(struct platform_device *ofdev) 520 { 521 struct mal_instance *mal; 522 int err = 0, i, bd_size; 523 int index = mal_count++; 524 unsigned int dcr_base; 525 const u32 *prop; 526 u32 cfg; 527 unsigned long irqflags; 528 irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde; 529 530 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL); 531 if (!mal) { 532 printk(KERN_ERR 533 "mal%d: out of memory allocating MAL structure!\n", 534 index); 535 return -ENOMEM; 536 } 537 mal->index = index; 538 mal->ofdev = ofdev; 539 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1; 540 541 MAL_DBG(mal, "probe" NL); 542 543 prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL); 544 if (prop == NULL) { 545 printk(KERN_ERR 546 "mal%d: can't find MAL num-tx-chans property!\n", 547 index); 548 err = -ENODEV; 549 goto fail; 550 } 551 mal->num_tx_chans = prop[0]; 552 553 prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL); 554 if (prop == NULL) { 555 printk(KERN_ERR 556 "mal%d: can't find MAL num-rx-chans property!\n", 557 index); 558 err = -ENODEV; 559 goto fail; 560 } 561 mal->num_rx_chans = prop[0]; 562 563 dcr_base = dcr_resource_start(ofdev->dev.of_node, 0); 564 if (dcr_base == 0) { 565 printk(KERN_ERR 566 "mal%d: can't find DCR resource!\n", index); 567 err = -ENODEV; 568 goto fail; 569 } 570 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100); 571 if (!DCR_MAP_OK(mal->dcr_host)) { 572 printk(KERN_ERR 573 "mal%d: failed to map DCRs !\n", index); 574 err = -ENODEV; 575 goto fail; 576 } 577 578 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) { 579 #if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \ 580 defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR) 581 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT | 582 MAL_FTR_COMMON_ERR_INT); 583 #else 584 printk(KERN_ERR "%s: Support for 405EZ not enabled!\n", 585 ofdev->dev.of_node->full_name); 586 err = -ENODEV; 587 goto fail; 588 #endif 589 } 590 591 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 592 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1); 593 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2); 594 595 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { 596 mal->txde_irq = mal->rxde_irq = mal->serr_irq; 597 } else { 598 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3); 599 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4); 600 } 601 602 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ || 603 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ || 604 mal->rxde_irq == NO_IRQ) { 605 printk(KERN_ERR 606 "mal%d: failed to map interrupts !\n", index); 607 err = -ENODEV; 608 goto fail_unmap; 609 } 610 611 INIT_LIST_HEAD(&mal->poll_list); 612 INIT_LIST_HEAD(&mal->list); 613 spin_lock_init(&mal->lock); 614 615 init_dummy_netdev(&mal->dummy_dev); 616 617 netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll, 618 CONFIG_IBM_EMAC_POLL_WEIGHT); 619 620 /* Load power-on reset defaults */ 621 mal_reset(mal); 622 623 /* Set the MAL configuration register */ 624 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT; 625 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA; 626 627 /* Current Axon is not happy with priority being non-0, it can 628 * deadlock, fix it up here 629 */ 630 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon")) 631 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10); 632 633 /* Apply configuration */ 634 set_mal_dcrn(mal, MAL_CFG, cfg); 635 636 /* Allocate space for BD rings */ 637 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32); 638 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32); 639 640 bd_size = sizeof(struct mal_descriptor) * 641 (NUM_TX_BUFF * mal->num_tx_chans + 642 NUM_RX_BUFF * mal->num_rx_chans); 643 mal->bd_virt = 644 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma, 645 GFP_KERNEL); 646 if (mal->bd_virt == NULL) { 647 printk(KERN_ERR 648 "mal%d: out of memory allocating RX/TX descriptors!\n", 649 index); 650 err = -ENOMEM; 651 goto fail_unmap; 652 } 653 memset(mal->bd_virt, 0, bd_size); 654 655 for (i = 0; i < mal->num_tx_chans; ++i) 656 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma + 657 sizeof(struct mal_descriptor) * 658 mal_tx_bd_offset(mal, i)); 659 660 for (i = 0; i < mal->num_rx_chans; ++i) 661 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma + 662 sizeof(struct mal_descriptor) * 663 mal_rx_bd_offset(mal, i)); 664 665 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) { 666 irqflags = IRQF_SHARED; 667 hdlr_serr = hdlr_txde = hdlr_rxde = mal_int; 668 } else { 669 irqflags = 0; 670 hdlr_serr = mal_serr; 671 hdlr_txde = mal_txde; 672 hdlr_rxde = mal_rxde; 673 } 674 675 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal); 676 if (err) 677 goto fail2; 678 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal); 679 if (err) 680 goto fail3; 681 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal); 682 if (err) 683 goto fail4; 684 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal); 685 if (err) 686 goto fail5; 687 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal); 688 if (err) 689 goto fail6; 690 691 /* Enable all MAL SERR interrupt sources */ 692 if (mal->version == 2) 693 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS); 694 else 695 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS); 696 697 /* Enable EOB interrupt */ 698 mal_enable_eob_irq(mal); 699 700 printk(KERN_INFO 701 "MAL v%d %s, %d TX channels, %d RX channels\n", 702 mal->version, ofdev->dev.of_node->full_name, 703 mal->num_tx_chans, mal->num_rx_chans); 704 705 /* Advertise this instance to the rest of the world */ 706 wmb(); 707 dev_set_drvdata(&ofdev->dev, mal); 708 709 mal_dbg_register(mal); 710 711 return 0; 712 713 fail6: 714 free_irq(mal->rxde_irq, mal); 715 fail5: 716 free_irq(mal->txeob_irq, mal); 717 fail4: 718 free_irq(mal->txde_irq, mal); 719 fail3: 720 free_irq(mal->serr_irq, mal); 721 fail2: 722 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma); 723 fail_unmap: 724 dcr_unmap(mal->dcr_host, 0x100); 725 fail: 726 kfree(mal); 727 728 return err; 729 } 730 731 static int mal_remove(struct platform_device *ofdev) 732 { 733 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev); 734 735 MAL_DBG(mal, "remove" NL); 736 737 /* Synchronize with scheduled polling */ 738 napi_disable(&mal->napi); 739 740 if (!list_empty(&mal->list)) 741 /* This is *very* bad */ 742 WARN(1, KERN_EMERG 743 "mal%d: commac list is not empty on remove!\n", 744 mal->index); 745 746 dev_set_drvdata(&ofdev->dev, NULL); 747 748 free_irq(mal->serr_irq, mal); 749 free_irq(mal->txde_irq, mal); 750 free_irq(mal->txeob_irq, mal); 751 free_irq(mal->rxde_irq, mal); 752 free_irq(mal->rxeob_irq, mal); 753 754 mal_reset(mal); 755 756 mal_dbg_unregister(mal); 757 758 dma_free_coherent(&ofdev->dev, 759 sizeof(struct mal_descriptor) * 760 (NUM_TX_BUFF * mal->num_tx_chans + 761 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt, 762 mal->bd_dma); 763 kfree(mal); 764 765 return 0; 766 } 767 768 static struct of_device_id mal_platform_match[] = 769 { 770 { 771 .compatible = "ibm,mcmal", 772 }, 773 { 774 .compatible = "ibm,mcmal2", 775 }, 776 /* Backward compat */ 777 { 778 .type = "mcmal-dma", 779 .compatible = "ibm,mcmal", 780 }, 781 { 782 .type = "mcmal-dma", 783 .compatible = "ibm,mcmal2", 784 }, 785 {}, 786 }; 787 788 static struct platform_driver mal_of_driver = { 789 .driver = { 790 .name = "mcmal", 791 .owner = THIS_MODULE, 792 .of_match_table = mal_platform_match, 793 }, 794 .probe = mal_probe, 795 .remove = mal_remove, 796 }; 797 798 int __init mal_init(void) 799 { 800 return platform_driver_register(&mal_of_driver); 801 } 802 803 void mal_exit(void) 804 { 805 platform_driver_unregister(&mal_of_driver); 806 } 807