1 /* 2 * drivers/net/ethernet/ibm/emac/emac.h 3 * 4 * Register definitions for PowerPC 4xx on-chip ethernet contoller 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies. 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * Based on original work by 15 * Matt Porter <mporter@kernel.crashing.org> 16 * Armin Kuster <akuster@mvista.com> 17 * Copyright 2002-2004 MontaVista Software Inc. 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 * 24 */ 25 #ifndef __IBM_NEWEMAC_H 26 #define __IBM_NEWEMAC_H 27 28 #include <linux/types.h> 29 #include <linux/phy.h> 30 31 /* EMAC registers Write Access rules */ 32 struct emac_regs { 33 /* Common registers across all EMAC implementations. */ 34 u32 mr0; /* Special */ 35 u32 mr1; /* Reset */ 36 u32 tmr0; /* Special */ 37 u32 tmr1; /* Special */ 38 u32 rmr; /* Reset */ 39 u32 isr; /* Always */ 40 u32 iser; /* Reset */ 41 u32 iahr; /* Reset, R, T */ 42 u32 ialr; /* Reset, R, T */ 43 u32 vtpid; /* Reset, R, T */ 44 u32 vtci; /* Reset, R, T */ 45 u32 ptr; /* Reset, T */ 46 union { 47 /* Registers unique to EMAC4 implementations */ 48 struct { 49 u32 iaht1; /* Reset, R */ 50 u32 iaht2; /* Reset, R */ 51 u32 iaht3; /* Reset, R */ 52 u32 iaht4; /* Reset, R */ 53 u32 gaht1; /* Reset, R */ 54 u32 gaht2; /* Reset, R */ 55 u32 gaht3; /* Reset, R */ 56 u32 gaht4; /* Reset, R */ 57 } emac4; 58 /* Registers unique to EMAC4SYNC implementations */ 59 struct { 60 u32 mahr; /* Reset, R, T */ 61 u32 malr; /* Reset, R, T */ 62 u32 mmahr; /* Reset, R, T */ 63 u32 mmalr; /* Reset, R, T */ 64 u32 rsvd0[4]; 65 } emac4sync; 66 } u0; 67 /* Common registers across all EMAC implementations. */ 68 u32 lsah; 69 u32 lsal; 70 u32 ipgvr; /* Reset, T */ 71 u32 stacr; /* Special */ 72 u32 trtr; /* Special */ 73 u32 rwmr; /* Reset */ 74 u32 octx; 75 u32 ocrx; 76 union { 77 /* Registers unique to EMAC4 implementations */ 78 struct { 79 u32 ipcr; 80 } emac4; 81 /* Registers unique to EMAC4SYNC implementations */ 82 struct { 83 u32 rsvd1; 84 u32 revid; 85 u32 rsvd2[2]; 86 u32 iaht1; /* Reset, R */ 87 u32 iaht2; /* Reset, R */ 88 u32 iaht3; /* Reset, R */ 89 u32 iaht4; /* Reset, R */ 90 u32 iaht5; /* Reset, R */ 91 u32 iaht6; /* Reset, R */ 92 u32 iaht7; /* Reset, R */ 93 u32 iaht8; /* Reset, R */ 94 u32 gaht1; /* Reset, R */ 95 u32 gaht2; /* Reset, R */ 96 u32 gaht3; /* Reset, R */ 97 u32 gaht4; /* Reset, R */ 98 u32 gaht5; /* Reset, R */ 99 u32 gaht6; /* Reset, R */ 100 u32 gaht7; /* Reset, R */ 101 u32 gaht8; /* Reset, R */ 102 u32 tpc; /* Reset, T */ 103 } emac4sync; 104 } u1; 105 }; 106 107 /* EMACx_MR0 */ 108 #define EMAC_MR0_RXI 0x80000000 109 #define EMAC_MR0_TXI 0x40000000 110 #define EMAC_MR0_SRST 0x20000000 111 #define EMAC_MR0_TXE 0x10000000 112 #define EMAC_MR0_RXE 0x08000000 113 #define EMAC_MR0_WKE 0x04000000 114 115 /* EMACx_MR1 */ 116 #define EMAC_MR1_FDE 0x80000000 117 #define EMAC_MR1_ILE 0x40000000 118 #define EMAC_MR1_VLE 0x20000000 119 #define EMAC_MR1_EIFC 0x10000000 120 #define EMAC_MR1_APP 0x08000000 121 #define EMAC_MR1_IST 0x01000000 122 123 #define EMAC_MR1_MF_MASK 0x00c00000 124 #define EMAC_MR1_MF_10 0x00000000 125 #define EMAC_MR1_MF_100 0x00400000 126 #define EMAC_MR1_MF_1000 0x00800000 127 #define EMAC_MR1_MF_1000GPCS 0x00c00000 128 #define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6) 129 130 #define EMAC_MR1_RFS_4K 0x00300000 131 #define EMAC_MR1_RFS_16K 0x00000000 132 #define EMAC_MR1_TFS_2K 0x00080000 133 #define EMAC_MR1_TR0_MULT 0x00008000 134 #define EMAC_MR1_JPSM 0x00000000 135 #define EMAC_MR1_MWSW_001 0x00000000 136 #define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT) 137 138 139 #define EMAC4_MR1_RFS_2K 0x00100000 140 #define EMAC4_MR1_RFS_4K 0x00180000 141 #define EMAC4_MR1_RFS_16K 0x00280000 142 #define EMAC4_MR1_TFS_2K 0x00020000 143 #define EMAC4_MR1_TFS_4K 0x00030000 144 #define EMAC4_MR1_TFS_16K 0x00050000 145 #define EMAC4_MR1_TR 0x00008000 146 #define EMAC4_MR1_MWSW_001 0x00001000 147 #define EMAC4_MR1_JPSM 0x00000800 148 #define EMAC4_MR1_OBCI_MASK 0x00000038 149 #define EMAC4_MR1_OBCI_50 0x00000000 150 #define EMAC4_MR1_OBCI_66 0x00000008 151 #define EMAC4_MR1_OBCI_83 0x00000010 152 #define EMAC4_MR1_OBCI_100 0x00000018 153 #define EMAC4_MR1_OBCI_100P 0x00000020 154 #define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \ 155 (freq) <= 66 ? EMAC4_MR1_OBCI_66 : \ 156 (freq) <= 83 ? EMAC4_MR1_OBCI_83 : \ 157 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \ 158 EMAC4_MR1_OBCI_100P) 159 160 /* EMACx_TMR0 */ 161 #define EMAC_TMR0_GNP 0x80000000 162 #define EMAC_TMR0_DEFAULT 0x00000000 163 #define EMAC4_TMR0_TFAE_2_32 0x00000001 164 #define EMAC4_TMR0_TFAE_4_64 0x00000002 165 #define EMAC4_TMR0_TFAE_8_128 0x00000003 166 #define EMAC4_TMR0_TFAE_16_256 0x00000004 167 #define EMAC4_TMR0_TFAE_32_512 0x00000005 168 #define EMAC4_TMR0_TFAE_64_1024 0x00000006 169 #define EMAC4_TMR0_TFAE_128_2048 0x00000007 170 #define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32 171 #define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT) 172 #define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT) 173 174 /* EMACx_TMR1 */ 175 176 #define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16)) 177 #define EMAC4_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14)) 178 179 /* EMACx_RMR */ 180 #define EMAC_RMR_SP 0x80000000 181 #define EMAC_RMR_SFCS 0x40000000 182 #define EMAC_RMR_RRP 0x20000000 183 #define EMAC_RMR_RFP 0x10000000 184 #define EMAC_RMR_ROP 0x08000000 185 #define EMAC_RMR_RPIR 0x04000000 186 #define EMAC_RMR_PPP 0x02000000 187 #define EMAC_RMR_PME 0x01000000 188 #define EMAC_RMR_PMME 0x00800000 189 #define EMAC_RMR_IAE 0x00400000 190 #define EMAC_RMR_MIAE 0x00200000 191 #define EMAC_RMR_BAE 0x00100000 192 #define EMAC_RMR_MAE 0x00080000 193 #define EMAC_RMR_BASE 0x00000000 194 #define EMAC4_RMR_RFAF_2_32 0x00000001 195 #define EMAC4_RMR_RFAF_4_64 0x00000002 196 #define EMAC4_RMR_RFAF_8_128 0x00000003 197 #define EMAC4_RMR_RFAF_16_256 0x00000004 198 #define EMAC4_RMR_RFAF_32_512 0x00000005 199 #define EMAC4_RMR_RFAF_64_1024 0x00000006 200 #define EMAC4_RMR_RFAF_128_2048 0x00000007 201 #define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048 202 #define EMAC4_RMR_MJS_MASK 0x0001fff8 203 #define EMAC4_RMR_MJS(s) (((s) << 3) & EMAC4_RMR_MJS_MASK) 204 205 /* EMACx_ISR & EMACx_ISER */ 206 #define EMAC4_ISR_TXPE 0x20000000 207 #define EMAC4_ISR_RXPE 0x10000000 208 #define EMAC4_ISR_TXUE 0x08000000 209 #define EMAC4_ISR_RXOE 0x04000000 210 #define EMAC_ISR_OVR 0x02000000 211 #define EMAC_ISR_PP 0x01000000 212 #define EMAC_ISR_BP 0x00800000 213 #define EMAC_ISR_RP 0x00400000 214 #define EMAC_ISR_SE 0x00200000 215 #define EMAC_ISR_ALE 0x00100000 216 #define EMAC_ISR_BFCS 0x00080000 217 #define EMAC_ISR_PTLE 0x00040000 218 #define EMAC_ISR_ORE 0x00020000 219 #define EMAC_ISR_IRE 0x00010000 220 #define EMAC_ISR_SQE 0x00000080 221 #define EMAC_ISR_TE 0x00000040 222 #define EMAC_ISR_MOS 0x00000002 223 #define EMAC_ISR_MOF 0x00000001 224 225 /* EMACx_STACR */ 226 #define EMAC_STACR_PHYD_MASK 0xffff 227 #define EMAC_STACR_PHYD_SHIFT 16 228 #define EMAC_STACR_OC 0x00008000 229 #define EMAC_STACR_PHYE 0x00004000 230 #define EMAC_STACR_STAC_MASK 0x00003000 231 #define EMAC_STACR_STAC_READ 0x00001000 232 #define EMAC_STACR_STAC_WRITE 0x00002000 233 #define EMAC_STACR_OPBC_MASK 0x00000C00 234 #define EMAC_STACR_OPBC_50 0x00000000 235 #define EMAC_STACR_OPBC_66 0x00000400 236 #define EMAC_STACR_OPBC_83 0x00000800 237 #define EMAC_STACR_OPBC_100 0x00000C00 238 #define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \ 239 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \ 240 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100) 241 #define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb) 242 #define EMAC4_STACR_BASE(opb) 0x00000000 243 #define EMAC_STACR_PCDA_MASK 0x1f 244 #define EMAC_STACR_PCDA_SHIFT 5 245 #define EMAC_STACR_PRA_MASK 0x1f 246 #define EMACX_STACR_STAC_MASK 0x00003800 247 #define EMACX_STACR_STAC_READ 0x00001000 248 #define EMACX_STACR_STAC_WRITE 0x00000800 249 #define EMACX_STACR_STAC_IND_ADDR 0x00002000 250 #define EMACX_STACR_STAC_IND_READ 0x00003800 251 #define EMACX_STACR_STAC_IND_READINC 0x00003000 252 #define EMACX_STACR_STAC_IND_WRITE 0x00002800 253 254 255 /* EMACx_TRTR */ 256 #define EMAC_TRTR_SHIFT_EMAC4 24 257 #define EMAC_TRTR_SHIFT 27 258 259 /* EMAC specific TX descriptor control fields (write access) */ 260 #define EMAC_TX_CTRL_GFCS 0x0200 261 #define EMAC_TX_CTRL_GP 0x0100 262 #define EMAC_TX_CTRL_ISA 0x0080 263 #define EMAC_TX_CTRL_RSA 0x0040 264 #define EMAC_TX_CTRL_IVT 0x0020 265 #define EMAC_TX_CTRL_RVT 0x0010 266 #define EMAC_TX_CTRL_TAH_CSUM 0x000e 267 268 /* EMAC specific TX descriptor status fields (read access) */ 269 #define EMAC_TX_ST_BFCS 0x0200 270 #define EMAC_TX_ST_LCS 0x0080 271 #define EMAC_TX_ST_ED 0x0040 272 #define EMAC_TX_ST_EC 0x0020 273 #define EMAC_TX_ST_LC 0x0010 274 #define EMAC_TX_ST_MC 0x0008 275 #define EMAC_TX_ST_SC 0x0004 276 #define EMAC_TX_ST_UR 0x0002 277 #define EMAC_TX_ST_SQE 0x0001 278 #define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \ 279 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \ 280 EMAC_TX_ST_MC | EMAC_TX_ST_UR) 281 #define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \ 282 EMAC_TX_ST_EC | EMAC_TX_ST_LC) 283 284 /* EMAC specific RX descriptor status fields (read access) */ 285 #define EMAC_RX_ST_OE 0x0200 286 #define EMAC_RX_ST_PP 0x0100 287 #define EMAC_RX_ST_BP 0x0080 288 #define EMAC_RX_ST_RP 0x0040 289 #define EMAC_RX_ST_SE 0x0020 290 #define EMAC_RX_ST_AE 0x0010 291 #define EMAC_RX_ST_BFCS 0x0008 292 #define EMAC_RX_ST_PTL 0x0004 293 #define EMAC_RX_ST_ORE 0x0002 294 #define EMAC_RX_ST_IRE 0x0001 295 #define EMAC_RX_TAH_BAD_CSUM 0x0003 296 #define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \ 297 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \ 298 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \ 299 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \ 300 EMAC_RX_ST_IRE ) 301 #endif /* __IBM_NEWEMAC_H */ 302