1 /* 2 * drivers/net/ethernet/ibm/emac/core.h 3 * 4 * Driver for PowerPC 4xx on-chip ethernet controller. 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies. 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * Based on original work by 15 * Armin Kuster <akuster@mvista.com> 16 * Johnnie Peters <jpeters@mvista.com> 17 * Copyright 2000, 2001 MontaVista Softare Inc. 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 * 24 */ 25 #ifndef __IBM_NEWEMAC_CORE_H 26 #define __IBM_NEWEMAC_CORE_H 27 28 #include <linux/module.h> 29 #include <linux/list.h> 30 #include <linux/kernel.h> 31 #include <linux/interrupt.h> 32 #include <linux/netdevice.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/spinlock.h> 35 #include <linux/of_platform.h> 36 #include <linux/slab.h> 37 38 #include <asm/io.h> 39 #include <asm/dcr.h> 40 41 #include "emac.h" 42 #include "phy.h" 43 #include "zmii.h" 44 #include "rgmii.h" 45 #include "mal.h" 46 #include "tah.h" 47 #include "debug.h" 48 49 #define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB 50 #define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB 51 52 /* Simple sanity check */ 53 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 54 #error Invalid number of buffer descriptors (greater than 256) 55 #endif 56 57 #define EMAC_MIN_MTU 46 58 59 /* Maximum L2 header length (VLAN tagged, no FCS) */ 60 #define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) 61 62 /* RX BD size for the given MTU */ 63 static inline int emac_rx_size(int mtu) 64 { 65 if (mtu > ETH_DATA_LEN) 66 return MAL_MAX_RX_SIZE; 67 else 68 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD); 69 } 70 71 /* Size of RX skb for the given MTU */ 72 static inline int emac_rx_skb_size(int mtu) 73 { 74 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); 75 76 return SKB_DATA_ALIGN(size + NET_IP_ALIGN) + NET_SKB_PAD; 77 } 78 79 /* RX DMA sync size */ 80 static inline int emac_rx_sync_size(int mtu) 81 { 82 return SKB_DATA_ALIGN(emac_rx_size(mtu) + NET_IP_ALIGN); 83 } 84 85 /* Driver statistcs is split into two parts to make it more cache friendly: 86 * - normal statistics (packet count, etc) 87 * - error statistics 88 * 89 * When statistics is requested by ethtool, these parts are concatenated, 90 * normal one goes first. 91 * 92 * Please, keep these structures in sync with emac_stats_keys. 93 */ 94 95 /* Normal TX/RX Statistics */ 96 struct emac_stats { 97 u64 rx_packets; 98 u64 rx_bytes; 99 u64 tx_packets; 100 u64 tx_bytes; 101 u64 rx_packets_csum; 102 u64 tx_packets_csum; 103 }; 104 105 /* Error statistics */ 106 struct emac_error_stats { 107 u64 tx_undo; 108 109 /* Software RX Errors */ 110 u64 rx_dropped_stack; 111 u64 rx_dropped_oom; 112 u64 rx_dropped_error; 113 u64 rx_dropped_resize; 114 u64 rx_dropped_mtu; 115 u64 rx_stopped; 116 /* BD reported RX errors */ 117 u64 rx_bd_errors; 118 u64 rx_bd_overrun; 119 u64 rx_bd_bad_packet; 120 u64 rx_bd_runt_packet; 121 u64 rx_bd_short_event; 122 u64 rx_bd_alignment_error; 123 u64 rx_bd_bad_fcs; 124 u64 rx_bd_packet_too_long; 125 u64 rx_bd_out_of_range; 126 u64 rx_bd_in_range; 127 /* EMAC IRQ reported RX errors */ 128 u64 rx_parity; 129 u64 rx_fifo_overrun; 130 u64 rx_overrun; 131 u64 rx_bad_packet; 132 u64 rx_runt_packet; 133 u64 rx_short_event; 134 u64 rx_alignment_error; 135 u64 rx_bad_fcs; 136 u64 rx_packet_too_long; 137 u64 rx_out_of_range; 138 u64 rx_in_range; 139 140 /* Software TX Errors */ 141 u64 tx_dropped; 142 /* BD reported TX errors */ 143 u64 tx_bd_errors; 144 u64 tx_bd_bad_fcs; 145 u64 tx_bd_carrier_loss; 146 u64 tx_bd_excessive_deferral; 147 u64 tx_bd_excessive_collisions; 148 u64 tx_bd_late_collision; 149 u64 tx_bd_multple_collisions; 150 u64 tx_bd_single_collision; 151 u64 tx_bd_underrun; 152 u64 tx_bd_sqe; 153 /* EMAC IRQ reported TX errors */ 154 u64 tx_parity; 155 u64 tx_underrun; 156 u64 tx_sqe; 157 u64 tx_errors; 158 }; 159 160 #define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ 161 sizeof(struct emac_error_stats)) \ 162 / sizeof(u64)) 163 164 struct emac_instance { 165 struct net_device *ndev; 166 struct emac_regs __iomem *emacp; 167 struct platform_device *ofdev; 168 struct device_node **blist; /* bootlist entry */ 169 170 /* MAL linkage */ 171 u32 mal_ph; 172 struct platform_device *mal_dev; 173 u32 mal_rx_chan; 174 u32 mal_tx_chan; 175 struct mal_instance *mal; 176 struct mal_commac commac; 177 178 /* PHY infos */ 179 int phy_mode; 180 u32 phy_map; 181 u32 phy_address; 182 u32 phy_feat_exc; 183 struct mii_phy phy; 184 struct mutex link_lock; 185 struct delayed_work link_work; 186 int link_polling; 187 188 /* GPCS PHY infos */ 189 u32 gpcs_address; 190 191 /* Shared MDIO if any */ 192 u32 mdio_ph; 193 struct platform_device *mdio_dev; 194 struct emac_instance *mdio_instance; 195 struct mutex mdio_lock; 196 197 /* Device-tree based phy configuration */ 198 struct mii_bus *mii_bus; 199 struct phy_device *phy_dev; 200 201 /* ZMII infos if any */ 202 u32 zmii_ph; 203 u32 zmii_port; 204 struct platform_device *zmii_dev; 205 206 /* RGMII infos if any */ 207 u32 rgmii_ph; 208 u32 rgmii_port; 209 struct platform_device *rgmii_dev; 210 211 /* TAH infos if any */ 212 u32 tah_ph; 213 u32 tah_port; 214 struct platform_device *tah_dev; 215 216 /* IRQs */ 217 int wol_irq; 218 int emac_irq; 219 220 /* OPB bus frequency in Mhz */ 221 u32 opb_bus_freq; 222 223 /* Cell index within an ASIC (for clk mgmnt) */ 224 u32 cell_index; 225 226 /* Max supported MTU */ 227 u32 max_mtu; 228 229 /* Feature bits (from probe table) */ 230 unsigned int features; 231 232 /* Tx and Rx fifo sizes & other infos in bytes */ 233 u32 tx_fifo_size; 234 u32 tx_fifo_size_gige; 235 u32 rx_fifo_size; 236 u32 rx_fifo_size_gige; 237 u32 fifo_entry_size; 238 u32 mal_burst_size; /* move to MAL ? */ 239 240 /* IAHT and GAHT filter parameterization */ 241 u32 xaht_slots_shift; 242 u32 xaht_width_shift; 243 244 /* Descriptor management 245 */ 246 struct mal_descriptor *tx_desc; 247 int tx_cnt; 248 int tx_slot; 249 int ack_slot; 250 251 struct mal_descriptor *rx_desc; 252 int rx_slot; 253 struct sk_buff *rx_sg_skb; /* 1 */ 254 int rx_skb_size; 255 int rx_sync_size; 256 257 struct sk_buff *tx_skb[NUM_TX_BUFF]; 258 struct sk_buff *rx_skb[NUM_RX_BUFF]; 259 260 /* Stats 261 */ 262 struct emac_error_stats estats; 263 struct emac_stats stats; 264 265 /* Misc 266 */ 267 int reset_failed; 268 int stop_timeout; /* in us */ 269 int no_mcast; 270 int mcast_pending; 271 int opened; 272 struct work_struct reset_work; 273 spinlock_t lock; 274 }; 275 276 /* 277 * Features of various EMAC implementations 278 */ 279 280 /* 281 * No flow control on 40x according to the original driver 282 */ 283 #define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 284 /* 285 * Cell is an EMAC4 286 */ 287 #define EMAC_FTR_EMAC4 0x00000002 288 /* 289 * For the 440SPe, AMCC inexplicably changed the polarity of 290 * the "operation complete" bit in the MII control register. 291 */ 292 #define EMAC_FTR_STACR_OC_INVERT 0x00000004 293 /* 294 * Set if we have a TAH. 295 */ 296 #define EMAC_FTR_HAS_TAH 0x00000008 297 /* 298 * Set if we have a ZMII. 299 */ 300 #define EMAC_FTR_HAS_ZMII 0x00000010 301 /* 302 * Set if we have a RGMII. 303 */ 304 #define EMAC_FTR_HAS_RGMII 0x00000020 305 /* 306 * Set if we have new type STACR with STAOPC 307 */ 308 #define EMAC_FTR_HAS_NEW_STACR 0x00000040 309 /* 310 * Set if we need phy clock workaround for 440gx 311 */ 312 #define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 313 /* 314 * Set if we need phy clock workaround for 440ep or 440gr 315 */ 316 #define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 317 /* 318 * The 405EX and 460EX contain the EMAC4SYNC core 319 */ 320 #define EMAC_FTR_EMAC4SYNC 0x00000200 321 /* 322 * Set if we need phy clock workaround for 460ex or 460gt 323 */ 324 #define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400 325 /* 326 * APM821xx requires Jumbo frame size set explicitly 327 */ 328 #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800 329 /* 330 * APM821xx does not support Half Duplex mode 331 */ 332 #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000 333 334 /* Right now, we don't quite handle the always/possible masks on the 335 * most optimal way as we don't have a way to say something like 336 * always EMAC4. Patches welcome. 337 */ 338 enum { 339 EMAC_FTRS_ALWAYS = 0, 340 341 EMAC_FTRS_POSSIBLE = 342 #ifdef CONFIG_IBM_EMAC_EMAC4 343 EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | 344 EMAC_FTR_HAS_NEW_STACR | 345 EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | 346 #endif 347 #ifdef CONFIG_IBM_EMAC_TAH 348 EMAC_FTR_HAS_TAH | 349 #endif 350 #ifdef CONFIG_IBM_EMAC_ZMII 351 EMAC_FTR_HAS_ZMII | 352 #endif 353 #ifdef CONFIG_IBM_EMAC_RGMII 354 EMAC_FTR_HAS_RGMII | 355 #endif 356 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 357 EMAC_FTR_NO_FLOW_CONTROL_40x | 358 #endif 359 EMAC_FTR_460EX_PHY_CLK_FIX | 360 EMAC_FTR_440EP_PHY_CLK_FIX | 361 EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 362 EMAC_FTR_APM821XX_NO_HALF_DUPLEX, 363 }; 364 365 static inline int emac_has_feature(struct emac_instance *dev, 366 unsigned long feature) 367 { 368 return (EMAC_FTRS_ALWAYS & feature) || 369 (EMAC_FTRS_POSSIBLE & dev->features & feature); 370 } 371 372 /* 373 * Various instances of the EMAC core have varying 1) number of 374 * address match slots, 2) width of the registers for handling address 375 * match slots, 3) number of registers for handling address match 376 * slots and 4) base offset for those registers. 377 * 378 * These macros and inlines handle these differences based on 379 * parameters supplied by the device structure which are, in turn, 380 * initialized based on the "compatible" entry in the device tree. 381 */ 382 383 #define EMAC4_XAHT_SLOTS_SHIFT 6 384 #define EMAC4_XAHT_WIDTH_SHIFT 4 385 386 #define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 387 #define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 388 389 /* The largest span between slots and widths above is 3 */ 390 #define EMAC_XAHT_MAX_REGS (1 << 3) 391 392 #define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) 393 #define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) 394 #define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ 395 (dev)->xaht_width_shift)) 396 397 #define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ 398 ((EMAC_XAHT_SLOTS(dev) - 1) - \ 399 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ 400 (dev)->xaht_slots_shift))) 401 402 #define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ 403 ((slot) >> (dev)->xaht_width_shift) 404 405 #define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ 406 ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ 407 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) 408 409 static inline u32 *emac_xaht_base(struct emac_instance *dev) 410 { 411 struct emac_regs __iomem *p = dev->emacp; 412 int offset; 413 414 /* The first IAHT entry always is the base of the block of 415 * IAHT and GAHT registers. 416 */ 417 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) 418 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); 419 else 420 offset = offsetof(struct emac_regs, u0.emac4.iaht1); 421 422 return (u32 *)((ptrdiff_t)p + offset); 423 } 424 425 static inline u32 *emac_gaht_base(struct emac_instance *dev) 426 { 427 /* GAHT registers always come after an identical number of 428 * IAHT registers. 429 */ 430 return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev); 431 } 432 433 static inline u32 *emac_iaht_base(struct emac_instance *dev) 434 { 435 /* IAHT registers always come before an identical number of 436 * GAHT registers. 437 */ 438 return emac_xaht_base(dev); 439 } 440 441 /* Ethtool get_regs complex data. 442 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH 443 * when available. 444 * 445 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, 446 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. 447 * Each register component is preceded with emac_ethtool_regs_subhdr. 448 * Order of the optional headers follows their relative bit posititions 449 * in emac_ethtool_regs_hdr.components 450 */ 451 #define EMAC_ETHTOOL_REGS_ZMII 0x00000001 452 #define EMAC_ETHTOOL_REGS_RGMII 0x00000002 453 #define EMAC_ETHTOOL_REGS_TAH 0x00000004 454 455 struct emac_ethtool_regs_hdr { 456 u32 components; 457 }; 458 459 struct emac_ethtool_regs_subhdr { 460 u32 version; 461 u32 index; 462 }; 463 464 #define EMAC_ETHTOOL_REGS_VER 3 465 #define EMAC4_ETHTOOL_REGS_VER 4 466 #define EMAC4SYNC_ETHTOOL_REGS_VER 5 467 468 #endif /* __IBM_NEWEMAC_CORE_H */ 469