1 /* 2 * drivers/net/ethernet/ibm/emac/core.c 3 * 4 * Driver for PowerPC 4xx on-chip ethernet controller. 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies. 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * Based on original work by 15 * Matt Porter <mporter@kernel.crashing.org> 16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 17 * Armin Kuster <akuster@mvista.com> 18 * Johnnie Peters <jpeters@mvista.com> 19 * 20 * This program is free software; you can redistribute it and/or modify it 21 * under the terms of the GNU General Public License as published by the 22 * Free Software Foundation; either version 2 of the License, or (at your 23 * option) any later version. 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <linux/sched.h> 29 #include <linux/string.h> 30 #include <linux/errno.h> 31 #include <linux/delay.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/etherdevice.h> 35 #include <linux/skbuff.h> 36 #include <linux/crc32.h> 37 #include <linux/ethtool.h> 38 #include <linux/mii.h> 39 #include <linux/bitops.h> 40 #include <linux/workqueue.h> 41 #include <linux/of.h> 42 #include <linux/of_address.h> 43 #include <linux/of_irq.h> 44 #include <linux/of_net.h> 45 #include <linux/of_mdio.h> 46 #include <linux/slab.h> 47 48 #include <asm/processor.h> 49 #include <asm/io.h> 50 #include <asm/dma.h> 51 #include <linux/uaccess.h> 52 #include <asm/dcr.h> 53 #include <asm/dcr-regs.h> 54 55 #include "core.h" 56 57 /* 58 * Lack of dma_unmap_???? calls is intentional. 59 * 60 * API-correct usage requires additional support state information to be 61 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to 62 * EMAC design (e.g. TX buffer passed from network stack can be split into 63 * several BDs, dma_map_single/dma_map_page can be used to map particular BD), 64 * maintaining such information will add additional overhead. 65 * Current DMA API implementation for 4xx processors only ensures cache coherency 66 * and dma_unmap_???? routines are empty and are likely to stay this way. 67 * I decided to omit dma_unmap_??? calls because I don't want to add additional 68 * complexity just for the sake of following some abstract API, when it doesn't 69 * add any real benefit to the driver. I understand that this decision maybe 70 * controversial, but I really tried to make code API-correct and efficient 71 * at the same time and didn't come up with code I liked :(. --ebs 72 */ 73 74 #define DRV_NAME "emac" 75 #define DRV_VERSION "3.54" 76 #define DRV_DESC "PPC 4xx OCP EMAC driver" 77 78 MODULE_DESCRIPTION(DRV_DESC); 79 MODULE_AUTHOR 80 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>"); 81 MODULE_LICENSE("GPL"); 82 83 /* minimum number of free TX descriptors required to wake up TX process */ 84 #define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4) 85 86 /* If packet size is less than this number, we allocate small skb and copy packet 87 * contents into it instead of just sending original big skb up 88 */ 89 #define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD 90 91 /* Since multiple EMACs share MDIO lines in various ways, we need 92 * to avoid re-using the same PHY ID in cases where the arch didn't 93 * setup precise phy_map entries 94 * 95 * XXX This is something that needs to be reworked as we can have multiple 96 * EMAC "sets" (multiple ASICs containing several EMACs) though we can 97 * probably require in that case to have explicit PHY IDs in the device-tree 98 */ 99 static u32 busy_phy_map; 100 static DEFINE_MUTEX(emac_phy_map_lock); 101 102 /* This is the wait queue used to wait on any event related to probe, that 103 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc... 104 */ 105 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait); 106 107 /* Having stable interface names is a doomed idea. However, it would be nice 108 * if we didn't have completely random interface names at boot too :-) It's 109 * just a matter of making everybody's life easier. Since we are doing 110 * threaded probing, it's a bit harder though. The base idea here is that 111 * we make up a list of all emacs in the device-tree before we register the 112 * driver. Every emac will then wait for the previous one in the list to 113 * initialize before itself. We should also keep that list ordered by 114 * cell_index. 115 * That list is only 4 entries long, meaning that additional EMACs don't 116 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased. 117 */ 118 119 #define EMAC_BOOT_LIST_SIZE 4 120 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE]; 121 122 /* How long should I wait for dependent devices ? */ 123 #define EMAC_PROBE_DEP_TIMEOUT (HZ * 5) 124 125 /* I don't want to litter system log with timeout errors 126 * when we have brain-damaged PHY. 127 */ 128 static inline void emac_report_timeout_error(struct emac_instance *dev, 129 const char *error) 130 { 131 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX | 132 EMAC_FTR_460EX_PHY_CLK_FIX | 133 EMAC_FTR_440EP_PHY_CLK_FIX)) 134 DBG(dev, "%s" NL, error); 135 else if (net_ratelimit()) 136 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error); 137 } 138 139 /* EMAC PHY clock workaround: 140 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, 141 * which allows controlling each EMAC clock 142 */ 143 static inline void emac_rx_clk_tx(struct emac_instance *dev) 144 { 145 #ifdef CONFIG_PPC_DCR_NATIVE 146 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 147 dcri_clrset(SDR0, SDR0_MFR, 148 0, SDR0_MFR_ECS >> dev->cell_index); 149 #endif 150 } 151 152 static inline void emac_rx_clk_default(struct emac_instance *dev) 153 { 154 #ifdef CONFIG_PPC_DCR_NATIVE 155 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX)) 156 dcri_clrset(SDR0, SDR0_MFR, 157 SDR0_MFR_ECS >> dev->cell_index, 0); 158 #endif 159 } 160 161 /* PHY polling intervals */ 162 #define PHY_POLL_LINK_ON HZ 163 #define PHY_POLL_LINK_OFF (HZ / 5) 164 165 /* Graceful stop timeouts in us. 166 * We should allow up to 1 frame time (full-duplex, ignoring collisions) 167 */ 168 #define STOP_TIMEOUT_10 1230 169 #define STOP_TIMEOUT_100 124 170 #define STOP_TIMEOUT_1000 13 171 #define STOP_TIMEOUT_1000_JUMBO 73 172 173 static unsigned char default_mcast_addr[] = { 174 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 175 }; 176 177 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */ 178 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = { 179 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum", 180 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom", 181 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu", 182 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet", 183 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error", 184 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range", 185 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun", 186 "rx_bad_packet", "rx_runt_packet", "rx_short_event", 187 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long", 188 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors", 189 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral", 190 "tx_bd_excessive_collisions", "tx_bd_late_collision", 191 "tx_bd_multple_collisions", "tx_bd_single_collision", 192 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe", 193 "tx_errors" 194 }; 195 196 static irqreturn_t emac_irq(int irq, void *dev_instance); 197 static void emac_clean_tx_ring(struct emac_instance *dev); 198 static void __emac_set_multicast_list(struct emac_instance *dev); 199 200 static inline int emac_phy_supports_gige(int phy_mode) 201 { 202 return phy_mode == PHY_MODE_GMII || 203 phy_mode == PHY_MODE_RGMII || 204 phy_mode == PHY_MODE_SGMII || 205 phy_mode == PHY_MODE_TBI || 206 phy_mode == PHY_MODE_RTBI; 207 } 208 209 static inline int emac_phy_gpcs(int phy_mode) 210 { 211 return phy_mode == PHY_MODE_SGMII || 212 phy_mode == PHY_MODE_TBI || 213 phy_mode == PHY_MODE_RTBI; 214 } 215 216 static inline void emac_tx_enable(struct emac_instance *dev) 217 { 218 struct emac_regs __iomem *p = dev->emacp; 219 u32 r; 220 221 DBG(dev, "tx_enable" NL); 222 223 r = in_be32(&p->mr0); 224 if (!(r & EMAC_MR0_TXE)) 225 out_be32(&p->mr0, r | EMAC_MR0_TXE); 226 } 227 228 static void emac_tx_disable(struct emac_instance *dev) 229 { 230 struct emac_regs __iomem *p = dev->emacp; 231 u32 r; 232 233 DBG(dev, "tx_disable" NL); 234 235 r = in_be32(&p->mr0); 236 if (r & EMAC_MR0_TXE) { 237 int n = dev->stop_timeout; 238 out_be32(&p->mr0, r & ~EMAC_MR0_TXE); 239 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) { 240 udelay(1); 241 --n; 242 } 243 if (unlikely(!n)) 244 emac_report_timeout_error(dev, "TX disable timeout"); 245 } 246 } 247 248 static void emac_rx_enable(struct emac_instance *dev) 249 { 250 struct emac_regs __iomem *p = dev->emacp; 251 u32 r; 252 253 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) 254 goto out; 255 256 DBG(dev, "rx_enable" NL); 257 258 r = in_be32(&p->mr0); 259 if (!(r & EMAC_MR0_RXE)) { 260 if (unlikely(!(r & EMAC_MR0_RXI))) { 261 /* Wait if previous async disable is still in progress */ 262 int n = dev->stop_timeout; 263 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 264 udelay(1); 265 --n; 266 } 267 if (unlikely(!n)) 268 emac_report_timeout_error(dev, 269 "RX disable timeout"); 270 } 271 out_be32(&p->mr0, r | EMAC_MR0_RXE); 272 } 273 out: 274 ; 275 } 276 277 static void emac_rx_disable(struct emac_instance *dev) 278 { 279 struct emac_regs __iomem *p = dev->emacp; 280 u32 r; 281 282 DBG(dev, "rx_disable" NL); 283 284 r = in_be32(&p->mr0); 285 if (r & EMAC_MR0_RXE) { 286 int n = dev->stop_timeout; 287 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 288 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { 289 udelay(1); 290 --n; 291 } 292 if (unlikely(!n)) 293 emac_report_timeout_error(dev, "RX disable timeout"); 294 } 295 } 296 297 static inline void emac_netif_stop(struct emac_instance *dev) 298 { 299 netif_tx_lock_bh(dev->ndev); 300 netif_addr_lock(dev->ndev); 301 dev->no_mcast = 1; 302 netif_addr_unlock(dev->ndev); 303 netif_tx_unlock_bh(dev->ndev); 304 netif_trans_update(dev->ndev); /* prevent tx timeout */ 305 mal_poll_disable(dev->mal, &dev->commac); 306 netif_tx_disable(dev->ndev); 307 } 308 309 static inline void emac_netif_start(struct emac_instance *dev) 310 { 311 netif_tx_lock_bh(dev->ndev); 312 netif_addr_lock(dev->ndev); 313 dev->no_mcast = 0; 314 if (dev->mcast_pending && netif_running(dev->ndev)) 315 __emac_set_multicast_list(dev); 316 netif_addr_unlock(dev->ndev); 317 netif_tx_unlock_bh(dev->ndev); 318 319 netif_wake_queue(dev->ndev); 320 321 /* NOTE: unconditional netif_wake_queue is only appropriate 322 * so long as all callers are assured to have free tx slots 323 * (taken from tg3... though the case where that is wrong is 324 * not terribly harmful) 325 */ 326 mal_poll_enable(dev->mal, &dev->commac); 327 } 328 329 static inline void emac_rx_disable_async(struct emac_instance *dev) 330 { 331 struct emac_regs __iomem *p = dev->emacp; 332 u32 r; 333 334 DBG(dev, "rx_disable_async" NL); 335 336 r = in_be32(&p->mr0); 337 if (r & EMAC_MR0_RXE) 338 out_be32(&p->mr0, r & ~EMAC_MR0_RXE); 339 } 340 341 static int emac_reset(struct emac_instance *dev) 342 { 343 struct emac_regs __iomem *p = dev->emacp; 344 int n = 20; 345 bool __maybe_unused try_internal_clock = false; 346 347 DBG(dev, "reset" NL); 348 349 if (!dev->reset_failed) { 350 /* 40x erratum suggests stopping RX channel before reset, 351 * we stop TX as well 352 */ 353 emac_rx_disable(dev); 354 emac_tx_disable(dev); 355 } 356 357 #ifdef CONFIG_PPC_DCR_NATIVE 358 do_retry: 359 /* 360 * PPC460EX/GT Embedded Processor Advanced User's Manual 361 * section 28.10.1 Mode Register 0 (EMACx_MR0) states: 362 * Note: The PHY must provide a TX Clk in order to perform a soft reset 363 * of the EMAC. If none is present, select the internal clock 364 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). 365 * After a soft reset, select the external clock. 366 * 367 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the 368 * ethernet cable is not attached. This causes the reset to timeout 369 * and the PHY detection code in emac_init_phy() is unable to 370 * communicate and detect the AR8035-A PHY. As a result, the emac 371 * driver bails out early and the user has no ethernet. 372 * In order to stay compatible with existing configurations, the 373 * driver will temporarily switch to the internal clock, after 374 * the first reset fails. 375 */ 376 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 377 if (try_internal_clock || (dev->phy_address == 0xffffffff && 378 dev->phy_map == 0xffffffff)) { 379 /* No PHY: select internal loop clock before reset */ 380 dcri_clrset(SDR0, SDR0_ETH_CFG, 381 0, SDR0_ETH_CFG_ECS << dev->cell_index); 382 } else { 383 /* PHY present: select external clock before reset */ 384 dcri_clrset(SDR0, SDR0_ETH_CFG, 385 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 386 } 387 } 388 #endif 389 390 out_be32(&p->mr0, EMAC_MR0_SRST); 391 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n) 392 --n; 393 394 #ifdef CONFIG_PPC_DCR_NATIVE 395 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) { 396 if (!n && !try_internal_clock) { 397 /* first attempt has timed out. */ 398 n = 20; 399 try_internal_clock = true; 400 goto do_retry; 401 } 402 403 if (try_internal_clock || (dev->phy_address == 0xffffffff && 404 dev->phy_map == 0xffffffff)) { 405 /* No PHY: restore external clock source after reset */ 406 dcri_clrset(SDR0, SDR0_ETH_CFG, 407 SDR0_ETH_CFG_ECS << dev->cell_index, 0); 408 } 409 } 410 #endif 411 412 if (n) { 413 dev->reset_failed = 0; 414 return 0; 415 } else { 416 emac_report_timeout_error(dev, "reset timeout"); 417 dev->reset_failed = 1; 418 return -ETIMEDOUT; 419 } 420 } 421 422 static void emac_hash_mc(struct emac_instance *dev) 423 { 424 const int regs = EMAC_XAHT_REGS(dev); 425 u32 *gaht_base = emac_gaht_base(dev); 426 u32 gaht_temp[regs]; 427 struct netdev_hw_addr *ha; 428 int i; 429 430 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev)); 431 432 memset(gaht_temp, 0, sizeof (gaht_temp)); 433 434 netdev_for_each_mc_addr(ha, dev->ndev) { 435 int slot, reg, mask; 436 DBG2(dev, "mc %pM" NL, ha->addr); 437 438 slot = EMAC_XAHT_CRC_TO_SLOT(dev, 439 ether_crc(ETH_ALEN, ha->addr)); 440 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot); 441 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot); 442 443 gaht_temp[reg] |= mask; 444 } 445 446 for (i = 0; i < regs; i++) 447 out_be32(gaht_base + i, gaht_temp[i]); 448 } 449 450 static inline u32 emac_iff2rmr(struct net_device *ndev) 451 { 452 struct emac_instance *dev = netdev_priv(ndev); 453 u32 r; 454 455 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE; 456 457 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 458 r |= EMAC4_RMR_BASE; 459 else 460 r |= EMAC_RMR_BASE; 461 462 if (ndev->flags & IFF_PROMISC) 463 r |= EMAC_RMR_PME; 464 else if (ndev->flags & IFF_ALLMULTI || 465 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev))) 466 r |= EMAC_RMR_PMME; 467 else if (!netdev_mc_empty(ndev)) 468 r |= EMAC_RMR_MAE; 469 470 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 471 r &= ~EMAC4_RMR_MJS_MASK; 472 r |= EMAC4_RMR_MJS(ndev->mtu); 473 } 474 475 return r; 476 } 477 478 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 479 { 480 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT; 481 482 DBG2(dev, "__emac_calc_base_mr1" NL); 483 484 switch(tx_size) { 485 case 2048: 486 ret |= EMAC_MR1_TFS_2K; 487 break; 488 default: 489 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 490 dev->ndev->name, tx_size); 491 } 492 493 switch(rx_size) { 494 case 16384: 495 ret |= EMAC_MR1_RFS_16K; 496 break; 497 case 4096: 498 ret |= EMAC_MR1_RFS_4K; 499 break; 500 default: 501 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 502 dev->ndev->name, rx_size); 503 } 504 505 return ret; 506 } 507 508 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 509 { 510 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR | 511 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000); 512 513 DBG2(dev, "__emac4_calc_base_mr1" NL); 514 515 switch(tx_size) { 516 case 16384: 517 ret |= EMAC4_MR1_TFS_16K; 518 break; 519 case 4096: 520 ret |= EMAC4_MR1_TFS_4K; 521 break; 522 case 2048: 523 ret |= EMAC4_MR1_TFS_2K; 524 break; 525 default: 526 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n", 527 dev->ndev->name, tx_size); 528 } 529 530 switch(rx_size) { 531 case 16384: 532 ret |= EMAC4_MR1_RFS_16K; 533 break; 534 case 4096: 535 ret |= EMAC4_MR1_RFS_4K; 536 break; 537 case 2048: 538 ret |= EMAC4_MR1_RFS_2K; 539 break; 540 default: 541 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n", 542 dev->ndev->name, rx_size); 543 } 544 545 return ret; 546 } 547 548 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size) 549 { 550 return emac_has_feature(dev, EMAC_FTR_EMAC4) ? 551 __emac4_calc_base_mr1(dev, tx_size, rx_size) : 552 __emac_calc_base_mr1(dev, tx_size, rx_size); 553 } 554 555 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size) 556 { 557 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 558 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4; 559 else 560 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT; 561 } 562 563 static inline u32 emac_calc_rwmr(struct emac_instance *dev, 564 unsigned int low, unsigned int high) 565 { 566 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 567 return (low << 22) | ( (high & 0x3ff) << 6); 568 else 569 return (low << 23) | ( (high & 0x1ff) << 7); 570 } 571 572 static int emac_configure(struct emac_instance *dev) 573 { 574 struct emac_regs __iomem *p = dev->emacp; 575 struct net_device *ndev = dev->ndev; 576 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev); 577 u32 r, mr1 = 0; 578 579 DBG(dev, "configure" NL); 580 581 if (!link) { 582 out_be32(&p->mr1, in_be32(&p->mr1) 583 | EMAC_MR1_FDE | EMAC_MR1_ILE); 584 udelay(100); 585 } else if (emac_reset(dev) < 0) 586 return -ETIMEDOUT; 587 588 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 589 tah_reset(dev->tah_dev); 590 591 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n", 592 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause); 593 594 /* Default fifo sizes */ 595 tx_size = dev->tx_fifo_size; 596 rx_size = dev->rx_fifo_size; 597 598 /* No link, force loopback */ 599 if (!link) 600 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE; 601 602 /* Check for full duplex */ 603 else if (dev->phy.duplex == DUPLEX_FULL) 604 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001; 605 606 /* Adjust fifo sizes, mr1 and timeouts based on link speed */ 607 dev->stop_timeout = STOP_TIMEOUT_10; 608 switch (dev->phy.speed) { 609 case SPEED_1000: 610 if (emac_phy_gpcs(dev->phy.mode)) { 611 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA( 612 (dev->phy.gpcs_address != 0xffffffff) ? 613 dev->phy.gpcs_address : dev->phy.address); 614 615 /* Put some arbitrary OUI, Manuf & Rev IDs so we can 616 * identify this GPCS PHY later. 617 */ 618 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef); 619 } else 620 mr1 |= EMAC_MR1_MF_1000; 621 622 /* Extended fifo sizes */ 623 tx_size = dev->tx_fifo_size_gige; 624 rx_size = dev->rx_fifo_size_gige; 625 626 if (dev->ndev->mtu > ETH_DATA_LEN) { 627 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 628 mr1 |= EMAC4_MR1_JPSM; 629 else 630 mr1 |= EMAC_MR1_JPSM; 631 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO; 632 } else 633 dev->stop_timeout = STOP_TIMEOUT_1000; 634 break; 635 case SPEED_100: 636 mr1 |= EMAC_MR1_MF_100; 637 dev->stop_timeout = STOP_TIMEOUT_100; 638 break; 639 default: /* make gcc happy */ 640 break; 641 } 642 643 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 644 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port, 645 dev->phy.speed); 646 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 647 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed); 648 649 /* on 40x erratum forces us to NOT use integrated flow control, 650 * let's hope it works on 44x ;) 651 */ 652 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) && 653 dev->phy.duplex == DUPLEX_FULL) { 654 if (dev->phy.pause) 655 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP; 656 else if (dev->phy.asym_pause) 657 mr1 |= EMAC_MR1_APP; 658 } 659 660 /* Add base settings & fifo sizes & program MR1 */ 661 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size); 662 out_be32(&p->mr1, mr1); 663 664 /* Set individual MAC address */ 665 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 666 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 667 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 668 ndev->dev_addr[5]); 669 670 /* VLAN Tag Protocol ID */ 671 out_be32(&p->vtpid, 0x8100); 672 673 /* Receive mode register */ 674 r = emac_iff2rmr(ndev); 675 if (r & EMAC_RMR_MAE) 676 emac_hash_mc(dev); 677 out_be32(&p->rmr, r); 678 679 /* FIFOs thresholds */ 680 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 681 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 682 tx_size / 2 / dev->fifo_entry_size); 683 else 684 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1, 685 tx_size / 2 / dev->fifo_entry_size); 686 out_be32(&p->tmr1, r); 687 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2)); 688 689 /* PAUSE frame is sent when RX FIFO reaches its high-water mark, 690 there should be still enough space in FIFO to allow the our link 691 partner time to process this frame and also time to send PAUSE 692 frame itself. 693 694 Here is the worst case scenario for the RX FIFO "headroom" 695 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap): 696 697 1) One maximum-length frame on TX 1522 bytes 698 2) One PAUSE frame time 64 bytes 699 3) PAUSE frame decode time allowance 64 bytes 700 4) One maximum-length frame on RX 1522 bytes 701 5) Round-trip propagation delay of the link (100Mb) 15 bytes 702 ---------- 703 3187 bytes 704 705 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes) 706 low-water mark to RX_FIFO_SIZE / 8 (512 bytes) 707 */ 708 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size, 709 rx_size / 4 / dev->fifo_entry_size); 710 out_be32(&p->rwmr, r); 711 712 /* Set PAUSE timer to the maximum */ 713 out_be32(&p->ptr, 0xffff); 714 715 /* IRQ sources */ 716 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE | 717 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE | 718 EMAC_ISR_IRE | EMAC_ISR_TE; 719 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 720 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE | 721 EMAC4_ISR_RXOE | */; 722 out_be32(&p->iser, r); 723 724 /* We need to take GPCS PHY out of isolate mode after EMAC reset */ 725 if (emac_phy_gpcs(dev->phy.mode)) { 726 if (dev->phy.gpcs_address != 0xffffffff) 727 emac_mii_reset_gpcs(&dev->phy); 728 else 729 emac_mii_reset_phy(&dev->phy); 730 } 731 732 return 0; 733 } 734 735 static void emac_reinitialize(struct emac_instance *dev) 736 { 737 DBG(dev, "reinitialize" NL); 738 739 emac_netif_stop(dev); 740 if (!emac_configure(dev)) { 741 emac_tx_enable(dev); 742 emac_rx_enable(dev); 743 } 744 emac_netif_start(dev); 745 } 746 747 static void emac_full_tx_reset(struct emac_instance *dev) 748 { 749 DBG(dev, "full_tx_reset" NL); 750 751 emac_tx_disable(dev); 752 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 753 emac_clean_tx_ring(dev); 754 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0; 755 756 emac_configure(dev); 757 758 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 759 emac_tx_enable(dev); 760 emac_rx_enable(dev); 761 } 762 763 static void emac_reset_work(struct work_struct *work) 764 { 765 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work); 766 767 DBG(dev, "reset_work" NL); 768 769 mutex_lock(&dev->link_lock); 770 if (dev->opened) { 771 emac_netif_stop(dev); 772 emac_full_tx_reset(dev); 773 emac_netif_start(dev); 774 } 775 mutex_unlock(&dev->link_lock); 776 } 777 778 static void emac_tx_timeout(struct net_device *ndev) 779 { 780 struct emac_instance *dev = netdev_priv(ndev); 781 782 DBG(dev, "tx_timeout" NL); 783 784 schedule_work(&dev->reset_work); 785 } 786 787 788 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr) 789 { 790 int done = !!(stacr & EMAC_STACR_OC); 791 792 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 793 done = !done; 794 795 return done; 796 }; 797 798 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg) 799 { 800 struct emac_regs __iomem *p = dev->emacp; 801 u32 r = 0; 802 int n, err = -ETIMEDOUT; 803 804 mutex_lock(&dev->mdio_lock); 805 806 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg); 807 808 /* Enable proper MDIO port */ 809 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 810 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 811 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 812 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 813 814 /* Wait for management interface to become idle */ 815 n = 20; 816 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 817 udelay(1); 818 if (!--n) { 819 DBG2(dev, " -> timeout wait idle\n"); 820 goto bail; 821 } 822 } 823 824 /* Issue read command */ 825 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 826 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 827 else 828 r = EMAC_STACR_BASE(dev->opb_bus_freq); 829 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 830 r |= EMAC_STACR_OC; 831 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 832 r |= EMACX_STACR_STAC_READ; 833 else 834 r |= EMAC_STACR_STAC_READ; 835 r |= (reg & EMAC_STACR_PRA_MASK) 836 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT); 837 out_be32(&p->stacr, r); 838 839 /* Wait for read to complete */ 840 n = 200; 841 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) { 842 udelay(1); 843 if (!--n) { 844 DBG2(dev, " -> timeout wait complete\n"); 845 goto bail; 846 } 847 } 848 849 if (unlikely(r & EMAC_STACR_PHYE)) { 850 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg); 851 err = -EREMOTEIO; 852 goto bail; 853 } 854 855 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK); 856 857 DBG2(dev, "mdio_read -> %04x" NL, r); 858 err = 0; 859 bail: 860 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 861 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 862 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 863 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 864 mutex_unlock(&dev->mdio_lock); 865 866 return err == 0 ? r : err; 867 } 868 869 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg, 870 u16 val) 871 { 872 struct emac_regs __iomem *p = dev->emacp; 873 u32 r = 0; 874 int n, err = -ETIMEDOUT; 875 876 mutex_lock(&dev->mdio_lock); 877 878 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); 879 880 /* Enable proper MDIO port */ 881 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 882 zmii_get_mdio(dev->zmii_dev, dev->zmii_port); 883 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 884 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port); 885 886 /* Wait for management interface to be idle */ 887 n = 20; 888 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 889 udelay(1); 890 if (!--n) { 891 DBG2(dev, " -> timeout wait idle\n"); 892 goto bail; 893 } 894 } 895 896 /* Issue write command */ 897 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 898 r = EMAC4_STACR_BASE(dev->opb_bus_freq); 899 else 900 r = EMAC_STACR_BASE(dev->opb_bus_freq); 901 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT)) 902 r |= EMAC_STACR_OC; 903 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR)) 904 r |= EMACX_STACR_STAC_WRITE; 905 else 906 r |= EMAC_STACR_STAC_WRITE; 907 r |= (reg & EMAC_STACR_PRA_MASK) | 908 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | 909 (val << EMAC_STACR_PHYD_SHIFT); 910 out_be32(&p->stacr, r); 911 912 /* Wait for write to complete */ 913 n = 200; 914 while (!emac_phy_done(dev, in_be32(&p->stacr))) { 915 udelay(1); 916 if (!--n) { 917 DBG2(dev, " -> timeout wait complete\n"); 918 goto bail; 919 } 920 } 921 err = 0; 922 bail: 923 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 924 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port); 925 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 926 zmii_put_mdio(dev->zmii_dev, dev->zmii_port); 927 mutex_unlock(&dev->mdio_lock); 928 } 929 930 static int emac_mdio_read(struct net_device *ndev, int id, int reg) 931 { 932 struct emac_instance *dev = netdev_priv(ndev); 933 int res; 934 935 res = __emac_mdio_read((dev->mdio_instance && 936 dev->phy.gpcs_address != id) ? 937 dev->mdio_instance : dev, 938 (u8) id, (u8) reg); 939 return res; 940 } 941 942 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) 943 { 944 struct emac_instance *dev = netdev_priv(ndev); 945 946 __emac_mdio_write((dev->mdio_instance && 947 dev->phy.gpcs_address != id) ? 948 dev->mdio_instance : dev, 949 (u8) id, (u8) reg, (u16) val); 950 } 951 952 /* Tx lock BH */ 953 static void __emac_set_multicast_list(struct emac_instance *dev) 954 { 955 struct emac_regs __iomem *p = dev->emacp; 956 u32 rmr = emac_iff2rmr(dev->ndev); 957 958 DBG(dev, "__multicast %08x" NL, rmr); 959 960 /* I decided to relax register access rules here to avoid 961 * full EMAC reset. 962 * 963 * There is a real problem with EMAC4 core if we use MWSW_001 bit 964 * in MR1 register and do a full EMAC reset. 965 * One TX BD status update is delayed and, after EMAC reset, it 966 * never happens, resulting in TX hung (it'll be recovered by TX 967 * timeout handler eventually, but this is just gross). 968 * So we either have to do full TX reset or try to cheat here :) 969 * 970 * The only required change is to RX mode register, so I *think* all 971 * we need is just to stop RX channel. This seems to work on all 972 * tested SoCs. --ebs 973 * 974 * If we need the full reset, we might just trigger the workqueue 975 * and do it async... a bit nasty but should work --BenH 976 */ 977 dev->mcast_pending = 0; 978 emac_rx_disable(dev); 979 if (rmr & EMAC_RMR_MAE) 980 emac_hash_mc(dev); 981 out_be32(&p->rmr, rmr); 982 emac_rx_enable(dev); 983 } 984 985 /* Tx lock BH */ 986 static void emac_set_multicast_list(struct net_device *ndev) 987 { 988 struct emac_instance *dev = netdev_priv(ndev); 989 990 DBG(dev, "multicast" NL); 991 992 BUG_ON(!netif_running(dev->ndev)); 993 994 if (dev->no_mcast) { 995 dev->mcast_pending = 1; 996 return; 997 } 998 999 mutex_lock(&dev->link_lock); 1000 __emac_set_multicast_list(dev); 1001 mutex_unlock(&dev->link_lock); 1002 } 1003 1004 static int emac_set_mac_address(struct net_device *ndev, void *sa) 1005 { 1006 struct emac_instance *dev = netdev_priv(ndev); 1007 struct sockaddr *addr = sa; 1008 struct emac_regs __iomem *p = dev->emacp; 1009 1010 if (!is_valid_ether_addr(addr->sa_data)) 1011 return -EADDRNOTAVAIL; 1012 1013 mutex_lock(&dev->link_lock); 1014 1015 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1016 1017 emac_rx_disable(dev); 1018 emac_tx_disable(dev); 1019 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]); 1020 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) | 1021 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) | 1022 ndev->dev_addr[5]); 1023 emac_tx_enable(dev); 1024 emac_rx_enable(dev); 1025 1026 mutex_unlock(&dev->link_lock); 1027 1028 return 0; 1029 } 1030 1031 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu) 1032 { 1033 int rx_sync_size = emac_rx_sync_size(new_mtu); 1034 int rx_skb_size = emac_rx_skb_size(new_mtu); 1035 int i, ret = 0; 1036 int mr1_jumbo_bit_change = 0; 1037 1038 mutex_lock(&dev->link_lock); 1039 emac_netif_stop(dev); 1040 emac_rx_disable(dev); 1041 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1042 1043 if (dev->rx_sg_skb) { 1044 ++dev->estats.rx_dropped_resize; 1045 dev_kfree_skb(dev->rx_sg_skb); 1046 dev->rx_sg_skb = NULL; 1047 } 1048 1049 /* Make a first pass over RX ring and mark BDs ready, dropping 1050 * non-processed packets on the way. We need this as a separate pass 1051 * to simplify error recovery in the case of allocation failure later. 1052 */ 1053 for (i = 0; i < NUM_RX_BUFF; ++i) { 1054 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST) 1055 ++dev->estats.rx_dropped_resize; 1056 1057 dev->rx_desc[i].data_len = 0; 1058 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | 1059 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1060 } 1061 1062 /* Reallocate RX ring only if bigger skb buffers are required */ 1063 if (rx_skb_size <= dev->rx_skb_size) 1064 goto skip; 1065 1066 /* Second pass, allocate new skbs */ 1067 for (i = 0; i < NUM_RX_BUFF; ++i) { 1068 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC); 1069 if (!skb) { 1070 ret = -ENOMEM; 1071 goto oom; 1072 } 1073 1074 BUG_ON(!dev->rx_skb[i]); 1075 dev_kfree_skb(dev->rx_skb[i]); 1076 1077 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2); 1078 dev->rx_desc[i].data_ptr = 1079 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size, 1080 DMA_FROM_DEVICE) + 2; 1081 dev->rx_skb[i] = skb; 1082 } 1083 skip: 1084 /* Check if we need to change "Jumbo" bit in MR1 */ 1085 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) { 1086 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) || 1087 (dev->ndev->mtu > ETH_DATA_LEN); 1088 } else { 1089 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^ 1090 (dev->ndev->mtu > ETH_DATA_LEN); 1091 } 1092 1093 if (mr1_jumbo_bit_change) { 1094 /* This is to prevent starting RX channel in emac_rx_enable() */ 1095 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1096 1097 dev->ndev->mtu = new_mtu; 1098 emac_full_tx_reset(dev); 1099 } 1100 1101 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu)); 1102 oom: 1103 /* Restart RX */ 1104 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1105 dev->rx_slot = 0; 1106 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1107 emac_rx_enable(dev); 1108 emac_netif_start(dev); 1109 mutex_unlock(&dev->link_lock); 1110 1111 return ret; 1112 } 1113 1114 /* Process ctx, rtnl_lock semaphore */ 1115 static int emac_change_mtu(struct net_device *ndev, int new_mtu) 1116 { 1117 struct emac_instance *dev = netdev_priv(ndev); 1118 int ret = 0; 1119 1120 DBG(dev, "change_mtu(%d)" NL, new_mtu); 1121 1122 if (netif_running(ndev)) { 1123 /* Check if we really need to reinitialize RX ring */ 1124 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu)) 1125 ret = emac_resize_rx_ring(dev, new_mtu); 1126 } 1127 1128 if (!ret) { 1129 ndev->mtu = new_mtu; 1130 dev->rx_skb_size = emac_rx_skb_size(new_mtu); 1131 dev->rx_sync_size = emac_rx_sync_size(new_mtu); 1132 } 1133 1134 return ret; 1135 } 1136 1137 static void emac_clean_tx_ring(struct emac_instance *dev) 1138 { 1139 int i; 1140 1141 for (i = 0; i < NUM_TX_BUFF; ++i) { 1142 if (dev->tx_skb[i]) { 1143 dev_kfree_skb(dev->tx_skb[i]); 1144 dev->tx_skb[i] = NULL; 1145 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY) 1146 ++dev->estats.tx_dropped; 1147 } 1148 dev->tx_desc[i].ctrl = 0; 1149 dev->tx_desc[i].data_ptr = 0; 1150 } 1151 } 1152 1153 static void emac_clean_rx_ring(struct emac_instance *dev) 1154 { 1155 int i; 1156 1157 for (i = 0; i < NUM_RX_BUFF; ++i) 1158 if (dev->rx_skb[i]) { 1159 dev->rx_desc[i].ctrl = 0; 1160 dev_kfree_skb(dev->rx_skb[i]); 1161 dev->rx_skb[i] = NULL; 1162 dev->rx_desc[i].data_ptr = 0; 1163 } 1164 1165 if (dev->rx_sg_skb) { 1166 dev_kfree_skb(dev->rx_sg_skb); 1167 dev->rx_sg_skb = NULL; 1168 } 1169 } 1170 1171 static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot, 1172 gfp_t flags) 1173 { 1174 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags); 1175 if (unlikely(!skb)) 1176 return -ENOMEM; 1177 1178 dev->rx_skb[slot] = skb; 1179 dev->rx_desc[slot].data_len = 0; 1180 1181 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2); 1182 dev->rx_desc[slot].data_ptr = 1183 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size, 1184 DMA_FROM_DEVICE) + 2; 1185 wmb(); 1186 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1187 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1188 1189 return 0; 1190 } 1191 1192 static void emac_print_link_status(struct emac_instance *dev) 1193 { 1194 if (netif_carrier_ok(dev->ndev)) 1195 printk(KERN_INFO "%s: link is up, %d %s%s\n", 1196 dev->ndev->name, dev->phy.speed, 1197 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX", 1198 dev->phy.pause ? ", pause enabled" : 1199 dev->phy.asym_pause ? ", asymmetric pause enabled" : ""); 1200 else 1201 printk(KERN_INFO "%s: link is down\n", dev->ndev->name); 1202 } 1203 1204 /* Process ctx, rtnl_lock semaphore */ 1205 static int emac_open(struct net_device *ndev) 1206 { 1207 struct emac_instance *dev = netdev_priv(ndev); 1208 int err, i; 1209 1210 DBG(dev, "open" NL); 1211 1212 /* Setup error IRQ handler */ 1213 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev); 1214 if (err) { 1215 printk(KERN_ERR "%s: failed to request IRQ %d\n", 1216 ndev->name, dev->emac_irq); 1217 return err; 1218 } 1219 1220 /* Allocate RX ring */ 1221 for (i = 0; i < NUM_RX_BUFF; ++i) 1222 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) { 1223 printk(KERN_ERR "%s: failed to allocate RX ring\n", 1224 ndev->name); 1225 goto oom; 1226 } 1227 1228 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0; 1229 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1230 dev->rx_sg_skb = NULL; 1231 1232 mutex_lock(&dev->link_lock); 1233 dev->opened = 1; 1234 1235 /* Start PHY polling now. 1236 */ 1237 if (dev->phy.address >= 0) { 1238 int link_poll_interval; 1239 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1240 dev->phy.def->ops->read_link(&dev->phy); 1241 emac_rx_clk_default(dev); 1242 netif_carrier_on(dev->ndev); 1243 link_poll_interval = PHY_POLL_LINK_ON; 1244 } else { 1245 emac_rx_clk_tx(dev); 1246 netif_carrier_off(dev->ndev); 1247 link_poll_interval = PHY_POLL_LINK_OFF; 1248 } 1249 dev->link_polling = 1; 1250 wmb(); 1251 schedule_delayed_work(&dev->link_work, link_poll_interval); 1252 emac_print_link_status(dev); 1253 } else 1254 netif_carrier_on(dev->ndev); 1255 1256 /* Required for Pause packet support in EMAC */ 1257 dev_mc_add_global(ndev, default_mcast_addr); 1258 1259 emac_configure(dev); 1260 mal_poll_add(dev->mal, &dev->commac); 1261 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); 1262 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu)); 1263 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1264 emac_tx_enable(dev); 1265 emac_rx_enable(dev); 1266 emac_netif_start(dev); 1267 1268 mutex_unlock(&dev->link_lock); 1269 1270 return 0; 1271 oom: 1272 emac_clean_rx_ring(dev); 1273 free_irq(dev->emac_irq, dev); 1274 1275 return -ENOMEM; 1276 } 1277 1278 /* BHs disabled */ 1279 #if 0 1280 static int emac_link_differs(struct emac_instance *dev) 1281 { 1282 u32 r = in_be32(&dev->emacp->mr1); 1283 1284 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF; 1285 int speed, pause, asym_pause; 1286 1287 if (r & EMAC_MR1_MF_1000) 1288 speed = SPEED_1000; 1289 else if (r & EMAC_MR1_MF_100) 1290 speed = SPEED_100; 1291 else 1292 speed = SPEED_10; 1293 1294 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) { 1295 case (EMAC_MR1_EIFC | EMAC_MR1_APP): 1296 pause = 1; 1297 asym_pause = 0; 1298 break; 1299 case EMAC_MR1_APP: 1300 pause = 0; 1301 asym_pause = 1; 1302 break; 1303 default: 1304 pause = asym_pause = 0; 1305 } 1306 return speed != dev->phy.speed || duplex != dev->phy.duplex || 1307 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause; 1308 } 1309 #endif 1310 1311 static void emac_link_timer(struct work_struct *work) 1312 { 1313 struct emac_instance *dev = 1314 container_of(to_delayed_work(work), 1315 struct emac_instance, link_work); 1316 int link_poll_interval; 1317 1318 mutex_lock(&dev->link_lock); 1319 DBG2(dev, "link timer" NL); 1320 1321 if (!dev->opened) 1322 goto bail; 1323 1324 if (dev->phy.def->ops->poll_link(&dev->phy)) { 1325 if (!netif_carrier_ok(dev->ndev)) { 1326 emac_rx_clk_default(dev); 1327 /* Get new link parameters */ 1328 dev->phy.def->ops->read_link(&dev->phy); 1329 1330 netif_carrier_on(dev->ndev); 1331 emac_netif_stop(dev); 1332 emac_full_tx_reset(dev); 1333 emac_netif_start(dev); 1334 emac_print_link_status(dev); 1335 } 1336 link_poll_interval = PHY_POLL_LINK_ON; 1337 } else { 1338 if (netif_carrier_ok(dev->ndev)) { 1339 emac_rx_clk_tx(dev); 1340 netif_carrier_off(dev->ndev); 1341 netif_tx_disable(dev->ndev); 1342 emac_reinitialize(dev); 1343 emac_print_link_status(dev); 1344 } 1345 link_poll_interval = PHY_POLL_LINK_OFF; 1346 } 1347 schedule_delayed_work(&dev->link_work, link_poll_interval); 1348 bail: 1349 mutex_unlock(&dev->link_lock); 1350 } 1351 1352 static void emac_force_link_update(struct emac_instance *dev) 1353 { 1354 netif_carrier_off(dev->ndev); 1355 smp_rmb(); 1356 if (dev->link_polling) { 1357 cancel_delayed_work_sync(&dev->link_work); 1358 if (dev->link_polling) 1359 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF); 1360 } 1361 } 1362 1363 /* Process ctx, rtnl_lock semaphore */ 1364 static int emac_close(struct net_device *ndev) 1365 { 1366 struct emac_instance *dev = netdev_priv(ndev); 1367 1368 DBG(dev, "close" NL); 1369 1370 if (dev->phy.address >= 0) { 1371 dev->link_polling = 0; 1372 cancel_delayed_work_sync(&dev->link_work); 1373 } 1374 mutex_lock(&dev->link_lock); 1375 emac_netif_stop(dev); 1376 dev->opened = 0; 1377 mutex_unlock(&dev->link_lock); 1378 1379 emac_rx_disable(dev); 1380 emac_tx_disable(dev); 1381 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan); 1382 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan); 1383 mal_poll_del(dev->mal, &dev->commac); 1384 1385 emac_clean_tx_ring(dev); 1386 emac_clean_rx_ring(dev); 1387 1388 free_irq(dev->emac_irq, dev); 1389 1390 netif_carrier_off(ndev); 1391 1392 return 0; 1393 } 1394 1395 static inline u16 emac_tx_csum(struct emac_instance *dev, 1396 struct sk_buff *skb) 1397 { 1398 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 1399 (skb->ip_summed == CHECKSUM_PARTIAL)) { 1400 ++dev->stats.tx_packets_csum; 1401 return EMAC_TX_CTRL_TAH_CSUM; 1402 } 1403 return 0; 1404 } 1405 1406 static inline int emac_xmit_finish(struct emac_instance *dev, int len) 1407 { 1408 struct emac_regs __iomem *p = dev->emacp; 1409 struct net_device *ndev = dev->ndev; 1410 1411 /* Send the packet out. If the if makes a significant perf 1412 * difference, then we can store the TMR0 value in "dev" 1413 * instead 1414 */ 1415 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) 1416 out_be32(&p->tmr0, EMAC4_TMR0_XMIT); 1417 else 1418 out_be32(&p->tmr0, EMAC_TMR0_XMIT); 1419 1420 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) { 1421 netif_stop_queue(ndev); 1422 DBG2(dev, "stopped TX queue" NL); 1423 } 1424 1425 netif_trans_update(ndev); 1426 ++dev->stats.tx_packets; 1427 dev->stats.tx_bytes += len; 1428 1429 return NETDEV_TX_OK; 1430 } 1431 1432 /* Tx lock BH */ 1433 static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1434 { 1435 struct emac_instance *dev = netdev_priv(ndev); 1436 unsigned int len = skb->len; 1437 int slot; 1438 1439 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1440 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb); 1441 1442 slot = dev->tx_slot++; 1443 if (dev->tx_slot == NUM_TX_BUFF) { 1444 dev->tx_slot = 0; 1445 ctrl |= MAL_TX_CTRL_WRAP; 1446 } 1447 1448 DBG2(dev, "xmit(%u) %d" NL, len, slot); 1449 1450 dev->tx_skb[slot] = skb; 1451 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev, 1452 skb->data, len, 1453 DMA_TO_DEVICE); 1454 dev->tx_desc[slot].data_len = (u16) len; 1455 wmb(); 1456 dev->tx_desc[slot].ctrl = ctrl; 1457 1458 return emac_xmit_finish(dev, len); 1459 } 1460 1461 static inline int emac_xmit_split(struct emac_instance *dev, int slot, 1462 u32 pd, int len, int last, u16 base_ctrl) 1463 { 1464 while (1) { 1465 u16 ctrl = base_ctrl; 1466 int chunk = min(len, MAL_MAX_TX_SIZE); 1467 len -= chunk; 1468 1469 slot = (slot + 1) % NUM_TX_BUFF; 1470 1471 if (last && !len) 1472 ctrl |= MAL_TX_CTRL_LAST; 1473 if (slot == NUM_TX_BUFF - 1) 1474 ctrl |= MAL_TX_CTRL_WRAP; 1475 1476 dev->tx_skb[slot] = NULL; 1477 dev->tx_desc[slot].data_ptr = pd; 1478 dev->tx_desc[slot].data_len = (u16) chunk; 1479 dev->tx_desc[slot].ctrl = ctrl; 1480 ++dev->tx_cnt; 1481 1482 if (!len) 1483 break; 1484 1485 pd += chunk; 1486 } 1487 return slot; 1488 } 1489 1490 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */ 1491 static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev) 1492 { 1493 struct emac_instance *dev = netdev_priv(ndev); 1494 int nr_frags = skb_shinfo(skb)->nr_frags; 1495 int len = skb->len, chunk; 1496 int slot, i; 1497 u16 ctrl; 1498 u32 pd; 1499 1500 /* This is common "fast" path */ 1501 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE)) 1502 return emac_start_xmit(skb, ndev); 1503 1504 len -= skb->data_len; 1505 1506 /* Note, this is only an *estimation*, we can still run out of empty 1507 * slots because of the additional fragmentation into 1508 * MAL_MAX_TX_SIZE-sized chunks 1509 */ 1510 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF)) 1511 goto stop_queue; 1512 1513 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY | 1514 emac_tx_csum(dev, skb); 1515 slot = dev->tx_slot; 1516 1517 /* skb data */ 1518 dev->tx_skb[slot] = NULL; 1519 chunk = min(len, MAL_MAX_TX_SIZE); 1520 dev->tx_desc[slot].data_ptr = pd = 1521 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE); 1522 dev->tx_desc[slot].data_len = (u16) chunk; 1523 len -= chunk; 1524 if (unlikely(len)) 1525 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags, 1526 ctrl); 1527 /* skb fragments */ 1528 for (i = 0; i < nr_frags; ++i) { 1529 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 1530 len = skb_frag_size(frag); 1531 1532 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF)) 1533 goto undo_frame; 1534 1535 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len, 1536 DMA_TO_DEVICE); 1537 1538 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1, 1539 ctrl); 1540 } 1541 1542 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot); 1543 1544 /* Attach skb to the last slot so we don't release it too early */ 1545 dev->tx_skb[slot] = skb; 1546 1547 /* Send the packet out */ 1548 if (dev->tx_slot == NUM_TX_BUFF - 1) 1549 ctrl |= MAL_TX_CTRL_WRAP; 1550 wmb(); 1551 dev->tx_desc[dev->tx_slot].ctrl = ctrl; 1552 dev->tx_slot = (slot + 1) % NUM_TX_BUFF; 1553 1554 return emac_xmit_finish(dev, skb->len); 1555 1556 undo_frame: 1557 /* Well, too bad. Our previous estimation was overly optimistic. 1558 * Undo everything. 1559 */ 1560 while (slot != dev->tx_slot) { 1561 dev->tx_desc[slot].ctrl = 0; 1562 --dev->tx_cnt; 1563 if (--slot < 0) 1564 slot = NUM_TX_BUFF - 1; 1565 } 1566 ++dev->estats.tx_undo; 1567 1568 stop_queue: 1569 netif_stop_queue(ndev); 1570 DBG2(dev, "stopped TX queue" NL); 1571 return NETDEV_TX_BUSY; 1572 } 1573 1574 /* Tx lock BHs */ 1575 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl) 1576 { 1577 struct emac_error_stats *st = &dev->estats; 1578 1579 DBG(dev, "BD TX error %04x" NL, ctrl); 1580 1581 ++st->tx_bd_errors; 1582 if (ctrl & EMAC_TX_ST_BFCS) 1583 ++st->tx_bd_bad_fcs; 1584 if (ctrl & EMAC_TX_ST_LCS) 1585 ++st->tx_bd_carrier_loss; 1586 if (ctrl & EMAC_TX_ST_ED) 1587 ++st->tx_bd_excessive_deferral; 1588 if (ctrl & EMAC_TX_ST_EC) 1589 ++st->tx_bd_excessive_collisions; 1590 if (ctrl & EMAC_TX_ST_LC) 1591 ++st->tx_bd_late_collision; 1592 if (ctrl & EMAC_TX_ST_MC) 1593 ++st->tx_bd_multple_collisions; 1594 if (ctrl & EMAC_TX_ST_SC) 1595 ++st->tx_bd_single_collision; 1596 if (ctrl & EMAC_TX_ST_UR) 1597 ++st->tx_bd_underrun; 1598 if (ctrl & EMAC_TX_ST_SQE) 1599 ++st->tx_bd_sqe; 1600 } 1601 1602 static void emac_poll_tx(void *param) 1603 { 1604 struct emac_instance *dev = param; 1605 u32 bad_mask; 1606 1607 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot); 1608 1609 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 1610 bad_mask = EMAC_IS_BAD_TX_TAH; 1611 else 1612 bad_mask = EMAC_IS_BAD_TX; 1613 1614 netif_tx_lock_bh(dev->ndev); 1615 if (dev->tx_cnt) { 1616 u16 ctrl; 1617 int slot = dev->ack_slot, n = 0; 1618 again: 1619 ctrl = dev->tx_desc[slot].ctrl; 1620 if (!(ctrl & MAL_TX_CTRL_READY)) { 1621 struct sk_buff *skb = dev->tx_skb[slot]; 1622 ++n; 1623 1624 if (skb) { 1625 dev_kfree_skb(skb); 1626 dev->tx_skb[slot] = NULL; 1627 } 1628 slot = (slot + 1) % NUM_TX_BUFF; 1629 1630 if (unlikely(ctrl & bad_mask)) 1631 emac_parse_tx_error(dev, ctrl); 1632 1633 if (--dev->tx_cnt) 1634 goto again; 1635 } 1636 if (n) { 1637 dev->ack_slot = slot; 1638 if (netif_queue_stopped(dev->ndev) && 1639 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH) 1640 netif_wake_queue(dev->ndev); 1641 1642 DBG2(dev, "tx %d pkts" NL, n); 1643 } 1644 } 1645 netif_tx_unlock_bh(dev->ndev); 1646 } 1647 1648 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot, 1649 int len) 1650 { 1651 struct sk_buff *skb = dev->rx_skb[slot]; 1652 1653 DBG2(dev, "recycle %d %d" NL, slot, len); 1654 1655 if (len) 1656 dma_map_single(&dev->ofdev->dev, skb->data - 2, 1657 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE); 1658 1659 dev->rx_desc[slot].data_len = 0; 1660 wmb(); 1661 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY | 1662 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0); 1663 } 1664 1665 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl) 1666 { 1667 struct emac_error_stats *st = &dev->estats; 1668 1669 DBG(dev, "BD RX error %04x" NL, ctrl); 1670 1671 ++st->rx_bd_errors; 1672 if (ctrl & EMAC_RX_ST_OE) 1673 ++st->rx_bd_overrun; 1674 if (ctrl & EMAC_RX_ST_BP) 1675 ++st->rx_bd_bad_packet; 1676 if (ctrl & EMAC_RX_ST_RP) 1677 ++st->rx_bd_runt_packet; 1678 if (ctrl & EMAC_RX_ST_SE) 1679 ++st->rx_bd_short_event; 1680 if (ctrl & EMAC_RX_ST_AE) 1681 ++st->rx_bd_alignment_error; 1682 if (ctrl & EMAC_RX_ST_BFCS) 1683 ++st->rx_bd_bad_fcs; 1684 if (ctrl & EMAC_RX_ST_PTL) 1685 ++st->rx_bd_packet_too_long; 1686 if (ctrl & EMAC_RX_ST_ORE) 1687 ++st->rx_bd_out_of_range; 1688 if (ctrl & EMAC_RX_ST_IRE) 1689 ++st->rx_bd_in_range; 1690 } 1691 1692 static inline void emac_rx_csum(struct emac_instance *dev, 1693 struct sk_buff *skb, u16 ctrl) 1694 { 1695 #ifdef CONFIG_IBM_EMAC_TAH 1696 if (!ctrl && dev->tah_dev) { 1697 skb->ip_summed = CHECKSUM_UNNECESSARY; 1698 ++dev->stats.rx_packets_csum; 1699 } 1700 #endif 1701 } 1702 1703 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot) 1704 { 1705 if (likely(dev->rx_sg_skb != NULL)) { 1706 int len = dev->rx_desc[slot].data_len; 1707 int tot_len = dev->rx_sg_skb->len + len; 1708 1709 if (unlikely(tot_len + 2 > dev->rx_skb_size)) { 1710 ++dev->estats.rx_dropped_mtu; 1711 dev_kfree_skb(dev->rx_sg_skb); 1712 dev->rx_sg_skb = NULL; 1713 } else { 1714 memcpy(skb_tail_pointer(dev->rx_sg_skb), 1715 dev->rx_skb[slot]->data, len); 1716 skb_put(dev->rx_sg_skb, len); 1717 emac_recycle_rx_skb(dev, slot, len); 1718 return 0; 1719 } 1720 } 1721 emac_recycle_rx_skb(dev, slot, 0); 1722 return -1; 1723 } 1724 1725 /* NAPI poll context */ 1726 static int emac_poll_rx(void *param, int budget) 1727 { 1728 struct emac_instance *dev = param; 1729 int slot = dev->rx_slot, received = 0; 1730 1731 DBG2(dev, "poll_rx(%d)" NL, budget); 1732 1733 again: 1734 while (budget > 0) { 1735 int len; 1736 struct sk_buff *skb; 1737 u16 ctrl = dev->rx_desc[slot].ctrl; 1738 1739 if (ctrl & MAL_RX_CTRL_EMPTY) 1740 break; 1741 1742 skb = dev->rx_skb[slot]; 1743 mb(); 1744 len = dev->rx_desc[slot].data_len; 1745 1746 if (unlikely(!MAL_IS_SINGLE_RX(ctrl))) 1747 goto sg; 1748 1749 ctrl &= EMAC_BAD_RX_MASK; 1750 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1751 emac_parse_rx_error(dev, ctrl); 1752 ++dev->estats.rx_dropped_error; 1753 emac_recycle_rx_skb(dev, slot, 0); 1754 len = 0; 1755 goto next; 1756 } 1757 1758 if (len < ETH_HLEN) { 1759 ++dev->estats.rx_dropped_stack; 1760 emac_recycle_rx_skb(dev, slot, len); 1761 goto next; 1762 } 1763 1764 if (len && len < EMAC_RX_COPY_THRESH) { 1765 struct sk_buff *copy_skb = 1766 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC); 1767 if (unlikely(!copy_skb)) 1768 goto oom; 1769 1770 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2); 1771 memcpy(copy_skb->data - 2, skb->data - 2, len + 2); 1772 emac_recycle_rx_skb(dev, slot, len); 1773 skb = copy_skb; 1774 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) 1775 goto oom; 1776 1777 skb_put(skb, len); 1778 push_packet: 1779 skb->protocol = eth_type_trans(skb, dev->ndev); 1780 emac_rx_csum(dev, skb, ctrl); 1781 1782 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) 1783 ++dev->estats.rx_dropped_stack; 1784 next: 1785 ++dev->stats.rx_packets; 1786 skip: 1787 dev->stats.rx_bytes += len; 1788 slot = (slot + 1) % NUM_RX_BUFF; 1789 --budget; 1790 ++received; 1791 continue; 1792 sg: 1793 if (ctrl & MAL_RX_CTRL_FIRST) { 1794 BUG_ON(dev->rx_sg_skb); 1795 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) { 1796 DBG(dev, "rx OOM %d" NL, slot); 1797 ++dev->estats.rx_dropped_oom; 1798 emac_recycle_rx_skb(dev, slot, 0); 1799 } else { 1800 dev->rx_sg_skb = skb; 1801 skb_put(skb, len); 1802 } 1803 } else if (!emac_rx_sg_append(dev, slot) && 1804 (ctrl & MAL_RX_CTRL_LAST)) { 1805 1806 skb = dev->rx_sg_skb; 1807 dev->rx_sg_skb = NULL; 1808 1809 ctrl &= EMAC_BAD_RX_MASK; 1810 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) { 1811 emac_parse_rx_error(dev, ctrl); 1812 ++dev->estats.rx_dropped_error; 1813 dev_kfree_skb(skb); 1814 len = 0; 1815 } else 1816 goto push_packet; 1817 } 1818 goto skip; 1819 oom: 1820 DBG(dev, "rx OOM %d" NL, slot); 1821 /* Drop the packet and recycle skb */ 1822 ++dev->estats.rx_dropped_oom; 1823 emac_recycle_rx_skb(dev, slot, 0); 1824 goto next; 1825 } 1826 1827 if (received) { 1828 DBG2(dev, "rx %d BDs" NL, received); 1829 dev->rx_slot = slot; 1830 } 1831 1832 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) { 1833 mb(); 1834 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) { 1835 DBG2(dev, "rx restart" NL); 1836 received = 0; 1837 goto again; 1838 } 1839 1840 if (dev->rx_sg_skb) { 1841 DBG2(dev, "dropping partial rx packet" NL); 1842 ++dev->estats.rx_dropped_error; 1843 dev_kfree_skb(dev->rx_sg_skb); 1844 dev->rx_sg_skb = NULL; 1845 } 1846 1847 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags); 1848 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan); 1849 emac_rx_enable(dev); 1850 dev->rx_slot = 0; 1851 } 1852 return received; 1853 } 1854 1855 /* NAPI poll context */ 1856 static int emac_peek_rx(void *param) 1857 { 1858 struct emac_instance *dev = param; 1859 1860 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY); 1861 } 1862 1863 /* NAPI poll context */ 1864 static int emac_peek_rx_sg(void *param) 1865 { 1866 struct emac_instance *dev = param; 1867 1868 int slot = dev->rx_slot; 1869 while (1) { 1870 u16 ctrl = dev->rx_desc[slot].ctrl; 1871 if (ctrl & MAL_RX_CTRL_EMPTY) 1872 return 0; 1873 else if (ctrl & MAL_RX_CTRL_LAST) 1874 return 1; 1875 1876 slot = (slot + 1) % NUM_RX_BUFF; 1877 1878 /* I'm just being paranoid here :) */ 1879 if (unlikely(slot == dev->rx_slot)) 1880 return 0; 1881 } 1882 } 1883 1884 /* Hard IRQ */ 1885 static void emac_rxde(void *param) 1886 { 1887 struct emac_instance *dev = param; 1888 1889 ++dev->estats.rx_stopped; 1890 emac_rx_disable_async(dev); 1891 } 1892 1893 /* Hard IRQ */ 1894 static irqreturn_t emac_irq(int irq, void *dev_instance) 1895 { 1896 struct emac_instance *dev = dev_instance; 1897 struct emac_regs __iomem *p = dev->emacp; 1898 struct emac_error_stats *st = &dev->estats; 1899 u32 isr; 1900 1901 spin_lock(&dev->lock); 1902 1903 isr = in_be32(&p->isr); 1904 out_be32(&p->isr, isr); 1905 1906 DBG(dev, "isr = %08x" NL, isr); 1907 1908 if (isr & EMAC4_ISR_TXPE) 1909 ++st->tx_parity; 1910 if (isr & EMAC4_ISR_RXPE) 1911 ++st->rx_parity; 1912 if (isr & EMAC4_ISR_TXUE) 1913 ++st->tx_underrun; 1914 if (isr & EMAC4_ISR_RXOE) 1915 ++st->rx_fifo_overrun; 1916 if (isr & EMAC_ISR_OVR) 1917 ++st->rx_overrun; 1918 if (isr & EMAC_ISR_BP) 1919 ++st->rx_bad_packet; 1920 if (isr & EMAC_ISR_RP) 1921 ++st->rx_runt_packet; 1922 if (isr & EMAC_ISR_SE) 1923 ++st->rx_short_event; 1924 if (isr & EMAC_ISR_ALE) 1925 ++st->rx_alignment_error; 1926 if (isr & EMAC_ISR_BFCS) 1927 ++st->rx_bad_fcs; 1928 if (isr & EMAC_ISR_PTLE) 1929 ++st->rx_packet_too_long; 1930 if (isr & EMAC_ISR_ORE) 1931 ++st->rx_out_of_range; 1932 if (isr & EMAC_ISR_IRE) 1933 ++st->rx_in_range; 1934 if (isr & EMAC_ISR_SQE) 1935 ++st->tx_sqe; 1936 if (isr & EMAC_ISR_TE) 1937 ++st->tx_errors; 1938 1939 spin_unlock(&dev->lock); 1940 1941 return IRQ_HANDLED; 1942 } 1943 1944 static struct net_device_stats *emac_stats(struct net_device *ndev) 1945 { 1946 struct emac_instance *dev = netdev_priv(ndev); 1947 struct emac_stats *st = &dev->stats; 1948 struct emac_error_stats *est = &dev->estats; 1949 struct net_device_stats *nst = &ndev->stats; 1950 unsigned long flags; 1951 1952 DBG2(dev, "stats" NL); 1953 1954 /* Compute "legacy" statistics */ 1955 spin_lock_irqsave(&dev->lock, flags); 1956 nst->rx_packets = (unsigned long)st->rx_packets; 1957 nst->rx_bytes = (unsigned long)st->rx_bytes; 1958 nst->tx_packets = (unsigned long)st->tx_packets; 1959 nst->tx_bytes = (unsigned long)st->tx_bytes; 1960 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom + 1961 est->rx_dropped_error + 1962 est->rx_dropped_resize + 1963 est->rx_dropped_mtu); 1964 nst->tx_dropped = (unsigned long)est->tx_dropped; 1965 1966 nst->rx_errors = (unsigned long)est->rx_bd_errors; 1967 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun + 1968 est->rx_fifo_overrun + 1969 est->rx_overrun); 1970 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error + 1971 est->rx_alignment_error); 1972 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs + 1973 est->rx_bad_fcs); 1974 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet + 1975 est->rx_bd_short_event + 1976 est->rx_bd_packet_too_long + 1977 est->rx_bd_out_of_range + 1978 est->rx_bd_in_range + 1979 est->rx_runt_packet + 1980 est->rx_short_event + 1981 est->rx_packet_too_long + 1982 est->rx_out_of_range + 1983 est->rx_in_range); 1984 1985 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors); 1986 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun + 1987 est->tx_underrun); 1988 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss; 1989 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral + 1990 est->tx_bd_excessive_collisions + 1991 est->tx_bd_late_collision + 1992 est->tx_bd_multple_collisions); 1993 spin_unlock_irqrestore(&dev->lock, flags); 1994 return nst; 1995 } 1996 1997 static struct mal_commac_ops emac_commac_ops = { 1998 .poll_tx = &emac_poll_tx, 1999 .poll_rx = &emac_poll_rx, 2000 .peek_rx = &emac_peek_rx, 2001 .rxde = &emac_rxde, 2002 }; 2003 2004 static struct mal_commac_ops emac_commac_sg_ops = { 2005 .poll_tx = &emac_poll_tx, 2006 .poll_rx = &emac_poll_rx, 2007 .peek_rx = &emac_peek_rx_sg, 2008 .rxde = &emac_rxde, 2009 }; 2010 2011 /* Ethtool support */ 2012 static int emac_ethtool_get_link_ksettings(struct net_device *ndev, 2013 struct ethtool_link_ksettings *cmd) 2014 { 2015 struct emac_instance *dev = netdev_priv(ndev); 2016 u32 supported, advertising; 2017 2018 supported = dev->phy.features; 2019 cmd->base.port = PORT_MII; 2020 cmd->base.phy_address = dev->phy.address; 2021 2022 mutex_lock(&dev->link_lock); 2023 advertising = dev->phy.advertising; 2024 cmd->base.autoneg = dev->phy.autoneg; 2025 cmd->base.speed = dev->phy.speed; 2026 cmd->base.duplex = dev->phy.duplex; 2027 mutex_unlock(&dev->link_lock); 2028 2029 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2030 supported); 2031 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 2032 advertising); 2033 2034 return 0; 2035 } 2036 2037 static int 2038 emac_ethtool_set_link_ksettings(struct net_device *ndev, 2039 const struct ethtool_link_ksettings *cmd) 2040 { 2041 struct emac_instance *dev = netdev_priv(ndev); 2042 u32 f = dev->phy.features; 2043 u32 advertising; 2044 2045 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2046 cmd->link_modes.advertising); 2047 2048 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL, 2049 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising); 2050 2051 /* Basic sanity checks */ 2052 if (dev->phy.address < 0) 2053 return -EOPNOTSUPP; 2054 if (cmd->base.autoneg != AUTONEG_ENABLE && 2055 cmd->base.autoneg != AUTONEG_DISABLE) 2056 return -EINVAL; 2057 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0) 2058 return -EINVAL; 2059 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) 2060 return -EINVAL; 2061 2062 if (cmd->base.autoneg == AUTONEG_DISABLE) { 2063 switch (cmd->base.speed) { 2064 case SPEED_10: 2065 if (cmd->base.duplex == DUPLEX_HALF && 2066 !(f & SUPPORTED_10baseT_Half)) 2067 return -EINVAL; 2068 if (cmd->base.duplex == DUPLEX_FULL && 2069 !(f & SUPPORTED_10baseT_Full)) 2070 return -EINVAL; 2071 break; 2072 case SPEED_100: 2073 if (cmd->base.duplex == DUPLEX_HALF && 2074 !(f & SUPPORTED_100baseT_Half)) 2075 return -EINVAL; 2076 if (cmd->base.duplex == DUPLEX_FULL && 2077 !(f & SUPPORTED_100baseT_Full)) 2078 return -EINVAL; 2079 break; 2080 case SPEED_1000: 2081 if (cmd->base.duplex == DUPLEX_HALF && 2082 !(f & SUPPORTED_1000baseT_Half)) 2083 return -EINVAL; 2084 if (cmd->base.duplex == DUPLEX_FULL && 2085 !(f & SUPPORTED_1000baseT_Full)) 2086 return -EINVAL; 2087 break; 2088 default: 2089 return -EINVAL; 2090 } 2091 2092 mutex_lock(&dev->link_lock); 2093 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed, 2094 cmd->base.duplex); 2095 mutex_unlock(&dev->link_lock); 2096 2097 } else { 2098 if (!(f & SUPPORTED_Autoneg)) 2099 return -EINVAL; 2100 2101 mutex_lock(&dev->link_lock); 2102 dev->phy.def->ops->setup_aneg(&dev->phy, 2103 (advertising & f) | 2104 (dev->phy.advertising & 2105 (ADVERTISED_Pause | 2106 ADVERTISED_Asym_Pause))); 2107 mutex_unlock(&dev->link_lock); 2108 } 2109 emac_force_link_update(dev); 2110 2111 return 0; 2112 } 2113 2114 static void emac_ethtool_get_ringparam(struct net_device *ndev, 2115 struct ethtool_ringparam *rp) 2116 { 2117 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF; 2118 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF; 2119 } 2120 2121 static void emac_ethtool_get_pauseparam(struct net_device *ndev, 2122 struct ethtool_pauseparam *pp) 2123 { 2124 struct emac_instance *dev = netdev_priv(ndev); 2125 2126 mutex_lock(&dev->link_lock); 2127 if ((dev->phy.features & SUPPORTED_Autoneg) && 2128 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause))) 2129 pp->autoneg = 1; 2130 2131 if (dev->phy.duplex == DUPLEX_FULL) { 2132 if (dev->phy.pause) 2133 pp->rx_pause = pp->tx_pause = 1; 2134 else if (dev->phy.asym_pause) 2135 pp->tx_pause = 1; 2136 } 2137 mutex_unlock(&dev->link_lock); 2138 } 2139 2140 static int emac_get_regs_len(struct emac_instance *dev) 2141 { 2142 return sizeof(struct emac_ethtool_regs_subhdr) + 2143 sizeof(struct emac_regs); 2144 } 2145 2146 static int emac_ethtool_get_regs_len(struct net_device *ndev) 2147 { 2148 struct emac_instance *dev = netdev_priv(ndev); 2149 int size; 2150 2151 size = sizeof(struct emac_ethtool_regs_hdr) + 2152 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal); 2153 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 2154 size += zmii_get_regs_len(dev->zmii_dev); 2155 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 2156 size += rgmii_get_regs_len(dev->rgmii_dev); 2157 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 2158 size += tah_get_regs_len(dev->tah_dev); 2159 2160 return size; 2161 } 2162 2163 static void *emac_dump_regs(struct emac_instance *dev, void *buf) 2164 { 2165 struct emac_ethtool_regs_subhdr *hdr = buf; 2166 2167 hdr->index = dev->cell_index; 2168 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2169 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER; 2170 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) { 2171 hdr->version = EMAC4_ETHTOOL_REGS_VER; 2172 } else { 2173 hdr->version = EMAC_ETHTOOL_REGS_VER; 2174 } 2175 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs)); 2176 return (void *)(hdr + 1) + sizeof(struct emac_regs); 2177 } 2178 2179 static void emac_ethtool_get_regs(struct net_device *ndev, 2180 struct ethtool_regs *regs, void *buf) 2181 { 2182 struct emac_instance *dev = netdev_priv(ndev); 2183 struct emac_ethtool_regs_hdr *hdr = buf; 2184 2185 hdr->components = 0; 2186 buf = hdr + 1; 2187 2188 buf = mal_dump_regs(dev->mal, buf); 2189 buf = emac_dump_regs(dev, buf); 2190 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) { 2191 hdr->components |= EMAC_ETHTOOL_REGS_ZMII; 2192 buf = zmii_dump_regs(dev->zmii_dev, buf); 2193 } 2194 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2195 hdr->components |= EMAC_ETHTOOL_REGS_RGMII; 2196 buf = rgmii_dump_regs(dev->rgmii_dev, buf); 2197 } 2198 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) { 2199 hdr->components |= EMAC_ETHTOOL_REGS_TAH; 2200 buf = tah_dump_regs(dev->tah_dev, buf); 2201 } 2202 } 2203 2204 static int emac_ethtool_nway_reset(struct net_device *ndev) 2205 { 2206 struct emac_instance *dev = netdev_priv(ndev); 2207 int res = 0; 2208 2209 DBG(dev, "nway_reset" NL); 2210 2211 if (dev->phy.address < 0) 2212 return -EOPNOTSUPP; 2213 2214 mutex_lock(&dev->link_lock); 2215 if (!dev->phy.autoneg) { 2216 res = -EINVAL; 2217 goto out; 2218 } 2219 2220 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising); 2221 out: 2222 mutex_unlock(&dev->link_lock); 2223 emac_force_link_update(dev); 2224 return res; 2225 } 2226 2227 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset) 2228 { 2229 if (stringset == ETH_SS_STATS) 2230 return EMAC_ETHTOOL_STATS_COUNT; 2231 else 2232 return -EINVAL; 2233 } 2234 2235 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset, 2236 u8 * buf) 2237 { 2238 if (stringset == ETH_SS_STATS) 2239 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys)); 2240 } 2241 2242 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev, 2243 struct ethtool_stats *estats, 2244 u64 * tmp_stats) 2245 { 2246 struct emac_instance *dev = netdev_priv(ndev); 2247 2248 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats)); 2249 tmp_stats += sizeof(dev->stats) / sizeof(u64); 2250 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats)); 2251 } 2252 2253 static void emac_ethtool_get_drvinfo(struct net_device *ndev, 2254 struct ethtool_drvinfo *info) 2255 { 2256 struct emac_instance *dev = netdev_priv(ndev); 2257 2258 strlcpy(info->driver, "ibm_emac", sizeof(info->driver)); 2259 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2260 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF", 2261 dev->cell_index, dev->ofdev->dev.of_node); 2262 } 2263 2264 static const struct ethtool_ops emac_ethtool_ops = { 2265 .get_drvinfo = emac_ethtool_get_drvinfo, 2266 2267 .get_regs_len = emac_ethtool_get_regs_len, 2268 .get_regs = emac_ethtool_get_regs, 2269 2270 .nway_reset = emac_ethtool_nway_reset, 2271 2272 .get_ringparam = emac_ethtool_get_ringparam, 2273 .get_pauseparam = emac_ethtool_get_pauseparam, 2274 2275 .get_strings = emac_ethtool_get_strings, 2276 .get_sset_count = emac_ethtool_get_sset_count, 2277 .get_ethtool_stats = emac_ethtool_get_ethtool_stats, 2278 2279 .get_link = ethtool_op_get_link, 2280 .get_link_ksettings = emac_ethtool_get_link_ksettings, 2281 .set_link_ksettings = emac_ethtool_set_link_ksettings, 2282 }; 2283 2284 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2285 { 2286 struct emac_instance *dev = netdev_priv(ndev); 2287 struct mii_ioctl_data *data = if_mii(rq); 2288 2289 DBG(dev, "ioctl %08x" NL, cmd); 2290 2291 if (dev->phy.address < 0) 2292 return -EOPNOTSUPP; 2293 2294 switch (cmd) { 2295 case SIOCGMIIPHY: 2296 data->phy_id = dev->phy.address; 2297 /* Fall through */ 2298 case SIOCGMIIREG: 2299 data->val_out = emac_mdio_read(ndev, dev->phy.address, 2300 data->reg_num); 2301 return 0; 2302 2303 case SIOCSMIIREG: 2304 emac_mdio_write(ndev, dev->phy.address, data->reg_num, 2305 data->val_in); 2306 return 0; 2307 default: 2308 return -EOPNOTSUPP; 2309 } 2310 } 2311 2312 struct emac_depentry { 2313 u32 phandle; 2314 struct device_node *node; 2315 struct platform_device *ofdev; 2316 void *drvdata; 2317 }; 2318 2319 #define EMAC_DEP_MAL_IDX 0 2320 #define EMAC_DEP_ZMII_IDX 1 2321 #define EMAC_DEP_RGMII_IDX 2 2322 #define EMAC_DEP_TAH_IDX 3 2323 #define EMAC_DEP_MDIO_IDX 4 2324 #define EMAC_DEP_PREV_IDX 5 2325 #define EMAC_DEP_COUNT 6 2326 2327 static int emac_check_deps(struct emac_instance *dev, 2328 struct emac_depentry *deps) 2329 { 2330 int i, there = 0; 2331 struct device_node *np; 2332 2333 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2334 /* no dependency on that item, allright */ 2335 if (deps[i].phandle == 0) { 2336 there++; 2337 continue; 2338 } 2339 /* special case for blist as the dependency might go away */ 2340 if (i == EMAC_DEP_PREV_IDX) { 2341 np = *(dev->blist - 1); 2342 if (np == NULL) { 2343 deps[i].phandle = 0; 2344 there++; 2345 continue; 2346 } 2347 if (deps[i].node == NULL) 2348 deps[i].node = of_node_get(np); 2349 } 2350 if (deps[i].node == NULL) 2351 deps[i].node = of_find_node_by_phandle(deps[i].phandle); 2352 if (deps[i].node == NULL) 2353 continue; 2354 if (deps[i].ofdev == NULL) 2355 deps[i].ofdev = of_find_device_by_node(deps[i].node); 2356 if (deps[i].ofdev == NULL) 2357 continue; 2358 if (deps[i].drvdata == NULL) 2359 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev); 2360 if (deps[i].drvdata != NULL) 2361 there++; 2362 } 2363 return there == EMAC_DEP_COUNT; 2364 } 2365 2366 static void emac_put_deps(struct emac_instance *dev) 2367 { 2368 of_dev_put(dev->mal_dev); 2369 of_dev_put(dev->zmii_dev); 2370 of_dev_put(dev->rgmii_dev); 2371 of_dev_put(dev->mdio_dev); 2372 of_dev_put(dev->tah_dev); 2373 } 2374 2375 static int emac_of_bus_notify(struct notifier_block *nb, unsigned long action, 2376 void *data) 2377 { 2378 /* We are only intereted in device addition */ 2379 if (action == BUS_NOTIFY_BOUND_DRIVER) 2380 wake_up_all(&emac_probe_wait); 2381 return 0; 2382 } 2383 2384 static struct notifier_block emac_of_bus_notifier = { 2385 .notifier_call = emac_of_bus_notify 2386 }; 2387 2388 static int emac_wait_deps(struct emac_instance *dev) 2389 { 2390 struct emac_depentry deps[EMAC_DEP_COUNT]; 2391 int i, err; 2392 2393 memset(&deps, 0, sizeof(deps)); 2394 2395 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph; 2396 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph; 2397 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph; 2398 if (dev->tah_ph) 2399 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph; 2400 if (dev->mdio_ph) 2401 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph; 2402 if (dev->blist && dev->blist > emac_boot_list) 2403 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu; 2404 bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier); 2405 wait_event_timeout(emac_probe_wait, 2406 emac_check_deps(dev, deps), 2407 EMAC_PROBE_DEP_TIMEOUT); 2408 bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier); 2409 err = emac_check_deps(dev, deps) ? 0 : -ENODEV; 2410 for (i = 0; i < EMAC_DEP_COUNT; i++) { 2411 of_node_put(deps[i].node); 2412 if (err) 2413 of_dev_put(deps[i].ofdev); 2414 } 2415 if (err == 0) { 2416 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev; 2417 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev; 2418 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev; 2419 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev; 2420 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev; 2421 } 2422 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev); 2423 return err; 2424 } 2425 2426 static int emac_read_uint_prop(struct device_node *np, const char *name, 2427 u32 *val, int fatal) 2428 { 2429 int len; 2430 const u32 *prop = of_get_property(np, name, &len); 2431 if (prop == NULL || len < sizeof(u32)) { 2432 if (fatal) 2433 printk(KERN_ERR "%pOF: missing %s property\n", 2434 np, name); 2435 return -ENODEV; 2436 } 2437 *val = *prop; 2438 return 0; 2439 } 2440 2441 static void emac_adjust_link(struct net_device *ndev) 2442 { 2443 struct emac_instance *dev = netdev_priv(ndev); 2444 struct phy_device *phy = dev->phy_dev; 2445 2446 dev->phy.autoneg = phy->autoneg; 2447 dev->phy.speed = phy->speed; 2448 dev->phy.duplex = phy->duplex; 2449 dev->phy.pause = phy->pause; 2450 dev->phy.asym_pause = phy->asym_pause; 2451 dev->phy.advertising = phy->advertising; 2452 } 2453 2454 static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum) 2455 { 2456 int ret = emac_mdio_read(bus->priv, addr, regnum); 2457 /* This is a workaround for powered down ports/phys. 2458 * In the wild, this was seen on the Cisco Meraki MX60(W). 2459 * This hardware disables ports as part of the handoff 2460 * procedure. Accessing the ports will lead to errors 2461 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good. 2462 */ 2463 return ret < 0 ? 0xffff : ret; 2464 } 2465 2466 static int emac_mii_bus_write(struct mii_bus *bus, int addr, 2467 int regnum, u16 val) 2468 { 2469 emac_mdio_write(bus->priv, addr, regnum, val); 2470 return 0; 2471 } 2472 2473 static int emac_mii_bus_reset(struct mii_bus *bus) 2474 { 2475 struct emac_instance *dev = netdev_priv(bus->priv); 2476 2477 return emac_reset(dev); 2478 } 2479 2480 static int emac_mdio_phy_start_aneg(struct mii_phy *phy, 2481 struct phy_device *phy_dev) 2482 { 2483 phy_dev->autoneg = phy->autoneg; 2484 phy_dev->speed = phy->speed; 2485 phy_dev->duplex = phy->duplex; 2486 phy_dev->advertising = phy->advertising; 2487 return phy_start_aneg(phy_dev); 2488 } 2489 2490 static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise) 2491 { 2492 struct net_device *ndev = phy->dev; 2493 struct emac_instance *dev = netdev_priv(ndev); 2494 2495 phy->autoneg = AUTONEG_ENABLE; 2496 phy->advertising = advertise; 2497 return emac_mdio_phy_start_aneg(phy, dev->phy_dev); 2498 } 2499 2500 static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd) 2501 { 2502 struct net_device *ndev = phy->dev; 2503 struct emac_instance *dev = netdev_priv(ndev); 2504 2505 phy->autoneg = AUTONEG_DISABLE; 2506 phy->speed = speed; 2507 phy->duplex = fd; 2508 return emac_mdio_phy_start_aneg(phy, dev->phy_dev); 2509 } 2510 2511 static int emac_mdio_poll_link(struct mii_phy *phy) 2512 { 2513 struct net_device *ndev = phy->dev; 2514 struct emac_instance *dev = netdev_priv(ndev); 2515 int res; 2516 2517 res = phy_read_status(dev->phy_dev); 2518 if (res) { 2519 dev_err(&dev->ofdev->dev, "link update failed (%d).", res); 2520 return ethtool_op_get_link(ndev); 2521 } 2522 2523 return dev->phy_dev->link; 2524 } 2525 2526 static int emac_mdio_read_link(struct mii_phy *phy) 2527 { 2528 struct net_device *ndev = phy->dev; 2529 struct emac_instance *dev = netdev_priv(ndev); 2530 struct phy_device *phy_dev = dev->phy_dev; 2531 int res; 2532 2533 res = phy_read_status(phy_dev); 2534 if (res) 2535 return res; 2536 2537 phy->speed = phy_dev->speed; 2538 phy->duplex = phy_dev->duplex; 2539 phy->pause = phy_dev->pause; 2540 phy->asym_pause = phy_dev->asym_pause; 2541 return 0; 2542 } 2543 2544 static int emac_mdio_init_phy(struct mii_phy *phy) 2545 { 2546 struct net_device *ndev = phy->dev; 2547 struct emac_instance *dev = netdev_priv(ndev); 2548 2549 phy_start(dev->phy_dev); 2550 return phy_init_hw(dev->phy_dev); 2551 } 2552 2553 static const struct mii_phy_ops emac_dt_mdio_phy_ops = { 2554 .init = emac_mdio_init_phy, 2555 .setup_aneg = emac_mdio_setup_aneg, 2556 .setup_forced = emac_mdio_setup_forced, 2557 .poll_link = emac_mdio_poll_link, 2558 .read_link = emac_mdio_read_link, 2559 }; 2560 2561 static int emac_dt_mdio_probe(struct emac_instance *dev) 2562 { 2563 struct device_node *mii_np; 2564 int res; 2565 2566 mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio"); 2567 if (!mii_np) { 2568 dev_err(&dev->ofdev->dev, "no mdio definition found."); 2569 return -ENODEV; 2570 } 2571 2572 if (!of_device_is_available(mii_np)) { 2573 res = -ENODEV; 2574 goto put_node; 2575 } 2576 2577 dev->mii_bus = devm_mdiobus_alloc(&dev->ofdev->dev); 2578 if (!dev->mii_bus) { 2579 res = -ENOMEM; 2580 goto put_node; 2581 } 2582 2583 dev->mii_bus->priv = dev->ndev; 2584 dev->mii_bus->parent = dev->ndev->dev.parent; 2585 dev->mii_bus->name = "emac_mdio"; 2586 dev->mii_bus->read = &emac_mii_bus_read; 2587 dev->mii_bus->write = &emac_mii_bus_write; 2588 dev->mii_bus->reset = &emac_mii_bus_reset; 2589 snprintf(dev->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name); 2590 res = of_mdiobus_register(dev->mii_bus, mii_np); 2591 if (res) { 2592 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)", 2593 dev->mii_bus->name, res); 2594 } 2595 2596 put_node: 2597 of_node_put(mii_np); 2598 return res; 2599 } 2600 2601 static int emac_dt_phy_connect(struct emac_instance *dev, 2602 struct device_node *phy_handle) 2603 { 2604 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def), 2605 GFP_KERNEL); 2606 if (!dev->phy.def) 2607 return -ENOMEM; 2608 2609 dev->phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 2610 0, dev->phy_mode); 2611 if (!dev->phy_dev) { 2612 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n"); 2613 return -ENODEV; 2614 } 2615 2616 dev->phy.def->phy_id = dev->phy_dev->drv->phy_id; 2617 dev->phy.def->phy_id_mask = dev->phy_dev->drv->phy_id_mask; 2618 dev->phy.def->name = dev->phy_dev->drv->name; 2619 dev->phy.def->ops = &emac_dt_mdio_phy_ops; 2620 dev->phy.features = dev->phy_dev->supported; 2621 dev->phy.address = dev->phy_dev->mdio.addr; 2622 dev->phy.mode = dev->phy_dev->interface; 2623 return 0; 2624 } 2625 2626 static int emac_dt_phy_probe(struct emac_instance *dev) 2627 { 2628 struct device_node *np = dev->ofdev->dev.of_node; 2629 struct device_node *phy_handle; 2630 int res = 1; 2631 2632 phy_handle = of_parse_phandle(np, "phy-handle", 0); 2633 2634 if (phy_handle) { 2635 res = emac_dt_mdio_probe(dev); 2636 if (!res) { 2637 res = emac_dt_phy_connect(dev, phy_handle); 2638 if (res) 2639 mdiobus_unregister(dev->mii_bus); 2640 } 2641 } 2642 2643 of_node_put(phy_handle); 2644 return res; 2645 } 2646 2647 static int emac_init_phy(struct emac_instance *dev) 2648 { 2649 struct device_node *np = dev->ofdev->dev.of_node; 2650 struct net_device *ndev = dev->ndev; 2651 u32 phy_map, adv; 2652 int i; 2653 2654 dev->phy.dev = ndev; 2655 dev->phy.mode = dev->phy_mode; 2656 2657 /* PHY-less configuration. */ 2658 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) || 2659 of_phy_is_fixed_link(np)) { 2660 emac_reset(dev); 2661 2662 /* PHY-less configuration. */ 2663 dev->phy.address = -1; 2664 dev->phy.features = SUPPORTED_MII; 2665 if (emac_phy_supports_gige(dev->phy_mode)) 2666 dev->phy.features |= SUPPORTED_1000baseT_Full; 2667 else 2668 dev->phy.features |= SUPPORTED_100baseT_Full; 2669 dev->phy.pause = 1; 2670 2671 if (of_phy_is_fixed_link(np)) { 2672 int res = emac_dt_mdio_probe(dev); 2673 2674 if (!res) { 2675 res = of_phy_register_fixed_link(np); 2676 if (res) 2677 mdiobus_unregister(dev->mii_bus); 2678 } 2679 return res; 2680 } 2681 return 0; 2682 } 2683 2684 mutex_lock(&emac_phy_map_lock); 2685 phy_map = dev->phy_map | busy_phy_map; 2686 2687 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map); 2688 2689 dev->phy.mdio_read = emac_mdio_read; 2690 dev->phy.mdio_write = emac_mdio_write; 2691 2692 /* Enable internal clock source */ 2693 #ifdef CONFIG_PPC_DCR_NATIVE 2694 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2695 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2696 #endif 2697 /* PHY clock workaround */ 2698 emac_rx_clk_tx(dev); 2699 2700 /* Enable internal clock source on 440GX*/ 2701 #ifdef CONFIG_PPC_DCR_NATIVE 2702 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2703 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); 2704 #endif 2705 /* Configure EMAC with defaults so we can at least use MDIO 2706 * This is needed mostly for 440GX 2707 */ 2708 if (emac_phy_gpcs(dev->phy.mode)) { 2709 /* XXX 2710 * Make GPCS PHY address equal to EMAC index. 2711 * We probably should take into account busy_phy_map 2712 * and/or phy_map here. 2713 * 2714 * Note that the busy_phy_map is currently global 2715 * while it should probably be per-ASIC... 2716 */ 2717 dev->phy.gpcs_address = dev->gpcs_address; 2718 if (dev->phy.gpcs_address == 0xffffffff) 2719 dev->phy.address = dev->cell_index; 2720 } 2721 2722 emac_configure(dev); 2723 2724 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) { 2725 int res = emac_dt_phy_probe(dev); 2726 2727 switch (res) { 2728 case 1: 2729 /* No phy-handle property configured. 2730 * Continue with the existing phy probe 2731 * and setup code. 2732 */ 2733 break; 2734 2735 case 0: 2736 mutex_unlock(&emac_phy_map_lock); 2737 goto init_phy; 2738 2739 default: 2740 mutex_unlock(&emac_phy_map_lock); 2741 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n", 2742 res); 2743 return res; 2744 } 2745 } 2746 2747 if (dev->phy_address != 0xffffffff) 2748 phy_map = ~(1 << dev->phy_address); 2749 2750 for (i = 0; i < 0x20; phy_map >>= 1, ++i) 2751 if (!(phy_map & 1)) { 2752 int r; 2753 busy_phy_map |= 1 << i; 2754 2755 /* Quick check if there is a PHY at the address */ 2756 r = emac_mdio_read(dev->ndev, i, MII_BMCR); 2757 if (r == 0xffff || r < 0) 2758 continue; 2759 if (!emac_mii_phy_probe(&dev->phy, i)) 2760 break; 2761 } 2762 2763 /* Enable external clock source */ 2764 #ifdef CONFIG_PPC_DCR_NATIVE 2765 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX)) 2766 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0); 2767 #endif 2768 mutex_unlock(&emac_phy_map_lock); 2769 if (i == 0x20) { 2770 printk(KERN_WARNING "%pOF: can't find PHY!\n", np); 2771 return -ENXIO; 2772 } 2773 2774 init_phy: 2775 /* Init PHY */ 2776 if (dev->phy.def->ops->init) 2777 dev->phy.def->ops->init(&dev->phy); 2778 2779 /* Disable any PHY features not supported by the platform */ 2780 dev->phy.def->features &= ~dev->phy_feat_exc; 2781 dev->phy.features &= ~dev->phy_feat_exc; 2782 2783 /* Setup initial link parameters */ 2784 if (dev->phy.features & SUPPORTED_Autoneg) { 2785 adv = dev->phy.features; 2786 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x)) 2787 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 2788 /* Restart autonegotiation */ 2789 dev->phy.def->ops->setup_aneg(&dev->phy, adv); 2790 } else { 2791 u32 f = dev->phy.def->features; 2792 int speed = SPEED_10, fd = DUPLEX_HALF; 2793 2794 /* Select highest supported speed/duplex */ 2795 if (f & SUPPORTED_1000baseT_Full) { 2796 speed = SPEED_1000; 2797 fd = DUPLEX_FULL; 2798 } else if (f & SUPPORTED_1000baseT_Half) 2799 speed = SPEED_1000; 2800 else if (f & SUPPORTED_100baseT_Full) { 2801 speed = SPEED_100; 2802 fd = DUPLEX_FULL; 2803 } else if (f & SUPPORTED_100baseT_Half) 2804 speed = SPEED_100; 2805 else if (f & SUPPORTED_10baseT_Full) 2806 fd = DUPLEX_FULL; 2807 2808 /* Force link parameters */ 2809 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd); 2810 } 2811 return 0; 2812 } 2813 2814 static int emac_init_config(struct emac_instance *dev) 2815 { 2816 struct device_node *np = dev->ofdev->dev.of_node; 2817 const void *p; 2818 2819 /* Read config from device-tree */ 2820 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1)) 2821 return -ENXIO; 2822 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1)) 2823 return -ENXIO; 2824 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1)) 2825 return -ENXIO; 2826 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1)) 2827 return -ENXIO; 2828 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0)) 2829 dev->max_mtu = ETH_DATA_LEN; 2830 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0)) 2831 dev->rx_fifo_size = 2048; 2832 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0)) 2833 dev->tx_fifo_size = 2048; 2834 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0)) 2835 dev->rx_fifo_size_gige = dev->rx_fifo_size; 2836 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0)) 2837 dev->tx_fifo_size_gige = dev->tx_fifo_size; 2838 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0)) 2839 dev->phy_address = 0xffffffff; 2840 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0)) 2841 dev->phy_map = 0xffffffff; 2842 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0)) 2843 dev->gpcs_address = 0xffffffff; 2844 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1)) 2845 return -ENXIO; 2846 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0)) 2847 dev->tah_ph = 0; 2848 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0)) 2849 dev->tah_port = 0; 2850 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0)) 2851 dev->mdio_ph = 0; 2852 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0)) 2853 dev->zmii_ph = 0; 2854 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0)) 2855 dev->zmii_port = 0xffffffff; 2856 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0)) 2857 dev->rgmii_ph = 0; 2858 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0)) 2859 dev->rgmii_port = 0xffffffff; 2860 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0)) 2861 dev->fifo_entry_size = 16; 2862 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0)) 2863 dev->mal_burst_size = 256; 2864 2865 /* PHY mode needs some decoding */ 2866 dev->phy_mode = of_get_phy_mode(np); 2867 if (dev->phy_mode < 0) 2868 dev->phy_mode = PHY_MODE_NA; 2869 2870 /* Check EMAC version */ 2871 if (of_device_is_compatible(np, "ibm,emac4sync")) { 2872 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC); 2873 if (of_device_is_compatible(np, "ibm,emac-460ex") || 2874 of_device_is_compatible(np, "ibm,emac-460gt")) 2875 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; 2876 if (of_device_is_compatible(np, "ibm,emac-405ex") || 2877 of_device_is_compatible(np, "ibm,emac-405exr")) 2878 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2879 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) { 2880 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 2881 EMAC_FTR_APM821XX_NO_HALF_DUPLEX | 2882 EMAC_FTR_460EX_PHY_CLK_FIX); 2883 } 2884 } else if (of_device_is_compatible(np, "ibm,emac4")) { 2885 dev->features |= EMAC_FTR_EMAC4; 2886 if (of_device_is_compatible(np, "ibm,emac-440gx")) 2887 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX; 2888 } else { 2889 if (of_device_is_compatible(np, "ibm,emac-440ep") || 2890 of_device_is_compatible(np, "ibm,emac-440gr")) 2891 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; 2892 if (of_device_is_compatible(np, "ibm,emac-405ez")) { 2893 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 2894 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x; 2895 #else 2896 printk(KERN_ERR "%pOF: Flow control not disabled!\n", 2897 np); 2898 return -ENXIO; 2899 #endif 2900 } 2901 2902 } 2903 2904 /* Fixup some feature bits based on the device tree */ 2905 if (of_get_property(np, "has-inverted-stacr-oc", NULL)) 2906 dev->features |= EMAC_FTR_STACR_OC_INVERT; 2907 if (of_get_property(np, "has-new-stacr-staopc", NULL)) 2908 dev->features |= EMAC_FTR_HAS_NEW_STACR; 2909 2910 /* CAB lacks the appropriate properties */ 2911 if (of_device_is_compatible(np, "ibm,emac-axon")) 2912 dev->features |= EMAC_FTR_HAS_NEW_STACR | 2913 EMAC_FTR_STACR_OC_INVERT; 2914 2915 /* Enable TAH/ZMII/RGMII features as found */ 2916 if (dev->tah_ph != 0) { 2917 #ifdef CONFIG_IBM_EMAC_TAH 2918 dev->features |= EMAC_FTR_HAS_TAH; 2919 #else 2920 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np); 2921 return -ENXIO; 2922 #endif 2923 } 2924 2925 if (dev->zmii_ph != 0) { 2926 #ifdef CONFIG_IBM_EMAC_ZMII 2927 dev->features |= EMAC_FTR_HAS_ZMII; 2928 #else 2929 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np); 2930 return -ENXIO; 2931 #endif 2932 } 2933 2934 if (dev->rgmii_ph != 0) { 2935 #ifdef CONFIG_IBM_EMAC_RGMII 2936 dev->features |= EMAC_FTR_HAS_RGMII; 2937 #else 2938 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np); 2939 return -ENXIO; 2940 #endif 2941 } 2942 2943 /* Read MAC-address */ 2944 p = of_get_property(np, "local-mac-address", NULL); 2945 if (p == NULL) { 2946 printk(KERN_ERR "%pOF: Can't find local-mac-address property\n", 2947 np); 2948 return -ENXIO; 2949 } 2950 memcpy(dev->ndev->dev_addr, p, ETH_ALEN); 2951 2952 /* IAHT and GAHT filter parameterization */ 2953 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) { 2954 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT; 2955 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT; 2956 } else { 2957 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT; 2958 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT; 2959 } 2960 2961 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE); 2962 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige); 2963 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige); 2964 DBG(dev, "max_mtu : %d\n", dev->max_mtu); 2965 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq); 2966 2967 return 0; 2968 } 2969 2970 static const struct net_device_ops emac_netdev_ops = { 2971 .ndo_open = emac_open, 2972 .ndo_stop = emac_close, 2973 .ndo_get_stats = emac_stats, 2974 .ndo_set_rx_mode = emac_set_multicast_list, 2975 .ndo_do_ioctl = emac_ioctl, 2976 .ndo_tx_timeout = emac_tx_timeout, 2977 .ndo_validate_addr = eth_validate_addr, 2978 .ndo_set_mac_address = emac_set_mac_address, 2979 .ndo_start_xmit = emac_start_xmit, 2980 }; 2981 2982 static const struct net_device_ops emac_gige_netdev_ops = { 2983 .ndo_open = emac_open, 2984 .ndo_stop = emac_close, 2985 .ndo_get_stats = emac_stats, 2986 .ndo_set_rx_mode = emac_set_multicast_list, 2987 .ndo_do_ioctl = emac_ioctl, 2988 .ndo_tx_timeout = emac_tx_timeout, 2989 .ndo_validate_addr = eth_validate_addr, 2990 .ndo_set_mac_address = emac_set_mac_address, 2991 .ndo_start_xmit = emac_start_xmit_sg, 2992 .ndo_change_mtu = emac_change_mtu, 2993 }; 2994 2995 static int emac_probe(struct platform_device *ofdev) 2996 { 2997 struct net_device *ndev; 2998 struct emac_instance *dev; 2999 struct device_node *np = ofdev->dev.of_node; 3000 struct device_node **blist = NULL; 3001 int err, i; 3002 3003 /* Skip unused/unwired EMACS. We leave the check for an unused 3004 * property here for now, but new flat device trees should set a 3005 * status property to "disabled" instead. 3006 */ 3007 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np)) 3008 return -ENODEV; 3009 3010 /* Find ourselves in the bootlist if we are there */ 3011 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3012 if (emac_boot_list[i] == np) 3013 blist = &emac_boot_list[i]; 3014 3015 /* Allocate our net_device structure */ 3016 err = -ENOMEM; 3017 ndev = alloc_etherdev(sizeof(struct emac_instance)); 3018 if (!ndev) 3019 goto err_gone; 3020 3021 dev = netdev_priv(ndev); 3022 dev->ndev = ndev; 3023 dev->ofdev = ofdev; 3024 dev->blist = blist; 3025 SET_NETDEV_DEV(ndev, &ofdev->dev); 3026 3027 /* Initialize some embedded data structures */ 3028 mutex_init(&dev->mdio_lock); 3029 mutex_init(&dev->link_lock); 3030 spin_lock_init(&dev->lock); 3031 INIT_WORK(&dev->reset_work, emac_reset_work); 3032 3033 /* Init various config data based on device-tree */ 3034 err = emac_init_config(dev); 3035 if (err) 3036 goto err_free; 3037 3038 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */ 3039 dev->emac_irq = irq_of_parse_and_map(np, 0); 3040 dev->wol_irq = irq_of_parse_and_map(np, 1); 3041 if (!dev->emac_irq) { 3042 printk(KERN_ERR "%pOF: Can't map main interrupt\n", np); 3043 err = -ENODEV; 3044 goto err_free; 3045 } 3046 ndev->irq = dev->emac_irq; 3047 3048 /* Map EMAC regs */ 3049 // TODO : platform_get_resource() and devm_ioremap_resource() 3050 dev->emacp = of_iomap(np, 0); 3051 if (dev->emacp == NULL) { 3052 printk(KERN_ERR "%pOF: Can't map device registers!\n", np); 3053 err = -ENOMEM; 3054 goto err_irq_unmap; 3055 } 3056 3057 /* Wait for dependent devices */ 3058 err = emac_wait_deps(dev); 3059 if (err) { 3060 printk(KERN_ERR 3061 "%pOF: Timeout waiting for dependent devices\n", np); 3062 /* display more info about what's missing ? */ 3063 goto err_reg_unmap; 3064 } 3065 dev->mal = platform_get_drvdata(dev->mal_dev); 3066 if (dev->mdio_dev != NULL) 3067 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev); 3068 3069 /* Register with MAL */ 3070 dev->commac.ops = &emac_commac_ops; 3071 dev->commac.dev = dev; 3072 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan); 3073 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan); 3074 err = mal_register_commac(dev->mal, &dev->commac); 3075 if (err) { 3076 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n", 3077 np, dev->mal_dev->dev.of_node); 3078 goto err_rel_deps; 3079 } 3080 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu); 3081 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu); 3082 3083 /* Get pointers to BD rings */ 3084 dev->tx_desc = 3085 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan); 3086 dev->rx_desc = 3087 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan); 3088 3089 DBG(dev, "tx_desc %p" NL, dev->tx_desc); 3090 DBG(dev, "rx_desc %p" NL, dev->rx_desc); 3091 3092 /* Clean rings */ 3093 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor)); 3094 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor)); 3095 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *)); 3096 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *)); 3097 3098 /* Attach to ZMII, if needed */ 3099 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && 3100 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0) 3101 goto err_unreg_commac; 3102 3103 /* Attach to RGMII, if needed */ 3104 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) && 3105 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0) 3106 goto err_detach_zmii; 3107 3108 /* Attach to TAH, if needed */ 3109 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) && 3110 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0) 3111 goto err_detach_rgmii; 3112 3113 /* Set some link defaults before we can find out real parameters */ 3114 dev->phy.speed = SPEED_100; 3115 dev->phy.duplex = DUPLEX_FULL; 3116 dev->phy.autoneg = AUTONEG_DISABLE; 3117 dev->phy.pause = dev->phy.asym_pause = 0; 3118 dev->stop_timeout = STOP_TIMEOUT_100; 3119 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer); 3120 3121 /* Some SoCs like APM821xx does not support Half Duplex mode. */ 3122 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) { 3123 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half | 3124 SUPPORTED_100baseT_Half | 3125 SUPPORTED_10baseT_Half); 3126 } 3127 3128 /* Find PHY if any */ 3129 err = emac_init_phy(dev); 3130 if (err != 0) 3131 goto err_detach_tah; 3132 3133 if (dev->tah_dev) { 3134 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG; 3135 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM; 3136 } 3137 ndev->watchdog_timeo = 5 * HZ; 3138 if (emac_phy_supports_gige(dev->phy_mode)) { 3139 ndev->netdev_ops = &emac_gige_netdev_ops; 3140 dev->commac.ops = &emac_commac_sg_ops; 3141 } else 3142 ndev->netdev_ops = &emac_netdev_ops; 3143 ndev->ethtool_ops = &emac_ethtool_ops; 3144 3145 /* MTU range: 46 - 1500 or whatever is in OF */ 3146 ndev->min_mtu = EMAC_MIN_MTU; 3147 ndev->max_mtu = dev->max_mtu; 3148 3149 netif_carrier_off(ndev); 3150 3151 err = register_netdev(ndev); 3152 if (err) { 3153 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n", 3154 np, err); 3155 goto err_detach_tah; 3156 } 3157 3158 /* Set our drvdata last as we don't want them visible until we are 3159 * fully initialized 3160 */ 3161 wmb(); 3162 platform_set_drvdata(ofdev, dev); 3163 3164 /* There's a new kid in town ! Let's tell everybody */ 3165 wake_up_all(&emac_probe_wait); 3166 3167 3168 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n", 3169 ndev->name, dev->cell_index, np, ndev->dev_addr); 3170 3171 if (dev->phy_mode == PHY_MODE_SGMII) 3172 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name); 3173 3174 if (dev->phy.address >= 0) 3175 printk("%s: found %s PHY (0x%02x)\n", ndev->name, 3176 dev->phy.def->name, dev->phy.address); 3177 3178 /* Life is good */ 3179 return 0; 3180 3181 /* I have a bad feeling about this ... */ 3182 3183 err_detach_tah: 3184 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3185 tah_detach(dev->tah_dev, dev->tah_port); 3186 err_detach_rgmii: 3187 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3188 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3189 err_detach_zmii: 3190 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3191 zmii_detach(dev->zmii_dev, dev->zmii_port); 3192 err_unreg_commac: 3193 mal_unregister_commac(dev->mal, &dev->commac); 3194 err_rel_deps: 3195 emac_put_deps(dev); 3196 err_reg_unmap: 3197 iounmap(dev->emacp); 3198 err_irq_unmap: 3199 if (dev->wol_irq) 3200 irq_dispose_mapping(dev->wol_irq); 3201 if (dev->emac_irq) 3202 irq_dispose_mapping(dev->emac_irq); 3203 err_free: 3204 free_netdev(ndev); 3205 err_gone: 3206 /* if we were on the bootlist, remove us as we won't show up and 3207 * wake up all waiters to notify them in case they were waiting 3208 * on us 3209 */ 3210 if (blist) { 3211 *blist = NULL; 3212 wake_up_all(&emac_probe_wait); 3213 } 3214 return err; 3215 } 3216 3217 static int emac_remove(struct platform_device *ofdev) 3218 { 3219 struct emac_instance *dev = platform_get_drvdata(ofdev); 3220 3221 DBG(dev, "remove" NL); 3222 3223 unregister_netdev(dev->ndev); 3224 3225 cancel_work_sync(&dev->reset_work); 3226 3227 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) 3228 tah_detach(dev->tah_dev, dev->tah_port); 3229 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) 3230 rgmii_detach(dev->rgmii_dev, dev->rgmii_port); 3231 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) 3232 zmii_detach(dev->zmii_dev, dev->zmii_port); 3233 3234 if (dev->phy_dev) 3235 phy_disconnect(dev->phy_dev); 3236 3237 if (dev->mii_bus) 3238 mdiobus_unregister(dev->mii_bus); 3239 3240 busy_phy_map &= ~(1 << dev->phy.address); 3241 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map); 3242 3243 mal_unregister_commac(dev->mal, &dev->commac); 3244 emac_put_deps(dev); 3245 3246 iounmap(dev->emacp); 3247 3248 if (dev->wol_irq) 3249 irq_dispose_mapping(dev->wol_irq); 3250 if (dev->emac_irq) 3251 irq_dispose_mapping(dev->emac_irq); 3252 3253 free_netdev(dev->ndev); 3254 3255 return 0; 3256 } 3257 3258 /* XXX Features in here should be replaced by properties... */ 3259 static const struct of_device_id emac_match[] = 3260 { 3261 { 3262 .type = "network", 3263 .compatible = "ibm,emac", 3264 }, 3265 { 3266 .type = "network", 3267 .compatible = "ibm,emac4", 3268 }, 3269 { 3270 .type = "network", 3271 .compatible = "ibm,emac4sync", 3272 }, 3273 {}, 3274 }; 3275 MODULE_DEVICE_TABLE(of, emac_match); 3276 3277 static struct platform_driver emac_driver = { 3278 .driver = { 3279 .name = "emac", 3280 .of_match_table = emac_match, 3281 }, 3282 .probe = emac_probe, 3283 .remove = emac_remove, 3284 }; 3285 3286 static void __init emac_make_bootlist(void) 3287 { 3288 struct device_node *np = NULL; 3289 int j, max, i = 0; 3290 int cell_indices[EMAC_BOOT_LIST_SIZE]; 3291 3292 /* Collect EMACs */ 3293 while((np = of_find_all_nodes(np)) != NULL) { 3294 const u32 *idx; 3295 3296 if (of_match_node(emac_match, np) == NULL) 3297 continue; 3298 if (of_get_property(np, "unused", NULL)) 3299 continue; 3300 idx = of_get_property(np, "cell-index", NULL); 3301 if (idx == NULL) 3302 continue; 3303 cell_indices[i] = *idx; 3304 emac_boot_list[i++] = of_node_get(np); 3305 if (i >= EMAC_BOOT_LIST_SIZE) { 3306 of_node_put(np); 3307 break; 3308 } 3309 } 3310 max = i; 3311 3312 /* Bubble sort them (doh, what a creative algorithm :-) */ 3313 for (i = 0; max > 1 && (i < (max - 1)); i++) 3314 for (j = i; j < max; j++) { 3315 if (cell_indices[i] > cell_indices[j]) { 3316 swap(emac_boot_list[i], emac_boot_list[j]); 3317 swap(cell_indices[i], cell_indices[j]); 3318 } 3319 } 3320 } 3321 3322 static int __init emac_init(void) 3323 { 3324 int rc; 3325 3326 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n"); 3327 3328 /* Build EMAC boot list */ 3329 emac_make_bootlist(); 3330 3331 /* Init submodules */ 3332 rc = mal_init(); 3333 if (rc) 3334 goto err; 3335 rc = zmii_init(); 3336 if (rc) 3337 goto err_mal; 3338 rc = rgmii_init(); 3339 if (rc) 3340 goto err_zmii; 3341 rc = tah_init(); 3342 if (rc) 3343 goto err_rgmii; 3344 rc = platform_driver_register(&emac_driver); 3345 if (rc) 3346 goto err_tah; 3347 3348 return 0; 3349 3350 err_tah: 3351 tah_exit(); 3352 err_rgmii: 3353 rgmii_exit(); 3354 err_zmii: 3355 zmii_exit(); 3356 err_mal: 3357 mal_exit(); 3358 err: 3359 return rc; 3360 } 3361 3362 static void __exit emac_exit(void) 3363 { 3364 int i; 3365 3366 platform_driver_unregister(&emac_driver); 3367 3368 tah_exit(); 3369 rgmii_exit(); 3370 zmii_exit(); 3371 mal_exit(); 3372 3373 /* Destroy EMAC boot list */ 3374 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++) 3375 of_node_put(emac_boot_list[i]); 3376 } 3377 3378 module_init(emac_init); 3379 module_exit(emac_exit); 3380