1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Huawei HiNIC PCI Express Linux driver
4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
5  */
6 
7 #include <linux/kernel.h>
8 #include <linux/netdevice.h>
9 #include <linux/u64_stats_sync.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/skbuff.h>
18 #include <linux/smp.h>
19 #include <asm/byteorder.h>
20 #include <linux/ip.h>
21 #include <linux/tcp.h>
22 #include <linux/sctp.h>
23 #include <linux/ipv6.h>
24 #include <net/ipv6.h>
25 #include <net/checksum.h>
26 #include <net/ip6_checksum.h>
27 
28 #include "hinic_common.h"
29 #include "hinic_hw_if.h"
30 #include "hinic_hw_wqe.h"
31 #include "hinic_hw_wq.h"
32 #include "hinic_hw_qp.h"
33 #include "hinic_hw_dev.h"
34 #include "hinic_dev.h"
35 #include "hinic_tx.h"
36 
37 #define TX_IRQ_NO_PENDING               0
38 #define TX_IRQ_NO_COALESC               0
39 #define TX_IRQ_NO_LLI_TIMER             0
40 #define TX_IRQ_NO_CREDIT                0
41 #define TX_IRQ_NO_RESEND_TIMER          0
42 
43 #define CI_UPDATE_NO_PENDING            0
44 #define CI_UPDATE_NO_COALESC            0
45 
46 #define HW_CONS_IDX(sq)                 be16_to_cpu(*(u16 *)((sq)->hw_ci_addr))
47 
48 #define MIN_SKB_LEN			32
49 
50 #define	MAX_PAYLOAD_OFFSET	        221
51 #define TRANSPORT_OFFSET(l4_hdr, skb)	((u32)((l4_hdr) - (skb)->data))
52 
53 union hinic_l3 {
54 	struct iphdr *v4;
55 	struct ipv6hdr *v6;
56 	unsigned char *hdr;
57 };
58 
59 union hinic_l4 {
60 	struct tcphdr *tcp;
61 	struct udphdr *udp;
62 	unsigned char *hdr;
63 };
64 
65 enum hinic_offload_type {
66 	TX_OFFLOAD_TSO     = BIT(0),
67 	TX_OFFLOAD_CSUM    = BIT(1),
68 	TX_OFFLOAD_VLAN    = BIT(2),
69 	TX_OFFLOAD_INVALID = BIT(3),
70 };
71 
72 /**
73  * hinic_txq_clean_stats - Clean the statistics of specific queue
74  * @txq: Logical Tx Queue
75  **/
76 void hinic_txq_clean_stats(struct hinic_txq *txq)
77 {
78 	struct hinic_txq_stats *txq_stats = &txq->txq_stats;
79 
80 	u64_stats_update_begin(&txq_stats->syncp);
81 	txq_stats->pkts    = 0;
82 	txq_stats->bytes   = 0;
83 	txq_stats->tx_busy = 0;
84 	txq_stats->tx_wake = 0;
85 	txq_stats->tx_dropped = 0;
86 	txq_stats->big_frags_pkts = 0;
87 	u64_stats_update_end(&txq_stats->syncp);
88 }
89 
90 /**
91  * hinic_txq_get_stats - get statistics of Tx Queue
92  * @txq: Logical Tx Queue
93  * @stats: return updated stats here
94  **/
95 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
96 {
97 	struct hinic_txq_stats *txq_stats = &txq->txq_stats;
98 	unsigned int start;
99 
100 	u64_stats_update_begin(&stats->syncp);
101 	do {
102 		start = u64_stats_fetch_begin(&txq_stats->syncp);
103 		stats->pkts    = txq_stats->pkts;
104 		stats->bytes   = txq_stats->bytes;
105 		stats->tx_busy = txq_stats->tx_busy;
106 		stats->tx_wake = txq_stats->tx_wake;
107 		stats->tx_dropped = txq_stats->tx_dropped;
108 		stats->big_frags_pkts = txq_stats->big_frags_pkts;
109 	} while (u64_stats_fetch_retry(&txq_stats->syncp, start));
110 	u64_stats_update_end(&stats->syncp);
111 }
112 
113 /**
114  * txq_stats_init - Initialize the statistics of specific queue
115  * @txq: Logical Tx Queue
116  **/
117 static void txq_stats_init(struct hinic_txq *txq)
118 {
119 	struct hinic_txq_stats *txq_stats = &txq->txq_stats;
120 
121 	u64_stats_init(&txq_stats->syncp);
122 	hinic_txq_clean_stats(txq);
123 }
124 
125 /**
126  * tx_map_skb - dma mapping for skb and return sges
127  * @nic_dev: nic device
128  * @skb: the skb
129  * @sges: returned sges
130  *
131  * Return 0 - Success, negative - Failure
132  **/
133 static int tx_map_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
134 		      struct hinic_sge *sges)
135 {
136 	struct hinic_hwdev *hwdev = nic_dev->hwdev;
137 	struct hinic_hwif *hwif = hwdev->hwif;
138 	struct pci_dev *pdev = hwif->pdev;
139 	skb_frag_t *frag;
140 	dma_addr_t dma_addr;
141 	int i, j;
142 
143 	dma_addr = dma_map_single(&pdev->dev, skb->data, skb_headlen(skb),
144 				  DMA_TO_DEVICE);
145 	if (dma_mapping_error(&pdev->dev, dma_addr)) {
146 		dev_err(&pdev->dev, "Failed to map Tx skb data\n");
147 		return -EFAULT;
148 	}
149 
150 	hinic_set_sge(&sges[0], dma_addr, skb_headlen(skb));
151 
152 	for (i = 0 ; i < skb_shinfo(skb)->nr_frags; i++) {
153 		frag = &skb_shinfo(skb)->frags[i];
154 
155 		dma_addr = skb_frag_dma_map(&pdev->dev, frag, 0,
156 					    skb_frag_size(frag),
157 					    DMA_TO_DEVICE);
158 		if (dma_mapping_error(&pdev->dev, dma_addr)) {
159 			dev_err(&pdev->dev, "Failed to map Tx skb frag\n");
160 			goto err_tx_map;
161 		}
162 
163 		hinic_set_sge(&sges[i + 1], dma_addr, skb_frag_size(frag));
164 	}
165 
166 	return 0;
167 
168 err_tx_map:
169 	for (j = 0; j < i; j++)
170 		dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[j + 1]),
171 			       sges[j + 1].len, DMA_TO_DEVICE);
172 
173 	dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
174 			 DMA_TO_DEVICE);
175 	return -EFAULT;
176 }
177 
178 /**
179  * tx_unmap_skb - unmap the dma address of the skb
180  * @nic_dev: nic device
181  * @skb: the skb
182  * @sges: the sges that are connected to the skb
183  **/
184 static void tx_unmap_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
185 			 struct hinic_sge *sges)
186 {
187 	struct hinic_hwdev *hwdev = nic_dev->hwdev;
188 	struct hinic_hwif *hwif = hwdev->hwif;
189 	struct pci_dev *pdev = hwif->pdev;
190 	int i;
191 
192 	for (i = 0; i < skb_shinfo(skb)->nr_frags ; i++)
193 		dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[i + 1]),
194 			       sges[i + 1].len, DMA_TO_DEVICE);
195 
196 	dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
197 			 DMA_TO_DEVICE);
198 }
199 
200 static void get_inner_l3_l4_type(struct sk_buff *skb, union hinic_l3 *ip,
201 				 union hinic_l4 *l4,
202 				 enum hinic_offload_type offload_type,
203 				 enum hinic_l3_offload_type *l3_type,
204 				 u8 *l4_proto)
205 {
206 	u8 *exthdr;
207 
208 	if (ip->v4->version == 4) {
209 		*l3_type = (offload_type == TX_OFFLOAD_CSUM) ?
210 			   IPV4_PKT_NO_CHKSUM_OFFLOAD :
211 			   IPV4_PKT_WITH_CHKSUM_OFFLOAD;
212 		*l4_proto = ip->v4->protocol;
213 	} else if (ip->v4->version == 6) {
214 		*l3_type = IPV6_PKT;
215 		exthdr = ip->hdr + sizeof(*ip->v6);
216 		*l4_proto = ip->v6->nexthdr;
217 		if (exthdr != l4->hdr) {
218 			int start = exthdr - skb->data;
219 			__be16 frag_off;
220 
221 			ipv6_skip_exthdr(skb, start, l4_proto, &frag_off);
222 		}
223 	} else {
224 		*l3_type = L3TYPE_UNKNOWN;
225 		*l4_proto = 0;
226 	}
227 }
228 
229 static void get_inner_l4_info(struct sk_buff *skb, union hinic_l4 *l4,
230 			      enum hinic_offload_type offload_type, u8 l4_proto,
231 			      enum hinic_l4_offload_type *l4_offload,
232 			      u32 *l4_len, u32 *offset)
233 {
234 	*l4_offload = OFFLOAD_DISABLE;
235 	*offset = 0;
236 	*l4_len = 0;
237 
238 	switch (l4_proto) {
239 	case IPPROTO_TCP:
240 		*l4_offload = TCP_OFFLOAD_ENABLE;
241 		/* doff in unit of 4B */
242 		*l4_len = l4->tcp->doff * 4;
243 		*offset = *l4_len + TRANSPORT_OFFSET(l4->hdr, skb);
244 		break;
245 
246 	case IPPROTO_UDP:
247 		*l4_offload = UDP_OFFLOAD_ENABLE;
248 		*l4_len = sizeof(struct udphdr);
249 		*offset = TRANSPORT_OFFSET(l4->hdr, skb);
250 		break;
251 
252 	case IPPROTO_SCTP:
253 		/* only csum offload support sctp */
254 		if (offload_type != TX_OFFLOAD_CSUM)
255 			break;
256 
257 		*l4_offload = SCTP_OFFLOAD_ENABLE;
258 		*l4_len = sizeof(struct sctphdr);
259 		*offset = TRANSPORT_OFFSET(l4->hdr, skb);
260 		break;
261 
262 	default:
263 		break;
264 	}
265 }
266 
267 static __sum16 csum_magic(union hinic_l3 *ip, unsigned short proto)
268 {
269 	return (ip->v4->version == 4) ?
270 		csum_tcpudp_magic(ip->v4->saddr, ip->v4->daddr, 0, proto, 0) :
271 		csum_ipv6_magic(&ip->v6->saddr, &ip->v6->daddr, 0, proto, 0);
272 }
273 
274 static int offload_tso(struct hinic_sq_task *task, u32 *queue_info,
275 		       struct sk_buff *skb)
276 {
277 	u32 offset, l4_len, ip_identify, network_hdr_len;
278 	enum hinic_l3_offload_type l3_offload;
279 	enum hinic_l4_offload_type l4_offload;
280 	union hinic_l3 ip;
281 	union hinic_l4 l4;
282 	u8 l4_proto;
283 
284 	if (!skb_is_gso(skb))
285 		return 0;
286 
287 	if (skb_cow_head(skb, 0) < 0)
288 		return -EPROTONOSUPPORT;
289 
290 	if (skb->encapsulation) {
291 		u32 gso_type = skb_shinfo(skb)->gso_type;
292 		u32 tunnel_type = 0;
293 		u32 l4_tunnel_len;
294 
295 		ip.hdr = skb_network_header(skb);
296 		l4.hdr = skb_transport_header(skb);
297 		network_hdr_len = skb_inner_network_header_len(skb);
298 
299 		if (ip.v4->version == 4) {
300 			ip.v4->tot_len = 0;
301 			l3_offload = IPV4_PKT_WITH_CHKSUM_OFFLOAD;
302 		} else if (ip.v4->version == 6) {
303 			l3_offload = IPV6_PKT;
304 		} else {
305 			l3_offload = 0;
306 		}
307 
308 		hinic_task_set_outter_l3(task, l3_offload,
309 					 skb_network_header_len(skb));
310 
311 		if (gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
312 			l4.udp->check = ~csum_magic(&ip, IPPROTO_UDP);
313 			tunnel_type = TUNNEL_UDP_CSUM;
314 		} else if (gso_type & SKB_GSO_UDP_TUNNEL) {
315 			tunnel_type = TUNNEL_UDP_NO_CSUM;
316 		}
317 
318 		l4_tunnel_len = skb_inner_network_offset(skb) -
319 				skb_transport_offset(skb);
320 		hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
321 
322 		ip.hdr = skb_inner_network_header(skb);
323 		l4.hdr = skb_inner_transport_header(skb);
324 	} else {
325 		ip.hdr = skb_network_header(skb);
326 		l4.hdr = skb_transport_header(skb);
327 		network_hdr_len = skb_network_header_len(skb);
328 	}
329 
330 	/* initialize inner IP header fields */
331 	if (ip.v4->version == 4)
332 		ip.v4->tot_len = 0;
333 	else
334 		ip.v6->payload_len = 0;
335 
336 	get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_TSO, &l3_offload,
337 			     &l4_proto);
338 
339 	hinic_task_set_inner_l3(task, l3_offload, network_hdr_len);
340 
341 	ip_identify = 0;
342 	if (l4_proto == IPPROTO_TCP)
343 		l4.tcp->check = ~csum_magic(&ip, IPPROTO_TCP);
344 
345 	get_inner_l4_info(skb, &l4, TX_OFFLOAD_TSO, l4_proto, &l4_offload,
346 			  &l4_len, &offset);
347 
348 	hinic_set_tso_inner_l4(task, queue_info, l4_offload, l4_len, offset,
349 			       ip_identify, skb_shinfo(skb)->gso_size);
350 
351 	return 1;
352 }
353 
354 static int offload_csum(struct hinic_sq_task *task, u32 *queue_info,
355 			struct sk_buff *skb)
356 {
357 	enum hinic_l4_offload_type l4_offload;
358 	u32 offset, l4_len, network_hdr_len;
359 	enum hinic_l3_offload_type l3_type;
360 	u32 tunnel_type = NOT_TUNNEL;
361 	union hinic_l3 ip;
362 	union hinic_l4 l4;
363 	u8 l4_proto;
364 
365 	if (skb->ip_summed != CHECKSUM_PARTIAL)
366 		return 0;
367 
368 	if (skb->encapsulation) {
369 		u32 l4_tunnel_len;
370 
371 		tunnel_type = TUNNEL_UDP_NO_CSUM;
372 		ip.hdr = skb_network_header(skb);
373 
374 		if (ip.v4->version == 4) {
375 			l3_type = IPV4_PKT_NO_CHKSUM_OFFLOAD;
376 			l4_proto = ip.v4->protocol;
377 		} else if (ip.v4->version == 6) {
378 			unsigned char *exthdr;
379 			__be16 frag_off;
380 
381 			l3_type = IPV6_PKT;
382 			tunnel_type = TUNNEL_UDP_CSUM;
383 			exthdr = ip.hdr + sizeof(*ip.v6);
384 			l4_proto = ip.v6->nexthdr;
385 			l4.hdr = skb_transport_header(skb);
386 			if (l4.hdr != exthdr)
387 				ipv6_skip_exthdr(skb, exthdr - skb->data,
388 						 &l4_proto, &frag_off);
389 		} else {
390 			l3_type = L3TYPE_UNKNOWN;
391 			l4_proto = IPPROTO_RAW;
392 		}
393 
394 		hinic_task_set_outter_l3(task, l3_type,
395 					 skb_network_header_len(skb));
396 
397 		switch (l4_proto) {
398 		case IPPROTO_UDP:
399 			l4_tunnel_len = skb_inner_network_offset(skb) -
400 					skb_transport_offset(skb);
401 			ip.hdr = skb_inner_network_header(skb);
402 			l4.hdr = skb_inner_transport_header(skb);
403 			network_hdr_len = skb_inner_network_header_len(skb);
404 			break;
405 		case IPPROTO_IPIP:
406 		case IPPROTO_IPV6:
407 			tunnel_type = NOT_TUNNEL;
408 			l4_tunnel_len = 0;
409 
410 			ip.hdr = skb_inner_network_header(skb);
411 			l4.hdr = skb_transport_header(skb);
412 			network_hdr_len = skb_network_header_len(skb);
413 			break;
414 		default:
415 			/* Unsupported tunnel packet, disable csum offload */
416 			skb_checksum_help(skb);
417 			return 0;
418 		}
419 
420 		hinic_task_set_tunnel_l4(task, tunnel_type, l4_tunnel_len);
421 	} else {
422 		ip.hdr = skb_network_header(skb);
423 		l4.hdr = skb_transport_header(skb);
424 		network_hdr_len = skb_network_header_len(skb);
425 	}
426 
427 	get_inner_l3_l4_type(skb, &ip, &l4, TX_OFFLOAD_CSUM, &l3_type,
428 			     &l4_proto);
429 
430 	hinic_task_set_inner_l3(task, l3_type, network_hdr_len);
431 
432 	get_inner_l4_info(skb, &l4, TX_OFFLOAD_CSUM, l4_proto, &l4_offload,
433 			  &l4_len, &offset);
434 
435 	hinic_set_cs_inner_l4(task, queue_info, l4_offload, l4_len, offset);
436 
437 	return 1;
438 }
439 
440 static void offload_vlan(struct hinic_sq_task *task, u32 *queue_info,
441 			 u16 vlan_tag, u16 vlan_pri)
442 {
443 	task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) |
444 				HINIC_SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD);
445 
446 	*queue_info |= HINIC_SQ_CTRL_SET(vlan_pri, QUEUE_INFO_PRI);
447 }
448 
449 static int hinic_tx_offload(struct sk_buff *skb, struct hinic_sq_task *task,
450 			    u32 *queue_info)
451 {
452 	enum hinic_offload_type offload = 0;
453 	u16 vlan_tag;
454 	int enabled;
455 
456 	enabled = offload_tso(task, queue_info, skb);
457 	if (enabled > 0) {
458 		offload |= TX_OFFLOAD_TSO;
459 	} else if (enabled == 0) {
460 		enabled = offload_csum(task, queue_info, skb);
461 		if (enabled)
462 			offload |= TX_OFFLOAD_CSUM;
463 	} else {
464 		return -EPROTONOSUPPORT;
465 	}
466 
467 	if (unlikely(skb_vlan_tag_present(skb))) {
468 		vlan_tag = skb_vlan_tag_get(skb);
469 		offload_vlan(task, queue_info, vlan_tag,
470 			     vlan_tag >> VLAN_PRIO_SHIFT);
471 		offload |= TX_OFFLOAD_VLAN;
472 	}
473 
474 	if (offload)
475 		hinic_task_set_l2hdr(task, skb_network_offset(skb));
476 
477 	/* payload offset should not more than 221 */
478 	if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_PLDOFF) >
479 	    MAX_PAYLOAD_OFFSET) {
480 		return -EPROTONOSUPPORT;
481 	}
482 
483 	/* mss should not less than 80 */
484 	if (HINIC_SQ_CTRL_GET(*queue_info, QUEUE_INFO_MSS) < HINIC_MSS_MIN) {
485 		*queue_info = HINIC_SQ_CTRL_CLEAR(*queue_info, QUEUE_INFO_MSS);
486 		*queue_info |= HINIC_SQ_CTRL_SET(HINIC_MSS_MIN, QUEUE_INFO_MSS);
487 	}
488 
489 	return 0;
490 }
491 
492 netdev_tx_t hinic_lb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
493 {
494 	struct hinic_dev *nic_dev = netdev_priv(netdev);
495 	u16 prod_idx, q_id = skb->queue_mapping;
496 	struct netdev_queue *netdev_txq;
497 	int nr_sges, err = NETDEV_TX_OK;
498 	struct hinic_sq_wqe *sq_wqe;
499 	unsigned int wqe_size;
500 	struct hinic_txq *txq;
501 	struct hinic_qp *qp;
502 
503 	txq = &nic_dev->txqs[q_id];
504 	qp = container_of(txq->sq, struct hinic_qp, sq);
505 	nr_sges = skb_shinfo(skb)->nr_frags + 1;
506 
507 	err = tx_map_skb(nic_dev, skb, txq->sges);
508 	if (err)
509 		goto skb_error;
510 
511 	wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
512 
513 	sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
514 	if (!sq_wqe) {
515 		netif_stop_subqueue(netdev, qp->q_id);
516 
517 		sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
518 		if (sq_wqe) {
519 			netif_wake_subqueue(nic_dev->netdev, qp->q_id);
520 			goto process_sq_wqe;
521 		}
522 
523 		tx_unmap_skb(nic_dev, skb, txq->sges);
524 
525 		u64_stats_update_begin(&txq->txq_stats.syncp);
526 		txq->txq_stats.tx_busy++;
527 		u64_stats_update_end(&txq->txq_stats.syncp);
528 		err = NETDEV_TX_BUSY;
529 		wqe_size = 0;
530 		goto flush_skbs;
531 	}
532 
533 process_sq_wqe:
534 	hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
535 	hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
536 
537 flush_skbs:
538 	netdev_txq = netdev_get_tx_queue(netdev, q_id);
539 	if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
540 		hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
541 
542 	return err;
543 
544 skb_error:
545 	dev_kfree_skb_any(skb);
546 	u64_stats_update_begin(&txq->txq_stats.syncp);
547 	txq->txq_stats.tx_dropped++;
548 	u64_stats_update_end(&txq->txq_stats.syncp);
549 
550 	return NETDEV_TX_OK;
551 }
552 
553 netdev_tx_t hinic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
554 {
555 	struct hinic_dev *nic_dev = netdev_priv(netdev);
556 	u16 prod_idx, q_id = skb->queue_mapping;
557 	struct netdev_queue *netdev_txq;
558 	int nr_sges, err = NETDEV_TX_OK;
559 	struct hinic_sq_wqe *sq_wqe;
560 	unsigned int wqe_size;
561 	struct hinic_txq *txq;
562 	struct hinic_qp *qp;
563 
564 	txq = &nic_dev->txqs[q_id];
565 	qp = container_of(txq->sq, struct hinic_qp, sq);
566 
567 	if (skb->len < MIN_SKB_LEN) {
568 		if (skb_pad(skb, MIN_SKB_LEN - skb->len)) {
569 			netdev_err(netdev, "Failed to pad skb\n");
570 			goto update_error_stats;
571 		}
572 
573 		skb->len = MIN_SKB_LEN;
574 	}
575 
576 	nr_sges = skb_shinfo(skb)->nr_frags + 1;
577 	if (nr_sges > 17) {
578 		u64_stats_update_begin(&txq->txq_stats.syncp);
579 		txq->txq_stats.big_frags_pkts++;
580 		u64_stats_update_end(&txq->txq_stats.syncp);
581 	}
582 
583 	if (nr_sges > txq->max_sges) {
584 		netdev_err(netdev, "Too many Tx sges\n");
585 		goto skb_error;
586 	}
587 
588 	err = tx_map_skb(nic_dev, skb, txq->sges);
589 	if (err)
590 		goto skb_error;
591 
592 	wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
593 
594 	sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
595 	if (!sq_wqe) {
596 		netif_stop_subqueue(netdev, qp->q_id);
597 
598 		/* Check for the case free_tx_poll is called in another cpu
599 		 * and we stopped the subqueue after free_tx_poll check.
600 		 */
601 		sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
602 		if (sq_wqe) {
603 			netif_wake_subqueue(nic_dev->netdev, qp->q_id);
604 			goto process_sq_wqe;
605 		}
606 
607 		tx_unmap_skb(nic_dev, skb, txq->sges);
608 
609 		u64_stats_update_begin(&txq->txq_stats.syncp);
610 		txq->txq_stats.tx_busy++;
611 		u64_stats_update_end(&txq->txq_stats.syncp);
612 		err = NETDEV_TX_BUSY;
613 		wqe_size = 0;
614 		goto flush_skbs;
615 	}
616 
617 process_sq_wqe:
618 	hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
619 
620 	err = hinic_tx_offload(skb, &sq_wqe->task, &sq_wqe->ctrl.queue_info);
621 	if (err)
622 		goto offload_error;
623 
624 	hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
625 
626 flush_skbs:
627 	netdev_txq = netdev_get_tx_queue(netdev, q_id);
628 	if ((!netdev_xmit_more()) || (netif_xmit_stopped(netdev_txq)))
629 		hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
630 
631 	return err;
632 
633 offload_error:
634 	hinic_sq_return_wqe(txq->sq, wqe_size);
635 	tx_unmap_skb(nic_dev, skb, txq->sges);
636 
637 skb_error:
638 	dev_kfree_skb_any(skb);
639 
640 update_error_stats:
641 	u64_stats_update_begin(&txq->txq_stats.syncp);
642 	txq->txq_stats.tx_dropped++;
643 	u64_stats_update_end(&txq->txq_stats.syncp);
644 
645 	return NETDEV_TX_OK;
646 }
647 
648 /**
649  * tx_free_skb - unmap and free skb
650  * @nic_dev: nic device
651  * @skb: the skb
652  * @sges: the sges that are connected to the skb
653  **/
654 static void tx_free_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
655 			struct hinic_sge *sges)
656 {
657 	tx_unmap_skb(nic_dev, skb, sges);
658 
659 	dev_kfree_skb_any(skb);
660 }
661 
662 /**
663  * free_all_rx_skbs - free all skbs in tx queue
664  * @txq: tx queue
665  **/
666 static void free_all_tx_skbs(struct hinic_txq *txq)
667 {
668 	struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
669 	struct hinic_sq *sq = txq->sq;
670 	struct hinic_sq_wqe *sq_wqe;
671 	unsigned int wqe_size;
672 	struct sk_buff *skb;
673 	int nr_sges;
674 	u16 ci;
675 
676 	while ((sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &ci))) {
677 		sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &ci);
678 		if (!sq_wqe)
679 			break;
680 
681 		nr_sges = skb_shinfo(skb)->nr_frags + 1;
682 
683 		hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
684 
685 		hinic_sq_put_wqe(sq, wqe_size);
686 
687 		tx_free_skb(nic_dev, skb, txq->free_sges);
688 	}
689 }
690 
691 /**
692  * free_tx_poll - free finished tx skbs in tx queue that connected to napi
693  * @napi: napi
694  * @budget: number of tx
695  *
696  * Return 0 - Success, negative - Failure
697  **/
698 static int free_tx_poll(struct napi_struct *napi, int budget)
699 {
700 	struct hinic_txq *txq = container_of(napi, struct hinic_txq, napi);
701 	struct hinic_qp *qp = container_of(txq->sq, struct hinic_qp, sq);
702 	struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
703 	struct netdev_queue *netdev_txq;
704 	struct hinic_sq *sq = txq->sq;
705 	struct hinic_wq *wq = sq->wq;
706 	struct hinic_sq_wqe *sq_wqe;
707 	unsigned int wqe_size;
708 	int nr_sges, pkts = 0;
709 	struct sk_buff *skb;
710 	u64 tx_bytes = 0;
711 	u16 hw_ci, sw_ci;
712 
713 	do {
714 		hw_ci = HW_CONS_IDX(sq) & wq->mask;
715 
716 		dma_rmb();
717 
718 		/* Reading a WQEBB to get real WQE size and consumer index. */
719 		sq_wqe = hinic_sq_read_wqebb(sq, &skb, &wqe_size, &sw_ci);
720 		if ((!sq_wqe) ||
721 		    (((hw_ci - sw_ci) & wq->mask) * wq->wqebb_size < wqe_size))
722 			break;
723 
724 		/* If this WQE have multiple WQEBBs, we will read again to get
725 		 * full size WQE.
726 		 */
727 		if (wqe_size > wq->wqebb_size) {
728 			sq_wqe = hinic_sq_read_wqe(sq, &skb, wqe_size, &sw_ci);
729 			if (unlikely(!sq_wqe))
730 				break;
731 		}
732 
733 		tx_bytes += skb->len;
734 		pkts++;
735 
736 		nr_sges = skb_shinfo(skb)->nr_frags + 1;
737 
738 		hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
739 
740 		hinic_sq_put_wqe(sq, wqe_size);
741 
742 		tx_free_skb(nic_dev, skb, txq->free_sges);
743 	} while (pkts < budget);
744 
745 	if (__netif_subqueue_stopped(nic_dev->netdev, qp->q_id) &&
746 	    hinic_get_sq_free_wqebbs(sq) >= HINIC_MIN_TX_NUM_WQEBBS(sq)) {
747 		netdev_txq = netdev_get_tx_queue(txq->netdev, qp->q_id);
748 
749 		__netif_tx_lock(netdev_txq, smp_processor_id());
750 		if (!netif_testing(nic_dev->netdev))
751 			netif_wake_subqueue(nic_dev->netdev, qp->q_id);
752 
753 		__netif_tx_unlock(netdev_txq);
754 
755 		u64_stats_update_begin(&txq->txq_stats.syncp);
756 		txq->txq_stats.tx_wake++;
757 		u64_stats_update_end(&txq->txq_stats.syncp);
758 	}
759 
760 	u64_stats_update_begin(&txq->txq_stats.syncp);
761 	txq->txq_stats.bytes += tx_bytes;
762 	txq->txq_stats.pkts += pkts;
763 	u64_stats_update_end(&txq->txq_stats.syncp);
764 
765 	if (pkts < budget) {
766 		napi_complete(napi);
767 		if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
768 			hinic_hwdev_set_msix_state(nic_dev->hwdev,
769 						   sq->msix_entry,
770 						   HINIC_MSIX_ENABLE);
771 
772 		return pkts;
773 	}
774 
775 	return budget;
776 }
777 
778 static irqreturn_t tx_irq(int irq, void *data)
779 {
780 	struct hinic_txq *txq = data;
781 	struct hinic_dev *nic_dev;
782 
783 	nic_dev = netdev_priv(txq->netdev);
784 
785 	if (!HINIC_IS_VF(nic_dev->hwdev->hwif))
786 		/* Disable the interrupt until napi will be completed */
787 		hinic_hwdev_set_msix_state(nic_dev->hwdev,
788 					   txq->sq->msix_entry,
789 					   HINIC_MSIX_DISABLE);
790 
791 	hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry);
792 
793 	napi_schedule(&txq->napi);
794 	return IRQ_HANDLED;
795 }
796 
797 static int tx_request_irq(struct hinic_txq *txq)
798 {
799 	struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
800 	struct hinic_msix_config interrupt_info = {0};
801 	struct hinic_intr_coal_info *intr_coal = NULL;
802 	struct hinic_hwdev *hwdev = nic_dev->hwdev;
803 	struct hinic_hwif *hwif = hwdev->hwif;
804 	struct pci_dev *pdev = hwif->pdev;
805 	struct hinic_sq *sq = txq->sq;
806 	struct hinic_qp *qp;
807 	int err;
808 
809 	qp = container_of(sq, struct hinic_qp, sq);
810 
811 	netif_napi_add(txq->netdev, &txq->napi, free_tx_poll, nic_dev->tx_weight);
812 
813 	hinic_hwdev_msix_set(nic_dev->hwdev, sq->msix_entry,
814 			     TX_IRQ_NO_PENDING, TX_IRQ_NO_COALESC,
815 			     TX_IRQ_NO_LLI_TIMER, TX_IRQ_NO_CREDIT,
816 			     TX_IRQ_NO_RESEND_TIMER);
817 
818 	intr_coal = &nic_dev->tx_intr_coalesce[qp->q_id];
819 	interrupt_info.msix_index = sq->msix_entry;
820 	interrupt_info.coalesce_timer_cnt = intr_coal->coalesce_timer_cfg;
821 	interrupt_info.pending_cnt = intr_coal->pending_limt;
822 	interrupt_info.resend_timer_cnt = intr_coal->resend_timer_cfg;
823 
824 	err = hinic_set_interrupt_cfg(hwdev, &interrupt_info);
825 	if (err) {
826 		netif_err(nic_dev, drv, txq->netdev,
827 			  "Failed to set TX interrupt coalescing attribute\n");
828 		netif_napi_del(&txq->napi);
829 		return err;
830 	}
831 
832 	err = request_irq(sq->irq, tx_irq, 0, txq->irq_name, txq);
833 	if (err) {
834 		dev_err(&pdev->dev, "Failed to request Tx irq\n");
835 		netif_napi_del(&txq->napi);
836 		return err;
837 	}
838 
839 	return 0;
840 }
841 
842 static void tx_free_irq(struct hinic_txq *txq)
843 {
844 	struct hinic_sq *sq = txq->sq;
845 
846 	free_irq(sq->irq, txq);
847 	netif_napi_del(&txq->napi);
848 }
849 
850 /**
851  * hinic_init_txq - Initialize the Tx Queue
852  * @txq: Logical Tx Queue
853  * @sq: Hardware Tx Queue to connect the Logical queue with
854  * @netdev: network device to connect the Logical queue with
855  *
856  * Return 0 - Success, negative - Failure
857  **/
858 int hinic_init_txq(struct hinic_txq *txq, struct hinic_sq *sq,
859 		   struct net_device *netdev)
860 {
861 	struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
862 	struct hinic_dev *nic_dev = netdev_priv(netdev);
863 	struct hinic_hwdev *hwdev = nic_dev->hwdev;
864 	int err, irqname_len;
865 	size_t sges_size;
866 
867 	txq->netdev = netdev;
868 	txq->sq = sq;
869 
870 	txq_stats_init(txq);
871 
872 	txq->max_sges = HINIC_MAX_SQ_BUFDESCS;
873 
874 	sges_size = txq->max_sges * sizeof(*txq->sges);
875 	txq->sges = devm_kzalloc(&netdev->dev, sges_size, GFP_KERNEL);
876 	if (!txq->sges)
877 		return -ENOMEM;
878 
879 	sges_size = txq->max_sges * sizeof(*txq->free_sges);
880 	txq->free_sges = devm_kzalloc(&netdev->dev, sges_size, GFP_KERNEL);
881 	if (!txq->free_sges) {
882 		err = -ENOMEM;
883 		goto err_alloc_free_sges;
884 	}
885 
886 	irqname_len = snprintf(NULL, 0, "%s_txq%d", netdev->name, qp->q_id) + 1;
887 	txq->irq_name = devm_kzalloc(&netdev->dev, irqname_len, GFP_KERNEL);
888 	if (!txq->irq_name) {
889 		err = -ENOMEM;
890 		goto err_alloc_irqname;
891 	}
892 
893 	sprintf(txq->irq_name, "%s_txq%d", netdev->name, qp->q_id);
894 
895 	err = hinic_hwdev_hw_ci_addr_set(hwdev, sq, CI_UPDATE_NO_PENDING,
896 					 CI_UPDATE_NO_COALESC);
897 	if (err)
898 		goto err_hw_ci;
899 
900 	err = tx_request_irq(txq);
901 	if (err) {
902 		netdev_err(netdev, "Failed to request Tx irq\n");
903 		goto err_req_tx_irq;
904 	}
905 
906 	return 0;
907 
908 err_req_tx_irq:
909 err_hw_ci:
910 	devm_kfree(&netdev->dev, txq->irq_name);
911 
912 err_alloc_irqname:
913 	devm_kfree(&netdev->dev, txq->free_sges);
914 
915 err_alloc_free_sges:
916 	devm_kfree(&netdev->dev, txq->sges);
917 	return err;
918 }
919 
920 /**
921  * hinic_clean_txq - Clean the Tx Queue
922  * @txq: Logical Tx Queue
923  **/
924 void hinic_clean_txq(struct hinic_txq *txq)
925 {
926 	struct net_device *netdev = txq->netdev;
927 
928 	tx_free_irq(txq);
929 
930 	free_all_tx_skbs(txq);
931 
932 	devm_kfree(&netdev->dev, txq->irq_name);
933 	devm_kfree(&netdev->dev, txq->free_sges);
934 	devm_kfree(&netdev->dev, txq->sges);
935 }
936